15637 lines
1.2 MiB
15637 lines
1.2 MiB
; --------------------------------------------------------------------------------
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; @Title: QN908x On-Chip Peripherals
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; @Props: Released
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; @Author: PID, LST
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; @Changelog: 2019-03-19 PID
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: 20180227UM_UM11023.pdf (Rev 1.1, 2018-02-27)
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; 20180227DS_QN908x.pdf (Rev 1.1, 2018-02-13)
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; @Core: Cortex-M4F
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; @Chip: QN9080DHN, QN9083DUK
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; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perqn908x.per 17736 2024-04-08 09:26:07Z kwisniewski $
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; Known problems:
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; MODULE REGISTER DESCRIPTION
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; USB 2.0 DEVCMDSTAT Misleading/not described access type. "RW1"
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; USB 2.0 INTSTAT Misleading/not described access type "RW1"
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; SYSCON RCO_PWR_MODE Misleading RCO_PWR_MODE description
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
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bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "SYSCON (System Architecture And Configuration)"
|
|
base ad:0x40000000
|
|
width 17.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "RST_SW_SET,Block Software Reset Set Register"
|
|
bitfld.long 0x00 31. " SET_REBOOT ,Write 1 to reboot entire system" "No action,Reset"
|
|
bitfld.long 0x00 30. " SET_REG_RST ,Write 1 to reset retention register" "No action,Reset"
|
|
bitfld.long 0x00 29. " SET_DP_RST ,Write 1 to set datapath reset" "No action,Reset"
|
|
newline
|
|
bitfld.long 0x00 28. " SET_FLASH_RST ,Write 1 to set flash controller reset" "No action,Reset"
|
|
bitfld.long 0x00 27. " SET_BLE_RST ,Write 1 to set BLE reset" "No action,Reset"
|
|
bitfld.long 0x00 26. " SET_CPU_RST ,Write 1 to set CPU reset" "No action,Reset"
|
|
newline
|
|
bitfld.long 0x00 22. " SET_SPIFI_RST ,Write 1 to set SPIFI reset" "No action,Reset"
|
|
bitfld.long 0x00 20. " SET_QDEC1_RST ,Write 1 to set QDEC 1 reset" "No action,Reset"
|
|
bitfld.long 0x00 19. " SET_QDEC0_RST ,Write 1 to set QDEC 0 reset" "No action,Reset"
|
|
newline
|
|
bitfld.long 0x00 17. " SET_DMA_RST ,Write 1 to set DMA reset" "No action,Reset"
|
|
bitfld.long 0x00 16. " SET_FSP_RST ,Write 1 to set FSP reset" "No action,Reset"
|
|
bitfld.long 0x00 15. " SET_CS_RST ,Write 1 to set capacitive sense reset" "No action,Reset"
|
|
newline
|
|
bitfld.long 0x00 14. " SET_DAC_RST ,Write 1 to set DAC reset" "No action,Reset"
|
|
bitfld.long 0x00 13. " SET_ADC_RST ,Write 1 to set ADC reset" "No action,Reset"
|
|
bitfld.long 0x00 12. " SET_RTC_RST ,Write 1 to set RTC reset" "No action,Reset"
|
|
newline
|
|
bitfld.long 0x00 11. " SET_GPIO_RST ,Write 1 to set GPIO reset" "No action,Reset"
|
|
bitfld.long 0x00 10. " SET_USB_RST ,Write 1 to set USB reset" "No action,Reset"
|
|
bitfld.long 0x00 9. " SET_WDT_RST ,Write 1 to set watchdog reset" "No action,Reset"
|
|
newline
|
|
bitfld.long 0x00 8. " SET_SCT_RST ,Write 1 to set SCT reset" "No action,Reset"
|
|
bitfld.long 0x00 7. " SET_TIM3_RST ,Write 1 to set CTIMER3 reset" "No action,Reset"
|
|
bitfld.long 0x00 6. " SET_TIM2_RST ,Write 1 to set CTIMER2 reset" "No action,Reset"
|
|
newline
|
|
bitfld.long 0x00 5. " SET_TIM1_RST ,Write 1 to set CTIMER1 reset" "No action,Reset"
|
|
bitfld.long 0x00 4. " SET_TIM0_RST ,Write 1 to set CTIMER0 reset" "No action,Reset"
|
|
bitfld.long 0x00 3. " SET_FC3_RST ,Write 1 to set FLEXCOMM3 reset" "No action,Reset"
|
|
newline
|
|
bitfld.long 0x00 2. " SET_FC2_RST ,Write 1 to set FLEXCOMM2 reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " SET_FC1_RST ,Write 1 to set FLEXCOMM1 reset" "No action,Reset"
|
|
bitfld.long 0x00 0. " SET_FC0_RST ,Write 1 to set FLEXCOMM0 reset" "No action,Reset"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "RST_SW_CLR,Block Software Reset Clear Register"
|
|
eventfld.long 0x00 30. " CLR_REG_RST ,Write 1 to clear retention register" "No action,Cleared"
|
|
eventfld.long 0x00 29. " CLR_DP_RST ,Write 1 to clear datapath reset" "No action,Cleared"
|
|
eventfld.long 0x00 28. " CLR_FLASH_RST ,Write 1 to clear flash controller reset" "No action,Cleared"
|
|
newline
|
|
eventfld.long 0x00 27. " CLR_BLE_RST ,Write 1 to clear BLE reset" "No action,Cleared"
|
|
eventfld.long 0x00 26. " CLR_CPU_RST ,Write 1 to clear CPU reset" "No action,Cleared"
|
|
eventfld.long 0x00 22. " CLR_SPIFI_RST ,Write 1 to clear SPIFI reset" "No action,Cleared"
|
|
newline
|
|
eventfld.long 0x00 20. " CLR_QDEC1_RST ,Write 1 to clear QDEC 1 reset" "No action,Cleared"
|
|
eventfld.long 0x00 19. " CLR_QDEC0_RST ,Write 1 to clear QDEC 0 reset" "No action,Cleared"
|
|
eventfld.long 0x00 17. " CLR_DMA_RST ,Write 1 to clear DMA reset" "No action,Cleared"
|
|
newline
|
|
eventfld.long 0x00 16. " CLR_FSP_RST ,Write 1 to clear FSP reset" "No action,Cleared"
|
|
eventfld.long 0x00 15. " CLR_CS_RST ,Write 1 to clear capacitive sense reset" "No action,Cleared"
|
|
eventfld.long 0x00 14. " CLR_DAC_RST ,Write 1 to clear DAC reset" "No action,Cleared"
|
|
newline
|
|
eventfld.long 0x00 13. " CLR_ADC_RST ,Write 1 to clear ADC reset" "No action,Cleared"
|
|
eventfld.long 0x00 12. " CLR_RTC_RST ,Write 1 to clear RTC reset" "No action,Cleared"
|
|
eventfld.long 0x00 11. " CLR_GPIO_RST ,Write 1 to clear GPIO reset" "No action,Cleared"
|
|
newline
|
|
eventfld.long 0x00 10. " CLR_USB_RST ,Write 1 to clear USB reset" "No action,Cleared"
|
|
eventfld.long 0x00 9. " CLR_WDT_RST ,Write 1 to clear watchdog reset" "No action,Cleared"
|
|
eventfld.long 0x00 8. " CLR_SCT_RST ,Write 1 to clear SCT reset" "No action,Cleared"
|
|
newline
|
|
eventfld.long 0x00 7. " CLR_TIM3_RST ,Write 1 to clear CTIMER3 reset" "No action,Cleared"
|
|
eventfld.long 0x00 6. " CLR_TIM2_RST ,Write 1 to clear CTIMER2 reset" "No action,Cleared"
|
|
eventfld.long 0x00 5. " CLR_TIM1_RST ,Write 1 to clear CTIMER1 reset" "No action,Cleared"
|
|
newline
|
|
eventfld.long 0x00 4. " CLR_TIM0_RST ,Write 1 to clear CTIMER0 reset" "No action,Cleared"
|
|
eventfld.long 0x00 3. " CLR_FC3_RST ,Write 1 to clear FLEXCOMM3 reset" "No action,Cleared"
|
|
eventfld.long 0x00 2. " CLR_FC2_RST ,Write 1 to clear FLEXCOMM2 reset" "No action,Cleared"
|
|
newline
|
|
eventfld.long 0x00 1. " CLR_FC1_RST ,Write 1 to clear FLEXCOMM1 reset" "No action,Cleared"
|
|
eventfld.long 0x00 0. " CLR_FC0_RST ,Write 1 to clear FLEXCOMM0 reset" "No action,Cleared"
|
|
line.long 0x04 "CLK_DIS,Clock Disable Register"
|
|
eventfld.long 0x04 31. " FCLK_DIS ,Write 1 to disable CPU FCLK" "No effect,Disabled"
|
|
eventfld.long 0x04 30. " PCLK_DIS ,Write 1 to disable PCLK of some logic" "No action,Disabled"
|
|
eventfld.long 0x04 27. " CLK_BLE_DIS ,Write 1 to disable BLE clock" "No action,Disabled"
|
|
newline
|
|
eventfld.long 0x04 25. " CLK_CAL_DIS ,Write 1 to disable calibration clock" "No action,Disabled"
|
|
eventfld.long 0x04 22. " CLK_SPIFI_DIS ,Write 1 to disable SPIFI clock" "No action,Disabled"
|
|
eventfld.long 0x04 21. " CLK_DP_DIS ,Write 1 to disable data 16MHZ or 8MHz clock" "No effect,Disabled"
|
|
newline
|
|
eventfld.long 0x04 20. " CLK_QDEC1_DIS ,Write 1 to disable QDEC1 clock" "No action,Disabled"
|
|
eventfld.long 0x04 19. " CLK_QDEC0_DIS ,Write 1 to disable QDEC0 clock" "No action,Disabled"
|
|
eventfld.long 0x04 17. " CLK_DMA_DIS ,Write 1 to disable DMA clock" "No action,Disabled"
|
|
newline
|
|
eventfld.long 0x04 16. " CLK_FSP_DIS ,Write 1 to disable FSP clock" "No action,Disabled"
|
|
eventfld.long 0x04 15. " CLK_CS_DIS ,Write 1 to disable capacitive sense clock" "No action,Disabled"
|
|
eventfld.long 0x04 14. " CLK_DAC_DIS ,Write 1 to disable DAC clock" "No action,Disabled"
|
|
newline
|
|
eventfld.long 0x04 13. " CLK_ADC_DIS ,Write 1 to disable ADC clock" "No action,Disabled"
|
|
eventfld.long 0x04 12. " CLK_BIV_DIS ,Write 1 to disable BIV APB clock include RTC BIV register" "No action,Disabled"
|
|
eventfld.long 0x04 11. " CLK_GPIO_DIS ,Write 1 to disable GPIO clock" "No action,Disabled"
|
|
newline
|
|
eventfld.long 0x04 10. " CLK_USB_DIS ,Write 1 to disable USB clock" "No action,Disabled"
|
|
eventfld.long 0x04 9. " CLK_WDT_DIS ,Write 1 to disable watchdog clock" "No action,Disabled"
|
|
eventfld.long 0x04 8. " CLK_SCT_DIS ,Write 1 to disable PWM clock" "No action,Disabled"
|
|
newline
|
|
eventfld.long 0x04 7. " CLK_TIM3_DIS ,Write 1 to disable timer 3 clock" "No action,Disabled"
|
|
eventfld.long 0x04 6. " CLK_TIM2_DIS ,Write 1 to disable timer 2 clock" "No action,Disabled"
|
|
eventfld.long 0x04 5. " CLK_TIM1_DIS ,Write 1 to disable timer 1 clock" "No action,Disabled"
|
|
newline
|
|
eventfld.long 0x04 4. " CLK_TIM0_DIS ,Write 1 to disable timer 0 clock" "No action,Disabled"
|
|
eventfld.long 0x04 3. " CLK_FC3_DIS ,Write 1 to disable FLEXCOMM3 clock" "No action,Disabled"
|
|
eventfld.long 0x04 2. " CLK_FC2_DIS ,Write 1 to disable FLEXCOMM2 clock" "No action,Disabled"
|
|
newline
|
|
eventfld.long 0x04 1. " CLK_FC1_DIS ,Write 1 to disable FLEXCOMM1 clock" "No action,Disabled"
|
|
eventfld.long 0x04 0. " CLK_FC0_DIS ,Write 1 to disable FLEXCOMM0 clock" "No action,Disabled"
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "CLK_EN,Clock Enable Register"
|
|
bitfld.long 0x00 27. " CLK_BLE_EN ,Write 1 to enable BLE clock" "No action,Enabled"
|
|
bitfld.long 0x00 25. " CLK_CAL_EN ,Write 1 to enable calibration clock" "No action,Enabled"
|
|
bitfld.long 0x00 22. " CLK_SPIFI_EN ,Write 1 to enable SPIFI clock" "No action,Enabled"
|
|
newline
|
|
bitfld.long 0x00 21. " CLK_DP_EN ,Write 1 to enable data path 16MHz/8MHz" "No action,Enabled"
|
|
bitfld.long 0x00 20. " CLK_QDEC1_EN ,Write 1 to enable QDEC 1 clock" "No action,Enabled"
|
|
bitfld.long 0x00 19. " CLK_QDEC0_EN ,Write 1 to enable QDEC 0 clock" "No action,Enabled"
|
|
newline
|
|
bitfld.long 0x00 17. " CLK_DMA_EN ,Write 1 to enable DMA clock" "No action,Enabled"
|
|
bitfld.long 0x00 16. " CLK_FSP_EN ,Write 1 to enable FSP clock" "No action,Enabled"
|
|
bitfld.long 0x00 15. " CLK_CS_EN ,Write 1 to enable capacitive sense clock" "No action,Enabled"
|
|
newline
|
|
bitfld.long 0x00 14. " CLK_DAC_EN ,Write 1 to enable DAC clock" "No action,Enabled"
|
|
bitfld.long 0x00 13. " CLK_ADC_EN ,Write 1 to enable ADC clock" "No action,Enabled"
|
|
bitfld.long 0x00 12. " CLK_BIV_EN ,Write 1 to enable BIV APB clock include RTC BIV register" "No action,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " CLK_GPIO_EN ,Write 1 to enable GPIO clock" "No action,Enabled"
|
|
bitfld.long 0x00 10. " CLK_USB_EN ,Write 1 to enable USB clock" "No action,Enabled"
|
|
bitfld.long 0x00 9. " CLK_WDT_EN ,Write 1 to enable watchdog clock" "No action,Enabled"
|
|
newline
|
|
bitfld.long 0x00 8. " CLK_SCT_EN ,Write 1 to enable PWM clock" "No action,Enabled"
|
|
bitfld.long 0x00 7. " CLK_TIM3_EN ,Write 1 to enable timer 3 clock" "No action,Enabled"
|
|
bitfld.long 0x00 6. " CLK_TIM2_EN ,Write 1 to enable timer 2 clock" "No action,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " CLK_TIM1_EN ,Write 1 to enable timer 1 clock" "No action,Enabled"
|
|
bitfld.long 0x00 4. " CLK_TIM0_EN ,Write 1 to enable timer 0 clock" "No action,Enabled"
|
|
bitfld.long 0x00 3. " CLK_FC3_EN ,Write 1 to enable FLEXCOMM3 clock" "No action,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " CLK_FC2_EN ,Write 1 to enable FLEXCOMM2 clock" "No action,Enabled"
|
|
bitfld.long 0x00 1. " CLK_FC1_EN ,Write 1 to enable FLEXCOMM1 clock" "No action,Enabled"
|
|
bitfld.long 0x00 0. " CLK_FC0_EN ,Write 1 to enable FLEXCOMM0 clock" "No action,Enabled"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "CLK_CTRL,System Clock Source And Divider Register"
|
|
bitfld.long 0x00 30.--31. " SYS_CLK_SEL ,SYS_CLK source selection" "32MHz internal,16/32MHz external,32kHz,?..."
|
|
bitfld.long 0x00 28. " CGBYPASS ,Active mode CPU power saving" "Enabled,Disabled"
|
|
bitfld.long 0x00 24.--27. " XTAL_OUT_DIV ,High frequency crystal clock output divider" "No divider,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30"
|
|
newline
|
|
bitfld.long 0x00 23. " CLK_32K_OE ,32kHz clock output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CLK_XTAL_OE ,System clock output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " CLK_32K_SEL ,Digital 32kHz clock source selection" "External crystal,Internal RCO"
|
|
newline
|
|
bitfld.long 0x00 20. " CLK_OSC32M_DIV ,Digital OSC clock input selection" "32MHz,16MHz"
|
|
bitfld.long 0x00 19. " CLK_XTAL_SEL ,Crystal clock indicator" "16MHz,32MHz"
|
|
bitfld.long 0x00 18. " CLK_WDT_SEL ,Watchdog clock selection" "32kHz,APB clock"
|
|
newline
|
|
bitfld.long 0x00 17. " CLK_BLE_SEL ,BLE frequency indicator" "8MHz,16MHz"
|
|
hexmask.long.word 0x00 4.--16. 1. " AHB_DIV ,AHB clock divider"
|
|
bitfld.long 0x00 0.--3. " APB_DIV ,APB clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
line.long 0x04 "SYS_MODE_CTRL,System Mode And Address Remap Register"
|
|
rbitfld.long 0x04 31. " BOOT_MODE ,Boot mode pin status" "Enters ISP,Flash without ISP"
|
|
rbitfld.long 0x04 29. " BG_RDY ,BG ready readout" "Not ready,Ready"
|
|
rbitfld.long 0x04 28. " OSC32M_RDY ,32MHz oscillator ready readout" "Not ready,Ready"
|
|
newline
|
|
rbitfld.long 0x04 27. " PLL48M_RDY ,48MHz PLL ready readout" "Not ready,Ready"
|
|
rbitfld.long 0x04 26. " XTAL32K_RDY ,32kHz crystal ready readout" "Not ready,Ready"
|
|
rbitfld.long 0x04 25. " XTAL_RDY ,16/32MHz crystal ready readout" "Not ready,Ready"
|
|
newline
|
|
bitfld.long 0x04 2. " LOCKUP_EN ,Lock up enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--1. " REMAP ,Software remap system address" "ROM,FLASH,RAM,?..."
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "SYS_STAT,System Status Register"
|
|
bitfld.long 0x00 14. " CLK_STATUS ,BLE status" "Active,Sleep mode"
|
|
bitfld.long 0x00 13. " RADIO_EN ,BLE radio_en output" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " OSC_EN ,BLE osc_en output" "Enabled,Disabled"
|
|
newline
|
|
bitfld.long 0x00 11. " TX_EN ,Enables TX state" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RX_EN ,Enables RX state" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EVENT_IN_PROCESS ,BLE event indicator" "Not in event process,In event process"
|
|
newline
|
|
bitfld.long 0x00 8. " BLE_FREQ_HOP ,BLE frequency word change flag" "Not changed,Changed"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FREQ_WORD ,BLE frequency word"
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "SYS_TICK,Systick Timer Control Register"
|
|
bitfld.long 0x00 31. " EN_STCLKEN ,Enables systick" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " NOREF ,Whether an external reference clock is available" "Available,Not available"
|
|
bitfld.long 0x00 24. " SKEW ,whether the TENMS value will generate a precise 10 millisecond time or an approximation" "Precise,Not precise"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,System tick timer calibration value"
|
|
line.long 0x04 "SRAM_CTRL,Exchange Memory Base Address Register"
|
|
hexmask.long.word 0x04 0.--14. 1. " EM_BASE_ADDR ,Exchange memory base address in system memory"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "CHIP_ID,Chip Id Register"
|
|
bitfld.long 0x00 31. " FSP_OPTION ,FSP option indicator" "Without FSP,With FSP"
|
|
bitfld.long 0x00 30. " USB_OPTION ,USB option indicator" "Without USB,With USB"
|
|
bitfld.long 0x00 29. " FPU_OPTION ,FPU option indicator" "Not present,Present"
|
|
newline
|
|
bitfld.long 0x00 28. " FLASH_OPTION ,Flash option indicator" "256k,512k"
|
|
bitfld.long 0x00 27. " ADC_OPTION ,ADC option resolution indicator" "Low,High"
|
|
bitfld.long 0x00 26. " MEM_OPTION ,Memory option indicator" "64k,128k"
|
|
newline
|
|
bitfld.long 0x00 6.--7. 14.--15. " CID[2:4] ,Chip revision" "A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P"
|
|
bitfld.long 0x00 8.--13. " CID3 ,Chip ID for product ID" "QN9020,,,,,,,,QN903x,QN903x,QN903x,QN903x,QN903x,QN903x,QN903x,QN903x,QN908x,QN908x,QN908x,QN908x,QN908x,QN908x,QN908x,QN908x,?..."
|
|
bitfld.long 0x00 3.--5. " CID1 ,Chip ID for product family" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " CID0 ,Chip ID for manufacture fab" "0,1,2,3,4,5,6,7"
|
|
if (((per.l(ad:0x40000000+0x110))&0x10000000)==0x10000000)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "ANA_CTRL0,Crystal And PA Register"
|
|
bitfld.long 0x00 30.--31. " XTAL_MODE ,Injection mode of the XTAL" "Oscillator,Digital clock,Single-end,Differential"
|
|
bitfld.long 0x00 28. " XTAL_EXTRA_CAP ,Add extra 16/32MHz XTAL load cap" "Not added,Added"
|
|
bitfld.long 0x00 22.--27. " XTAL_LOAD_CAP ,Register-controlled load cap of the XTAL in normal mode[pF]" "10,10.35,10.7,11.05,11.4,11.75,12.1,12.45,12.8,13.15,13.5,13.85,14.2,14.55,14.9,15.25,15.6,15.95,16.3,16.65,17,17.35,17.7,18.05,18.4,18.75,19.1,19.45,19.8,20.15,20.5,20.85,21.2,21.55,21.9,22.25,22.6,22.95,23.3,23.65,24,24.35,24.7,25.05,25.4,25.75,26.1,26.45,26.8,27.15,27.5,27.85,28.2,28.55,28.9,29.25,29.6,29.95,30.3,30.65,31,31.35,31.7,32.05"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " XTAL_AMP ,Crystal amplitude set register" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PA_POWER ,PA power control"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "ANA_CTRL0,Crystal And PA Register"
|
|
bitfld.long 0x00 30.--31. " XTAL_MODE ,Injection mode of the XTAL" "Oscillator,Digital clock,Single-end,Differential"
|
|
bitfld.long 0x00 28. " XTAL_EXTRA_CAP ,Add extra 16/32MHz XTAL load cap" "Not added,Added"
|
|
bitfld.long 0x00 22.--27. " XTAL_LOAD_CAP ,Register-controlled load cap of the XTAL in normal mode[pF]" "5,5.35,5.7,6.05,6.4,6.75,7.1,7.45,7.8,8.15,8.5,8.85,9.2,9.55,9.9,10.25,10.6,10.95,11.3,11.65,12,12.35,12.7,13.05,13.4,13.75,14.1,14.45,14.8,15.15,15.5,15.85,16.2,16.55,16.9,17.25,17.6,17.95,18.3,18.65,19,19.35,19.7,20.05,20.4,20.75,21.1,21.45,21.8,22.15,22.5,22.85,23.2,23.55,23.9,24.25,24.6,24.95,25.3,25.65,26,26.35,26.7,27.05"
|
|
newline
|
|
bitfld.long 0x00 20.--21. " XTAL_AMP ,Crystal amplitude set register" "0,1,2,3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PA_POWER ,PA power control"
|
|
endif
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "XTAL_CTRL,Crystal Control Register"
|
|
bitfld.long 0x00 31. " XTAL_DIV ,Divide crystal clock when external crystal is 32MHz" "32MHz,16MHz"
|
|
bitfld.long 0x00 30. " XTAL_INV ,Inverse crystal clock" "Not inversed,Inversed"
|
|
bitfld.long 0x00 24.--29. " XTAL_SU_CA_REG ,Register controlled load cap of the XTAL_A in speed-up mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. " XTAL_SU_CB_REG ,Register controlled load cap of the XTAL_B in speed-up mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 11. " DIV_DIFF_CLK_DIG_DIS ,Disables differential clock of digital" "No,Yes"
|
|
bitfld.long 0x00 10. " XTAL_XOUT_DIS_REG ,Disables 16/32MHz XTAL clock out" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. " XTAL_XRDY_REG ,Enables crystal ready signal by register" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XTAL_XSMT_EN_REG ,Hysteresis buffer regulator" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " XTAL_BP_HYSRES_REG ,Reduces the hysteresis voltage bypassing the degeneration resistor" "Not bypassed,Bypassed"
|
|
newline
|
|
bitfld.long 0x00 6. " XTAL_BPXDLY ,Bypass the power up delay in the crystal core" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 5. " XTAL_XCUR_BOOST_REG ,Crystal current boost regulator" "Not increased,Increased"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "BUCK,BUCK Control Register"
|
|
bitfld.long 0x00 21. " BUCK_IC ,Frequency compensation versus BVDD variation" "No compensation,Compensation"
|
|
bitfld.long 0x00 16.--20. " BUCK_TMOS ,Constant on time control" "Max,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Min"
|
|
bitfld.long 0x00 12.--13. " BUCK_VBG_SEL ,Buck reference setting" "1.05V,1.15V,1.2V,1.225V"
|
|
newline
|
|
bitfld.long 0x00 10.--11. " BUCK_VREF_SEL ,FC current setting" "Max,,,Min"
|
|
bitfld.long 0x00 8.--9. " BUCK_ISEL ,Buck current bias control" "50%,75%,100%,125%"
|
|
bitfld.long 0x00 1. " BUCK_IND_USE_EN ,Turn on buck output stage gradually" "No action,Turn on"
|
|
newline
|
|
bitfld.long 0x00 0. " BUCK_DRIVER_PART_EN ,Short external inductor" "Not short,Short"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "FC_FRG,Flexcomm Clock Divider Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FRG_MULT1 ,Flexcomm1 clock generator.Numerator of the fractional divider"
|
|
hexmask.long.byte 0x00 16.--23. 1. " FRG_DIV1 ,Flexcomm1 clock generator.Denominator of the fractional divider"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FRG_MULT0 ,Flexcomm0 clock generator.Numerator of the fractional divider"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " FRG_DIV0 ,Flexcomm0 clock generator.Denominator of the fractional divider"
|
|
group.long 0x800++0x11
|
|
line.long 0x00 "PIO_PULL_CFG0,Pad Pull Control Register 0"
|
|
bitfld.long 0x00 30.--31. " PA15_PULL ,PA15 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x00 28.--29. " PA14_PULL ,PA14 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x00 26.--27. " PA13_PULL ,PA13 pull control" "High-Z,Pull down,Pull up,?..."
|
|
newline
|
|
bitfld.long 0x00 24.--25. " PA12_PULL ,PA12 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x00 22.--23. " PA11_PULL ,PA11 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x00 20.--21. " PA10_PULL ,PA10 pull control" "High-Z,Pull down,Pull up,?..."
|
|
newline
|
|
bitfld.long 0x00 18.--19. " PA9_PULL ,PA9 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x00 16.--17. " PA8_PULL ,PA8 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x00 14.--15. " PA7_PULL ,PA7 pull control" "High-Z,Pull down,Pull up,?..."
|
|
newline
|
|
bitfld.long 0x00 12.--13. " PA6_PULL ,PA6 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x00 10.--11. " PA5_PULL ,PA5 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x00 8.--9. " PA4_PULL ,PA4 pull control" "High-Z,Pull down,Pull up,?..."
|
|
newline
|
|
bitfld.long 0x00 6.--7. " PA3_PULL ,PA3 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x00 4.--5. " PA2_PULL ,PA2 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x00 2.--3. " PA1_PULL ,PA1 pull control" "High-Z,Pull down,Pull up,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--1. " PA0_PULL ,PA0 pull control" "High-Z,Pull down,Pull up,?..."
|
|
line.long 0x04 "PIO_PULL_CFG1,Pad Pull Control Register 1"
|
|
bitfld.long 0x04 30.--31. " PA31_PULL ,PA31 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x04 28.--29. " PA30_PULL ,PA30 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x04 26.--27. " PA29_PULL ,PA29 pull control" "High-Z,Pull down,Pull up,?..."
|
|
newline
|
|
bitfld.long 0x04 24.--25. " PA28_PULL ,PA28 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x04 22.--23. " PA27_PULL ,PA27 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x04 20.--21. " PA26_PULL ,PA26 pull control" "High-Z,Pull down,Pull up,?..."
|
|
newline
|
|
bitfld.long 0x04 18.--19. " PA25_PULL ,PA25 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x04 16.--17. " PA24_PULL ,PA24 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x04 14.--15. " PA23_PULL ,PA23 pull control" "High-Z,Pull down,Pull up,?..."
|
|
newline
|
|
bitfld.long 0x04 12.--13. " PA22_PULL ,PA22 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x04 10.--11. " PA21_PULL ,PA21 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x04 8.--9. " PA20_PULL ,PA20 pull control" "High-Z,Pull down,Pull up,?..."
|
|
newline
|
|
bitfld.long 0x04 6.--7. " PA19_PULL ,PA19 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x04 4.--5. " PA18_PULL ,PA18 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x04 2.--3. " PA17_PULL ,PA17 pull control" "High-Z,Pull down,Pull up,?..."
|
|
newline
|
|
bitfld.long 0x04 0.--1. " PA16_PULL ,PA16 pull control" "High-Z,Pull down,Pull up,?..."
|
|
line.long 0x08 "PIO_PULL_CFG2,Pad Pull Control Register 2"
|
|
bitfld.long 0x08 4.--5. " PB2_PULL ,PB2 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x08 2.--3. " PB1_PULL ,PB1 pull control" "High-Z,Pull down,Pull up,?..."
|
|
bitfld.long 0x08 0.--1. " PB0_PULL ,PB0 pull control" "High-Z,Pull down,Pull up,?..."
|
|
wgroup.long 0x80C++0x03
|
|
line.long 0x00 "IO_CAP,IO Status Capture Register"
|
|
bitfld.long 0x00 0. " PIN_RETENTION ,Capture pad output" "No action,Captured"
|
|
group.long 0x810++0x37
|
|
line.long 0x00 "PIO_DRV_CFG0,Pad Drive Strength Register 0"
|
|
bitfld.long 0x00 31. " PA31_DRV ,PA31 drive strength" "0,1"
|
|
bitfld.long 0x00 30. " PA30_DRV ,PA30 drive strength" "0,1"
|
|
bitfld.long 0x00 29. " PA29_DRV ,PA29 drive strength" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. " PA28_DRV ,PA28 drive strength" "0,1"
|
|
bitfld.long 0x00 27. " PA27_DRV ,PA27 drive strength" "0,1"
|
|
bitfld.long 0x00 26. " PA26_DRV ,PA26 drive strength" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. " PA25_DRV ,PA25 drive strength" "0,1"
|
|
bitfld.long 0x00 24. " PA24_DRV ,PA24 drive strength" "0,1"
|
|
bitfld.long 0x00 23. " PA23_DRV ,PA23 drive strength" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. " PA22_DRV ,PA22 drive strength" "0,1"
|
|
bitfld.long 0x00 21. " PA21_DRV ,PA21 drive strength" "0,1"
|
|
bitfld.long 0x00 20. " PA20_DRV ,PA20 drive strength" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. " PA19_DRV ,PA19 drive strength" "0,1"
|
|
bitfld.long 0x00 18. " PA18_DRV ,PA18 drive strength" "0,1"
|
|
bitfld.long 0x00 17. " PA17_DRV ,PA17 drive strength" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. " PA16_DRV ,PA16 drive strength" "0,1"
|
|
bitfld.long 0x00 15. " PA15_DRV ,PA15 drive strength" "0,1"
|
|
bitfld.long 0x00 14. " PA14_DRV ,PA14 drive strength" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. " PA13_DRV ,PA13 drive strength" "0,1"
|
|
bitfld.long 0x00 12. " PA12_DRV ,PA12 drive strength" "0,1"
|
|
bitfld.long 0x00 11. " PA11_DRV ,PA11 drive strength" "0,1"
|
|
newline
|
|
bitfld.long 0x00 10. " PA10_DRV ,PA10 drive strength" "0,1"
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bitfld.long 0x00 9. " PA09_DRV ,PA09 drive strength" "0,1"
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bitfld.long 0x00 8. " PA08_DRV ,PA08 drive strength" "0,1"
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bitfld.long 0x00 7. " PA07_DRV ,PA07 drive strength" "0,1"
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bitfld.long 0x00 6. " PA06_DRV ,PA06 drive strength" "0,1"
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bitfld.long 0x00 5. " PA05_DRV ,PA05 drive strength" "0,1"
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bitfld.long 0x00 4. " PA04_DRV ,PA04 drive strength" "0,1"
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bitfld.long 0x00 3. " PA03_DRV ,PA03 drive strength" "0,1"
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bitfld.long 0x00 2. " PA02_DRV ,PA02 drive strength" "0,1"
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bitfld.long 0x00 1. " PA01_DRV ,PA01 drive strength" "0,1"
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bitfld.long 0x00 0. " PA00_DRV ,PA00 drive strength" "0,1"
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line.long 0x04 "PIO_DRV_CFG1,Pad Drive Strength Register 1"
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bitfld.long 0x04 2. " PB02_DRV ,PB02 drive strength" "0,1"
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bitfld.long 0x04 1. " PB01_DRV ,PB01 drive strength" "0,1"
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bitfld.long 0x04 0. " PB00_DRV ,PB00 drive strength" "0,1"
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line.long 0x08 "PIO_DRV_CFG2,Pad Drive Extra Register"
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bitfld.long 0x08 27. " PA27_DRV_EXTRA ,Enables extra driven on PA27" "Disabled,Enabled"
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bitfld.long 0x08 26. " PA26_DRV_EXTRA ,Enables extra driven on PA26" "Disabled,Enabled"
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bitfld.long 0x08 19. " PA19_DRV_EXTRA ,Enables extra driven on PA19" "Disabled,Enabled"
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bitfld.long 0x08 11. " PA11_DRV_EXTRA ,Enables extra driven on PA11" "Disabled,Enabled"
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bitfld.long 0x08 6. " PA06_DRV_EXTRA ,Enables extra driven on PA06" "Disabled,Enabled"
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line.long 0x0C "PIO_CFG_MISC,Pin Misc Control Register"
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bitfld.long 0x0C 19. " RFE_INV ,Inverse RFE polarity" "Not inversed,Inversed"
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bitfld.long 0x0C 18. " TRX_EN_INV ,Inverse TX_EN & RX_EN pin MUX output polarity" "Not inversed,Inversed"
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bitfld.long 0x0C 16. " PB02_MODE ,Chip mode pin function select" "Chip mode input,Antenna output"
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bitfld.long 0x0C 15. " PSYNC ,Bypass first stage of synchronization of DMA pin trigger" "Not bypassed,Bypassed"
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bitfld.long 0x0C 1. " PB01_AE ,Enable PB01 analog function" "Disabled,Enabled"
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bitfld.long 0x0C 0. " PB00_AE ,Enable PB00 analog function" "Disabled,Enabled"
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line.long 0x10 "PIO_WAKEUP_LVL0,Pin Wakeup Polarity Register 0"
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bitfld.long 0x10 31. " PA31_WAKEUP_LVL ,Control the wake-up polarity of PA31 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 30. " PA30_WAKEUP_LVL ,Control the wake-up polarity of PA30 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 29. " PA29_WAKEUP_LVL ,Control the wake-up polarity of PA29 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 28. " PA28_WAKEUP_LVL ,Control the wake-up polarity of PA28 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 27. " PA27_WAKEUP_LVL ,Control the wake-up polarity of PA27 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 26. " PA26_WAKEUP_LVL ,Control the wake-up polarity of PA26 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 25. " PA25_WAKEUP_LVL ,Control the wake-up polarity of PA25 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 24. " PA24_WAKEUP_LVL ,Control the wake-up polarity of PA24 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 23. " PA23_WAKEUP_LVL ,Control the wake-up polarity of PA23 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 22. " PA22_WAKEUP_LVL ,Control the wake-up polarity of PA22 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 21. " PA21_WAKEUP_LVL ,Control the wake-up polarity of PA21 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 20. " PA20_WAKEUP_LVL ,Control the wake-up polarity of PA20 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 19. " PA19_WAKEUP_LVL ,Control the wake-up polarity of PA19 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 18. " PA18_WAKEUP_LVL ,Control the wake-up polarity of PA18 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 17. " PA17_WAKEUP_LVL ,Control the wake-up polarity of PA17 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 16. " PA16_WAKEUP_LVL ,Control the wake-up polarity of PA16 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 15. " PA15_WAKEUP_LVL ,Control the wake-up polarity of PA15 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 14. " PA14_WAKEUP_LVL ,Control the wake-up polarity of PA14 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 13. " PA13_WAKEUP_LVL ,Control the wake-up polarity of PA13 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 12. " PA12_WAKEUP_LVL ,Control the wake-up polarity of PA12 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 11. " PA11_WAKEUP_LVL ,Control the wake-up polarity of PA11 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 10. " PA10_WAKEUP_LVL ,Control the wake-up polarity of PA10 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 9. " PA09_WAKEUP_LVL ,Control the wake-up polarity of PA09 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 8. " PA08_WAKEUP_LVL ,Control the wake-up polarity of PA08 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 7. " PA07_WAKEUP_LVL ,Control the wake-up polarity of PA07 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 6. " PA06_WAKEUP_LVL ,Control the wake-up polarity of PA06 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 5. " PA05_WAKEUP_LVL ,Control the wake-up polarity of PA05 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 4. " PA04_WAKEUP_LVL ,Control the wake-up polarity of PA04 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 3. " PA03_WAKEUP_LVL ,Control the wake-up polarity of PA03 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 2. " PA02_WAKEUP_LVL ,Control the wake-up polarity of PA02 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 1. " PA01_WAKEUP_LVL ,Control the wake-up polarity of PA01 in sleep mode" "High-level,Low-level"
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bitfld.long 0x10 0. " PA00_WAKEUP_LVL ,Control the wake-up polarity of PA00 in sleep mode" "High-level,Low-level"
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line.long 0x14 "PIO_WAKEUP_LVL1,Pin Wakeup Polarity Register 1"
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bitfld.long 0x14 2. " PB02_WAKEUP_LVL ,Control the wake-up polarity of PB02 in sleep mode" "High-level,Low-level"
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bitfld.long 0x14 1. " PB01_WAKEUP_LVL ,Control the wake-up polarity of PB01 in sleep mode" "High-level,Low-level"
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bitfld.long 0x14 0. " PB00_WAKEUP_LVL ,Control the wake-up polarity of PB00 in sleep mode" "High-level,Low-level"
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line.long 0x18 "PIO_IE_CFG0,Pad Input Enable Register 0"
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bitfld.long 0x18 31. " PA31_IE_LVL ,PA31 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 30. " PA30_IE_LVL ,PA30 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 29. " PA29_IE_LVL ,PA29 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 28. " PA28_IE_LVL ,PA28 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 27. " PA27_IE_LVL ,PA27 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 26. " PA26_IE_LVL ,PA26 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 25. " PA25_IE_LVL ,PA25 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 24. " PA24_IE_LVL ,PA24 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 23. " PA23_IE_LVL ,PA23 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 22. " PA22_IE_LVL ,PA22 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 21. " PA21_IE_LVL ,PA21 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 20. " PA20_IE_LVL ,PA20 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 19. " PA19_IE_LVL ,PA19 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 18. " PA18_IE_LVL ,PA18 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 17. " PA17_IE_LVL ,PA17 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 16. " PA16_IE_LVL ,PA16 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 15. " PA15_IE_LVL ,PA15 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 14. " PA14_IE_LVL ,PA14 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 13. " PA13_IE_LVL ,PA13 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 12. " PA12_IE_LVL ,PA12 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 11. " PA11_IE_LVL ,PA11 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 10. " PA10_IE_LVL ,PA10 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 9. " PA09_IE_LVL ,PA09 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 8. " PA08_IE_LVL ,PA08 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 7. " PA07_IE_LVL ,PA07 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 6. " PA06_IE_LVL ,PA06 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 5. " PA05_IE_LVL ,PA05 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 4. " PA04_IE_LVL ,PA04 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 3. " PA03_IE_LVL ,PA03 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 2. " PA02_IE_LVL ,PA02 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 1. " PA01_IE_LVL ,PA01 digital input enable" "Disabled,Enabled"
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bitfld.long 0x18 0. " PA00_IE_LVL ,PA00 digital input enable" "Disabled,Enabled"
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line.long 0x1C "PIO_IE_CFG1,Pad Input Enable Register 1"
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bitfld.long 0x1C 2. " BOOT_MODE_IE ,PB02 input enable" "Disabled,Enabled"
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bitfld.long 0x1C 1. " PB01_IE_LVL ,PB01 digital input enable" "Disabled,Enabled"
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bitfld.long 0x1C 0. " PB00_IE_LVL ,PB00 digital input enable" "Disabled,Enabled"
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line.long 0x20 "PIO_FUNC_CFG0,Pin MUX Control Register 0"
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bitfld.long 0x20 28.--30. " PA07_FUNC ,PA07 function control register" ",GPIOA7(I/O),ADC_VREFI(AI),SCT0_OUT2(O),CTIMER1_CAP0(I),FC1_CTS_SDA(I/O),BLE_PTI1(O),SPIFI_CSN(O)"
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bitfld.long 0x20 24.--26. " PA06_FUNC ,PA06 function control register" ",GPIOA6(I/O),ADC_EX_CAP(AI),SCT0_OUT3(O),CTIMER0_MAT2(O),FC1_RTS_SCL(I/O),BLE_PTI0(O),SPIFI_CLK(O)"
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bitfld.long 0x20 20.--22. " PA05_FUNC ,PA05 function control register" ",GPIOA5(I/O),ADC3(AI),SCT0_OUT5(O),CTIMER0_MAT1(O),FC0_RXD(I/O),FC2_SCL_MISO(I/O),SPIFI_IO1(I/O)"
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newline
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bitfld.long 0x20 16.--18. " PA04_FUNC ,PA04 function control register" ",GPIOA4(I/O),ADC2(AI),SCT0_OUT4(O),CTIMER0_MAT0(O),FC0_TXD(O),FC2_SDA_MOSI(I/O),SPIFI_IO0(I/O)"
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bitfld.long 0x20 12.--14. " PA03_FUNC ,PA03 function control register" ",GPIOA3(I/O),QDEC0_B(I),SCT0_OUT3(O),CTIMER0_MAT1(O),,FC2_SDA_SSEL0(I/O),RFE_TX_EN(O)"
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bitfld.long 0x20 8.--10. " PA02_FUNC ,PA02 function control register" ",GPIOA2(I/O),QDEC0_A(I),SCT0_OUT2(0),CTIMER0_MAT0(O),,FC2_SCL_SSEL1(I/O),RFE_RX_EN(O)"
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newline
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bitfld.long 0x20 4.--6. " PA01_FUNC ,PA01 function control register" ",GPIOA1(I/O),ADC1(AI),SCT0_OUT1(0),CTIMER0_CAP1(I),FC0_CTS(O),FC2_SSEL2(I/O),WLAN_RX(I)"
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bitfld.long 0x20 0.--2. " PA00_FUNC ,PA00 function control register" ",GPIOA0(I/O),ADC0(AI),SCT0_OUT0(0),CTIMER0_CAPO(I),FC0_RTS(O),FC2_SSEL3(I/O),WLAN_TX(I)"
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line.long 0x24 "PIO_FUNC_CFG1,Pin MUX Control Register 1"
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bitfld.long 0x24 28.--30. " PA15_FUNC ,PA15 function control register" ",GPIOA15(I/O),CS1(AI),SCT0_OUT0(O),CTIMER2_CAP1(I),FC0_CTS(I),FC3_SCK(I/O),QDEC1_B(I)"
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bitfld.long 0x24 24.--26. " PA14_FUNC ,PA14 function control register" ",GPIOA14(I/O),CS0(AI),ANT_SW(O),CTIMER2_CAP0(I),FC0_RTS(O),FC3_SSEL0(I/O),QDEC1_A(I)"
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bitfld.long 0x24 20.--22. " PA13_FUNC ,PA13 function control register" ",GPIOA13(I/O),,SCT0_OUT4(O),ACMP1_OUT(O),FC1_RXD_SDA(I/O),FC3_SSEL1(I/O),RFE_EN(O)"
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newline
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bitfld.long 0x24 16.--18. " PA12_FUNC ,PA12 function control register" ",GPIOA12(I/O),,SCT0_OUT5(O),ACMP0_OUT(O),FC1_TXD_SCL(I/O),DC_DAC(O),ANT_SW(O)"
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bitfld.long 0x24 12.--14. " PA11_FUNC ,PA11 function control register" ",GPIOA11(I/O),ADC7(AI),SCT0_IN3(I),CTIMER1_MAT2(O),FC2_SSEL2(I/O),ACMP1_OUT(O),BLE_RX(O)"
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bitfld.long 0x24 8.--10. " PA10_FUNC ,PA10 function control register" ",GPIOA10(I/O),ADC6(AI),SCT0_IN2(I),CTIMER1_MAT1(O),FC1_SCK(I/O),ACMP0_OUT(O),BLE_TX(O)"
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bitfld.long 0x24 4.--6. " PA09_FUNC ,PA09 function control register" ",GPIOA9(I/O),ADC5(AI),SCT0_IN1(I),CTIMER0_MAT0(O),FC1_RXD_SDA(I/O),BLE_PTI3(O),SPIFI_IO3(I/O)"
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bitfld.long 0x24 0.--2. " PA08_FUNC ,PA08 function control register" ",GPIOA8(I/O),ADC4(AI),SCT0_IN0(I),CTIMER0_CAP1(I),FC1_TXD_SCL(I/O),BLE_PTI2(O),SPIFI_IO2(I/O)"
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line.long 0x28 "PIO_FUNC_CFG2,Pin MUX Control Register 2"
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bitfld.long 0x28 28.--30. " PA23_FUNC ,PA23 function control register" ",SWDIO(I/O),GPIOA23(I/O),SCT0_IN3(I),CTIMER3_MAT1(O),FC2_SCL_SSEL1(I/O),FC3_SSEL2(I/O),QDEC1_B(I)"
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bitfld.long 0x28 24.--26. " PA22_FUNC ,PA22 function control register" ",SWCLK(I/O),GPIOA22(I/O),SCT0_IN2(I),CTIMER3_MAT0(O),FC2_SDA_SSEL0(I/O),FC3_SSEL3(I/O),QDEC1_A(I)"
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bitfld.long 0x28 20.--22. " PA21_FUNC ,PA21 function control register" ",GPIOA21(I/O),QDEC1_B(I),SCT0_OUT0(O),CTIMER2_MAT1(O),FC2_SSEL3(I/O),FC1_CTS_SDA(I/O),SPIFI_CSN(O)"
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newline
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bitfld.long 0x28 16.--18. " PA20_FUNC ,PA20 function control register" ",GPIOA20(I/O),QDEC1_A(I),SCT0_OUT1(O),CTIMER2_MAT0(O),SWO(I/O),FC1_RTS_SCL(I/O),SPIFI_CLK(O)"
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bitfld.long 0x28 12.--14. " PA19_FUNC ,PA19 function control register" ",GPIOA19(I/O),CS5(AI),SCT0_OUT2(O),RFE_EN(O),FC0_SCK(I/O),FC3_SSEL3(I/O),BLE_IN_PROC(O)"
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bitfld.long 0x28 8.--10. " PA18_FUNC ,PA18 function control register" ",GPIOA18(I/O),CS4(AI),SCT0_OUT3(O),CTIMER2_MAT2(O),FC0_SCK(I/O),FC3_SSEL2(I/O),BLE_SYNC(O)"
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newline
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bitfld.long 0x28 4.--6. " PA17_FUNC ,PA17 function control register" ",GPIOA17(I/O),CS3(AI),SD_DAC(O),CTIMER2_MAT1(O),FC0_RXD(I/O),FC3_MISO(I/O),QDEC0_B(I)"
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bitfld.long 0x28 0.--2. " PA16_FUNC ,PA16 function control register" ",GPIOA16(I/O),CS2(AI),SCT0_OUT1(O),CTIMER2_MAT0(O),FC0_TXD(O),FC3_MOSI(I/O),QDEC0_A(I)"
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line.long 0x2C "PIO_FUNC_CFG3,Pin MUX Control Register 3"
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bitfld.long 0x2C 28.--30. " PA31_FUNC ,PA31 function control register" ",GPIOA31(I/O),DAC(A0),RTC_CAP(I),CTIMER3_MAT2(O),SWO(I/O),FC3_SCK(I/O),SPIFI_CLK(O)"
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bitfld.long 0x2C 24.--26. " PA30_FUNC ,PA30 function control register" ",GPIOA30(I/O),ACMP1P(AI),ETM_TRACEDAT3(O),CTIMER3_MAT1(O),FC2_SCK(I/O),FC3_MOSI(I/O),SPIFI_IO3(I/0)"
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bitfld.long 0x2C 20.--22. " PA29_FUNC ,PA29 function control register" ",GPIOA29(I/O),ACMP1N(AI),ETM_TRACEDAT2(O),CTIMER3_MAT0(O),FC2_SCK(I/O),FC3_MISO(I/O),SPIFI_IO2(I/O)"
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newline
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bitfld.long 0x2C 16.--18. " PA28_FUNC ,PA28 function control register" ",GPIOA28(I/O),CLK_AHB(O),ETM_TRACECLK(O),RTC_CAP(I),FC1_SCK(I/O),SD_DAC(O),SPIFI_CSN(O)"
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bitfld.long 0x2C 12.--14. " PA27_FUNC ,PA27 function control register" ",GPIOA27(I/O),USB_DM(A),SCT0_IN1(I),CTIMER1_MAT2(O),FC2_SCL_MISO(I/O),QDEC0_B(I),BLE_IN_PROC(O)"
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bitfld.long 0x2C 8.--10. " PA26_FUNC ,PA26 function control register" ",GPIOA26(I/O),USB_DP(A),SCT0_IN0(I),CTIMER1_MAT0(O),FC2_SDA_MOSI(I/O),QDEC0_A(I),BLE_SYNC(O)"
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bitfld.long 0x2C 4.--6. " PA25_FUNC ,PA25 function control register" ",GPIOA25(I/O),ACMPOP/CS7(AI),ETM_TRACEDAT1(O),CTIMER3_CAP1(I),RFE_TX_EN(O),FC3_SSEL0(I/O),SPIFI_IO1(I/O)"
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bitfld.long 0x2C 0.--2. " PA24_FUNC ,PA24 function control register" ",GPIOA24(I/O),ACMPON/CS6(AI),ETM_TRACEDAT0(O),CTIMER3_CAP0(I),RFE_RX_EN(O),FC3_SSEL1(I/O),SPIFI_IO0(I/O)"
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line.long 0x30 "PIO_WAKEUP_EN0,Pin Function Selection In Sleep Mode Register 0"
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bitfld.long 0x30 31. " PA31_WAKEUP_EN ,Control GPIOA[31] as wakeup source" "Not controlled,Controlled"
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bitfld.long 0x30 30. " PA30_WAKEUP_EN ,Control GPIOA[30] as wakeup source" "Not controlled,Controlled"
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bitfld.long 0x30 29. " PA29_WAKEUP_EN ,Control GPIOA[29] as wakeup source" "Not controlled,Controlled"
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bitfld.long 0x30 28. " PA28_WAKEUP_EN ,Control GPIOA[28] as wakeup source" "Not controlled,Controlled"
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bitfld.long 0x30 27. " PA27_WAKEUP_EN ,Control GPIOA[27] as wakeup source" "Not controlled,Controlled"
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bitfld.long 0x30 26. " PA26_WAKEUP_EN ,Control GPIOA[26] as wakeup source" "Not controlled,Controlled"
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newline
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bitfld.long 0x30 25. " PA25_WAKEUP_EN ,Control GPIOA[25] as wakeup source" "Not controlled,Controlled"
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bitfld.long 0x30 24. " PA24_WAKEUP_EN ,Control GPIOA[24] as wakeup source" "Not controlled,Controlled"
|
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bitfld.long 0x30 23. " PA23_WAKEUP_EN ,Control GPIOA[23] as wakeup source" "Not controlled,Controlled"
|
|
newline
|
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bitfld.long 0x30 22. " PA22_WAKEUP_EN ,Control GPIOA[22] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 21. " PA21_WAKEUP_EN ,Control GPIOA[21] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 20. " PA20_WAKEUP_EN ,Control GPIOA[20] as wakeup source" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x30 19. " PA19_WAKEUP_EN ,Control GPIOA[19] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 18. " PA18_WAKEUP_EN ,Control GPIOA[18] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 17. " PA17_WAKEUP_EN ,Control GPIOA[17] as wakeup source" "Not controlled,Controlled"
|
|
newline
|
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bitfld.long 0x30 16. " PA16_WAKEUP_EN ,Control GPIOA[16] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 15. " PA15_WAKEUP_EN ,Control GPIOA[15] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 14. " PA14_WAKEUP_EN ,Control GPIOA[14] as wakeup source" "Not controlled,Controlled"
|
|
newline
|
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bitfld.long 0x30 13. " PA13_WAKEUP_EN ,Control GPIOA[13] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 12. " PA12_WAKEUP_EN ,Control GPIOA[12] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 11. " PA11_WAKEUP_EN ,Control GPIOA[11] as wakeup source" "Not controlled,Controlled"
|
|
newline
|
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bitfld.long 0x30 10. " PA10_WAKEUP_EN ,Control GPIOA[10] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 9. " PA09_WAKEUP_EN ,Control GPIOA[9] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 8. " PA08_WAKEUP_EN ,Control GPIOA[8] as wakeup source" "Not controlled,Controlled"
|
|
newline
|
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bitfld.long 0x30 7. " PA07_WAKEUP_EN ,Control GPIOA[7] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 6. " PA06_WAKEUP_EN ,Control GPIOA[6] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 5. " PA05_WAKEUP_EN ,Control GPIOA[5] as wakeup source" "Not controlled,Controlled"
|
|
newline
|
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bitfld.long 0x30 4. " PA04_WAKEUP_EN ,Control GPIOA[4] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 3. " PA03_WAKEUP_EN ,Control GPIOA[3] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 2. " PA02_WAKEUP_EN ,Control GPIOA[2] as wakeup source" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x30 1. " PA01_WAKEUP_EN ,Control GPIOA[1] as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x30 0. " PA00_WAKEUP_EN ,Control GPIOA[0] as wakeup source" "Not controlled,Controlled"
|
|
line.long 0x34 "PIO_WAKEUP_EN1,Pin Function Selection In Sleep Mode Register 1"
|
|
bitfld.long 0x34 31. " PDM_IO_SEL ,Pin status selection in power-down mode" "PIO_CFGx,IO_CAP"
|
|
bitfld.long 0x34 25. " PA25_XTAL_OE ,XTAL clock output enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 24. " PA24_32K_OE ,32K clock output enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x34 19. " PA19_XTAL_OE ,XTAL clock output enable" "Disabled,Enabled"
|
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bitfld.long 0x34 18. " PA18_32K_OE ,32K clock output enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 11. " PA11_XTAL_OE ,XTAL clock output enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x34 10. " PA10_32K_OE ,32K clock output enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 5. " PA05_XTAL_OE ,XTAL clock output enable" "Disabled,Enabled"
|
|
bitfld.long 0x34 4. " PA04_32K_OE ,32K clock output enable" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x34 2. " PB02_WAKEUP_EN ,Control PB02 in GPIOB as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x34 1. " PB01_WAKEUP_EN ,Control PB01 in GPIOB as wakeup source" "Not controlled,Controlled"
|
|
bitfld.long 0x34 0. " PB00_WAKEUP_EN ,Control PB00 in GPIOB as wakeup source" "Not controlled,Controlled"
|
|
rgroup.long 0x848++0x0F
|
|
line.long 0x00 "PIO_CAP_OE0,Pin Output Enable Status In Sleep Mode Register 0"
|
|
bitfld.long 0x00 31. " PA31_CAP_OE ,PA31 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PA30_CAP_OE ,PA30 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " PA29_CAP_OE ,PA29 output enable status" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 28. " PA28_CAP_OE ,PA28 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PA27_CAP_OE ,PA27 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " PA26_CAP_OE ,PA26 output enable status" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 25. " PA25_CAP_OE ,PA25 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " PA24_CAP_OE ,PA24 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " PA23_CAP_OE ,PA23 output enable status" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 22. " PA22_CAP_OE ,PA22 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " PA21_CAP_OE ,PA21 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " PA20_CAP_OE ,PA20 output enable status" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 19. " PA19_CAP_OE ,PA19 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PA18_CAP_OE ,PA18 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PA17_CAP_OE ,PA17 output enable status" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 16. " PA16_CAP_OE ,PA16 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PA15_CAP_OE ,PA15 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PA14_CAP_OE ,PA14 output enable status" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 13. " PA13_CAP_OE ,PA13 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PA12_CAP_OE ,PA12 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PA11_CAP_OE ,PA11 output enable status" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 10. " PA10_CAP_OE ,PA10 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PA09_CAP_OE ,PA09 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PA08_CAP_OE ,PA08 output enable status" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 7. " PA07_CAP_OE ,PA07 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PA06_CAP_OE ,PA06 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PA05_CAP_OE ,PA05 output enable status" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 4. " PA04_CAP_OE ,PA04 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PA03_CAP_OE ,PA03 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PA02_CAP_OE ,PA02 output enable status" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x00 1. " PA01_CAP_OE ,PA01 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PA00_CAP_OE ,PA00 output enable status" "Disabled,Enabled"
|
|
line.long 0x04 "PIO_CAP_OE1,Pin Output Enable Status In Sleep Mode Register 1"
|
|
bitfld.long 0x04 2. " PB02_CAP_OE ,PB02 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " PB01_CAP_OE ,PB01 output enable status" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " PB00_CAP_OE ,PB00 output enable status" "Disabled,Enabled"
|
|
line.long 0x08 "PIO_CAP_OUT0,Pin Output Status In Sleep Mode Register 0"
|
|
bitfld.long 0x08 31. " PA31_CAP_OUT ,PA31 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " PA30_CAP_OUT ,PA30 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " PA29_CAP_OUT ,PA29 output status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 28. " PA28_CAP_OUT ,PA28 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 27. " PA27_CAP_OUT ,PA27 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " PA26_CAP_OUT ,PA26 output status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 25. " PA25_CAP_OUT ,PA25 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " PA24_CAP_OUT ,PA24 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 23. " PA23_CAP_OUT ,PA23 output status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 22. " PA22_CAP_OUT ,PA22 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " PA21_CAP_OUT ,PA21 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " PA20_CAP_OUT ,PA20 output status" "Disabled,Enabled"
|
|
newline
|
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bitfld.long 0x08 19. " PA19_CAP_OUT ,PA19 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " PA18_CAP_OUT ,PA18 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 17. " PA17_CAP_OUT ,PA17 output status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 16. " PA16_CAP_OUT ,PA16 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " PA15_CAP_OUT ,PA15 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " PA14_CAP_OUT ,PA14 output status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 13. " PA13_CAP_OUT ,PA13 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " PA12_CAP_OUT ,PA12 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " PA11_CAP_OUT ,PA11 output status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 10. " PA10_CAP_OUT ,PA10 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " PA09_CAP_OUT ,PA09 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " PA08_CAP_OUT ,PA08 output status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 7. " PA07_CAP_OUT ,PA07 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " PA06_CAP_OUT ,PA06 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " PA05_CAP_OUT ,PA05 output status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 4. " PA04_CAP_OUT ,PA04 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " PA03_CAP_OUT ,PA03 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PA02_CAP_OUT ,PA02 output status" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x08 1. " PA01_CAP_OUT ,PA01 output status" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " PA00_CAP_OUT ,PA00 output status" "Disabled,Enabled"
|
|
line.long 0x0C "PIO_CAP_OUT1,Pin Output Status In Sleep Mode Register 1"
|
|
bitfld.long 0x0C 2. " PB02_CAP_OUT ,PB02 output status" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " PB01_CAP_OUT ,PB01 output status" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " PB00_CAP_OUT ,PB00 output status" "Disabled,Enabled"
|
|
group.long 0x0858++0x0F
|
|
line.long 0x00 "RST_CAUSE_SRC,Reset Source Status Register 0"
|
|
bitfld.long 0x00 31. " RST_CAUSE_CLR ,RESET_CAUSE clear" "No action,Clear"
|
|
hexmask.long.word 0x00 0.--8. 1. " RESET_CAUSE ,Reset source indicator"
|
|
line.long 0x04 "PMU_CTRL0,Power Management Unit Control Register 0"
|
|
bitfld.long 0x04 31. " BOND_EN ,Enable FSP option" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " RETENTION_EN ,Enable all CPU registers to be retained in power-down mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " PMU_EN ,Enable chip power-down mode" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 28. " WAKEUP_EN ,Enable sleep wakeup source" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " RTC_SEC_WAKEUP_EN ,Enable RTC interrupt as wakeup source" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " OSC_INT_EN ,Enable OSC_EN as interrupt and wakeup source" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 20. " MCU_MODE ,Power management BG/V2I/VREG_A/VREG_D" "Power on,Power down"
|
|
bitfld.long 0x04 18. " FSP_DIS ,Power management FSP/USB/CRC/SPIFI" "Power on,Power down"
|
|
bitfld.long 0x04 17. " FIR_DIS ,Power management FIR buffer" "Power on,Power down"
|
|
newline
|
|
bitfld.long 0x04 16. " BLE_DID ,Power management on BLE" "Power on,Power down"
|
|
bitfld.long 0x04 9. " MEM9_DIS ,Power control for SRAM memory block 9" "Power on,Power down"
|
|
bitfld.long 0x04 8. " MEM8_DIS ,Power control for SRAM memory block 8" "Power on,Power down"
|
|
newline
|
|
bitfld.long 0x04 7. " MEM7_DIS ,Power control for SRAM memory block 7" "Power on,Power down"
|
|
bitfld.long 0x04 6. " MEM6_DIS ,Power control for SRAM memory block 6" "Power on,Power down"
|
|
bitfld.long 0x04 5. " MEM5_DIS ,Power control for SRAM memory block 5" "Power on,Power down"
|
|
newline
|
|
bitfld.long 0x04 4. " MEM4_DIS ,Power control for SRAM memory block 4" "Power on,Power down"
|
|
bitfld.long 0x04 3. " MEM3_DIS ,Power control for SRAM memory block 3" "Power on,Power down"
|
|
bitfld.long 0x04 2. " MEM2_DIS ,Power control for SRAM memory block 2" "Power on,Power down"
|
|
newline
|
|
bitfld.long 0x04 1. " MEM1_DIS ,Power control for SRAM memory block 1" "Power on,Power down"
|
|
bitfld.long 0x04 0. " MEM0_DIS ,Power control for SRAM memory block 0" "Power on,Power down"
|
|
line.long 0x08 "PMU_CTRL1,Power Management Unit Control Register 1"
|
|
bitfld.long 0x08 31. " XTAL32K_PDM_DIS ,XTAL32K power control in sleep mode" "Power on,Power down"
|
|
bitfld.long 0x08 30. " RCO32K_PDM_DIS ,RCO32K power control in sleep mode" "Power on,Power down"
|
|
bitfld.long 0x08 16.--19. " BUCK_CTRL ,BUCK power control" "Power on,1,2,3,4,5,6,7,8,9,10,11,12,13,14,Power down"
|
|
newline
|
|
bitfld.long 0x08 11. " CAP_SEN_DIS ,Cap sensor power control" "Power on,Power down"
|
|
bitfld.long 0x08 10. " DAC_DIS ,DAC power control" "Power on,Power down"
|
|
bitfld.long 0x08 9. " ADC_VREF_DIS ,VREF DRV in SD ADC power control" "Power on,Power down"
|
|
newline
|
|
bitfld.long 0x08 8. " ADC_VCM_DIS ,VCM DRV in SD ADC power control" "Power on,Power down"
|
|
bitfld.long 0x08 7. " ADC_DIS ,SD ADC power control" "Power on,Power down"
|
|
bitfld.long 0x08 6. " ADC_BG_DIS ,Bandgap in SD ADC power control" "Power on,Power down"
|
|
newline
|
|
bitfld.long 0x08 5. " ADC_BUF_DIS ,Buffer in SD ADC power control" "Power on,Power down"
|
|
bitfld.long 0x08 4. " USBPLL_DIS ,USB 48 M PLL power control" "Power on,Power down"
|
|
bitfld.long 0x08 3. " OSC32M_DIS ,OSC power control" "Analog circuit control,Power down"
|
|
newline
|
|
bitfld.long 0x08 2. " XTAL_DIS ,XTAL 16/32MHz power control" "Power on,Power down"
|
|
bitfld.long 0x08 1. " XTAL32K_DIS ,XTAL 32kHz power control" "Power on,Power down"
|
|
bitfld.long 0x08 0. " RCO32K_DIS ,32k RCO power control" "Power on,Power down"
|
|
line.long 0x0C "ANA_EN,Analog Setting Register"
|
|
bitfld.long 0x0C 31. " ACMP1_INTEN ,Enable ACMP1 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " ACMP0_INTEN ,Enable ACMP0 interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28.--29. " ACMP1_EDGE_SEL ,ACMP1 interrupt edge selection" "Positive,Negative,Both,?..."
|
|
newline
|
|
bitfld.long 0x0C 26.--27. " ACMP0_EDGE_SEL ,ACMP0 interrupt edge selection" "Positive,Negative,Both,?..."
|
|
rbitfld.long 0x0C 25. " ACMP1_VALUE ,Comparator 1 output" "0,1"
|
|
rbitfld.long 0x0C 24. " ACMP0_VALUE ,Comparator 0 output" "0,1"
|
|
newline
|
|
bitfld.long 0x0C 21.--22. " BOR_THR ,Brown-out reset threshold voltages" "1.5V,1.85V,2V,3V"
|
|
bitfld.long 0x0C 19.--20. " BOD_THR ,Brown-out reset threshold voltages" "2.06V,2.45V,2.72V,3.04V"
|
|
bitfld.long 0x0C 18. " ACMP_VREF_SEL ,Acmp_vref selection" "VBG,VCC"
|
|
newline
|
|
bitfld.long 0x0C 17. " ACMP1_HYST_EN ,Hysteresis enable of ACMP1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " ACMP0_HYST_EN ,Hysteresis enable of ACMP0" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12.--15. " ACMP1_REF ,ACMP1 reference voltage selection" "External,Acmp_vref*1/16,Acmp_vref*2/16,Acmp_vref*3/16,Acmp_vref*4/16,Acmp_vref*5/16,Acmp_vref*6/16,Acmp_vref*7/16,Acmp_vref*8/16,Acmp_vref*9/16,Acmp_vref*10/16,Acmp_vref*11/16,Acmp_vref*12/16,Acmp_vref*13/16,Acmp_vref*14/16,Acmp_vref*15/16"
|
|
newline
|
|
bitfld.long 0x0C 8.--11. " ACMP0_REF ,ACMP0 reference voltage selection" "External,Acmp_vref*1/16,Acmp_vref*2/16,Acmp_vref*3/16,Acmp_vref*4/16,Acmp_vref*5/16,Acmp_vref*6/16,Acmp_vref*7/16,Acmp_vref*8/16,Acmp_vref*9/16,Acmp_vref*10/16,Acmp_vref*11/16,Acmp_vref*12/16,Acmp_vref*13/16,Acmp_vref*14/16,Acmp_vref*15/16"
|
|
bitfld.long 0x0C 6. " BOR_EN ,Enable brown-out reset detector" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " BOR_AMP_EN ,Enable the AMP of brown-out reset detector" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 4. " ACMP1_EN ,Enable comparator 1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " ACMP0_EN ,Enable comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " BAT_MON_EN ,Enable battery monitor" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 1. " BOD_EN ,Enable brown-out detector" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " BOD_AMP_EN ,Enable the AMP of brown-out detector" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40000000+0x868))&0x4000)==0x4000)
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "XTAL32K_CTRL,Crystal 32K Control Register"
|
|
bitfld.long 0x00 14. " XTAL32K_EXTRA_CAP ,Add extra XTAL32K load cap or not" "Not added,Added"
|
|
bitfld.long 0x00 8.--13. " XTAL32K_LOAD_CAP ,Load cap selection of XTAL32K" "10pF,10.4pF,10.8pF,11.2pF,11.6pF,12pF,12.4pF,12.8pF,13.2pF,13.6pF,14pF,14.4pF,14.8pF,15.2pF,15.6pF,16pF,16.4pF,16.8pF,17.2pF,17.6pF,18pF,18.4pF,18.8pF,19.2pF,19.6pF,20pF,20.4pF,20.8pF,21.2pF,21.6pF,22pF,22.4pF,22.8pF,23.2pF,23.6pF,24pF,24.4pF,24.8pF,25.2pF,25.6pF,26pF,26.4pF,26.8pF,27.2pF,27.6pF,28pF,28.4pF,28.8pF,29.2pF,29.6pF,30pF,30.4pF,30.8pF,31.2pF,31.6pF,32pF,32.4pF,32.8pF,33.2pF,33.6pF,34pF,34.4pF,34.8pF,35.2pF"
|
|
bitfld.long 0x00 6.--7. " XTAL32K_INJ ,XTAL 32kHz clock injection mode" "On-chip oscillator,External digital clock,External sine wave clock,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--5. " XTALK32K_ICTRL ,XTAL 32 gm cell current bias Y" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x868++0x03
|
|
line.long 0x00 "XTAL32K_CTRL,Crystal 32K Control Register"
|
|
bitfld.long 0x00 14. " XTAL32K_EXTRA_CAP ,Add extra XTAL32K load cap or not" "Not added,Added"
|
|
bitfld.long 0x00 8.--13. " XTAL32K_LOAD_CAP ,Load cap selection of XTAL32K" "3.6pF,4pF,4.4pF,4.8pF,5.2pF,5.6pF,6pF,6.4pF,6.8pF,7.2pF,7.6pF,8pF,8.4pF,8.8pF,9.2pF,9.6pF,10pF,10.4pF,10.8pF,11.2pF,11.6pF,12pF,12.4pF,12.8pF,13.2pF,13.6pF,14pF,14.4pF,14.8pF,15.2pF,15.6pF,16pF,16.4pF,16.8pF,17.2pF,17.6pF,18pF,18.4pF,18.8pF,19.2pF,19.6pF,20pF,20.4pF,20.8pF,21.2pF,21.6pF,22pF,22.4pF,22.8pF,23.2pF,23.6pF,24pF,24.4pF,24.8pF,25.2pF,25.6pF,26pF,26.4pF,26.8pF,27.2pF,27.6pF,28pF,28.4pF,28.8pF"
|
|
bitfld.long 0x00 6.--7. " XTAL32K_INJ ,XTAL 32kHz clock injection mode" "On-chip oscillator,External digital clock,External sine wave clock,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--5. " XTALK32K_ICTRL ,XTAL 32 gm cell current bias Y" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
group.long 0x86C++0x03
|
|
line.long 0x00 "USB_CFG,USB Configuration Register"
|
|
bitfld.long 0x00 5. " USB_PHYSTDBY_WEN ,USB PHY control power selection" "USB controller,USB PHYSTDBY register"
|
|
bitfld.long 0x00 4. " USB_PHYSTDBY ,USB PHY power control" "Off,On"
|
|
bitfld.long 0x00 3. " USB_VBUS ,USB voltage connection" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. " DPPUEN_B_PHY_SEL ,Control source selection for pull-up resistor" "Register,USB"
|
|
bitfld.long 0x00 0. " DPPUEN_B_PHY_POL ,Drive high to inverse the polarity of the connection" "Low,High"
|
|
group.long 0x880++0x07
|
|
line.long 0x00 "PMU_CTRL2,Power Management Unit Control Register 2"
|
|
bitfld.long 0x00 31. " SEL_PD ,Power control selection" "HW,SW"
|
|
bitfld.long 0x00 30. " FLSH_PDM_DIS ,Power down flash VDD25 in power-down mode" "No action,Power down"
|
|
bitfld.long 0x00 29. " FLSH_DIS ,Switch off flash power" "Switched on,Switched off"
|
|
newline
|
|
bitfld.long 0x00 21. " RC_CAL_DIS ,Switch off RCCAL power" "Switched on,Switched off"
|
|
bitfld.long 0x00 20. " SAR_DIS ,Switch off SAR ADC power" "Switched on,Switched off"
|
|
bitfld.long 0x00 19. " PPF_DIS ,Switch off PPF power" "Switched on,Switched off"
|
|
newline
|
|
bitfld.long 0x00 18. " PKDET_DIS ,Switch off RRF and PPF peek detector power" "Switched on,Switched off"
|
|
bitfld.long 0x00 17. " MIXER_DIS ,Switch off MIXER power" "Switched on,Switched off"
|
|
bitfld.long 0x00 16. " LNA_DIS ,Switch off LNA power" "Switched on,Switched off"
|
|
newline
|
|
bitfld.long 0x00 15. " PA_DIS ,Switch off PA power" "Switched on,Switched off"
|
|
bitfld.long 0x00 14. " PA_PK_DIS ,Switch off PA peek detector power" "Switched on,Switched off"
|
|
bitfld.long 0x00 13. " VCO_DIS ,Switch off VCO power" "Switched on,Switched off"
|
|
newline
|
|
bitfld.long 0x00 12. " LO_DIS ,Switch off LO power" "Switched on,Switched off"
|
|
bitfld.long 0x00 11. " VREG_D_DIS ,Switch off VREG_D power" "Switched on,Switched off"
|
|
bitfld.long 0x00 10. " VREG_A_DIS ,Switch off VREG_A power" "Switched on,Switched off"
|
|
newline
|
|
bitfld.long 0x00 9. " V2L_DIS ,Switch off V2L power" "Switched on,Switched off"
|
|
bitfld.long 0x00 8. " BG_DIS ,Switch off bandgap power" "Switched on,Switched off"
|
|
bitfld.long 0x00 7. " RX_EN_SEL ,RX_EN width selection" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. " RFAGC_ON ,Enable RFAGC" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " OSC32M_PDM_DIS ,Power down 32M oscillator in power-down mode" "Power on,Power down"
|
|
bitfld.long 0x00 4. " XTAL_PDM_DIS ,Power down XTAL in power-down mode" "Power on,Power down"
|
|
newline
|
|
bitfld.long 0x00 3. " VREG_D_PDM_DIS ,Power down VREG_D in power-down mode" "Power on,Power down"
|
|
bitfld.long 0x00 2. " VREG_A_PDM_DIS ,Power down VREG_A in power-down mode" "Power on,Power down"
|
|
bitfld.long 0x00 1. " V2L_PDM_DIS ,Power down V2L in power-down mode" "Power on,Power down"
|
|
newline
|
|
bitfld.long 0x00 0. " BG_PDM_DIS ,Power down bandgap in power-down mode" "Power on,Power down"
|
|
line.long 0x04 "ANA_CTRL1,IVREF And DVREG Setting Register"
|
|
bitfld.long 0x04 31. " BUCK_DPD ,ZC control select" "Low,High"
|
|
bitfld.long 0x04 28.--30. " DVREG11_SET_DIG ,Vregd set" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 26.--27. " BM_X32BUF ,XTAL32K buffer current bias" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 25. " X32_SMT_EN ,Enable schmidt trigger in XTAL32K" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " XTAL32K_FORCE_RDY ,XTAL32K ready from register" "Not ready,Ready"
|
|
bitfld.long 0x04 21.--23. " IV_VREG11_SET ,VREG11 setting" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x04 19.--20. " IV_IREF_SEL ,Reference current selection" "0,1,2,3"
|
|
bitfld.long 0x04 18. " BUCK_PD_DCM ,Setting buck in DCM mode" "DCM mode,No action"
|
|
bitfld.long 0x04 17. " BUCK_PD_CCM ,Setting buck in CCM mode" "CCM mode,No action"
|
|
newline
|
|
bitfld.long 0x04 16. " PDM_DIS_BUCK ,Power off buck in power-down mode" "Power on,Power off"
|
|
bitfld.long 0x04 12.--15. " IV_BG_SEL ,VBG voltage select" "1200mV,1203mV,1206mV,1209mV,1212mV,1215mV,1218mV,1221mV,1224mV,1227mV,1230mV,1233mV,1236mV,1239mV,1242mV,1245mV"
|
|
bitfld.long 0x04 11. " VDD_PMU_MEM_SW ,Close the switch between vdd_omu and vdd_mem" "Open,Close"
|
|
newline
|
|
bitfld.long 0x04 10. " VDD_PMU_SET_ULTRA_LOW ,Ultra low setting ofr vdd_pmu" "No action,Ultra low"
|
|
bitfld.long 0x04 9. " VDD_MEM_SET_EXTRA ,Extra high setting for vdd_mem" "No action,Extra"
|
|
bitfld.long 0x04 8. " VDD_PMU_SET_EXTRA ,Extra high setting for vdd_pmu" "No action,Extra"
|
|
newline
|
|
bitfld.long 0x04 6.--7. " VDD_MEM_SET ,Vdd_mem while wakeup" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " VDD_MEM_SET_PDM ,Vdd_mem while in power-down mode" "0,1,2,3"
|
|
bitfld.long 0x04 2.--3. " VDD_PMU_SET ,Vdd_pmu while wakeup" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x04 0.--1. " VDD_PMU_SET_PDM ,Vdd_pmu while in power down" "0,1,2,3"
|
|
group.long 0x890++0x03
|
|
line.long 0x00 "MISC,MISC Register"
|
|
bitfld.long 0x00 25. " DPPU_OPT_POL ,Drive high to swap pull up strength value" "0,1"
|
|
bitfld.long 0x00 24. " DPPU_OPT_SEL ,Pull-up strength source selection" "Register,USB controller"
|
|
bitfld.long 0x00 18. " DIS_USB_PULLUP ,Disconnects USB pull up resistor" "Dependable,Disconnected"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " RCO_PWR_MODE ,RCO VDD selection" "1.1V 630nA 250ppm,,0.95V 350nA 340ppm,0.82V 200nA 500ppm"
|
|
width 0x0B
|
|
tree.end
|
|
tree "NVIC (Nested Vectored Interrupt Control)"
|
|
base ad:0xE000E000
|
|
width 7.
|
|
group.long 0x100++0x07
|
|
line.long 0x00 "ISER0,Interrupt Set-Enable Register 0"
|
|
bitfld.long 0x00 31. " ISE_ADC ,ADC interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " ISE_WDT ,Watchdog timer interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 29. " ISE_CTIMER3 ,Standard counter/timer CTRIMER3 interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 28. " ISE_CTIMER2 ,Standard counter/timer CTRIMER2 interrupt enable" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 27. " ISE_CTIMER1 ,Standard counter/timer CTRIMER1 interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 26. " ISE_CTIMER0 ,Standard counter/timer CTRIMER0 interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 25. " ISE_QDEC1 ,Quadrature decoder QDEC1 interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 24. " ISE_QDEC0 ,Quadrature decoder QDEC0 interrupt enable" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " ISE_FSP ,FSP interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " ISE_BLE ,BLE interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 21. " ISE_FC3 ,Flexcomm interface 3 interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 20. " ISE_FC2 ,Flexcomm interface 2 interrupt enable" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 19. " ISE_FC1 ,Flexcomm interface 1 interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " ISE_FC0 ,Flexcomm interface 0 interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " ISE_USB ,USB device enable" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " ISE_OSC_INT_LOW ,BLE sleep interrupt enable" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " ISE_PIN_INT3 ,Pin interrupt/pattern match engine slice 3 interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " ISE_PIN_INT2 ,Pin interrupt/pattern match engine slice 2 interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 13. " ISE_PIN_INT1 ,Pin interrupt/pattern match engine slice 1 interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " ISE_PIN_INT0 ,Pin interrupt/pattern match engine slice 0 interrupt enable" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " ISE_DMA ,DMA interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " ISE_GPIOB ,GPIOB interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 9. " ISE_GPIOA ,GPIOA interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " ISE_CS ,Capacitive sense detection interrupt enable" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " ISE_CS_WAKEUP ,Capacitive sense wake up interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " ISE_RTC_FR ,RTC free running match interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 5. " ISE_RTC_SEC ,RTC second match interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 3. " ISE_ACMP1 ,Analog comparator 1 interrupt enable" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " ISE_ACMP0 ,Analog comparator 0 interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " ISE_OSC ,BLE oscillator wake up interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " ISE_EXTIO_WAKEUP ,External GPIO interrupt enable" "No effect,Enabled"
|
|
line.long 0x04 "ISER1,Interrupt Set-Enable Register 1"
|
|
bitfld.long 0x04 31. " ISE_BOD ,BOD interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x04 6. " ISE_RNG ,Random number generator interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x04 4. " ISE_SCT ,SCTimer/PWM interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x04 3. " ISE_SPIFI ,SPI flash controller interrupt enable" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " ISE_FLASH ,Flash controller interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x04 1. " ISE_XTAL_READY ,High frequency crystal ready interrupt enable" "No effect,Enabled"
|
|
bitfld.long 0x04 0. " ISE_DAC ,DAC interrupt enable" "No effect,Enabled"
|
|
group.long 0x180++0x07
|
|
line.long 0x00 "ICER0,Interrupt Clear-Enable Register 0"
|
|
bitfld.long 0x00 31. " ICE_ADC ,ADC interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 30. " ICE_WDT ,Watchdog timer interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 29. " ICE_CTIMER3 ,Standard counter/timer CTRIMER3 interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 28. " ICE_CTIMER2 ,Standard counter/timer CTRIMER2 interrupt disable" "No effect,Disabled"
|
|
newline
|
|
bitfld.long 0x00 27. " ICE_CTIMER1 ,Standard counter/timer CTRIMER1 interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 26. " ICE_CTIMER0 ,Standard counter/timer CTRIMER0 interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 25. " ICE_QDEC1 ,Quadrature decoder QDEC1 interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 24. " ICE_QDEC0 ,Quadrature decoder QDEC0 interrupt disable" "No effect,Disabled"
|
|
newline
|
|
bitfld.long 0x00 23. " ICE_FSP ,FSP interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 22. " ICE_BLE ,BLE interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 21. " ICE_FC3 ,Flexcomm interface 3 interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 20. " ICE_FC2 ,Flexcomm interface 2 interrupt disable" "No effect,Disabled"
|
|
newline
|
|
bitfld.long 0x00 19. " ICE_FC1 ,Flexcomm interface 1 interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 18. " ICE_FC0 ,Flexcomm interface 0 interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 17. " ICE_USB ,USB device disable" "No effect,Disabled"
|
|
bitfld.long 0x00 16. " ICE_OSC_INT_LOW ,BLE sleep interrupt disable" "No effect,Disabled"
|
|
newline
|
|
bitfld.long 0x00 15. " ICE_PIN_INT3 ,Pin interrupt/pattern match engine slice 3 interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 14. " ICE_PIN_INT2 ,Pin interrupt/pattern match engine slice 2 interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 13. " ICE_PIN_INT1 ,Pin interrupt/pattern match engine slice 1 interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 12. " ICE_PIN_INT0 ,Pin interrupt/pattern match engine slice 0 interrupt disable" "No effect,Disabled"
|
|
newline
|
|
bitfld.long 0x00 11. " ICE_DMA ,DMA interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 10. " ICE_GPIOB ,GPIOB interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 9. " ICE_GPIOA ,GPIOA interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 8. " ICE_CS ,Capacitive sense detection interrupt disable" "No effect,Disabled"
|
|
newline
|
|
bitfld.long 0x00 7. " ICE_CS_WAKEUP ,Capacitive sense wake up interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 6. " ICE_RTC_FR ,RTC free running match interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 5. " ICE_RTC_SEC ,RTC second match interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 3. " ICE_ACMP1 ,Analog comparator 1 interrupt disable" "No effect,Disabled"
|
|
newline
|
|
bitfld.long 0x00 2. " ICE_ACMP0 ,Analog comparator 0 interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 1. " ICE_OSC ,BLE oscillator wake up interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x00 0. " ICE_EXTIO_WAKEUP ,External GPIO interrupt disable" "No effect,Disabled"
|
|
line.long 0x04 "ICER1,Interrupt Clear-Enable Register 1"
|
|
bitfld.long 0x04 31. " ICE_BOD ,BOD interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x04 6. " ICE_RNG ,Random number generator interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x04 4. " ICE_SCT ,SCTimer/PWM interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x04 3. " ICE_SPIFI ,SPI flash controller interrupt disable" "No effect,Disabled"
|
|
newline
|
|
bitfld.long 0x04 2. " ICE_FLASH ,Flash controller interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x04 1. " ICE_XTAL_READY ,High frequency crystal ready interrupt disable" "No effect,Disabled"
|
|
bitfld.long 0x04 0. " ICE_DAC ,DAC interrupt disable" "No effect,Disabled"
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "ISPR0,Interrupt Set Pending Register 0"
|
|
bitfld.long 0x00 31. " ISP_ADC ,ADC interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 30. " ISP_WDT ,Watchdog timer interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 29. " ISP_CTIMER3 ,Standard counter/timer CTRIMER3 interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 28. " ISP_CTIMER2 ,Standard counter/timer CTRIMER2 interrupt pending set" "No effect,Pending"
|
|
newline
|
|
bitfld.long 0x00 27. " ISP_CTIMER1 ,Standard counter/timer CTRIMER1 interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 26. " ISP_CTIMER0 ,Standard counter/timer CTRIMER0 interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 25. " ISP_QDEC1 ,Quadrature decoder QDEC1 interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 24. " ISP_QDEC0 ,Quadrature decoder QDEC0 interrupt pending set" "No effect,Pending"
|
|
newline
|
|
bitfld.long 0x00 23. " ISP_FSP ,FSP interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 22. " ISP_BLE ,BLE interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 21. " ISP_FC3 ,Flexcomm interface 3 interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 20. " ISP_FC2 ,Flexcomm interface 2 interrupt pending set" "No effect,Pending"
|
|
newline
|
|
bitfld.long 0x00 19. " ISP_FC1 ,Flexcomm interface 1 interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 18. " ISP_FC0 ,Flexcomm interface 0 interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 17. " ISP_USB ,USB device pending set" "No effect,Pending"
|
|
bitfld.long 0x00 16. " ISP_OSC_INT_LOW ,BLE sleep interrupt pending set" "No effect,Pending"
|
|
newline
|
|
bitfld.long 0x00 15. " ISP_PIN_INT3 ,Pin interrupt/pattern match engine slice 3 interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 14. " ISP_PIN_INT2 ,Pin interrupt/pattern match engine slice 2 interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 13. " ISP_PIN_INT1 ,Pin interrupt/pattern match engine slice 1 interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 12. " ISP_PIN_INT0 ,Pin interrupt/pattern match engine slice 0 interrupt pending set" "No effect,Pending"
|
|
newline
|
|
bitfld.long 0x00 11. " ISP_DMA ,DMA interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 10. " ISP_GPIOB ,GPIOB interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 9. " ISP_GPIOA ,GPIOA interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 8. " ISP_CS ,Capacitive sense detection interrupt pending set" "No effect,Pending"
|
|
newline
|
|
bitfld.long 0x00 7. " ISP_CS_WAKEUP ,Capacitive sense wake up interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 6. " ISP_RTC_FR ,RTC free running match interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 5. " ISP_RTC_SEC ,RTC second match interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 3. " ISP_ACMP1 ,Analog comparator 1 interrupt pending set" "No effect,Pending"
|
|
newline
|
|
bitfld.long 0x00 2. " ISP_ACMP0 ,Analog comparator 0 interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 1. " ISP_OSC ,BLE oscillator wake up interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x00 0. " ISP_EXTIO_WAKEUP ,External GPIO interrupt pending set" "No effect,Pending"
|
|
line.long 0x04 "ISPR1,Interrupt Set Pending Register 1"
|
|
bitfld.long 0x04 31. " ISP_BOD ,BOD interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x04 6. " ISP_RNG ,Random number generator interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x04 4. " ISP_SCT ,SCTimer/PWM interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x04 3. " ISP_SPIFI ,SPI flash controller interrupt pending set" "No effect,Pending"
|
|
newline
|
|
bitfld.long 0x04 2. " ISP_FLASH ,Flash controller interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x04 1. " ISP_XTAL_READY ,High frequency crystal ready interrupt pending set" "No effect,Pending"
|
|
bitfld.long 0x04 0. " ISP_DAC ,DAC interrupt pending set" "No effect,Pending"
|
|
group.long 0x280++0x07
|
|
line.long 0x00 "ICPR0,Interrupt Clear Pending Register 0"
|
|
bitfld.long 0x00 31. " ICP_ADC ,ADC interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 30. " ICP_WDT ,Watchdog timer interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 29. " ICP_CTIMER3 ,Standard counter/timer CTRIMER3 interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 28. " ICP_CTIMER2 ,Standard counter/timer CTRIMER2 interrupt pending clear" "No effect,Not pending"
|
|
newline
|
|
bitfld.long 0x00 27. " ICP_CTIMER1 ,Standard counter/timer CTRIMER1 interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 26. " ICP_CTIMER0 ,Standard counter/timer CTRIMER0 interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 25. " ICP_QDEC1 ,Quadrature decoder QDEC1 interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 24. " ICP_QDEC0 ,Quadrature decoder QDEC0 interrupt pending clear" "No effect,Not pending"
|
|
newline
|
|
bitfld.long 0x00 23. " ICP_FSP ,FSP interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 22. " ICP_BLE ,BLE interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 21. " ICP_FC3 ,Flexcomm interface 3 interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 20. " ICP_FC2 ,Flexcomm interface 2 interrupt pending clear" "No effect,Not pending"
|
|
newline
|
|
bitfld.long 0x00 19. " ICP_FC1 ,Flexcomm interface 1 interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 18. " ICP_FC0 ,Flexcomm interface 0 interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 17. " ICP_USB ,USB device pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 16. " ICP_OSC_INT_LOW ,BLE sleep interrupt pending clear" "No effect,Not pending"
|
|
newline
|
|
bitfld.long 0x00 15. " ICP_PIN_INT3 ,Pin interrupt/pattern match engine slice 3 interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 14. " ICP_PIN_INT2 ,Pin interrupt/pattern match engine slice 2 interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 13. " ICP_PIN_INT1 ,Pin interrupt/pattern match engine slice 1 interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 12. " ICP_PIN_INT0 ,Pin interrupt/pattern match engine slice 0 interrupt pending clear" "No effect,Not pending"
|
|
newline
|
|
bitfld.long 0x00 11. " ICP_DMA ,DMA interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 10. " ICP_GPIOB ,GPIOB interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 9. " ICP_GPIOA ,GPIOA interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 8. " ICP_CS ,Capacitive sense detection interrupt pending clear" "No effect,Not pending"
|
|
newline
|
|
bitfld.long 0x00 7. " ICP_CS_WAKEUP ,Capacitive sense wake up interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 6. " ICP_RTC_FR ,RTC free running match interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 5. " ICP_RTC_SEC ,RTC second match interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 3. " ICP_ACMP1 ,Analog comparator 1 interrupt pending clear" "No effect,Not pending"
|
|
newline
|
|
bitfld.long 0x00 2. " ICP_ACMP0 ,Analog comparator 0 interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 1. " ICP_OSC ,BLE oscillator wake up interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x00 0. " ICP_EXTIO_WAKEUP ,External GPIO interrupt pending clear" "No effect,Not pending"
|
|
line.long 0x04 "ICPR1,Interrupt Clear Pending Register 1"
|
|
bitfld.long 0x04 31. " ICP_BOD ,BOD interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x04 6. " ICP_RNG ,Random number generator interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x04 4. " ICP_SCT ,SCTimer/PWM interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x04 3. " ICP_SPIFI ,SPI flash controller interrupt pending clear" "No effect,Not pending"
|
|
newline
|
|
bitfld.long 0x04 2. " ICP_FLASH ,Flash controller interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x04 1. " ICP_XTAL_READY ,High frequency crystal ready interrupt pending clear" "No effect,Not pending"
|
|
bitfld.long 0x04 0. " ICP_DAC ,DAC interrupt pending clear" "No effect,Not pending"
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "IABR0,Interrupt Active Bit Register 0"
|
|
bitfld.long 0x00 31. " IAB_ADC ,ADC interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 30. " IAB_WDT ,Watchdog timer interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 29. " IAB_CTIMER3 ,Standard counter/timer CTRIMER3 interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 28. " IAB_CTIMER2 ,Standard counter/timer CTRIMER2 interrupt active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 27. " IAB_CTIMER1 ,Standard counter/timer CTRIMER1 interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 26. " IAB_CTIMER0 ,Standard counter/timer CTRIMER0 interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 25. " IAB_QDEC1 ,Quadrature decoder QDEC1 interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 24. " IAB_QDEC0 ,Quadrature decoder QDEC0 interrupt active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 23. " IAB_FSP ,FSP interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 22. " IAB_BLE ,BLE interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 21. " IAB_FC3 ,Flexcomm interface 3 interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 20. " IAB_FC2 ,Flexcomm interface 2 interrupt active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 19. " IAB_FC1 ,Flexcomm interface 1 interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 18. " IAB_FC0 ,Flexcomm interface 0 interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 17. " IAB_USB ,USB device enable" "Not active,Active"
|
|
bitfld.long 0x00 16. " IAB_OSC_INT_LOW ,BLE sleep interrupt active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 15. " IAB_PIN_INT3 ,Pin interrupt/pattern match engine slice 3 interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 14. " IAB_PIN_INT2 ,Pin interrupt/pattern match engine slice 2 interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 13. " IAB_PIN_INT1 ,Pin interrupt/pattern match engine slice 1 interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 12. " IAB_PIN_INT0 ,Pin interrupt/pattern match engine slice 0 interrupt active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 11. " IAB_DMA ,DMA interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 10. " IAB_GPIOB ,GPIOB interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 9. " IAB_GPIOA ,GPIOA interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 8. " IAB_CS ,Capacitive sense detection interrupt active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " IAB_CS_WAKEUP ,Capacitive sense wake up interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 6. " IAB_RTC_FR ,RTC free running match interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 5. " IAB_RTC_SEC ,RTC second match interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 3. " IAB_ACMP1 ,Analog comparator 1 interrupt active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 2. " IAB_ACMP0 ,Analog comparator 0 interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 1. " IAB_OSC ,BLE oscillator wake up interrupt active" "Not active,Active"
|
|
bitfld.long 0x00 0. " IAB_EXTIO_WAKEUP ,External GPIO interrupt active" "Not active,Active"
|
|
line.long 0x04 "IABR1,Interrupt Active Bit Register 1"
|
|
bitfld.long 0x04 31. " IAB_BOD ,BOD interrupt active" "Not active,Active"
|
|
bitfld.long 0x04 6. " IAB_RNG ,Random number generator interrupt active" "Not active,Active"
|
|
bitfld.long 0x04 4. " IAB_SCT ,SCTimer/PWM interrupt active" "Not active,Active"
|
|
bitfld.long 0x04 3. " IAB_SPIFI ,SPI flash controller interrupt active" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x04 2. " IAB_FLASH ,Flash controller interrupt active" "Not active,Active"
|
|
bitfld.long 0x04 1. " IAB_XTAL_READY ,High frequency crystal ready interrupt active" "Not active,Active"
|
|
bitfld.long 0x04 0. " IAB_DAC ,DAC interrupt active" "Not active,Active"
|
|
group.long 0x400++0x33
|
|
line.long 0x00 "IPR0,Interrupt Priority Register 0"
|
|
bitfld.long 0x00 29.--31. " IP_ACMP1 ,ACMP1 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21.--23. " IP_ACMP0 ,ACMP0 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 13.--15. " IP_OSC ,BLE oscillator interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5.--7. " IP_EXTIO_WAKEUP ,External IO wake up interrupt priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "IPR1,Interrupt Priority Register 1"
|
|
bitfld.long 0x04 29.--31. " IP_CS_WAKEUP ,Cap sense sleep wake up interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 21.--23. " IP_RTC_FR ,RTC free running interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 13.--15. " IP_RTC_SEC ,RTC second interrupt priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "IPR2,Interrupt Priority Register 2"
|
|
bitfld.long 0x08 29.--31. " IP_DMA ,DMA interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 21.--23. " IP_GPIOB ,GPIOB interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 13.--15. " IP_GPIOA ,GPIOA oscillator interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x08 5.--7. " IP_CS ,Cap sense interrupt priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "IPR3,Interrupt Priority Register 3"
|
|
bitfld.long 0x0C 29.--31. " IP_PIN_INT3 ,Pin interrupt/pattern match engine slice 3 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 21.--23. " IP_PIN_INT2 ,Pin interrupt/pattern match engine slice 2 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 13.--15. " IP_PIN_INT1 ,Pin interrupt/pattern match engine slice 1 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0C 5.--7. " IP_PIN_INT0 ,Pin interrupt/pattern match engine slice 0 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register 4"
|
|
bitfld.long 0x10 29.--31. " IP_FC1 ,Flexcomm interface 1 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 21.--23. " IP_FC0 ,Flexcomm interface 0 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 13.--15. " IP_USB ,USB interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 5.--7. " IP_OSC_INT_LOW ,Interrupt priority of inverse of BLE_WAKEUP" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register 5"
|
|
bitfld.long 0x14 29.--31. " IP_FSP ,FSP interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 21.--23. " IP_BLE ,All BLE interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 13.--15. " IP_FC3 ,Flexcomm interface 3 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 5.--7. " IP_FC2 ,Flexcomm interface 2 Interrupt priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register 6"
|
|
bitfld.long 0x18 29.--31. " IP_CTIMER1 ,Standard counter/timer CTIMER1 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 21.--23. " IP_CTIMER0 ,Standard counter/timer CTIMER0 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 13.--15. " IP_QDEC1 ,QDEC1 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x18 5.--7. " IP_QDEC0 ,QDEC0 Interrupt priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register 7"
|
|
bitfld.long 0x1C 29.--31. " IP_ADC ,ADC interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x1C 21.--23. " IP_WDT ,WDT interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x1C 13.--15. " IP_CTIMER3 ,Standard counter/timer CTIMER3 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x1C 5.--7. " IP_CTIMER2 ,Standard counter/timer CTIMER2 interrupt priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register 8"
|
|
bitfld.long 0x20 29.--31. " IP_SPIFI ,SPI flash interface interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x20 21.--23. " IP_FLASH ,Embedded flash interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x20 13.--15. " IP_XTAL_READY ,High frequency crystal ready interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x20 5.--7. " IP_DAC ,DAC interrupt priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register 9"
|
|
bitfld.long 0x24 21.--23. " IP_RNG ,RNG interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x24 5.--7. " IP_SCT ,SCT interrupt priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register 10"
|
|
bitfld.long 0x28 29.--31. " IP_BLE_RX ,BLE RX interrupt priority" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x28 21.--23. " IP_BLE_TX ,BLE TX interrupt priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register 11"
|
|
bitfld.long 0x2C 5.--7. " IP_BLE_FREQ_HOP ,BLE frequency interrupt priority" "0,1,2,3,4,5,6,7"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register 12"
|
|
bitfld.long 0x30 29.--31. " IP_BOD ,BOD interrupt priority" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " INTID ,Generates an interrupt for the specified the interrupt number"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Input MUX (Input Multiplexing)"
|
|
base ad:0x40006200
|
|
width 19.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PINTSEL0,Pin Interrupt Select Register 0"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PA00,PA01,,,PA04,PA05,PA06,PA07,PA08,PA09,PA10,PA11,,,PA14,PA15,PA16,PA17,PA18,PA19,,,PA22,PA23,PA24,PA25,PA26,PA27,,PA29,PA30,PA31"
|
|
else
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PA00,PA01,PA02,PA03,PA04,PA05,PA06,PA07,PA08,PA09,PA10,PA11,PA12,PA13,PA14,PA15,PA16,PA17,PA18,PA19,PA20,PA21,PA22,PA23,PA24,PA25,PA26,PA27,PA28,PA29,PA30,PA31"
|
|
endif
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PINTSEL1,Pin Interrupt Select Register 1"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PA00,PA01,,,PA04,PA05,PA06,PA07,PA08,PA09,PA10,PA11,,,PA14,PA15,PA16,PA17,PA18,PA19,,,PA22,PA23,PA24,PA25,PA26,PA27,,PA29,PA30,PA31"
|
|
else
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PA00,PA01,PA02,PA03,PA04,PA05,PA06,PA07,PA08,PA09,PA10,PA11,PA12,PA13,PA14,PA15,PA16,PA17,PA18,PA19,PA20,PA21,PA22,PA23,PA24,PA25,PA26,PA27,PA28,PA29,PA30,PA31"
|
|
endif
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "PINTSEL2,Pin Interrupt Select Register 2"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PA00,PA01,,,PA04,PA05,PA06,PA07,PA08,PA09,PA10,PA11,,,PA14,PA15,PA16,PA17,PA18,PA19,,,PA22,PA23,PA24,PA25,PA26,PA27,,PA29,PA30,PA31"
|
|
else
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PA00,PA01,PA02,PA03,PA04,PA05,PA06,PA07,PA08,PA09,PA10,PA11,PA12,PA13,PA14,PA15,PA16,PA17,PA18,PA19,PA20,PA21,PA22,PA23,PA24,PA25,PA26,PA27,PA28,PA29,PA30,PA31"
|
|
endif
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PINTSEL3,Pin Interrupt Select Register 3"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PA00,PA01,,,PA04,PA05,PA06,PA07,PA08,PA09,PA10,PA11,,,PA14,PA15,PA16,PA17,PA18,PA19,,,PA22,PA23,PA24,PA25,PA26,PA27,,PA29,PA30,PA31"
|
|
else
|
|
bitfld.long 0x00 0.--4. " INTPIN ,Pin number select for pin interrupt or pattern match engine input" "PA00,PA01,PA02,PA03,PA04,PA05,PA06,PA07,PA08,PA09,PA10,PA11,PA12,PA13,PA14,PA15,PA16,PA17,PA18,PA19,PA20,PA21,PA22,PA23,PA24,PA25,PA26,PA27,PA28,PA29,PA30,PA31"
|
|
endif
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX0 ,Trigger Select Register For DMA Channel 0 "
|
|
bitfld.long 0x00 0.--4. " INP0 ,Trigger input number for DMA channel 0 " "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX1 ,Trigger Select Register For DMA Channel 1 "
|
|
bitfld.long 0x00 0.--4. " INP1 ,Trigger input number for DMA channel 1 " "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX2 ,Trigger Select Register For DMA Channel 2 "
|
|
bitfld.long 0x00 0.--4. " INP2 ,Trigger input number for DMA channel 2 " "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX3 ,Trigger Select Register For DMA Channel 3 "
|
|
bitfld.long 0x00 0.--4. " INP3 ,Trigger input number for DMA channel 3 " "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX4 ,Trigger Select Register For DMA Channel 4 "
|
|
bitfld.long 0x00 0.--4. " INP4 ,Trigger input number for DMA channel 4 " "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX5 ,Trigger Select Register For DMA Channel 5 "
|
|
bitfld.long 0x00 0.--4. " INP5 ,Trigger input number for DMA channel 5 " "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX6 ,Trigger Select Register For DMA Channel 6 "
|
|
bitfld.long 0x00 0.--4. " INP6 ,Trigger input number for DMA channel 6 " "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX7 ,Trigger Select Register For DMA Channel 7 "
|
|
bitfld.long 0x00 0.--4. " INP7 ,Trigger input number for DMA channel 7 " "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX8 ,Trigger Select Register For DMA Channel 8 "
|
|
bitfld.long 0x00 0.--4. " INP8 ,Trigger input number for DMA channel 8 " "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX9 ,Trigger Select Register For DMA Channel 9 "
|
|
bitfld.long 0x00 0.--4. " INP9 ,Trigger input number for DMA channel 9 " "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX10,Trigger Select Register For DMA Channel 10"
|
|
bitfld.long 0x00 0.--4. " INP10 ,Trigger input number for DMA channel 10" "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX11,Trigger Select Register For DMA Channel 11"
|
|
bitfld.long 0x00 0.--4. " INP11 ,Trigger input number for DMA channel 11" "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX12,Trigger Select Register For DMA Channel 12"
|
|
bitfld.long 0x00 0.--4. " INP12 ,Trigger input number for DMA channel 12" "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX13,Trigger Select Register For DMA Channel 13"
|
|
bitfld.long 0x00 0.--4. " INP13 ,Trigger input number for DMA channel 13" "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX14,Trigger Select Register For DMA Channel 14"
|
|
bitfld.long 0x00 0.--4. " INP14 ,Trigger input number for DMA channel 14" "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX15,Trigger Select Register For DMA Channel 15"
|
|
bitfld.long 0x00 0.--4. " INP15 ,Trigger input number for DMA channel 15" "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX16,Trigger Select Register For DMA Channel 16"
|
|
bitfld.long 0x00 0.--4. " INP16 ,Trigger input number for DMA channel 16" "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX17,Trigger Select Register For DMA Channel 17"
|
|
bitfld.long 0x00 0.--4. " INP17 ,Trigger input number for DMA channel 17" "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX18,Trigger Select Register For DMA Channel 18"
|
|
bitfld.long 0x00 0.--4. " INP18 ,Trigger input number for DMA channel 18" "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "DMA_ITRIG_INMUX19,Trigger Select Register For DMA Channel 19"
|
|
bitfld.long 0x00 0.--4. " INP19 ,Trigger input number for DMA channel 19" "FSP DMA request,RTC second trigger,SCT0 DMA request 0,SCT0 DMA request 1,CTIMER0 match 0,CTIMER0 match 1,CTIMER1 match 0,CTIMER1 match 1,CTIMER2 match 0,CTIMER2 match 1,CTIMER3 match 0,CTIMER3 match 1,Pin interrupt 0,Pin interrupt 1,Pin interrupt 2,Pin interrupt 3,DMA output trigger MUX 0,DMA output trigger MUX 1,DMA output trigger MUX 2,DMA output trigger MUX 3,?..."
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "DMA_OTRIG_INMUX0,DMA Output trigger Feedback MUX Register 0"
|
|
bitfld.long 0x00 0.--4. " INP0 ,DMA output trigger selection to become DMA trigger 16" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "DMA_OTRIG_INMUX1,DMA Output trigger Feedback MUX Register 1"
|
|
bitfld.long 0x00 0.--4. " INP1 ,DMA output trigger selection to become DMA trigger 17" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "DMA_OTRIG_INMUX2,DMA Output trigger Feedback MUX Register 2"
|
|
bitfld.long 0x00 0.--4. " INP2 ,DMA output trigger selection to become DMA trigger 18" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "DMA_OTRIG_INMUX3,DMA Output trigger Feedback MUX Register 3"
|
|
bitfld.long 0x00 0.--4. " INP3 ,DMA output trigger selection to become DMA trigger 19" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "GPIO (General Purpose I/O)"
|
|
tree "GPIOA"
|
|
base ad:0x4008C000
|
|
width 15.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DATA,GPIOA Register Value"
|
|
bitfld.long 0x00 31. " DATA[31] ,Data value on PA31" "0,1"
|
|
bitfld.long 0x00 30. " [30] ,Data value on PA30" "0,1"
|
|
bitfld.long 0x00 29. " [29] ,Data value on PA29" "0,1"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 28. " [28] ,Data value on PA28" "0,1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Data value on PA27" "0,1"
|
|
bitfld.long 0x00 26. " [26] ,Data value on PA26" "0,1"
|
|
bitfld.long 0x00 25. " [25] ,Data value on PA25" "0,1"
|
|
bitfld.long 0x00 24. " [24] ,Data value on PA24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Data value on PA23" "0,1"
|
|
bitfld.long 0x00 22. " [22] ,Data value on PA22" "0,1"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 21. " [21] ,Data value on PA21" "0,1"
|
|
bitfld.long 0x00 20. " [20] ,Data value on PA20" "0,1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Data value on PA19" "0,1"
|
|
bitfld.long 0x00 18. " [18] ,Data value on PA18" "0,1"
|
|
bitfld.long 0x00 17. " [17] ,Data value on PA17" "0,1"
|
|
bitfld.long 0x00 16. " [16] ,Data value on PA16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Data value on PA15" "0,1"
|
|
bitfld.long 0x00 14. " [14] ,Data value on PA14" "0,1"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 13. " [13] ,Data value on PA13" "0,1"
|
|
bitfld.long 0x00 12. " [12] ,Data value on PA12" "0,1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Data value on PA11" "0,1"
|
|
bitfld.long 0x00 10. " [10] ,Data value on PA10" "0,1"
|
|
bitfld.long 0x00 9. " [9] ,Data value on PA09" "0,1"
|
|
bitfld.long 0x00 8. " [8] ,Data value on PA08" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Data value on PA07" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,Data value on PA06" "0,1"
|
|
bitfld.long 0x00 5. " [5] ,Data value on PA05" "0,1"
|
|
bitfld.long 0x00 4. " [4] ,Data value on PA04" "0,1"
|
|
newline
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 3. " [3] ,Data value on PA03" "0,1"
|
|
bitfld.long 0x00 2. " [2] ,Data value on PA02" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,Data value on PA01" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,Data value on PA00" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DATAOUT,GPIOA Output Status Register"
|
|
bitfld.long 0x00 31. " DATAOUT[31] ,Data output register value bit 31" "0,1"
|
|
bitfld.long 0x00 30. " [30] ,Data output register value bit 30" "0,1"
|
|
bitfld.long 0x00 29. " [29] ,Data output register value bit 29" "0,1"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 28. " [28] ,Data output register value bit 28" "0,1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Data output register value bit 27" "0,1"
|
|
bitfld.long 0x00 26. " [26] ,Data output register value bit 26" "0,1"
|
|
bitfld.long 0x00 25. " [25] ,Data output register value bit 25" "0,1"
|
|
bitfld.long 0x00 24. " [24] ,Data output register value bit 24" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Data output register value bit 23" "0,1"
|
|
bitfld.long 0x00 22. " [22] ,Data output register value bit 22" "0,1"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 21. " [21] ,Data output register value bit 21" "0,1"
|
|
bitfld.long 0x00 20. " [20] ,Data output register value bit 20" "0,1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Data output register value bit 19" "0,1"
|
|
bitfld.long 0x00 18. " [18] ,Data output register value bit 18" "0,1"
|
|
bitfld.long 0x00 17. " [17] ,Data output register value bit 17" "0,1"
|
|
bitfld.long 0x00 16. " [16] ,Data output register value bit 16" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Data output register value bit 15" "0,1"
|
|
bitfld.long 0x00 14. " [14] ,Data output register value bit 14" "0,1"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 13. " [13] ,Data output register value bit 13" "0,1"
|
|
bitfld.long 0x00 12. " [12] ,Data output register value bit 12" "0,1"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Data output register value bit 11" "0,1"
|
|
bitfld.long 0x00 10. " [10] ,Data output register value bit 10" "0,1"
|
|
bitfld.long 0x00 9. " [9] ,Data output register value bit 9" "0,1"
|
|
bitfld.long 0x00 8. " [8] ,Data output register value bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Data output register value bit 7" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,Data output register value bit 6" "0,1"
|
|
bitfld.long 0x00 5. " [5] ,Data output register value bit 5" "0,1"
|
|
bitfld.long 0x00 4. " [4] ,Data output register value bit 4" "0,1"
|
|
newline
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 3. " [3] ,Data output register value bit 3" "0,1"
|
|
bitfld.long 0x00 2. " [2] ,Data output register value bit 2" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,Data output register value bit 1" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,Data output register value bit 0" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "OUTEN_SET/CLR,GPIOA Output Set/Clear Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " OUTEN[31] ,Port A pin 31 data output bit" "Low,High"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Port A pin 30 data output bit" "Low,High"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Port A pin 29 data output bit" "Low,High"
|
|
sif !cpuis("QN9083DUK")
|
|
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Port A pin 28 data output bit" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Port A pin 27 data output bit" "Low,High"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Port A pin 26 data output bit" "Low,High"
|
|
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Port A pin 25 data output bit" "Low,High"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Port A pin 24 data output bit" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Port A pin 23 data output bit" "Low,High"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Port A pin 22 data output bit" "Low,High"
|
|
sif !cpuis("QN9083DUK")
|
|
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Port A pin 21 data output bit" "Low,High"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Port A pin 20 data output bit" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Port A pin 19 data output bit" "Low,High"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Port A pin 18 data output bit" "Low,High"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Port A pin 17 data output bit" "Low,High"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Port A pin 16 data output bit" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Port A pin 15 data output bit" "Low,High"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Port A pin 14 data output bit" "Low,High"
|
|
sif !cpuis("QN9083DUK")
|
|
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Port A pin 13 data output bit" "Low,High"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Port A pin 12 data output bit" "Low,High"
|
|
endif
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Port A pin 11 data output bit" "Low,High"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Port A pin 10 data output bit" "Low,High"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Port A pin 9 data output bit" "Low,High"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Port A pin 8 data output bit" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Port A pin 7 data output bit" "Low,High"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Port A pin 6 data output bit" "Low,High"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Port A pin 5 data output bit" "Low,High"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Port A pin 4 data output bit" "Low,High"
|
|
newline
|
|
sif !cpuis("QN9083DUK")
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Port A pin 3 data output bit" "Low,High"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Port A pin 2 data output bit" "Low,High"
|
|
newline
|
|
endif
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Port A pin 1 data output bit" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Port A pin 0 data output bit" "Low,High"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INTENSET,GPIOA Interrupt Enable Set Register"
|
|
bitfld.long 0x00 31. " INTENSET[31] ,Interrupt enable set on PA31" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Interrupt enable set on PA30" "No effect,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Interrupt enable set on PA29" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 28. " [28] ,Interrupt enable set on PA28" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Interrupt enable set on PA27" "No effect,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Interrupt enable set on PA26" "No effect,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Interrupt enable set on PA25" "No effect,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Interrupt enable set on PA24" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Interrupt enable set on PA23" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Interrupt enable set on PA22" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 21. " [21] ,Interrupt enable set on PA21" "No effect,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Interrupt enable set on PA20" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Interrupt enable set on PA19" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Interrupt enable set on PA18" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Interrupt enable set on PA17" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Interrupt enable set on PA16" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Interrupt enable set on PA15" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt enable set on PA14" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 13. " [13] ,Interrupt enable set on PA13" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt enable set on PA12" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Interrupt enable set on PA11" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt enable set on PA10" "No effect,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Interrupt enable set on PA09" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt enable set on PA08" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Interrupt enable set on PA07" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt enable set on PA06" "No effect,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt enable set on PA05" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt enable set on PA04" "No effect,Enabled"
|
|
newline
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 3. " [3] ,Interrupt enable set on PA03" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt enable set on PA02" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,Interrupt enable set on PA01" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt enable set on PA00" "No effect,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INTENCLR,GPIOA Port Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " INTENCLR[31] ,Interrupt enable clear on PA31" "No effect,Enabled"
|
|
eventfld.long 0x00 30. " [30] ,Interrupt enable clear on PA30" "No effect,Enabled"
|
|
eventfld.long 0x00 29. " [29] ,Interrupt enable clear on PA29" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x00 28. " [28] ,Interrupt enable clear on PA28" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Interrupt enable clear on PA27" "No effect,Enabled"
|
|
eventfld.long 0x00 26. " [26] ,Interrupt enable clear on PA26" "No effect,Enabled"
|
|
eventfld.long 0x00 25. " [25] ,Interrupt enable clear on PA25" "No effect,Enabled"
|
|
eventfld.long 0x00 24. " [24] ,Interrupt enable clear on PA24" "No effect,Enabled"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Interrupt enable clear on PA23" "No effect,Enabled"
|
|
eventfld.long 0x00 22. " [22] ,Interrupt enable clear on PA22" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x00 21. " [21] ,Interrupt enable clear on PA21" "No effect,Enabled"
|
|
eventfld.long 0x00 20. " [20] ,Interrupt enable clear on PA20" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Interrupt enable clear on PA19" "No effect,Enabled"
|
|
eventfld.long 0x00 18. " [18] ,Interrupt enable clear on PA18" "No effect,Enabled"
|
|
eventfld.long 0x00 17. " [17] ,Interrupt enable clear on PA17" "No effect,Enabled"
|
|
eventfld.long 0x00 16. " [16] ,Interrupt enable clear on PA16" "No effect,Enabled"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Interrupt enable clear on PA15" "No effect,Enabled"
|
|
eventfld.long 0x00 14. " [14] ,Interrupt enable clear on PA14" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x00 13. " [13] ,Interrupt enable clear on PA13" "No effect,Enabled"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt enable clear on PA12" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Interrupt enable clear on PA11" "No effect,Enabled"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt enable clear on PA10" "No effect,Enabled"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt enable clear on PA09" "No effect,Enabled"
|
|
eventfld.long 0x00 8. " [8] ,Interrupt enable clear on PA08" "No effect,Enabled"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Interrupt enable clear on PA07" "No effect,Enabled"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt enable clear on PA06" "No effect,Enabled"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt enable clear on PA05" "No effect,Enabled"
|
|
eventfld.long 0x00 4. " [4] ,Interrupt enable clear on PA04" "No effect,Enabled"
|
|
newline
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x00 3. " [3] ,Interrupt enable clear on PA03" "No effect,Enabled"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt enable clear on PA02" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 1. " [1] ,Interrupt enable clear on PA01" "No effect,Enabled"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt enable clear on PA00" "No effect,Enabled"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INTTYPESET,GPIOA Interrupt Type Set Register"
|
|
bitfld.long 0x00 31. " INTTYPESET[31] ,Interrupt type set on PA31" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Interrupt type set on PA30" "No effect,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Interrupt type set on PA29" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 28. " [28] ,Interrupt type set on PA28" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Interrupt type set on PA27" "No effect,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Interrupt type set on PA26" "No effect,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Interrupt type set on PA25" "No effect,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Interrupt type set on PA24" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Interrupt type set on PA23" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Interrupt type set on PA22" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 21. " [21] ,Interrupt type set on PA21" "No effect,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Interrupt type set on PA20" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Interrupt type set on PA19" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Interrupt type set on PA18" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Interrupt type set on PA17" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Interrupt type set on PA16" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Interrupt type set on PA15" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt type set on PA14" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 13. " [13] ,Interrupt type set on PA13" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt type set on PA12" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Interrupt type set on PA11" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt type set on PA10" "No effect,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Interrupt type set on PA09" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt type set on PA08" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Interrupt type set on PA07" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt type set on PA06" "No effect,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt type set on PA05" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt type set on PA04" "No effect,Enabled"
|
|
newline
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 3. " [3] ,Interrupt type set on PA03" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt type set on PA02" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,Interrupt type set on PA01" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt type set on PA00" "No effect,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTTYPECLR,GPIOA Interrupt Type Clear Register"
|
|
eventfld.long 0x00 31. " INTTYPECLR[31] ,Interrupt type clear on PA31" "No effect,Enabled"
|
|
eventfld.long 0x00 30. " [30] ,Interrupt type clear on PA30" "No effect,Enabled"
|
|
eventfld.long 0x00 29. " [29] ,Interrupt type clear on PA29" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x00 28. " [28] ,Interrupt type clear on PA28" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Interrupt type clear on PA27" "No effect,Enabled"
|
|
eventfld.long 0x00 26. " [26] ,Interrupt type clear on PA26" "No effect,Enabled"
|
|
eventfld.long 0x00 25. " [25] ,Interrupt type clear on PA25" "No effect,Enabled"
|
|
eventfld.long 0x00 24. " [24] ,Interrupt type clear on PA24" "No effect,Enabled"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Interrupt type clear on PA23" "No effect,Enabled"
|
|
eventfld.long 0x00 22. " [22] ,Interrupt type clear on PA22" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x00 21. " [21] ,Interrupt type clear on PA21" "No effect,Enabled"
|
|
eventfld.long 0x00 20. " [20] ,Interrupt type clear on PA20" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Interrupt type clear on PA19" "No effect,Enabled"
|
|
eventfld.long 0x00 18. " [18] ,Interrupt type clear on PA18" "No effect,Enabled"
|
|
eventfld.long 0x00 17. " [17] ,Interrupt type clear on PA17" "No effect,Enabled"
|
|
eventfld.long 0x00 16. " [16] ,Interrupt type clear on PA16" "No effect,Enabled"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Interrupt type clear on PA15" "No effect,Enabled"
|
|
eventfld.long 0x00 14. " [14] ,Interrupt type clear on PA14" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x00 13. " [13] ,Interrupt type clear on PA13" "No effect,Enabled"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt type clear on PA12" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Interrupt type clear on PA11" "No effect,Enabled"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt type clear on PA10" "No effect,Enabled"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt type clear on PA09" "No effect,Enabled"
|
|
eventfld.long 0x00 8. " [8] ,Interrupt type clear on PA08" "No effect,Enabled"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Interrupt type clear on PA07" "No effect,Enabled"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt type clear on PA06" "No effect,Enabled"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt type clear on PA05" "No effect,Enabled"
|
|
eventfld.long 0x00 4. " [4] ,Interrupt type clear on PA04" "No effect,Enabled"
|
|
newline
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x00 3. " [3] ,Interrupt type clear on PA03" "No effect,Enabled"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt type clear on PA02" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 1. " [1] ,Interrupt type clear on PA01" "No effect,Enabled"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt type clear on PA00" "No effect,Enabled"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "INTPOLSET,GPIOA Interrupt Polarity Set Register"
|
|
bitfld.long 0x00 31. " INTPOLSET[31] ,Polarity-level/Edge IRQ configuration on PA31" "No effect,Enabled"
|
|
bitfld.long 0x00 30. " [30] ,Polarity-level/Edge IRQ configuration on PA30" "No effect,Enabled"
|
|
bitfld.long 0x00 29. " [29] ,Polarity-level/Edge IRQ configuration on PA29" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 28. " [28] ,Polarity-level/Edge IRQ configuration on PA28" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Polarity-level/Edge IRQ configuration on PA27" "No effect,Enabled"
|
|
bitfld.long 0x00 26. " [26] ,Polarity-level/Edge IRQ configuration on PA26" "No effect,Enabled"
|
|
bitfld.long 0x00 25. " [25] ,Polarity-level/Edge IRQ configuration on PA25" "No effect,Enabled"
|
|
bitfld.long 0x00 24. " [24] ,Polarity-level/Edge IRQ configuration on PA24" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Polarity-level/Edge IRQ configuration on PA23" "No effect,Enabled"
|
|
bitfld.long 0x00 22. " [22] ,Polarity-level/Edge IRQ configuration on PA22" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 21. " [21] ,Polarity-level/Edge IRQ configuration on PA21" "No effect,Enabled"
|
|
bitfld.long 0x00 20. " [20] ,Polarity-level/Edge IRQ configuration on PA20" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Polarity-level/Edge IRQ configuration on PA19" "No effect,Enabled"
|
|
bitfld.long 0x00 18. " [18] ,Polarity-level/Edge IRQ configuration on PA18" "No effect,Enabled"
|
|
bitfld.long 0x00 17. " [17] ,Polarity-level/Edge IRQ configuration on PA17" "No effect,Enabled"
|
|
bitfld.long 0x00 16. " [16] ,Polarity-level/Edge IRQ configuration on PA16" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Polarity-level/Edge IRQ configuration on PA15" "No effect,Enabled"
|
|
bitfld.long 0x00 14. " [14] ,Polarity-level/Edge IRQ configuration on PA14" "No effect,Enabled"
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 13. " [13] ,Polarity-level/Edge IRQ configuration on PA13" "No effect,Enabled"
|
|
bitfld.long 0x00 12. " [12] ,Polarity-level/Edge IRQ configuration on PA12" "No effect,Enabled"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Polarity-level/Edge IRQ configuration on PA11" "No effect,Enabled"
|
|
bitfld.long 0x00 10. " [10] ,Polarity-level/Edge IRQ configuration on PA10" "No effect,Enabled"
|
|
bitfld.long 0x00 9. " [9] ,Polarity-level/Edge IRQ configuration on PA09" "No effect,Enabled"
|
|
bitfld.long 0x00 8. " [8] ,Polarity-level/Edge IRQ configuration on PA08" "No effect,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Polarity-level/Edge IRQ configuration on PA07" "No effect,Enabled"
|
|
bitfld.long 0x00 6. " [6] ,Polarity-level/Edge IRQ configuration on PA06" "No effect,Enabled"
|
|
bitfld.long 0x00 5. " [5] ,Polarity-level/Edge IRQ configuration on PA05" "No effect,Enabled"
|
|
bitfld.long 0x00 4. " [4] ,Polarity-level/Edge IRQ configuration on PA04" "No effect,Enabled"
|
|
newline
|
|
sif !cpuis("QN9083DUK")
|
|
bitfld.long 0x00 3. " [3] ,Polarity-level/Edge IRQ configuration on PA03" "No effect,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Polarity-level/Edge IRQ configuration on PA02" "No effect,Enabled"
|
|
newline
|
|
endif
|
|
bitfld.long 0x00 1. " [1] ,Polarity-level/Edge IRQ configuration on PA01" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Polarity-level/Edge IRQ configuration on PA00" "No effect,Enabled"
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "INTPOLCLR,GPIOA Interrupt Polarity Set Register"
|
|
eventfld.long 0x00 31. " INTPOLCLR[31] ,Interrupt polarity clear on PA31" "No effect,Cleared"
|
|
eventfld.long 0x00 30. " [30] ,Interrupt polarity clear on PA30" "No effect,Cleared"
|
|
eventfld.long 0x00 29. " [29] ,Interrupt polarity clear on PA29" "No effect,Cleared"
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x00 28. " [28] ,Interrupt polarity clear on PA28" "No effect,Cleared"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 27. " [27] ,Interrupt polarity clear on PA27" "No effect,Cleared"
|
|
eventfld.long 0x00 26. " [26] ,Interrupt polarity clear on PA26" "No effect,Cleared"
|
|
eventfld.long 0x00 25. " [25] ,Interrupt polarity clear on PA25" "No effect,Cleared"
|
|
eventfld.long 0x00 24. " [24] ,Interrupt polarity clear on PA24" "No effect,Cleared"
|
|
newline
|
|
eventfld.long 0x00 23. " [23] ,Interrupt polarity clear on PA23" "No effect,Cleared"
|
|
eventfld.long 0x00 22. " [22] ,Interrupt polarity clear on PA22" "No effect,Cleared"
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x00 21. " [21] ,Interrupt polarity clear on PA21" "No effect,Cleared"
|
|
eventfld.long 0x00 20. " [20] ,Interrupt polarity clear on PA20" "No effect,Cleared"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 19. " [19] ,Interrupt polarity clear on PA19" "No effect,Cleared"
|
|
eventfld.long 0x00 18. " [18] ,Interrupt polarity clear on PA18" "No effect,Cleared"
|
|
eventfld.long 0x00 17. " [17] ,Interrupt polarity clear on PA17" "No effect,Cleared"
|
|
eventfld.long 0x00 16. " [16] ,Interrupt polarity clear on PA16" "No effect,Cleared"
|
|
newline
|
|
eventfld.long 0x00 15. " [15] ,Interrupt polarity clear on PA15" "No effect,Cleared"
|
|
eventfld.long 0x00 14. " [14] ,Interrupt polarity clear on PA14" "No effect,Cleared"
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x00 13. " [13] ,Interrupt polarity clear on PA13" "No effect,Cleared"
|
|
eventfld.long 0x00 12. " [12] ,Interrupt polarity clear on PA12" "No effect,Cleared"
|
|
endif
|
|
newline
|
|
eventfld.long 0x00 11. " [11] ,Interrupt polarity clear on PA11" "No effect,Cleared"
|
|
eventfld.long 0x00 10. " [10] ,Interrupt polarity clear on PA10" "No effect,Cleared"
|
|
eventfld.long 0x00 9. " [9] ,Interrupt polarity clear on PA09" "No effect,Cleared"
|
|
eventfld.long 0x00 8. " [8] ,Interrupt polarity clear on PA08" "No effect,Cleared"
|
|
newline
|
|
eventfld.long 0x00 7. " [7] ,Interrupt polarity clear on PA07" "No effect,Cleared"
|
|
eventfld.long 0x00 6. " [6] ,Interrupt polarity clear on PA06" "No effect,Cleared"
|
|
eventfld.long 0x00 5. " [5] ,Interrupt polarity clear on PA05" "No effect,Cleared"
|
|
eventfld.long 0x00 4. " [4] ,Interrupt polarity clear on PA04" "No effect,Cleared"
|
|
newline
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x00 3. " [3] ,Interrupt polarity clear on PA03" "No effect,Cleared"
|
|
eventfld.long 0x00 2. " [2] ,Interrupt polarity clear on PA02" "No effect,Cleared"
|
|
newline
|
|
endif
|
|
eventfld.long 0x00 1. " [1] ,Interrupt polarity clear on PA01" "No effect,Cleared"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt polarity clear on PA00" "No effect,Cleared"
|
|
line.long 0x04 "INTSTATUS,GPIOA Interrupt Status Register"
|
|
eventfld.long 0x04 31. " INTSTATUS[31] ,Clear interrupt request on PA31" "No effect,Cleared"
|
|
eventfld.long 0x04 30. " [30] ,Clear interrupt request on PA30" "No effect,Cleared"
|
|
eventfld.long 0x04 29. " [29] ,Clear interrupt request on PA29" "No effect,Cleared"
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x04 28. " [28] ,Clear interrupt request on PA28" "No effect,Cleared"
|
|
endif
|
|
newline
|
|
eventfld.long 0x04 27. " [27] ,Clear interrupt request on PA27" "No effect,Cleared"
|
|
eventfld.long 0x04 26. " [26] ,Clear interrupt request on PA26" "No effect,Cleared"
|
|
eventfld.long 0x04 25. " [25] ,Clear interrupt request on PA25" "No effect,Cleared"
|
|
eventfld.long 0x04 24. " [24] ,Clear interrupt request on PA24" "No effect,Cleared"
|
|
newline
|
|
eventfld.long 0x04 23. " [23] ,Clear interrupt request on PA23" "No effect,Cleared"
|
|
eventfld.long 0x04 22. " [22] ,Clear interrupt request on PA22" "No effect,Cleared"
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x04 21. " [21] ,Clear interrupt request on PA21" "No effect,Cleared"
|
|
eventfld.long 0x04 20. " [20] ,Clear interrupt request on PA20" "No effect,Cleared"
|
|
endif
|
|
newline
|
|
eventfld.long 0x04 19. " [19] ,Clear interrupt request on PA19" "No effect,Cleared"
|
|
eventfld.long 0x04 18. " [18] ,Clear interrupt request on PA18" "No effect,Cleared"
|
|
eventfld.long 0x04 17. " [17] ,Clear interrupt request on PA17" "No effect,Cleared"
|
|
eventfld.long 0x04 16. " [16] ,Clear interrupt request on PA16" "No effect,Cleared"
|
|
newline
|
|
eventfld.long 0x04 15. " [15] ,Clear interrupt request on PA15" "No effect,Cleared"
|
|
eventfld.long 0x04 14. " [14] ,Clear interrupt request on PA14" "No effect,Cleared"
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x04 13. " [13] ,Clear interrupt request on PA13" "No effect,Cleared"
|
|
eventfld.long 0x04 12. " [12] ,Clear interrupt request on PA12" "No effect,Cleared"
|
|
endif
|
|
newline
|
|
eventfld.long 0x04 11. " [11] ,Clear interrupt request on PA11" "No effect,Cleared"
|
|
eventfld.long 0x04 10. " [10] ,Clear interrupt request on PA10" "No effect,Cleared"
|
|
eventfld.long 0x04 9. " [9] ,Clear interrupt request on PA09" "No effect,Cleared"
|
|
eventfld.long 0x04 8. " [8] ,Clear interrupt request on PA08" "No effect,Cleared"
|
|
newline
|
|
eventfld.long 0x04 7. " [7] ,Clear interrupt request on PA07" "No effect,Cleared"
|
|
eventfld.long 0x04 6. " [6] ,Clear interrupt request on PA06" "No effect,Cleared"
|
|
eventfld.long 0x04 5. " [5] ,Clear interrupt request on PA05" "No effect,Cleared"
|
|
eventfld.long 0x04 4. " [4] ,Clear interrupt request on PA04" "No effect,Cleared"
|
|
newline
|
|
sif !cpuis("QN9083DUK")
|
|
eventfld.long 0x04 3. " [3] ,Clear interrupt request on PA03" "No effect,Cleared"
|
|
eventfld.long 0x04 2. " [2] ,Clear interrupt request on PA02" "No effect,Cleared"
|
|
newline
|
|
endif
|
|
eventfld.long 0x04 1. " [1] ,Clear interrupt request on PA01" "No effect,Cleared"
|
|
eventfld.long 0x04 0. " [0] ,Clear interrupt request on PA00" "No effect,Cleared"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIOB"
|
|
base ad:0x4008D000
|
|
width 15.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DATA,GPIOB Register Value"
|
|
bitfld.long 0x00 2. " DATA[2] ,Data value on PB02" "0,1"
|
|
bitfld.long 0x00 1. " [1] ,Data value on PB01" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,Data value on PB00" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DATAOUT,GPIOB Output Status Register"
|
|
bitfld.long 0x00 2. " DATAOUT[2] ,Data output register value bit 2" "0,1"
|
|
bitfld.long 0x00 1. " [1] ,Data output register value bit 1" "0,1"
|
|
bitfld.long 0x00 0. " [0] ,Data output register value bit 0" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "OUTEN_SET/CLR,GPIOB Output Set/Clear Register"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " OUTEN[2] ,Port B pin 2 data output bit" "Low,High"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Port B pin 1 data output bit" "Low,High"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Port B pin 0 data output bit" "Low,High"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "INTENSET,GPIOB Interrupt Enable Set Register"
|
|
bitfld.long 0x00 2. " INTENSET[2] ,Interrupt enable set on PB02" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt enable set on PB01" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt enable set on PB00" "No effect,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INTENCLR,GPIOB Port Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 2. " INTENCLR[2] ,Interrupt enable clear on PB02" "No effect,Enabled"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt enable clear on PB01" "No effect,Enabled"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt enable clear on PB00" "No effect,Enabled"
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "INTTYPESET,GPIOB Interrupt Type Set Register"
|
|
bitfld.long 0x00 2. " INTTYPESET[2] ,Interrupt type set on PB02" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt type set on PB01" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt type set on PB00" "No effect,Enabled"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "INTTYPECLR,GPIOB Interrupt Type Clear Register"
|
|
eventfld.long 0x00 2. " INTTYPECLR[2] ,Interrupt type clear on PB02" "No effect,Enabled"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt type clear on PB01" "No effect,Enabled"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt type clear on PB00" "No effect,Enabled"
|
|
wgroup.long 0x30++0x03
|
|
line.long 0x00 "INTPOLSET,GPIOB Interrupt Polarity Set Register"
|
|
bitfld.long 0x00 2. " INTPOLSET[2] ,Polarity-level/Edge IRQ configuration on PB02" "No effect,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Polarity-level/Edge IRQ configuration on PB01" "No effect,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Polarity-level/Edge IRQ configuration on PB00" "No effect,Enabled"
|
|
group.long 0x34++0x07
|
|
line.long 0x00 "INTPOLCLR,GPIOB Interrupt Polarity Set Register"
|
|
eventfld.long 0x00 2. " INTPOLCLR[2] ,Interrupt polarity clear on PB02" "No effect,Cleared"
|
|
eventfld.long 0x00 1. " [1] ,Interrupt polarity clear on PB01" "No effect,Cleared"
|
|
eventfld.long 0x00 0. " [0] ,Interrupt polarity clear on PB00" "No effect,Cleared"
|
|
line.long 0x04 "INTSTATUS,GPIOB Interrupt Status Register"
|
|
eventfld.long 0x04 2. " INTSTATUS[2] ,Clear interrupt request on PB02" "No effect,Cleared"
|
|
eventfld.long 0x04 1. " [1] ,Clear interrupt request on PB01" "No effect,Cleared"
|
|
eventfld.long 0x04 0. " [0] ,Clear interrupt request on PB00" "No effect,Cleared"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "PINT (Pin Interrupt And Pattern Match)"
|
|
base ad:0x40006000
|
|
width 8.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "ISEL,Pin Interrupt Mode Register"
|
|
bitfld.long 0x00 3. " PMODE[3] ,Interrupt mode selection for pin in PINSTEL3 register" "Edge,Level"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt mode selection for pin in PINSTEL2 register" "Edge,Level"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt mode selection for pin in PINSTEL1 register" "Edge,Level"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt mode selection for pin in PINSTEL0 register" "Edge,Level"
|
|
line.long 0x04 "IENR,Pin Interrupt Level Or Rising Edge Interrupt Enable Register"
|
|
bitfld.long 0x04 3. " ENRL[3] ,Enables the rising edge or level interrupt for pin in PINSTEL3 register" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Enables the rising edge or level interrupt for pin in PINSTEL2 register" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " [1] ,Enables the rising edge or level interrupt for pin in PINSTEL1 register" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,Enables the rising edge or level interrupt for pin in PINSTEL0 register" "Disabled,Enabled"
|
|
wgroup.long 0x08++0x07
|
|
line.long 0x00 "SIENR,Pin Interrupt Level Or Rising Edge Interrupt Set Register"
|
|
bitfld.long 0x00 3. " SETENRL[3] ,Ones written to this address sets corresponding bits in the IENR" "No operation,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Ones written to this address sets corresponding bits in the IENR" "No operation,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Ones written to this address sets corresponding bits in the IENR" "No operation,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Ones written to this address sets corresponding bits in the IENR" "No operation,Enabled"
|
|
line.long 0x04 "CIENR,Pin Interrupt Level Or Rising Edge Interrupt Clear Register"
|
|
bitfld.long 0x04 3. " CENRL[3] ,Ones written to this address clear bits in the IENR register to the corresponding bits" "No operation,Disabled"
|
|
bitfld.long 0x04 2. " [2] ,Ones written to this address clear bits in the IENR register to the corresponding bits" "No operation,Disabled"
|
|
bitfld.long 0x04 1. " [1] ,Ones written to this address clear bits in the IENR register to the corresponding bits" "No operation,Disabled"
|
|
bitfld.long 0x04 0. " [0] ,Ones written to this address clear bits in the IENR register to the corresponding bits" "No operation,Disabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IENF,Pin Interrupt Active Level Or Falling Edge Interrupt Enable Register"
|
|
bitfld.long 0x00 3. " ENAF[3] ,Enables the falling edge or configures the active level interrupt for each pin interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Enables the falling edge or configures the active level interrupt for each pin interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Enables the falling edge or configures the active level interrupt for each pin interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Enables the falling edge or configures the active level interrupt for each pin interrupt" "Disabled,Enabled"
|
|
wgroup.long 0x14++0x07
|
|
line.long 0x00 "SIENF,Pin Interrupt Active Level Or Falling Edge Interrupt Set Register"
|
|
bitfld.long 0x00 3. " SETENAF[3] ,Ones written to this address set corresponding bits in the IENF" "No operation,Enabled"
|
|
bitfld.long 0x00 2. " [2] ,Ones written to this address set corresponding bits in the IENF" "No operation,Enabled"
|
|
bitfld.long 0x00 1. " [1] ,Ones written to this address set corresponding bits in the IENF" "No operation,Enabled"
|
|
bitfld.long 0x00 0. " [0] ,Ones written to this address set corresponding bits in the IENF" "No operation,Enabled"
|
|
line.long 0x04 "CIENF,Pin Interrupt Active Level Or Falling Edge Interrupt Clear Register"
|
|
bitfld.long 0x04 3. " CENAF[3] ,Ones written to this address clears corresponding bits in the IENF" "No operation,Disabled"
|
|
bitfld.long 0x04 2. " [2] ,Ones written to this address clears corresponding bits in the IENF" "No operation,Disabled"
|
|
bitfld.long 0x04 1. " [1] ,Ones written to this address clears corresponding bits in the IENF" "No operation,Disabled"
|
|
bitfld.long 0x04 0. " [0] ,Ones written to this address clears corresponding bits in the IENF" "No operation,Disabled"
|
|
group.long 0x1C++0x7
|
|
line.long 0x00 "RISE,Pin Interrupt Rising Edge Register"
|
|
bitfld.long 0x00 3. " RDET[3] ,Rising edge detect for selected pin in PINTSEL3 register" "No operation,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Rising edge detect for selected pin in PINTSEL2 register" "No operation,Cleared"
|
|
bitfld.long 0x00 1. " [1] ,Rising edge detect for selected pin in PINTSEL1 register" "No operation,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Rising edge detect for selected pin in PINTSEL0 register" "No operation,Cleared"
|
|
line.long 0x04 "FALL,Pin Interrupt Falling Edge Register"
|
|
bitfld.long 0x04 3. " FDET[3] ,Falling edge detect for selected pin in PINTSEL3 register" "No operation,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,Falling edge detect for selected pin in PINTSEL2 register" "No operation,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,Falling edge detect for selected pin in PINTSEL1 register" "No operation,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,Falling edge detect for selected pin in PINTSEL0 register" "No operation,Cleared"
|
|
if (((per.l(ad:0x40006000))&0x0F)==0x0F)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Inverts the active level in PINTSEL3 register" "No operation,Switched"
|
|
bitfld.long 0x00 2. " [2] ,Inverts the active level in PINTSEL2 register" "No operation,Switched"
|
|
bitfld.long 0x00 1. " [1] ,Inverts the active level in PINTSEL1 register" "No operation,Switched"
|
|
bitfld.long 0x00 0. " [0] ,Inverts the active level in PINTSEL0 register" "No operation,Switched"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x0E)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Inverts the active level in PINTSEL3 register" "No operation,Switched"
|
|
bitfld.long 0x00 2. " [2] ,Inverts the active level in PINTSEL2 register" "No operation,Switched"
|
|
bitfld.long 0x00 1. " [1] ,Inverts the active level in PINTSEL1 register" "No operation,Switched"
|
|
bitfld.long 0x00 0. " [0] ,Clears the edge interrupt in PINTSEL0 register" "No operation,Cleared"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x0D)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Inverts the active level in PINTSEL3 register" "No operation,Switched"
|
|
bitfld.long 0x00 2. " [2] ,Inverts the active level in PINTSEL2 register" "No operation,Switched"
|
|
bitfld.long 0x00 1. " [1] ,Clears the edge interrupt in PINTSEL1 register" "No operation,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Inverts the active level in PINTSEL0 register" "No operation,Switched"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x0C)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Inverts the active level in PINTSEL3 register" "No operation,Switched"
|
|
bitfld.long 0x00 2. " [2] ,Inverts the active level in PINTSEL2 register" "No operation,Switched"
|
|
bitfld.long 0x00 1. " [1] ,Clears the edge interrupt in PINTSEL1 register" "No operation,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Clears the edge interrupt in PINTSEL0 register" "No operation,Cleared"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x0B)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Inverts the active level in PINTSEL3 register" "No operation,Switched"
|
|
bitfld.long 0x00 2. " [2] ,Clears the edge interrupt in PINTSEL2 register" "No operation,Cleared"
|
|
bitfld.long 0x00 1. " [1] ,Inverts the active level in PINTSEL1 register" "No operation,Switched"
|
|
bitfld.long 0x00 0. " [0] ,Inverts the active level in PINTSEL0 register" "No operation,Switched"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x0A)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Inverts the active level in PINTSEL3 register" "No operation,Switched"
|
|
bitfld.long 0x00 2. " [2] ,Clears the edge interrupt in PINTSEL2 register" "No operation,Cleared"
|
|
bitfld.long 0x00 1. " [1] ,Inverts the active level in PINTSEL1 register" "No operation,Switched"
|
|
bitfld.long 0x00 0. " [0] ,Inverts the active level in PINTSEL0 register" "No operation,Switched"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x09)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Inverts the active level in PINTSEL3 register" "No operation,Switched"
|
|
bitfld.long 0x00 2. " [2] ,Clears the edge interrupt in PINTSEL2 register" "No operation,Cleared"
|
|
bitfld.long 0x00 1. " [1] ,Clears the edge interrupt in PINTSEL1 register" "No operation,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Inverts the active level in PINTSEL0 register" "No operation,Switched"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x08)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Inverts the active level in PINTSEL3 register" "No operation,Switched"
|
|
bitfld.long 0x00 2. " [2] ,Clears the edge interrupt in PINTSEL2 register" "No operation,Cleared"
|
|
bitfld.long 0x00 1. " [1] ,Clears the edge interrupt in PINTSEL1 register" "No operation,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Clears the edge interrupt in PINTSEL0 register" "No operation,Cleared"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x07)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Clears the edge interrupt in PINTSEL3 register" "No operation,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Inverts the active level in PINTSEL2 register" "No operation,Switched"
|
|
bitfld.long 0x00 1. " [1] ,Inverts the active level in PINTSEL1 register" "No operation,Switched"
|
|
bitfld.long 0x00 0. " [0] ,Inverts the active level in PINTSEL0 register" "No operation,Switched"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x06)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Clears the edge interrupt in PINTSEL3 register" "No operation,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Inverts the active level in PINTSEL2 register" "No operation,Switched"
|
|
bitfld.long 0x00 1. " [1] ,Inverts the active level in PINTSEL1 register" "No operation,Switched"
|
|
bitfld.long 0x00 0. " [0] ,Clears the edge interrupt in PINTSEL0 register" "No operation,Cleared"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x05)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Clears the edge interrupt in PINTSEL3 register" "No operation,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Inverts the active level in PINTSEL2 register" "No operation,Switched"
|
|
bitfld.long 0x00 1. " [1] ,Clears the edge interrupt in PINTSEL1 register" "No operation,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Inverts the active level in PINTSEL0 register" "No operation,Switched"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x04)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Clears the edge interrupt in PINTSEL3 register" "No operation,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Inverts the active level in PINTSEL2 register" "No operation,Switched"
|
|
bitfld.long 0x00 1. " [1] ,Clears the edge interrupt in PINTSEL1 register" "No operation,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Clears the edge interrupt in PINTSEL0 register" "No operation,Cleared"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x03)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Clears the edge interrupt in PINTSEL3 register" "No operation,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Clears the edge interrupt in PINTSEL2 register" "No operation,Cleared"
|
|
bitfld.long 0x00 1. " [1] ,Inverts the active level in PINTSEL1 register" "No operation,Switched"
|
|
bitfld.long 0x00 0. " [0] ,Inverts the active level in PINTSEL0 register" "No operation,Switched"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x02)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Clears the edge interrupt in PINTSEL3 register" "No operation,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Clears the edge interrupt in PINTSEL2 register" "No operation,Cleared"
|
|
bitfld.long 0x00 1. " [1] ,Inverts the active level in PINTSEL1 register" "No operation,Switched"
|
|
bitfld.long 0x00 0. " [0] ,Clears the edge interrupt in PINTSEL0 register" "No operation,Cleared"
|
|
elif (((per.l(ad:0x40006000))&0x0F)==0x01)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Clears the edge interrupt in PINTSEL3 register" "No operation,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Clears the edge interrupt in PINTSEL2 register" "No operation,Cleared"
|
|
bitfld.long 0x00 1. " [1] ,Clears the edge interrupt in PINTSEL1 register" "No operation,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Inverts the active level in PINTSEL0 register" "No operation,Switched"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IST,Pin Interrupt Status Register"
|
|
bitfld.long 0x00 3. " PSTAT[3] ,Clears the edge interrupt in PINTSEL3 register" "No operation,Cleared"
|
|
bitfld.long 0x00 2. " [2] ,Clears the edge interrupt in PINTSEL2 register" "No operation,Cleared"
|
|
bitfld.long 0x00 1. " [1] ,Clears the edge interrupt in PINTSEL1 register" "No operation,Cleared"
|
|
bitfld.long 0x00 0. " [0] ,Clears the edge interrupt in PINTSEL0 register" "No operation,Cleared"
|
|
endif
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "PMCTRL,Pattern Match Interrupt Control Register"
|
|
bitfld.long 0x00 27. " PMAT[3] ,Displays the current state of pattern matches" "No match,Match"
|
|
bitfld.long 0x00 26. " [2] ,Displays the current state of pattern matches" "No match,Match"
|
|
bitfld.long 0x00 25. " [1] ,Displays the current state of pattern matches" "No match,Match"
|
|
bitfld.long 0x00 24. " [0] ,Displays the current state of pattern matches" "No match,Match"
|
|
newline
|
|
bitfld.long 0x00 0. " SEL_PMATCH ,Specifies whether the four pin interrupts are controlled by the pin interrupt function or by the pattern match function" "Pin interrupt,Pattern match"
|
|
line.long 0x04 "PMSRC,Pattern Match Bit Slice Source Register"
|
|
bitfld.long 0x04 17.--19. " SRC[3] ,Selects the input source for bit slice 3" "Input 0,Input 1,Input 2,Input 3,?..."
|
|
bitfld.long 0x04 14.--16. " [2] ,Selects the input source for bit slice 2" "Input 0,Input 1,Input 2,Input 3,?..."
|
|
bitfld.long 0x04 11.--13. " [1] ,Selects the input source for bit slice 1" "Input 0,Input 1,Input 2,Input 3,?..."
|
|
bitfld.long 0x04 8.--10. " [0] ,Selects the input source for bit slice 0" "Input 0,Input 1,Input 2,Input 3,?..."
|
|
newline
|
|
line.long 0x08 "PMCFG,Pattern Match Bit Slice Configuration Register"
|
|
bitfld.long 0x08 17.--19. " CFG[3] ,Specifies the match contribution condition for bit slice 3" "Constant high,Sticky rising edge,Sticky falling edge,Sticky rising or falling edge,High level,Low level,Constant 0,Event"
|
|
bitfld.long 0x08 14.--16. " [2] ,Specifies the match contribution condition for bit slice 2" "Constant high,Sticky rising edge,Sticky falling edge,Sticky rising or falling edge,High level,Low level,Constant 0,Event"
|
|
bitfld.long 0x08 11.--13. " [1] ,Specifies the match contribution condition for bit slice 1" "Constant high,Sticky rising edge,Sticky falling edge,Sticky rising or falling edge,High level,Low level,Constant 0,Event"
|
|
bitfld.long 0x08 8.--10. " [0] ,Specifies the match contribution condition for bit slice 0" "Constant high,Sticky rising edge,Sticky falling edge,Sticky rising or falling edge,High level,Low level,Constant 0,Event"
|
|
newline
|
|
bitfld.long 0x08 3. " PROD_ENDPTS[3] ,Determines whether slice 3 is an endpoint" "No effect,Endpoint"
|
|
bitfld.long 0x08 2. " [2] ,Determines whether slice 2 is an endpoint" "No effect,Endpoint"
|
|
bitfld.long 0x08 1. " [1] ,Determines whether slice 1 is an endpoint" "No effect,Endpoint"
|
|
bitfld.long 0x08 0. " [0] ,Determines whether slice 0 is an endpoint" "No effect,Endpoint"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMA (DMA Controller)"
|
|
base ad:0x40082000
|
|
width 20.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,DMA Control"
|
|
bitfld.long 0x00 0. " ENABLE ,DMA controller master enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "INTSTAT,Interrupt Status Register"
|
|
bitfld.long 0x00 2. " ACTIVEERRINT ,Summarizes whether any error interrupts are pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " ACTIVEINT ,Summarizes whether any enabled interrupts are pending" "Not pending,Pending"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SRAMBASE,SRAM Address Of The Channel Configuration Table"
|
|
hexmask.long.tbyte 0x00 9.--31. 0x2 " OFFSET ,Address bits 31:9 of the beginning of the DMA descriptor table"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ENABLESET0_SET/CLR,Channel Enable Read Set And Clear For All DMA Channels"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x08 19. " ENA[19] ,Enables or disables DMA channel 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x08 18. " [18] ,Enables or disables DMA channel 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x08 17. " [17] ,Enables or disables DMA channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x08 16. " [16] ,Enables or disables DMA channel 16" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x08 15. " [15] ,Enables or disables DMA channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x08 14. " [14] ,Enables or disables DMA channel 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x08 13. " [13] ,Enables or disables DMA channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x08 12. " [12] ,Enables or disables DMA channel 12" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x08 11. " [11] ,Enables or disables DMA channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x08 10. " [10] ,Enables or disables DMA channel 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x08 9. " [9] ,Enables or disables DMA channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x08 8. " [8] ,Enables or disables DMA channel 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x08 7. " [7] ,Enables or disables DMA channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x08 6. " [6] ,Enables or disables DMA channel 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x08 5. " [5] ,Enables or disables DMA channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x08 4. " [4] ,Enables or disables DMA channel 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x08 3. " [3] ,Enables or disables DMA channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x08 2. " [2] ,Enables or disables DMA channel 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x08 1. " [1] ,Enables or disables DMA channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " [0] ,Enables or disables DMA channel 0" "Disabled,Enabled"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "ACTIVE0,Active Status Register 0"
|
|
bitfld.long 0x00 19. " ACT[19] ,Active flag for DMA channel 19" "Not active,Active"
|
|
bitfld.long 0x00 18. " [18] ,Active flag for DMA channel 18" "Not active,Active"
|
|
bitfld.long 0x00 17. " [17] ,Active flag for DMA channel 17" "Not active,Active"
|
|
bitfld.long 0x00 16. " [16] ,Active flag for DMA channel 16" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Active flag for DMA channel 15" "Not active,Active"
|
|
bitfld.long 0x00 14. " [14] ,Active flag for DMA channel 14" "Not active,Active"
|
|
bitfld.long 0x00 13. " [13] ,Active flag for DMA channel 13" "Not active,Active"
|
|
bitfld.long 0x00 12. " [12] ,Active flag for DMA channel 12" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Active flag for DMA channel 11" "Not active,Active"
|
|
bitfld.long 0x00 10. " [10] ,Active flag for DMA channel 10" "Not active,Active"
|
|
bitfld.long 0x00 9. " [9] ,Active flag for DMA channel 9" "Not active,Active"
|
|
bitfld.long 0x00 8. " [8] ,Active flag for DMA channel 8" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Active flag for DMA channel 7" "Not active,Active"
|
|
bitfld.long 0x00 6. " [6] ,Active flag for DMA channel 6" "Not active,Active"
|
|
bitfld.long 0x00 5. " [5] ,Active flag for DMA channel 5" "Not active,Active"
|
|
bitfld.long 0x00 4. " [4] ,Active flag for DMA channel 4" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Active flag for DMA channel 3" "Not active,Active"
|
|
bitfld.long 0x00 2. " [2] ,Active flag for DMA channel 2" "Not active,Active"
|
|
bitfld.long 0x00 1. " [1] ,Active flag for DMA channel 1" "Not active,Active"
|
|
bitfld.long 0x00 0. " [0] ,Active flag for DMA channel 0" "Not active,Active"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "BUSY0,Busy Status Register 0"
|
|
bitfld.long 0x00 19. " BSY[19] ,Busy flag for DMA channel 19" "Not busy,Busy"
|
|
bitfld.long 0x00 18. " [18] ,Busy flag for DMA channel 18" "Not busy,Busy"
|
|
bitfld.long 0x00 17. " [17] ,Busy flag for DMA channel 17" "Not busy,Busy"
|
|
bitfld.long 0x00 16. " [16] ,Busy flag for DMA channel 16" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Busy flag for DMA channel 15" "Not busy,Busy"
|
|
bitfld.long 0x00 14. " [14] ,Busy flag for DMA channel 14" "Not busy,Busy"
|
|
bitfld.long 0x00 13. " [13] ,Busy flag for DMA channel 13" "Not busy,Busy"
|
|
bitfld.long 0x00 12. " [12] ,Busy flag for DMA channel 12" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Busy flag for DMA channel 11" "Not busy,Busy"
|
|
bitfld.long 0x00 10. " [10] ,Busy flag for DMA channel 10" "Not busy,Busy"
|
|
bitfld.long 0x00 9. " [9] ,Busy flag for DMA channel 9" "Not busy,Busy"
|
|
bitfld.long 0x00 8. " [8] ,Busy flag for DMA channel 8" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Busy flag for DMA channel 7" "Not busy,Busy"
|
|
bitfld.long 0x00 6. " [6] ,Busy flag for DMA channel 6" "Not busy,Busy"
|
|
bitfld.long 0x00 5. " [5] ,Busy flag for DMA channel 5" "Not busy,Busy"
|
|
bitfld.long 0x00 4. " [4] ,Busy flag for DMA channel 4" "Not busy,Busy"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Busy flag for DMA channel 3" "Not busy,Busy"
|
|
bitfld.long 0x00 2. " [2] ,Busy flag for DMA channel 2" "Not busy,Busy"
|
|
bitfld.long 0x00 1. " [1] ,Busy flag for DMA channel 1" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " [0] ,Busy flag for DMA channel 0" "Not busy,Busy"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "ERRINT0,Error Interrupt Register 0"
|
|
bitfld.long 0x00 19. " ERR[19] ,Error interrupt flag for DMA channel 19" "Not active,Active"
|
|
bitfld.long 0x00 18. " [18] ,Error interrupt flag for DMA channel 18" "Not active,Active"
|
|
bitfld.long 0x00 17. " [17] ,Error interrupt flag for DMA channel 17" "Not active,Active"
|
|
bitfld.long 0x00 16. " [16] ,Error interrupt flag for DMA channel 16" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Error interrupt flag for DMA channel 15" "Not active,Active"
|
|
bitfld.long 0x00 14. " [14] ,Error interrupt flag for DMA channel 14" "Not active,Active"
|
|
bitfld.long 0x00 13. " [13] ,Error interrupt flag for DMA channel 13" "Not active,Active"
|
|
bitfld.long 0x00 12. " [12] ,Error interrupt flag for DMA channel 12" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Error interrupt flag for DMA channel 11" "Not active,Active"
|
|
bitfld.long 0x00 10. " [10] ,Error interrupt flag for DMA channel 10" "Not active,Active"
|
|
bitfld.long 0x00 9. " [9] ,Error interrupt flag for DMA channel 9" "Not active,Active"
|
|
bitfld.long 0x00 8. " [8] ,Error interrupt flag for DMA channel 8" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Error interrupt flag for DMA channel 7" "Not active,Active"
|
|
bitfld.long 0x00 6. " [6] ,Error interrupt flag for DMA channel 6" "Not active,Active"
|
|
bitfld.long 0x00 5. " [5] ,Error interrupt flag for DMA channel 5" "Not active,Active"
|
|
bitfld.long 0x00 4. " [4] ,Error interrupt flag for DMA channel 4" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Error interrupt flag for DMA channel 3" "Not active,Active"
|
|
bitfld.long 0x00 2. " [2] ,Error interrupt flag for DMA channel 2" "Not active,Active"
|
|
bitfld.long 0x00 1. " [1] ,Error interrupt flag for DMA channel 1" "Not active,Active"
|
|
bitfld.long 0x00 0. " [0] ,Error interrupt flag for DMA channel 0" "Not active,Active"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "INTENSET0_SET/CLR,Interrupt Enable Read Set And Clear For All DMA Channels"
|
|
setclrfld.long 0x00 19. 0x00 19. 0x08 19. " INTEN[19] ,Interrupt enable read and set for DMA channel 19" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x08 18. " [18] ,Interrupt enable read and set for DMA channel 18" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x08 17. " [17] ,Interrupt enable read and set for DMA channel 17" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x08 16. " [16] ,Interrupt enable read and set for DMA channel 16" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x00 15. 0x08 15. " [15] ,Interrupt enable read and set for DMA channel 15" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x08 14. " [14] ,Interrupt enable read and set for DMA channel 14" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x08 13. " [13] ,Interrupt enable read and set for DMA channel 13" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x08 12. " [12] ,Interrupt enable read and set for DMA channel 12" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x00 11. 0x08 11. " [11] ,Interrupt enable read and set for DMA channel 11" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x08 10. " [10] ,Interrupt enable read and set for DMA channel 10" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x08 9. " [9] ,Interrupt enable read and set for DMA channel 9" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x08 8. " [8] ,Interrupt enable read and set for DMA channel 8" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x00 7. 0x08 7. " [7] ,Interrupt enable read and set for DMA channel 7" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x08 6. " [6] ,Interrupt enable read and set for DMA channel 6" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x08 5. " [5] ,Interrupt enable read and set for DMA channel 5" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x08 4. " [4] ,Interrupt enable read and set for DMA channel 4" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x00 3. 0x08 3. " [3] ,Interrupt enable read and set for DMA channel 3" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x08 2. " [2] ,Interrupt enable read and set for DMA channel 2" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x08 1. " [1] ,Interrupt enable read and set for DMA channel 1" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " [0] ,Interrupt enable read and set for DMA channel 0" "Disabled,Enabled"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "INTA0,Interrupt A Status For All DMA Channels"
|
|
bitfld.long 0x00 19. " IA[19] ,Interrupt A status for DMA channel 19" "Not active,Active"
|
|
bitfld.long 0x00 18. " [18] ,Interrupt A status for DMA channel 18" "Not active,Active"
|
|
bitfld.long 0x00 17. " [17] ,Interrupt A status for DMA channel 17" "Not active,Active"
|
|
bitfld.long 0x00 16. " [16] ,Interrupt A status for DMA channel 16" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Interrupt A status for DMA channel 15" "Not active,Active"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt A status for DMA channel 14" "Not active,Active"
|
|
bitfld.long 0x00 13. " [13] ,Interrupt A status for DMA channel 13" "Not active,Active"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt A status for DMA channel 12" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Interrupt A status for DMA channel 11" "Not active,Active"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt A status for DMA channel 10" "Not active,Active"
|
|
bitfld.long 0x00 9. " [9] ,Interrupt A status for DMA channel 9" "Not active,Active"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt A status for DMA channel 8" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Interrupt A status for DMA channel 7" "Not active,Active"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt A status for DMA channel 6" "Not active,Active"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt A status for DMA channel 5" "Not active,Active"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt A status for DMA channel 4" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Interrupt A status for DMA channel 3" "Not active,Active"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt A status for DMA channel 2" "Not active,Active"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt A status for DMA channel 1" "Not active,Active"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt A status for DMA channel 0" "Not active,Active"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "INTB0,Interrupt B Status For All DMA Channels"
|
|
bitfld.long 0x00 19. " IB[19] ,Interrupt B status for DMA channel 19" "Not active,Active"
|
|
bitfld.long 0x00 18. " [18] ,Interrupt B status for DMA channel 18" "Not active,Active"
|
|
bitfld.long 0x00 17. " [17] ,Interrupt B status for DMA channel 17" "Not active,Active"
|
|
bitfld.long 0x00 16. " [16] ,Interrupt B status for DMA channel 16" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Interrupt B status for DMA channel 15" "Not active,Active"
|
|
bitfld.long 0x00 14. " [14] ,Interrupt B status for DMA channel 14" "Not active,Active"
|
|
bitfld.long 0x00 13. " [13] ,Interrupt B status for DMA channel 13" "Not active,Active"
|
|
bitfld.long 0x00 12. " [12] ,Interrupt B status for DMA channel 12" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Interrupt B status for DMA channel 11" "Not active,Active"
|
|
bitfld.long 0x00 10. " [10] ,Interrupt B status for DMA channel 10" "Not active,Active"
|
|
bitfld.long 0x00 9. " [9] ,Interrupt B status for DMA channel 9" "Not active,Active"
|
|
bitfld.long 0x00 8. " [8] ,Interrupt B status for DMA channel 8" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Interrupt B status for DMA channel 7" "Not active,Active"
|
|
bitfld.long 0x00 6. " [6] ,Interrupt B status for DMA channel 6" "Not active,Active"
|
|
bitfld.long 0x00 5. " [5] ,Interrupt B status for DMA channel 5" "Not active,Active"
|
|
bitfld.long 0x00 4. " [4] ,Interrupt B status for DMA channel 4" "Not active,Active"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Interrupt B status for DMA channel 3" "Not active,Active"
|
|
bitfld.long 0x00 2. " [2] ,Interrupt B status for DMA channel 2" "Not active,Active"
|
|
bitfld.long 0x00 1. " [1] ,Interrupt B status for DMA channel 1" "Not active,Active"
|
|
bitfld.long 0x00 0. " [0] ,Interrupt B status for DMA channel 0" "Not active,Active"
|
|
wgroup.long 0x68++0x03
|
|
line.long 0x00 "SETVALID0,Set Valid 0 Register"
|
|
bitfld.long 0x00 19. " SV[19] ,SETVALID control for DMA channel 19" "No effect,Set"
|
|
bitfld.long 0x00 18. " [18] ,SETVALID control for DMA channel 18" "No effect,Set"
|
|
bitfld.long 0x00 17. " [17] ,SETVALID control for DMA channel 17" "No effect,Set"
|
|
bitfld.long 0x00 16. " [16] ,SETVALID control for DMA channel 16" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,SETVALID control for DMA channel 15" "No effect,Set"
|
|
bitfld.long 0x00 14. " [14] ,SETVALID control for DMA channel 14" "No effect,Set"
|
|
bitfld.long 0x00 13. " [13] ,SETVALID control for DMA channel 13" "No effect,Set"
|
|
bitfld.long 0x00 12. " [12] ,SETVALID control for DMA channel 12" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,SETVALID control for DMA channel 11" "No effect,Set"
|
|
bitfld.long 0x00 10. " [10] ,SETVALID control for DMA channel 10" "No effect,Set"
|
|
bitfld.long 0x00 9. " [9] ,SETVALID control for DMA channel 9" "No effect,Set"
|
|
bitfld.long 0x00 8. " [8] ,SETVALID control for DMA channel 8" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,SETVALID control for DMA channel 7" "No effect,Set"
|
|
bitfld.long 0x00 6. " [6] ,SETVALID control for DMA channel 6" "No effect,Set"
|
|
bitfld.long 0x00 5. " [5] ,SETVALID control for DMA channel 5" "No effect,Set"
|
|
bitfld.long 0x00 4. " [4] ,SETVALID control for DMA channel 4" "No effect,Set"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,SETVALID control for DMA channel 3" "No effect,Set"
|
|
bitfld.long 0x00 2. " [2] ,SETVALID control for DMA channel 2" "No effect,Set"
|
|
bitfld.long 0x00 1. " [1] ,SETVALID control for DMA channel 1" "No effect,Set"
|
|
bitfld.long 0x00 0. " [0] ,SETVALID control for DMA channel 0" "No effect,Set"
|
|
wgroup.long 0x70++0x03
|
|
line.long 0x00 "SETTRIG0,Set Trigger Control Bits For All DMA Channels"
|
|
bitfld.long 0x00 19. " TRIG[19] ,Set trigger control bit for DMA channel 19" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 18. " [18] ,Set trigger control bit for DMA channel 18" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 17. " [17] ,Set trigger control bit for DMA channel 17" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 16. " [16] ,Set trigger control bit for DMA channel 16" "No effect,Set the TRIG bit"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Set trigger control bit for DMA channel 15" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 14. " [14] ,Set trigger control bit for DMA channel 14" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 13. " [13] ,Set trigger control bit for DMA channel 13" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 12. " [12] ,Set trigger control bit for DMA channel 12" "No effect,Set the TRIG bit"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Set trigger control bit for DMA channel 11" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 10. " [10] ,Set trigger control bit for DMA channel 10" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 9. " [9] ,Set trigger control bit for DMA channel 9" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 8. " [8] ,Set trigger control bit for DMA channel 8" "No effect,Set the TRIG bit"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Set trigger control bit for DMA channel 7" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 6. " [6] ,Set trigger control bit for DMA channel 6" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 5. " [5] ,Set trigger control bit for DMA channel 5" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 4. " [4] ,Set trigger control bit for DMA channel 4" "No effect,Set the TRIG bit"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Set trigger control bit for DMA channel 3" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 2. " [2] ,Set trigger control bit for DMA channel 2" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 1. " [1] ,Set trigger control bit for DMA channel 1" "No effect,Set the TRIG bit"
|
|
bitfld.long 0x00 0. " [0] ,Set trigger control bit for DMA channel 0" "No effect,Set the TRIG bit"
|
|
wgroup.long 0x78++0x03
|
|
line.long 0x00 "ABORT0,Channel Abort Control For All DMA Channels"
|
|
bitfld.long 0x00 19. " ABORTCTRL[19] ,Abort control for DMA channel 19" "No effect,Aborted"
|
|
bitfld.long 0x00 18. " [18] ,Abort control for DMA channel 18" "No effect,Aborted"
|
|
bitfld.long 0x00 17. " [17] ,Abort control for DMA channel 17" "No effect,Aborted"
|
|
bitfld.long 0x00 16. " [16] ,Abort control for DMA channel 16" "No effect,Aborted"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Abort control for DMA channel 15" "No effect,Aborted"
|
|
bitfld.long 0x00 14. " [14] ,Abort control for DMA channel 14" "No effect,Aborted"
|
|
bitfld.long 0x00 13. " [13] ,Abort control for DMA channel 13" "No effect,Aborted"
|
|
bitfld.long 0x00 12. " [12] ,Abort control for DMA channel 12" "No effect,Aborted"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Abort control for DMA channel 11" "No effect,Aborted"
|
|
bitfld.long 0x00 10. " [10] ,Abort control for DMA channel 10" "No effect,Aborted"
|
|
bitfld.long 0x00 9. " [9] ,Abort control for DMA channel 9" "No effect,Aborted"
|
|
bitfld.long 0x00 8. " [8] ,Abort control for DMA channel 8" "No effect,Aborted"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Abort control for DMA channel 7" "No effect,Aborted"
|
|
bitfld.long 0x00 6. " [6] ,Abort control for DMA channel 6" "No effect,Aborted"
|
|
bitfld.long 0x00 5. " [5] ,Abort control for DMA channel 5" "No effect,Aborted"
|
|
bitfld.long 0x00 4. " [4] ,Abort control for DMA channel 4" "No effect,Aborted"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Abort control for DMA channel 3" "No effect,Aborted"
|
|
bitfld.long 0x00 2. " [2] ,Abort control for DMA channel 2" "No effect,Aborted"
|
|
bitfld.long 0x00 1. " [1] ,Abort control for DMA channel 1" "No effect,Aborted"
|
|
bitfld.long 0x00 0. " [0] ,Abort control for DMA channel 0" "No effect,Aborted"
|
|
tree "Channel 0"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "CFG0,Configuration Register For DMA Channel 0"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 0 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x400+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT0,Control And Status Register For DMA Channel 0"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 0" "Not occurred,Occurred"
|
|
group.long (0x400+0x08)++0x03
|
|
line.long 0x00 "XFERCFG0,Transfer Configuration Register For DMA Channel 0"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "CFG1,Configuration Register For DMA Channel 1"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 1 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x410+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT1,Control And Status Register For DMA Channel 1"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 1" "Not occurred,Occurred"
|
|
group.long (0x410+0x08)++0x03
|
|
line.long 0x00 "XFERCFG1,Transfer Configuration Register For DMA Channel 1"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "CFG2,Configuration Register For DMA Channel 2"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 2 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x420+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT2,Control And Status Register For DMA Channel 2"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 2" "Not occurred,Occurred"
|
|
group.long (0x420+0x08)++0x03
|
|
line.long 0x00 "XFERCFG2,Transfer Configuration Register For DMA Channel 2"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "CFG3,Configuration Register For DMA Channel 3"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 3 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x430+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT3,Control And Status Register For DMA Channel 3"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 3" "Not occurred,Occurred"
|
|
group.long (0x430+0x08)++0x03
|
|
line.long 0x00 "XFERCFG3,Transfer Configuration Register For DMA Channel 3"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "CFG4,Configuration Register For DMA Channel 4"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 4 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x440+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT4,Control And Status Register For DMA Channel 4"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 4" "Not occurred,Occurred"
|
|
group.long (0x440+0x08)++0x03
|
|
line.long 0x00 "XFERCFG4,Transfer Configuration Register For DMA Channel 4"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "CFG5,Configuration Register For DMA Channel 5"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 5 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x450+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT5,Control And Status Register For DMA Channel 5"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 5" "Not occurred,Occurred"
|
|
group.long (0x450+0x08)++0x03
|
|
line.long 0x00 "XFERCFG5,Transfer Configuration Register For DMA Channel 5"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 6"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "CFG6,Configuration Register For DMA Channel 6"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 6 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x460+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT6,Control And Status Register For DMA Channel 6"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 6" "Not occurred,Occurred"
|
|
group.long (0x460+0x08)++0x03
|
|
line.long 0x00 "XFERCFG6,Transfer Configuration Register For DMA Channel 6"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 7"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "CFG7,Configuration Register For DMA Channel 7"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 7 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x470+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT7,Control And Status Register For DMA Channel 7"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 7" "Not occurred,Occurred"
|
|
group.long (0x470+0x08)++0x03
|
|
line.long 0x00 "XFERCFG7,Transfer Configuration Register For DMA Channel 7"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 8"
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "CFG8,Configuration Register For DMA Channel 8"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 8 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x480+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT8,Control And Status Register For DMA Channel 8"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 8" "Not occurred,Occurred"
|
|
group.long (0x480+0x08)++0x03
|
|
line.long 0x00 "XFERCFG8,Transfer Configuration Register For DMA Channel 8"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 9"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "CFG9,Configuration Register For DMA Channel 9"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 9 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x490+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT9,Control And Status Register For DMA Channel 9"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 9" "Not occurred,Occurred"
|
|
group.long (0x490+0x08)++0x03
|
|
line.long 0x00 "XFERCFG9,Transfer Configuration Register For DMA Channel 9"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 10"
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "CFG10,Configuration Register For DMA Channel 10"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 10 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x4A0+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT10,Control And Status Register For DMA Channel 10"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 10" "Not occurred,Occurred"
|
|
group.long (0x4A0+0x08)++0x03
|
|
line.long 0x00 "XFERCFG10,Transfer Configuration Register For DMA Channel 10"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 11"
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "CFG11,Configuration Register For DMA Channel 11"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 11 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x4B0+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT11,Control And Status Register For DMA Channel 11"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 11" "Not occurred,Occurred"
|
|
group.long (0x4B0+0x08)++0x03
|
|
line.long 0x00 "XFERCFG11,Transfer Configuration Register For DMA Channel 11"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 12"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "CFG12,Configuration Register For DMA Channel 12"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 12 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x4C0+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT12,Control And Status Register For DMA Channel 12"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 12" "Not occurred,Occurred"
|
|
group.long (0x4C0+0x08)++0x03
|
|
line.long 0x00 "XFERCFG12,Transfer Configuration Register For DMA Channel 12"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 13"
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "CFG13,Configuration Register For DMA Channel 13"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 13 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x4D0+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT13,Control And Status Register For DMA Channel 13"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 13" "Not occurred,Occurred"
|
|
group.long (0x4D0+0x08)++0x03
|
|
line.long 0x00 "XFERCFG13,Transfer Configuration Register For DMA Channel 13"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 14"
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "CFG14,Configuration Register For DMA Channel 14"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 14 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x4E0+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT14,Control And Status Register For DMA Channel 14"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 14" "Not occurred,Occurred"
|
|
group.long (0x4E0+0x08)++0x03
|
|
line.long 0x00 "XFERCFG14,Transfer Configuration Register For DMA Channel 14"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 15"
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "CFG15,Configuration Register For DMA Channel 15"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 15 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x4F0+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT15,Control And Status Register For DMA Channel 15"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 15" "Not occurred,Occurred"
|
|
group.long (0x4F0+0x08)++0x03
|
|
line.long 0x00 "XFERCFG15,Transfer Configuration Register For DMA Channel 15"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 16"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "CFG16,Configuration Register For DMA Channel 16"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 16 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x500+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT16,Control And Status Register For DMA Channel 16"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 16" "Not occurred,Occurred"
|
|
group.long (0x500+0x08)++0x03
|
|
line.long 0x00 "XFERCFG16,Transfer Configuration Register For DMA Channel 16"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 17"
|
|
group.long 0x510++0x03
|
|
line.long 0x00 "CFG17,Configuration Register For DMA Channel 17"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 17 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x510+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT17,Control And Status Register For DMA Channel 17"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 17" "Not occurred,Occurred"
|
|
group.long (0x510+0x08)++0x03
|
|
line.long 0x00 "XFERCFG17,Transfer Configuration Register For DMA Channel 17"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 18"
|
|
group.long 0x520++0x03
|
|
line.long 0x00 "CFG18,Configuration Register For DMA Channel 18"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 18 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x520+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT18,Control And Status Register For DMA Channel 18"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 18" "Not occurred,Occurred"
|
|
group.long (0x520+0x08)++0x03
|
|
line.long 0x00 "XFERCFG18,Transfer Configuration Register For DMA Channel 18"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
tree "Channel 19"
|
|
group.long 0x530++0x03
|
|
line.long 0x00 "CFG19,Configuration Register For DMA Channel 19"
|
|
bitfld.long 0x00 16.--18. " CHPRIORITY ,Priority of 19 channel when multiple DMA requests are pending" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DSTBURSTWRAP ,Destination burst wrap enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SRCBURSTWRAP ,Source burst wrap enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " BURSTPOWER ,Controls address wrapping" "1,2,4,8,16,31,64,128,256,512,1024,?..."
|
|
newline
|
|
bitfld.long 0x00 6. " TRIGBURST ,Selects whether hardware triggers cause a single or burst transfer" "Single transfer,Burst transfer"
|
|
bitfld.long 0x00 5. " TRIGTYPE ,Selects hardware trigger as edge triggered or level triggered" "Edge,Level"
|
|
bitfld.long 0x00 4. " TRIGPOL ,Selects the polarity of a hardware trigger for this channel" "Low-falling,High-rising"
|
|
bitfld.long 0x00 1. " HWTRIGEN ,Hardware triggering enable for this channel" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " PERIPHREQEN ,Peripheral request enable" "Disabled,Enabled"
|
|
rgroup.long (0x530+0x04)++0x03
|
|
line.long 0x00 "CTLSTAT19,Control And Status Register For DMA Channel 19"
|
|
bitfld.long 0x00 2. " TRIG ,Indicated that the trigger for this channel is currently set" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " VALIDPENDING ,Valid pending flag for this channel 19" "Not occurred,Occurred"
|
|
group.long (0x530+0x08)++0x03
|
|
line.long 0x00 "XFERCFG19,Transfer Configuration Register For DMA Channel 19"
|
|
hexmask.long.word 0x00 16.--25. 1. " XFERCOUNT ,Total number of transfers to be performed"
|
|
bitfld.long 0x00 14.--15. " DSTINC ,Determines whether the destination address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 12.--13. " SRINC ,Determines whether the source address is incremented for each DMA transfer" "No increment,1xwidth,2xwidth,4xwidth"
|
|
bitfld.long 0x00 8.--9. " WIDTH ,Transfer width used for this DMA channel" "8-bit,16-bit,31-bit,?..."
|
|
newline
|
|
bitfld.long 0x00 5. " SETINTB ,Set interrupt flag B for this channel" "No effect,Set"
|
|
bitfld.long 0x00 4. " SETINTA ,Set interrupt flag A for this channel" "No effect,Set"
|
|
bitfld.long 0x00 3. " CLRTRIG ,Clear trigger" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " SWTRIG ,Software trigger" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 1. " RELOAD ,Indicates whether the control structure of the channel will be reloaded when the current descriptor is exhausted" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CFGVALID ,Configuration valid flag" "Not valid,Valid"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCT (SCTimer/PWM)"
|
|
base ad:0x40085000
|
|
width 15.
|
|
if (((per.l(ad:0x40085000+0x00))&0x01)==0x00)
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "CONFIG,SCT Configuration Register"
|
|
bitfld.long 0x00 18. " AUTOLIMIT_H ,Auto limit upper bits value" "Not matched,Matched"
|
|
bitfld.long 0x00 17. " AUTOLIMIT_L ,Auto limit lower bits value" "Not matched,Matched"
|
|
bitfld.long 0x00 12. " INSYNC[3] ,Synchronization for input 3" "Not synchronized,Synchronized"
|
|
newline
|
|
bitfld.long 0x00 11. " INSYNC[2] ,Synchronization for input 2" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 10. " INSYNC[1] ,Synchronization for input 1" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 9. " INSYNC[0] ,Synchronization for input 0" "Not synchronized,Synchronized"
|
|
newline
|
|
bitfld.long 0x00 8. " NORELOAD_H ,1 in this bit prevents the higher match registers from being reloaded from their respective reload registers" "Allowed,Prohibited"
|
|
bitfld.long 0x00 7. " NORELOAD_L ,1 in this bit prevents the higher match registers from being reloaded from their respective reload registers" "Allowed,Prohibited"
|
|
bitfld.long 0x00 3.--6. " CKSEL ,SCT clock select" "Rising - I0,Falling - I0,Rising - I1,Falling - I1,Rising - I2,Falling - I2,Rising - I3,Falling - I3,Rising - I4,Falling - I4,Rising - I5,Falling - I5,Rising - I6,Falling - I6,Rising - I7,Falling - I7"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "System clock,Sampled system clock,SCT input clock,Asynchronous"
|
|
bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16-bit counters,One 32-bit counter"
|
|
line.long 0x04 "CTRL,SCT Control Register"
|
|
hexmask.long.byte 0x04 21.--28. 1. " PRE_H ,Specifies the factor by which the SCT clock is prescaled to produce the H counter clock"
|
|
bitfld.long 0x04 20. " BIDIR_H ,H counter direction select" "Up,Up-down"
|
|
bitfld.long 0x04 19. " CLRCTR_H ,Clear the H counter" "No action,Clear"
|
|
newline
|
|
bitfld.long 0x04 18. " HALT_H ,Stops the H counter and event occurrence" "No action,Halted"
|
|
bitfld.long 0x04 17. " STOP_H ,Stops the H counter but events can still occur" "No action,Stopped"
|
|
bitfld.long 0x04 16. " DOWN_H ,H counter counting down enable" "No action,Count down"
|
|
newline
|
|
hexmask.long.byte 0x04 5.--12. 1. " PRE_L ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock"
|
|
bitfld.long 0x04 4. " BIDIR_L ,L counter direction select" "Up,Up-down"
|
|
bitfld.long 0x04 3. " CLRCTR_L ,Clear the L or unified counter" "No action,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " HALT_L ,Stops The L or unified counter and event occurrence" "No action,Halted"
|
|
bitfld.long 0x04 1. " STOP_L ,Stops the L or unified counter but event can still occur" "No action,Stopped"
|
|
bitfld.long 0x04 0. " DOWN_L ,L or unified counter counting down enable" "No action,Count down"
|
|
line.long 0x08 "LIMIT,SCT Limit Event Select Register"
|
|
bitfld.long 0x08 31. " LIMMSK_H[31] ,Event 31 is used as a counter limit for the H counter" "Not used,Used"
|
|
bitfld.long 0x08 30. " [30] ,Event 30 is used as a counter limit for the H counter" "Not used,Used"
|
|
bitfld.long 0x08 29. " [29] ,Event 29 is used as a counter limit for the H counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 28. " [28] ,Event 28 is used as a counter limit for the H counter" "Not used,Used"
|
|
bitfld.long 0x08 27. " [27] ,Event 27 is used as a counter limit for the H counter" "Not used,Used"
|
|
bitfld.long 0x08 26. " [26] ,Event 26 is used as a counter limit for the H counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 25. " [25] ,Event 25 is used as a counter limit for the H counter" "Not used,Used"
|
|
bitfld.long 0x08 24. " [24] ,Event 24 is used as a counter limit for the H counter" "Not used,Used"
|
|
bitfld.long 0x08 23. " [23] ,Event 23 is used as a counter limit for the H counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 22. " [22] ,Event 22 is used as a counter limit for the H counter" "Not used,Used"
|
|
bitfld.long 0x08 21. " [21] ,Event 21 is used as a counter limit for the H counter" "Not used,Used"
|
|
bitfld.long 0x08 20. " [20] ,Event 20 is used as a counter limit for the H counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,Event 19 is used as a counter limit for the H counter" "Not used,Used"
|
|
bitfld.long 0x08 18. " [18] ,Event 18 is used as a counter limit for the H counter" "Not used,Used"
|
|
bitfld.long 0x08 17. " [17] ,Event 17 is used as a counter limit for the H counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 16. " [16] ,Event 16 is used as a counter limit for the H counter" "Not used,Used"
|
|
bitfld.long 0x08 15. " LIMMSK_L[15] ,Event 15 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 14. " [14] ,Event 14 is used as a counter limit for the L counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 13. " [13] ,Event 13 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 12. " [12] ,Event 12 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 11. " [11] ,Event 11 is used as a counter limit for the L counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 10. " [10] ,Event 10 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 9. " [9] ,Event 9 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 8. " [8] ,Event 8 is used as a counter limit for the L counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Event 7 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 6. " [6] ,Event 6 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 5. " [5] ,Event 5 is used as a counter limit for the L counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 4. " [4] ,Event 4 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 3. " [3] ,Event 3 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 2. " [2] ,Event 2 is used as a counter limit for the L counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 1. " [1] ,Event 1 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 0. " [0] ,Event 0 is used as a counter limit for the L counter" "Not used,Used"
|
|
line.long 0x0C "HALT,SCT Halt Event Select Register"
|
|
bitfld.long 0x0C 31. " HALTMSK_H[31] ,Event 31 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 30. " [30] ,Event 30 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 29. " [29] ,Event 29 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 28. " [28] ,Event 28 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 27. " [27] ,Event 27 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 26. " [26] ,Event 26 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 25. " [25] ,Event 25 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 24. " [24] ,Event 24 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 23. " [23] ,Event 23 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 22. " [22] ,Event 22 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 21. " [21] ,Event 21 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 20. " [20] ,Event 20 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 19. " [19] ,Event 19 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 18. " [18] ,Event 18 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 17. " [17] ,Event 17 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 16. " [16] ,Event 16 is used to set the HALT_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 15. " HALTMSK_L[15] ,Event 15 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 14. " [14] ,Event 14 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 13. " [13] ,Event 13 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 12. " [12] ,Event 12 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 11. " [11] ,Event 11 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 10. " [10] ,Event 10 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 9. " [9] ,Event 9 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 8. " [8] ,Event 8 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 7. " [7] ,Event 7 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 6. " [6] ,Event 6 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 5. " [5] ,Event 5 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 4. " [4] ,Event 4 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 3. " [3] ,Event 3 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 2. " [2] ,Event 2 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 1. " [1] ,Event 1 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 0. " [0] ,Event 0 is used to set the HALT_L bit in CTRL register" "Not used,Used"
|
|
line.long 0x10 "STOP,SCT Stop Event Select Register"
|
|
bitfld.long 0x10 31. " STOPMSK_H[31] ,Event 31 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 30. " [30] ,Event 30 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 29. " [29] ,Event 29 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 28. " [28] ,Event 28 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 27. " [27] ,Event 27 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 26. " [26] ,Event 26 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 25. " [25] ,Event 25 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 24. " [24] ,Event 24 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 23. " [23] ,Event 23 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 22. " [22] ,Event 22 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 21. " [21] ,Event 21 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 20. " [20] ,Event 20 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 19. " [19] ,Event 19 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 18. " [18] ,Event 18 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 17. " [17] ,Event 17 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 16. " [16] ,Event 16 is used to set the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 15. " STOPMSK_L[15] ,Event 15 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 14. " [14] ,Event 14 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 13. " [13] ,Event 13 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 12. " [12] ,Event 12 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 11. " [11] ,Event 11 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 10. " [10] ,Event 10 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 9. " [9] ,Event 9 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 8. " [8] ,Event 8 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 7. " [7] ,Event 7 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 6. " [6] ,Event 6 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 5. " [5] ,Event 5 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 4. " [4] ,Event 4 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 3. " [3] ,Event 3 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 2. " [2] ,Event 2 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 1. " [1] ,Event 1 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 0. " [0] ,Event 0 is used to set the STOP_L bit in CTRL register" "Not used,Used"
|
|
line.long 0x14 "START,SCT Start Event Select Register"
|
|
bitfld.long 0x14 31. " STARTMSK_H[31] ,Event 31 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 30. " [30] ,Event 30 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 29. " [29] ,Event 29 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 28. " [28] ,Event 28 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 27. " [27] ,Event 27 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 26. " [26] ,Event 26 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 25. " [25] ,Event 25 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 24. " [24] ,Event 24 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 23. " [23] ,Event 23 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 22. " [22] ,Event 22 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 21. " [21] ,Event 21 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 20. " [20] ,Event 20 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 19. " [19] ,Event 19 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 18. " [18] ,Event 18 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 17. " [17] ,Event 17 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 16. " [16] ,Event 16 is used to clear the STOP_H bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 15. " STARTMSK_L[15] ,Event 15 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 14. " [14] ,Event 14 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 13. " [13] ,Event 13 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 12. " [12] ,Event 12 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 11. " [11] ,Event 11 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 10. " [10] ,Event 10 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 9. " [9] ,Event 9 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 8. " [8] ,Event 8 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 7. " [7] ,Event 7 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 6. " [6] ,Event 6 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 5. " [5] ,Event 5 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 4. " [4] ,Event 4 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 3. " [3] ,Event 3 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 2. " [2] ,Event 2 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 1. " [1] ,Event 1 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 0. " [0] ,Event 0 is used to clear the STOP_L bit in CTRL register" "Not used,Used"
|
|
if (((per.l(ad:0x40085000+0x04))&0x40004)==0x40004)
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "COUNT,SCT Counter Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CTR_H ,Read or write the 16-bit H counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CTR_L ,Read or write the 16-bit L counter value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "STATE,SCT State Register"
|
|
bitfld.long 0x00 16.--20. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "COUNT,SCT Counter Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CTR_H ,Read or write the 16-bit H counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CTR_L ,Read or write the 16-bit L counter value"
|
|
line.long 0x04 "STATE,SCT State Register"
|
|
bitfld.long 0x04 16.--20. " STATE_H ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x04 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
else
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "CONFIG,SCT Configuration Register"
|
|
bitfld.long 0x00 17. " AUTOLIMIT_L ,Auto limit lower bits value" "Not matched,Matched"
|
|
bitfld.long 0x00 12. " INSYNC[3] ,Synchronization for input 3" "Not synchronized,Synchronized"
|
|
newline
|
|
bitfld.long 0x00 11. " INSYNC[2] ,Synchronization for input 2" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 10. " INSYNC[1] ,Synchronization for input 1" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 9. " INSYNC[0] ,Synchronization for input 0" "Not synchronized,Synchronized"
|
|
newline
|
|
bitfld.long 0x00 7. " NORELOAD_L ,1 in this bit prevents the higher match registers from being reloaded from their respective reload registers" "Allowed,Prohibited"
|
|
bitfld.long 0x00 3.--6. " CKSEL ,SCT clock select" "Rising - I0,Falling - I0,Rising - I1,Falling - I1,Rising - I2,Falling - I2,Rising - I3,Falling - I3,Rising - I4,Falling - I4,Rising - I5,Falling - I5,Rising - I6,Falling - I6,Rising - I7,Falling - I7"
|
|
newline
|
|
bitfld.long 0x00 1.--2. " CLKMODE ,SCT clock mode" "System clock,Sampled system clock,SCT input clock,Asynchronous"
|
|
bitfld.long 0x00 0. " UNIFY ,SCT operation" "Two 16-bit counters,One 32-bit counter"
|
|
line.long 0x04 "CTRL,SCT Control Register"
|
|
newline
|
|
newline
|
|
hexmask.long.byte 0x04 5.--12. 1. " PRE_L ,Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock"
|
|
bitfld.long 0x04 4. " BIDIR_L ,L counter direction select" "Up,Up-down"
|
|
bitfld.long 0x04 3. " CLRCTR_L ,Clear the L or unified counter" "No action,Cleared"
|
|
newline
|
|
bitfld.long 0x04 2. " HALT_L ,Stops The L or unified counter and event occurrence" "No action,Halted"
|
|
bitfld.long 0x04 1. " STOP_L ,Stops the L or unified counter but event can still occur" "No action,Stopped"
|
|
bitfld.long 0x04 0. " DOWN_L ,L or unified counter counting down enable" "No action,Count down"
|
|
line.long 0x08 "LIMIT,SCT Limit Event Select Register"
|
|
bitfld.long 0x08 15. " LIMMSK_L[15] ,Event 15 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 14. " [14] ,Event 14 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 13. " [13] ,Event 13 is used as a counter limit for the L counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 12. " [12] ,Event 12 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 11. " [11] ,Event 11 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 10. " [10] ,Event 10 is used as a counter limit for the L counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 9. " [9] ,Event 9 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 8. " [8] ,Event 8 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 7. " [7] ,Event 7 is used as a counter limit for the L counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 6. " [6] ,Event 6 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 5. " [5] ,Event 5 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 4. " [4] ,Event 4 is used as a counter limit for the L counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,Event 3 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 2. " [2] ,Event 2 is used as a counter limit for the L counter" "Not used,Used"
|
|
bitfld.long 0x08 1. " [1] ,Event 1 is used as a counter limit for the L counter" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x08 0. " [0] ,Event 0 is used as a counter limit for the L counter" "Not used,Used"
|
|
line.long 0x0C "HALT,SCT Halt Event Select Register"
|
|
bitfld.long 0x0C 15. " HALTMSK_L[15] ,Event 15 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 14. " [14] ,Event 14 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 13. " [13] ,Event 13 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 12. " [12] ,Event 12 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 11. " [11] ,Event 11 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 10. " [10] ,Event 10 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 9. " [9] ,Event 9 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 8. " [8] ,Event 8 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 7. " [7] ,Event 7 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 6. " [6] ,Event 6 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 5. " [5] ,Event 5 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 4. " [4] ,Event 4 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 3. " [3] ,Event 3 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 2. " [2] ,Event 2 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x0C 1. " [1] ,Event 1 is used to set the HALT_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x0C 0. " [0] ,Event 0 is used to set the HALT_L bit in CTRL register" "Not used,Used"
|
|
line.long 0x10 "STOP,SCT Stop Event Select Register"
|
|
bitfld.long 0x10 15. " STOPMSK_L[15] ,Event 15 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 14. " [14] ,Event 14 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 13. " [13] ,Event 13 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 12. " [12] ,Event 12 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 11. " [11] ,Event 11 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 10. " [10] ,Event 10 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 9. " [9] ,Event 9 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 8. " [8] ,Event 8 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 7. " [7] ,Event 7 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 6. " [6] ,Event 6 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 5. " [5] ,Event 5 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 4. " [4] ,Event 4 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 3. " [3] ,Event 3 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 2. " [2] ,Event 2 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x10 1. " [1] ,Event 1 is used to set the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x10 0. " [0] ,Event 0 is used to set the STOP_L bit in CTRL register" "Not used,Used"
|
|
line.long 0x14 "START,SCT Start Event Select Register"
|
|
bitfld.long 0x14 15. " STARTMSK_L[15] ,Event 15 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 14. " [14] ,Event 14 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 13. " [13] ,Event 13 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 12. " [12] ,Event 12 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 11. " [11] ,Event 11 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 10. " [10] ,Event 10 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 9. " [9] ,Event 9 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 8. " [8] ,Event 8 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 7. " [7] ,Event 7 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 6. " [6] ,Event 6 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 5. " [5] ,Event 5 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 4. " [4] ,Event 4 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 3. " [3] ,Event 3 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 2. " [2] ,Event 2 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
bitfld.long 0x14 1. " [1] ,Event 1 is used to clear the STOP_L bit in CTRL register " "Not used,Used"
|
|
newline
|
|
bitfld.long 0x14 0. " [0] ,Event 0 is used to clear the STOP_L bit in CTRL register" "Not used,Used"
|
|
if (((per.l(ad:0x40085000+0x04))&0x40004)==0x40004)
|
|
rgroup.long 0x40++0x07
|
|
line.long 0x00 "COUNT,SCT Counter Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CTR_H ,Read or write the upper 16 bits of the 32-bit unified counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CTR_L ,Read or write the lower 16 bits of the 32-bit unified counter"
|
|
else
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "COUNT,SCT Counter Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CTR_H ,Read or write the upper 16 bits of the 32-bit unified counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CTR_L ,Read or write the lower 16 bits of the 32-bit unified counter"
|
|
endif
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "STATE,SCT State Register"
|
|
bitfld.long 0x00 0.--4. " STATE_L ,State variable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "INPUT,SCT Input Register"
|
|
hexmask.long.word 0x00 20.--31. 1. " SIN ,Input state for the remainder of states implemented in this SCT"
|
|
bitfld.long 0x00 19. " SIN3 ,Input 3 state following the synchronization specified by INSYNC0" "Low,High"
|
|
bitfld.long 0x00 18. " SIN2 ,Input 2 state following the synchronization specified by INSYNC0" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 17. " SIN1 ,Input 1 state following the synchronization specified by INSYNC0" "Low,High"
|
|
bitfld.long 0x00 16. " SIN0 ,Input 0 state following the synchronization specified by INSYNC0" "Low,High"
|
|
hexmask.long.word 0x00 4.--15. 1. " AIN ,Input state for the remainder of input implemented in this SCT"
|
|
newline
|
|
bitfld.long 0x00 3. " AIN3 ,Input 3 state on the last SCT clock edge" "Low,High"
|
|
bitfld.long 0x00 2. " AIN2 ,Input 2 state on the last SCT clock edge" "Low,High"
|
|
bitfld.long 0x00 1. " AIN1 ,Input 1 state on the last SCT clock edge" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " AIN0 ,Input 0 state on the last SCT clock edge" "Low,High"
|
|
if (((per.l(ad:0x40085000+0x00))&0x01)==0x00)
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "REGMODE,SCT Match/Capture Mode Register"
|
|
bitfld.long 0x00 31. " REGMOD_H[15] ,Control match/capture register 15" "Not controlled,Controlled"
|
|
bitfld.long 0x00 30. " [14] ,Control match/capture register 14" "Not controlled,Controlled"
|
|
bitfld.long 0x00 29. " [13] ,Control match/capture register 13" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 28. " [12] ,Control match/capture register 12" "Not controlled,Controlled"
|
|
bitfld.long 0x00 27. " [11] ,Control match/capture register 11" "Not controlled,Controlled"
|
|
bitfld.long 0x00 26. " [10] ,Control match/capture register 10" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 25. " [9] ,Control match/capture register 9" "Not controlled,Controlled"
|
|
bitfld.long 0x00 24. " [8] ,Control match/capture register 8" "Not controlled,Controlled"
|
|
bitfld.long 0x00 23. " [7] ,Control match/capture register 7" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 22. " [6] ,Control match/capture register 6" "Not controlled,Controlled"
|
|
bitfld.long 0x00 21. " [5] ,Control match/capture register 5" "Not controlled,Controlled"
|
|
bitfld.long 0x00 20. " [4] ,Control match/capture register 4" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 19. " [3] ,Control match/capture register 3" "Not controlled,Controlled"
|
|
bitfld.long 0x00 18. " [2] ,Control match/capture register 2" "Not controlled,Controlled"
|
|
bitfld.long 0x00 17. " [1] ,Control match/capture register 1" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 16. " [0] ,Control match/capture register 0" "Not controlled,Controlled"
|
|
bitfld.long 0x00 15. " REGMOD_L[15] ,Control match/capture register 15" "Not controlled,Controlled"
|
|
bitfld.long 0x00 14. " [14] ,Control match/capture register 14" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 13. " [13] ,Control match/capture register 13" "Not controlled,Controlled"
|
|
bitfld.long 0x00 12. " [12] ,Control match/capture register 12" "Not controlled,Controlled"
|
|
bitfld.long 0x00 11. " [11] ,Control match/capture register 11" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 10. " [10] ,Control match/capture register 10" "Not controlled,Controlled"
|
|
bitfld.long 0x00 9. " [9] ,Control match/capture register 9" "Not controlled,Controlled"
|
|
bitfld.long 0x00 8. " [8] ,Control match/capture register 8" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Control match/capture register 7" "Not controlled,Controlled"
|
|
bitfld.long 0x00 6. " [6] ,Control match/capture register 6" "Not controlled,Controlled"
|
|
bitfld.long 0x00 5. " [5] ,Control match/capture register 5" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 4. " [4] ,Control match/capture register 4" "Not controlled,Controlled"
|
|
bitfld.long 0x00 3. " [3] ,Control match/capture register 3" "Not controlled,Controlled"
|
|
bitfld.long 0x00 2. " [2] ,Control match/capture register 2" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 1. " [1] ,Control match/capture register 1" "Not controlled,Controlled"
|
|
bitfld.long 0x00 0. " [0] ,Control match/capture register 0" "Not controlled,Controlled"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "REGMODE,SCT Match/Capture Mode Register"
|
|
bitfld.long 0x00 15. " REGMOD_L[15] ,Control match/capture register 15" "Not controlled,Controlled"
|
|
bitfld.long 0x00 14. " [14] ,Control match/capture register 14" "Not controlled,Controlled"
|
|
bitfld.long 0x00 13. " [13] ,Control match/capture register 13" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Control match/capture register 12" "Not controlled,Controlled"
|
|
bitfld.long 0x00 11. " [11] ,Control match/capture register 11" "Not controlled,Controlled"
|
|
bitfld.long 0x00 10. " [10] ,Control match/capture register 10" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Control match/capture register 9" "Not controlled,Controlled"
|
|
bitfld.long 0x00 8. " [8] ,Control match/capture register 8" "Not controlled,Controlled"
|
|
bitfld.long 0x00 7. " [7] ,Control match/capture register 7" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Control match/capture register 6" "Not controlled,Controlled"
|
|
bitfld.long 0x00 5. " [5] ,Control match/capture register 5" "Not controlled,Controlled"
|
|
bitfld.long 0x00 4. " [4] ,Control match/capture register 4" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Control match/capture register 3" "Not controlled,Controlled"
|
|
bitfld.long 0x00 2. " [2] ,Control match/capture register 2" "Not controlled,Controlled"
|
|
bitfld.long 0x00 1. " [1] ,Control match/capture register 1" "Not controlled,Controlled"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Control match/capture register 0" "Not controlled,Controlled"
|
|
endif
|
|
if ((((per.l(ad:0x40085000+0x04))&0x40004)==0x04)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))||((((per.l(ad:0x40085000+0x04))&0x40004)==0x40004)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x00))
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OUTPUT,SCT Output Register"
|
|
bitfld.long 0x00 15. " OUT[15] ,Force state change on output 15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Force state change on output 14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Force state change on output 13" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Force state change on output 12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Force state change on output 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Force state change on output 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Force state change on output 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Force state change on output 8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Force state change on output 7" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Force state change on output 6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Force state change on output 5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Force state change on output 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Force state change on output 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Force state change on output 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Force state change on output 1" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Force state change on output 0" "Low,High"
|
|
else
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "OUTPUT,SCT Output Register"
|
|
bitfld.long 0x00 15. " OUT[15] ,Force state change on output 15" "Low,High"
|
|
bitfld.long 0x00 14. " [14] ,Force state change on output 14" "Low,High"
|
|
bitfld.long 0x00 13. " [13] ,Force state change on output 13" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Force state change on output 12" "Low,High"
|
|
bitfld.long 0x00 11. " [11] ,Force state change on output 11" "Low,High"
|
|
bitfld.long 0x00 10. " [10] ,Force state change on output 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Force state change on output 9" "Low,High"
|
|
bitfld.long 0x00 8. " [8] ,Force state change on output 8" "Low,High"
|
|
bitfld.long 0x00 7. " [7] ,Force state change on output 7" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Force state change on output 6" "Low,High"
|
|
bitfld.long 0x00 5. " [5] ,Force state change on output 5" "Low,High"
|
|
bitfld.long 0x00 4. " [4] ,Force state change on output 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Force state change on output 3" "Low,High"
|
|
bitfld.long 0x00 2. " [2] ,Force state change on output 2" "Low,High"
|
|
bitfld.long 0x00 1. " [1] ,Force state change on output 1" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Force state change on output 0" "Low,High"
|
|
endif
|
|
if (((per.l(ad:0x40085000+0x00))&0x01)==0x00)
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "OUTPUTDIRCTRL,SCT Output Counter Direction Control Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. " SETCLR ,Set/clear operation controls for the remainder of outputs on this SCT"
|
|
bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depending,Reversed on L,Reversed on H,?..."
|
|
bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depending,Reversed on L,Reversed on H,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depending,Reversed on L,Reversed on H,?..."
|
|
bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depending,Reversed on L,Reversed on H,?..."
|
|
bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depending,Reversed on L,Reversed on H,?..."
|
|
else
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "OUTPUTDIRCTRL,SCT Output Counter Direction Control Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. " SETCLR ,Set/clear operation controls for the remainder of outputs on this SCT"
|
|
bitfld.long 0x00 8.--9. " SETCLR4 ,Set/clear operation on output 4" "Not depending,Reversed on L,?..."
|
|
bitfld.long 0x00 6.--7. " SETCLR3 ,Set/clear operation on output 3" "Not depending,Reversed on L,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--5. " SETCLR2 ,Set/clear operation on output 2" "Not depending,Reversed on L,?..."
|
|
bitfld.long 0x00 2.--3. " SETCLR1 ,Set/clear operation on output 1" "Not depending,Reversed on L,?..."
|
|
bitfld.long 0x00 0.--1. " SETCLR0 ,Set/clear operation on output 0" "Not depending,Reversed on L,?..."
|
|
endif
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "RES,SCT Conflict Resolution Register"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. " ORES ,Resolution controls for the remainder of outputs on this SCT"
|
|
bitfld.long 0x00 8.--9. " O4RES ,Effect of simultaneous set and clear on output 4" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x00 6.--7. " O3RES ,Effect of simultaneous set and clear on output 3" "No change,Set,Clear,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4.--5. " O2RES ,Effect of simultaneous set and clear on output 2" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x00 2.--3. " O1RES ,Effect of simultaneous set and clear on output 1" "No change,Set,Clear,Toggle"
|
|
bitfld.long 0x00 0.--1. " O0RES ,Effect of simultaneous set and clear on output 0" "No change,Set,Clear,Toggle"
|
|
line.long 0x04 "DMAREQUEST0,SCT DMA Request 0 Register"
|
|
rbitfld.long 0x04 31. " DRQ0 ,Indicate the state of DMA request 0" "Low,High"
|
|
bitfld.long 0x04 30. " DRL0 ,Trigger DMA request 0" "Not triggered,Triggered"
|
|
bitfld.long 0x04 15. " DEV_0[15] ,Event 15 triggers DMA request 0" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x04 14. " [14] ,Event 14 triggers DMA request 0" "Not triggered,Triggered"
|
|
bitfld.long 0x04 13. " [13] ,Event 13 triggers DMA request 0" "Not triggered,Triggered"
|
|
bitfld.long 0x04 12. " [12] ,Event 12 triggers DMA request 0" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,Event 11 triggers DMA request 0" "Not triggered,Triggered"
|
|
bitfld.long 0x04 10. " [10] ,Event 10 triggers DMA request 0" "Not triggered,Triggered"
|
|
bitfld.long 0x04 9. " [9] ,Event 9 triggers DMA request 0" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x04 8. " [8] ,Event 8 triggers DMA request 0" "Not triggered,Triggered"
|
|
bitfld.long 0x04 7. " [7] ,Event 7 triggers DMA request 0" "Not triggered,Triggered"
|
|
bitfld.long 0x04 6. " [6] ,Event 6 triggers DMA request 0" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x04 5. " [5] ,Event 5 triggers DMA request 0" "Not triggered,Triggered"
|
|
bitfld.long 0x04 4. " [4] ,Event 4 triggers DMA request 0" "Not triggered,Triggered"
|
|
bitfld.long 0x04 3. " [3] ,Event 3 triggers DMA request 0" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x04 2. " [2] ,Event 2 triggers DMA request 0" "Not triggered,Triggered"
|
|
bitfld.long 0x04 1. " [1] ,Event 1 triggers DMA request 0" "Not triggered,Triggered"
|
|
bitfld.long 0x04 0. " [0] ,Event 0 triggers DMA request 0" "Not triggered,Triggered"
|
|
line.long 0x08 "DMAREQUEST1,SCT DMA Request 1 Register"
|
|
rbitfld.long 0x08 31. " DRQ1 ,Indicate the state of DMA request 1" "Low,High"
|
|
bitfld.long 0x08 30. " DRL1 ,Trigger DMA request 1" "Not triggered,Triggered"
|
|
bitfld.long 0x08 15. " DEV_1[15] ,Event 15 triggers DMA request 1" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x08 14. " [14] ,Event 14 triggers DMA request 1" "Not triggered,Triggered"
|
|
bitfld.long 0x08 13. " [13] ,Event 13 triggers DMA request 1" "Not triggered,Triggered"
|
|
bitfld.long 0x08 12. " [12] ,Event 12 triggers DMA request 1" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x08 11. " [11] ,Event 11 triggers DMA request 1" "Not triggered,Triggered"
|
|
bitfld.long 0x08 10. " [10] ,Event 10 triggers DMA request 1" "Not triggered,Triggered"
|
|
bitfld.long 0x08 9. " [9] ,Event 9 triggers DMA request 1" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x08 8. " [8] ,Event 8 triggers DMA request 1" "Not triggered,Triggered"
|
|
bitfld.long 0x08 7. " [7] ,Event 7 triggers DMA request 1" "Not triggered,Triggered"
|
|
bitfld.long 0x08 6. " [6] ,Event 6 triggers DMA request 1" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x08 5. " [5] ,Event 5 triggers DMA request 1" "Not triggered,Triggered"
|
|
bitfld.long 0x08 4. " [4] ,Event 4 triggers DMA request 1" "Not triggered,Triggered"
|
|
bitfld.long 0x08 3. " [3] ,Event 3 triggers DMA request 1" "Not triggered,Triggered"
|
|
newline
|
|
bitfld.long 0x08 2. " [2] ,Event 2 triggers DMA request 1" "Not triggered,Triggered"
|
|
bitfld.long 0x08 1. " [1] ,Event 1 triggers DMA request 1" "Not triggered,Triggered"
|
|
bitfld.long 0x08 0. " [0] ,Event 0 triggers DMA request 1" "Not triggered,Triggered"
|
|
group.long 0xF0++0x0F
|
|
line.long 0x00 "EVEN,SCT Event Interrupt Enable Register"
|
|
bitfld.long 0x00 15. " IEN[15] ,Requests an interrupt when FLAG[15] is set" "No action,Requested"
|
|
bitfld.long 0x00 14. " [14] ,Requests an interrupt when FLAG[14] is set" "No action,Requested"
|
|
bitfld.long 0x00 13. " [13] ,Requests an interrupt when FLAG[13] is set" "No action,Requested"
|
|
newline
|
|
bitfld.long 0x00 12. " [12] ,Requests an interrupt when FLAG[12] is set" "No action,Requested"
|
|
bitfld.long 0x00 11. " [11] ,Requests an interrupt when FLAG[11] is set" "No action,Requested"
|
|
bitfld.long 0x00 10. " [10] ,Requests an interrupt when FLAG[10] is set" "No action,Requested"
|
|
newline
|
|
bitfld.long 0x00 9. " [9] ,Requests an interrupt when FLAG[9] is set" "No action,Requested"
|
|
bitfld.long 0x00 8. " [8] ,Requests an interrupt when FLAG[8] is set" "No action,Requested"
|
|
bitfld.long 0x00 7. " [7] ,Requests an interrupt when FLAG[7] is set" "No action,Requested"
|
|
newline
|
|
bitfld.long 0x00 6. " [6] ,Requests an interrupt when FLAG[6] is set" "No action,Requested"
|
|
bitfld.long 0x00 5. " [5] ,Requests an interrupt when FLAG[5] is set" "No action,Requested"
|
|
bitfld.long 0x00 4. " [4] ,Requests an interrupt when FLAG[4] is set" "No action,Requested"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Requests an interrupt when FLAG[3] is set" "No action,Requested"
|
|
bitfld.long 0x00 2. " [2] ,Requests an interrupt when FLAG[2] is set" "No action,Requested"
|
|
bitfld.long 0x00 1. " [1] ,Requests an interrupt when FLAG[1] is set" "No action,Requested"
|
|
newline
|
|
bitfld.long 0x00 0. " [0] ,Requests an interrupt when FLAG[0] is set" "No action,Requested"
|
|
line.long 0x04 "EVFLAG,SCT Event Flag Register"
|
|
bitfld.long 0x04 15. " FLAG[15] ,Sets the bit when an event 15 occurred" "Low,High"
|
|
bitfld.long 0x04 14. " [14] ,Sets the bit when an event 14 occurred" "Low,High"
|
|
bitfld.long 0x04 13. " [13] ,Sets the bit when an event 13 occurred" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 12. " [12] ,Sets the bit when an event 12 occurred" "Low,High"
|
|
bitfld.long 0x04 11. " [11] ,Sets the bit when an event 11 occurred" "Low,High"
|
|
bitfld.long 0x04 10. " [10] ,Sets the bit when an event 10 occurred" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 9. " [9] ,Sets the bit when an event 9 occurred" "Low,High"
|
|
bitfld.long 0x04 8. " [8] ,Sets the bit when an event 8 occurred" "Low,High"
|
|
bitfld.long 0x04 7. " [7] ,Sets the bit when an event 7 occurred" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 6. " [6] ,Sets the bit when an event 6 occurred" "Low,High"
|
|
bitfld.long 0x04 5. " [5] ,Sets the bit when an event 5 occurred" "Low,High"
|
|
bitfld.long 0x04 4. " [4] ,Sets the bit when an event 4 occurred" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,Sets the bit when an event 3 occurred" "Low,High"
|
|
bitfld.long 0x04 2. " [2] ,Sets the bit when an event 2 occurred" "Low,High"
|
|
bitfld.long 0x04 1. " [1] ,Sets the bit when an event 1 occurred" "Low,High"
|
|
newline
|
|
bitfld.long 0x04 0. " [0] ,Sets the bit when an event 0 occurred" "Low,High"
|
|
line.long 0x08 "CONEN,SCT Conflict Interrupt Enable Register"
|
|
bitfld.long 0x08 15. " NCEN[15] ,Requests an interrupt when conflict flag register 15 is set" "No action,Requested"
|
|
bitfld.long 0x08 14. " [14] ,Requests an interrupt when conflict flag register 14 is set" "No action,Requested"
|
|
bitfld.long 0x08 13. " [13] ,Requests an interrupt when conflict flag register 13 is set" "No action,Requested"
|
|
newline
|
|
bitfld.long 0x08 12. " [12] ,Requests an interrupt when conflict flag register 12 is set" "No action,Requested"
|
|
bitfld.long 0x08 11. " [11] ,Requests an interrupt when conflict flag register 11 is set" "No action,Requested"
|
|
bitfld.long 0x08 10. " [10] ,Requests an interrupt when conflict flag register 10 is set" "No action,Requested"
|
|
newline
|
|
bitfld.long 0x08 9. " [9] ,Requests an interrupt when conflict flag register 9 is set" "No action,Requested"
|
|
bitfld.long 0x08 8. " [8] ,Requests an interrupt when conflict flag register 8 is set" "No action,Requested"
|
|
bitfld.long 0x08 7. " [7] ,Requests an interrupt when conflict flag register 7 is set" "No action,Requested"
|
|
newline
|
|
bitfld.long 0x08 6. " [6] ,Requests an interrupt when conflict flag register 6 is set" "No action,Requested"
|
|
bitfld.long 0x08 5. " [5] ,Requests an interrupt when conflict flag register 5 is set" "No action,Requested"
|
|
bitfld.long 0x08 4. " [4] ,Requests an interrupt when conflict flag register 4 is set" "No action,Requested"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,Requests an interrupt when conflict flag register 3 is set" "No action,Requested"
|
|
bitfld.long 0x08 2. " [2] ,Requests an interrupt when conflict flag register 2 is set" "No action,Requested"
|
|
bitfld.long 0x08 1. " [1] ,Requests an interrupt when conflict flag register 1 is set" "No action,Requested"
|
|
newline
|
|
bitfld.long 0x08 0. " [0] ,Requests an interrupt when conflict flag register 0 is set" "No action,Requested"
|
|
line.long 0x0C "CONFLAG,SCT Conflict Flag Register"
|
|
bitfld.long 0x0C 31. " BUSERRH ,The most recent bus error from this SCT" "No error,Error"
|
|
bitfld.long 0x0C 30. " BUSERRL ,The most recent bus error from this SCT" "No error,Error"
|
|
bitfld.long 0x0C 15. " NCFLAG[15] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x0C 14. " [14] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 13. " [13] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 12. " [12] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x0C 11. " [11] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 10. " [10] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 9. " [9] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x0C 8. " [8] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 7. " [7] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 6. " [6] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x0C 5. " [5] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 4. " [4] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 3. " [3] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x0C 2. " [2] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 1. " [1] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
bitfld.long 0x0C 0. " [0] ,Conflict event occurred on output" "Not occurred,Occurred"
|
|
newline
|
|
if ((((per.l(ad:0x40085000+0x4C))&0x01)==0x01)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x00))
|
|
group.long (0x100+0x04)++0x03
|
|
line.long 0x00 "CAP0,SCT Capture Register Of Capture Channel 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP0_H ,Read the 16-bit counter value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP0_L ,Read the 16-bit counter value at which this register was last captured"
|
|
group.long (0x100+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL0,SCT Capture Control Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAPCON0_H ,Event m causes the CAP0_H register to be loaded"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON0_L ,Event m causes the CAP0_L register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x01)==0x01)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "CAP0,SCT Capture Register Of Capture Channel 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP0_H ,Read the upper 16 bits of the 32-bit value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP0_L ,Read the lower 16 bits of the 32-bit value at which this register was last captured"
|
|
group.long (0x100+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL0,SCT Capture Control Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON0_L ,Event m causes the CAP0 register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x01)==0x00)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MATCH0,SCT Match Value Register Of Match Channel 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH0_H ,Read or write the upper 16 bits of the 32-bit value to be compared to the unified counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH0_L ,Read or write the lower 16 bits of the 32-bit value to be compared to the unified counter"
|
|
group.long (0x100+0x100)++0x03
|
|
line.long 0x00 "MATCHREL0,SCT Match Reload Value Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD0_H ,Specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD0_L ,Specifies the lower 16 bits of the 32-bit value to be loaded into the MATCH0 register"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "MATCH0,SCT Match Value Register Of Match Channel 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH0_H ,Read or write the 16-bit value to be compared to the H counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH0_L ,Read or write the 16-bit value to be compared to the L counter"
|
|
group.long (0x100+0x100)++0x03
|
|
line.long 0x00 "MATCHREL0,SCT Match Reload Value Register 0"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD0_H ,Specifies the 16-bit to be loaded into the MATCH0_H register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD0_L ,Specifies the 16-bit value to be loaded into the MATCH0_L register"
|
|
endif
|
|
if ((((per.l(ad:0x40085000+0x4C))&0x02)==0x02)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x00))
|
|
group.long (0x104+0x04)++0x03
|
|
line.long 0x00 "CAP1,SCT Capture Register Of Capture Channel 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP1_H ,Read the 16-bit counter value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP1_L ,Read the 16-bit counter value at which this register was last captured"
|
|
group.long (0x104+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL1,SCT Capture Control Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAPCON1_H ,Event m causes the CAP1_H register to be loaded"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON1_L ,Event m causes the CAP1_L register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x02)==0x02)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "CAP1,SCT Capture Register Of Capture Channel 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP1_H ,Read the upper 16 bits of the 32-bit value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP1_L ,Read the lower 16 bits of the 32-bit value at which this register was last captured"
|
|
group.long (0x104+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL1,SCT Capture Control Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON1_L ,Event m causes the CAP1 register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x02)==0x00)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "MATCH1,SCT Match Value Register Of Match Channel 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH1_H ,Read or write the upper 16 bits of the 32-bit value to be compared to the unified counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH1_L ,Read or write the lower 16 bits of the 32-bit value to be compared to the unified counter"
|
|
group.long (0x104+0x100)++0x03
|
|
line.long 0x00 "MATCHREL1,SCT Match Reload Value Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD1_H ,Specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD1_L ,Specifies the lower 16 bits of the 32-bit value to be loaded into the MATCH1 register"
|
|
else
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "MATCH1,SCT Match Value Register Of Match Channel 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH1_H ,Read or write the 16-bit value to be compared to the H counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH1_L ,Read or write the 16-bit value to be compared to the L counter"
|
|
group.long (0x104+0x100)++0x03
|
|
line.long 0x00 "MATCHREL1,SCT Match Reload Value Register 1"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD1_H ,Specifies the 16-bit to be loaded into the MATCH1_H register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD1_L ,Specifies the 16-bit value to be loaded into the MATCH1_L register"
|
|
endif
|
|
if ((((per.l(ad:0x40085000+0x4C))&0x04)==0x04)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x00))
|
|
group.long (0x108+0x04)++0x03
|
|
line.long 0x00 "CAP2,SCT Capture Register Of Capture Channel 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP2_H ,Read the 16-bit counter value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP2_L ,Read the 16-bit counter value at which this register was last captured"
|
|
group.long (0x108+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL2,SCT Capture Control Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAPCON2_H ,Event m causes the CAP2_H register to be loaded"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON2_L ,Event m causes the CAP2_L register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x04)==0x04)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "CAP2,SCT Capture Register Of Capture Channel 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP2_H ,Read the upper 16 bits of the 32-bit value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP2_L ,Read the lower 16 bits of the 32-bit value at which this register was last captured"
|
|
group.long (0x108+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL2,SCT Capture Control Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON2_L ,Event m causes the CAP2 register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x04)==0x00)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "MATCH2,SCT Match Value Register Of Match Channel 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH2_H ,Read or write the upper 16 bits of the 32-bit value to be compared to the unified counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH2_L ,Read or write the lower 16 bits of the 32-bit value to be compared to the unified counter"
|
|
group.long (0x108+0x100)++0x03
|
|
line.long 0x00 "MATCHREL2,SCT Match Reload Value Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD2_H ,Specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD2_L ,Specifies the lower 16 bits of the 32-bit value to be loaded into the MATCH2 register"
|
|
else
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "MATCH2,SCT Match Value Register Of Match Channel 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH2_H ,Read or write the 16-bit value to be compared to the H counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH2_L ,Read or write the 16-bit value to be compared to the L counter"
|
|
group.long (0x108+0x100)++0x03
|
|
line.long 0x00 "MATCHREL2,SCT Match Reload Value Register 2"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD2_H ,Specifies the 16-bit to be loaded into the MATCH2_H register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD2_L ,Specifies the 16-bit value to be loaded into the MATCH2_L register"
|
|
endif
|
|
if ((((per.l(ad:0x40085000+0x4C))&0x08)==0x08)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x00))
|
|
group.long (0x10C+0x04)++0x03
|
|
line.long 0x00 "CAP3,SCT Capture Register Of Capture Channel 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP3_H ,Read the 16-bit counter value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP3_L ,Read the 16-bit counter value at which this register was last captured"
|
|
group.long (0x10C+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL3,SCT Capture Control Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAPCON3_H ,Event m causes the CAP3_H register to be loaded"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON3_L ,Event m causes the CAP3_L register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x08)==0x08)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "CAP3,SCT Capture Register Of Capture Channel 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP3_H ,Read the upper 16 bits of the 32-bit value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP3_L ,Read the lower 16 bits of the 32-bit value at which this register was last captured"
|
|
group.long (0x10C+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL3,SCT Capture Control Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON3_L ,Event m causes the CAP3 register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x08)==0x00)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "MATCH3,SCT Match Value Register Of Match Channel 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH3_H ,Read or write the upper 16 bits of the 32-bit value to be compared to the unified counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH3_L ,Read or write the lower 16 bits of the 32-bit value to be compared to the unified counter"
|
|
group.long (0x10C+0x100)++0x03
|
|
line.long 0x00 "MATCHREL3,SCT Match Reload Value Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD3_H ,Specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD3_L ,Specifies the lower 16 bits of the 32-bit value to be loaded into the MATCH3 register"
|
|
else
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "MATCH3,SCT Match Value Register Of Match Channel 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH3_H ,Read or write the 16-bit value to be compared to the H counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH3_L ,Read or write the 16-bit value to be compared to the L counter"
|
|
group.long (0x10C+0x100)++0x03
|
|
line.long 0x00 "MATCHREL3,SCT Match Reload Value Register 3"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD3_H ,Specifies the 16-bit to be loaded into the MATCH3_H register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD3_L ,Specifies the 16-bit value to be loaded into the MATCH3_L register"
|
|
endif
|
|
if ((((per.l(ad:0x40085000+0x4C))&0x10)==0x10)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x00))
|
|
group.long (0x110+0x04)++0x03
|
|
line.long 0x00 "CAP4,SCT Capture Register Of Capture Channel 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP4_H ,Read the 16-bit counter value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP4_L ,Read the 16-bit counter value at which this register was last captured"
|
|
group.long (0x110+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL4,SCT Capture Control Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAPCON4_H ,Event m causes the CAP4_H register to be loaded"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON4_L ,Event m causes the CAP4_L register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x10)==0x10)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "CAP4,SCT Capture Register Of Capture Channel 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP4_H ,Read the upper 16 bits of the 32-bit value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP4_L ,Read the lower 16 bits of the 32-bit value at which this register was last captured"
|
|
group.long (0x110+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL4,SCT Capture Control Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON4_L ,Event m causes the CAP4 register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x10)==0x00)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MATCH4,SCT Match Value Register Of Match Channel 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH4_H ,Read or write the upper 16 bits of the 32-bit value to be compared to the unified counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH4_L ,Read or write the lower 16 bits of the 32-bit value to be compared to the unified counter"
|
|
group.long (0x110+0x100)++0x03
|
|
line.long 0x00 "MATCHREL4,SCT Match Reload Value Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD4_H ,Specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD4_L ,Specifies the lower 16 bits of the 32-bit value to be loaded into the MATCH4 register"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "MATCH4,SCT Match Value Register Of Match Channel 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH4_H ,Read or write the 16-bit value to be compared to the H counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH4_L ,Read or write the 16-bit value to be compared to the L counter"
|
|
group.long (0x110+0x100)++0x03
|
|
line.long 0x00 "MATCHREL4,SCT Match Reload Value Register 4"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD4_H ,Specifies the 16-bit to be loaded into the MATCH4_H register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD4_L ,Specifies the 16-bit value to be loaded into the MATCH4_L register"
|
|
endif
|
|
if ((((per.l(ad:0x40085000+0x4C))&0x20)==0x20)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x00))
|
|
group.long (0x114+0x04)++0x03
|
|
line.long 0x00 "CAP5,SCT Capture Register Of Capture Channel 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP5_H ,Read the 16-bit counter value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP5_L ,Read the 16-bit counter value at which this register was last captured"
|
|
group.long (0x114+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL5,SCT Capture Control Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAPCON5_H ,Event m causes the CAP5_H register to be loaded"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON5_L ,Event m causes the CAP5_L register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x20)==0x20)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "CAP5,SCT Capture Register Of Capture Channel 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP5_H ,Read the upper 16 bits of the 32-bit value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP5_L ,Read the lower 16 bits of the 32-bit value at which this register was last captured"
|
|
group.long (0x114+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL5,SCT Capture Control Register 5"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON5_L ,Event m causes the CAP5 register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x20)==0x00)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MATCH5,SCT Match Value Register Of Match Channel 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH5_H ,Read or write the upper 16 bits of the 32-bit value to be compared to the unified counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH5_L ,Read or write the lower 16 bits of the 32-bit value to be compared to the unified counter"
|
|
group.long (0x114+0x100)++0x03
|
|
line.long 0x00 "MATCHREL5,SCT Match Reload Value Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD5_H ,Specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD5_L ,Specifies the lower 16 bits of the 32-bit value to be loaded into the MATCH5 register"
|
|
else
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "MATCH5,SCT Match Value Register Of Match Channel 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH5_H ,Read or write the 16-bit value to be compared to the H counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH5_L ,Read or write the 16-bit value to be compared to the L counter"
|
|
group.long (0x114+0x100)++0x03
|
|
line.long 0x00 "MATCHREL5,SCT Match Reload Value Register 5"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD5_H ,Specifies the 16-bit to be loaded into the MATCH5_H register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD5_L ,Specifies the 16-bit value to be loaded into the MATCH5_L register"
|
|
endif
|
|
if ((((per.l(ad:0x40085000+0x4C))&0x40)==0x40)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x00))
|
|
group.long (0x118+0x04)++0x03
|
|
line.long 0x00 "CAP6,SCT Capture Register Of Capture Channel 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP6_H ,Read the 16-bit counter value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP6_L ,Read the 16-bit counter value at which this register was last captured"
|
|
group.long (0x118+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL6,SCT Capture Control Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAPCON6_H ,Event m causes the CAP6_H register to be loaded"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON6_L ,Event m causes the CAP6_L register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x40)==0x40)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "CAP6,SCT Capture Register Of Capture Channel 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP6_H ,Read the upper 16 bits of the 32-bit value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP6_L ,Read the lower 16 bits of the 32-bit value at which this register was last captured"
|
|
group.long (0x118+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL6,SCT Capture Control Register 6"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON6_L ,Event m causes the CAP6 register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x40)==0x00)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MATCH6,SCT Match Value Register Of Match Channel 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH6_H ,Read or write the upper 16 bits of the 32-bit value to be compared to the unified counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH6_L ,Read or write the lower 16 bits of the 32-bit value to be compared to the unified counter"
|
|
group.long (0x118+0x100)++0x03
|
|
line.long 0x00 "MATCHREL6,SCT Match Reload Value Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD6_H ,Specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD6_L ,Specifies the lower 16 bits of the 32-bit value to be loaded into the MATCH6 register"
|
|
else
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "MATCH6,SCT Match Value Register Of Match Channel 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH6_H ,Read or write the 16-bit value to be compared to the H counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH6_L ,Read or write the 16-bit value to be compared to the L counter"
|
|
group.long (0x118+0x100)++0x03
|
|
line.long 0x00 "MATCHREL6,SCT Match Reload Value Register 6"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD6_H ,Specifies the 16-bit to be loaded into the MATCH6_H register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD6_L ,Specifies the 16-bit value to be loaded into the MATCH6_L register"
|
|
endif
|
|
if ((((per.l(ad:0x40085000+0x4C))&0x80)==0x80)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x00))
|
|
group.long (0x11C+0x04)++0x03
|
|
line.long 0x00 "CAP7,SCT Capture Register Of Capture Channel 7"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP7_H ,Read the 16-bit counter value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP7_L ,Read the 16-bit counter value at which this register was last captured"
|
|
group.long (0x11C+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL7,SCT Capture Control Register 7"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAPCON7_H ,Event m causes the CAP7_H register to be loaded"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON7_L ,Event m causes the CAP7_L register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x80)==0x80)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "CAP7,SCT Capture Register Of Capture Channel 7"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP7_H ,Read the upper 16 bits of the 32-bit value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP7_L ,Read the lower 16 bits of the 32-bit value at which this register was last captured"
|
|
group.long (0x11C+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL7,SCT Capture Control Register 7"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON7_L ,Event m causes the CAP7 register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x80)==0x00)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MATCH7,SCT Match Value Register Of Match Channel 7"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH7_H ,Read or write the upper 16 bits of the 32-bit value to be compared to the unified counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH7_L ,Read or write the lower 16 bits of the 32-bit value to be compared to the unified counter"
|
|
group.long (0x11C+0x100)++0x03
|
|
line.long 0x00 "MATCHREL7,SCT Match Reload Value Register 7"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD7_H ,Specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD7_L ,Specifies the lower 16 bits of the 32-bit value to be loaded into the MATCH7 register"
|
|
else
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "MATCH7,SCT Match Value Register Of Match Channel 7"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH7_H ,Read or write the 16-bit value to be compared to the H counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH7_L ,Read or write the 16-bit value to be compared to the L counter"
|
|
group.long (0x11C+0x100)++0x03
|
|
line.long 0x00 "MATCHREL7,SCT Match Reload Value Register 7"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD7_H ,Specifies the 16-bit to be loaded into the MATCH7_H register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD7_L ,Specifies the 16-bit value to be loaded into the MATCH7_L register"
|
|
endif
|
|
if ((((per.l(ad:0x40085000+0x4C))&0x100)==0x100)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x00))
|
|
group.long (0x120+0x04)++0x03
|
|
line.long 0x00 "CAP8,SCT Capture Register Of Capture Channel 8"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP8_H ,Read the 16-bit counter value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP8_L ,Read the 16-bit counter value at which this register was last captured"
|
|
group.long (0x120+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL8,SCT Capture Control Register 8"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAPCON8_H ,Event m causes the CAP8_H register to be loaded"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON8_L ,Event m causes the CAP8_L register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x100)==0x100)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "CAP8,SCT Capture Register Of Capture Channel 8"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP8_H ,Read the upper 16 bits of the 32-bit value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP8_L ,Read the lower 16 bits of the 32-bit value at which this register was last captured"
|
|
group.long (0x120+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL8,SCT Capture Control Register 8"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON8_L ,Event m causes the CAP8 register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x100)==0x00)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "MATCH8,SCT Match Value Register Of Match Channel 8"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH8_H ,Read or write the upper 16 bits of the 32-bit value to be compared to the unified counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH8_L ,Read or write the lower 16 bits of the 32-bit value to be compared to the unified counter"
|
|
group.long (0x120+0x100)++0x03
|
|
line.long 0x00 "MATCHREL8,SCT Match Reload Value Register 8"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD8_H ,Specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD8_L ,Specifies the lower 16 bits of the 32-bit value to be loaded into the MATCH8 register"
|
|
else
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "MATCH8,SCT Match Value Register Of Match Channel 8"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH8_H ,Read or write the 16-bit value to be compared to the H counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH8_L ,Read or write the 16-bit value to be compared to the L counter"
|
|
group.long (0x120+0x100)++0x03
|
|
line.long 0x00 "MATCHREL8,SCT Match Reload Value Register 8"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD8_H ,Specifies the 16-bit to be loaded into the MATCH8_H register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD8_L ,Specifies the 16-bit value to be loaded into the MATCH8_L register"
|
|
endif
|
|
if ((((per.l(ad:0x40085000+0x4C))&0x200)==0x200)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x00))
|
|
group.long (0x124+0x04)++0x03
|
|
line.long 0x00 "CAP9,SCT Capture Register Of Capture Channel 9"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP9_H ,Read the 16-bit counter value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP9_L ,Read the 16-bit counter value at which this register was last captured"
|
|
group.long (0x124+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL9,SCT Capture Control Register 9"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAPCON9_H ,Event m causes the CAP9_H register to be loaded"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON9_L ,Event m causes the CAP9_L register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x200)==0x200)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "CAP9,SCT Capture Register Of Capture Channel 9"
|
|
hexmask.long.word 0x00 16.--31. 1. " CAP9_H ,Read the upper 16 bits of the 32-bit value at which this register was last captured"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAP9_L ,Read the lower 16 bits of the 32-bit value at which this register was last captured"
|
|
group.long (0x124+0x100)++0x03
|
|
line.long 0x00 "CAPCTRL9,SCT Capture Control Register 9"
|
|
hexmask.long.word 0x00 0.--15. 1. " CAPCON9_L ,Event m causes the CAP9 register to be loaded"
|
|
elif ((((per.l(ad:0x40085000+0x4C))&0x200)==0x00)&&(((per.l(ad:0x40085000+0x00))&0x01)==0x01))
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MATCH9,SCT Match Value Register Of Match Channel 9"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH9_H ,Read or write the upper 16 bits of the 32-bit value to be compared to the unified counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH9_L ,Read or write the lower 16 bits of the 32-bit value to be compared to the unified counter"
|
|
group.long (0x124+0x100)++0x03
|
|
line.long 0x00 "MATCHREL9,SCT Match Reload Value Register 9"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD9_H ,Specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD9_L ,Specifies the lower 16 bits of the 32-bit value to be loaded into the MATCH9 register"
|
|
else
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "MATCH9,SCT Match Value Register Of Match Channel 9"
|
|
hexmask.long.word 0x00 16.--31. 1. " MATCH9_H ,Read or write the 16-bit value to be compared to the H counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH9_L ,Read or write the 16-bit value to be compared to the L counter"
|
|
group.long (0x124+0x100)++0x03
|
|
line.long 0x00 "MATCHREL9,SCT Match Reload Value Register 9"
|
|
hexmask.long.word 0x00 16.--31. 1. " RELOAD9_H ,Specifies the 16-bit to be loaded into the MATCH9_H register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RELOAD9_L ,Specifies the 16-bit value to be loaded into the MATCH9_L register"
|
|
endif
|
|
newline
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "EV0_STATE,SCT Event State Register 0"
|
|
bitfld.long 0x00 15. " STATEMSK[15] ,Event state bit 15" "No action,State 15"
|
|
bitfld.long 0x00 14. " [14] ,Event state bit 14" "No action,State 14"
|
|
bitfld.long 0x00 13. " [13] ,Event state bit 13" "No action,State 13"
|
|
bitfld.long 0x00 12. " [12] ,Event state bit 12" "No action,State 12"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event state bit 11" "No action,State 11"
|
|
bitfld.long 0x00 10. " [10] ,Event state bit 10" "No action,State 10"
|
|
bitfld.long 0x00 9. " [9] ,Event state bit 9" "No action,State 9"
|
|
bitfld.long 0x00 8. " [8] ,Event state bit 8" "No action,State 8"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event state bit 7" "No action,State 7"
|
|
bitfld.long 0x00 6. " [6] ,Event state bit 6" "No action,State 6"
|
|
bitfld.long 0x00 5. " [5] ,Event state bit 5" "No action,State 5"
|
|
bitfld.long 0x00 4. " [4] ,Event state bit 4" "No action,State 4"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Event state bit 3" "No action,State 3"
|
|
bitfld.long 0x00 2. " [2] ,Event state bit 2" "No action,State 2"
|
|
bitfld.long 0x00 1. " [1] ,Event state bit 1" "No action,State 1"
|
|
bitfld.long 0x00 0. " [0] ,Event state bit 0" "No action,State 0"
|
|
if (((per.l(ad:0x40085000+0x00))&0x01)==0x00)
|
|
group.long (0x300+0x04)++0x03
|
|
line.long 0x00 "EV0_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION0 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM0 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV0 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD0 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE0 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND0 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL0 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL0 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
bitfld.long 0x00 4. " HEVENT0 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL0 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x300+0x04)++0x03
|
|
line.long 0x00 "EV0_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION0 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM0 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV0 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD0 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE0 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND0 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL0 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL0 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
rbitfld.long 0x00 4. " HEVENT0 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL0 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "EV1_STATE,SCT Event State Register 1"
|
|
bitfld.long 0x00 15. " STATEMSK[15] ,Event state bit 15" "No action,State 15"
|
|
bitfld.long 0x00 14. " [14] ,Event state bit 14" "No action,State 14"
|
|
bitfld.long 0x00 13. " [13] ,Event state bit 13" "No action,State 13"
|
|
bitfld.long 0x00 12. " [12] ,Event state bit 12" "No action,State 12"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event state bit 11" "No action,State 11"
|
|
bitfld.long 0x00 10. " [10] ,Event state bit 10" "No action,State 10"
|
|
bitfld.long 0x00 9. " [9] ,Event state bit 9" "No action,State 9"
|
|
bitfld.long 0x00 8. " [8] ,Event state bit 8" "No action,State 8"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event state bit 7" "No action,State 7"
|
|
bitfld.long 0x00 6. " [6] ,Event state bit 6" "No action,State 6"
|
|
bitfld.long 0x00 5. " [5] ,Event state bit 5" "No action,State 5"
|
|
bitfld.long 0x00 4. " [4] ,Event state bit 4" "No action,State 4"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Event state bit 3" "No action,State 3"
|
|
bitfld.long 0x00 2. " [2] ,Event state bit 2" "No action,State 2"
|
|
bitfld.long 0x00 1. " [1] ,Event state bit 1" "No action,State 1"
|
|
bitfld.long 0x00 0. " [0] ,Event state bit 0" "No action,State 0"
|
|
if (((per.l(ad:0x40085000+0x00))&0x01)==0x00)
|
|
group.long (0x308+0x04)++0x03
|
|
line.long 0x00 "EV1_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION1 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM1 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV1 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD1 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE1 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND1 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL1 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL1 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
bitfld.long 0x00 4. " HEVENT1 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL1 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x308+0x04)++0x03
|
|
line.long 0x00 "EV1_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION1 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM1 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV1 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD1 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE1 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND1 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL1 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL1 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
rbitfld.long 0x00 4. " HEVENT1 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL1 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "EV2_STATE,SCT Event State Register 2"
|
|
bitfld.long 0x00 15. " STATEMSK[15] ,Event state bit 15" "No action,State 15"
|
|
bitfld.long 0x00 14. " [14] ,Event state bit 14" "No action,State 14"
|
|
bitfld.long 0x00 13. " [13] ,Event state bit 13" "No action,State 13"
|
|
bitfld.long 0x00 12. " [12] ,Event state bit 12" "No action,State 12"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event state bit 11" "No action,State 11"
|
|
bitfld.long 0x00 10. " [10] ,Event state bit 10" "No action,State 10"
|
|
bitfld.long 0x00 9. " [9] ,Event state bit 9" "No action,State 9"
|
|
bitfld.long 0x00 8. " [8] ,Event state bit 8" "No action,State 8"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event state bit 7" "No action,State 7"
|
|
bitfld.long 0x00 6. " [6] ,Event state bit 6" "No action,State 6"
|
|
bitfld.long 0x00 5. " [5] ,Event state bit 5" "No action,State 5"
|
|
bitfld.long 0x00 4. " [4] ,Event state bit 4" "No action,State 4"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Event state bit 3" "No action,State 3"
|
|
bitfld.long 0x00 2. " [2] ,Event state bit 2" "No action,State 2"
|
|
bitfld.long 0x00 1. " [1] ,Event state bit 1" "No action,State 1"
|
|
bitfld.long 0x00 0. " [0] ,Event state bit 0" "No action,State 0"
|
|
if (((per.l(ad:0x40085000+0x00))&0x01)==0x00)
|
|
group.long (0x310+0x04)++0x03
|
|
line.long 0x00 "EV2_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION2 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM2 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV2 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD2 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE2 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND2 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL2 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL2 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
bitfld.long 0x00 4. " HEVENT2 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL2 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x310+0x04)++0x03
|
|
line.long 0x00 "EV2_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION2 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM2 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV2 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD2 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE2 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND2 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL2 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL2 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
rbitfld.long 0x00 4. " HEVENT2 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL2 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "EV3_STATE,SCT Event State Register 3"
|
|
bitfld.long 0x00 15. " STATEMSK[15] ,Event state bit 15" "No action,State 15"
|
|
bitfld.long 0x00 14. " [14] ,Event state bit 14" "No action,State 14"
|
|
bitfld.long 0x00 13. " [13] ,Event state bit 13" "No action,State 13"
|
|
bitfld.long 0x00 12. " [12] ,Event state bit 12" "No action,State 12"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event state bit 11" "No action,State 11"
|
|
bitfld.long 0x00 10. " [10] ,Event state bit 10" "No action,State 10"
|
|
bitfld.long 0x00 9. " [9] ,Event state bit 9" "No action,State 9"
|
|
bitfld.long 0x00 8. " [8] ,Event state bit 8" "No action,State 8"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event state bit 7" "No action,State 7"
|
|
bitfld.long 0x00 6. " [6] ,Event state bit 6" "No action,State 6"
|
|
bitfld.long 0x00 5. " [5] ,Event state bit 5" "No action,State 5"
|
|
bitfld.long 0x00 4. " [4] ,Event state bit 4" "No action,State 4"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Event state bit 3" "No action,State 3"
|
|
bitfld.long 0x00 2. " [2] ,Event state bit 2" "No action,State 2"
|
|
bitfld.long 0x00 1. " [1] ,Event state bit 1" "No action,State 1"
|
|
bitfld.long 0x00 0. " [0] ,Event state bit 0" "No action,State 0"
|
|
if (((per.l(ad:0x40085000+0x00))&0x01)==0x00)
|
|
group.long (0x318+0x04)++0x03
|
|
line.long 0x00 "EV3_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION3 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM3 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV3 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD3 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE3 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND3 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL3 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL3 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
bitfld.long 0x00 4. " HEVENT3 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL3 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x318+0x04)++0x03
|
|
line.long 0x00 "EV3_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION3 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM3 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV3 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD3 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE3 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND3 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL3 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL3 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
rbitfld.long 0x00 4. " HEVENT3 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL3 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "EV4_STATE,SCT Event State Register 4"
|
|
bitfld.long 0x00 15. " STATEMSK[15] ,Event state bit 15" "No action,State 15"
|
|
bitfld.long 0x00 14. " [14] ,Event state bit 14" "No action,State 14"
|
|
bitfld.long 0x00 13. " [13] ,Event state bit 13" "No action,State 13"
|
|
bitfld.long 0x00 12. " [12] ,Event state bit 12" "No action,State 12"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event state bit 11" "No action,State 11"
|
|
bitfld.long 0x00 10. " [10] ,Event state bit 10" "No action,State 10"
|
|
bitfld.long 0x00 9. " [9] ,Event state bit 9" "No action,State 9"
|
|
bitfld.long 0x00 8. " [8] ,Event state bit 8" "No action,State 8"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event state bit 7" "No action,State 7"
|
|
bitfld.long 0x00 6. " [6] ,Event state bit 6" "No action,State 6"
|
|
bitfld.long 0x00 5. " [5] ,Event state bit 5" "No action,State 5"
|
|
bitfld.long 0x00 4. " [4] ,Event state bit 4" "No action,State 4"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Event state bit 3" "No action,State 3"
|
|
bitfld.long 0x00 2. " [2] ,Event state bit 2" "No action,State 2"
|
|
bitfld.long 0x00 1. " [1] ,Event state bit 1" "No action,State 1"
|
|
bitfld.long 0x00 0. " [0] ,Event state bit 0" "No action,State 0"
|
|
if (((per.l(ad:0x40085000+0x00))&0x01)==0x00)
|
|
group.long (0x320+0x04)++0x03
|
|
line.long 0x00 "EV4_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION4 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM4 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV4 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD4 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE4 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND4 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL4 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL4 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
bitfld.long 0x00 4. " HEVENT4 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL4 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x320+0x04)++0x03
|
|
line.long 0x00 "EV4_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION4 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM4 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV4 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD4 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE4 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND4 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL4 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL4 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
rbitfld.long 0x00 4. " HEVENT4 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL4 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x328++0x03
|
|
line.long 0x00 "EV5_STATE,SCT Event State Register 5"
|
|
bitfld.long 0x00 15. " STATEMSK[15] ,Event state bit 15" "No action,State 15"
|
|
bitfld.long 0x00 14. " [14] ,Event state bit 14" "No action,State 14"
|
|
bitfld.long 0x00 13. " [13] ,Event state bit 13" "No action,State 13"
|
|
bitfld.long 0x00 12. " [12] ,Event state bit 12" "No action,State 12"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event state bit 11" "No action,State 11"
|
|
bitfld.long 0x00 10. " [10] ,Event state bit 10" "No action,State 10"
|
|
bitfld.long 0x00 9. " [9] ,Event state bit 9" "No action,State 9"
|
|
bitfld.long 0x00 8. " [8] ,Event state bit 8" "No action,State 8"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event state bit 7" "No action,State 7"
|
|
bitfld.long 0x00 6. " [6] ,Event state bit 6" "No action,State 6"
|
|
bitfld.long 0x00 5. " [5] ,Event state bit 5" "No action,State 5"
|
|
bitfld.long 0x00 4. " [4] ,Event state bit 4" "No action,State 4"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Event state bit 3" "No action,State 3"
|
|
bitfld.long 0x00 2. " [2] ,Event state bit 2" "No action,State 2"
|
|
bitfld.long 0x00 1. " [1] ,Event state bit 1" "No action,State 1"
|
|
bitfld.long 0x00 0. " [0] ,Event state bit 0" "No action,State 0"
|
|
if (((per.l(ad:0x40085000+0x00))&0x01)==0x00)
|
|
group.long (0x328+0x04)++0x03
|
|
line.long 0x00 "EV5_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION5 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM5 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV5 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD5 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE5 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND5 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL5 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL5 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
bitfld.long 0x00 4. " HEVENT5 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL5 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x328+0x04)++0x03
|
|
line.long 0x00 "EV5_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION5 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM5 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV5 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD5 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE5 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND5 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL5 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL5 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
rbitfld.long 0x00 4. " HEVENT5 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL5 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "EV6_STATE,SCT Event State Register 6"
|
|
bitfld.long 0x00 15. " STATEMSK[15] ,Event state bit 15" "No action,State 15"
|
|
bitfld.long 0x00 14. " [14] ,Event state bit 14" "No action,State 14"
|
|
bitfld.long 0x00 13. " [13] ,Event state bit 13" "No action,State 13"
|
|
bitfld.long 0x00 12. " [12] ,Event state bit 12" "No action,State 12"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event state bit 11" "No action,State 11"
|
|
bitfld.long 0x00 10. " [10] ,Event state bit 10" "No action,State 10"
|
|
bitfld.long 0x00 9. " [9] ,Event state bit 9" "No action,State 9"
|
|
bitfld.long 0x00 8. " [8] ,Event state bit 8" "No action,State 8"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event state bit 7" "No action,State 7"
|
|
bitfld.long 0x00 6. " [6] ,Event state bit 6" "No action,State 6"
|
|
bitfld.long 0x00 5. " [5] ,Event state bit 5" "No action,State 5"
|
|
bitfld.long 0x00 4. " [4] ,Event state bit 4" "No action,State 4"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Event state bit 3" "No action,State 3"
|
|
bitfld.long 0x00 2. " [2] ,Event state bit 2" "No action,State 2"
|
|
bitfld.long 0x00 1. " [1] ,Event state bit 1" "No action,State 1"
|
|
bitfld.long 0x00 0. " [0] ,Event state bit 0" "No action,State 0"
|
|
if (((per.l(ad:0x40085000+0x00))&0x01)==0x00)
|
|
group.long (0x330+0x04)++0x03
|
|
line.long 0x00 "EV6_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION6 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM6 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV6 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD6 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE6 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND6 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL6 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL6 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
bitfld.long 0x00 4. " HEVENT6 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL6 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x330+0x04)++0x03
|
|
line.long 0x00 "EV6_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION6 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM6 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV6 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD6 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE6 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND6 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL6 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL6 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
rbitfld.long 0x00 4. " HEVENT6 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL6 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x338++0x03
|
|
line.long 0x00 "EV7_STATE,SCT Event State Register 7"
|
|
bitfld.long 0x00 15. " STATEMSK[15] ,Event state bit 15" "No action,State 15"
|
|
bitfld.long 0x00 14. " [14] ,Event state bit 14" "No action,State 14"
|
|
bitfld.long 0x00 13. " [13] ,Event state bit 13" "No action,State 13"
|
|
bitfld.long 0x00 12. " [12] ,Event state bit 12" "No action,State 12"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event state bit 11" "No action,State 11"
|
|
bitfld.long 0x00 10. " [10] ,Event state bit 10" "No action,State 10"
|
|
bitfld.long 0x00 9. " [9] ,Event state bit 9" "No action,State 9"
|
|
bitfld.long 0x00 8. " [8] ,Event state bit 8" "No action,State 8"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event state bit 7" "No action,State 7"
|
|
bitfld.long 0x00 6. " [6] ,Event state bit 6" "No action,State 6"
|
|
bitfld.long 0x00 5. " [5] ,Event state bit 5" "No action,State 5"
|
|
bitfld.long 0x00 4. " [4] ,Event state bit 4" "No action,State 4"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Event state bit 3" "No action,State 3"
|
|
bitfld.long 0x00 2. " [2] ,Event state bit 2" "No action,State 2"
|
|
bitfld.long 0x00 1. " [1] ,Event state bit 1" "No action,State 1"
|
|
bitfld.long 0x00 0. " [0] ,Event state bit 0" "No action,State 0"
|
|
if (((per.l(ad:0x40085000+0x00))&0x01)==0x00)
|
|
group.long (0x338+0x04)++0x03
|
|
line.long 0x00 "EV7_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION7 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM7 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV7 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD7 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE7 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND7 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL7 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL7 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
bitfld.long 0x00 4. " HEVENT7 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL7 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x338+0x04)++0x03
|
|
line.long 0x00 "EV7_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION7 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM7 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV7 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD7 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE7 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND7 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL7 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL7 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
rbitfld.long 0x00 4. " HEVENT7 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL7 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "EV8_STATE,SCT Event State Register 8"
|
|
bitfld.long 0x00 15. " STATEMSK[15] ,Event state bit 15" "No action,State 15"
|
|
bitfld.long 0x00 14. " [14] ,Event state bit 14" "No action,State 14"
|
|
bitfld.long 0x00 13. " [13] ,Event state bit 13" "No action,State 13"
|
|
bitfld.long 0x00 12. " [12] ,Event state bit 12" "No action,State 12"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event state bit 11" "No action,State 11"
|
|
bitfld.long 0x00 10. " [10] ,Event state bit 10" "No action,State 10"
|
|
bitfld.long 0x00 9. " [9] ,Event state bit 9" "No action,State 9"
|
|
bitfld.long 0x00 8. " [8] ,Event state bit 8" "No action,State 8"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event state bit 7" "No action,State 7"
|
|
bitfld.long 0x00 6. " [6] ,Event state bit 6" "No action,State 6"
|
|
bitfld.long 0x00 5. " [5] ,Event state bit 5" "No action,State 5"
|
|
bitfld.long 0x00 4. " [4] ,Event state bit 4" "No action,State 4"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Event state bit 3" "No action,State 3"
|
|
bitfld.long 0x00 2. " [2] ,Event state bit 2" "No action,State 2"
|
|
bitfld.long 0x00 1. " [1] ,Event state bit 1" "No action,State 1"
|
|
bitfld.long 0x00 0. " [0] ,Event state bit 0" "No action,State 0"
|
|
if (((per.l(ad:0x40085000+0x00))&0x01)==0x00)
|
|
group.long (0x340+0x04)++0x03
|
|
line.long 0x00 "EV8_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION8 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM8 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV8 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD8 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE8 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND8 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL8 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL8 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
bitfld.long 0x00 4. " HEVENT8 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL8 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x340+0x04)++0x03
|
|
line.long 0x00 "EV8_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION8 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM8 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV8 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD8 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE8 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND8 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL8 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL8 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
rbitfld.long 0x00 4. " HEVENT8 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL8 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x348++0x03
|
|
line.long 0x00 "EV9_STATE,SCT Event State Register 9"
|
|
bitfld.long 0x00 15. " STATEMSK[15] ,Event state bit 15" "No action,State 15"
|
|
bitfld.long 0x00 14. " [14] ,Event state bit 14" "No action,State 14"
|
|
bitfld.long 0x00 13. " [13] ,Event state bit 13" "No action,State 13"
|
|
bitfld.long 0x00 12. " [12] ,Event state bit 12" "No action,State 12"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Event state bit 11" "No action,State 11"
|
|
bitfld.long 0x00 10. " [10] ,Event state bit 10" "No action,State 10"
|
|
bitfld.long 0x00 9. " [9] ,Event state bit 9" "No action,State 9"
|
|
bitfld.long 0x00 8. " [8] ,Event state bit 8" "No action,State 8"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Event state bit 7" "No action,State 7"
|
|
bitfld.long 0x00 6. " [6] ,Event state bit 6" "No action,State 6"
|
|
bitfld.long 0x00 5. " [5] ,Event state bit 5" "No action,State 5"
|
|
bitfld.long 0x00 4. " [4] ,Event state bit 4" "No action,State 4"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Event state bit 3" "No action,State 3"
|
|
bitfld.long 0x00 2. " [2] ,Event state bit 2" "No action,State 2"
|
|
bitfld.long 0x00 1. " [1] ,Event state bit 1" "No action,State 1"
|
|
bitfld.long 0x00 0. " [0] ,Event state bit 0" "No action,State 0"
|
|
if (((per.l(ad:0x40085000+0x00))&0x01)==0x00)
|
|
group.long (0x348+0x04)++0x03
|
|
line.long 0x00 "EV9_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION9 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM9 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV9 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD9 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE9 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND9 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL9 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL9 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
bitfld.long 0x00 4. " HEVENT9 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL9 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long (0x348+0x04)++0x03
|
|
line.long 0x00 "EV9_CTRL,SCT Event Control Register"
|
|
bitfld.long 0x00 21.--22. " DIRECTION9 ,Direction qualifier for event generation" "Direction independent,Counting up,Counting down,?..."
|
|
bitfld.long 0x00 20. " MATCHMEM9 ,Specifies matching rules" "EQ,GE/EQ/LE"
|
|
bitfld.long 0x00 15.--19. " STATEV9 ,This value is loaded into or added to the state selected by HEVENT" "No change,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 14. " STATELD9 ,Controls how the STATEV value modifies the state selected by HEVENT" "Added,Loaded"
|
|
newline
|
|
bitfld.long 0x00 12.--13. " COMBMODE9 ,Selects how the specified match and I/O condition are used and combined" "OR,MATCH,IO,AND"
|
|
bitfld.long 0x00 10.--11. " IOCOND9 ,Selects the I/O condition for event n" "Low,Rise,Fall,High"
|
|
bitfld.long 0x00 6.--9. " IOSEL9 ,Selects the input or output signal number associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 5. " OUTSEL9 ,Input/output select" "Inputs,Outputs"
|
|
newline
|
|
rbitfld.long 0x00 4. " HEVENT9 ,Select L/H counter" "L,H"
|
|
bitfld.long 0x00 0.--3. " MATCHSEL9 ,Selects the match register associated with this event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x500++0x07
|
|
line.long 0x00 "OUT0_SET,SCT Output 0 Set Register"
|
|
bitfld.long 0x00 15. " SET[15] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
line.long 0x04 "OUT0_CLR,SCT Output 0 Clear Register"
|
|
bitfld.long 0x04 15. " CLR[15] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
group.long 0x508++0x07
|
|
line.long 0x00 "OUT1_SET,SCT Output 0 Set Register"
|
|
bitfld.long 0x00 15. " SET[15] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
line.long 0x04 "OUT1_CLR,SCT Output 0 Clear Register"
|
|
bitfld.long 0x04 15. " CLR[15] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
group.long 0x510++0x07
|
|
line.long 0x00 "OUT2_SET,SCT Output 0 Set Register"
|
|
bitfld.long 0x00 15. " SET[15] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
line.long 0x04 "OUT2_CLR,SCT Output 0 Clear Register"
|
|
bitfld.long 0x04 15. " CLR[15] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
group.long 0x518++0x07
|
|
line.long 0x00 "OUT3_SET,SCT Output 0 Set Register"
|
|
bitfld.long 0x00 15. " SET[15] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
line.long 0x04 "OUT3_CLR,SCT Output 0 Clear Register"
|
|
bitfld.long 0x04 15. " CLR[15] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
group.long 0x520++0x07
|
|
line.long 0x00 "OUT4_SET,SCT Output 0 Set Register"
|
|
bitfld.long 0x00 15. " SET[15] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
line.long 0x04 "OUT4_CLR,SCT Output 0 Clear Register"
|
|
bitfld.long 0x04 15. " CLR[15] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
group.long 0x528++0x07
|
|
line.long 0x00 "OUT5_SET,SCT Output 0 Set Register"
|
|
bitfld.long 0x00 15. " SET[15] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
line.long 0x04 "OUT5_CLR,SCT Output 0 Clear Register"
|
|
bitfld.long 0x04 15. " CLR[15] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
group.long 0x530++0x07
|
|
line.long 0x00 "OUT6_SET,SCT Output 0 Set Register"
|
|
bitfld.long 0x00 15. " SET[15] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
line.long 0x04 "OUT6_CLR,SCT Output 0 Clear Register"
|
|
bitfld.long 0x04 15. " CLR[15] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
group.long 0x538++0x07
|
|
line.long 0x00 "OUT7_SET,SCT Output 0 Set Register"
|
|
bitfld.long 0x00 15. " SET[15] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 14. " [14] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 13. " [13] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 12. " [12] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 10. " [10] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 9. " [9] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 8. " [8] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 6. " [6] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 5. " [5] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 4. " [4] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 2. " [2] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 1. " [1] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
bitfld.long 0x00 0. " [0] ,A 1 in bit m selects event m to set output n" "Not set,Set"
|
|
line.long 0x04 "OUT7_CLR,SCT Output 0 Clear Register"
|
|
bitfld.long 0x04 15. " CLR[15] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 14. " [14] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 13. " [13] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 12. " [12] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 10. " [10] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 9. " [9] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 8. " [8] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 6. " [6] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 5. " [5] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 4. " [4] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 2. " [2] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 1. " [1] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0. " [0] ,A 1 in bit m selects event m to clear output n" "Not cleared,Cleared"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "CTIMER (Standard Counter/Timers)"
|
|
tree "CTIMER0"
|
|
base ad:0x40002000
|
|
width 6.
|
|
group.long 0x00++0x3B
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
bitfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3 event" "No effect,Interrupt reset"
|
|
newline
|
|
bitfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0 event" "No effect,Interrupt reset"
|
|
line.long 0x04 "TCR,Timer Control Register"
|
|
bitfld.long 0x04 1. " CRST ,Counter reset" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x08 "TC,Timer Counter Register"
|
|
line.long 0x0C "PR,Timer Prescale Registers"
|
|
line.long 0x10 "PC,Timer Prescale Counter Register"
|
|
line.long 0x14 "MCR,Match Control Register"
|
|
bitfld.long 0x14 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
line.long 0x18 "MR0,Timer Match Register"
|
|
line.long 0x1C "MR1,Timer Match Register"
|
|
line.long 0x20 "MR2,Timer Match Register"
|
|
line.long 0x24 "MR3,Timer Match Register"
|
|
line.long 0x28 "CCR,Capture Control Register"
|
|
bitfld.long 0x28 8. " CAP2L ,Generate interrupt on channel 2 capture event" "Not generated,Generated"
|
|
bitfld.long 0x28 7. " CAP2FE ,Falling edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x28 6. " CAP2RE ,Rising edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " CAP1L ,Generate interrupt on channel 1 capture event" "Not generated,Generated"
|
|
newline
|
|
bitfld.long 0x28 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x28 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " CAP0I ,Generate interrupt on channel 0" "Not generated,Generated"
|
|
bitfld.long 0x28 1. " CAP0FE ,Falling edge of capture channel 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x28 0. " CAP0RE ,Rising edge of capture channel 0" "Disabled,Enabled"
|
|
line.long 0x2C "CR0,Timer Capture Register 0"
|
|
line.long 0x30 "CR1,Timer Capture Register 1"
|
|
line.long 0x34 "CR2,Timer Capture Register 2"
|
|
line.long 0x38 "EMR,External Match Register"
|
|
bitfld.long 0x38 10.--11. " EMC[3] ,External match control 3" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x38 8.--9. " [2] ,External match control 2" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x38 6.--7. " [1] ,External match control 1" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x38 4.--5. " [0] ,External match control 0" "No effect,Clear,Set,Toggle"
|
|
newline
|
|
bitfld.long 0x38 3. " EM[3] ,External match 3" "Low,High"
|
|
bitfld.long 0x38 2. " [2] ,External match 2" "Low,High"
|
|
bitfld.long 0x38 1. " [1] ,External match 1" "Low,High"
|
|
bitfld.long 0x38 0. " [0] ,External match 0" "Low,High"
|
|
if (((per.l(ad:0x40002000+0x70))&0x10)==0x10)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTCR,Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Ch 0 rising,Ch 0 falling,Ch 1 rising,Ch 1 falling,Ch 2 rising,Ch 2 falling,?..."
|
|
bitfld.long 0x00 4. " ENCC ,Enable clearing of the timer and the prescaler" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CINSEL ,Count input select" "Channel 0,Channel 1,Channel 2,?..."
|
|
bitfld.long 0x00 0.--1. " CTMODE ,Counter/timer mode" "Timer mode,Counter mode rising edge,Counter mode falling edge,Count mode dual edge"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTCR,Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "No effect,No effect,No effect,No effect,No effect,No effect,?..."
|
|
bitfld.long 0x00 4. " ENCC ,Enable clearing of the timer and the prescaler" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CINSEL ,Count input select" "Channel 0,Channel 1,Channel 2,?..."
|
|
bitfld.long 0x00 0.--1. " CTMODE ,Counter/timer mode" "Timer mode,Counter mode rising edge,Counter mode falling edge,Count mode dual edge"
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PWMC,PWM Control Register"
|
|
bitfld.long 0x00 3. " PWMEN[3] ,PWM mode enable for channel 3" "Match,PWM"
|
|
bitfld.long 0x00 2. " [2] ,PWM mode enable for channel 2" "Match,PWM"
|
|
bitfld.long 0x00 1. " [1] ,PWM mode enable for channel 1" "Match,PWM"
|
|
bitfld.long 0x00 0. " [0] ,PWM mode enable for channel 0" "Match,PWM"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CTIMER1"
|
|
base ad:0x40003000
|
|
width 6.
|
|
group.long 0x00++0x3B
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
bitfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3 event" "No effect,Interrupt reset"
|
|
newline
|
|
bitfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0 event" "No effect,Interrupt reset"
|
|
line.long 0x04 "TCR,Timer Control Register"
|
|
bitfld.long 0x04 1. " CRST ,Counter reset" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x08 "TC,Timer Counter Register"
|
|
line.long 0x0C "PR,Timer Prescale Registers"
|
|
line.long 0x10 "PC,Timer Prescale Counter Register"
|
|
line.long 0x14 "MCR,Match Control Register"
|
|
bitfld.long 0x14 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
line.long 0x18 "MR0,Timer Match Register"
|
|
line.long 0x1C "MR1,Timer Match Register"
|
|
line.long 0x20 "MR2,Timer Match Register"
|
|
line.long 0x24 "MR3,Timer Match Register"
|
|
line.long 0x28 "CCR,Capture Control Register"
|
|
bitfld.long 0x28 8. " CAP2L ,Generate interrupt on channel 2 capture event" "Not generated,Generated"
|
|
bitfld.long 0x28 7. " CAP2FE ,Falling edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x28 6. " CAP2RE ,Rising edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " CAP1L ,Generate interrupt on channel 1 capture event" "Not generated,Generated"
|
|
newline
|
|
bitfld.long 0x28 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x28 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " CAP0I ,Generate interrupt on channel 0" "Not generated,Generated"
|
|
bitfld.long 0x28 1. " CAP0FE ,Falling edge of capture channel 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x28 0. " CAP0RE ,Rising edge of capture channel 0" "Disabled,Enabled"
|
|
line.long 0x2C "CR0,Timer Capture Register 0"
|
|
line.long 0x30 "CR1,Timer Capture Register 1"
|
|
line.long 0x34 "CR2,Timer Capture Register 2"
|
|
line.long 0x38 "EMR,External Match Register"
|
|
bitfld.long 0x38 10.--11. " EMC[3] ,External match control 3" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x38 8.--9. " [2] ,External match control 2" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x38 6.--7. " [1] ,External match control 1" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x38 4.--5. " [0] ,External match control 0" "No effect,Clear,Set,Toggle"
|
|
newline
|
|
bitfld.long 0x38 3. " EM[3] ,External match 3" "Low,High"
|
|
bitfld.long 0x38 2. " [2] ,External match 2" "Low,High"
|
|
bitfld.long 0x38 1. " [1] ,External match 1" "Low,High"
|
|
bitfld.long 0x38 0. " [0] ,External match 0" "Low,High"
|
|
if (((per.l(ad:0x40003000+0x70))&0x10)==0x10)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTCR,Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Ch 0 rising,Ch 0 falling,Ch 1 rising,Ch 1 falling,Ch 2 rising,Ch 2 falling,?..."
|
|
bitfld.long 0x00 4. " ENCC ,Enable clearing of the timer and the prescaler" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CINSEL ,Count input select" "Channel 0,Channel 1,Channel 2,?..."
|
|
bitfld.long 0x00 0.--1. " CTMODE ,Counter/timer mode" "Timer mode,Counter mode rising edge,Counter mode falling edge,Count mode dual edge"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTCR,Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "No effect,No effect,No effect,No effect,No effect,No effect,?..."
|
|
bitfld.long 0x00 4. " ENCC ,Enable clearing of the timer and the prescaler" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CINSEL ,Count input select" "Channel 0,Channel 1,Channel 2,?..."
|
|
bitfld.long 0x00 0.--1. " CTMODE ,Counter/timer mode" "Timer mode,Counter mode rising edge,Counter mode falling edge,Count mode dual edge"
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PWMC,PWM Control Register"
|
|
bitfld.long 0x00 3. " PWMEN[3] ,PWM mode enable for channel 3" "Match,PWM"
|
|
bitfld.long 0x00 2. " [2] ,PWM mode enable for channel 2" "Match,PWM"
|
|
bitfld.long 0x00 1. " [1] ,PWM mode enable for channel 1" "Match,PWM"
|
|
bitfld.long 0x00 0. " [0] ,PWM mode enable for channel 0" "Match,PWM"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CTIMER2"
|
|
base ad:0x40004000
|
|
width 6.
|
|
group.long 0x00++0x3B
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
bitfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3 event" "No effect,Interrupt reset"
|
|
newline
|
|
bitfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0 event" "No effect,Interrupt reset"
|
|
line.long 0x04 "TCR,Timer Control Register"
|
|
bitfld.long 0x04 1. " CRST ,Counter reset" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x08 "TC,Timer Counter Register"
|
|
line.long 0x0C "PR,Timer Prescale Registers"
|
|
line.long 0x10 "PC,Timer Prescale Counter Register"
|
|
line.long 0x14 "MCR,Match Control Register"
|
|
bitfld.long 0x14 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
line.long 0x18 "MR0,Timer Match Register"
|
|
line.long 0x1C "MR1,Timer Match Register"
|
|
line.long 0x20 "MR2,Timer Match Register"
|
|
line.long 0x24 "MR3,Timer Match Register"
|
|
line.long 0x28 "CCR,Capture Control Register"
|
|
bitfld.long 0x28 8. " CAP2L ,Generate interrupt on channel 2 capture event" "Not generated,Generated"
|
|
bitfld.long 0x28 7. " CAP2FE ,Falling edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x28 6. " CAP2RE ,Rising edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " CAP1L ,Generate interrupt on channel 1 capture event" "Not generated,Generated"
|
|
newline
|
|
bitfld.long 0x28 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x28 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " CAP0I ,Generate interrupt on channel 0" "Not generated,Generated"
|
|
bitfld.long 0x28 1. " CAP0FE ,Falling edge of capture channel 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x28 0. " CAP0RE ,Rising edge of capture channel 0" "Disabled,Enabled"
|
|
line.long 0x2C "CR0,Timer Capture Register 0"
|
|
line.long 0x30 "CR1,Timer Capture Register 1"
|
|
line.long 0x34 "CR2,Timer Capture Register 2"
|
|
line.long 0x38 "EMR,External Match Register"
|
|
bitfld.long 0x38 10.--11. " EMC[3] ,External match control 3" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x38 8.--9. " [2] ,External match control 2" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x38 6.--7. " [1] ,External match control 1" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x38 4.--5. " [0] ,External match control 0" "No effect,Clear,Set,Toggle"
|
|
newline
|
|
bitfld.long 0x38 3. " EM[3] ,External match 3" "Low,High"
|
|
bitfld.long 0x38 2. " [2] ,External match 2" "Low,High"
|
|
bitfld.long 0x38 1. " [1] ,External match 1" "Low,High"
|
|
bitfld.long 0x38 0. " [0] ,External match 0" "Low,High"
|
|
if (((per.l(ad:0x40004000+0x70))&0x10)==0x10)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTCR,Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Ch 0 rising,Ch 0 falling,Ch 1 rising,Ch 1 falling,Ch 2 rising,Ch 2 falling,?..."
|
|
bitfld.long 0x00 4. " ENCC ,Enable clearing of the timer and the prescaler" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CINSEL ,Count input select" "Channel 0,Channel 1,Channel 2,?..."
|
|
bitfld.long 0x00 0.--1. " CTMODE ,Counter/timer mode" "Timer mode,Counter mode rising edge,Counter mode falling edge,Count mode dual edge"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTCR,Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "No effect,No effect,No effect,No effect,No effect,No effect,?..."
|
|
bitfld.long 0x00 4. " ENCC ,Enable clearing of the timer and the prescaler" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CINSEL ,Count input select" "Channel 0,Channel 1,Channel 2,?..."
|
|
bitfld.long 0x00 0.--1. " CTMODE ,Counter/timer mode" "Timer mode,Counter mode rising edge,Counter mode falling edge,Count mode dual edge"
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PWMC,PWM Control Register"
|
|
bitfld.long 0x00 3. " PWMEN[3] ,PWM mode enable for channel 3" "Match,PWM"
|
|
bitfld.long 0x00 2. " [2] ,PWM mode enable for channel 2" "Match,PWM"
|
|
bitfld.long 0x00 1. " [1] ,PWM mode enable for channel 1" "Match,PWM"
|
|
bitfld.long 0x00 0. " [0] ,PWM mode enable for channel 0" "Match,PWM"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CTIMER3"
|
|
base ad:0x40050000
|
|
width 6.
|
|
group.long 0x00++0x3B
|
|
line.long 0x00 "IR,Interrupt Register"
|
|
bitfld.long 0x00 6. " CR2INT ,Interrupt flag for capture channel 2 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 5. " CR1INT ,Interrupt flag for capture channel 1 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 4. " CR0INT ,Interrupt flag for capture channel 0 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 3. " MR3INT ,Interrupt flag for match channel 3 event" "No effect,Interrupt reset"
|
|
newline
|
|
bitfld.long 0x00 2. " MR2INT ,Interrupt flag for match channel 2 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 1. " MR1INT ,Interrupt flag for match channel 1 event" "No effect,Interrupt reset"
|
|
bitfld.long 0x00 0. " MR0INT ,Interrupt flag for match channel 0 event" "No effect,Interrupt reset"
|
|
line.long 0x04 "TCR,Timer Control Register"
|
|
bitfld.long 0x04 1. " CRST ,Counter reset" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x08 "TC,Timer Counter Register"
|
|
line.long 0x0C "PR,Timer Prescale Registers"
|
|
line.long 0x10 "PC,Timer Prescale Counter Register"
|
|
line.long 0x14 "MCR,Match Control Register"
|
|
bitfld.long 0x14 11. " MR3S ,Stop on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " MR3R ,Reset on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " MR3I ,Interrupt on MR3" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " MR2S ,Stop on MR2" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 7. " MR2R ,Reset on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " MR2I ,Interrupt on MR2" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " MR1S ,Stop on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " MR1R ,Reset on MR1" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 3. " MR1I ,Interrupt on MR1" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " MR0S ,Stop on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " MR0R ,Reset on MR0" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " MR0I ,Interrupt on MR0" "Disabled,Enabled"
|
|
line.long 0x18 "MR0,Timer Match Register"
|
|
line.long 0x1C "MR1,Timer Match Register"
|
|
line.long 0x20 "MR2,Timer Match Register"
|
|
line.long 0x24 "MR3,Timer Match Register"
|
|
line.long 0x28 "CCR,Capture Control Register"
|
|
bitfld.long 0x28 8. " CAP2L ,Generate interrupt on channel 2 capture event" "Not generated,Generated"
|
|
bitfld.long 0x28 7. " CAP2FE ,Falling edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x28 6. " CAP2RE ,Rising edge of capture channel 2" "Disabled,Enabled"
|
|
bitfld.long 0x28 5. " CAP1L ,Generate interrupt on channel 1 capture event" "Not generated,Generated"
|
|
newline
|
|
bitfld.long 0x28 4. " CAP1FE ,Falling edge of capture channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x28 3. " CAP1RE ,Rising edge of capture channel 1" "Disabled,Enabled"
|
|
bitfld.long 0x28 2. " CAP0I ,Generate interrupt on channel 0" "Not generated,Generated"
|
|
bitfld.long 0x28 1. " CAP0FE ,Falling edge of capture channel 0" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x28 0. " CAP0RE ,Rising edge of capture channel 0" "Disabled,Enabled"
|
|
line.long 0x2C "CR0,Timer Capture Register 0"
|
|
line.long 0x30 "CR1,Timer Capture Register 1"
|
|
line.long 0x34 "CR2,Timer Capture Register 2"
|
|
line.long 0x38 "EMR,External Match Register"
|
|
bitfld.long 0x38 10.--11. " EMC[3] ,External match control 3" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x38 8.--9. " [2] ,External match control 2" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x38 6.--7. " [1] ,External match control 1" "No effect,Clear,Set,Toggle"
|
|
bitfld.long 0x38 4.--5. " [0] ,External match control 0" "No effect,Clear,Set,Toggle"
|
|
newline
|
|
bitfld.long 0x38 3. " EM[3] ,External match 3" "Low,High"
|
|
bitfld.long 0x38 2. " [2] ,External match 2" "Low,High"
|
|
bitfld.long 0x38 1. " [1] ,External match 1" "Low,High"
|
|
bitfld.long 0x38 0. " [0] ,External match 0" "Low,High"
|
|
if (((per.l(ad:0x40050000+0x70))&0x10)==0x10)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTCR,Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "Ch 0 rising,Ch 0 falling,Ch 1 rising,Ch 1 falling,Ch 2 rising,Ch 2 falling,?..."
|
|
bitfld.long 0x00 4. " ENCC ,Enable clearing of the timer and the prescaler" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CINSEL ,Count input select" "Channel 0,Channel 1,Channel 2,?..."
|
|
bitfld.long 0x00 0.--1. " CTMODE ,Counter/timer mode" "Timer mode,Counter mode rising edge,Counter mode falling edge,Count mode dual edge"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CTCR,Count Control Register"
|
|
bitfld.long 0x00 5.--7. " SELCC ,Edge select" "No effect,No effect,No effect,No effect,No effect,No effect,?..."
|
|
bitfld.long 0x00 4. " ENCC ,Enable clearing of the timer and the prescaler" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " CINSEL ,Count input select" "Channel 0,Channel 1,Channel 2,?..."
|
|
bitfld.long 0x00 0.--1. " CTMODE ,Counter/timer mode" "Timer mode,Counter mode rising edge,Counter mode falling edge,Count mode dual edge"
|
|
endif
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "PWMC,PWM Control Register"
|
|
bitfld.long 0x00 3. " PWMEN[3] ,PWM mode enable for channel 3" "Match,PWM"
|
|
bitfld.long 0x00 2. " [2] ,PWM mode enable for channel 2" "Match,PWM"
|
|
bitfld.long 0x00 1. " [1] ,PWM mode enable for channel 1" "Match,PWM"
|
|
bitfld.long 0x00 0. " [0] ,PWM mode enable for channel 0" "Match,PWM"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "WDT (WatchDog Timer)"
|
|
base ad:0x40001000
|
|
width 9.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "LOAD,Watchdog Counter Start Value Register"
|
|
hexmask.long 0x00 0.--31. 1. " LOAD ,Contains the value from which the counter is to decrement"
|
|
line.long 0x04 "VALUE,Watchdog Counter Value Register"
|
|
hexmask.long 0x04 0.--31. 1. " VALUE ,The current value of the decrementing counter"
|
|
line.long 0x08 "CTRL,Watchdog Control Register"
|
|
bitfld.long 0x08 1. " RESEN ,Enable watchdog reset output WDOGRES" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " INTEN ,Enable the interrupt event WDOGINT" "Disabled,Enabled"
|
|
line.long 0x0C "INT_CLR,Interrupt Clear Register"
|
|
bitfld.long 0x0C 0. " INTCLR ,Cleat TheWatchdog interrupt and reloads the counter from the value in WDOGLOAD" "Cleared,Cleared"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "INT_RAW,Raw Interrupt Status Register"
|
|
bitfld.long 0x00 0. " RAWINTSTAT ,Raw interrupt status from the counter" "Not interrupted,Interrupted"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MIS,Interrupt Mask Register"
|
|
bitfld.long 0x00 0. " MASKINTSTAT ,Enabled interrupt status from counter" "Not interrupted,Interrupted"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "LOCK,Watchdog Lock Register"
|
|
hexmask.long 0x00 0.--31. 1. " LOCK_31_0 ,Writing 0x1ACCE551 enables write access to all other registers"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x4000B000
|
|
width 11.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTRL,RTC Control Register"
|
|
bitfld.long 0x00 8. " CAL_EN ,Calibration enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CFG ,RTC second configuration control" "Low,High"
|
|
bitfld.long 0x00 0. " SEC_INT_EN ,RTC second interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "STATUS,RTC Status Register"
|
|
rbitfld.long 0x04 31. " FREE_RUNNING_INT ,Free running interrupt status" "Not interrupted,Interrupted"
|
|
rbitfld.long 0x04 18. " THR_RST_SYNC ,THE_RST synchronization busy indicator" "Idle,Busy"
|
|
rbitfld.long 0x04 17. " THR_INT_SYNC ,THR_INT synchronization busy indicator" "Idle,Busy"
|
|
rbitfld.long 0x04 16. " FREE_SYNC ,CNT2_CTRL synchronization busy indicator" "Idle,Busy"
|
|
newline
|
|
rbitfld.long 0x04 12. " CALIB_SYNC ,CAL synchronization busy indicator" "Idle,Busy"
|
|
rbitfld.long 0x04 10. " SEC_SYNC ,SEC synchronization busy indicator" "Idle,Busy"
|
|
rbitfld.long 0x04 9. " STATUS_SYNC ,STATUS synchronization busy indicator" "Idle,Busy"
|
|
rbitfld.long 0x04 8. " CTRL_SYNC ,CTRL synchronization busy indicator" "Idle,Busy"
|
|
newline
|
|
eventfld.long 0x04 0. " SEC_INT ,Second interrupt flag" "Low,High"
|
|
line.long 0x08 "SEC,RTC Second Register"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CAL,RTC Calibration Register"
|
|
bitfld.long 0x00 16. " DIR ,RTC calibration direction indicator" "Forward,Backward"
|
|
hexmask.long.word 0x00 0.--15. 1. " PPM ,RTC calibration ppm value"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CNT_VAL,STC Count Value Register"
|
|
hexmask.long.word 0x00 0.--14. 1. " CNT ,RTC counter current value read only"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "CNT2_CTRL,Free Running Control Register"
|
|
bitfld.long 0x00 3. " CNT2_RST ,Enable free running reset" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CNT2_WAKEUP ,Enable free running wakeup" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CNT2_INT_EN ,Enable free running interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CNT2_EN ,Enable free running counter" "Disabled,Enabled"
|
|
line.long 0x04 "THR_INT,Interrupt Threshold Of Free Running Counter Register"
|
|
line.long 0x08 "THR_RST,Reset Threshold Of Free Running Counter Register"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CNT2,Free Running Count Value Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SYSTICK (CPU System Tick Timer)"
|
|
base ad:0xE000E000
|
|
width 7.
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "CSR,System Timer Control And Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,System tick counted to zero" "Not counted,Counted"
|
|
newline
|
|
sif cpuis("LPC11U*")
|
|
bitfld.long 0x00 2. " CLKSOURCE ,System tick clock source selection" "Sys clk/2,Sys clk"
|
|
else
|
|
bitfld.long 0x00 2. " CLKSOURCE ,System tick clock source selection" "32kHz,CLK_AHB"
|
|
endif
|
|
newline
|
|
bitfld.long 0x00 1. " TICKINT ,System tick interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,System tick counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "RVR,System Timer Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value loaded into the system tick counter when it counts to 0"
|
|
line.long 0x08 "CVR,System Timer Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Current value of the system tick counter"
|
|
line.long 0x0C "CALIB,System Timer Calibration Value Register"
|
|
bitfld.long 0x0C 31. " NOREF ,No separate reference clock is provided" "Provided,Not provided"
|
|
bitfld.long 0x0C 30. " SKEW ,TENMS value generate a precise/approximate time" "Precise,Approximate"
|
|
sif cpuis("LPC11U*")
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " TENMS ,Calibration value is not known"
|
|
else
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " TENMS ,Reload value from the SYS_TICK register in the SYSCON block"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "FSP (Fusion Signal Processing)"
|
|
base ad:0x40088000
|
|
width 18.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "SYS_CTRL,FSP System Control Register"
|
|
bitfld.long 0x00 2. " SCF_ABORT ,SE COR FIR abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 1. " MOU_ABORT ,Matrix operation unit abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 0. " TE_ABORT ,Transform engine abort" "Not aborted,Aborted"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,FSP Status Register"
|
|
bitfld.long 0x00 2. " FIR_READY ,FIR output buffer is not empty which is valid for read" "Not empty,Empty"
|
|
bitfld.long 0x00 1. " FPU1_BUSY ,TE MOU is in processing busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " FPU0_BUSY ,SE COR FIR is in processing busy" "Not busy,Busy"
|
|
group.long 0x08++0x07
|
|
line.long 0x00 "INT,FSP Interrupt Register"
|
|
rbitfld.long 0x00 31. " FSP_INT ,Or signal of all FSP function interrupt in this register" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " TALU_CALC_ERR_INT ,TALU calculation error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 25. " TALU_DOUT_ERR_INT ,TALU output data error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 24. " TALU_DIN_ERR_INT ,TALU input data error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " FINV_ZERO_INT ,FINV input data is zero interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 21. " FINV_DOUT_OV_INT ,FINV output data overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 20. " FINV_DIN_ERR_INT ,FINV input data is inf or nan interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 19. " FPU1_DOUT_OV_INT ,MOU TE output data overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " FPU1_DIN_OV_INT ,MOU TE input data overflow interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 17. " FPU1_CALC_OUT_ERR_INT ,MOU TE calculation output data error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " FPU1_CALC_IN_ERR_INT ,MOU TE calculation input data error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " SINGULAR_INT ,MOU singular interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 11. " FPU0_DOUT_OV_INT ,SE COR FIR output data overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " FPU0_DIN_OV_INT ,SE COR FIR input data overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " FPU0_CALC_OUT_ERR_INT ,SE COR FIR calculation output data error interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 8. " FPU0_CALC_IN_ERR_INT ,SE COR FIR calculation input data error interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " COR_DONE_INT ,Correlation done interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " SE_DONE_INT ,Statistic engine done interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x00 1. " MOU_DONE_INT ,Matrix operation unit done interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " TE_DONE_INT ,Transform engine done interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTEN,FSP Interrupt Enable Register"
|
|
bitfld.long 0x04 31. " FSP_INTEN ,Or signal of all FSP function interrupt in this register enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " TALU_CALC_ERR_INTEN ,TALU calculation error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 25. " TALU_DOUT_ERR_INTEN ,TALU output data error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 24. " TALU_DIN_ERR_INTEN ,TALU input data error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " FINV_ZERO_INTEN ,FINV input data is zero interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " FINV_DOUT_OV_INTEN ,FINV output data overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 20. " FINV_DIN_ERR_INTEN ,FINV input data is inf or nan interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " FPU1_DOUT_OV_INTEN ,MOU TE output data overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " FPU1_DIN_OV_INTEN ,MOU TE input data overflow interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 17. " FPU1_CALC_OUT_ERR_INTEN ,MOU TE calculation output data error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " FPU1_CALC_IN_ERR_INTEN ,MOU TE calculation input data error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " SINGULAR_INTEN ,MOU singular interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 11. " FPU0_DOUT_OV_INTEN ,SE COR FIR output data overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " FPU0_DIN_OV_INTEN ,SE COR FIR input data overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " FPU0_CALC_OUT_ERR_INTEN ,SE COR FIR calculation output data error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " FPU0_CALC_IN_ERR_INTEN ,SE COR FIR calculation input data error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " COR_DONE_INTEN ,Correlation done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SE_DONE_INTEN ,Statistic engine done interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 1. " MOU_DONE_INTEN ,Matrix operation unit done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TE_DONE_INTEN ,Transform engine done interrupt enable" "Disabled,Enabled"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "TE_CTRL,Transform Engine Control Register"
|
|
bitfld.long 0x00 24.--26. " TE_PAUSE_LVL ,Transform engine stop level for debug use only" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TE_SCALE ,TE scale"
|
|
bitfld.long 0x00 7. " TE_DOUT_FP_SEL ,TE output data format select" "Fixed,Floating"
|
|
newline
|
|
bitfld.long 0x00 6. " TE_DIN_FP_SEL ,TE input data format select" "Fixed,Floating"
|
|
bitfld.long 0x00 4.--5. " TE_PTS ,TE compute point" "64 points,128 points,256 points,"
|
|
bitfld.long 0x00 2.--3. " TE_IO_MODE ,TE input and output mode select [input/output]" "Real/Complex,Complex/Complex,Real/Real,Complex/Real"
|
|
newline
|
|
bitfld.long 0x00 0.--1. " TE_MODE ,TE compute mode" "FFT,IFFT,DCT,IDCT"
|
|
line.long 0x04 "TE_SRC_BASE,Transform Engine Source Data Memory Base Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " TE_SRC_BASE ,TE source data memory base address"
|
|
line.long 0x08 "TE_DST_BASE,Transform Engine Destination Data Memory Base Register"
|
|
hexmask.long.tbyte 0x08 0.--16. 1. " TE_DST_BASE ,TE destination data memory base address"
|
|
group.long 0x40++0x17
|
|
line.long 0x00 "MOU_CTRL,Matrix Operation Unit Control Register"
|
|
bitfld.long 0x00 31. " UING_STOP ,Stop at U-Matrix inverse" "Not stopped,Stopped"
|
|
bitfld.long 0x00 30. " LU_STOP ,Stop at LU" "Not stopped,Stopped"
|
|
bitfld.long 0x00 28.--29. " DIV_EPSILON ,Define minimum value in matrix inversion" "0,32,64,?..."
|
|
newline
|
|
bitfld.long 0x00 24.--27. " MAT_K ,MOU matrix row only valid when matrix mult operation" "1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 20.--23. " MAT_N ,MOU matrix row only valid when column of matrix is not equal to row" "1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 16.--19. " MAT_M ,MOU matrix column" "1,2,3,4,5,6,7,8,9,?..."
|
|
newline
|
|
bitfld.long 0x00 9. " MOU_DOUT_FP_SEL ,MOU data output format select" "Fixed,Floating"
|
|
bitfld.long 0x00 8. " MOU_DIN_FP_SEL ,MOU data input format select" "Fixed,Floating"
|
|
bitfld.long 0x00 0.--3. " OP_MODE ,MOU operation mode" "Inversion,Matrix multiply,Transposition,Linear operation,Dot multiply,?..."
|
|
line.long 0x04 "MA_SRC_BASE,Matrix A Source Data Memory Base Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 0x01 " MA_SRC_BASE ,Matrix A source data memory base address"
|
|
line.long 0x08 "MB_SRC_BASE,Matrix B Source Data Memory Base Register"
|
|
hexmask.long.tbyte 0x08 0.--16. 0x01 " MB_SRC_BASE ,Matrix B source data memory base address"
|
|
line.long 0x0C "MO_DST_BASE,Matrix Output Data Memory Base Register"
|
|
hexmask.long.tbyte 0x0C 0.--16. 0x01 " MB_SRC_BASE ,Matrix operation unit output data destination memory base address"
|
|
line.long 0x10 "MOU_SCALEA,Scale Coefficient A Register"
|
|
line.long 0x14 "MOU_SCALEB,Scale Coefficient B Register"
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "SE_CTRL,Static Engine Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SE_LEN ,Statistic engine length"
|
|
bitfld.long 0x00 7. " SE_DOUT_FP_SEL ,SE data output format select" "Fixed,Floating"
|
|
bitfld.long 0x00 6. " SE_DIN_FP_SEL ,SE data input format select" "Fixed,Floating"
|
|
newline
|
|
bitfld.long 0x00 5. " PWR_EN ,Power calculation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SUM_EN ,Summary calculation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MAX_IDX_EN ,Maximum value index calculation enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " MIN_ISC_EN ,Minimum value index calculation enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MAX_SEL ,Maximum value selection" "First one,Last one"
|
|
bitfld.long 0x00 0. " MIN_SEL ,Minimum value selection" "First one,Last one"
|
|
line.long 0x04 "SE_SRC_BASE,Statistic Engine Source Data Base Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " SE_SRC_BASE ,Statistic engine source data base address"
|
|
rgroup.long 0x68++0x0B
|
|
line.long 0x00 "SE_IDX,Max Or Min Data Index Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SE_MAX_IDX ,Maximum data index of an array"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SE_MIN_IDX ,Minimum data index of an array"
|
|
line.long 0x04 "SE_SUM,Array Summary Result Register"
|
|
line.long 0x08 "SE_PWR,Array Power Result Register"
|
|
group.long 0x80++0x13
|
|
line.long 0x00 "COR_CTRL,Correlation Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " COR_Y_LEN ,The length of Y sequence to be correlator 0-255"
|
|
hexmask.long.byte 0x00 16.--23. 1. " COR_X_LEN ,The length of X sequence to be correlator 0-255"
|
|
bitfld.long 0x00 9. " COR_DOUT_FP_SEL ,COR output data format select" "Fixed,Floating"
|
|
newline
|
|
bitfld.long 0x00 8. " COR_DIN_FP_SEL ,COR input data format select" "Fixed,Floating"
|
|
line.long 0x04 "CX_SRC_BASE,Correlation X Sequence Base Register"
|
|
hexmask.long.tbyte 0x04 0.--16. 1. " COR_X_ADDR ,The base address of X sequence to be correlator"
|
|
line.long 0x08 "CY_SRC_BASE,Correlation Y Sequence Base Register"
|
|
hexmask.long.tbyte 0x08 0.--16. 1. " COR_Y_ADDR ,The base address of Y sequence to be correlator"
|
|
line.long 0x0C "CO_DST_BASE,Correlation Output Sequence Base Register"
|
|
hexmask.long.tbyte 0x0C 0.--16. 1. " COR_DST_BASE ,Correlation output data destination address base"
|
|
line.long 0x10 "COR_OFFSET,Correlation Offset Register"
|
|
hexmask.long.byte 0x10 8.--15. 0x1 " COR_Y_OFFSET ,COR input Y SEQ offset 0-255"
|
|
hexmask.long.byte 0x10 0.--7. 1. " COR_X_OFFSET ,COR input X SEQ offset 0-255"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "FIR_CFG_CH0,FIR Channel 0 Configuration Register"
|
|
bitfld.long 0x00 31. " FIR_CH0_BUF_CLR ,FIR channel 0 buffer clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 30. " FIR_BUF_CLR_ALL ,Clear all FIR buffer" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16.--19. " FIR_CH0_TAP_LEN ,FIR channel 0 tal length minus 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 0x01 " FIR_CH0_COEF_BASE ,FIR channel 0 coefficient base address"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "FIR_CFG_CH1,FIR Channel 1 Configuration Register"
|
|
bitfld.long 0x00 31. " FIR_CH1_BUF_CLR ,FIR channel 1 buffer clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16.--19. " FIR_CH1_TAP_LEN ,FIR channel 1 tal length minus 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " FIR_CH1_COEF_BASE ,FIR channel 1 coefficient base address"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "FIR_CFG_CH2,FIR Channel 2 Configuration Register"
|
|
bitfld.long 0x00 31. " FIR_CH2_BUF_CLR ,FIR channel 2 buffer clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16.--19. " FIR_CH2_TAP_LEN ,FIR channel 2 tal length minus 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " FIR_CH2_COEF_BASE ,FIR channel 2 coefficient base address"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "FIR_CFG_CH3,FIR Channel 3 Configuration Register"
|
|
bitfld.long 0x00 31. " FIR_CH3_BUF_CLR ,FIR channel 3 buffer clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16.--19. " FIR_CH3_TAP_LEN ,FIR channel 3 tal length minus 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " FIR_CH3_COEF_BASE ,FIR channel 3 coefficient base address"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "FIR_CFG_CH4,FIR Channel 4 Configuration Register"
|
|
bitfld.long 0x00 31. " FIR_CH4_BUF_CLR ,FIR channel 4 buffer clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16.--19. " FIR_CH4_TAP_LEN ,FIR channel 4 tal length minus 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " FIR_CH4_COEF_BASE ,FIR channel 4 coefficient base address"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "FIR_CFG_CH5,FIR Channel 5 Configuration Register"
|
|
bitfld.long 0x00 31. " FIR_CH5_BUF_CLR ,FIR channel 5 buffer clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16.--19. " FIR_CH5_TAP_LEN ,FIR channel 5 tal length minus 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " FIR_CH5_COEF_BASE ,FIR channel 5 coefficient base address"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "FIR_CFG_CH6,FIR Channel 6 Configuration Register"
|
|
bitfld.long 0x00 31. " FIR_CH6_BUF_CLR ,FIR channel 6 buffer clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16.--19. " FIR_CH6_TAP_LEN ,FIR channel 6 tal length minus 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " FIR_CH6_COEF_BASE ,FIR channel 6 coefficient base address"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "FIR_CFG_CH7,FIR Channel 7 Configuration Register"
|
|
bitfld.long 0x00 31. " FIR_CH7_BUF_CLR ,FIR channel 7 buffer clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16.--19. " FIR_CH7_TAP_LEN ,FIR channel 7 tal length minus 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " FIR_CH7_COEF_BASE ,FIR channel 7 coefficient base address"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "FIR_CFG_CH8,FIR Channel 8 Configuration Register"
|
|
bitfld.long 0x00 31. " FIR_CH8_BUF_CLR ,FIR channel 8 buffer clear" "Not cleared,Cleared"
|
|
bitfld.long 0x00 16.--19. " FIR_CH8_TAP_LEN ,FIR channel 8 tal length minus 1" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " FIR_CH8_COEF_BASE ,FIR channel 8 coefficient base address"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "FIR_DAT0_FX,FIR Channel 0 Fixed Point Data Input And Output Register"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "FIR_DAT1_FX,FIR Channel 1 Fixed Point Data Input And Output Register"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "FIR_DAT2_FX,FIR Channel 2 Fixed Point Data Input And Output Register"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "FIR_DAT3_FX,FIR Channel 3 Fixed Point Data Input And Output Register"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "FIR_DAT4_FX,FIR Channel 4 Fixed Point Data Input And Output Register"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "FIR_DAT5_FX,FIR Channel 5 Fixed Point Data Input And Output Register"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "FIR_DAT6_FX,FIR Channel 6 Fixed Point Data Input And Output Register"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "FIR_DAT7_FX,FIR Channel 7 Fixed Point Data Input And Output Register"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "FIR_DAT8_FX,FIR Channel 8 Fixed Point Data Input And Output Register"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "FIR_DAT0_FL,FIR Channel 0 Floating Point Data Input And Output Register"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "FIR_DAT1_FL,FIR Channel 1 Floating Point Data Input And Output Register"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "FIR_DAT2_FL,FIR Channel 2 Floating Point Data Input And Output Register"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "FIR_DAT3_FL,FIR Channel 3 Floating Point Data Input And Output Register"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "FIR_DAT4_FL,FIR Channel 4 Floating Point Data Input And Output Register"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "FIR_DAT5_FL,FIR Channel 5 Floating Point Data Input And Output Register"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "FIR_DAT6_FL,FIR Channel 6 Floating Point Data Input And Output Register"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "FIR_DAT7_FL,FIR Channel 7 Floating Point Data Input And Output Register"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "FIR_DAT8_FL,FIR Channel 8 Floating Point Data Input And Output Register"
|
|
wgroup.long 0x140++0x5F
|
|
line.long 0x00 "SIN_COS_IXOX,Sin And Cos Input Fixed Output Fixed Mode Data Address Register"
|
|
hexmask.long.word 0x00 16.--31. 0x01 " SIN_COS_IXOX_DST ,SIN_COS output data destination address"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " SIN_COS_IXOX_SRC ,SIN_COS input data source address"
|
|
line.long 0x04 "SIN_COS_IXOL,Sin And Cos Input Fixed Output Floating Mode Data Address Register"
|
|
hexmask.long.word 0x04 16.--31. 0x01 " SIN_COS_IXOL_DST ,SIN_COS output data destination address"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " SIN_COS_IXOL_SRC ,SIN_COS input data source address"
|
|
line.long 0x08 "SIN_COS_ILOX,Sin And Cos Input Floating Output Fixed Mode Data Address Register"
|
|
hexmask.long.word 0x08 16.--31. 0x01 " SIN_COS_ILOX_DST ,SIN_COS output data destination address"
|
|
hexmask.long.word 0x08 0.--15. 0x01 " SIN_COS_ILOX_SRC ,SIN_COS input data source address"
|
|
line.long 0x0C "SIN_COS_ILOL,Sin And Cos Input Floating Output Floating Mode Data Address Register"
|
|
hexmask.long.word 0x0C 16.--31. 0x01 " SIN_COS_ILOL_DST ,SIN_COS output data destination address"
|
|
hexmask.long.word 0x0C 0.--15. 0x01 " SIN_COS_ILOL_SRC ,SIN_COS input data source address"
|
|
line.long 0x10 "LN_SQRT_IXOX,LN And Sqrt Input Fixed Output Fixed Mode Data Address Register"
|
|
hexmask.long.word 0x10 16.--31. 0x01 " LN_SQRT_IXOX_DST ,LN_SQRT output data destination address"
|
|
hexmask.long.word 0x10 0.--15. 0x01 " LN_SQRT_IXOX_SRC ,LN_SQRT input data source address"
|
|
line.long 0x14 "LN_SQRT_IXOL,LN And Sqrt Input Fixed Output Floating Mode Data Address Register"
|
|
hexmask.long.word 0x14 16.--31. 0x01 " LN_SQRT_IXOL_DST ,LN_SQRT output data destination address"
|
|
hexmask.long.word 0x14 0.--15. 0x01 " LN_SQRT_IXOL_SRC ,LN_SQRT input data source address"
|
|
line.long 0x18 "LN_SQRT_ILOX,LN And Sqrt Input Floating Output Fixed Mode Data Address Register"
|
|
hexmask.long.word 0x18 16.--31. 0x01 " LN_SQRT_ILOX_DST ,LN_SQRT output data destination address"
|
|
hexmask.long.word 0x18 0.--15. 0x01 " LN_SQRT_ILOX_SRC ,LN_SQRT input data source address"
|
|
line.long 0x1C "LN_SQRT_ILOL,LN And Sqrt Input Floating Output Floating Mode Data Address Register"
|
|
hexmask.long.word 0x1C 16.--31. 0x01 " LN_SQRT_ILOL_DST ,LN_SQRT output data destination address"
|
|
hexmask.long.word 0x1C 0.--15. 0x01 " LN_SQRT_ILOL_SRC ,LN_SQRT input data source address"
|
|
line.long 0x20 "CORDIC_T0UP_IXOX,Native Cordic Input Fixed Output Fixed Mode Data Address Register"
|
|
hexmask.long.word 0x20 16.--31. 0x01 " CORDIC_T0UP_IXOX_DST ,CORDIC_T0UP output data destination address"
|
|
hexmask.long.word 0x20 0.--15. 0x01 " CORDIC_T0UP_IXOX_SRC ,CORDIC_T0UP input data source address"
|
|
line.long 0x24 "CORDIC_T0UP_IXOL,Native Cordic Input Fixed Output Floating Mode Data Address Register"
|
|
hexmask.long.word 0x24 16.--31. 0x01 " CORDIC_T0UP_IXOL_DST ,CORDIC_T0UP output data destination address"
|
|
hexmask.long.word 0x24 0.--15. 0x01 " CORDIC_T0UP_IXOL_SRC ,CORDIC_T0UP input data source address"
|
|
line.long 0x28 "CORDIC_T0UP_ILOX,Native Cordic Input Floating Output Fixed Mode Data Address Register"
|
|
hexmask.long.word 0x28 16.--31. 0x01 " CORDIC_T0UP_ILOX_DST ,CORDIC_T0UP output data destination address"
|
|
hexmask.long.word 0x28 0.--15. 0x01 " CORDIC_T0UP_ILOX_SRC ,CORDIC_T0UP input data source address"
|
|
line.long 0x2C "CORDIC_T0UP_ILOL,Native Cordic Input Floating Output Floating Mode Data Address Register"
|
|
hexmask.long.word 0x2C 16.--31. 0x01 " CORDIC_T0UP_ILOL_DST ,CORDIC_T0UP output data destination address"
|
|
hexmask.long.word 0x2C 0.--15. 0x01 " CORDIC_T0UP_ILOL_SRC ,CORDIC_T0UP input data source address"
|
|
line.long 0x30 "CORDIC_T0UN_IXOX,Native Cordic Input Fixed Output Fixed Mode Data Address Register"
|
|
hexmask.long.word 0x30 16.--31. 0x01 " CORDIC_T0UN_IXOX_DST ,CORDIC_T0UN output data destination address"
|
|
hexmask.long.word 0x30 0.--15. 0x01 " CORDIC_T0UN_IXOX_SRC ,CORDIC_T0UN input data source address"
|
|
line.long 0x34 "CORDIC_T0UN_IXOL,Native Cordic Input Fixed Output Floating Mode Data Address Register"
|
|
hexmask.long.word 0x34 16.--31. 0x01 " CORDIC_T0UN_IXOL_DST ,CORDIC_T0UN output data destination address"
|
|
hexmask.long.word 0x34 0.--15. 0x01 " CORDIC_T0UN_IXOL_SRC ,CORDIC_T0UN input data source address"
|
|
line.long 0x38 "CORDIC_T0UN_ILOX,Native Cordic Input Floating Output Fixed Mode Data Address Register"
|
|
hexmask.long.word 0x38 16.--31. 0x01 " CORDIC_T0UN_ILOX_DST ,CORDIC_T0UN output data destination address"
|
|
hexmask.long.word 0x38 0.--15. 0x01 " CORDIC_T0UN_ILOX_SRC ,CORDIC_T0UN input data source address"
|
|
line.long 0x3C "CORDIC_T0UN_ILOL,Native Cordic Input Floating Output Floating Mode Data Address Register"
|
|
hexmask.long.word 0x3C 16.--31. 0x01 " CORDIC_T0UN_ILOL_DST ,CORDIC_T0UN output data destination address"
|
|
hexmask.long.word 0x3C 0.--15. 0x01 " CORDIC_T0UN_ILOL_SRC ,CORDIC_T0UN input data source address"
|
|
line.long 0x40 "CORDIC_T1UP_IXOX,Native Cordic Input Fixed Output Fixed Mode Data Address Register"
|
|
hexmask.long.word 0x40 16.--31. 0x01 " CORDIC_T1UP_IXOX_DST ,CORDIC_T1UP output data destination address"
|
|
hexmask.long.word 0x40 0.--15. 0x01 " CORDIC_T1UP_IXOX_SRC ,CORDIC_T1UP input data source address"
|
|
line.long 0x44 "CORDIC_T1UP_IXOL,Native Cordic Input Fixed Output Floating Mode Data Address Register"
|
|
hexmask.long.word 0x44 16.--31. 0x01 " CORDIC_T1UP_IXOL_DST ,CORDIC_T1UP output data destination address"
|
|
hexmask.long.word 0x44 0.--15. 0x01 " CORDIC_T1UP_IXOL_SRC ,CORDIC_T1UP input data source address"
|
|
line.long 0x48 "CORDIC_T1UP_ILOX,Native Cordic Input Floating Output Fixed Mode Data Address Register"
|
|
hexmask.long.word 0x48 16.--31. 0x01 " CORDIC_T1UP_ILOX_DST ,CORDIC_T1UP output data destination address"
|
|
hexmask.long.word 0x48 0.--15. 0x01 " CORDIC_T1UP_ILOX_SRC ,CORDIC_T1UP input data source address"
|
|
line.long 0x4C "CORDIC_T1UP_ILOL,Native Cordic Input Floating Output Floating Mode Data Address Register"
|
|
hexmask.long.word 0x4C 16.--31. 0x01 " CORDIC_T1UP_ILOL_DST ,CORDIC_T1UP output data destination address"
|
|
hexmask.long.word 0x4C 0.--15. 0x01 " CORDIC_T1UP_ILOL_SRC ,CORDIC_T1UP input data source address"
|
|
line.long 0x50 "CORDIC_T1UN_IXOX,Native Cordic Input Fixed Output Fixed Mode Data Address Register"
|
|
hexmask.long.word 0x50 16.--31. 0x01 " CORDIC_T1UN_IXOX_DST ,CORDIC_T1UN output data destination address"
|
|
hexmask.long.word 0x50 0.--15. 0x01 " CORDIC_T1UN_IXOX_SRC ,CORDIC_T1UN input data source address"
|
|
line.long 0x54 "CORDIC_T1UN_IXOL,Native Cordic Input Fixed Output Floating Mode Data Address Register"
|
|
hexmask.long.word 0x54 16.--31. 0x01 " CORDIC_T1UN_IXOL_DST ,CORDIC_T1UN output data destination address"
|
|
hexmask.long.word 0x54 0.--15. 0x01 " CORDIC_T1UN_IXOL_SRC ,CORDIC_T1UN input data source address"
|
|
line.long 0x58 "CORDIC_T1UN_ILOX,Native Cordic Input Floating Output Fixed Mode Data Address Register"
|
|
hexmask.long.word 0x58 16.--31. 0x01 " CORDIC_T1UN_ILOX_DST ,CORDIC_T1UN output data destination address"
|
|
hexmask.long.word 0x58 0.--15. 0x01 " CORDIC_T1UN_ILOX_SRC ,CORDIC_T1UN input data source address"
|
|
line.long 0x5C "CORDIC_T1UN_ILOL,Native Cordic Input Floating Output Floating Mode Data Address Register"
|
|
hexmask.long.word 0x5C 16.--31. 0x01 " CORDIC_T1UN_ILOL_DST ,CORDIC_T1UN output data destination address"
|
|
hexmask.long.word 0x5C 0.--15. 0x01 " CORDIC_T1UN_ILOL_SRC ,CORDIC_T1UN input data source address"
|
|
width 0x0B
|
|
tree.end
|
|
tree "USB 2.0 (USB 2.0 Device Controller)"
|
|
base ad:0x40084000
|
|
width 16.
|
|
group.long 0x00++0x2B
|
|
line.long 0x00 "DEVCMDSTAT,USB Device Command/Status Register"
|
|
rbitfld.long 0x00 28. " VBUCDEBOUNCED ,Indicated if Vbus is detected or not" "Not detected,Detected"
|
|
bitfld.long 0x00 26. " DRES_C ,Device status - reset change" "Not occurred,Occurred"
|
|
bitfld.long 0x00 25. " DSUS_C ,Device status - suspend change" "Not occurred,Occurred"
|
|
bitfld.long 0x00 24. " DCON_C ,Device status - connect change" "Not occurred,Occurred"
|
|
newline
|
|
rbitfld.long 0x00 20. " LPM_REWP ,LPM remote wake-up enabled by USB host" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " LPM_SUS ,Device status - LPM suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 17. " DSUS ,Device status - suspend" "Not suspended,Suspended"
|
|
bitfld.long 0x00 16. " DCON ,Device status - connect" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 15. " INTONNAK_CI ,Interrupt on NAK for control IN EP" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " INTONNAK_CO ,Interrupt on NAK for control OUT EP" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " INTONNAK_AI ,Interrupt on NAK for interrupt and bulk IN EP" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INTONNAK_AO ,Interrupt on NAK for interrupt and bulk OUT EP" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 11. " LPM_SUP ,LPM not supported" "Not supported,Supported"
|
|
bitfld.long 0x00 9. " FORCE_NEEDCLK ,Forces the NEEDCLK output to always be on" "Not forced,Forced"
|
|
bitfld.long 0x00 8. " SETUP ,SETUP token received" "Not received,Received"
|
|
bitfld.long 0x00 7. " DEV_EN ,USB device enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. " DEV_ADDR ,USB device address"
|
|
line.long 0x04 "INFO,USB Info Register"
|
|
bitfld.long 0x04 11.--14. " ERR_CODE ,Error code which last occurred" "No error,PID encoding error,PIR unknown,Packet unexpected,Token CRC error,Data CRC error,Time out,Babble,Truncated EOP,Sent/receiver NAK,Sent stall,Overrun,Sent empty packet,Bitstuff error,Sync error,Wrong data toggle"
|
|
hexmask.long.word 0x04 0.--10. 1. " FRAME_NR ,Frame number"
|
|
line.long 0x08 "EPLISTSTART,USB EP Command/Status List Start Address"
|
|
hexmask.long.tbyte 0x08 8.--31. 0x1 " EP_LIST ,Start address of the YSB EP command/status list"
|
|
line.long 0x0C "DATABUFSTART,USB Data Buffer Start Address"
|
|
hexmask.long.word 0x0C 22.--31. 0x40 " DA_BUF ,Start address of the buffer pointer page"
|
|
line.long 0x10 "LPM,USB Link Power Management Register"
|
|
bitfld.long 0x10 8. " DATA_PENDING ,Handshake type" "ACK handshake,NYET handshake"
|
|
bitfld.long 0x10 4.--7. " HIRD_SW ,Host initiated resume duration - SW" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
rbitfld.long 0x10 0.--3. " HIRD_HW ,Host initiated resume duration - HW" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x14 "EPSKIP,USB Endpoint Skip"
|
|
bitfld.long 0x14 29. " SKIP[29] ,Endpoint 29 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 28. " [28] ,Endpoint 28 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 27. " [27] ,Endpoint 27 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 26. " [26] ,Endpoint 26 skip request" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x14 25. " [25] ,Endpoint 25 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 24. " [24] ,Endpoint 24 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 23. " [23] ,Endpoint 23 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 22. " [22] ,Endpoint 22 skip request" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x14 21. " [21] ,Endpoint 21 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 20. " [20] ,Endpoint 20 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 19. " [19] ,Endpoint 19 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 18. " [18] ,Endpoint 18 skip request" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x14 17. " [17] ,Endpoint 17 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 16. " [16] ,Endpoint 16 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 15. " [15] ,Endpoint 15 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 14. " [14] ,Endpoint 14 skip request" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x14 13. " [13] ,Endpoint 13 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 12. " [12] ,Endpoint 12 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 11. " [11] ,Endpoint 11 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 10. " [10] ,Endpoint 10 skip request" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x14 9. " [9] ,Endpoint 9 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 8. " [8] ,Endpoint 8 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 7. " [7] ,Endpoint 7 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 6. " [6] ,Endpoint 6 skip request" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x14 5. " [5] ,Endpoint 5 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 4. " [4] ,Endpoint 4 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 3. " [3] ,Endpoint 3 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 2. " [2] ,Endpoint 2 skip request" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x14 1. " [1] ,Endpoint 1 skip request" "Not occurred,Occurred"
|
|
bitfld.long 0x14 0. " [0] ,Endpoint 0 skip request" "Not occurred,Occurred"
|
|
line.long 0x18 "EPINUSE,USB Endpoint Buffer In Use"
|
|
bitfld.long 0x18 9. " BUF[9] ,Buffer 9 in use" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x18 8. " [8] ,Buffer 8 in use" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x18 7. " [7] ,Buffer 7 in use" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x18 6. " [6] ,Buffer 6 in use" "Buffer 0,Buffer 1"
|
|
newline
|
|
bitfld.long 0x18 5. " [5] ,Buffer 5 in use" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x18 4. " [4] ,Buffer 4 in use" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x18 3. " [3] ,Buffer 3 in use" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x18 2. " [2] ,Buffer 2 in use" "Buffer 0,Buffer 1"
|
|
newline
|
|
bitfld.long 0x18 1. " [1] ,Buffer 1 in use" "Buffer 0,Buffer 1"
|
|
bitfld.long 0x18 0. " [0] ,Buffer 0 in use" "Buffer 0,Buffer 1"
|
|
line.long 0x1C "EPBUFCFG,USB Endpoint Buffer Configuration Register"
|
|
bitfld.long 0x1C 9. " BUF_SB[9] ,Buffer usage bit 9" "Single-buffer,Double-buffer"
|
|
bitfld.long 0x1C 8. " [8] ,Buffer usage bit 8" "Single-buffer,Double-buffer"
|
|
bitfld.long 0x1C 7. " [7] ,Buffer usage bit 7" "Single-buffer,Double-buffer"
|
|
bitfld.long 0x1C 6. " [6] ,Buffer usage bit 6" "Single-buffer,Double-buffer"
|
|
newline
|
|
bitfld.long 0x1C 5. " [5] ,Buffer usage bit 5" "Single-buffer,Double-buffer"
|
|
bitfld.long 0x1C 4. " [4] ,Buffer usage bit 4" "Single-buffer,Double-buffer"
|
|
bitfld.long 0x1C 3. " [3] ,Buffer usage bit 3" "Single-buffer,Double-buffer"
|
|
bitfld.long 0x1C 2. " [2] ,Buffer usage bit 2" "Single-buffer,Double-buffer"
|
|
newline
|
|
bitfld.long 0x1C 1. " [1] ,Buffer usage bit 1" "Single-buffer,Double-buffer"
|
|
bitfld.long 0x1C 0. " [0] ,Buffer usage bit 0" "Single-buffer,Double-buffer"
|
|
line.long 0x20 "INTSTAT,USB Interrupt Status Register"
|
|
bitfld.long 0x20 31. " DEV_INT ,Device status interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 30. " FRAME_INT ,Frame interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 15. " EP7IN ,Interrupt status register bit for the EP7 IN direction" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 14. " EP7OUT ,Interrupt status register bit for the EP7 OUT direction" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x20 13. " EP6IN ,Interrupt status register bit for the EP6 IN direction" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 12. " EP6OUT ,Interrupt status register bit for the EP6 OUT direction" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 11. " EP5IN ,Interrupt status register bit for the EP5 IN direction" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 10. " EP5OUT ,Interrupt status register bit for the EP5 OUT direction" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x20 9. " EP4IN ,Interrupt status register bit for the EP4 IN direction" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 8. " EP4OUT ,Interrupt status register bit for the EP4 OUT direction" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 7. " EP3IN ,Interrupt status register bit for the EP3 IN direction" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 6. " EP3OUT ,Interrupt status register bit for the EP3 OUT direction" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x20 5. " EP2IN ,Interrupt status register bit for the EP2 IN direction" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 4. " EP2OUT ,Interrupt status register bit for the EP2 OUT direction" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 3. " EP1IN ,Interrupt status register bit for the EP1 IN direction" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 2. " EP1OUT ,Interrupt status register bit for the EP1 OUT direction" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x20 1. " EP0IN ,Interrupt status register bit for the EP0 IN direction" "No interrupt,Interrupt"
|
|
bitfld.long 0x20 0. " EP0OUT ,Interrupt status register bit for the EP0 OUT direction" "No interrupt,Interrupt"
|
|
line.long 0x24 "INTEN,USB Interrupt Enable Register"
|
|
bitfld.long 0x24 31. " DEV_INT_EN ,Device interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 30. " FRAME_INT_EN ,Frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x24 15. " EP_INT_EN[15] ,Endpoint 15 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 14. " [14] ,Endpoint 14 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 13. " [13] ,Endpoint 13 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 12. " [12] ,Endpoint 12 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 11. " [11] ,Endpoint 11 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 10. " [10] ,Endpoint 10 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 9. " [9] ,Endpoint 9 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 8. " [8] ,Endpoint 8 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 7. " [7] ,Endpoint 7 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 6. " [6] ,Endpoint 6 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 5. " [5] ,Endpoint 5 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 4. " [4] ,Endpoint 4 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 3. " [3] ,Endpoint 3 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 2. " [2] ,Endpoint 2 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x24 1. " [1] ,Endpoint 1 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " [0] ,Endpoint 0 interrupt enable by corresponding USB interrupt routing bit" "Disabled,Enabled"
|
|
line.long 0x28 "INTSETSTAT,USB Set Interrupt Status Register"
|
|
bitfld.long 0x28 31. " DEV_SET_INT ,Device interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 30. " FRAME_SET_INT ,Frame interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 15. " EP_SET_INT[15] ,Endpoint 15 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 14. " [14] ,Endpoint 14 interrupt status set" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x28 13. " [13] ,Endpoint 13 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 12. " [12] ,Endpoint 12 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 11. " [11] ,Endpoint 11 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 10. " [10] ,Endpoint 10 interrupt status set" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x28 9. " [9] ,Endpoint 9 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 8. " [8] ,Endpoint 8 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 7. " [7] ,Endpoint 7 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 6. " [6] ,Endpoint 6 interrupt status set" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x28 5. " [5] ,Endpoint 5 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 4. " [4] ,Endpoint 4 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 3. " [3] ,Endpoint 3 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 2. " [2] ,Endpoint 2 interrupt status set" "Not set,Set"
|
|
newline
|
|
bitfld.long 0x28 1. " [1] ,Endpoint 1 interrupt status set" "Not set,Set"
|
|
bitfld.long 0x28 0. " [0] ,Endpoint 0 interrupt status set" "Not set,Set"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "EPTOGGLE,USB Endpoint Toggle Register"
|
|
bitfld.long 0x00 15. " EP7IN_TOGGLE ,Endpoint EP7IN data toggle value" "0,1"
|
|
bitfld.long 0x00 14. " EP7OUT_TOGGLE ,Endpoint EP7OUT data toggle value" "0,1"
|
|
bitfld.long 0x00 13. " EP6IN_TOGGLE ,Endpoint EP6IN data toggle value" "0,1"
|
|
bitfld.long 0x00 12. " EP6OUT_TOGGLE ,Endpoint EP6OUT data toggle value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. " EP5IN_TOGGLE ,Endpoint EP5IN data toggle value" "0,1"
|
|
bitfld.long 0x00 10. " EP5OUT_TOGGLE ,Endpoint EP5OUT data toggle value" "0,1"
|
|
bitfld.long 0x00 9. " EP4IN_TOGGLE ,Endpoint EP4IN data toggle value" "0,1"
|
|
bitfld.long 0x00 8. " EP4OUT_TOGGLE ,Endpoint EP4OUT data toggle value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. " EP3IN_TOGGLE ,Endpoint EP3IN data toggle value" "0,1"
|
|
bitfld.long 0x00 6. " EP3OUT_TOGGLE ,Endpoint EP3OUT data toggle value" "0,1"
|
|
bitfld.long 0x00 5. " EP2IN_TOGGLE ,Endpoint EP2IN data toggle value" "0,1"
|
|
bitfld.long 0x00 4. " EP2OUT_TOGGLE ,Endpoint EP2OUT data toggle value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " EP1IN_TOGGLE ,Endpoint EP1IN data toggle value" "0,1"
|
|
bitfld.long 0x00 2. " EP1OUT_TOGGLE ,Endpoint EP1OUT data toggle value" "0,1"
|
|
bitfld.long 0x00 1. " EP0IN_TOGGLE ,Endpoint EP0IN data toggle value" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. " EP0OUT_TOGGLE ,Endpoint EP0OUT data toggle value" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "FISC (Flexcomm Interface Serial Communication)"
|
|
tree "Flexcomm 0"
|
|
base ad:0x40083000
|
|
width 8.
|
|
if (((per.l(ad:0x40083000+0xFF8))&0x07)==0x01)
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "IOMODE,IO Mode Register"
|
|
bitfld.long 0x00 1. " DIO_OEN ,Indicates IO output enable" "Input,Output"
|
|
bitfld.long 0x00 0. " DIO_MODE ,IO mode register" "USART,7816"
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x07)==0x02)
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "IOMODE,IO Mode Register"
|
|
bitfld.long 0x00 1. " DIO_OEN ,Indicates IO output enable" "Input,Output"
|
|
bitfld.long 0x00 0. " DIO_MODE ,IO mode register" "SPI,3-wire SPI"
|
|
else
|
|
hgroup.long 0xF00++0x03
|
|
hide.long 0x00 "IOMODE,IO Mode Register"
|
|
endif
|
|
if (((per.l(ad:0x40083000+0xFF8))&0x08)==0x08)
|
|
if (((per.l(ad:0x40083000+0xFF8))&0x70)==0x70)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x30)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x50)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,,I2C,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x10)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x60)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x20)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x40)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,,I2C,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x00)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,?..."
|
|
endif
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x08)==0x00)
|
|
if (((per.l(ad:0x40083000+0xFF8))&0x70)==0x70)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x30)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x50)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,,I2C,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x10)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x60)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x20)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x40)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,,I2C,?..."
|
|
elif (((per.l(ad:0x40083000+0xFF8))&0x70)==0x00)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,?..."
|
|
endif
|
|
endif
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "PID,Peripheral Identification Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ID ,Module identifier for the selected function"
|
|
bitfld.long 0x00 12.--15. " MAJOR_REV ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " MINOR_REV ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Flexcomm 1"
|
|
base ad:0x40086000
|
|
width 8.
|
|
if (((per.l(ad:0x40086000+0xFF8))&0x07)==0x01)
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "IOMODE,IO Mode Register"
|
|
bitfld.long 0x00 1. " DIO_OEN ,Indicates IO output enable" "Input,Output"
|
|
bitfld.long 0x00 0. " DIO_MODE ,IO mode register" "USART,7816"
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x07)==0x02)
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "IOMODE,IO Mode Register"
|
|
bitfld.long 0x00 1. " DIO_OEN ,Indicates IO output enable" "Input,Output"
|
|
bitfld.long 0x00 0. " DIO_MODE ,IO mode register" "SPI,3-wire SPI"
|
|
else
|
|
hgroup.long 0xF00++0x03
|
|
hide.long 0x00 "IOMODE,IO Mode Register"
|
|
endif
|
|
if (((per.l(ad:0x40086000+0xFF8))&0x08)==0x08)
|
|
if (((per.l(ad:0x40086000+0xFF8))&0x70)==0x70)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x30)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x50)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,,I2C,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x10)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x60)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x20)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x40)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,,I2C,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x00)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,?..."
|
|
endif
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x08)==0x00)
|
|
if (((per.l(ad:0x40086000+0xFF8))&0x70)==0x70)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x30)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x50)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,,I2C,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x10)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x60)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x20)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x40)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,,I2C,?..."
|
|
elif (((per.l(ad:0x40086000+0xFF8))&0x70)==0x00)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,?..."
|
|
endif
|
|
endif
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "PID,Peripheral Identification Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ID ,Module identifier for the selected function"
|
|
bitfld.long 0x00 12.--15. " MAJOR_REV ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " MINOR_REV ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Flexcomm 2"
|
|
base ad:0x40087000
|
|
width 8.
|
|
if (((per.l(ad:0x40087000+0xFF8))&0x07)==0x01)
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "IOMODE,IO Mode Register"
|
|
bitfld.long 0x00 1. " DIO_OEN ,Indicates IO output enable" "Input,Output"
|
|
bitfld.long 0x00 0. " DIO_MODE ,IO mode register" "USART,7816"
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x07)==0x02)
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "IOMODE,IO Mode Register"
|
|
bitfld.long 0x00 1. " DIO_OEN ,Indicates IO output enable" "Input,Output"
|
|
bitfld.long 0x00 0. " DIO_MODE ,IO mode register" "SPI,3-wire SPI"
|
|
else
|
|
hgroup.long 0xF00++0x03
|
|
hide.long 0x00 "IOMODE,IO Mode Register"
|
|
endif
|
|
if (((per.l(ad:0x40087000+0xFF8))&0x08)==0x08)
|
|
if (((per.l(ad:0x40087000+0xFF8))&0x70)==0x70)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x30)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x50)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,,I2C,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x10)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x60)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x20)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x40)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,,I2C,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x00)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,?..."
|
|
endif
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x08)==0x00)
|
|
if (((per.l(ad:0x40087000+0xFF8))&0x70)==0x70)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x30)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x50)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,,I2C,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x10)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x60)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x20)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x40)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,,I2C,?..."
|
|
elif (((per.l(ad:0x40087000+0xFF8))&0x70)==0x00)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,?..."
|
|
endif
|
|
endif
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "PID,Peripheral Identification Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ID ,Module identifier for the selected function"
|
|
bitfld.long 0x00 12.--15. " MAJOR_REV ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " MINOR_REV ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Flexcomm 3"
|
|
base ad:0x4008F000
|
|
width 8.
|
|
if (((per.l(ad:0x4008F000+0xFF8))&0x07)==0x01)
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "IOMODE,IO Mode Register"
|
|
bitfld.long 0x00 1. " DIO_OEN ,Indicates IO output enable" "Input,Output"
|
|
bitfld.long 0x00 0. " DIO_MODE ,IO mode register" "USART,7816"
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x07)==0x02)
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "IOMODE,IO Mode Register"
|
|
bitfld.long 0x00 1. " DIO_OEN ,Indicates IO output enable" "Input,Output"
|
|
bitfld.long 0x00 0. " DIO_MODE ,IO mode register" "SPI,3-wire SPI"
|
|
else
|
|
hgroup.long 0xF00++0x03
|
|
hide.long 0x00 "IOMODE,IO Mode Register"
|
|
endif
|
|
if (((per.l(ad:0x4008F000+0xFF8))&0x08)==0x08)
|
|
if (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x70)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x30)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x50)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,,I2C,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x10)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x60)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x20)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x40)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,,I2C,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x00)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
rbitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,?..."
|
|
endif
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x08)==0x00)
|
|
if (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x70)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x30)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,SPI,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x50)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,,I2C,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x10)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,USART,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x60)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,I2C,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x20)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,SPI,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x40)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,,,I2C,?..."
|
|
elif (((per.l(ad:0x4008F000+0xFF8))&0x70)==0x00)
|
|
group.long 0xFF8++0x03
|
|
line.long 0x00 "PSELID,Peripheral Select And Flexcomm Interface ID Register"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ID ,Flexcomm interface ID"
|
|
rbitfld.long 0x00 8. " SC3W ,Smart card/SPI 3 wire mode feature indicator" "Not supported,Supported"
|
|
rbitfld.long 0x00 6. " I2CPRESENT ,I2C present indicator" "Not included,Included"
|
|
rbitfld.long 0x00 5. " SPIPRESENT ,SPI present indicator" "Not included,Included"
|
|
newline
|
|
rbitfld.long 0x00 4. " USARTPRESENT ,USART present indicator" "Not included,Included"
|
|
bitfld.long 0x00 3. " LOCK ,Lock the peripheral select" "Not locked,Locked"
|
|
bitfld.long 0x00 0.--2. " PERSEL ,Peripheral select" "No selection,?..."
|
|
endif
|
|
endif
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "PID,Peripheral Identification Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " ID ,Module identifier for the selected function"
|
|
bitfld.long 0x00 12.--15. " MAJOR_REV ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " MINOR_REV ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "USART"
|
|
tree "USART0"
|
|
base ad:0x40083000
|
|
width 15.
|
|
if (((per.l(ad:0x40083000))&0x800)==0x800)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CFG,USART0 Configuration Register"
|
|
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 21. " OEPON ,Output enable polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " OESEL ,Output enable select" "Standard,RS-485"
|
|
bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " LOOP ,Selects data loopback mode" "Normal operation,Loopback mode"
|
|
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master"
|
|
bitfld.long 0x00 12. " CLKPOL ,Selects the clock polarity and sampling edge of receiver data in synchronous mode" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 9. " CTSEN ,Determines whether CTS is used for flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LINMODE ,LIN break mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " MODE32K ,Selects standard or 32 kHz clocking mode" "Standard,32kHz"
|
|
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 stop bit,?..."
|
|
bitfld.long 0x00 4.--5. " PARITYSEL ,Selects what type of parity is used by the USART" "No parity,,Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " DATALEN ,Selects the data size for the USART" "7-bit,8-bit,9-bit,?..."
|
|
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CFG,USART0 Configuration Register"
|
|
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 21. " OEPON ,Output enable polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " OESEL ,Output enable select" "Standard,RS-485"
|
|
bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " LOOP ,Selects data loopback mode" "Normal operation,Loopback mode"
|
|
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master"
|
|
bitfld.long 0x00 12. " CLKPOL ,Selects the clock polarity and sampling edge of receiver data in synchronous mode" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 9. " CTSEN ,Determines whether CTS is used for flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LINMODE ,LIN break mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " MODE32K ,Selects standard or 32 kHz clocking mode" "Standard,32kHz"
|
|
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 4.--5. " PARITYSEL ,Selects what type of parity is used by the USART" "No parity,,Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " DATALEN ,Selects the data size for the USART" "7-bit,8-bit,9-bit,?..."
|
|
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "CTL,USART0 Control Register"
|
|
bitfld.long 0x00 16. " AUTOBAUD ,Auto-baud enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear"
|
|
bitfld.long 0x00 8. " CC ,Continuous clock generation" "Clock on character,Continuous clock"
|
|
newline
|
|
bitfld.long 0x00 6. " TXDIS ,Transmit disable" "Not disabled,Disabled"
|
|
bitfld.long 0x00 2. " ADDRDET ,Enable address detect mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Normal operation,Continuous break"
|
|
line.long 0x04 "STAT,USART0 Status Register"
|
|
eventfld.long 0x04 16. " ABERR ,Auto baud error" "No error,Error"
|
|
eventfld.long 0x04 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 12. " START ,Indicates when start is detected on the receiver input" "No detected,Detected"
|
|
eventfld.long 0x04 11. " DELTARXBRK ,Change in the state of receiver break detection occurs" "Not changed,Changed"
|
|
newline
|
|
rbitfld.long 0x04 10. " RXBRK ,Received break" "Not received,Received"
|
|
rbitfld.long 0x04 6. " TXDISSTAT ,Transmitter disabled status flag" "No change,Fully idle"
|
|
bitfld.long 0x04 5. " DELTACTS ,CTS flag change detection" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x04 4. " CTS ,Reflects the current state of the CTS signal" "Low,High"
|
|
rbitfld.long 0x04 3. " TXIDLE ,Transmitter idle" "Transmitting data,Not Transmitting data"
|
|
rbitfld.long 0x04 1. " RXIDLE ,Receiver idle" "Receiving data,Not receiving data"
|
|
line.long 0x08 "INTEN_SET/CLR,Interrupt Enable Read And Set/Clear Register For USART0 Status"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x0C 16. " ABERREN ,Enables an interrupt when an auto baud error occurs" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x0C 15. " RXNOISEEN ,Enables an interrupt on noise detection" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x0C 14. " PARITYERREN ,Enables an interrupt on parity error detection" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 13. 0x08 13. 0x0C 13. " FRAMERREN ,Enables an interrupt on framing error detection" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x0C 12. " STARTEN ,Enables an interrupt on start bit detection" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " DELTARXBRKEN ,Change of state occurred in the detection of a received break condition interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 6. 0x08 6. 0x0C 6. " TXDISEN ,Enabled an interrupt when transmitter is fully disabled" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x0C 5. " DELTACTSEN ,Enables an interrupt on CTS input change detection" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x0C 3. " TXIDLEEN ,Enables an interrupt when TXIDLE is set to one" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BRG,Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BRGVAL ,A value that is used to divide the USART input clock"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "INTSTAT,Interrupt Status Register"
|
|
bitfld.long 0x00 16. " ABERRINT ,Auto baud error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " START ,Start is detected on the receiver input" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " DELTARXBRK ,Change in the state of receiver break detection occurs" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " DELTACTS ,Change in the state of the CTS input is detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status" "Not idle,Idle"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "OSR,Oversample Selection Register For Asynchronous Communication"
|
|
bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5 function,6 function,7 function,8 function,9 function,10 function,11 function,12 function,13 function,14 function,15 function,16 function"
|
|
line.long 0x04 "ADDR,Address Register For Automatic Address Matching"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,8-bit address used with automatic address matching"
|
|
group.long 0xE00++0x0B
|
|
line.long 0x00 "FIFOCFG,FIFO Configuration And Enable Register"
|
|
bitfld.long 0x00 17. " EMPTYRX ,Empty command for the receive FIFO" "Not emptied,Emptied"
|
|
bitfld.long 0x00 16. " EMPTYTX ,Empty command for the transmit FIFO" "Not emptied,Emptied"
|
|
bitfld.long 0x00 13. " DMARX ,DMA configuration for receive" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 12. " DMATX ,DMA configuration for transmit" "Not used,Used"
|
|
rbitfld.long 0x00 4.--5. " SIZE ,FIFO size configuration" "16 entries,Not applicable,Not applicable,Not applicable"
|
|
bitfld.long 0x00 1. " ENABLERX ,Enable the receive FIFO" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " ENABLETX ,Enable the transmit FIFO" "Disabled,Enabled"
|
|
line.long 0x04 "FIFOSTAT,FIFO Status Register"
|
|
rbitfld.long 0x04 16.--20. " RXLVL ,Receive FIFO current level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Full"
|
|
rbitfld.long 0x04 8.--12. " TXLVL ,Transmit FIFO current level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Full"
|
|
rbitfld.long 0x04 7. " RXFULL ,Receive FIFO full" "Not full,Full"
|
|
newline
|
|
rbitfld.long 0x04 6. " RXNOTEMPTY ,Receive FIFO not empty" "Empty,Not empty"
|
|
rbitfld.long 0x04 5. " TXNOTFULL ,Transmit FIFO not full" "Full,Not full"
|
|
rbitfld.long 0x04 4. " TXEMPTY ,Transmit FIFO empty" "Not empty,Empty"
|
|
newline
|
|
rbitfld.long 0x04 3. " PERINT ,Peripheral interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " RXERR ,RX FIFO error,Will be set if a receive FIFO overflow occurs" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " TXERR ,TX FIFO error,Will be set if a transmit FIFO overflow occurs" "Not occurred,Occurred"
|
|
line.long 0x08 "FIFOTRIG,FIFO Trigger Level Settings For Interrupt And DMA Request"
|
|
bitfld.long 0x08 16.--19. " RXLVL ,Receive FIFO level trigger point" "1 entry,2 entries,3 entries,4 entries,5 entries,6 entries,7 entries,8 entries,9 entries,10 entries,11 entries,12 entries,13 entries,14 entries,15 entries,16 entries"
|
|
bitfld.long 0x08 8.--11. " TXLVL ,Transmit FIFO level trigger point" "Empty,1 entry,2 entries,3 entries,4 entries,5 entries,6 entries,7 entries,8 entries,9 entries,10 entries,11 entries,12 entries,13 entries,14 entries,15 entries"
|
|
bitfld.long 0x08 1. " RXLVLENA ,Receive FIFO level trigger enable" "Not generated,Generated"
|
|
newline
|
|
bitfld.long 0x08 0. " TXLVLENA ,Transmit FIFO level trigger enable" "Not generated,Generated"
|
|
group.long 0xE18++0x03
|
|
line.long 0x00 "FIFOINTEN,FIFO Interrupt Enable And Read Register"
|
|
bitfld.long 0x00 4. " PERINT ,Peripheral interrupt status" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXLVL_SET/CLR ,Receive FIFO level interrupt occurred" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXLVL_SET/CLR ,Transmit FIFO level interrupt occurred" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXERR_SET/CLR ,Receive FIFO error occurred" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXERR_SET/CLR ,Transmit FIFO error occurred" "Not occurred,Occurred"
|
|
wgroup.long 0xE20++0x03
|
|
line.long 0x00 "FIFOWR,FIFO Write Data"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXDATA ,Transmit data to the FIFO"
|
|
rgroup.long 0xE30++0x03
|
|
line.long 0x00 "FIFORD,FIFO Read Data"
|
|
bitfld.long 0x00 15. " RXNOISE ,Received noise flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " PARITYERR ,Parity error status flag" "Not detected,Detected"
|
|
bitfld.long 0x00 13. " FRAMERR ,Framing error status flag" "Stop bit not missing,Stop bit missing"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATA ,Receiver data from the FIFO"
|
|
rgroup.long 0xE40++0x03
|
|
line.long 0x00 "FIFORDNOPOP,FIFO Data Read With No FIFO Pop"
|
|
bitfld.long 0x00 15. " RXNOISE ,Receiver noise flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " PARITYERR ,Parity error status flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " FRAMERR ,Framing error status flag" "Not occurred,Occurred"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATA ,Receiver data from the FIFO"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "ID,USART0 Module Identification"
|
|
hexmask.long.word 0x00 16.--31. 1. " ID ,Module identifier for the selected function"
|
|
bitfld.long 0x00 12.--15. " Major_Rev ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " Minor_Rev ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " APERTURE ,Aperture: encoded as (aperture size/4K)"
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART1"
|
|
base ad:0x40086000
|
|
width 15.
|
|
if (((per.l(ad:0x40086000))&0x800)==0x800)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CFG,USART1 Configuration Register"
|
|
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 21. " OEPON ,Output enable polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " OESEL ,Output enable select" "Standard,RS-485"
|
|
bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " LOOP ,Selects data loopback mode" "Normal operation,Loopback mode"
|
|
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master"
|
|
bitfld.long 0x00 12. " CLKPOL ,Selects the clock polarity and sampling edge of receiver data in synchronous mode" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 9. " CTSEN ,Determines whether CTS is used for flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LINMODE ,LIN break mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " MODE32K ,Selects standard or 32 kHz clocking mode" "Standard,32kHz"
|
|
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 stop bit,?..."
|
|
bitfld.long 0x00 4.--5. " PARITYSEL ,Selects what type of parity is used by the USART" "No parity,,Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " DATALEN ,Selects the data size for the USART" "7-bit,8-bit,9-bit,?..."
|
|
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CFG,USART1 Configuration Register"
|
|
bitfld.long 0x00 23. " TXPOL ,Transmit data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 22. " RXPOL ,Receive data polarity" "Standard,Inverted"
|
|
bitfld.long 0x00 21. " OEPON ,Output enable polarity" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. " OESEL ,Output enable select" "Standard,RS-485"
|
|
bitfld.long 0x00 19. " AUTOADDR ,Automatic address matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " OETA ,Output enable turnaround time enable for RS-485 operation" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 15. " LOOP ,Selects data loopback mode" "Normal operation,Loopback mode"
|
|
bitfld.long 0x00 14. " SYNCMST ,Synchronous mode master select" "Slave,Master"
|
|
bitfld.long 0x00 12. " CLKPOL ,Selects the clock polarity and sampling edge of receiver data in synchronous mode" "Falling,Rising"
|
|
newline
|
|
bitfld.long 0x00 11. " SYNCEN ,Selects synchronous or asynchronous operation" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 9. " CTSEN ,Determines whether CTS is used for flow control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LINMODE ,LIN break mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 7. " MODE32K ,Selects standard or 32 kHz clocking mode" "Standard,32kHz"
|
|
bitfld.long 0x00 6. " STOPLEN ,Number of stop bits appended to transmitted data" "1 stop bit,2 stop bits"
|
|
bitfld.long 0x00 4.--5. " PARITYSEL ,Selects what type of parity is used by the USART" "No parity,,Even,Odd"
|
|
newline
|
|
bitfld.long 0x00 2.--3. " DATALEN ,Selects the data size for the USART" "7-bit,8-bit,9-bit,?..."
|
|
bitfld.long 0x00 0. " ENABLE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "CTL,USART1 Control Register"
|
|
bitfld.long 0x00 16. " AUTOBAUD ,Auto-baud enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CLRCCONRX ,Clear continuous clock" "No effect,Auto-clear"
|
|
bitfld.long 0x00 8. " CC ,Continuous clock generation" "Clock on character,Continuous clock"
|
|
newline
|
|
bitfld.long 0x00 6. " TXDIS ,Transmit disable" "Not disabled,Disabled"
|
|
bitfld.long 0x00 2. " ADDRDET ,Enable address detect mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXBRKEN ,Break enable" "Normal operation,Continuous break"
|
|
line.long 0x04 "STAT,USART1 Status Register"
|
|
eventfld.long 0x04 16. " ABERR ,Auto baud error" "No error,Error"
|
|
eventfld.long 0x04 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
eventfld.long 0x04 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 12. " START ,Indicates when start is detected on the receiver input" "No detected,Detected"
|
|
eventfld.long 0x04 11. " DELTARXBRK ,Change in the state of receiver break detection occurs" "Not changed,Changed"
|
|
newline
|
|
rbitfld.long 0x04 10. " RXBRK ,Received break" "Not received,Received"
|
|
rbitfld.long 0x04 6. " TXDISSTAT ,Transmitter disabled status flag" "No change,Fully idle"
|
|
bitfld.long 0x04 5. " DELTACTS ,CTS flag change detection" "Not detected,Detected"
|
|
newline
|
|
rbitfld.long 0x04 4. " CTS ,Reflects the current state of the CTS signal" "Low,High"
|
|
rbitfld.long 0x04 3. " TXIDLE ,Transmitter idle" "Transmitting data,Not Transmitting data"
|
|
rbitfld.long 0x04 1. " RXIDLE ,Receiver idle" "Receiving data,Not receiving data"
|
|
line.long 0x08 "INTEN_SET/CLR,Interrupt Enable Read And Set/Clear Register For USART1 Status"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x0C 16. " ABERREN ,Enables an interrupt when an auto baud error occurs" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x0C 15. " RXNOISEEN ,Enables an interrupt on noise detection" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x0C 14. " PARITYERREN ,Enables an interrupt on parity error detection" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 13. 0x08 13. 0x0C 13. " FRAMERREN ,Enables an interrupt on framing error detection" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x0C 12. " STARTEN ,Enables an interrupt on start bit detection" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " DELTARXBRKEN ,Change of state occurred in the detection of a received break condition interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 6. 0x08 6. 0x0C 6. " TXDISEN ,Enabled an interrupt when transmitter is fully disabled" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x0C 5. " DELTACTSEN ,Enables an interrupt on CTS input change detection" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x0C 3. " TXIDLEEN ,Enables an interrupt when TXIDLE is set to one" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BRG,Baud Rate Generator Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BRGVAL ,A value that is used to divide the USART input clock"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "INTSTAT,Interrupt Status Register"
|
|
bitfld.long 0x00 16. " ABERRINT ,Auto baud error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 15. " RXNOISEINT ,Received noise interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 14. " PARITYERRINT ,Parity error interrupt flag" "No interrupt,Interrupt"
|
|
newline
|
|
bitfld.long 0x00 13. " FRAMERRINT ,Framing error interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 12. " START ,Start is detected on the receiver input" "Not detected,Detected"
|
|
bitfld.long 0x00 11. " DELTARXBRK ,Change in the state of receiver break detection occurs" "Not changed,Changed"
|
|
newline
|
|
bitfld.long 0x00 6. " TXDISINT ,Transmitter disabled interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " DELTACTS ,Change in the state of the CTS input is detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " TXIDLE ,Transmitter idle status" "Not idle,Idle"
|
|
group.long 0x28++0x07
|
|
line.long 0x00 "OSR,Oversample Selection Register For Asynchronous Communication"
|
|
bitfld.long 0x00 0.--3. " OSRVAL ,Oversample selection value" ",,,,5 function,6 function,7 function,8 function,9 function,10 function,11 function,12 function,13 function,14 function,15 function,16 function"
|
|
line.long 0x04 "ADDR,Address Register For Automatic Address Matching"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " ADDRESS ,8-bit address used with automatic address matching"
|
|
group.long 0xE00++0x0B
|
|
line.long 0x00 "FIFOCFG,FIFO Configuration And Enable Register"
|
|
bitfld.long 0x00 17. " EMPTYRX ,Empty command for the receive FIFO" "Not emptied,Emptied"
|
|
bitfld.long 0x00 16. " EMPTYTX ,Empty command for the transmit FIFO" "Not emptied,Emptied"
|
|
bitfld.long 0x00 13. " DMARX ,DMA configuration for receive" "Not used,Used"
|
|
newline
|
|
bitfld.long 0x00 12. " DMATX ,DMA configuration for transmit" "Not used,Used"
|
|
rbitfld.long 0x00 4.--5. " SIZE ,FIFO size configuration" "16 entries,Not applicable,Not applicable,Not applicable"
|
|
bitfld.long 0x00 1. " ENABLERX ,Enable the receive FIFO" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " ENABLETX ,Enable the transmit FIFO" "Disabled,Enabled"
|
|
line.long 0x04 "FIFOSTAT,FIFO Status Register"
|
|
rbitfld.long 0x04 16.--20. " RXLVL ,Receive FIFO current level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Full"
|
|
rbitfld.long 0x04 8.--12. " TXLVL ,Transmit FIFO current level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Full"
|
|
rbitfld.long 0x04 7. " RXFULL ,Receive FIFO full" "Not full,Full"
|
|
newline
|
|
rbitfld.long 0x04 6. " RXNOTEMPTY ,Receive FIFO not empty" "Empty,Not empty"
|
|
rbitfld.long 0x04 5. " TXNOTFULL ,Transmit FIFO not full" "Full,Not full"
|
|
rbitfld.long 0x04 4. " TXEMPTY ,Transmit FIFO empty" "Not empty,Empty"
|
|
newline
|
|
rbitfld.long 0x04 3. " PERINT ,Peripheral interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " RXERR ,RX FIFO error,Will be set if a receive FIFO overflow occurs" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " TXERR ,TX FIFO error,Will be set if a transmit FIFO overflow occurs" "Not occurred,Occurred"
|
|
line.long 0x08 "FIFOTRIG,FIFO Trigger Level Settings For Interrupt And DMA Request"
|
|
bitfld.long 0x08 16.--19. " RXLVL ,Receive FIFO level trigger point" "1 entry,2 entries,3 entries,4 entries,5 entries,6 entries,7 entries,8 entries,9 entries,10 entries,11 entries,12 entries,13 entries,14 entries,15 entries,16 entries"
|
|
bitfld.long 0x08 8.--11. " TXLVL ,Transmit FIFO level trigger point" "Empty,1 entry,2 entries,3 entries,4 entries,5 entries,6 entries,7 entries,8 entries,9 entries,10 entries,11 entries,12 entries,13 entries,14 entries,15 entries"
|
|
bitfld.long 0x08 1. " RXLVLENA ,Receive FIFO level trigger enable" "Not generated,Generated"
|
|
newline
|
|
bitfld.long 0x08 0. " TXLVLENA ,Transmit FIFO level trigger enable" "Not generated,Generated"
|
|
group.long 0xE18++0x03
|
|
line.long 0x00 "FIFOINTEN,FIFO Interrupt Enable And Read Register"
|
|
bitfld.long 0x00 4. " PERINT ,Peripheral interrupt status" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 3. -0x08 3. -0x04 3. " RXLVL_SET/CLR ,Receive FIFO level interrupt occurred" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. -0x08 2. -0x04 2. " TXLVL_SET/CLR ,Transmit FIFO level interrupt occurred" "Not occurred,Occurred"
|
|
newline
|
|
setclrfld.long 0x00 1. -0x08 1. -0x04 1. " RXERR_SET/CLR ,Receive FIFO error occurred" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " TXERR_SET/CLR ,Transmit FIFO error occurred" "Not occurred,Occurred"
|
|
wgroup.long 0xE20++0x03
|
|
line.long 0x00 "FIFOWR,FIFO Write Data"
|
|
hexmask.long.word 0x00 0.--8. 1. " TXDATA ,Transmit data to the FIFO"
|
|
rgroup.long 0xE30++0x03
|
|
line.long 0x00 "FIFORD,FIFO Read Data"
|
|
bitfld.long 0x00 15. " RXNOISE ,Received noise flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " PARITYERR ,Parity error status flag" "Not detected,Detected"
|
|
bitfld.long 0x00 13. " FRAMERR ,Framing error status flag" "Stop bit not missing,Stop bit missing"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATA ,Receiver data from the FIFO"
|
|
rgroup.long 0xE40++0x03
|
|
line.long 0x00 "FIFORDNOPOP,FIFO Data Read With No FIFO Pop"
|
|
bitfld.long 0x00 15. " RXNOISE ,Receiver noise flag" "Not received,Received"
|
|
bitfld.long 0x00 14. " PARITYERR ,Parity error status flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 13. " FRAMERR ,Framing error status flag" "Not occurred,Occurred"
|
|
newline
|
|
hexmask.long.word 0x00 0.--8. 1. " RXDATA ,Receiver data from the FIFO"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "ID,USART1 Module Identification"
|
|
hexmask.long.word 0x00 16.--31. 1. " ID ,Module identifier for the selected function"
|
|
bitfld.long 0x00 12.--15. " Major_Rev ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " Minor_Rev ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " APERTURE ,Aperture: encoded as (aperture size/4K)"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "SPI"
|
|
tree "SPI0"
|
|
base ad:0x40087000
|
|
width 18.
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "CFG,SPI0 Configuration Register"
|
|
bitfld.long 0x00 11. " SPOL3 ,SSEL3 polarity select" "Low,High"
|
|
bitfld.long 0x00 10. " SPOL2 ,SSEL2 polarity select" "Low,High"
|
|
bitfld.long 0x00 9. " SPOL1 ,SSEL1 polarity select" "Low,High"
|
|
bitfld.long 0x00 8. " SPOL9 ,SSEL0 polarity select" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " LOOP ,Loopback mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity select" "Low,High"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase select" "Change,Capture"
|
|
bitfld.long 0x00 3. " LSBF ,LSB first mode enable" "Standard,Reversed"
|
|
newline
|
|
bitfld.long 0x00 2. " MASTER ,Master mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 0. " ENABLE ,SPI enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40087000+0x00))&0x01)==0x00)
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "DLY,SPI0 Delay Register"
|
|
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that SSEL is deasserted between transfers" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times"
|
|
bitfld.long 0x00 8.--11. " FRAME_DELAY ,Controls the minimum amount of time between frames" "No add time,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POST_DELAY ,Controls the amount of time between the end of data transfer and SSEL de-assertion" "No add time,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PRE_DELAY ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "No add time,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "DLY,SPI0 Delay Register"
|
|
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that SSEL is deasserted between transfers" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times"
|
|
rbitfld.long 0x00 8.--11. " FRAME_DELAY ,Controls the minimum amount of time between frames" "No add time,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POST_DELAY ,Controls the amount of time between the end of data transfer and SSEL de-assertion" "No add time,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PRE_DELAY ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "No add time,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x408++0x07
|
|
line.long 0x00 "STAT,SPI0 Status Register"
|
|
rbitfld.long 0x00 8. " MSTIDLE ,Master idle status flag" "Not fully idle,Fully idle"
|
|
eventfld.long 0x00 7. " ENDTRANSFER ,End transfer control bit" "Transfer end,Force end"
|
|
rbitfld.long 0x00 6. " STALLED ,Stalled status flag" "Not stalled,Stalled"
|
|
eventfld.long 0x00 5. " SSD ,Slave select deassert" "Not deasserted,Deasserted"
|
|
newline
|
|
eventfld.long 0x00 4. " SSA ,Slave select assert" "Not asserted,Asserted"
|
|
line.long 0x04 "INTENSET/CLR,SPI0 Interrupt Enable Read And Set/Clear Register"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x08 8. " MSTIDLE ,Master idle interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x08 5. " SSDEN ,Slave select deassert interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x08 4. " SSAEN ,Slave select assert interrupt" "No interrupt,Interrupt"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "DIV,SPI0 Clock Divider Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIVVAL ,Rate divider value"
|
|
rgroup.long 0x428++0x03
|
|
line.long 0x00 "INTSTAT,SPI0 Interrupt Status Register"
|
|
bitfld.long 0x00 8. " MSTIDLE ,Master idle status flag" "Not set,Set"
|
|
bitfld.long 0x00 5. " SSD ,Slave select de-assert flag" "Not set,Set"
|
|
bitfld.long 0x00 4. " SSA ,Slave select assert flag" "Not set,Set"
|
|
group.long 0xE00++0x0B
|
|
line.long 0x00 "FIFOCFG,FIFO Configuration And Enable Register"
|
|
bitfld.long 0x00 17. " EMPTYRX ,Empty command for the receive FIFO" "Not emptied,Emptied"
|
|
bitfld.long 0x00 16. " EMPTYTX ,Empty command for the transmit FIFO" "Not emptied,Emptied"
|
|
bitfld.long 0x00 13. " DMARX ,DMA configuration for receive" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMATX ,DMA configuration for transmit" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. " SIZE ,FIFO size configuration" "8 entries,Not applicable,Not applicable,Not applicable"
|
|
bitfld.long 0x00 1. " ENABLERX ,Enable the receive FIFO" "Not enabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLETX ,Enable the transmit FIFO" "Not enabled,Enabled"
|
|
line.long 0x04 "FIFOSTAT,FIFO Status Register"
|
|
rbitfld.long 0x04 16.--20. " RXLVL ,Receive FIFO current level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Full"
|
|
rbitfld.long 0x04 8.--12. " TXLVL ,Transmit FIFO current level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Full"
|
|
rbitfld.long 0x04 7. " RXFULL ,Receive FIFO full" "Not full,Full"
|
|
rbitfld.long 0x04 6. " RXNOTEMPTY ,Receive FIFO not empty" "Not empty,Empty"
|
|
newline
|
|
rbitfld.long 0x04 5. " TXNOTFULL ,Transmit FIFO not full" "Full,Not full"
|
|
rbitfld.long 0x04 4. " TXEMPTY ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 3. " PERINT ,Peripheral interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " RXERR ,RX FIFO error" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 0. " TXERR ,TX FIFO error" "Not occurred,Occurred"
|
|
line.long 0x08 "FIFOTRIG,FIFO Trigger Level Settings For Interrupt And DMA Request Register"
|
|
bitfld.long 0x08 16.--19. " RXLVL ,Receive FIFO level trigger point" "1 entry,2 entries,3 entries,4 entries,5 entries,6 entries,7 entries,?..."
|
|
bitfld.long 0x08 8.--11. " TXLVL ,Transmit FIFO level trigger point" "Empty,1 entry,2 entries,3 entries,4 entries,5 entries,6 entries,7 entries,?..."
|
|
bitfld.long 0x08 1. " RXLVLENA ,Receive FIFO level trigger enable" "Not generated,Generated"
|
|
bitfld.long 0x08 0. " TXLVLENA ,Transmit FIFO level trigger enable" "Not generated,Generated"
|
|
group.long 0xE10++0x03
|
|
line.long 0x00 "FIFOINTENSET/CLR,FIFO Interrupt Enable Set/Clear And Read Register"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " RXLVL ,Receive FIFO interrupt occurred" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXLVL ,Transmit FIFO interrupt occurred" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " RXERR ,Receive FIFO error occurred" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " TXERR ,Transmit FIFO error occurred" "Not occurred,Occurred"
|
|
rgroup.long 0xE18++0x03
|
|
line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status Register"
|
|
bitfld.long 0x00 4. " PERINT ,Peripheral interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " RXLVL ,Receive FIFO level interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " TXLVL ,Transmit FIFO level interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RXERR ,RX FIFO error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0. " TXERR ,TX FIXO error" "Not occurred,Occurred"
|
|
wgroup.long 0xE20++0x03
|
|
line.long 0x00 "FIFOWR,FIFO Write Data"
|
|
bitfld.long 0x00 24.--27. " LEN ,Data length" ",,,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.long 0x00 22. " RXIGNORE ,Receive ignore" "Read,Ignored"
|
|
bitfld.long 0x00 21. " EOF ,End of frame" "Not EOF,EOF"
|
|
bitfld.long 0x00 20. " EOT ,End of transfer" "Not deasserted,Deasserted"
|
|
newline
|
|
bitfld.long 0x00 19. " TXSSEL3_N ,Transmit slave select" "Asserted,Not asserted"
|
|
bitfld.long 0x00 18. " TXSSEL2_N ,Transmit slave select" "Asserted,Not asserted"
|
|
bitfld.long 0x00 17. " TXSSEL1_N ,Transmit slave select" "Asserted,Not asserted"
|
|
bitfld.long 0x00 16. " TXSSEL0_N ,Transmit slave select" "Asserted,Not asserted"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data to the FIFO"
|
|
rgroup.long 0xE30++0x03
|
|
line.long 0x00 "FIFORD,FIFO Read Data"
|
|
bitfld.long 0x00 20. " SOT ,Start of transfer" "Not started,Started"
|
|
bitfld.long 0x00 19. " RXSSEL3_N ,Slave select for receive" "Active,Not active"
|
|
bitfld.long 0x00 18. " RXSSEL2_N ,Slave select for receive" "Active,Not active"
|
|
bitfld.long 0x00 17. " RXSSEL1_N ,Slave select for receive" "Active,Not active"
|
|
newline
|
|
bitfld.long 0x00 16. " RXSSEL0_N ,Slave select for receive" "Active,Not active"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,Receiver data from the FIFO"
|
|
rgroup.long 0xE40++0x03
|
|
line.long 0x00 "FIFORDNOPOP,FIFO Data Read With No FIFO Pop Register"
|
|
bitfld.long 0x00 20. " SOT ,Start of transfer flag" "Not started,Started"
|
|
bitfld.long 0x00 19. " RXSSEL3_N ,Slave select for receive" "Active,Not active"
|
|
bitfld.long 0x00 18. " RXSSEL2_N ,Slave select for receive" "Active,Not active"
|
|
bitfld.long 0x00 17. " RXSSEL1_N ,Slave select for receive" "Active,Not active"
|
|
newline
|
|
bitfld.long 0x00 16. " RXSSEL0_N ,Slave select for receive" "Active,Not active"
|
|
hexmask.long.word 0x00 0.--15. " RXDATA ,Received data from the FIFO"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "ID,SPI Module Identification Register"
|
|
bitfld.long 0x00 12.--15. " MAJOR_REV ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " MINOR_REV ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " APERTURE ,Aperture"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0x4008F000
|
|
width 18.
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "CFG,SPI1 Configuration Register"
|
|
bitfld.long 0x00 11. " SPOL3 ,SSEL3 polarity select" "Low,High"
|
|
bitfld.long 0x00 10. " SPOL2 ,SSEL2 polarity select" "Low,High"
|
|
bitfld.long 0x00 9. " SPOL1 ,SSEL1 polarity select" "Low,High"
|
|
bitfld.long 0x00 8. " SPOL9 ,SSEL0 polarity select" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. " LOOP ,Loopback mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CPOL ,Clock polarity select" "Low,High"
|
|
bitfld.long 0x00 4. " CPHA ,Clock phase select" "Change,Capture"
|
|
bitfld.long 0x00 3. " LSBF ,LSB first mode enable" "Standard,Reversed"
|
|
newline
|
|
bitfld.long 0x00 2. " MASTER ,Master mode select" "Slave mode,Master mode"
|
|
bitfld.long 0x00 0. " ENABLE ,SPI enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x4008F000+0x00))&0x01)==0x00)
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "DLY,SPI1 Delay Register"
|
|
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that SSEL is deasserted between transfers" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times"
|
|
bitfld.long 0x00 8.--11. " FRAME_DELAY ,Controls the minimum amount of time between frames" "No add time,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POST_DELAY ,Controls the amount of time between the end of data transfer and SSEL de-assertion" "No add time,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PRE_DELAY ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "No add time,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "DLY,SPI1 Delay Register"
|
|
bitfld.long 0x00 12.--15. " TRANSFER_DELAY ,Controls the minimum amount of time that SSEL is deasserted between transfers" "1 time,2 times,3 times,4 times,5 times,6 times,7 times,8 times,9 times,10 times,11 times,12 times,13 times,14 times,15 times,16 times"
|
|
rbitfld.long 0x00 8.--11. " FRAME_DELAY ,Controls the minimum amount of time between frames" "No add time,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " POST_DELAY ,Controls the amount of time between the end of data transfer and SSEL de-assertion" "No add time,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PRE_DELAY ,Controls the amount of time between SSEL assertion and the beginning of a data transfer" "No add time,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.long 0x408++0x07
|
|
line.long 0x00 "STAT,SPI1 Status Register"
|
|
rbitfld.long 0x00 8. " MSTIDLE ,Master idle status flag" "Not fully idle,Fully idle"
|
|
eventfld.long 0x00 7. " ENDTRANSFER ,End transfer control bit" "Transfer end,Force end"
|
|
rbitfld.long 0x00 6. " STALLED ,Stalled status flag" "Not stalled,Stalled"
|
|
eventfld.long 0x00 5. " SSD ,Slave select deassert" "Not deasserted,Deasserted"
|
|
newline
|
|
eventfld.long 0x00 4. " SSA ,Slave select assert" "Not asserted,Asserted"
|
|
line.long 0x04 "INTENSET/CLR,SPI1 Interrupt Enable Read And Set/Clear Register"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x08 8. " MSTIDLE ,Master idle interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x08 5. " SSDEN ,Slave select deassert interrupt" "No interrupt,Interrupt"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x08 4. " SSAEN ,Slave select assert interrupt" "No interrupt,Interrupt"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "DIV,SPI1 Clock Divider Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DIVVAL ,Rate divider value"
|
|
rgroup.long 0x428++0x03
|
|
line.long 0x00 "INTSTAT,SPI1 Interrupt Status Register"
|
|
bitfld.long 0x00 8. " MSTIDLE ,Master idle status flag" "Not set,Set"
|
|
bitfld.long 0x00 5. " SSD ,Slave select de-assert flag" "Not set,Set"
|
|
bitfld.long 0x00 4. " SSA ,Slave select assert flag" "Not set,Set"
|
|
group.long 0xE00++0x0B
|
|
line.long 0x00 "FIFOCFG,FIFO Configuration And Enable Register"
|
|
bitfld.long 0x00 17. " EMPTYRX ,Empty command for the receive FIFO" "Not emptied,Emptied"
|
|
bitfld.long 0x00 16. " EMPTYTX ,Empty command for the transmit FIFO" "Not emptied,Emptied"
|
|
bitfld.long 0x00 13. " DMARX ,DMA configuration for receive" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMATX ,DMA configuration for transmit" "Disabled,Enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--5. " SIZE ,FIFO size configuration" "8 entries,Not applicable,Not applicable,Not applicable"
|
|
bitfld.long 0x00 1. " ENABLERX ,Enable the receive FIFO" "Not enabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLETX ,Enable the transmit FIFO" "Not enabled,Enabled"
|
|
line.long 0x04 "FIFOSTAT,FIFO Status Register"
|
|
rbitfld.long 0x04 16.--20. " RXLVL ,Receive FIFO current level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Full"
|
|
rbitfld.long 0x04 8.--12. " TXLVL ,Transmit FIFO current level" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Full"
|
|
rbitfld.long 0x04 7. " RXFULL ,Receive FIFO full" "Not full,Full"
|
|
rbitfld.long 0x04 6. " RXNOTEMPTY ,Receive FIFO not empty" "Not empty,Empty"
|
|
newline
|
|
rbitfld.long 0x04 5. " TXNOTFULL ,Transmit FIFO not full" "Full,Not full"
|
|
rbitfld.long 0x04 4. " TXEMPTY ,Transmit FIFO empty" "Not empty,Empty"
|
|
rbitfld.long 0x04 3. " PERINT ,Peripheral interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 1. " RXERR ,RX FIFO error" "Not occurred,Occurred"
|
|
newline
|
|
eventfld.long 0x04 0. " TXERR ,TX FIFO error" "Not occurred,Occurred"
|
|
line.long 0x08 "FIFOTRIG,FIFO Trigger Level Settings For Interrupt And DMA Request Register"
|
|
bitfld.long 0x08 16.--19. " RXLVL ,Receive FIFO level trigger point" "1 entry,2 entries,3 entries,4 entries,5 entries,6 entries,7 entries,?..."
|
|
bitfld.long 0x08 8.--11. " TXLVL ,Transmit FIFO level trigger point" "Empty,1 entry,2 entries,3 entries,4 entries,5 entries,6 entries,7 entries,?..."
|
|
bitfld.long 0x08 1. " RXLVLENA ,Receive FIFO level trigger enable" "Not generated,Generated"
|
|
bitfld.long 0x08 0. " TXLVLENA ,Transmit FIFO level trigger enable" "Not generated,Generated"
|
|
group.long 0xE10++0x03
|
|
line.long 0x00 "FIFOINTENSET/CLR,FIFO Interrupt Enable Set/Clear And Read Register"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " RXLVL ,Receive FIFO interrupt occurred" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TXLVL ,Transmit FIFO interrupt occurred" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " RXERR ,Receive FIFO error occurred" "Not occurred,Occurred"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " TXERR ,Transmit FIFO error occurred" "Not occurred,Occurred"
|
|
rgroup.long 0xE18++0x03
|
|
line.long 0x00 "FIFOINTSTAT,FIFO Interrupt Status Register"
|
|
bitfld.long 0x00 4. " PERINT ,Peripheral interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " RXLVL ,Receive FIFO level interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " TXLVL ,Transmit FIFO level interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " RXERR ,RX FIFO error" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 0. " TXERR ,TX FIXO error" "Not occurred,Occurred"
|
|
wgroup.long 0xE20++0x03
|
|
line.long 0x00 "FIFOWR,FIFO Write Data"
|
|
bitfld.long 0x00 24.--27. " LEN ,Data length" ",,,4 bits,5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.long 0x00 22. " RXIGNORE ,Receive ignore" "Read,Ignored"
|
|
bitfld.long 0x00 21. " EOF ,End of frame" "Not EOF,EOF"
|
|
bitfld.long 0x00 20. " EOT ,End of transfer" "Not deasserted,Deasserted"
|
|
newline
|
|
bitfld.long 0x00 19. " TXSSEL3_N ,Transmit slave select" "Asserted,Not asserted"
|
|
bitfld.long 0x00 18. " TXSSEL2_N ,Transmit slave select" "Asserted,Not asserted"
|
|
bitfld.long 0x00 17. " TXSSEL1_N ,Transmit slave select" "Asserted,Not asserted"
|
|
bitfld.long 0x00 16. " TXSSEL0_N ,Transmit slave select" "Asserted,Not asserted"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transmit data to the FIFO"
|
|
rgroup.long 0xE30++0x03
|
|
line.long 0x00 "FIFORD,FIFO Read Data"
|
|
bitfld.long 0x00 20. " SOT ,Start of transfer" "Not started,Started"
|
|
bitfld.long 0x00 19. " RXSSEL3_N ,Slave select for receive" "Active,Not active"
|
|
bitfld.long 0x00 18. " RXSSEL2_N ,Slave select for receive" "Active,Not active"
|
|
bitfld.long 0x00 17. " RXSSEL1_N ,Slave select for receive" "Active,Not active"
|
|
newline
|
|
bitfld.long 0x00 16. " RXSSEL0_N ,Slave select for receive" "Active,Not active"
|
|
hexmask.long.word 0x00 0.--15. 1. " RXDATA ,Receiver data from the FIFO"
|
|
rgroup.long 0xE40++0x03
|
|
line.long 0x00 "FIFORDNOPOP,FIFO Data Read With No FIFO Pop Register"
|
|
bitfld.long 0x00 20. " SOT ,Start of transfer flag" "Not started,Started"
|
|
bitfld.long 0x00 19. " RXSSEL3_N ,Slave select for receive" "Active,Not active"
|
|
bitfld.long 0x00 18. " RXSSEL2_N ,Slave select for receive" "Active,Not active"
|
|
bitfld.long 0x00 17. " RXSSEL1_N ,Slave select for receive" "Active,Not active"
|
|
newline
|
|
bitfld.long 0x00 16. " RXSSEL0_N ,Slave select for receive" "Active,Not active"
|
|
hexmask.long.word 0x00 0.--15. " RXDATA ,Received data from the FIFO"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "ID,SPI Module Identification Register"
|
|
bitfld.long 0x00 12.--15. " MAJOR_REV ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " MINOR_REV ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " APERTURE ,Aperture"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "I2C"
|
|
tree "I2C0"
|
|
base ad:0x40086000
|
|
width 16.
|
|
group.long 0x800++0x0B
|
|
line.long 0x00 "CFG,Configuration For Shared Functions"
|
|
bitfld.long 0x00 4. " MONCLKSTR ,Monitor function clock stretching" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIMEOUTEN ,I2C-but time-out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MONEN ,Monitor enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SLVEN ,Slave enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MSTEN ,Master enable" "Disabled,Enabled"
|
|
line.long 0x04 "STAT,Status Register For Master Slave And Monitor Functions"
|
|
eventfld.long 0x04 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "No time-out,Time-out"
|
|
eventfld.long 0x04 24. " EVENTTIMEOUT ,Event time-out interrupt flag" "No time-out,Time-out"
|
|
eventfld.long 0x04 19. " MONIDLE ,Monitor idle flag" "Not idle,Idle"
|
|
newline
|
|
rbitfld.long 0x04 18. " MONACTIVE ,Monitor active flag" "Inactive,Active"
|
|
eventfld.long 0x04 17. " MONOV ,Monitor overflow flag" "No overrun,Overrun"
|
|
rbitfld.long 0x04 16. " MONRDY ,Monitor ready" "No data,Data waiting"
|
|
newline
|
|
eventfld.long 0x04 15. " SLVDESEL ,Slave deselected flag" "Not deselected,Deselected"
|
|
rbitfld.long 0x04 14. " SLVSEL ,Slave selected flag" "Not selected,Selected"
|
|
rbitfld.long 0x04 12.--13. " SLVIDX ,Slave address match index" "Addr.0 matched,Addr.1 matched,Addr.2 matched,Addr.3 matched"
|
|
newline
|
|
rbitfld.long 0x04 11. " SLVNOTSTR ,Slave not stretching" "Stretching,Not stretching"
|
|
rbitfld.long 0x04 9.--10. " SLVSTATE ,Slave state code" "Address,Receive,Transmit,?..."
|
|
rbitfld.long 0x04 8. " SLVPENDING ,Slave pending" "In progress,Pending"
|
|
newline
|
|
eventfld.long 0x04 6. " MSTSTSTPERR ,Master start/stop error flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 4. " MSTARBLOSS ,Master arbitration loss flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x04 1.--3. " MSTSTATE ,Master state code" "Idle,Receive ready,Transmit ready,NACK address,NACK data,?..."
|
|
newline
|
|
rbitfld.long 0x04 0. " MSTPENDING ,Master pending" "In progress,Pending"
|
|
line.long 0x08 "INTENSET/CLR,Interrupt Enable Set/Clear And Read Register"
|
|
setclrfld.long 0x08 25. 0x08 25. 0x0C 25. " SCLTIMEOUTEN_SET/CLR ,SCL time-out interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x0C 24. " EVENTTIMEOUTEN_SET/CLR ,Event time-out interrupt mode" "Disabled,Enabled"
|
|
setclrfld.long 0x08 19. 0x08 19. 0x0C 19. " MONIDLEEN_SET/CLR ,Monitor idle interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 17. 0x08 17. 0x0C 17. " MONOVEN_SET/CLR ,Monitor overrun interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x0C 16. " MONRDYEN_SET/CLR ,Monitor data ready interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x0C 15. " SLVDESELEN_SET/CLR ,Slave deselect interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " SLVNOTSTREN_SET/CLR ,Slave not stretching interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " SLVPENGINGEN_SET/CLR ,Slave pending interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x0C 6. " MSTSTSTPERREN_SET/CLR ,Master start/stop error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " MSTARBLOSSEN_SET/CLR ,Master arbitration loss interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " MSTPENDINGEN_SET/CLR ,Master pending interrupt enable" "Disabled,Enabled"
|
|
group.long 0x810++0x07
|
|
line.long 0x00 "TIMEOUT,Time-out Value Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " TO ,Time-out time value"
|
|
bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CLKDIV,Clock Pre-divider For The Entire I2C-bus Interface"
|
|
hexmask.long.word 0x04 0.--15. 1. " DIVVAL ,FCLK clock divider"
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "INTSTAT,Interrupt Status Register For Master Slave And Monitor Functions"
|
|
bitfld.long 0x00 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " EVENTTIMEOUT ,Event time-out interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " MONIDLE ,Monitor idle flag" "Not idle,Idle"
|
|
newline
|
|
bitfld.long 0x00 17. " MONOV ,Monitor overflow flag" "Not overflowed,Overflowed"
|
|
bitfld.long 0x00 16. " MONRDY ,Monitor ready" "Not ready,Ready"
|
|
bitfld.long 0x00 15. " SLVDESEL ,Slave deselected flag" "Not deselected,Deselected"
|
|
newline
|
|
bitfld.long 0x00 11. " SLVNOTSTR ,Slave not stretching status" "Not stretching,Stretching"
|
|
bitfld.long 0x00 8. " SVLPENDING ,Slave pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " MSTSTSTPERR ,Master start/stop error flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 4. " MSTARBLOSS ,Master arbitration loss flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " MSTPENDING ,Master pending" "Not pending,Pending"
|
|
group.long 0x820++0x0b
|
|
line.long 0x00 "MSTCTL,Master Control Register"
|
|
bitfld.long 0x00 3. " MSTDMA ,Master DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stopped"
|
|
bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Started"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTCONTINUE ,Master continue" "No effect,Continued"
|
|
line.long 0x04 "MSTTIME,Master Timing Configuration"
|
|
bitfld.long 0x04 4.--6. " MSTSCLHIGH ,Master SCL high time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks"
|
|
bitfld.long 0x04 0.--2. " MSTSCLLOW ,Master SCL low time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks"
|
|
line.long 0x08 "MSTDAT,Combined Master Receiver And Transmitter Data Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA ,Master function data register"
|
|
if (((per.l(ad:0x40086000+0x804))&0x100)==0x100)
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "SLVCTL,Slave Control Register"
|
|
bitfld.long 0x00 9. " AUTOMATCHREAD ,Direction to be chosen for the next operation" "Write,Read"
|
|
bitfld.long 0x00 8. " AUTOACK ,Automatic acknowledge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SLVNACK ,Slave NACK" "No effect,NACK"
|
|
bitfld.long 0x00 0. " SLVCONTINUE ,Slave continue" "No effect,Continue"
|
|
else
|
|
rgroup.long 0x840++0x03
|
|
line.long 0x00 "SLVCTL,Slave Control Register"
|
|
bitfld.long 0x00 9. " AUTOMATCHREAD ,Direction to be chosen for the next operation" "Write,Read"
|
|
bitfld.long 0x00 8. " AUTOACK ,Automatic acknowledge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SLVNACK ,Slave NACK" "No effect,NACK"
|
|
bitfld.long 0x00 0. " SLVCONTINUE ,Slave continue" "No effect,Continue"
|
|
endif
|
|
group.long 0x844++0x07
|
|
line.long 0x00 "SLVDAT,Combined Slave Receiver And Transmitter Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Slave function data register"
|
|
line.long 0x04 "SLVADR0,Slave Address 0"
|
|
bitfld.long 0x04 15. " AUTONACK ,Automatic NACK operation" "Normal operation,Automatic-only"
|
|
hexmask.long.byte 0x04 1.--7. 0x02 " SLVADR0 ,Slave address"
|
|
bitfld.long 0x04 0. " SADISABLE0 ,Slave address 0 disable" "No,Yes"
|
|
group.long 0x84C++0x03
|
|
line.long 0x00 "SVLADR1,Slave Address 1"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR1 ,Slave address"
|
|
bitfld.long 0x00 0. " SADISABLE1 ,Slave address 1 disable" "No,Yes"
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "SVLADR2,Slave Address 2"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR2 ,Slave address"
|
|
bitfld.long 0x00 0. " SADISABLE2 ,Slave address 2 disable" "No,Yes"
|
|
group.long 0x854++0x03
|
|
line.long 0x00 "SVLADR3,Slave Address 3"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR3 ,Slave address"
|
|
bitfld.long 0x00 0. " SADISABLE3 ,Slave address 3 disable" "No,Yes"
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "SLVQUAL0,Slave Qualification For Address 0"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " SLVQUAL0 ,Slave address qualifier for address 0"
|
|
bitfld.long 0x00 0. " QUALMODE0 ,Qualify mode for slave address 0" "Mask,Extend"
|
|
rgroup.long 0x880++0x03
|
|
line.long 0x00 "MONRXDAT,Monitor Receiver Data Register"
|
|
bitfld.long 0x00 10. " MONNACK ,Monitor received NACK" "Acknowledged,Not acknowledged"
|
|
bitfld.long 0x00 9. " MONRESTART ,Monitor receiver repeated start" "Not repeated,Repeated"
|
|
bitfld.long 0x00 8. " MONSTART ,Monitor received start" "Not started,Started"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MONRXDAT ,Monitor function receiver data"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "ID,I2C-bus Module Identification"
|
|
hexmask.long.word 0x00 16.--31. 1. " ID ,Unique module identifier for this IP block"
|
|
bitfld.long 0x00 12.--15. " MAJOR_REV ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " MINOR_REV ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " APERTURE ,Aperture"
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C1"
|
|
base ad:0x40087000
|
|
width 16.
|
|
group.long 0x800++0x0B
|
|
line.long 0x00 "CFG,Configuration For Shared Functions"
|
|
bitfld.long 0x00 4. " MONCLKSTR ,Monitor function clock stretching" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIMEOUTEN ,I2C-but time-out enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MONEN ,Monitor enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SLVEN ,Slave enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MSTEN ,Master enable" "Disabled,Enabled"
|
|
line.long 0x04 "STAT,Status Register For Master Slave And Monitor Functions"
|
|
eventfld.long 0x04 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "No time-out,Time-out"
|
|
eventfld.long 0x04 24. " EVENTTIMEOUT ,Event time-out interrupt flag" "No time-out,Time-out"
|
|
eventfld.long 0x04 19. " MONIDLE ,Monitor idle flag" "Not idle,Idle"
|
|
newline
|
|
rbitfld.long 0x04 18. " MONACTIVE ,Monitor active flag" "Inactive,Active"
|
|
eventfld.long 0x04 17. " MONOV ,Monitor overflow flag" "No overrun,Overrun"
|
|
rbitfld.long 0x04 16. " MONRDY ,Monitor ready" "No data,Data waiting"
|
|
newline
|
|
eventfld.long 0x04 15. " SLVDESEL ,Slave deselected flag" "Not deselected,Deselected"
|
|
rbitfld.long 0x04 14. " SLVSEL ,Slave selected flag" "Not selected,Selected"
|
|
rbitfld.long 0x04 12.--13. " SLVIDX ,Slave address match index" "Addr.0 matched,Addr.1 matched,Addr.2 matched,Addr.3 matched"
|
|
newline
|
|
rbitfld.long 0x04 11. " SLVNOTSTR ,Slave not stretching" "Stretching,Not stretching"
|
|
rbitfld.long 0x04 9.--10. " SLVSTATE ,Slave state code" "Address,Receive,Transmit,?..."
|
|
rbitfld.long 0x04 8. " SLVPENDING ,Slave pending" "In progress,Pending"
|
|
newline
|
|
eventfld.long 0x04 6. " MSTSTSTPERR ,Master start/stop error flag" "Not occurred,Occurred"
|
|
eventfld.long 0x04 4. " MSTARBLOSS ,Master arbitration loss flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x04 1.--3. " MSTSTATE ,Master state code" "Idle,Receive ready,Transmit ready,NACK address,NACK data,?..."
|
|
newline
|
|
rbitfld.long 0x04 0. " MSTPENDING ,Master pending" "In progress,Pending"
|
|
line.long 0x08 "INTENSET/CLR,Interrupt Enable Set/Clear And Read Register"
|
|
setclrfld.long 0x08 25. 0x08 25. 0x0C 25. " SCLTIMEOUTEN_SET/CLR ,SCL time-out interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x0C 24. " EVENTTIMEOUTEN_SET/CLR ,Event time-out interrupt mode" "Disabled,Enabled"
|
|
setclrfld.long 0x08 19. 0x08 19. 0x0C 19. " MONIDLEEN_SET/CLR ,Monitor idle interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 17. 0x08 17. 0x0C 17. " MONOVEN_SET/CLR ,Monitor overrun interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x0C 16. " MONRDYEN_SET/CLR ,Monitor data ready interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x0C 15. " SLVDESELEN_SET/CLR ,Slave deselect interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " SLVNOTSTREN_SET/CLR ,Slave not stretching interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " SLVPENGINGEN_SET/CLR ,Slave pending interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x0C 6. " MSTSTSTPERREN_SET/CLR ,Master start/stop error interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " MSTARBLOSSEN_SET/CLR ,Master arbitration loss interrupt enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " MSTPENDINGEN_SET/CLR ,Master pending interrupt enable" "Disabled,Enabled"
|
|
group.long 0x810++0x07
|
|
line.long 0x00 "TIMEOUT,Time-out Value Register"
|
|
hexmask.long.word 0x00 4.--15. 1. " TO ,Time-out time value"
|
|
bitfld.long 0x00 0.--3. " TOMIN ,Time-out time value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "CLKDIV,Clock Pre-divider For The Entire I2C-bus Interface"
|
|
hexmask.long.word 0x04 0.--15. 1. " DIVVAL ,FCLK clock divider"
|
|
rgroup.long 0x818++0x03
|
|
line.long 0x00 "INTSTAT,Interrupt Status Register For Master Slave And Monitor Functions"
|
|
bitfld.long 0x00 25. " SCLTIMEOUT ,SCL time-out interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 24. " EVENTTIMEOUT ,Event time-out interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 19. " MONIDLE ,Monitor idle flag" "Not idle,Idle"
|
|
newline
|
|
bitfld.long 0x00 17. " MONOV ,Monitor overflow flag" "Not overflowed,Overflowed"
|
|
bitfld.long 0x00 16. " MONRDY ,Monitor ready" "Not ready,Ready"
|
|
bitfld.long 0x00 15. " SLVDESEL ,Slave deselected flag" "Not deselected,Deselected"
|
|
newline
|
|
bitfld.long 0x00 11. " SLVNOTSTR ,Slave not stretching status" "Not stretching,Stretching"
|
|
bitfld.long 0x00 8. " SVLPENDING ,Slave pending" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " MSTSTSTPERR ,Master start/stop error flag" "No error,Error"
|
|
newline
|
|
bitfld.long 0x00 4. " MSTARBLOSS ,Master arbitration loss flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " MSTPENDING ,Master pending" "Not pending,Pending"
|
|
group.long 0x820++0x0b
|
|
line.long 0x00 "MSTCTL,Master Control Register"
|
|
bitfld.long 0x00 3. " MSTDMA ,Master DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MSTSTOP ,Master stop control" "No effect,Stopped"
|
|
bitfld.long 0x00 1. " MSTSTART ,Master start control" "No effect,Started"
|
|
newline
|
|
bitfld.long 0x00 0. " MSTCONTINUE ,Master continue" "No effect,Continued"
|
|
line.long 0x04 "MSTTIME,Master Timing Configuration"
|
|
bitfld.long 0x04 4.--6. " MSTSCLHIGH ,Master SCL high time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks"
|
|
bitfld.long 0x04 0.--2. " MSTSCLLOW ,Master SCL low time" "2 clocks,3 clocks,4 clocks,5 clocks,6 clocks,7 clocks,8 clocks,9 clocks"
|
|
line.long 0x08 "MSTDAT,Combined Master Receiver And Transmitter Data Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA ,Master function data register"
|
|
if (((per.l(ad:0x40087000+0x804))&0x100)==0x100)
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "SLVCTL,Slave Control Register"
|
|
bitfld.long 0x00 9. " AUTOMATCHREAD ,Direction to be chosen for the next operation" "Write,Read"
|
|
bitfld.long 0x00 8. " AUTOACK ,Automatic acknowledge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SLVNACK ,Slave NACK" "No effect,NACK"
|
|
bitfld.long 0x00 0. " SLVCONTINUE ,Slave continue" "No effect,Continue"
|
|
else
|
|
rgroup.long 0x840++0x03
|
|
line.long 0x00 "SLVCTL,Slave Control Register"
|
|
bitfld.long 0x00 9. " AUTOMATCHREAD ,Direction to be chosen for the next operation" "Write,Read"
|
|
bitfld.long 0x00 8. " AUTOACK ,Automatic acknowledge enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SLVDMA ,Slave DMA enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " SLVNACK ,Slave NACK" "No effect,NACK"
|
|
bitfld.long 0x00 0. " SLVCONTINUE ,Slave continue" "No effect,Continue"
|
|
endif
|
|
group.long 0x844++0x07
|
|
line.long 0x00 "SLVDAT,Combined Slave Receiver And Transmitter Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Slave function data register"
|
|
line.long 0x04 "SLVADR0,Slave Address 0"
|
|
bitfld.long 0x04 15. " AUTONACK ,Automatic NACK operation" "Normal operation,Automatic-only"
|
|
hexmask.long.byte 0x04 1.--7. 0x02 " SLVADR0 ,Slave address"
|
|
bitfld.long 0x04 0. " SADISABLE0 ,Slave address 0 disable" "No,Yes"
|
|
group.long 0x84C++0x03
|
|
line.long 0x00 "SVLADR1,Slave Address 1"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR1 ,Slave address"
|
|
bitfld.long 0x00 0. " SADISABLE1 ,Slave address 1 disable" "No,Yes"
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "SVLADR2,Slave Address 2"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR2 ,Slave address"
|
|
bitfld.long 0x00 0. " SADISABLE2 ,Slave address 2 disable" "No,Yes"
|
|
group.long 0x854++0x03
|
|
line.long 0x00 "SVLADR3,Slave Address 3"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " SLVADR3 ,Slave address"
|
|
bitfld.long 0x00 0. " SADISABLE3 ,Slave address 3 disable" "No,Yes"
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "SLVQUAL0,Slave Qualification For Address 0"
|
|
hexmask.long.byte 0x00 1.--7. 0x2 " SLVQUAL0 ,Slave address qualifier for address 0"
|
|
bitfld.long 0x00 0. " QUALMODE0 ,Qualify mode for slave address 0" "Mask,Extend"
|
|
rgroup.long 0x880++0x03
|
|
line.long 0x00 "MONRXDAT,Monitor Receiver Data Register"
|
|
bitfld.long 0x00 10. " MONNACK ,Monitor received NACK" "Acknowledged,Not acknowledged"
|
|
bitfld.long 0x00 9. " MONRESTART ,Monitor receiver repeated start" "Not repeated,Repeated"
|
|
bitfld.long 0x00 8. " MONSTART ,Monitor received start" "Not started,Started"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " MONRXDAT ,Monitor function receiver data"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "ID,I2C-bus Module Identification"
|
|
hexmask.long.word 0x00 16.--31. 1. " ID ,Unique module identifier for this IP block"
|
|
bitfld.long 0x00 12.--15. " MAJOR_REV ,Major revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " MINOR_REV ,Minor revision of module implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " APERTURE ,Aperture"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.open "QDEC (Quadrature Decoder)"
|
|
tree "QDEC0"
|
|
base ad:0x40009000
|
|
width 11.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,QDEC Configuration And Control Register"
|
|
bitfld.long 0x00 6. " DB_FILTER_EN ,Debounce filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SINGLE_SAMPLE_SRST_EN ,Single sample soft reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " AUTO_CLR_EN ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SOFT_CLR ,Software clear" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 2. " STOP ,Stop operation" "Not stopped,Stopped"
|
|
bitfld.long 0x00 1. " START ,Start operation" "Not started,Started"
|
|
bitfld.long 0x00 0. " QDEC_EN ,QDEC enable" "Disabled,Enabled"
|
|
line.long 0x04 "SAMP_CTL,QDEC Sample Control Register"
|
|
bitfld.long 0x04 16.--19. " DB_SAMP_DIV ,Debounce filter sample clock divide" "1,2,4,8,16,32,64,1,1,1,1,1,1,1,1,1"
|
|
bitfld.long 0x04 8.--11. " PTS ,Total sample points" "5,10,40,80,120,160,200,240,280,320,360,400,5,5,5,5"
|
|
bitfld.long 0x04 0.--4. " DIVIDE ,Sample clock divide" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x08++0x1B
|
|
line.long 0x00 "SAMPLE,QDEC Sample Value Register"
|
|
bitfld.long 0x00 0.--1. " SAMPLE ,Sample value" "No transition,+1 transition,-1 transition,?..."
|
|
line.long 0x04 "ACC,QDEC Valid Accumulator Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " ACC ,ACC snapshot when SAMPLE_END interrupt is valid"
|
|
line.long 0x08 "ACC_R,ACC Snapshot Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " ACC_R ,Valid sample value accumulator"
|
|
line.long 0x0C "DB,QDEC Invalid Accumulator Register"
|
|
bitfld.long 0x0C 0.--3. " DB ,Invalid sample value accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DB_R,B Snapshot Register"
|
|
bitfld.long 0x10 0.--3. " DB_R ,DB snapshot when SAMPLE_END interrupt is valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "INT,QDEC Interrupt Register"
|
|
bitfld.long 0x00 3. " DB_OF ,Double transition accumulator overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 2. " ACC_OF ,Valid sample accumulator overflow or underflow" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " SINGLE_END ,Sample end event triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " SINGLE_SAMPL ,Each normal sample is done" "Not done,Done"
|
|
line.long 0x04 "INTEN,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x04 3. " DB_OF_INTEN ,Double transition accumulator overflow interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ACC_OF_INTEN ,Valid sample accumulator overflow or underflow interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " SINGLE_END_INTEN ,Sample end event triggered interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SINGLE_SAMPLE_INTEN ,Each normal sample is done interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "STAT,QDEC Status Register"
|
|
bitfld.long 0x00 0. " QDEC_BUSY ,QDEC is running" "Idle,Running"
|
|
width 0x0B
|
|
tree.end
|
|
tree "QDEC1"
|
|
base ad:0x40009800
|
|
width 11.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "CTRL,QDEC Configuration And Control Register"
|
|
bitfld.long 0x00 6. " DB_FILTER_EN ,Debounce filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SINGLE_SAMPLE_SRST_EN ,Single sample soft reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " AUTO_CLR_EN ,Auto clear enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SOFT_CLR ,Software clear" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 2. " STOP ,Stop operation" "Not stopped,Stopped"
|
|
bitfld.long 0x00 1. " START ,Start operation" "Not started,Started"
|
|
bitfld.long 0x00 0. " QDEC_EN ,QDEC enable" "Disabled,Enabled"
|
|
line.long 0x04 "SAMP_CTL,QDEC Sample Control Register"
|
|
bitfld.long 0x04 16.--19. " DB_SAMP_DIV ,Debounce filter sample clock divide" "1,2,4,8,16,32,64,1,1,1,1,1,1,1,1,1"
|
|
bitfld.long 0x04 8.--11. " PTS ,Total sample points" "5,10,40,80,120,160,200,240,280,320,360,400,5,5,5,5"
|
|
bitfld.long 0x04 0.--4. " DIVIDE ,Sample clock divide" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x08++0x1B
|
|
line.long 0x00 "SAMPLE,QDEC Sample Value Register"
|
|
bitfld.long 0x00 0.--1. " SAMPLE ,Sample value" "No transition,+1 transition,-1 transition,?..."
|
|
line.long 0x04 "ACC,QDEC Valid Accumulator Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " ACC ,ACC snapshot when SAMPLE_END interrupt is valid"
|
|
line.long 0x08 "ACC_R,ACC Snapshot Register"
|
|
hexmask.long.word 0x08 0.--10. 1. " ACC_R ,Valid sample value accumulator"
|
|
line.long 0x0C "DB,QDEC Invalid Accumulator Register"
|
|
bitfld.long 0x0C 0.--3. " DB ,Invalid sample value accumulator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "DB_R,B Snapshot Register"
|
|
bitfld.long 0x10 0.--3. " DB_R ,DB snapshot when SAMPLE_END interrupt is valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "INT,QDEC Interrupt Register"
|
|
bitfld.long 0x00 3. " DB_OF ,Double transition accumulator overflow" "No overflow,Overflow"
|
|
bitfld.long 0x00 2. " ACC_OF ,Valid sample accumulator overflow or underflow" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " SINGLE_END ,Sample end event triggered" "Not triggered,Triggered"
|
|
bitfld.long 0x00 0. " SINGLE_SAMPL ,Each normal sample is done" "Not done,Done"
|
|
line.long 0x04 "INTEN,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x04 3. " DB_OF_INTEN ,Double transition accumulator overflow interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " ACC_OF_INTEN ,Valid sample accumulator overflow or underflow interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " SINGLE_END_INTEN ,Sample end event triggered interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " SINGLE_SAMPLE_INTEN ,Each normal sample is done interrupt" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "STAT,QDEC Status Register"
|
|
bitfld.long 0x00 0. " QDEC_BUSY ,QDEC is running" "Idle,Running"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SPIFI (SPI Flash Interface)"
|
|
base ad:0x40080000
|
|
width 8.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "CTRL,SPIFI Control Register"
|
|
bitfld.long 0x00 31. " DMAEN ,DMA Request Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " FBCLK ,Feedback clock select" "Internal,Feedback"
|
|
bitfld.long 0x00 29. " RFCLK ,Input data active edge" "Rising,Falling"
|
|
newline
|
|
bitfld.long 0x00 28. " DUAL ,Dual protocol" "Quad protocol,Dual protocol"
|
|
bitfld.long 0x00 27. " PRFTCH_DIS ,Cache prefetching disable" "No,Yes"
|
|
bitfld.long 0x00 23. " MODE3 ,SPI Mode 3 select" "SCK LOW,SCK HIGH"
|
|
newline
|
|
bitfld.long 0x00 22. " INTEN ,SPIFI Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " D_PRFTCH_DIS ,Data prefetch disable" "No,Yes"
|
|
bitfld.long 0x00 16.--19. " CSHIGH ,CS high time" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. " TIMEOUT ,Timeout value"
|
|
line.long 0x04 "CMD,SPIFI Command Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " OPCODE ,Command opcode"
|
|
bitfld.long 0x04 21.--23. " FRAMEFORM ,Opcode and address fields control" ",Opcode / no address,Opcode / 1 LSB,Opcode / 2 LSBs,Opcode / 3 LSBs,Opcode / 4 LSBs,No opcode / 3 LSBs,No opcode / 4 bytes"
|
|
bitfld.long 0x04 19.--20. " FIELDFORM ,Command fields send control" "All serial,Data quad/dual,Serial opcode,All quad/dual"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " INTLEN ,Intermediate bytes preceding data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 15. " DOUT ,Data direction" "Input,Output"
|
|
bitfld.long 0x04 14. " POLL ,Polling enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x04 0.--13. 1. " DATALEN ,Data length"
|
|
line.long 0x08 "ADDR,SPIFI Address Register"
|
|
line.long 0x0C "IDATA,SPIFI Intermediate Data Register"
|
|
line.long 0x10 "CLIMIT,SPIFI Cache Limit Register"
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "DATA,SPIFI Data Register"
|
|
in
|
|
group.long 0x18++0x07
|
|
line.long 0x00 "MCMD,SPIFI Memory Command Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " OPCODE ,Command opcode"
|
|
bitfld.long 0x00 21.--23. " FRAMEFORM ,Opcode and address fields control" ",Opcode / no address,Opcode / 1 LSB,Opcode / 2 LSBs,Opcode / 3 LSBs,Opcode / 4 LSBs,No opcode / 3 LSBs,No opcode / 4 bytes"
|
|
bitfld.long 0x00 19.--20. " FIELDFORM ,Command fields send control" "All serial,Data quad/dual,Serial opcode,All quad/dual"
|
|
newline
|
|
bitfld.long 0x00 16.--18. " INTLEN ,Intermediate bytes preceding data" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DOUT ,Data direction" "Input,Output"
|
|
bitfld.long 0x00 14. " POLL ,Polling enable" "Disabled,Enabled"
|
|
line.long 0x04 "STAT,SPIFI Status Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " VERSION ,SPIFI version"
|
|
eventfld.long 0x04 5. " INTRQ ,Interrupt request" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " RESET ,Current command or memory mode abort" "No effect,Reset"
|
|
newline
|
|
bitfld.long 0x04 1. " CMD ,Command register written" "Not written,Written"
|
|
bitfld.long 0x04 0. " MCINIT ,Memory Command register write successful" "Not written,Written"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RNG (Random Number Generator)"
|
|
base ad:0x40007C00
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,RNG Control Register"
|
|
bitfld.long 0x00 4.--5. " NUM ,RNG data bit width" "8,16,,32"
|
|
eventfld.long 0x00 0. " ENABLE ,RNG enable" "Disabled,Enabled"
|
|
rgroup.long 0x04++0x07
|
|
line.long 0x00 "STAT,RNG Status Register"
|
|
bitfld.long 0x00 0. " BUSY ,Module is in processing" "Idle,In process"
|
|
line.long 0x04 "DATA,RNG Output Data Register"
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "INT,Interrupt Status Register"
|
|
eventfld.long 0x00 0. " DONE ,Random data generate done" "Not done,Done"
|
|
line.long 0x04 "INTEN,Interrupt Enable Register"
|
|
bitfld.long 0x04 0. " DONE_INTEN ,Random data generate done mask" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CRC Engine"
|
|
base ad:0x4008E000
|
|
width 9.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "MODE,CRC Mode Register"
|
|
bitfld.long 0x00 5. " CMPL_SUM ,Data 1's complement enable for CRC_SUM" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BIT_RVS_SUM ,Bit order for CRC_SUM" "Not reversed,Reversed"
|
|
bitfld.long 0x00 3. " CMPL_WR ,Data 1's complement enable for CRC_WR_DATA" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 2. " BIT_RVS_WR ,Bit order for CRC_WR_DATA" "Not reversed,Reversed"
|
|
bitfld.long 0x00 0.--1. " CRC_POLY ,CRC polynomial select" "CRC-CCITT,CRC-16,CRC-32,CRC-32"
|
|
line.long 0x04 "SEED,CRC Seed Register"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SUM,CRC Checksum Register"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "WR_DATA,CRC Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Flash Memory Controller"
|
|
base ad:0x40081000
|
|
width 16.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "INI_RD_EN,Flash Initial Read Enable Register"
|
|
bitfld.long 0x00 0. " INI_RD_EN ,Update the flash controller lock and protection scheme" "Not updated,Updated"
|
|
line.long 0x04 "ERASE_CTRL,Flash Erase Control Register"
|
|
bitfld.long 0x04 31. " PAGE_ERASEH_EN ,Block 1 page erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " PAGE_ERASEL_EN ,Block 0 page erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 29. " HALF_ERASEH_EN ,Mass erase for block 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " HALF_ERASEL_EN ,Mass erase for block 0 enable" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.byte 0x04 8.--14. 1. " PAGE_INDXH , Block 1 page erase index"
|
|
hexmask.long.byte 0x04 0.--6. 1. " PAGE_INDXL , Block 0 page erase index"
|
|
line.long 0x08 "ERASE_TIME,Flash Erase Time Setting Register"
|
|
hexmask.long.tbyte 0x08 0.--19. 1. " ERASE_TIME_BASE ,Number of 8 MHz clock cycles to use for the erase time"
|
|
line.long 0x0C "TIME_CTRL,Flash Operation Time Setting Register"
|
|
hexmask.long.byte 0x0C 12.--19. 1. " TIME_BASE ,Amount of AHB clock cycles equal to 2 us"
|
|
hexmask.long.word 0x0C 0.--11. 1. " PRGM_CYCLE ,Maximum number of write operations"
|
|
line.long 0x10 "SMART_CTRL,Smart Erase Control Register"
|
|
bitfld.long 0x10 12.--17. " MAX_ERASE ,Maximum number of erase attempts for one smart erase operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x10 8.--11. " MAX_WRITE ,Maximum number of write attempts for one smart write operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 5. " SMART_ERASEH_EN ,Flash block 1 smart erase enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " SMART_ERASEL_EN ,Flash block 0 smart erase enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x10 3. " SMART_WRITEH_EN ,Flash block 1 smart write enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " SMART_WRITEL_EN ,Flash block 0 smart write enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " PRGMH_EN ,Flash block 1 write enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " PRGML_EN ,Flash block 0 write enable" "Disabled,Enabled"
|
|
line.long 0x14 "INT_EN,Interrupt Enable Register"
|
|
bitfld.long 0x14 31. " EMBFSH_INT_EN ,Flash interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " WR_BUFH_INT_EN ,Block 1 write buffer status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " WRITEH_INT_EN ,Block 1 write status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " ERASEH_INT_EN ,Block 1 erase status interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 9. " LOCKH_INT_EN ,Block 1 lock error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " AHBH_INT_EN ,Block 1 AHB error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " WR_BUFL_INT_EN ,Block 0 write buffer status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " WRITEL_INT_EN ,Block 0 write status interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x14 2. " ERASEL_INT_EN ,Block 0 erase status interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " LOCKL_INT_EN ,Block 0 lock error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " AHBL_INT_EN ,Block 0 AHB error interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "INT_STAT,Interrupt Status Register"
|
|
bitfld.long 0x00 14. " ERASE_FAIL_H_INT ,Smart erase on flash block 1 failed" "Not failed,Failed"
|
|
bitfld.long 0x00 13. " WRITE_FAIL_H_INT ,Smart write on flash block 1 failed" "Not failed,Failed"
|
|
bitfld.long 0x00 12. " WR_BUFH_INT ,Flash block 1 write buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 11. " WRITEH_INT ,Flash block 1 write operation completed" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 10. " ERASEH_INT ,Flash block 1 erase operation completed" "Not completed,Completed"
|
|
bitfld.long 0x00 9. " LOCKH_INT ,Flash block 1 locked page being accessed error" "No error,Error"
|
|
bitfld.long 0x00 8. " AHBH_INT ,Flash block 1 AHB error" "No error,Error"
|
|
bitfld.long 0x00 6. " ERASE_FAIL_L_INT ,Smart erase on flash block 0 failed" "Not failed,Failed"
|
|
newline
|
|
bitfld.long 0x00 5. " WRITE_FAIL_L_INT ,Smart write on flash block 0 failed" "Not failed,Failed"
|
|
bitfld.long 0x00 4. " WR_BUFL_INT ,Flash block 0 write buffer empty" "Not empty,Empty"
|
|
bitfld.long 0x00 3. " WRITEL_INT ,Flash block 0 write operation completed" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " ERASEL_INT ,Flash block 0 erase operation completed" "Not completed,Completed"
|
|
newline
|
|
bitfld.long 0x00 1. " LOCKL_INT ,Flash block 0 locked page being accessed error" "No error,Error"
|
|
bitfld.long 0x00 0. " AHBL_INT ,Flash block 0 AHB error" "No error,Error"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "INT_CLR,Interrupt Clear Register"
|
|
bitfld.long 0x00 11. " WRITEH_INT_CLR ,Clear block 1 flash write status interrupt" "Not cleared,Cleared"
|
|
bitfld.long 0x00 10. " ERASEH_INT_CLR ,Clear block 1 flash erase status interrupt" "Not cleared,Cleared"
|
|
bitfld.long 0x00 9. " LOCKH_INT_CLR ,Clear block 1 flash lock page error status interrupt" "Not cleared,Cleared"
|
|
bitfld.long 0x00 8. " AHBH_INT_CLR ,Clear block 1 flash AHB error status interrupt" "Not cleared,Cleared"
|
|
newline
|
|
bitfld.long 0x00 3. " WRITEL_INT_CLR ,Clear block 0 flash write status interrupt" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " ERASEL_INT_CLR ,Clear block 0 flash erase status interrupt" "Not cleared,Cleared"
|
|
bitfld.long 0x00 1. " LOCKL_INT_CLR ,Clear block 0 flash lock page error status interrupt" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " AHBL_INT_CLR ,Clear block 0 flash AHB error status interrupt" "Not cleared,Cleared"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "LOCK_STAT_0,Lock Status Register 0"
|
|
bitfld.long 0x00 31. " PAGE_LOCK_[31] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 30. " [30] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 29. " [29] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 28. " [28] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 26. " [26] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 25. " [25] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 24. " [24] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 22. " [22] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 21. " [21] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 20. " [20] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 18. " [18] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 17. " [17] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 16. " [16] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 12. " [12] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 9. " [9] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " [5] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Flash page lock status" "Locked,Unlocked"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "LOCK_STAT_1,Lock Status Register 1"
|
|
bitfld.long 0x00 31. " PAGE_LOCK_[31] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 30. " [30] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 29. " [29] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 28. " [28] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 26. " [26] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 25. " [25] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 24. " [24] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 22. " [22] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 21. " [21] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 20. " [20] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 18. " [18] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 17. " [17] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 16. " [16] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 12. " [12] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 9. " [9] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " [5] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Flash page lock status" "Locked,Unlocked"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "LOCK_STAT_2,Lock Status Register 2"
|
|
bitfld.long 0x00 31. " PAGE_LOCK_[31] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 30. " [30] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 29. " [29] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 28. " [28] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 26. " [26] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 25. " [25] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 24. " [24] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 22. " [22] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 21. " [21] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 20. " [20] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 18. " [18] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 17. " [17] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 16. " [16] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 12. " [12] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 9. " [9] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " [5] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Flash page lock status" "Locked,Unlocked"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "LOCK_STAT_3,Lock Status Register 3"
|
|
bitfld.long 0x00 31. " PAGE_LOCK_[31] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 30. " [30] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 29. " [29] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 28. " [28] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 26. " [26] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 25. " [25] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 24. " [24] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 22. " [22] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 21. " [21] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 20. " [20] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 18. " [18] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 17. " [17] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 16. " [16] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 12. " [12] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 9. " [9] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " [5] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Flash page lock status" "Locked,Unlocked"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "LOCK_STAT_4,Lock Status Register 4"
|
|
bitfld.long 0x00 31. " PAGE_LOCK_[31] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 30. " [30] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 29. " [29] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 28. " [28] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 26. " [26] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 25. " [25] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 24. " [24] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 22. " [22] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 21. " [21] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 20. " [20] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 18. " [18] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 17. " [17] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 16. " [16] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 12. " [12] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 9. " [9] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " [5] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Flash page lock status" "Locked,Unlocked"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "LOCK_STAT_5,Lock Status Register 5"
|
|
bitfld.long 0x00 31. " PAGE_LOCK_[31] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 30. " [30] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 29. " [29] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 28. " [28] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 26. " [26] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 25. " [25] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 24. " [24] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 22. " [22] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 21. " [21] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 20. " [20] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 18. " [18] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 17. " [17] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 16. " [16] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 12. " [12] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 9. " [9] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " [5] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Flash page lock status" "Locked,Unlocked"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "LOCK_STAT_6,Lock Status Register 6"
|
|
bitfld.long 0x00 31. " PAGE_LOCK_[31] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 30. " [30] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 29. " [29] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 28. " [28] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 26. " [26] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 25. " [25] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 24. " [24] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 22. " [22] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 21. " [21] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 20. " [20] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 18. " [18] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 17. " [17] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 16. " [16] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 12. " [12] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 9. " [9] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " [5] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Flash page lock status" "Locked,Unlocked"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "LOCK_STAT_7,Lock Status Register 7"
|
|
bitfld.long 0x00 31. " PAGE_LOCK_[31] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 30. " [30] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 29. " [29] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 28. " [28] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 27. " [27] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 26. " [26] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 25. " [25] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 24. " [24] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 23. " [23] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 22. " [22] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 21. " [21] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 20. " [20] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 19. " [19] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 18. " [18] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 17. " [17] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 16. " [16] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 15. " [15] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 14. " [14] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 13. " [13] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 12. " [12] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 11. " [11] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 10. " [10] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 9. " [9] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 8. " [8] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 7. " [7] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 6. " [6] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 5. " [5] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 4. " [4] ,Flash page lock status" "Locked,Unlocked"
|
|
newline
|
|
bitfld.long 0x00 3. " [3] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 2. " [2] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 1. " [1] ,Flash page lock status" "Locked,Unlocked"
|
|
bitfld.long 0x00 0. " [0] ,Flash page lock status" "Locked,Unlocked"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "LOCK_STAT_8,Lock Status Register 8"
|
|
bitfld.long 0x00 2. " MEM_PROTECT_EN ,SWD memory protection status" "Unprotected,Protected"
|
|
bitfld.long 0x00 1. " FSH_PROTECT_EN ,SWD flash protection status" "Unprotected,Protected"
|
|
bitfld.long 0x00 0. " MASS_ERASE_LOCK_EN ,Mass erase lock status" "Locked,Unlocked"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "STATUS1,Status Register 1"
|
|
bitfld.long 0x00 26. " FSH_STA ,Flash ready status" "Not ready,Ready"
|
|
bitfld.long 0x00 15. " INI_RD_DONE ,Flash initial read done" "In progress,Done"
|
|
bitfld.long 0x00 13. " FSH_WR_BUSY_H ,Flash block 1 write operation is in progress" "Done,In progress"
|
|
bitfld.long 0x00 12. " FSH_ERA_BUSY_H ,Flash block 1 erase operation is in progress" "Done,In progress"
|
|
newline
|
|
bitfld.long 0x00 10. " FSH_WR_BUSY_L ,Flash block 0 write operation is in progress" "Done,In progress"
|
|
bitfld.long 0x00 9. " FSH_ERA_BUSY_L ,Flash block 0 erase operation is in progress" "Done,In progress"
|
|
rgroup.long 0x5C++0x17
|
|
line.long 0x00 "ERR_INFOL_1,Flash block 0 Error Information Register 1"
|
|
bitfld.long 0x00 18.--23. " SMART_FAILL_CTR ,Amount of fails during a smart write or smart erase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " WR_FAILEDL_ADDR ,Flash block 0 smart write failed address"
|
|
line.long 0x04 "ERR_INFOL_2,Flash Block 0 Error Information Register 2"
|
|
line.long 0x08 "ERR_INFOL_3,Flash Block 0 Error Information Register 3"
|
|
hexmask.long.word 0x08 0.--15. 1. " ERA_FAILEDL_INFO ,Flash block 0 smart erase failed address"
|
|
line.long 0x0C "ERR_INFOH_1,Flash block 1 Error Information Register 1"
|
|
bitfld.long 0x0C 18.--23. " SMART_FAILH_CTR ,Amount of fails during a smart write or smart erase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.tbyte 0x0C 0.--17. 1. " WR_FAILEDH_ADDR ,Flash block 1 smart write failed address"
|
|
line.long 0x10 "ERR_INFOH_2,Flash Block 1 Error Information Register 2"
|
|
hexmask.long 0x10 0.--31. 1. " WR_FAILEDH_DATA ,Flash block 1 smart write failed data"
|
|
line.long 0x14 "ERR_INFOH_3,Flash Block 1 Error Information Register 3"
|
|
hexmask.long.word 0x14 0.--15. 1. " ERA_FAILEDH_INFO ,Flash block 1 smart erase failed address"
|
|
group.long 0xA8++0x07
|
|
line.long 0x00 "DEBUG_PASSWORD,Debug Port Access Password Register"
|
|
line.long 0x04 "ERASE_PASSWORD,Erase Password Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DAC"
|
|
base ad:0x40007400
|
|
width 11.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "ANG_CFG,DAC Analog Configuration Register"
|
|
bitfld.long 0x00 16.--19. " VCM ,Set the common mode voltage of the filter output" "800mV,900mV,1000mV,1100mV,1200mV,1300mV,1400mV,1500mV,1600mV,1700mV,1800mV,1900mV,2000mV,2100mV,2200mV,2300mV"
|
|
bitfld.long 0x00 12. " FILTER_150K_EN ,FILTER_150K enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " FILTER_BW ,Set the Miller compensation capacitance of the OPAMP" "56 fF,97.6 fF,141.5 fF,183.1 fF"
|
|
bitfld.long 0x00 4.--6. " DAC_AMP ,Set the current bias of the DAC" "50%,75%,100%,125%,150%,175%,200%,225%"
|
|
newline
|
|
bitfld.long 0x00 0.--2. " FILTER_BM ,Set the filter bias current" "50%,75%,100%,125%,150%,175%,200%,225%"
|
|
line.long 0x04 "CTRL,DAC Control Register"
|
|
bitfld.long 0x04 31. " CLK_INV ,DAC clock invert" "Not inverted,Inverted"
|
|
hexmask.long.byte 0x04 24.--30. 1. " CLK_DIV ,DAC clock divider"
|
|
bitfld.long 0x04 16.--21. " TRG_SEL ,Trigger select" "PA00,PA01,PA02,PA03,PA04,PA05,PA06,PA07,PA08,PA09,PA10,PA11,PA12,PA13,PA14,PA15,PA16,PA17,PA18,PA19,PA20,PA21,PA22,PA23,PA24,PA25,PA26,PA27,PA28,PA29,PA30,PA31,PB00,PB01,PB02,Software trigger,Software trigger,Software trigger,SCT_OUT0,SCT_OUT1,SCT_OUT2,SCT_OUT3,SCT_OUT4,SCT_OUT5,SCT_OUT6,SCT_OUT7,SCT_OUT8,SCT_OUT9,CTIMER0_MAT0,CTIMER0_MAT1,CTIMER0_MAT2,CTIMER0_MAT3,CTIMER1_MAT0,CTIMER1_MAT1,CTIMER1_MAT2,CTIMER1_MAT3,CTIMER2_MAT0,CTIMER2_MAT1,CTIMER2_MAT2,CTIMER2_MAT3,CTIMER3_MAT0,CTIMER3_MAT1,CTIMER3_MAT2,CTIMER3_MAT3"
|
|
bitfld.long 0x04 11.--12. " TRG_EDGE ,Trigger edge select" "Positive,Negative,Both,?..."
|
|
newline
|
|
bitfld.long 0x04 10. " TRG_MODE ,Trigger mode" "Single,Continuous"
|
|
bitfld.long 0x04 9. " BUF_IN_ALGN ,FIFO Input data align" "Right,Left"
|
|
bitfld.long 0x04 8. " BUF_OUT_ALGN ,FIFO and sine wave generator output data align" "Right,Left"
|
|
bitfld.long 0x04 7. " SIGN_INV ,Sets inverse sign bit" "No set,Set"
|
|
newline
|
|
bitfld.long 0x04 4.--6. " SMPL_RATE ,Sigma delta modulator down-sample rate" "8,16,32,64,128,256,512,1024"
|
|
bitfld.long 0x04 3. " MOD_WD ,Modulator output width" "1 bit,8 bit"
|
|
bitfld.long 0x04 2. " MOD_EN ,Modulator enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " SIN_EN ,Sine wave enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 0. " ENABLE ,DAC module enable" "Disabled,Enabled"
|
|
line.long 0x08 "SIN_CFG0,Sin-Wave Configuration Register 0"
|
|
hexmask.long.word 0x08 16.--31. 1. " SIN_AMP ,Sine wave amplitude"
|
|
hexmask.long.word 0x08 0.--15. 1. " SIN_FREQ ,Sine wave frequency"
|
|
line.long 0x0C "SIN_CFG1,Sin-Wave Configuration Register 1"
|
|
hexmask.long.tbyte 0x0C 0.--19. 1. " SIN_DC ,DC value of sin wave"
|
|
line.long 0x10 "GAIN_CTRL,Gain Control Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " GAIN ,Digital FIFO output multiply with GAIN_CTRL to scale to certain range"
|
|
wgroup.long 0x14++0x07
|
|
line.long 0x00 "CLR_TRG,Clear Trigger Register"
|
|
bitfld.long 0x00 1. " SW_TRG ,Software trigger" "No triggered,Triggered"
|
|
bitfld.long 0x00 0. " BUF_CLR ,Clear buffer signal" "No cleared,Cleared"
|
|
line.long 0x04 "DIN,DAC Data Input Register"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "INT,DAC Interrupt Register"
|
|
rbitfld.long 0x00 6. " BUF_HFUL_INT ,Buffer half full interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " BUF_UD_INT ,Buffer underflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " BUF_OV_INT ,Buffer overflow interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 3. " BUF_HEMT_INT ,Buffer half empty interrupt" "No interrupt,Interrupt"
|
|
newline
|
|
rbitfld.long 0x00 2. " BUF_EMT_INT ,Buffer empty interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 1. " BUF_FUL_INT ,Buffer full interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 0. " BUF_NFUL_INT ,Buffer not full interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTEN,DAC Interrupt Enable Register"
|
|
bitfld.long 0x04 6. " BUF_HFUL_INTEN ,Buffer half full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " BUF_UD_INTEN ,Buffer underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " BUF_OV_INTEN ,Buffer overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " BUF_HEMT_INTEN ,Buffer half empty interrupt enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 2. " BUF_EMT_INTEN ,Buffer empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " BUF_FUL_INTEN ,Buffer full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BUF_NFUL_INTEN ,Buffer not full interrupt enable" "Disabled,Enabled"
|
|
rgroup.long 0x24++0x07
|
|
line.long 0x00 "INT_STAT,DAC Interrupt Status Register"
|
|
bitfld.long 0x00 16. " DAC_INT_STAT ,DAC all interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " BUF_HFUL_INT_STAT ,Buffer half full interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " BUF_UD_INT_STAT ,Buffer underflow interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " BUF_OV_INT_STAT ,Buffer overflow interrupt status" "Not occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x00 3. " BUF_HEMT_INT_STAT ,Buffer half empty interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " BUF_EMT_INT_STAT ,Buffer empty interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " BUF_FUL_INT_STAT ,Buffer full interrupt status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " BUF_NFUL_INT_STAT ,Buffer not full interrupt status" "Not occurred,Occurred"
|
|
line.long 0x04 "STATUS,DAC Status Register"
|
|
bitfld.long 0x04 20.--22. " BUF_RD_PTR ,Buffer read pointer" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--18. " BUF_WR_PTR ,Buffer write pointer" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0. " BUSY ,Busy" "No busy,Busy"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC (SD ADC Controller)"
|
|
base ad:0x40007000
|
|
width 10.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "CTRL,ADC Control Register"
|
|
bitfld.long 0x00 23.--28. " TRIGGER ,ADC start trigger source selection" "PA00,PA01,PA02,PA03,PA04,PA05,PA06,PA07,PA08,PA09,PA10,PA11,PA12,PA13,PA14,PA15,PA16,PA17,PA18,PA19,PA20,PA21,PA22,PA23,PA24,PA25,PA26,PA27,PA28,PA29,PA30,PA31,PB00,PB01,PB02,Software trigger,RNG trigger,,SCT_OUT0,SCT_OUT1,SCT_OUT2,SCT_OUT3,SCT_OUT4,SCT_OUT5,SCT_OUT6,SCT_OUT7,SCT_OUT8,SCT_OUT9,CTIMER0_MAT0,CTIMER0_MAT1,CTIMER0_MAT2,CTIMER0_MAT3,CTIMER1_MAT0,CTIMER1_MAT1,CTIMER1_MAT2,CTIMER1_MAT3,CTIMER2_MAT0,CTIMER2_MAT1,CTIMER2_MAT2,CTIMER2_MAT3,CTIMER3_MAT0,CTIMER3_MAT1,CTIMER3_MAT2,CTIMER3_MAT3"
|
|
bitfld.long 0x00 21. " SRST_DIS ,ADC reset disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " VREFO_EN ,Bandgap out-chip capacitor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " DATA_FORMAT ,Data output format" "31 bit frac.,22 bit frac."
|
|
newline
|
|
bitfld.long 0x00 18. " CH_IDX_EN ,Channel index appending enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " VREF_SEL ,Sigma-delta ADC reference source selection" "Internal v_ref,External v_ref,V_ext without driver,Vcc"
|
|
bitfld.long 0x00 13. " SIG_INV_EN , Sigma-delta input signal invert" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--12. " CLKDIV ,Sigma-delta ADC clock frequency selection" "/128,/64,/32,/16,/8,/4,/2,/1"
|
|
newline
|
|
bitfld.long 0x00 8.--9. " CLKSEL ,Sigma-delta ADC clock select" "4 M,32 K,?..."
|
|
bitfld.long 0x00 7. " SW_START ,Software start ADC conversion" "Not started,Started"
|
|
bitfld.long 0x00 3. " WCMP_EN ,Window compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SCAN_EN ,Scan mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 1. " CONV_MODE ,ADC conversion mode" "Burst,Single"
|
|
bitfld.long 0x00 0. " ENABLE ,ADC enable" "Disabled,Enabled"
|
|
line.long 0x04 "CH_SEL,ADC Channel Select Register"
|
|
bitfld.long 0x04 31. " CH_SEL[31] ,ADC channel 31 select" "Not selected,Selected"
|
|
bitfld.long 0x04 30. " [30] ,ADC channel 30 select" "Not selected,Selected"
|
|
bitfld.long 0x04 29. " [29] ,ADC channel 29 select" "Not selected,Selected"
|
|
bitfld.long 0x04 28. " [28] ,ADC channel 28 select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 27. " [27] ,ADC channel 27 select" "Not selected,Selected"
|
|
bitfld.long 0x04 26. " [26] ,ADC channel 26 select" "Not selected,Selected"
|
|
bitfld.long 0x04 25. " [25] ,ADC channel 25 select" "Not selected,Selected"
|
|
bitfld.long 0x04 24. " [24] ,ADC channel 24 select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 23. " [23] ,ADC channel 23 select" "Not selected,Selected"
|
|
bitfld.long 0x04 22. " [22] ,ADC channel 22 select" "Not selected,Selected"
|
|
bitfld.long 0x04 21. " [21] ,ADC channel 21 select" "Not selected,Selected"
|
|
bitfld.long 0x04 20. " [20] ,ADC channel 20 select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 19. " [19] ,ADC channel 19 select" "Not selected,Selected"
|
|
bitfld.long 0x04 18. " [18] ,ADC channel 18 select" "Not selected,Selected"
|
|
bitfld.long 0x04 17. " [17] ,ADC channel 17 select" "Not selected,Selected"
|
|
bitfld.long 0x04 16. " [16] ,ADC channel 16 select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 15. " [15] ,ADC channel 15 select" "Not selected,Selected"
|
|
bitfld.long 0x04 14. " [14] ,ADC channel 14 select" "Not selected,Selected"
|
|
bitfld.long 0x04 13. " [13] ,ADC channel 13 select" "Not selected,Selected"
|
|
bitfld.long 0x04 12. " [12] ,ADC channel 12 select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 11. " [11] ,ADC channel 11 select" "Not selected,Selected"
|
|
bitfld.long 0x04 10. " [10] ,ADC channel 10 select" "Not selected,Selected"
|
|
bitfld.long 0x04 9. " [9] ,ADC channel 9 select" "Not selected,Selected"
|
|
bitfld.long 0x04 8. " [8] ,ADC channel 8 select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 7. " [7] ,ADC channel 7 select" "Not selected,Selected"
|
|
bitfld.long 0x04 6. " [6] ,ADC channel 6 select" "Not selected,Selected"
|
|
bitfld.long 0x04 5. " [5] ,ADC channel 5 select" "Not selected,Selected"
|
|
bitfld.long 0x04 4. " [4] ,ADC channel 4 select" "Not selected,Selected"
|
|
newline
|
|
bitfld.long 0x04 3. " [3] ,ADC channel 3 select" "Not selected,Selected"
|
|
bitfld.long 0x04 2. " [2] ,ADC channel 2 select" "Not selected,Selected"
|
|
bitfld.long 0x04 1. " [1] ,ADC channel 1 select" "Not selected,Selected"
|
|
bitfld.long 0x04 0. " [0] ,ADC channel 0 select" "Not selected,Selected"
|
|
line.long 0x08 "CH_CFG,ADC Channel Configuration Register"
|
|
bitfld.long 0x08 31. " CH_CFG[31] ,Channel 31 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 30. " [30] ,Channel 30 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 29. " [29] ,Channel 29 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 28. " [28] ,Channel 28 configuration option select" "CFG0,CFG1"
|
|
newline
|
|
bitfld.long 0x08 27. " [27] ,Channel 27 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 26. " [26] ,Channel 26 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 25. " [25] ,Channel 25 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 24. " [24] ,Channel 24 configuration option select" "CFG0,CFG1"
|
|
newline
|
|
bitfld.long 0x08 23. " [23] ,Channel 23 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 22. " [22] ,Channel 22 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 21. " [21] ,Channel 21 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 20. " [20] ,Channel 20 configuration option select" "CFG0,CFG1"
|
|
newline
|
|
bitfld.long 0x08 19. " [19] ,Channel 19 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 18. " [18] ,Channel 18 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 17. " [17] ,Channel 17 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 16. " [16] ,Channel 16 configuration option select" "CFG0,CFG1"
|
|
newline
|
|
bitfld.long 0x08 15. " [15] ,Channel 15 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 14. " [14] ,Channel 14 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 13. " [13] ,Channel 13 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 12. " [12] ,Channel 12 configuration option select" "CFG0,CFG1"
|
|
newline
|
|
bitfld.long 0x08 11. " [11] ,Channel 11 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 10. " [10] ,Channel 10 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 9. " [9] ,Channel 9 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 8. " [8] ,Channel 8 configuration option select" "CFG0,CFG1"
|
|
newline
|
|
bitfld.long 0x08 7. " [7] ,Channel 7 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 6. " [6] ,Channel 6 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 5. " [5] ,Channel 5 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 4. " [4] ,Channel 4 configuration option select" "CFG0,CFG1"
|
|
newline
|
|
bitfld.long 0x08 3. " [3] ,Channel 3 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 2. " [2] ,Channel 2 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 1. " [1] ,Channel 1 configuration option select" "CFG0,CFG1"
|
|
bitfld.long 0x08 0. " [0] ,Channel 0 configuration option select" "CFG0,CFG1"
|
|
line.long 0x0C "WCMP_THR,Window Compare Threshold Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " WCMP_THR_HIGH ,Windows compare high threshold"
|
|
hexmask.long.word 0x0C 0.--15. 1. " WCMP_THR_LOW ,Windows compare low threshold"
|
|
line.long 0x10 "INTEN,ADC Interrupt Mask Register"
|
|
bitfld.long 0x10 31. " ADC_INTEN ,ADC interrupt enable" "Not masked,Masked"
|
|
bitfld.long 0x10 2. " FIFO_OF_INTEN ,FIFO overflow interrupt enable" "Not masked,Masked"
|
|
bitfld.long 0x10 1. " WCMP_INTEN ,Window compare interrupt enable" "Not masked,Masked"
|
|
bitfld.long 0x10 0. " DAT_RDY_INTEN ,Data ready interrupt enable" "Not masked,Masked"
|
|
line.long 0x14 "INT,ADC Interrupt Status Register"
|
|
rbitfld.long 0x14 31. " ADC_INT ,ADC interrupt" "Not occurred,Occurred"
|
|
eventfld.long 0x14 2. " FIFO_OF_INT ,FIFO overflow interrupt" "Not occurred,Occurred"
|
|
eventfld.long 0x14 1. " WCMP_INT ,Window compare interrupt" "Not occurred,Occurred"
|
|
rbitfld.long 0x14 0. " DAT_RDY_INT ,Data ready interrupt" "Not occurred,Occurred"
|
|
hgroup.long 0x18++0x03
|
|
hide.long 0x00 "DATA,ADC Converted Data Register"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "CFG0,ADC Configuration 0 Register"
|
|
bitfld.long 0x00 29.--31. " SCAN_INTV0 ,Interval when switching ADC source" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x00 23.--28. " DS_DATA_STABLE0 ,Down sample date stable number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 20.--22. " DOWN_SAMPLE_RATE0 ,Filter down sample rate" ",32,,64,256,128,?..."
|
|
bitfld.long 0x00 14.--19. " PGA_VCM0 ,SD ADC PGA output common voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 13. " PGA_VCM_DIR0 ,SD ADC PGA output common voltage control direction signal" "Down,Up"
|
|
bitfld.long 0x00 12. " PGA_VCM_EN0 ,SD ADC PGA output common voltage control enable signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--11. " ADC_VCM0 ,SD ADC input common voltage selection" "1/16,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
bitfld.long 0x00 8. " VREF_GAIN0 ,SD ADC reference gain selection" "1,1.5"
|
|
newline
|
|
bitfld.long 0x00 6.--7. " ADC_GAIN0 ,SD ADC gain selection" "0.5,1,1.5,2"
|
|
bitfld.long 0x00 4.--5. " PGA_VINN0 ,SD ADC PGA VIN input offset selection" "V_ref,3/4 x V_ref,1/2 x V_ref,AVSS"
|
|
bitfld.long 0x00 3. " PGA_BP0 ,SD ADC input PGA bypass enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " PGA_GAIN0 ,SD ADC input PGA gain" "1,2,4,8,16,?..."
|
|
line.long 0x04 "CFG1,ADC Configuration 1 Register"
|
|
bitfld.long 0x04 29.--31. " SCAN_INTV1 ,Interval when switching ADC source" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x04 23.--28. " DS_DATA_STABLE1 ,Down sample date stable number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--22. " DOWN_SAMPLE_RATE1 ,Filter down sample rate" ",32,,64,256,128,?..."
|
|
bitfld.long 0x04 14.--19. " PGA_VCM1 ,SD ADC PGA output common voltage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x04 13. " PGA_VCM_DIR1 ,SD ADC PGA output common voltage control direction signal" "Down,Up"
|
|
bitfld.long 0x04 12. " PGA_VCM_EN1 ,SD ADC PGA output common voltage control enable signal" "Disabled,Enabled"
|
|
bitfld.long 0x04 9.--11. " ADC_VCM1 ,SD ADC input common voltage selection" "1/16,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
bitfld.long 0x04 8. " VREF_GAIN1 ,SD ADC reference gain selection" "1,1.5"
|
|
newline
|
|
bitfld.long 0x04 6.--7. " ADC_GAIN1 ,SD ADC gain selection" "0.5,1,1.5,2"
|
|
bitfld.long 0x04 4.--5. " PGA_VINN1 ,SD ADC PGA VIN input offset selection" "V_ref,3/4 x V_ref,1/2 x V_ref,AVSS"
|
|
bitfld.long 0x04 3. " PGA_BP1 ,SD ADC input PGA bypass enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--2. " PGA_GAIN1 ,SD ADC input PGA gain" "1,2,4,8,16,?..."
|
|
line.long 0x08 "BG_BF,ADC Bandgap And Buffer Setting Register"
|
|
bitfld.long 0x08 14. " PGA_BM_DIV2 ,PGA bias value" "Current,Half"
|
|
bitfld.long 0x08 13. " PGA_CHOP_EN ,Chopper in PGA enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " TEMP_EN ,Temperature sensor enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4.--7. " BG_SEL ,Bandgap voltage selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x08 0.--2. " PGA_BM ,SD ADC buffer bias current selection" "0.5,0.75,1,1.5,2,3,?..."
|
|
line.long 0x0C "ANA_CTRL,ADC Core And Reference Setting Register"
|
|
bitfld.long 0x0C 20. " ADC_BM_DIV2 ,SD ADC bias half value" "Current,Half"
|
|
bitfld.long 0x0C 19. " VINN_OUT_BM_X3 ,PGA VINN output driver bias current triple enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16.--18. " VINN_OUT_BM ,PGA VINN output driver bias current selection" "50%,75%,100%,150%,200%,300%,?..."
|
|
bitfld.long 0x0C 12.--14. " VINN_IN_BM ,PGA VINN input driver bias current selection" "50%,75%,100%,150%,200%,300%,?..."
|
|
newline
|
|
bitfld.long 0x0C 11. " VREF_BM_X3 ,SD ADC reference driver bias current triple enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8.--10. " VREF_BM ,SD ADC reference driver bias current selection" "50%,75%,100%,150%,200%,300%,?..."
|
|
bitfld.long 0x0C 7. " INV_CLK ,SD ADC output clock invert" "Not inverted,Inverted"
|
|
bitfld.long 0x0C 6. " CHOP_EN ,SD ADC chopper enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x0C 5. " DITHER_EN ,SD ADC PN sequence in chopper mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " ADC_ORDER ,SD ADC 2 order mode selection enable" "3 order,2 order"
|
|
bitfld.long 0x0C 0.--2. " ADC_BM ,ADC bias current selection" "50%,75%,100%,150%,200%,300%,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "Capacitive Sense"
|
|
base ad:0x40007800
|
|
width 13.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "CTRL0,Capacitive Sense Control Register 0"
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|
hexmask.long.word 0x00 16.--24. 1. " CLK_DIV ,Clock divisor"
|
|
hexmask.long.byte 0x00 2.--7. 1. " OSC_FREQ ,Relaxation oscillator frequency configuration"
|
|
bitfld.long 0x00 1. " SRST ,Soft reset enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Capacitive sense enable" "Disabled,Enabled"
|
|
line.long 0x04 "CTRL1,Capacitive Sense Control Register 1"
|
|
bitfld.long 0x04 23. " CH7 ,Capacitive sense channel 7 enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " CH6 ,Capacitive sense channel 6 enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " CH5 ,Capacitive sense channel 5 enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " CH4 ,Capacitive sense channel 4 enabled" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " CH3 ,Capacitive sense channel 3 enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " CH2 ,Capacitive sense channel 2 enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 17. " CH1 ,Capacitive sense channel 1 enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CH0 ,Capacitive sense channel 0 enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long.word 0x04 0.--15. 1. " PERIOD ,Number of clock cycles"
|
|
line.long 0x08 "INTSTAT,Interrupt Status Register"
|
|
eventfld.long 0x08 3. " SCAN_INT ,Scan done status flag for all enabled channels" "Not done,Done"
|
|
rbitfld.long 0x08 2. " FIFO_FULL_INT ,FIFO full status indicator" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 1. " FIFO_HFULL_INT ,FIFO half full status indicator" "Not occurred,Occurred"
|
|
rbitfld.long 0x08 0. " FIFO_NOTEMPTY_INT ,FIFO not empty status indicator" "Not occurred,Occurred"
|
|
line.long 0x0C "INTEN,Interrupt Enable Register"
|
|
bitfld.long 0x0C 3. " SCAN_INTEN ,Interrupt mask of SCAN_INT" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " FIFO_FULL_INT ,FIFO full status indicator" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " FIFO_HFULL_INT ,FIFO half full status indicator" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " FIFO_NOTEMPTY_INT ,FIFO not empty status indicator" "Disabled,Enabled"
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "FIFODATA,Output Data Register"
|
|
in
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "LP_CTRL,Low Power Mode Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " THR ,Threshold value"
|
|
bitfld.long 0x00 5.--7. " LP_CH ,Selects which channel index to monitor while in LP mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 4. " LP_EN ,Capacitive sense LP mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " DEBONCE_NUM ,Number of CLK_32K cycles encounter the threshold value before the wake-up interrupt is triggered" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "LP_INTSTAT,Low Power Interrupt Register"
|
|
bitfld.long 0x00 0. " LP_INT ,Counter output less than the programmed threshold value status flag" "Not occurred,Occurred"
|
|
group.long 0x1C++0x07
|
|
line.long 0x00 "LP_INTEN,Low Power Interrupt Mask Register"
|
|
bitfld.long 0x00 0. " LP_INTEN ,Interrupt enable for the LP mode interrupt" "Disabled,Enabled"
|
|
line.long 0x04 "IDLE_PERIOD,Idle Period Number Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " IDLE_PERIOD ,Number of clock cyles to wait between channel scans"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Radio"
|
|
base ad:0x4000D000
|
|
width 17.
|
|
group.long 0x2800++0x03
|
|
line.long 0x00 "LO_CFG,Analog Configuration Register"
|
|
bitfld.long 0x00 31. " LO_CHANGE ,Hop calibration enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LO_SEL ,LO divider selection" "Lookup table,Register configured"
|
|
hexmask.long.tbyte 0x00 6.--27. 1. " LO_FRAC_CFG ,LO divider factual part register"
|
|
newline
|
|
bitfld.long 0x00 0.--5. " LO_INT_CFG ,LO divider integer part register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1000++0x0B
|
|
line.long 0x00 "DP_TOP_SYS_CTRL,Datapath System Control Register"
|
|
bitfld.long 0x00 31. " DET_MODE ,Detection mode" "Low power,High performance"
|
|
bitfld.long 0x00 30. " ANT_DATA_START ,Data start ant mode signal" "Not started,Started"
|
|
bitfld.long 0x00 28.--29. " RX_MODE ,RX mode" "BLE,Base rate,Ant,Prop"
|
|
newline
|
|
bitfld.long 0x00 27. " TX_REQ ,TX request" "Not requested,Requested"
|
|
bitfld.long 0x00 26. " RX_REQ ,RX request" "Not requested,Requested"
|
|
bitfld.long 0x00 25. " TX_EN_SEL ,TX enable select signal" "BLE IP,User programmed"
|
|
newline
|
|
bitfld.long 0x00 24. " RX_EN_SEL ,RX enable select signal" "BLE IP,User programmed"
|
|
hexmask.long.byte 0x00 16.--23. 1. " H_IDX ,H index from 0.25 to 0.75"
|
|
bitfld.long 0x00 15. " PDU_LEN_SEL ,PDU length selection" "BLE IP,User programmed"
|
|
newline
|
|
bitfld.long 0x00 14. " AA_SEL ,access address selection" "BLE IP,User programmed"
|
|
hexmask.long.word 0x00 0.--13. 1. " RX_PDU_LEN_IN ,PDU length user programmed in bit"
|
|
line.long 0x04 "PROP_MODE_CTRL,Prop Mode Control Register"
|
|
bitfld.long 0x04 27.--31. " TX_POWER_DONE_TIME ,TX power down time in ant and prop mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 26. " TX_ALWAYS_ON ,TX always on" "No,Yes"
|
|
bitfld.long 0x04 25. " RX_ALWAYS_ON ,RX always on" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 24. " PROP_DIRECTION_MODE ,Prop direction find mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22.--23. " PROP_DIRECTION_RATE ,Prop direction find mode sample rate" "250 k,125 k,62.5 k,31.25k"
|
|
bitfld.long 0x04 20.--21. " PROP_DATA_RATE ,Prop mode data rate" "1 MHz,500 kHz,,250 kHz"
|
|
newline
|
|
bitfld.long 0x04 16.--18. " PROP_PRE_NUM ,Size of prop mode preamble in bytes" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x04 12.--13. " PROP_AN_NUM ,Size of prop mode network address in bytes" ",3,4,5"
|
|
bitfld.long 0x04 8.--9. " PROP_CRC_NUM ,Size of prop mode CRC" "No CRC,8 bit,16 bit,24 bit"
|
|
newline
|
|
hexmask.long.byte 0x04 0.--7. 1. " PROP_AA_ADDR_IN ,Prop mode"
|
|
line.long 0x08 "ACCESS_ADDR,Access Address Register"
|
|
hexmask.long 0x08 0.--31. 1. " AA_ADDR_IN ,Access address user programmed"
|
|
group.long 0x102C++0x07
|
|
line.long 0x00 "CRC_SEED,CRC Seed Register"
|
|
bitfld.long 0x00 24. " CRC_SEED_WEN ,Manual program crc seed enable" "Disabled,Enabled"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CRC_SEED_IN ,User programmed CRC seed"
|
|
line.long 0x04 "DP_FUNC_CTRL,Datapath Function Control Register"
|
|
bitfld.long 0x04 31. " RX_EN_MODE ,Receiver mode" "One,Repetitious"
|
|
bitfld.long 0x04 30. " TX_EN_MODE ,Transmit mode" "One,Repetitious"
|
|
bitfld.long 0x04 29. " ADC_IN_FLIP ,Exchange I and Q signals enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 28. " CFO_INI_EN ,Initial CFO enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 27. " CFO_TRACK_EN ,Tracking CFO enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " HIP_CFO_EN ,CFO estimation in HP mode enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 25. " FAGC_WEN ,Manual fine agc gain enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " FAGC_WIN_LEN ,Estimation length select" "1,2*1"
|
|
bitfld.long 0x04 23. " RESAMPLER_BP ,Resampler enable or bypass" "2,9"
|
|
newline
|
|
bitfld.long 0x04 22. " RESAMPLER_TAP_WEN ,Manual resampler tap number enable" "Auto selection,Enabled"
|
|
bitfld.long 0x04 21. " RESAMPLER_TAP ,Resampler tap number" "2,9"
|
|
bitfld.long 0x04 20. " XCORR_WIN_AUTO_EN ,Correlation window size auto selection enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 19. " XCORR_AA_LEN_WEN ,Manual correlation AA length enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " XCORR_AA_LEN ,Access address bit number select" "16,32"
|
|
bitfld.long 0x04 17. " XCORR_FULLWIN_EN ,Full sync window enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 16. " XCORR_FILT_EN ,XCORR filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " TRACK_LEN_WEN ,Manual track length enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12.--13. " TRACK_LEN ,Track length" "0,16,24,32"
|
|
newline
|
|
bitfld.long 0x04 11. " FIX_DELAY_EN ,Fix delay between max_par and burst_det" "Bitmatch,Fixed delay"
|
|
bitfld.long 0x04 10. " DC_AVE_EN ,CFO estimation average enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " FR_OFFSET_EN ,PDU frequency offset track enable" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x04 8. " LP_ADJ_MODE ,LP delay adjust mode" "58 us,49 us"
|
|
bitfld.long 0x04 7. " DOUT_ADJ_DIS ,Data delay adjust disable" "Enabled,Disabled"
|
|
bitfld.long 0x04 6. " LP_SNR_LEN_AUTO ,LP mode SNR acc length" "Fixed,Auto adjust"
|
|
newline
|
|
bitfld.long 0x04 4.--5. " CHF_COEF_IDX ,Channel filter coefficient index" "LP COEF,HP32,,HP5"
|
|
bitfld.long 0x04 3. " CHF_COEF_WEN ,Manual select channel filter coefficient enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--2. " DP_STATISTICS_SEL ,Datapath statistics selection" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x1038++0x0B
|
|
line.long 0x00 "BLE_DP_STATUS1,Datapath Status 1 Register"
|
|
bitfld.long 0x00 27. " TX_BUSY ,TX busy signal" "No busy,Busy"
|
|
bitfld.long 0x00 26. " CNR_VLD ,CNR estimation valid" "Invalid,Valid"
|
|
bitfld.long 0x00 25. " SNR_VLD ,SNR estimation valid" "Invalid,Valid"
|
|
newline
|
|
bitfld.long 0x00 24. " AGC_RSSI_READY ,Signal RSSI valid" "Invalid,Valid"
|
|
hexmask.long.byte 0x00 16.--23. 1. " AGC_RSSI ,Signal rssi db value"
|
|
bitfld.long 0x00 8.--13. " CNR_EST ,SNR estimation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. " SNR_EST ,CNR estimation"
|
|
line.long 0x04 "BLE_DP_STATUS2,Datapath Status 2 Register"
|
|
bitfld.long 0x04 31. " DP_STATUS_VLD_0 ,Data path status valid" "Invalid,Valid"
|
|
bitfld.long 0x04 30. " BURST_DET ,Indicator of burst detection" "Not sync,Sync"
|
|
bitfld.long 0x04 29. " CRC_ERROR ,Indicator of packet CRC error" "Not Occurred,Occurred"
|
|
newline
|
|
bitfld.long 0x04 16.--21. " AA_ERR_NUM ,Access address error number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.long.word 0x04 0.--15. 1. " VALID_PCK_NUM ,Received valid packet number"
|
|
line.long 0x08 "BLE_DP_STATUS3,Datapath Status 3 Register"
|
|
hexmask.long.word 0x08 16.--26. 1. " CFO_EST_FD ,Indicator of packet CRC error"
|
|
hexmask.long.word 0x08 0.--10. 1. " FD_CFO_TRACK ,Normalized cfo tracking estimation"
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "PROP_TX_BUF,Prop TX Buffer Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PROP_TX_BUF ,TX buffer"
|
|
line.long 0x04 "PROP_RX_BUF,Prop RX Buffer Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PROP_RX_BUF ,RX buffer"
|
|
line.long 0x08 "PROP_STATE,Prop Status Register"
|
|
bitfld.long 0x08 7. " PROP_CLR ,Clear PROP_INTF control register" "Not cleared,Cleared"
|
|
rbitfld.long 0x08 6. " TX_BUSY ,TX is busy" "No busy,Busy"
|
|
rbitfld.long 0x08 5. " RX_BUSY ,RX is busy" "No busy,Busy"
|
|
newline
|
|
rbitfld.long 0x08 4. " TX_INT ,TX interrupt" "Not interrupted,Interrupted"
|
|
rbitfld.long 0x08 3. " RX_INT ,RX interrupt" "Not interrupted,Interrupted"
|
|
bitfld.long 0x08 2. " RX_INT_MASK ,RX interrupt mask" "Not masked,Masked"
|
|
newline
|
|
bitfld.long 0x08 1. " TX_INT_MASK ,TX interrupt mask" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " BIT_ORDER ,Bit numbering" "LSB,MSB"
|
|
width 0x0B
|
|
tree.end
|
|
newline
|