27359 lines
1.9 MiB
27359 lines
1.9 MiB
; --------------------------------------------------------------------------------
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; @Title: CY8C4XXX-BL On-Chip Peripherals
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; @Props: Released
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; @Author: TRJ
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; @Changelog: 2017-11-06 TRJ
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; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
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; @Doc: 001-92739_PSoC_4_BLE_Registers_TRM.pdf (Rev.*C 19.02.2016)
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; 001-94624_PSoC_4XX8_BLE_Family_Datasheet.pdf (Rev.*K 11.05.2016)
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; 001-92738_PSoC_4_BLE_Architecture_TRM.pdf (Rev.*C 12.02.2016)
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; PSoC_4_BLE_Registers_TRM.pdf (Rev.*E 31.08.2017)
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; @Chip: CY8C4127FNI-BL483, CY8C4127FNI-BL493, CY8C4127LQI-BL453
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; CY8C4127LQI-BL473, CY8C4127LQI-BL483, CY8C4127LQI-BL493
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; CY8C4128FNI-BL443, CY8C4128FNI-BL453, CY8C4128FNI-BL473
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; CY8C4128FNI-BL483, CY8C4128FNI-BL493, CY8C4128FNI-BL543
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; CY8C4128FNI-BL553, CY8C4128FNI-BL563, CY8C4128FNI-BL573
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; CY8C4128FNI-BL583, CY8C4128FNI-BL593, CY8C4128LQI-BL443
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; CY8C4128LQI-BL453, CY8C4128LQI-BL473, CY8C4128LQI-BL483
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; CY8C4128LQI-BL493, CY8C4128LQI-BL543, CY8C4128LQI-BL553
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; CY8C4128LQI-BL563, CY8C4128LQI-BL573, CY8C4128LQI-BL583
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; CY8C4128LQI-BL593, CY8C4247FNI-BL483, CY8C4247FNI-BL493
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; CY8C4247LQI-BL453, CY8C4247LQI-BL463, CY8C4247LQI-BL473
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; CY8C4247LQI-BL483, CY8C4247LQI-BL493, CY8C4248FLI-BL483
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; CY8C4248FLI-BL583, CY8C4248FNI-BL453, CY8C4248FNI-BL463
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; CY8C4248FNI-BL473, CY8C4248FNI-BL483, CY8C4248FNI-BL493
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; CY8C4248FNI-BL543, CY8C4248FNI-BL553 CY8C4248FNI-BL563
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; CY8C4248FNI-BL573, CY8C4248FNI-BL583, CY8C4248FNI-BL593
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; CY8C4248FNQ-BL583
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; @Core: Cortex-M0
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perpsoc4xx8ble.per 8461 2017-11-06 14:38:10Z askoncej $
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config 16. 8.
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; Known Problems:
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; SFLASH: INITIAL_SPCIF_TRIM_M1_DAC0 [0:7] : missing "SPCIF_TRIM1"
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tree.close "Core Registers (Cortex-M0)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Nested Vectored Interrupt Controller (NVIC)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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tree "Interrupt Enable Registers"
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group.long 0x100++0x03
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line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
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tree.end
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tree "Interrupt Pending Registers"
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group.long 0x200++0x03
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line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
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setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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textline " "
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setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
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textline " "
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|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
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textline " "
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|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
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textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
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setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
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textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
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setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
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setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
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setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
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setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
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setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
sif cpuis("CY8C42*-BL*")
|
|
tree "BCTL (UDB Array Bank Control)"
|
|
base ad:0x400F6000
|
|
width 10.
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "DRV,Master Digital Clock Drive Register"
|
|
bitfld.byte 0x00 7. " DRV7 ,Master digital clock drive enable 7" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " DRV6 ,Master digital clock drive enable 6" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " DRV5 ,Master digital clock drive enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DRV4 ,Master digital clock drive enable 4" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " DRV3 ,Master digital clock drive enable 3" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " DRV2 ,Master digital clock drive enable 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DRV1 ,Master digital clock drive enable 1" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " DRV0 ,Master digital clock drive enable 0" "Disabled,Enabled"
|
|
line.byte 0x01 "MDCLK_EN,Digital Clock Enable"
|
|
bitfld.byte 0x01 7. " DCEN7 ,Master digital clock enable bit 7" "Disabled,Enabled"
|
|
bitfld.byte 0x01 6. " DCEN6 ,Master digital clock enable bit 6" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " DCEN5 ,Master digital clock enable bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " DCEN4 ,Master digital clock enable bit 4" "Disabled,Enabled"
|
|
bitfld.byte 0x01 3. " DCEN3 ,Master digital clock enable bit 3" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " DCEN2 ,Master digital clock enable bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " DCEN1 ,Master digital clock enable bit 1" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " DCEN0 ,Master digital clock enable bit 0" "Disabled,Enabled"
|
|
line.byte 0x02 "MBCLK_EN,Bus Clock Enable"
|
|
bitfld.byte 0x02 0. " BCEN ,Bank clock enable" "Disabled,Enabled"
|
|
group.byte 0x08++0x03
|
|
line.byte 0x00 "BOTSEL_L,Lower Nibble Bottom Digital Clock Select Register"
|
|
bitfld.byte 0x00 6.--7. " CLK_SEL3 ,Clock selection control for digital clock 3" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
bitfld.byte 0x00 4.--5. " CLK_SEL2 ,Clock selection control for digital clock 2" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " CLK_SEL1 ,Clock selection control for digital clock 1" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
bitfld.byte 0x00 0.--1. " CLK_SEL0 ,Clock selection control for digital clock 0" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
line.byte 0x01 "BOTSEL_U,Upper Nibble Bottom Digital Clock Select Register"
|
|
bitfld.byte 0x01 6.--7. " CLK_SEL7 ,Clock selection control for digital clock 7" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
bitfld.byte 0x01 4.--5. " CLK_SEL6 ,Clock selection control for digital clock 6" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
textline " "
|
|
bitfld.byte 0x01 2.--3. " CLK_SEL5 ,Clock selection control for digital clock 5" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
bitfld.byte 0x01 0.--1. " CLK_SEL4 ,Clock selection control for digital clock 4" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
line.byte 0x02 "TOPSEL_L,Lower Nibble Top Digital Clock Select Register"
|
|
bitfld.byte 0x02 6.--7. " CLK_SEL3 ,Clock selection control for digital clock 3" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
bitfld.byte 0x02 4.--5. " CLK_SEL2 ,Clock selection control for digital clock 2" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
textline " "
|
|
bitfld.byte 0x02 2.--3. " CLK_SEL1 ,Clock selection control for digital clock 1" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
bitfld.byte 0x02 0.--1. " CLK_SEL0 ,Clock selection control for digital clock 0" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
line.byte 0x03 "TOPSEL_U,Upper Nibble Top Digital Clock Select Register"
|
|
bitfld.byte 0x03 6.--7. " CLK_SEL7 ,Clock selection control for digital clock 7" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
bitfld.byte 0x03 4.--5. " CLK_SEL6 ,Clock selection control for digital clock 6" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
textline " "
|
|
bitfld.byte 0x03 2.--3. " CLK_SEL5 ,Clock selection control for digital clock 5" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
bitfld.byte 0x03 0.--1. " CLK_SEL4 ,Clock selection control for digital clock 4" "Edge enabled,Port input,DSI output,Synchronized DSI output"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "QCLK_EN0,Quadrant Digital Clock Enable Register 0"
|
|
bitfld.word 0x00 15. " SLEEP_TEST ,Drives sleep into the UDB array for internal UDB test purposes" "Not asserted,Asserted"
|
|
bitfld.word 0x00 14. " NC0 ,Spare register bit" "0,1"
|
|
bitfld.word 0x00 13. " WR_CFG_OPT ,Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe" "Half,Full"
|
|
textline " "
|
|
bitfld.word 0x00 12. " GLB_DSI_WR ,Enable global write operation for the DSI routing channels" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " DISABLE_ROUTE ,Route disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 10. " GCH_WR_HI ,Enable global write operation for the routing channel with the higher address in the associated quadrant" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " GCH_WR_LO ,Enable global write operation for the routing channel with the lower address in the associated quadrant" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BCEN_Q ,Bank clock enable control" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " DCEN7 ,Digital clock enable control bit 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " DCEN6 ,Digital clock enable control bit 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " DCEN5 ,Digital clock enable control bit 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " DCEN4 ,Digital clock enable control bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DCEN3 ,Digital clock enable control bit 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DCEN2 ,Digital clock enable control bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DCEN1 ,Digital clock enable control bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DCEN0 ,Digital clock enable control bit 0" "Disabled,Enabled"
|
|
group.word 0x12++0x01
|
|
line.word 0x00 "QCLK_EN1,Quadrant Digital Clock Enable Register 1"
|
|
bitfld.word 0x00 15. " SLEEP_TEST ,Drives sleep into the UDB array for internal UDB test purposes" "Not asserted,Asserted"
|
|
bitfld.word 0x00 14. " NC0 ,Spare register bit" "0,1"
|
|
bitfld.word 0x00 13. " WR_CFG_OPT ,Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe" "Half,Full"
|
|
textline " "
|
|
bitfld.word 0x00 12. " GLB_DSI_WR ,Enable global write operation for the DSI routing channels" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " DISABLE_ROUTE ,Route disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 10. " GCH_WR_HI ,Enable global write operation for the routing channel with the higher address in the associated quadrant" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " GCH_WR_LO ,Enable global write operation for the routing channel with the lower address in the associated quadrant" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BCEN_Q ,Bank clock enable control" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " DCEN7 ,Digital clock enable control bit 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " DCEN6 ,Digital clock enable control bit 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " DCEN5 ,Digital clock enable control bit 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " DCEN4 ,Digital clock enable control bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DCEN3 ,Digital clock enable control bit 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DCEN2 ,Digital clock enable control bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DCEN1 ,Digital clock enable control bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DCEN0 ,Digital clock enable control bit 0" "Disabled,Enabled"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "QCLK_EN2,Quadrant Digital Clock Enable Register 2"
|
|
bitfld.word 0x00 15. " SLEEP_TEST ,Drives sleep into the UDB array for internal UDB test purposes" "Not asserted,Asserted"
|
|
bitfld.word 0x00 14. " NC0 ,Spare register bit" "0,1"
|
|
bitfld.word 0x00 13. " WR_CFG_OPT ,Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe" "Half,Full"
|
|
textline " "
|
|
bitfld.word 0x00 12. " GLB_DSI_WR ,Enable global write operation for the DSI routing channels" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " DISABLE_ROUTE ,Route disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 10. " GCH_WR_HI ,Enable global write operation for the routing channel with the higher address in the associated quadrant" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " GCH_WR_LO ,Enable global write operation for the routing channel with the lower address in the associated quadrant" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BCEN_Q ,Bank clock enable control" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " DCEN7 ,Digital clock enable control bit 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " DCEN6 ,Digital clock enable control bit 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " DCEN5 ,Digital clock enable control bit 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " DCEN4 ,Digital clock enable control bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DCEN3 ,Digital clock enable control bit 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DCEN2 ,Digital clock enable control bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DCEN1 ,Digital clock enable control bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DCEN0 ,Digital clock enable control bit 0" "Disabled,Enabled"
|
|
group.word 0x16++0x01
|
|
line.word 0x00 "QCLK_EN3,Quadrant Digital Clock Enable Register 3"
|
|
bitfld.word 0x00 15. " SLEEP_TEST ,Drives sleep into the UDB array for internal UDB test purposes" "Not asserted,Asserted"
|
|
bitfld.word 0x00 14. " NC0 ,Spare register bit" "0,1"
|
|
bitfld.word 0x00 13. " WR_CFG_OPT ,Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe" "Half,Full"
|
|
textline " "
|
|
bitfld.word 0x00 12. " GLB_DSI_WR ,Enable global write operation for the DSI routing channels" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " DISABLE_ROUTE ,Route disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 10. " GCH_WR_HI ,Enable global write operation for the routing channel with the higher address in the associated quadrant" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " GCH_WR_LO ,Enable global write operation for the routing channel with the lower address in the associated quadrant" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BCEN_Q ,Bank clock enable control" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " DCEN7 ,Digital clock enable control bit 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " DCEN6 ,Digital clock enable control bit 6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " DCEN5 ,Digital clock enable control bit 5" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " DCEN4 ,Digital clock enable control bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DCEN3 ,Digital clock enable control bit 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " DCEN2 ,Digital clock enable control bit 2" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " DCEN1 ,Digital clock enable control bit 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DCEN0 ,Digital clock enable control bit 0" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "BLELL (BLE Link Layer)"
|
|
base ad:0x402E1000
|
|
width 31.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "COMMAND_REGISTER,Instruction Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " COMMAND ,8-bit command from firmware to the link layer controller"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EVENT_INTR,Event(Interrupt) Status And Clear Register"
|
|
bitfld.long 0x00 6. " ENC_INTR ,Encryption module interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " DSM_INTR ,Deep sleep mode exit interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " SM_INTR ,Sleep-mode-exit interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " CONN_INTR ,Connection interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INIT_INTR ,Initiator interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " SCAN_INTR ,Scanner interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADV_INTR ,Advertiser interrupt" "No interrupt,Interrupt"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "EVENT_ENABLE,Event Indications Enable"
|
|
bitfld.long 0x00 6. " ENC_INT_EN ,Encryption module interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " DSM_INT_EN ,Deep sleep mode exit interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SM_INT_EN ,Sleep-mode-exit interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CONN_INT_EN ,Connection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INIT_INT_EN ,Initiator interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SCAN_INT_EN ,Scanner interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADV_INT_EN ,Advertiser interrupt enable" "Disabled,Enabled"
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "ADV_PARAMS,Advertising Parameters Register"
|
|
rbitfld.long 0x00 15. " RCV_TX_ADDR ,Transmit address field of the received packet extracted from the receive packet" "0,1"
|
|
bitfld.long 0x00 10. " ADV_LOW_DUTY_CYCLE ,Duty cycle connectable directed advertising variant use" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RX_ADDR ,Peer addresses type" "Public,Random"
|
|
bitfld.long 0x00 5.--7. " ADV_CHANNEL_MAP ,Advertising channel select" ",,,,,Channel 37,Channel 38,Channel 39"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " ADV_FILT_POLICY ,Advertising filter policy" "Scan any/connect any,Scan white list/connect any,Scan any/connect white list,Scan white list/connect white list"
|
|
bitfld.long 0x00 1.--2. " ADV_TYPE ,Advertising type" "Connectable undirected advertising,Connectable directed advertising,Discoverable undirected advertising,Non connectable undirected advertising"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TX_ADDR ,Device own address type" "Public,Random"
|
|
line.long 0x04 "ADV_INTERVAL_TIMEOUT,Advertising Interval Register"
|
|
hexmask.long.word 0x04 0.--14. 1. " ADV_INTERVAL ,Advertising interval"
|
|
line.long 0x08 "ADV_INTR,Advertising Interrupt Status And Clear Register"
|
|
rbitfld.long 0x08 8. " ADV_ON ,Advertiser procedure is ON in hardware" "Off,On"
|
|
eventfld.long 0x08 7. " ADV_TIMEOUT ,Directed advertising event time out interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 6. " SLV_CONNECTED ,Indicates that connection is created as slave" "Master,Slave"
|
|
eventfld.long 0x08 5. " CONN_REQ_RX_INTR ,Indicates connect request packet is received" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x08 4. " SCAN_REQ_RX_INTR ,Indicates scan request packet received" "Not received,Received"
|
|
eventfld.long 0x08 3. " SCAN_RSP_TX_INTR ,Indicates scan response packet transmitted" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x08 2. " ADV_TX_INTR ,Indicates ADV packet is transmitted" "Not transmitted,Transmitted"
|
|
eventfld.long 0x08 1. " ADV_CLOSE_INTR ,Indicates current advertising event is closed" "Not closed,Closed"
|
|
textline " "
|
|
eventfld.long 0x08 0. " ADV_STRT_INTR ,Indicates a new advertising event started after interval expiry" "Not started,Started"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "ADV_NEXT_INSTANT,Advertising Next Instant"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADV_NEXT_INSTANT ,Shows the next start of advertising event with reference to the internal reference clock"
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "SCAN_INTERVAL,Scan Interval Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SCAN_INTERVAL ,Interval between two consecutive scanning events"
|
|
line.long 0x04 "SCAN_WINDOW,Scan Window Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " SCAN_WINDOW ,Duration of scan in a scanning event"
|
|
line.long 0x08 "SCAN_PARAM,Scanning Parameters Register"
|
|
bitfld.long 0x08 5. " DUP_FILT_EN ,Filter duplicate packets" "Disabled,Enabled"
|
|
bitfld.long 0x08 3.--4. " SCAN_FILT_POLICY ,The scanner filter policy determines how the scanner processes advertising packets" "Any device,Whitelist only,?..."
|
|
textline " "
|
|
bitfld.long 0x08 1.--2. " SCAN_TYPE ,Scan type" "Passive,Active,?..."
|
|
bitfld.long 0x08 0. " TX_ADDR ,Devices own address type" "Public,Random"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SCAN_INTR,Scan Interrupt Status And Clear Register"
|
|
rbitfld.long 0x00 8. " SCAN_ON ,Scan procedure status" "Not active,Active"
|
|
eventfld.long 0x00 4. " SCAN_RSP_RX_INTR ,Indicates SCAN_RSP packet is received" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ADV_RX_INTR ,Indicates ADV packet received" "Not received,Received"
|
|
eventfld.long 0x00 2. " SCAN_TX_INTR ,Indicates scan request packet is transmitted" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x00 1. " SCAN_CLOSE_INTR ,Indicates scan window is closed" "Opened,Closed"
|
|
eventfld.long 0x00 0. " SCAN_STRT_INTR ,Indicates scan window is opened" "Closed,Opened"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "SCAN_NEXT_INSTANT,Advertising Next Instant"
|
|
hexmask.long.word 0x00 0.--15. 1. " NEXT_SCAN_INSTANT ,Shows the instant with respect to internal reference clock of resolution 625us at which next scanning event begins"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "INIT_INTERVAL,Initiator Interval Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT_SCAN_INTERVAL ,Initiator interval"
|
|
line.long 0x04 "INIT_WINDOW,Initiator Window Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " INIT_SCAN_WINDOW ,Duration of scan in a scanning event"
|
|
line.long 0x08 "INIT_PARAM,Initiator Parameters Register"
|
|
bitfld.long 0x08 3. " INIT_FILT_POLICY ,Initiator filter policy" "Not used,Used"
|
|
bitfld.long 0x08 1. " RX_ADDR__RX_TX_ADDR ,Peer address type" "Public,Random"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TX_ADDR ,Device own address type" "Public,Random"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "INIT_INTR,Scan Interrupt Status And Clear Register"
|
|
bitfld.long 0x00 4. " MASTER_CONN_CREATED ,Indicates if connection is created as master" "Slave,Master"
|
|
bitfld.long 0x00 2. " INIT_TX_START_INTR ,Indicates if initiator packet (Conreq) transmission has started" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INIT_CLOSE_WINDOW_INR ,Indicates if initiator scan window has finished" "Not finished,Finished"
|
|
bitfld.long 0x00 0. " INIT_INTERVAL_EXPIRE_INTR ,Indicates if initiator scan window has started" "Not started,Started"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "INIT_NEXT_INSTANT,Initiator Next Instant"
|
|
hexmask.long.word 0x00 0.--15. 1. " INIT_NEXT_INSTANT ,Shows the instant with respect to internal reference clock of resolution 625 us at which next initiator scanning event begins"
|
|
group.long 0x58++0x0B
|
|
line.long 0x00 "DEVICE_RAND_ADDR_L,Lower 16 Bit Random Address Of The Device"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " DEVICE_RAND_ADDR_L ,Lower 16 bit of 48-bit random address of the device"
|
|
line.long 0x04 "DEVICE_RAND_ADDR_M,Middle 16 Bit Random Address Of The Device"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " DEVICE_RAND_ADDR_M ,Middle 16 bit of 48-bit random address of the device"
|
|
line.long 0x08 "DEVICE_RAND_ADDR_H,High 16 Bit Random Address Of The Device"
|
|
hexmask.long.word 0x08 0.--15. 0x01 " DEVICE_RAND_ADDR_H ,High 16 bit of 48-bit random address of the device"
|
|
group.long 0x68++0x0B
|
|
line.long 0x00 "PEER_ADDR_L,Lower 16 Bit Address Of The Peer Device"
|
|
hexmask.long.word 0x00 0.--15. 0x01 " PEER_ADDR_L ,Lower 16 bit of 48-bit address of the peer device"
|
|
line.long 0x04 "PEER_ADDR_M,Middle 16 Bit Address Of The Peer Device"
|
|
hexmask.long.word 0x04 0.--15. 0x01 " PEER_ADDR_M ,Middle 16 bit of 48-bit address of the peer device"
|
|
line.long 0x08 "PEER_ADDR_H,Higher 16 Bit Address Of The Peer Device"
|
|
hexmask.long.word 0x08 0.--15. 0x01 " PEER_ADDR_L ,Higher 16 bit of 48-bit address of the peer device"
|
|
group.long 0x78++0x0F
|
|
line.long 0x00 "WL_ADDR_TYPE,Whitelist Address Type"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " WL_ADDR_TYPE ,8 address type bits corresponding to the device address stored"
|
|
line.long 0x04 "WL_ENABLE,Whitelist Valid Entry Bit"
|
|
bitfld.long 0x04 7. " WL_ENABLE[7] ,Whitelist enable 0" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " [6] ,Whitelist enable 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " [5] ,Whitelist enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " [4] ,Whitelist enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Whitelist enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " [2] ,Whitelist enable 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " [1] ,Whitelist enable 6" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " [0] ,Whitelist enable 7" "Disabled,Enabled"
|
|
line.long 0x08 "TRANSMIT_WINDOW_OFFSET,Transmit Window Offset"
|
|
hexmask.long.word 0x08 0.--15. 1. " TX_WINDOW_OFFSET ,Tx windows offset"
|
|
line.long 0x0C "TRANSMIT_WINDOW_SIZE,Transmit Window Size"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TX_WINDOW_SIZE ,Tx window size"
|
|
group.long 0x88++0x0B
|
|
line.long 0x00 "DATA_CHANNELS_L0,Data Channel Map 0 Lower Word"
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|
hexmask.long.word 0x00 0.--15. 1. " DATA_CHANNELS_L0 ,Indicates which of the data channels are in use"
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|
line.long 0x04 "DATA_CHANNELS_M0,Data Channel Map 0 Middle Word"
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|
hexmask.long.word 0x04 0.--15. 1. " DATA_CHANNELS_M0 ,Indicates which of the data channels are in use"
|
|
line.long 0x08 "DATA_CHANNELS_H0,Data Channel Map 0 Higher Word"
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|
hexmask.long.word 0x08 0.--15. 1. " DATA_CHANNELS_H0 ,Indicates which of the data channels are in use"
|
|
group.long 0x98++0x0B
|
|
line.long 0x00 "DATA_CHANNELS_L1,Data Channel Map 1 Lower Word"
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|
hexmask.long.word 0x00 0.--15. 1. " DATA_CHANNELS_L1 ,Indicates which of the data channels are in use"
|
|
line.long 0x04 "DATA_CHANNELS_M1,Data Channel Map 1 Middle Word"
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|
hexmask.long.word 0x04 0.--15. 1. " DATA_CHANNELS_M1 ,Indicates which of the data channels are in use"
|
|
line.long 0x08 "DATA_CHANNELS_H1,Data Channel Map 1 Higher Word"
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|
hexmask.long.word 0x08 0.--15. 1. " DATA_CHANNELS_H1 ,Indicates which of the data channels are in use"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CONN_INTR,Connection Interrupt Status And Clear Register"
|
|
bitfld.long 0x00 15. " PING_NEARLY_EXPIRD_INTR ,Indicates that ping timer has nearly expired" "Not expired,Expired"
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|
bitfld.long 0x00 14. " PING_TIMER_EXPIRD_INTR ,Indicates that ping timer has expired" "Not expired,Expired"
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|
textline " "
|
|
bitfld.long 0x00 11.--13. " RX_PDU_STATUS ,Status of PDU received" "Empty,Bad packet,New data,Bad packet,,Bad packet,Duplcate packet,Bad packet"
|
|
bitfld.long 0x00 8.--10. " DISCON_STATUS ,Reason for disconnect indicates the reason the link is disconnected by hardware" ",Connection failed,Supervision timeout,Kill connection by host,Kill after ACK tranmitted,PDU timer expired,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " CON_UPDT_DONE ,Connection update done" "Not done,Done"
|
|
bitfld.long 0x00 6. " CE_RX ,Indicates that a packet is received in the connection event" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CE_TX_ACK ,Indicates that the connection event transmission acknowledgement is received for the previous non-empty packet transmitted" "Not received,Received"
|
|
bitfld.long 0x00 4. " CLOSE_CE ,Indicates that the connection event closed interrupt has happened" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x00 3. " START_CE ,Indicates that the connection event started interrupt has happened" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MAP_UPDT_DONE ,Indicates that the channel map update is completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONN_ESTB ,Indicates that the connection has been established" "Not established,Established"
|
|
bitfld.long 0x00 0. " CONN_CLOSED ,Indicates that the link is disconnected" "Not disconnected,Disconnected"
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|
rgroup.long 0xAC++0x03
|
|
line.long 0x00 "CONN_STATUS,Connection Channel Status"
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|
bitfld.long 0x00 12.--15. " RECEIVE_PACKET_COUNT ,Stores the count for the number of receive packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0xB0++0x03
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|
line.long 0x00 "CONN_INDEX,Connection Index Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONN_INDEX ,Index the multiple connections existing"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "WAKEUP_CONFIG,Wakeup Configuration"
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|
bitfld.long 0x00 10.--15. " DSM_OFFSET_TO_WAKEUP_INSTANT ,Number of slots before the wake up instant before which the hardware needs to exit from deep sleep mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
hexmask.long.byte 0x00 0.--7. 1. " OSC_STARTUP_DELAY ,Oscillator stabilization/startup delay"
|
|
group.long 0xC0++0x07
|
|
line.long 0x00 "WAKEUP_CONTROL,Wakeup Control"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAKEUP_INSTANT ,Instant ,instant, with reference to the internal 16-bit clock reference, at which the hardware must wakeup from deep sleep mode"
|
|
line.long 0x04 "CLOCK_CONFIG,Clock Control"
|
|
bitfld.long 0x04 15. " DEEP_SLEEP_MODE_EN ,Enable deep sleep mode" "Disabled,Enabled"
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|
bitfld.long 0x04 14. " SLEEP_MODE_EN ,Enable sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " SM_INTR_EN ,Enable SM exit interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " SM_AUTO_WKUP_EN ,Enable sleep mode auto wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LPO_SEL_EXTERNAL ,Select external sleep clock" "Internal generated clock,External clock"
|
|
bitfld.long 0x04 8. " LPO_CLK_FREQ_SEL ,Clock frequency select" "32khz,32.768khz"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LLH_IDLE ,Indicates if hardware is doing any transmit/receive operation" "Busy,Idle"
|
|
bitfld.long 0x04 6. " PHY_CLK_GATE_EN ,Digital PHY clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " SYSCLK_GATE_EN ,Sysclk gate enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CORECLK_GATE_EN ,Core clock gate enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CONN_CLK_GATE_EN ,Connection block clock gate enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " INIT_CLK_GATE_EN ,Initiator block clock gate enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SCAN_CLK_GATE_EN ,Scan block clock gate enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " ADV_CLK_GATE_EN ,Advertiser block clock gate enable" "Disabled,Enabled"
|
|
rgroup.long 0xC8++0x03
|
|
line.long 0x00 "TIM_COUNTER_L,Reference Clock"
|
|
hexmask.long.word 0x00 0.--15. 1. " TIM_REF_CLOCK ,16-bit internal reference clock"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "POC_REG__TIM_CONTROL,BLE Time Control"
|
|
bitfld.long 0x00 3.--7. " BB_CLK_FREQ_MINUS_1 ,LLH clock configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
wgroup.long 0xE0++0x03
|
|
line.long 0x00 "ADV_TX_DATA_FIFO,Advertising Data Transmit FIFO"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADV_TX_DATA ,IO mapped FIFO of depth 16 to store ADV data of maximum length 31 bytes for transmitting"
|
|
wgroup.long 0xE8++0x03
|
|
line.long 0x00 "ADV_SCN_RSP_TX_FIFO,Advertising Scan Response Data Transmit FIFO"
|
|
hexmask.long.word 0x00 0.--15. 1. " SCAN_RSP_DATA ,IO mapped FIFO of depth 16 to store scan response data of maximum length 31 bytes for transmitting"
|
|
rgroup.long 0xF8++0x03
|
|
line.long 0x00 "INIT_SCN_ADV_RX_FIFO,Advertising Scan Response Data Receive Data FIFO"
|
|
hexmask.long.word 0x00 0.--15. 1. " ADV_SCAN_RSP_RX_DATA ,IO mapped FIFO of depth 64 to store ADV and SCAN_RSP header and payload received by the scanner"
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "CONN_INTERVAL,Connection Interval"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNECTION_INTERVAL ,Spacing be-tween the connection events"
|
|
line.long 0x04 "SUP_TIMEOUT,Supervision Timeout"
|
|
hexmask.long.word 0x04 0.--15. 1. " SUPERVISION_TIMEOUT ,Maximum time between two received data packet pdus before the connection is considered lost"
|
|
line.long 0x08 "SLAVE_LATENCY,Slave Latency"
|
|
hexmask.long.word 0x08 0.--15. 1. " SLAVE_LATENCY ,Consecutive connection events that the slave device is not required to listen for master"
|
|
line.long 0x0C "CE_LENGTH,Connection Event Length"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CONNECTION_EVENT_LENGTH ,Length of connection event"
|
|
line.long 0x10 "PDU_ACCESS_ADDR_L_REGISTER,Access Address Lower"
|
|
hexmask.long.word 0x10 0.--15. 1. " PDU_ACCESS_ADDRESS_LOWER_BITS ,Lower 16 bits of the access address for each link layer connection between any two devices"
|
|
line.long 0x14 "PDU_ACCESS_ADDR_H_REGISTER,Access Address Higher"
|
|
hexmask.long.word 0x14 0.--15. 1. " PDU_ACCESS_ADDRESS_HIGHER_BITS ,Higher 16 bits of the access address for each link layer connection between any two devices"
|
|
line.long 0x18 "CONN_CE_INSTANT,Connection Event Instant"
|
|
hexmask.long.word 0x18 0.--15. 1. " CE_INSTANT ,Free running connection event"
|
|
line.long 0x1C "CE_CNFG_STS_REGISTER,Connection Configuration & Status Register"
|
|
rbitfld.long 0x1C 12.--15. " CURRENT_PDU_INDEX ,The index of the transmit packet buffer that is currently in transmission/waiting for transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x1C 10. " CONN_ACTIVE ,This bit is 1 whenever the connection is active" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " PAUSE_DATA ,Pause data" "Not paused,Paused"
|
|
bitfld.long 0x1C 7. " MAP_INDEX__CURR_INDEX ,Written by firmware to select the map index to be used by hardware for this connection" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " MD ,MD bit set to 1 indicates device has more data to be sent" "0,1"
|
|
bitfld.long 0x1C 5. " MAS_SLV ,Indicates that device is confi-gured as a master or a slave" "Slave,Master"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " DATA_LIST_HEAD_UP ,Update the first packet buffer index ready for transmission to start/resume data transfer after a pause" "Not started,Started"
|
|
bitfld.long 0x1C 0.--3. " DATA_LIST_INDEX_LAST_ACK_INDEX ,Data list index for start/resume" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x120++0x07
|
|
line.long 0x00 "NEXT_CE_INSTANT,Next Connection Event Instant"
|
|
hexmask.long.word 0x00 0.--15. 1. " NEXT_CE_INSTANT ,16-bit internal reference clock value at which the next connection event will occur on a connection"
|
|
line.long 0x04 "CONN_CE_COUNTER,Connection Event Counter"
|
|
hexmask.long.word 0x04 0.--15. 1. " CONNECTION_EVENT_COUNTER ,This is the free running counter conneventcounter as defined by bluetooth spec"
|
|
group.long 0x128++0x07
|
|
line.long 0x00 "DATA_LIST_SENT_UPDATE__STATUS,Data List Sent Update And Status"
|
|
bitfld.long 0x00 7. " SET_CLEAR ,Sets the SENT bit in hardware for the selected packet buffer" "0,1"
|
|
rbitfld.long 0x00 4. " TX_SENT_4 ,Status of the SENT bit in the hard-ware for each packet buffer" "No packet,Queued"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " LIST_INDEX__TX_SENT_3_0 ,Status of the SENT bit in the hard-ware for each packet buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "DATA_LIST_ACK_UPDATE__STATUS,Data List Ack Update And Status"
|
|
bitfld.long 0x04 7. " SET_CLEAR ,Sets the ACK bit in hardware for the selected packet buffer" "0,1"
|
|
rbitfld.long 0x04 4. " TX_ACK_4 ,Status of the ACK bit in the hard-ware for each packet buffer" "No packet,Queued"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " LIST_INDEX__TX_ACK_3_0 ,Status of the ACK bit in the hard-ware for each packet buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DATA_MEM_DESCRIPTOR0,Data Buffer Descriptor 0 To 4"
|
|
bitfld.long 0x00 2.--6. " DATA_LENGTH ,Length of the data packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--1. " LLID ,The LLID indicates whether the packet is an LL data PDU or an LL control PDU" ",Fragment L2CAP message/empty,Start/end L2CAP message,LL control PDU"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DATA_MEM_DESCRIPTOR1,Data Buffer Descriptor 0 To 4"
|
|
bitfld.long 0x00 2.--6. " DATA_LENGTH ,Length of the data packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--1. " LLID ,The LLID indicates whether the packet is an LL data PDU or an LL control PDU" ",Fragment L2CAP message/empty,Start/end L2CAP message,LL control PDU"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "DATA_MEM_DESCRIPTOR2,Data Buffer Descriptor 0 To 4"
|
|
bitfld.long 0x00 2.--6. " DATA_LENGTH ,Length of the data packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--1. " LLID ,The LLID indicates whether the packet is an LL data PDU or an LL control PDU" ",Fragment L2CAP message/empty,Start/end L2CAP message,LL control PDU"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "DATA_MEM_DESCRIPTOR3,Data Buffer Descriptor 0 To 4"
|
|
bitfld.long 0x00 2.--6. " DATA_LENGTH ,Length of the data packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--1. " LLID ,The LLID indicates whether the packet is an LL data PDU or an LL control PDU" ",Fragment L2CAP message/empty,Start/end L2CAP message,LL control PDU"
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "DATA_MEM_DESCRIPTOR4,Data Buffer Descriptor 0 To 4"
|
|
bitfld.long 0x00 2.--6. " DATA_LENGTH ,Length of the data packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--1. " LLID ,The LLID indicates whether the packet is an LL data PDU or an LL control PDU" ",Fragment L2CAP message/empty,Start/end L2CAP message,LL control PDU"
|
|
group.long 0x160++0x07
|
|
line.long 0x00 "WINDOW_WIDEN_INTVL,Window Widen For Interval"
|
|
hexmask.long.word 0x00 0.--11. 1. " WINDOW_WIDEN_INTVL ,Increased listening time for the slave"
|
|
line.long 0x04 "WINDOW_WIDEN_WINOFF,Window Widen For Offset"
|
|
hexmask.long.word 0x04 0.--11. 1. " WINDOW_WIDEN_WINOFF ,Additional number of microseconds the slave must extend its listening window to listen for a master packet"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "LE_RF_TEST_MODE,Direct Test Mode Control"
|
|
bitfld.long 0x00 10.--15. " TEST_LENGTH ,Length in bytes of payload data in each packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,?..."
|
|
bitfld.long 0x00 7.--9. " PKT_PAYLOAD ,Payload type as per the HCI parameter" "Pseudo-Random bit sequence 9,Pattern of alter-nating bits 11110000,Pattern of alternating bits 10101010,Pseudo-Random bit sequence 15,Pat-tern of all 1 bits,Pattern of all 0 bits,Pattern of alternating bits 00001111,Pattern of alternating bits 0101"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TEST_TYPE ,DTM test" "Off,On"
|
|
bitfld.long 0x00 0.--5. " TEST_FREQUENCY ,Frequency range" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x174++0x03
|
|
line.long 0x00 "DTM_RX_PKT_COUNT,Direct Test Mode Receive Packet Count"
|
|
hexmask.long.word 0x00 0.--15. 1. " RX_PACKET_COUNT ,Number of packets received in receive test mode"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "TXRX_HOP,Channel Address Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. " HOP_CH_RX ,Receive channel index"
|
|
hexmask.long.byte 0x00 0.--6. 1. " HOP_CH_TX ,Transmit channel index"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "TX_RX_ON_DELAY,Transmit/receive Data Delay"
|
|
hexmask.long.byte 0x00 8.--15. 1. " TXON_DELAY ,Transmit delay"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXON_DELAY ,Receive delay"
|
|
group.long 0x1C0++0x3B
|
|
line.long 0x00 "DEV_PUB_ADDR_L,Device Public Address Lower Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DEV_PUB_ADDR_L ,Lower 16 bit of 48-bit public address of the device"
|
|
line.long 0x04 "DEV_PUB_ADDR_M,Device Public Address Middle Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " DEV_PUB_ADDR_M ,Middle 16 bit of 48-bit public address of the device"
|
|
line.long 0x08 "DEV_PUB_ADDR_H,Device Public Address Higher Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " DEV_PUB_ADDR_H ,Higher 16 bit of 48-bit public address of the device"
|
|
line.long 0x0C "ADV_CH_TX_POWER,Advetising Channel Transmit Power"
|
|
hexmask.long.word 0x0C 0.--15. 1. " ADV_TRANSMIT_POWER ,Advetising transmit power"
|
|
line.long 0x10 "OFFSET_TO_FIRST_INSTANT,Offset To First Instant"
|
|
hexmask.long.word 0x10 0.--15. 1. " OFFSET_TO_FIRST_EVENT ,The offset w.r.t the internal reference clock at which instant the first event occurs"
|
|
line.long 0x14 "ADV_CONFIG,Advertiser Configuration Register"
|
|
bitfld.long 0x14 11.--15. " ADV_PKT_INTERVAL ,Time between the beginning of two consecutive advertising pdus" "0,0.625,1.25,1.875,2.5,3.125,3.750,4.375,5,5.625,6.25,6.875,7.5,8.125,8.750,9.375,10,?..."
|
|
bitfld.long 0x14 8. " ADV_RAND_DISABLE ,Disable randomization of adv interval" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ADV_TIMEOUT_EN ,Enable adv_timeout interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " SLV_CONNECTED_EN ,Enable slave connected interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " ADV_CONN_REQ_RX_EN ,Enable connect request packet received interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " ADV_SCN_REQ_RX_EN ,Enable scan request packet received interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " SCN_RSP_TX_EN ,Enable scan response packet transmitted interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " ADV_TX_EN ,Enable adv packet transmitted interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ADV_CLS_EN ,Enable advertising event stop interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " ADV_STRT_EN ,Enable advertising event start interrupt" "Disabled,Enabled"
|
|
line.long 0x18 "SCAN_CONFIG,Scan Configuration Register"
|
|
bitfld.long 0x18 13.--15. " SCAN_CHANNEL_MAP ,Advertising channels that are enabled for scanning operation" "Disabled,37,38,37/38,39,37/39,38/39,All"
|
|
bitfld.long 0x18 11. " BACKOFF_ENABLE ,Enable random backoff feature in scanner" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " SCN_RSP_RX_EN ,Enable scan_rsp packet received interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x18 3. " ADV_RX_EN ,Enable adv packet received interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 2. " SCN_TX_EN ,Enable scan request packet transmitted interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x18 1. " SCN_CLOSE_EN ,Enable scan event close interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " SCN_STRT_EN ,Enable scan event start interrupt" "Disabled,Enabled"
|
|
line.long 0x1C "INIT_CONFIG,Initiator Configuration Register"
|
|
bitfld.long 0x1C 13.--15. " INIT_CHANNEL_MAP ,Advertising channels that are enabled for initiator scanning operation" "Disabled,37,38,37/38,39,37/39,38/39,All"
|
|
bitfld.long 0x1C 4. " CONN_CREATED ,Enable master connection created interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " CONN_REQ_TX_EN ,Enables connection request packet transmission start interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " INIT_CLOSE_EN ,Enable initiator event close interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " INIT_STRT_EN ,Enable initiator event start interrupt" "Disabled,Enabled"
|
|
line.long 0x20 "CONN_CONFIG,Connection Configuration Register"
|
|
bitfld.long 0x20 15. " CONN_REQ_1SLOT_EARLY ,Enable extension of the conn request to arbiter to 1 slot early" "Disabled,Enabled"
|
|
bitfld.long 0x20 14. " MASK_SUTO_AT_UPDT ,Enable masking of internal hardware supervision timeout trigger when switching from old connection parameters to new parameters" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 13. " EXTEND_CU_TX_WIN ,Enable extending the additional rx window on slave side during connection update in event of packet miss at the update instant" "Disabled,Enabled"
|
|
bitfld.long 0x20 12. " SLV_MD_CONFIG ,Configure the MD bit control when IUT is in slave role" "Pending,Queued"
|
|
textline " "
|
|
bitfld.long 0x20 11. " DSM_SLOT_VARIANCE ,DSM slot counting mode" "Less,More"
|
|
bitfld.long 0x20 8. " MD_BIT_CLEAR ,MD (More data) bit needs to be controlled by software or hardware and software logic combined" "Software,Both"
|
|
textline " "
|
|
bitfld.long 0x20 4.--7. " RX_INTR_THRESHOLD ,Allows setting a threshold for the packet received interrupt to the firmware" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x20 0.--3. " RX_PKT_LIMIT ,Defines a limit for the number of rx packets that can be re-ceived by the LLH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x24 "CONN_CH_TX_POWER,Connection Channel Transmit Power"
|
|
hexmask.long.word 0x24 0.--15. 1. " CONNCH_TRANSMIT_POWER ,Transmit power to be used for all packets transmitted on the connection channel"
|
|
line.long 0x28 "CONN_PARAM1,Connection Parameter 1"
|
|
hexmask.long.byte 0x28 8.--15. 1. " CRC_INIT_L ,Lower byte (7:0) of the CRC initialization vector"
|
|
bitfld.long 0x28 3.--7. " HOP_INCREMENT_PARAM ,Hop increment for connection channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " SCA_PARAM ,Sleep clock accuracy" "0,1,2,3,4,5,6,7"
|
|
line.long 0x2C "CONN_PARAM2,Connection Parameter 2"
|
|
hexmask.long.word 0x2C 0.--15. 1. " CRC_INIT_H ,Upper two bytes (23:8) of the CRC initialization vector"
|
|
line.long 0x30 "CONN_INTR_MASK,Connection Interrupt Mask"
|
|
bitfld.long 0x30 15. " PING_NEARLY_EXPIRD_INTR ,Ping timer nearly expired interrupt is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x30 14. " PING_TIMER_EXPIRD_INTR ,Ping timer expired interrupt is enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 9. " RX_BAD_PDU_INT_EN ,Packet receive bad pdu interrupt is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x30 8. " RX_GOOD_PDU_INT_EN ,Packet receive good pdu interrupt is enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 7. " CONN_UPDATE_INTR_EN ,Connection update interrupt is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x30 6. " CE_RX_INT_EN ,Interrupt is enabled for reception of packet in a connection event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 5. " CE_TX_ACK_INT_EN ,Transmission acknowledgement interrupt is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x30 4. " CLOSE_CE_INT_EN ,Connection event closed interrupt is enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 3. " START_CE_INT_EN ,Connection event start interrupt is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x30 2. " MAP_UPDT_INT_EN ,Channel map update interrupt is enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 1. " CONN_ESTB_INT_EN ,Connection establishment interrupt is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x30 0. " CONN_CL_INT_EN ,Connection closed interrupt is enabled" "Disabled,Enabled"
|
|
line.long 0x34 "SLAVE_TIMING_CONTROL,Slave Timing Control"
|
|
hexmask.long.byte 0x34 8.--15. 1. " SLAVE_TIME_ADJ_VAL ,Timing adjust value"
|
|
hexmask.long.byte 0x34 0.--7. 1. " SLAVE_TIME_SET_VAL ,Programmable adjust value to the clock counter when slave is connected"
|
|
line.long 0x38 "RECEIVE_TRIG_CTRL,Receive Trigger Control"
|
|
hexmask.long.byte 0x38 8.--15. 1. " ACC_TRIGGER_TIMEOUT ,If access address match does not occur then within this time from the start of receive operation the receive operation times out and stops"
|
|
bitfld.long 0x38 0.--5. " ACC_TRIGGER_THRESHOLD ,Access address match threshold value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,?..."
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "DPLL_CONFIG,DPLL & CY Correlator Configuration Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DPLL_CORREL_CONFIG ,DPLL & CY correlator configuration"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "WHITELIST_BASE_ADDR,Whitelist Base Address"
|
|
hexmask.long.word 0x00 0.--15. 1. " WL_BASE_ADDR ,Device address values written to white list memory are written as 16-bit wide address"
|
|
group.long 0x3A4++0x0F
|
|
line.long 0x00 "CONN_UPDATE_NEW_INTERVAL,Connection Update New Interval"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONN_UPDT_INTERVAL ,New connection interval that the hardware will use after the connection update instant"
|
|
line.long 0x04 "CONN_UPDATE_NEW_LATENCY,Connection Update New Latency"
|
|
hexmask.long.word 0x04 0.--15. 1. " CONN_UPDT_SLV_LATENCY ,New slave latency parameter that the hardware will use after the connection update instant"
|
|
line.long 0x08 "CONN_UPDATE_NEW_SUP_TO,Connection Update New Supervision Timeout"
|
|
hexmask.long.word 0x08 0.--15. 1. " CONN_UPDT_SUP_TO ,New supervision timeout that the hardware will use after the connection update instant"
|
|
line.long 0x0C "CONN_UPDATE_NEW_SL_INTERVAL,Connection Update New Slave Latency X Conn Interval Value"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SL_CONN_INTERVAL_VAL ,New slave latency * conn interval value that the hardware will use after the connection update instant"
|
|
group.long 0x3C0++0x2F
|
|
line.long 0x00 "CONN_REQ_WORD0,Connection Request Address Word 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " ACCESS_ADDR_LOWER ,Lower 16 bits of the access address that is to be sent in the connect request packet of the initiator"
|
|
line.long 0x04 "CONN_REQ_WORD1,Connection Request Address Word 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " ACCESS_ADDR_UPPER ,Upper 16 bits of the access address that is to be sent in the connect request packet of the initiator"
|
|
line.long 0x08 "CONN_REQ_WORD2,Connection Request Address Word 2"
|
|
hexmask.long.byte 0x08 8.--15. 1. " CRC_INIT_LOWER ,Lower byte [7:0] of the CRC initialization value"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TX_WINDOW_SIZE_VAL ,Window_size along with the window_offset is used to calculate the first connection point anchor point for the master"
|
|
line.long 0x0C "CONN_REQ_WORD3,Connection Request Address Word 3"
|
|
hexmask.long.word 0x0C 0.--15. 1. " CRC_INIT_UPPER ,Upper byte [23:8] of the CRC initialization value that is to be sent in the connect request packet of the initiator"
|
|
line.long 0x10 "CONN_REQ_WORD4,Connection Request Address Word 4"
|
|
hexmask.long.word 0x10 0.--15. 1. " TX_WINDOW_OFFSET ,Anchor point for the master transmission"
|
|
line.long 0x14 "CONN_REQ_WORD5,Connection Request Address Word 5"
|
|
hexmask.long.word 0x14 0.--15. 1. " CONNECTION_INTERVAL_VAL ,Spacing between the connection events"
|
|
line.long 0x18 "CONN_REQ_WORD6,Connection Request Address Word 6"
|
|
hexmask.long.word 0x18 0.--15. 1. " SLAVE_LATENCY_VAL ,Number of consecutive connection events that the slave device is not required to listen for master"
|
|
line.long 0x1C "CONN_REQ_WORD7,Connection Request Address Word 7"
|
|
hexmask.long.word 0x1C 0.--15. 1. " SUPERVISION_TIMEOUT_VAL ,Maximum time between two received data packet pdus before the connection is considered lost"
|
|
line.long 0x20 "CONN_REQ_WORD8,Connection Request Address Word 8"
|
|
hexmask.long.word 0x20 0.--15. 1. " DATA_CHANNELS_LOWER ,Which of the data channels are in use"
|
|
line.long 0x24 "CONN_REQ_WORD9,Connection Request Address Word 9"
|
|
hexmask.long.word 0x24 0.--15. 1. " DATA_CHANNELS_MID ,Which of the data channels are in use"
|
|
line.long 0x28 "CONN_REQ_WORD10,Connection Request Address Word 10"
|
|
hexmask.long.word 0x28 0.--15. 1. " DATA_CHANNELS_UPPER ,Which of the data channels are in use"
|
|
line.long 0x2C "CONN_REQ_WORD11,Connection Request Address Word 11"
|
|
bitfld.long 0x2C 5.--7. " SCA_2 ,Sleep clock accuracies given in ppm" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x2C 0.--4. " HOP_INCREMENT_2 ,This field is used for the data channel selection process" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x400++0x0B
|
|
line.long 0x00 "PACKET_COUNTER0,Packet Counter 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " PACKET_COUNTER_LOWER ,Lower 16-bits of the packet counter value passed as part of nonce for the packet to be encrypted"
|
|
line.long 0x04 "PACKET_COUNTER1,Packet Counter 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " PACKET_COUNTER_MIDDLE ,Middle 16-bits of the packet counter value passed as part of nonce for the packet to be encrypted"
|
|
line.long 0x08 "PACKET_COUNTER2,Packet Counter 2"
|
|
hexmask.long.word 0x08 0.--15. 1. " PACKET_COUNTER_UPPER ,UPPER 16-bits of the packet counter value passed as part of nonce for the packet to be encrypted"
|
|
group.long 0x410++0x0F
|
|
line.long 0x00 "IV_MASTER0,Master Initialization Vector 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " IV_MASTER_LOWER ,Lower 16-bits of the ivm field which contains the masters portion of the initialization vector"
|
|
line.long 0x04 "IV_MASTER1,Master Initialization Vector 1"
|
|
hexmask.long.word 0x04 0.--15. 1. " IV_MASTER_UPPER ,Upper 16-bits of the ivm field which contains the masters portion of the initialization vector"
|
|
line.long 0x08 "IV_SLAVE0,Slave Initialization Vector 0"
|
|
hexmask.long.word 0x08 0.--15. 1. " IV_SLAVE_LOWER ,Lower 16-bits of the ivm field which contains the slaves portion of the initialization vector"
|
|
line.long 0x0C "IV_SLAVE1,Slave Initialization Vector 1"
|
|
hexmask.long.word 0x0C 0.--15. 1. " IV_SLAVE_UPPER ,Upper 16-bits of the ivm field which contains the slaves portion of the initialization vector"
|
|
wgroup.long 0x420++0x03
|
|
line.long 0x00 "ENC_KEY0,Encryption Key Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " ENC_KEY ,The encryption key / session key which is used in ECB encryption CCM encryption and CCM decryption"
|
|
wgroup.long 0x424++0x03
|
|
line.long 0x00 "ENC_KEY1,Encryption Key Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " ENC_KEY ,The encryption key / session key which is used in ECB encryption CCM encryption and CCM decryption"
|
|
wgroup.long 0x428++0x03
|
|
line.long 0x00 "ENC_KEY2,Encryption Key Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " ENC_KEY ,The encryption key / session key which is used in ECB encryption CCM encryption and CCM decryption"
|
|
wgroup.long 0x42C++0x03
|
|
line.long 0x00 "ENC_KEY3,Encryption Key Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " ENC_KEY ,The encryption key / session key which is used in ECB encryption CCM encryption and CCM decryption"
|
|
wgroup.long 0x430++0x03
|
|
line.long 0x00 "ENC_KEY4,Encryption Key Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " ENC_KEY ,The encryption key / session key which is used in ECB encryption CCM encryption and CCM decryption"
|
|
wgroup.long 0x434++0x03
|
|
line.long 0x00 "ENC_KEY5,Encryption Key Register 5"
|
|
hexmask.long.word 0x00 0.--15. 1. " ENC_KEY ,The encryption key / session key which is used in ECB encryption CCM encryption and CCM decryption"
|
|
wgroup.long 0x438++0x03
|
|
line.long 0x00 "ENC_KEY6,Encryption Key Register 6"
|
|
hexmask.long.word 0x00 0.--15. 1. " ENC_KEY ,The encryption key / session key which is used in ECB encryption CCM encryption and CCM decryption"
|
|
wgroup.long 0x43C++0x03
|
|
line.long 0x00 "ENC_KEY7,Encryption Key Register 7"
|
|
hexmask.long.word 0x00 0.--15. 1. " ENC_KEY ,The encryption key / session key which is used in ECB encryption CCM encryption and CCM decryption"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "DATA0,Input / Output Data Register 0"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA0 ,Input / output data"
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "DATA1,Input / Output Data Register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA1 ,Input / output data"
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "DATA2,Input / Output Data Register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA2 ,Input / output data"
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "DATA3,Input / Output Data Register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA3 ,Input / output data"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "DATA4,Input / Output Data Register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA4 ,Input / output data"
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "DATA5,Input / Output Data Register 5"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA5 ,Input / output data"
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "DATA6,Input / Output Data Register 6"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA6 ,Input / output data"
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "DATA7,Input / Output Data Register 7"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA7 ,Input / output data"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "DATA8,Input / Output Data Register 8"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA8 ,Input / output data"
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "DATA9,Input / Output Data Register 9"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA9 ,Input / output data"
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "DATA10,Input / Output Data Register 10"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA10 ,Input / output data"
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "DATA11,Input / Output Data Register 11"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA11 ,Input / output data"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "DATA12,Input / Output Data Register 12"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA12 ,Input / output data"
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "DATA13,Input / Output Data Register 13"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA13 ,Input / output data"
|
|
group.long 0x478++0x07
|
|
line.long 0x00 "MIC_IN0,MIC Input Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MIC_IN_LOWER ,Lower 16-bits of the MIC field used for CCM decryption"
|
|
line.long 0x04 "MIC_IN1,MIC Input Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MIC_IN_UPPER ,Upper 16-bits of the MIC field used for CCM decryption"
|
|
rgroup.long 0x480++0x07
|
|
line.long 0x00 "MIC_OUT0,MIC Output Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MIC_OUT_LOWER ,Lower 16-bits of the MIC generated during CCM encryption"
|
|
line.long 0x04 "MIC_OUT1,MIC Output Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MIC_OUT_UPPER ,Upper 16-bits of the MIC generated during CCM encryption"
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "ENC_PARAMS,Encryption Parameter Register"
|
|
bitfld.long 0x00 7. " DIRECTION ,Data channel direction" "Slave,Master"
|
|
bitfld.long 0x00 2.--6. " PAYLOAD_LENGTH ,Length of the input data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DATA_PDU_HEADER ,LLID of the packet" "0,1,2,3"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "ENC_CONFIG,Encryption Configuration"
|
|
bitfld.long 0x00 2. " DEC_ENC ,Decryption/encryption" "Encrypt,Decrypt"
|
|
bitfld.long 0x00 1. " ECB_CCM ,ECB/CCM" "CCM,ECB"
|
|
textline " "
|
|
bitfld.long 0x00 0. " START_PROC ,Start the AES processing" "Not started,Started"
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "ENC_INTR_EN,Encryption Interrupt Enable"
|
|
bitfld.long 0x00 2. " CCM_PROC_INTR_EN ,CCM processed interupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ECB_PROC_INTR_EN ,ECB processed interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTH_PASS_INTR_EN ,Authentication interrupt enable" "Disabled,Enabled"
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "ENC_INTR,Encryption Interrupt Status And Clear Register"
|
|
bitfld.long 0x00 3. " IN_DATA_CLEAR ,Clears the input data" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CCM_PROC_INTR ,CCM processed interrupt" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ECB_PROC_INTR ,ECB processed interrupt" "Not cleared,Cleared"
|
|
bitfld.long 0x00 0. " AUTH_PASS_INTR ,Authentication interrupt" "Not cleared,Cleared"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "CONN_TXMEM_BASE_ADDR,Connection TX Memory Base Address"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONN_TX_MEM_BASE_ADDR ,Data values written to tx memory are written as 16-bit wide data"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "CONN_RXMEM_BASE_ADDR,Connection RX Memory Base Address"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONN_RX_MEM_BASE_ADDR ,Data values written to rx memory are written as 16-bit wide data"
|
|
group.long 0xA04++0x03
|
|
line.long 0x00 "PDU_RESP_TIMER,PDU Response Timer"
|
|
hexmask.long.word 0x00 0.--15. 1. " PDU_RESP_TIME_VAL ,Count value to monitor the time to get a response for a PDU from peer device"
|
|
rgroup.long 0xA08++0x07
|
|
line.long 0x00 "NEXT_RESP_TIMER_EXP,Next Response Timeout Instant"
|
|
hexmask.long.word 0x00 0.--15. 1. " NEXT_RESPONSE_INSTANT ,Clock instant at which the next PDU response timeout event will occur on a connection"
|
|
line.long 0x04 "NEXT_SUP_TO,Next Supervision Timeout Instant"
|
|
hexmask.long.word 0x04 0.--15. 1. " NEXT_TIMEOUT_INSTANT ,Clock instant at which the next connection supervision timeout event will occur on a connection"
|
|
group.long 0xA10++0x17
|
|
line.long 0x00 "LLH_FEATURE_CONFIG,Feature Enable"
|
|
bitfld.long 0x00 1. " SL_DSM_EN ,Enable slave latency period DSM" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " QUICK_TRANSMIT ,Quick transmit feature in slave latency enable" "Disabled,Enabled"
|
|
line.long 0x04 "WIN_MIN_STEP_SIZE,Window Minimum Step Size"
|
|
hexmask.long.byte 0x04 8.--15. 1. " WINDOW_MIN_FW ,Minimum window interval value programmed by firmware"
|
|
bitfld.long 0x04 4.--7. " STEPUP ,If packets are missed the reference window is gradually increased by step up size until it receives 2 consecutive good packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " STEPDN ,After receiving 2 consecutive good packets the reference window is gradually decremented by step down size until it reaches window minimum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SLV_WIN_ADJ,Slave Window Adjustment"
|
|
hexmask.long.word 0x08 0.--10. 1. " SLV_WIN_ADJ ,Window adjust value"
|
|
line.long 0x0C "SL_CONN_INTERVAL,Slave Latency X Conn Interval Value"
|
|
hexmask.long.word 0x0C 0.--15. 1. " SL_CONN_INTERVAL_VAL ,(Sl*ci) product for the ongoing connection"
|
|
line.long 0x10 "LE_PING_TIMER_ADDR,LE Ping Connection Timer Address"
|
|
hexmask.long.word 0x10 0.--15. 1. " CONN_PING_TIMER_ADDR ,LE Au-thenticated payload timeout (Le APTO)"
|
|
line.long 0x14 "LE_PING_TIMER_OFFSET,LE Ping Connection Timer Offset"
|
|
hexmask.long.word 0x14 0.--15. 1. " CONN_PING_TIMER_OFFSET ,Ping timer nearly expired offset in the order of 10ms"
|
|
rgroup.long 0xA28++0x07
|
|
line.long 0x00 "LE_PING_TIMER_NEXT_EXP,LE Ping Timer Next Expiry Instant"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONN_PING_TIMER_NEXT_EXP ,The value of ping timer next expiry instant in the terms of native clock value"
|
|
line.long 0x04 "LE_PING_TIMER_WRAP_COUNT,LE Ping Timer Wrap Count"
|
|
hexmask.long.word 0x04 0.--15. 1. " CONN_SEC_CURRENT_WRAP ,Holds the current position of the ping timer"
|
|
group.long 0xE00++0x07
|
|
line.long 0x00 "TX_EN_EXT_DELAY,Transmit Enable Extension Delay"
|
|
bitfld.long 0x00 0.--4. " TXEN_EXT_DELAY ,Transmit enable extension delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TX_RX_SYNTH_DELAY,Transmit/receive Enable Delay"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TX_EN_DELAY ,The delay used to assert rif_tx_en exactly tx_tramp micro-seconds ahead of the first bit of the tx_data which can be used to turn on the radio transmitter"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RX_EN_DELAY ,The delay used to assert rif_rx_en rx_tramp micro-seconds ahead of first bit of the expected rx_data which can be used to turn on the radio receiver"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BLERD (BLE Radio)"
|
|
base ad:0x402E0000
|
|
width 15.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CFG1,Generic Configure Register 1"
|
|
bitfld.long 0x00 13.--15. " LNA_GAIN ,LNA setting gain" "VLG,LG,MH,IHG,HG,VHG,?..."
|
|
bitfld.long 0x00 11.--12. " CBPF_GAIN ,CBPF setting gain" "0dB,3dB,12dB,15dB"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BURNING_CLK_EN ,Burn in function mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ADC_DC_CAPTURE_EN ,ADC DC capture enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " RADIO_STANDALONE ,Radio standalone" "Linked,Not linked"
|
|
bitfld.long 0x00 7. " TX_PA_RAMP_MODE ,Ramp to PA gain" "One short,2dB steps"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ADC_IQ_INVERSE ,Swap ADC I/Q path" "Not swapped,Swapped"
|
|
bitfld.long 0x00 5. " EN_BR_CLK ,Enable brclk output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CLKGATING_DISABLE ,Disable the clock gating logic globally" "No,Yes"
|
|
bitfld.long 0x00 3. " RF_PLL_DIRECT ,Program channel frequency as direct frequency mode" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AGC_DISABLE ,Disable the AGC" "No,Yes"
|
|
bitfld.long 0x00 1. " TX_DATA_INVERSE ,Invert modulation transmit data" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RX_DATA_INVERSE ,Invert modulation receiving data" "Not inverted,Inverted"
|
|
line.long 0x04 "CFG2,Generic Configure Register 2"
|
|
bitfld.long 0x04 15. " ADC_DFT_EN ,ADC DFT enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " DAC_DFT_EN ,DAC DFT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " DAC_DFT_MODE , DAC DFT mode definition" "dac_reg_data,12Mhz,1Mhz,4Mhz"
|
|
hexmask.long.word 0x04 0.--9. 1. " DAC_REG_DATA ,DAC input"
|
|
line.long 0x08 "MODEM,Modem Configuration"
|
|
bitfld.long 0x08 15. " CW_MODE ,Modulation continue wave output" "Input,Output"
|
|
bitfld.long 0x08 14. " ADCDFT_SEL ,ADC DFT capture data select" "Before image filter,After image filter"
|
|
textline " "
|
|
bitfld.long 0x08 13. " READ_DC_OFFSET_SEL ,Read back offset select" "Analog,Digital"
|
|
bitfld.long 0x08 12. " LOAD_PREV_GAIN_EN ,Load previous RX packet gain" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ADC_PWR_EST_EN ,Power estimation for ADC output enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " DC_SCALING_EN ,DC scalling enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " ADC_FULL_SWING_DETECT_EN ,ADC full swing detect enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " IMREJ_BYPASS ,Bypass image filter in demoulation" "No bypass,Bypass"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " DC_PARAM ,Demodulation frequency deviation selection" "320K,350K,400K,430K"
|
|
bitfld.long 0x08 5. " RESET2_EN ,Demodulation soft reset enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " RST_CNT2_SEL ,Soft reset condition selection" "32bits,16bits"
|
|
bitfld.long 0x08 2.--3. " WIDE_SPD ,Demodulation alpha value for DC offset tracking in wide speed" "8,10,12,14"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " NARROW_SPD ,Set alpha value for DC offset tracking speed in narrow mode" "1,2,3,4"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "FSM,RFCTRL State Information"
|
|
bitfld.long 0x00 14.--15. " STATE ,RFCTRL major state" "Sleep mode,RX mode,TX mode,Idle mode"
|
|
bitfld.long 0x00 11.--13. " SY_STATE ,RFCTRL SYNTH state" "SY off,SY regulator power up,SV VCO pup up,SY LO path power up,Frequency calibration,PLL setting,PLL locked,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " TX_STATE ,RFCTRL TX state" "TX off,TX regulator powerup,TX baseband powerup,KV calibration,TX PLL settling,TX ready,?..."
|
|
bitfld.long 0x00 5.--7. " RX_STATE ,RFCTRL RX state" "RX off,RX regulator powerup,RX baseband and IF powerup,DC calibration,RX wait for PLL settling,RX ADC DC value capture,RX receive ON,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " ISO_ENABLE ,Monitor isolation cell enable signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " FCAL_PASS_DETECT ,TX balun power detector" "Failed,Passed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LFLDO_OK ,LF LDO powered up" "No,Yes"
|
|
bitfld.long 0x00 1. " LSLDO_OK ,LS LDO powered up" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XO_AMP_DETECT ,XO amplitude detection" "Not reached 60%,Reached 60%"
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DBUS,RFCTRL Mode Transition Control"
|
|
bitfld.long 0x00 15. " XTAL_ENABLE ,Crystal enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISOLATE_N ,Force isolation cell enable of analog/digital boundary" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DIRECT_TXEN ,Direct TX enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DIRECT_RXEN ,Direct RX enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " RF_FREQ ,RF frequency"
|
|
line.long 0x04 "CFGCTRL,RFCTRL Running Configuration"
|
|
bitfld.long 0x04 15. " TESTMODE_EN ,Test mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " FCAL_RERUN ,FCAL force rerun" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 10. " KVCAL_RERUN ,KVCAL force rerun" "No,Yes"
|
|
bitfld.long 0x04 9. " RCCAL_MODE ,RC-cal mode" "Normal mode,Slow mode"
|
|
textline " "
|
|
bitfld.long 0x04 8. " RCCAL_RERUN ,RC-cal forced rerun" "No,Yes"
|
|
bitfld.long 0x04 7. " DCCAL_MODE ,RX DC offset calibration mode" "Normal mode,Slow mode"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DCCAL_RERUN ,DC CAL forced rerun" "No,Yes"
|
|
bitfld.long 0x04 5. " IGNORE_FRAC ,Fractional part ignore" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x04 4. " DSM_MODE[4] ,DSM mode 4" "Third order PLL,First order PLL"
|
|
bitfld.long 0x04 2.--3. " [3:2] ,DSM mode in TX" "Input dither but no initial condition for DSM,Input dither and initial condition to DSM,No input dither and initial condition,No input dither but initial condition is given"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " [1:0] ,DSM mode in RX" "Input dither but no initial condition for DSM,Input dither and initial condition to DSM,No input dither and initial condition,No input dither but initial condition is given"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "RSSI,RX Envelpe Detector And RSSI Value"
|
|
hexmask.long.byte 0x00 8.--14. 1. " POSTFILT ,RSSI value after the filter in digital"
|
|
hexmask.long.byte 0x00 0.--6. 1. " PREFILT ,RSSI value before the filter in digital"
|
|
group.long 0x24++0xC7
|
|
line.long 0x00 "RMAP,BG LDO Bypass Mode"
|
|
bitfld.long 0x00 11. " BB_BYPASS[11] ,V2ILDO power down" "Off,Power down"
|
|
bitfld.long 0x00 10. " [10] , BG LDO power down" "Off,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 9. " [9] ,LS LDO power down" "Off,Power down"
|
|
bitfld.long 0x00 8. " [8] ,LF LDO power down" "Off,Power down"
|
|
textline " "
|
|
bitfld.long 0x00 7. " [7] ,Spare bit" "0,1"
|
|
bitfld.long 0x00 6. " [6] ,Bypass BBV2LDO" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " [5] ,Bypass LS LDO" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 4. " [4] ,Bypass LF LDO" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,BG output" "0,1"
|
|
bitfld.long 0x00 2. " [2] ,Bypass xo amp detect" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " [1] ,Bypass LF LDO ok signal" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 0. " [0] ,Bypass LS LDO ok signal bit" "Not bypassed,Bypassed"
|
|
line.long 0x04 "KVCAL,KVCAL Running Configuration"
|
|
hexmask.long.byte 0x04 4.--11. 1. " EXP_FREQ_DIFF ,Expected difference in KVCAL configuration counts"
|
|
bitfld.long 0x04 2.--3. " RUN_DURATION ,Run duration" "512,376,256,128"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " DAC_STEP ,DAC step" "512,376,256,128"
|
|
line.long 0x08 "CFG_1_FCAL,FCAL Running Configure 5_6"
|
|
hexmask.long.byte 0x08 7.--13. 1. " COARSE_FRAMES_7 ,Number of frames to run for the calibration 7th coarse bit"
|
|
hexmask.long.byte 0x08 0.--6. 1. " COARSE_FRAMES_6 ,Number of frames to run for the calibration 6th coarse bit"
|
|
line.long 0x0C "CFG_2_FCAL,FCAL Running Configure 7_2"
|
|
hexmask.long.byte 0x0C 7.--13. 1. " COARSE_FRAMES_5 ,Number of frames to run for the calibration 5th coarse bit"
|
|
hexmask.long.byte 0x0C 0.--6. 1. " COARSE_FRAMES_4 ,Number of frames to run for the calibration 4th coarse bit"
|
|
line.long 0x10 "CFG_3_FCAL,FCAL Running Configure 3_4"
|
|
hexmask.long.byte 0x10 7.--13. 1. " COARSE_FRAMES_3 ,Number of frames to run for the calibration 3th coarse bit"
|
|
hexmask.long.byte 0x10 0.--6. 1. " COARSE_FRAMES_2 ,Number of frames to run for the calibration 2th coarse bit"
|
|
line.long 0x14 "CFG_4_FCAL,FCAL Running Configure 0_1"
|
|
hexmask.long.byte 0x14 7.--13. 1. " COARSE_FRAMES_1 ,Number of frames to run for the calibration 1th coarse bit"
|
|
hexmask.long.byte 0x14 0.--6. 1. " COARSE_FRAMES_0 ,Number of frames to run for the calibration 0th coarse bit"
|
|
line.long 0x18 "CFG_5_FCAL,FCAL Running Framer Fine"
|
|
bitfld.long 0x18 7.--10. " CNT_SEL ,Select which count should be reflected in the FCAL_DBG_2 and FCAL_DBG_3 registers" ",FCAL 7 coarse,FCAL 6 coarse,FCAL 5 coarse,FCAL 4 coarse,FCAL 3 coarse,FCAL 2 coarse,FCAL 1 coarse,FCAL 0 coarse,FCAL 3 fine,FCAL 2 fine,FCAL 1 fine,FCAL 0 fine,VCO open loop count,KVCAL observed count,KVCAL gain"
|
|
hexmask.long.byte 0x18 0.--6. 1. " FINE_FRAMES ,Number of frames to run for all the calibration of all the fine bits"
|
|
line.long 0x1C "CFG_6_FCAL,FCAL Running VCO OL"
|
|
bitfld.long 0x1C 13.--14. " DRIFT_CHECK ,Drift check start" "0us,100us,200us,300us"
|
|
bitfld.long 0x1C 12. " DRIFT_CHECK_EN ,Enables the FCAL drift check" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " VCO_OL_ENBL ,Vco openloop characterization enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x1C 0.--10. 1. " FRAMES_VCO_OL ,Number of frames to run in VCO openloop characterization"
|
|
line.long 0x20 "FCAL_TEST,FCAL Test Mode Configuration"
|
|
bitfld.long 0x20 14. " LOOP_POLARITY ,Inverts the polarity of the FCAL loop" "Not inverted,Inverted"
|
|
bitfld.long 0x20 13. " CNT_POLARITY ,Inverts the polarity of the FCAL counter output coming in to the RFCTRL" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x20 12. " MODE ,Force the coarse and fine bits of FCAL output enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x20 4.--11. 1. " COARSE ,Force coarse bits output of the FCAL engine when test_mode is set"
|
|
textline " "
|
|
bitfld.long 0x20 0.--3. " FINE ,Force fine bits output of the FCAL engine when test_mode is set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x24 "TEST,RCCAL And Procmon Test Configuration"
|
|
bitfld.long 0x24 14. " FRCCAL_POLARITY ,RC CAL polarity invert" "Not inverted,Inverted"
|
|
bitfld.long 0x24 13. " FRCCAL_MODE ,Force RC CAL mode" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x24 8.--12. " FRCCAL_CODE ,Force RC CAL code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x24 7. " KVCAL_MODE ,Force KV CAL mode" "Not forced,Forced"
|
|
textline " "
|
|
hexmask.long.byte 0x24 0.--6. 1. " KVCAL_GAIN ,Force KV CAL code"
|
|
line.long 0x28 "FPD_TEST,Ldos Test"
|
|
bitfld.long 0x28 13. " FPUP_ALL ,Force powerup all" "No,Yes"
|
|
bitfld.long 0x28 12. " BALUN_CTUNE ,Force powerdown balun ctune block" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x28 11. " BALUN_HFLDO ,Balun HF LDO is forced power down" "No,Yes"
|
|
bitfld.long 0x28 10. " SY_LDOFFFB ,Force power down SY LDO LOFFFB" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x28 9. " SY_LDOLOPATH ,Force power down SY LDO LOPATH" "No,Yes"
|
|
bitfld.long 0x28 8. " SY_LDOVCO ,Force power down SY LDOVCO" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x28 7. " FAST_CHARGE ,Force power the fast charge bit for LDO lopath" "No,Yes"
|
|
bitfld.long 0x28 4. " BB_RCCAL_BLOCK ,Forcefully powers down the RC CAL block" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x28 3. " BB_XO_BUF_SY ,Forcefully powers down xo buffer to synth" "No,Yes"
|
|
bitfld.long 0x28 2. " BB_XO_BUF_ADC ,Forcefully powers down xo buffer to ADC" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x28 0. " BB_FPUP_XO_BUF_ALL ,Forcefully powers down all the buffers in XO" "No,Yes"
|
|
line.long 0x2C "SY,SY Test Configuration 1"
|
|
bitfld.long 0x2C 15. " TEST_FPUP_ALL ,All the blocks in SY are forced power up" "No,Yes"
|
|
bitfld.long 0x2C 14. " TEST_FPD_LOOP_FREEZE ,Loop freeze is forced low" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x2C 13. " TEST_FPD_OPENLOOP ,The loop_freeze is forced low" "No,Yes"
|
|
bitfld.long 0x2C 12. " TEST_FPD_FCAL_AMP ,The fcal amp is forced powered down" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x2C 11. " TEST_FPD_TX_POWERSAVE ,The fcal amp is forced powered down" "No,Yes"
|
|
bitfld.long 0x2C 10. " TEST_FPD_DIV2_DRV ,The TX powersave bit is force to zero" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " TEST_FPD_LOPATHTX ,SY LOpath TX buffer is forced powered down" "No,Yes"
|
|
bitfld.long 0x2C 8. " TEST_FPD_CPLPF ,SY CP and LPF are forced powered down" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x2C 7. " TEST_FPD_FCAL ,SY FCAL counter is forced powered down" "No,Yes"
|
|
bitfld.long 0x2C 6. " TEST_FPD_DIVN ,SY DIVN block is forced powered down" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x2C 5. " TEST_FPD_DIV2_BUF ,SY LOpath FCAL buffer is forced powered down" "No,Yes"
|
|
bitfld.long 0x2C 4. " TEST_FPD_LOPATHDIVN ,SY LOpath DIVN buffer is forced powered down" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x2C 2. " TEST_FPD_DIV2 ,SY high speed divider block is forced powered down" "No,Yes"
|
|
bitfld.long 0x2C 1. " TEST_FPD_VCO ,SY VCO block is forced powered down" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x2C 0. " TEST_FPD_IBIAS ,SY IBIAS block is forced powered down" "No,Yes"
|
|
line.long 0x30 "TEST2_SY,SY Test Configuration 2"
|
|
hexmask.long.byte 0x30 8.--15. 1. " DSM_FRAC ,Force bits for DSM fractional bits"
|
|
bitfld.long 0x30 7. " FORCE_DSM_FRAC ,Force the MSB 8bit of the DSM fractional part with Reg[15-8]" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x30 6. " FORCE_DSM_RUN ,DSM_run signal assert" "Not asserted,Asserted"
|
|
bitfld.long 0x30 5. " FPD_DSM_RUN ,DSM run signal de-assert" "Not de-asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x30 0.--3. " ICP_CODE ,ICP code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x34 "TX,Transmit Test Configuration"
|
|
bitfld.long 0x34 8. " TEST_FPUP_TX_ALL ,Force powerup all the TX blocks" "No,Yes"
|
|
bitfld.long 0x34 7. " TEST_FPD_KVM_PFDEV ,Modulator enable positive 1mhz frequency deviation mode" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x34 6. " TEST_FPD_KVM_NFDEV ,Modulator enable negative 1mhz frequency deviation mode" "Enabled,Disabled"
|
|
bitfld.long 0x34 5. " TEST_FPD_FN_TXEN ,The modulator control signal f_n_txen deasswert" "Not deasswerted,Deasswerted"
|
|
textline " "
|
|
bitfld.long 0x34 4. " TEST_FPD_PREDRIVER ,Forced power down TX pre-drive" "No,Yes"
|
|
bitfld.long 0x34 3. " TEST_FPD_DRIVER ,Forced power down TX driver" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x34 2. " TEST_FPD_LPF ,Forced power down TX LPF" "No,Yes"
|
|
bitfld.long 0x34 1. " TEST_FPD_DAC ,Forced power down TX DAC" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x34 0. " TEST_FPD_IBIAS ,Forced power down TX ibias" "No,Yes"
|
|
line.long 0x38 "RX,RX Test Configuration"
|
|
bitfld.long 0x38 12. " TEST_FPUP_RX_ALL ,Force powerup all RX blocks" "No,Yes"
|
|
bitfld.long 0x38 11. " TEST_FPD_FN_RXEN ,The demodulator control signal f_n_rxen deassert" "Not deasserted,Deasserted"
|
|
textline " "
|
|
bitfld.long 0x38 10. " TEST_FPD_LNA_HIZ ,LNA HIZ signal deassert" "Not deasserted,Deasserted"
|
|
bitfld.long 0x38 9. " TEST_FPD_LNA ,Force power down RX LNA" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x38 8. " TEST_FPD_MIXER_RF ,Force power down RX MIXER RF block" "No,Yes"
|
|
bitfld.long 0x38 7. " TEST_FPD_MIXER_LO ,Force power down RX MIXER LO block" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x38 6. " TEST_FPD_TIA ,Force power down RX TIA" "No,Yes"
|
|
bitfld.long 0x38 5. " TEST_FPD_BPF ,Force power down RX BPF" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x38 4. " TEST_FPD_ADC_QREFGEN ,Force power down RX ADC QREF generation lock" "No,Yes"
|
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bitfld.long 0x38 3. " TEST_FPD_ADC_QCORE ,Force power down RX ADC Q core block" "No,Yes"
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textline " "
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bitfld.long 0x38 2. " TEST_FPD_ADC_IREFGEN ,Force power donw RX ADC IREF generation lock" "No,Yes"
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bitfld.long 0x38 1. " TEST_FPD_ADC_ICORE ,Force power down RX ADC I core block" "No,Yes"
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textline " "
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bitfld.long 0x38 0. " TEST_FPD_IBIAS ,Force power down RX IBIAS block" "No,Yes"
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line.long 0x3C "DIAG1,RF Diagnostics Configuration 1"
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bitfld.long 0x3C 5.--9. " SEL ,Sel" "HFLDO,Balun,BB_TRANCHAR,BB_LSLDO,BB_V2ILDO,BB_V2I,BB BGAP,BB LFLDO,BB RCCAL,BB refcore,BB XO,RX IBIAS,RX ADC,RX CBPF2,RX CBPF1,RX TIA,RX mixer,RX LNA,TX IBIAS,TX DAC,TX LPF,,TX driver,SY LDO lopath,,SY LDO FFFB,SY IBIAS,SY LO path,,SY_DIVN_FCAL,SY_PDCPLPF,Injection_monitor"
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bitfld.long 0x3C 1.--4. " CODE ,Global diagnositic code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x3C 0. " DISABLE ,Diagnositcs fro all blocks disable" "No,Yes"
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line.long 0x40 "IM,Inject Monitor Configuration"
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bitfld.long 0x40 13.--14. " DIAG_BUMP[3:2] ,Diag bump code 32" "0.9V,1.0V,1.1V,0.8V"
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bitfld.long 0x40 11.--12. " [1:0] ,Diag bump code 10" "0.9V,1.0V,1.1V,0.8V"
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textline " "
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bitfld.long 0x40 10. " DIAG_LOOPBACK ,Monitor various outputs in the chip and inject to on-chip ADC" "No monitor,Monitor"
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bitfld.long 0x40 6.--9. " DIAG_INJ_CODE ,Injection code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x40 5. " DIAG_INJ_DISABLE ,Globally disable the injection" "No,Yes"
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bitfld.long 0x40 1.--4. " DIAG_MONI_CODE ,Monitor code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x40 0. " DIAG_MON_DISABLE ,Globally disable the monitor" "Enabled,Disabled"
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line.long 0x44 "LDO_BYPASS,Ldos Bypass Configuration"
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bitfld.long 0x44 3. " HFLDO ,BB SY HF LDO bypass" "Not bypassed,Bypassed"
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bitfld.long 0x44 2. " SYLDOFFFB ,Synth LDO_FFFB bypass" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x44 1. " SYLDOLOPATH ,Synth LDO_LOPATH bypass" "Not bypassed,Bypassed"
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bitfld.long 0x44 0. " SYLDOVCO ,Synth LDO_VCO bypass" "Not bypassed,Bypassed"
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line.long 0x48 "LDO,Bump Bits For Ldos Atlantis"
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bitfld.long 0x48 9.--11. " BUMP_SY_FFFB ,FF and FB LDO output" "1.800V,1.846V,1.894V,1.946V,2.000V,1.649V,1.701V,1.756V"
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bitfld.long 0x48 7.--8. " BUMP_SY_LHV ,HV LDO output" "1.894V,2.000V,1.800V,1.846V"
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textline " "
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bitfld.long 0x48 5.--6. " BUMP_SY_LOPATH ,LOPATH LDO output" "1.762V,1.861V,1.673V,1.716V"
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bitfld.long 0x48 3.--4. " BUMP_SY_VCO ,VCO LDO output" "1.413V,1.494V,1.329V,1.371V"
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textline " "
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bitfld.long 0x48 0.--2. " BUMP_BALUM_HF ,HF LDO output" "1.800V,1.846V,1.894V,1.946V,?..."
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line.long 0x4C "BB_BUMP1,Bump Bits For Ldos BB"
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bitfld.long 0x4C 15. " FPD_REFORCE ,Force power down for refcore" "No,Yes"
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bitfld.long 0x4C 14. " FORCE_BGSTARTUP ,Force BG start up" "No,Yes"
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textline " "
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bitfld.long 0x4C 8.--10. " LSLDO ,LS LDO output" "1.708V,1.747V,1.802V,1.849V,1.904V,1.552V,1.591V,1.650V"
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bitfld.long 0x4C 5.--7. " LFLDO ,XO LDO/BB LDO output" "1.894V/1.800V,1.946V/1.846V,2.000V/1.894V,2.000V/1.946V,1.701V/1.649V,1.756V/1.649V,1.800V/1.701V,1.846V/1.756V"
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textline " "
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bitfld.long 0x4C 4. " V2I_REG[4] ,Error amp quiescent bit 4" "5u,10u"
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bitfld.long 0x4C 2.--3. " [2:3] ,Error amp quiescent bits 23" "1.8V,1.85V,1.9V,1.75V"
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textline " "
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bitfld.long 0x4C 0.--1. " REFCORE_VDD ,Bumps the ibias current of refcore" "10u,9.1u,11.1u,12.5u"
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line.long 0x50 "BB_BUMP2,BB Bump Configuration"
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bitfld.long 0x50 15. " SY_IBIAS[3] ,SY_IBIAS current bump" "BG,RCAL"
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bitfld.long 0x50 13.--14. " [12] ,Reperesent current bump" "0%,+12.5%,-25%,-12.5%"
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textline " "
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bitfld.long 0x50 10.--12. " VBG_TRIM ,Trims the bandgap voltage" "0%,1.6%,3.2%,4.8%,6.4%,-4.8%,-3.2%,-1.6%"
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bitfld.long 0x50 9. " V2I[9] ,Error amp quiescent current" "5u,10u"
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textline " "
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bitfld.long 0x50 5.--8. " [5:8] ,Trims the BGR current" "0%,-2.5%,-5%,-7.5%,-10%,-12.5%,-15%,-17.5%,20%,17.5%,15%,12.5%,10%,7.5%,5%,2.5%"
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bitfld.long 0x50 4. " V21_RCAL[4] ,Error amp quiescent current" "5u,10u"
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textline " "
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bitfld.long 0x50 0.--3. " [0:3] ,Trims the RCAL current" "0%,-2.5%,-5%,-7.5%,-10%,?..."
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line.long 0x54 "BB_XO,BB Bump Configuration 1"
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bitfld.long 0x54 13.--14. " CTRL_RPREF ,Controls the reference voltage fed as input to the regulators which generate vdd_xo and vdd_xb" "1.289V,1.227V,1.164V,1.382V"
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bitfld.long 0x54 10.--12. " CTRL_VDDL_XB ,Controls the value of supply filter resistance in the inverter chain" "1.028k,1.172k,1.367k,1.540k,1.889k,2.055k,0.503k,0.747k"
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textline " "
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bitfld.long 0x54 7.--9. " CTRL_VDDL_XO ,Controls the value of supply filter resistance in the xo core" "0.769k,0.877k,1.023k,1.152k,1.413k,1.537k,0.376k,0.559k"
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bitfld.long 0x54 5.--6. " CTRL_RC_FASTSTART_RES ,Controls the time constant with which the surge current from rc_faststart block decays down to zero" "387us,309us,232us,464us"
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textline " "
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bitfld.long 0x54 4. " EN_AMPDET_FASTSTART ,This bit is used to force startup of the vtnbyr circuit in the biasgen_and_reg block of the XO" "Normal startup,Forced startup"
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bitfld.long 0x54 3. " EN_AMPDET_CURMEAS ,This bit can be used to disable all the caps on both X1 node and X2 node" "Enabled,Disabled"
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textline " "
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bitfld.long 0x54 2. " EN_CURMEAS ,This bit is used to force startup of the positive feedback loop in the amplitude detect block of the XO" "Normal startup,Forced startup"
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bitfld.long 0x54 1. " EN_RE_FASTSTART ,Enables/disables the RC faststart block in the XO" "Disabled,Enabled"
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textline " "
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bitfld.long 0x54 0. " DIS_XOCORE_SUPFILT ,Enables/disables the supply filter of the XO core" "No,Yes"
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line.long 0x58 "BB_XO_CAPTRIM,BB Bump Configuration 2"
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hexmask.long.byte 0x58 8.--15. 1. " X1 ,Control cap on X1 node"
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hexmask.long.byte 0x58 0.--7. 1. " X2 ,Control cap on X2 node"
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line.long 0x5C "SY_BUMP1,SY Bump Bits Configuration 1"
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bitfld.long 0x5C 12.--15. " PDCPLPF ,Bump for PD CP and LPF blocks" "-20%,-15%,-10%,-5%,0%,5%,10%,15%,?..."
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bitfld.long 0x5C 8.--11. " LOPATH ,Bump bits for LO path bulk bias" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x5C 7. " LDOLO_FORCE_STARTUP ,Force start-up of the VT/R circuit in VCOLOPATH LCO" "No force start-up,Force start-up"
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bitfld.long 0x5C 5.--6. " IBIAS_LOPATH ,Bump bits for clkbias in lopath" "0m,100m,200m,400m"
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textline " "
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bitfld.long 0x5C 4. " LOFB_POWERSAVE ,Enable powersave for LOFB buffer" "Disabled,Enabled"
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bitfld.long 0x5C 2.--3. " VCO[2:3] ,Bump bits for SY VCO block 2-3" "50 Ohms,30 Ohms,22 Ohms,16 Ohms"
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textline " "
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bitfld.long 0x5C 0.--1. " [0:1] ,Bump bits for SY VCO block 0-1" "58 Ohms,39 Ohms,22 Ohms,16 Ohms"
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line.long 0x60 "SY_BUMP2,SY Bump Bits Configuration 2"
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bitfld.long 0x60 14.--15. " PDCP_OFFSET ,Bump for the bias voltage of the 8x node" "925mV,925mV+108mV,925mV-158mV,925mV-080mV"
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bitfld.long 0x60 12.--13. " RST_DLY ,Bumping the reset delay" "500ps,424ps,350ps,300ps"
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textline " "
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bitfld.long 0x60 11. " VMOD_PULLDN ,Pull down control for the modulating port" "No pull down,Pull down"
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bitfld.long 0x60 10. " VCTRL_PULLDN ,Test mode to pull down for noise simulation" "Normal mode,Test mode"
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textline " "
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bitfld.long 0x60 9. " PUP_MON ,Test mode to monitor buffered 1x output on the injmon buffer" "Normal mode,Test mode"
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bitfld.long 0x60 8. " CLKNC_MODE ,Control the nc_clock_mux" "Given from DIVN once openloop is made low,Always connected to crystal clock"
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textline " "
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bitfld.long 0x60 6.--7. " ICP_OFFSET ,Bump bits to set the offset pulse width in RX mode" "2.45n,1.75ns,1.3ns,25ps"
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bitfld.long 0x60 4.--5. " ICP_XFACTOR ,Enable power save for SY FB buffers in TXPOWERSAVE mode" "0,1,2,3"
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textline " "
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bitfld.long 0x60 2.--3. " ACAP_BIAS_SEL ,ACAP bias voltage is selected based on these bits" "630mV,700mV,560mV,595mV"
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bitfld.long 0x60 0.--1. " FCAL_BIAS_SEL ,VCTRL bias voltage is selected based on these bits" "Vddvco/2,Vddvco/2 + 5.6%,Vddvco/2 - 2.8%,Vddvco/2 - 5.6%"
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line.long 0x64 "TX_BUMP1,Transmit Bump Configuration 1"
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bitfld.long 0x64 14.--15. " SY_DIVN_TXPOWERSAVE ,Divn power save bits" "ALL,ALL-D2,ALL-D2-D1,ALL-D2-D1-Buf"
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bitfld.long 0x64 10.--13. " TX_VTXREF_PROG ,TX modulation port varactor vtxref bias voltage bump settings" "100mV,150mV,200mV,250mV,300mV,350mV,400mV,450mV,500mV,550mV,600mV,?..."
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textline " "
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bitfld.long 0x64 8.--9. " TX_LPF[3:2] ,Bump bits for TX LPF op-amp reference voltage" "400mV,450mV,300mV,350mV"
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bitfld.long 0x64 6.--7. " [1:0] ,Bump bits for TX LPF op-amp bias current" "400mV,450mV,300mV,350mV"
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textline " "
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bitfld.long 0x64 4.--5. " SY_RST_DLY_TX ,Bumping the reset delay" "500ps,424ps,350ps,300ps"
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bitfld.long 0x64 0.--3. " TX_DRIVER ,Driver bias current selection bump bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x68 "TX_BUMP2,Transmit Bump Configuration 2"
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bitfld.long 0x68 14.--15. " SY_CP_TXPOWERSAVE ,Charge pump power save bits" "ALL,ALL-8x CP,ALL-8x-1x CP,All-buffer"
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bitfld.long 0x68 10.--13. " DAC_RES ,TX DAC load resistor bump settings" "-20%,-17.5%,-15%,-12.5%,-10%,-7.5%,-5%,-2.5%,0%,2.5%,5%,7.5%,10%,12.5%,15%,17.5%"
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textline " "
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bitfld.long 0x68 8.--9. " SY_ICP_OFFSET_TX ,Bump bits to set the offset pulse width in TX mode" "2.45ns,1.75ns,1.3ns,25ps"
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bitfld.long 0x68 6.--7. " SY_LDOBGREF_EN ,Enables a bandgap" "None,VCO ldo,LOPATH ldo,VCO+LOPATH ldo"
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textline " "
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bitfld.long 0x68 4.--5. " DRV_VCASCH ,Programs the driver cascode gate bias voltage" "0.3V,0.2V,0.1V,?..."
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bitfld.long 0x68 0.--3. " DRV_AB_VBIAS ,Bias voltage for the class-AB driver" "571.224mV,604.508mV,626.357mV,641.856mV,656.04mV,667.096mV,678.775mV,688.005mV,698.817mv,707.272mV,718.103mV,726.411mV,737.995mV,746.708mV,759.919mV,769.735mV"
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line.long 0x6C "RX_BUMP1,Receiver Bump Configuration 1"
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bitfld.long 0x6C 15. " RX_BUMP1_LNA3 ,Enables the HG and LG LNA section's cascode biases" "Disabled,Enabled"
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bitfld.long 0x6C 14. " RX_BUMP1_LNA2 ,Forces pull down of inputs of LNA" "No force pull down,Force pull down"
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textline " "
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bitfld.long 0x6C 13. " RX_BUMP1_LNA1 ,Boost the LNA bias current ot HP equivalent" "Not boosted,Boosted"
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bitfld.long 0x6C 12. " RX_BUMP1_LNA0 ,Forces the TIA" "Not forced,Forced"
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textline " "
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bitfld.long 0x6C 10.--11. " MIXER ,Bump bits to control LNA gate bias voltage in RX mode" "0.5V,0.4V,0.3V,0.2V"
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bitfld.long 0x6C 8.--9. " MIXER_VBIAS_SW ,Bump bits for mixer VBIAS switch" "0.38V,0.3V,0.255V,0.17V"
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textline " "
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bitfld.long 0x6C 6.--7. " IF_OFFSET_CALDAC ,Bit setting offset DAC LSB" "132.4nA,150.8nA,118.0nA,106.5nA"
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bitfld.long 0x6C 3.--5. " CBPF ,CBPF CM ref voltage" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x6C 0.--2. " TIA ,TIA CM ref voltage" "0,1,2,3,4,5,6,7"
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line.long 0x70 "RX_BUMP2,Receiver Bump Configuration 2"
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bitfld.long 0x70 13. " SY_LOWKVMMODE ,Enables a lower Kv/2 mode" "Disabled,Enabled"
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bitfld.long 0x70 12. " SY_LOWKVAMODE ,Enables a lower Kv/2 mode" "Disabled,Enabled"
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textline " "
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bitfld.long 0x70 11. " SY_HILINEARITYR2_MODE ,Switches the RX mode between settings used in TX vs a higher linearity setting" "TX,Alternative RX"
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bitfld.long 0x70 10. " SY_R2HIGHMODE ,Enables a higher R2 mode for loop stabilization with low kv and debug mode" "40 kohms,60 kohms"
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textline " "
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bitfld.long 0x70 9. " COMPLEX_DISABLE ,Setting this bit to disables the complex operation" "Enabled,Disabled"
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bitfld.long 0x70 8. " CBPF_HIZ_ENABLE ,Configures the CBPF output as hi-Z enabling independent ADC testing with the injection system" "Disabled,Enabled"
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textline " "
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bitfld.long 0x70 6.--7. " IF_CM_IBIAS ,Bump bits for common mode setting currents of the TIA and the CBPF amplifiers" "+0%,+15%,-20%,-15%"
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bitfld.long 0x70 4.--5. " CBPF_IBIAS ,Bump bits for BGR bias currents of offset calibration DAC" "+0%,+15%,-20%,-15%"
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textline " "
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bitfld.long 0x70 2.--3. " TIA_IBIAS ,Bump bits for RCAL bias currents of the TIA and the CBPF amplifiers" "+0%,+15%,-20%,-15%"
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bitfld.long 0x70 0.--1. " LNA_IBIAS ,Bump bits for PTAT bias currents of LNA" "+0%,+15%,-25%,-50%"
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line.long 0x74 "ADC_BUMP1,ADC1 Bump Configuration"
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bitfld.long 0x74 14.--15. " BWCTRL ,Reference generators bandwidth boost" "0A,20A,40A,60A"
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bitfld.long 0x74 13. " OPAMP_BYPASS ,Bypass op-amp and diode connect reference generators servo loop" "Not bypassed,Bypassed"
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textline " "
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bitfld.long 0x74 12. " LOWPOWER ,Current reduction mode in the reference generator" "No bump,50% bump"
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bitfld.long 0x74 11. " LOOPDLY4X_EN ,Loop delay increment by 4x in SAR return path" "Disabled,Enabled"
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textline " "
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bitfld.long 0x74 9.--10. " LOOPDLY ,Loop delay control in SAR return path" "Min delay,,,Max delay"
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bitfld.long 0x74 6.--8. " IBG_CAL ,Bump bits for the preamps bias current" "0A,12.5A,5A,7.5A,?..."
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textline " "
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bitfld.long 0x74 3.--5. " Q_REF ,Bump bits for the channel-Q reference voltage" "650mV,,,680mV,610mV,?..."
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bitfld.long 0x74 0.--2. " I_REF ,Bump bits for the channel-I reference voltage" "650mV,,,680mV,610mV,?..."
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line.long 0x78 "ADC_BUMP2,ADC 2 Bump Configuration"
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bitfld.long 0x78 13. " PREAMP_BWCTRL1 ,Bandwidth bump bits for the preamp 1" "Not connected,Connected"
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bitfld.long 0x78 12. " PREAMP_BWCTRL2 ,Bandwidth bump bits for the preamp 2" "Not connected,Connected"
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textline " "
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bitfld.long 0x78 11. " IQSWAP ,Swaps the I and Q channel Vbg/R for ref.gen" "Not swapped,Swapped"
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bitfld.long 0x78 8.--10. " RETURN_SKEW ,Delaying the sampling clock from the comparator wrt to the data" "Min delay,,,,,,,Max delay"
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textline " "
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bitfld.long 0x78 7. " SHORT_INPUT ,Put the ADC in idle channel mode" "Normal mode,Idle mode"
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bitfld.long 0x78 6. " PREAMP_GAINCTRL_N ,Enable preamps low/high gain modes over conversion cycle" "Disabled,Enabled"
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textline " "
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bitfld.long 0x78 5. " PREAMP_SOURCECTRL_N ,Disconnect source coupled node of the preamp during track phase" "Disabled,Enabled"
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bitfld.long 0x78 4. " IBUMP ,CBPF gains only at lowest gain setting" "Enabled,Disabled"
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textline " "
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bitfld.long 0x78 3. " METADET_EN ,Enable meta detection" "Disabled,Enabled"
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bitfld.long 0x78 2. " DUTCYCLE_25 ,Clock duty cycle control" "50/50,25/75"
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textline " "
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bitfld.long 0x78 1. " CYCLE_B5_DELAY ,Enable redundant conversion cycle at b5 position" "Disabled,Enabled"
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bitfld.long 0x78 0. " CYCLE_B2_DELAY ,Enable redundant conversion cycle at b2 position" "Disabled,Enabled"
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line.long 0x7C "BALUN,BALUN Bump Configuration"
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bitfld.long 0x7C 4.--7. " BUMP_TX_CTUNE ,Programmable bits to change tuning capacitance in the balun primary side in TX operation" "42.5,48.8,55.1,61.4,67.7,74,80.3,86.6,92.9,99.2,105.5,111.8,118.1,124.4,130.7,137"
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bitfld.long 0x7C 0.--3. " BUMP_RX_CTUNE ,Programmable bits to change tuning capacitance in the balun primary side in RX operation" "42.5,48.8,55.1,61.4,67.7,74,80.3,86.6,92.9,99.2,105.5,111.8,118.1,124.4,130.7,137"
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line.long 0x80 "CTR1,RFCTRL Control Timing 1"
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bitfld.long 0x80 14.--15. " AGC_RST_DLY ,AGC reset delay" "0.25us,1.25us,2.25us,3.25us"
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bitfld.long 0x80 13. " RX_ENV_FREEZE_EN ,Demodulation soft reset to frequency tracking enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x80 12. " RX_DC_FREEZE_EN ,Demodulation soft reset to DC cancellation enable" "Disabled,Enabled"
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bitfld.long 0x80 10.--11. " DBG_SELECT ,DBG select" "Soft reset,AGC FSM MSB,Gain decrease/increase,ADC full swing detection"
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textline " "
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bitfld.long 0x80 9. " ADC_FULL_SWING_MONI_EN ,ADC full swing monitor enable" "Disabled,Enabled"
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bitfld.long 0x80 8. " TX_DF2_SEL ,DF2 max frequency deviation" "224KHz,242KHz"
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textline " "
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bitfld.long 0x80 6.--7. " TX_MODSTART_TIME ,Controls the time between the PUP_TX_DRIVER going high and when f_n_txen is asserted" "0us,1us,2us,3us"
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bitfld.long 0x80 5. " TX_PREDRV_TIME ,PA predrive pup time" "After LDO,After KVCAL"
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textline " "
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bitfld.long 0x80 3.--4. " TX_FREEZE_TIME ,Tx freeze time" "30us,40us,50us,25us"
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bitfld.long 0x80 1.--2. " PLL_SETTLING_TIME ,PLL setting time" "25us,30us,40us,50us"
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textline " "
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bitfld.long 0x80 0. " VCO_WARMUP_TIME ,Vco warm up time" "5us,10us"
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line.long 0x84 "AGC,AGC Timing Conifguration"
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bitfld.long 0x84 13.--15. " START_WAIT_TIM ,Start AGC waiting time when RFCTRL set AGC enable" "0us,1us,2us,3us,4us,5us,6us,7us"
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bitfld.long 0x84 8.--12. " GAIN_STABLE_TIM ,Gain stable time after gain assignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x84 6.--7. " PWR_MEAS_TIM ,AGC power measurement time" "0.25us,0.5us,0.75us,1us"
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bitfld.long 0x84 4.--5. " GAIN_SAT_THRES ,ADC saturated detection threshold for doing a fast transition" "0dBm,1dBm,2dBm,3dBm"
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textline " "
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bitfld.long 0x84 3. " GAIN_MAPPING_MODE ,Atlantis TC rev gain mapping" "Disabled,Enabled"
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bitfld.long 0x84 2. " SAT_CHK_TIM ,ADC saturated detection timing" "3 12MHz clock,3 12MHz clock"
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textline " "
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bitfld.long 0x84 1. " CHECK_SAT_EN ,Quick check saturated ADC enable" "Disabled,Enabled"
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bitfld.long 0x84 0. " RST_EN ,AGC soft reset enable" "Disabled,Enabled"
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line.long 0x88 "THRSHD1,AGC Step Threshold 1"
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bitfld.long 0x88 8.--13. " AGC66_60 ,Threshold gain change from 60dB to 48dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x88 0.--5. " AGC60_66 ,Threshold gain change from 66dB to 60dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x8C "THRSHD2,AGC Step Threshold 2"
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bitfld.long 0x8C 8.--13. " AGC60_48 ,Threshold gain change from 48dB to 60dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x8C 0.--5. " AGC48_60 ,Threshold gain change from 60dB to 48dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x90 "THRSHD3,AGC Step Threshold 3"
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bitfld.long 0x90 8.--13. " AGC48_36 ,Threshold gain change from 36dB to 48dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x90 0.--5. " AGC36_48 ,Threshold gain change from 48dB to 36dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x94 "THRSHD4,AGC Step Threshold 4"
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bitfld.long 0x94 8.--13. " AGC36_18 ,Threshold gain change from 18dB to 36dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x94 0.--5. " AGC18_66 ,Threshold gain change from 36dB to 18dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x98 "THRSHD5,AGC Step Threshold 5"
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bitfld.long 0x98 8.--13. " AGC18_0 ,Threshold gain change from 0dB to 18dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x98 0.--5. " AGC0_18 ,Threshold gain change from 18dB to 0dB" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x9C "DC,ADC I/Q DC Compensate Value"
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hexmask.long.byte 0x9C 8.--15. 1. " COMP_I_CODE ,This code is removed from the ADC Q output"
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hexmask.long.byte 0x9C 0.--7. 1. " COMP_Q_CODE ,This code is removed from the ADC I output"
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line.long 0xA0 "IQMIS,IQ Mismatch Correction Value"
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hexmask.long.byte 0xA0 8.--15. 1. " IQCOMP_IVAL ,Q-component of the IQ mismatch correction"
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hexmask.long.byte 0xA0 0.--7. 1. " IQCOMP_QVAL ,I-component of the IQ mismatch correction"
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line.long 0xA4 "DCCAL,DC CAL And Setting"
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bitfld.long 0xA4 14. " TEST_I_POLARITY ,Inverts the polarity of DCCAL I code" "Not inverted,Inverted"
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bitfld.long 0xA4 13. " TEST_Q_POLARITY ,Inverts the polarity of DCCAL Q code" "Not inverted,Inverted"
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textline " "
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bitfld.long 0xA4 12. " TEST_MODE ,Enable the DCCAL test mode" "Disabled,Enabled"
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bitfld.long 0xA4 6.--11. " TEST_QBITS ,This value is driven to DCCAL qcode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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textline " "
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bitfld.long 0xA4 0.--5. " TEST_IBITS ,This value is driven to DCCAL icode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0xA8 "RCCAL,TX LPF And TIA/CBPF RC Code"
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bitfld.long 0xA8 14.--15. " AGC_GAIN_INC_TIMES_THRES ,AGC gain increase requirement wait times" "1st,2nd,3rd,4th"
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bitfld.long 0xA8 13. " SOFTRST_EN_TODIFF ,Soft reset is enabled to diffdet block" "Disabled,Enabled"
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textline " "
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bitfld.long 0xA8 12. " SOFTRST_EN_TOSTR ,Soft reset is enabled to STR block" "Disabled,Enabled"
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bitfld.long 0xA8 11. " SOFTRST_POWER_DIFF ,Soft reset power change detection" "6dB,12dB"
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textline " "
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bitfld.long 0xA8 5.--9. " CODE_TX ,Force RC code for TX LPF under test mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0xA8 0.--4. " CODE_RX ,Force RC code for TIA/CBPF under test mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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line.long 0xAC "DSM1,DSM Freeze Code 1"
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bitfld.long 0xAC 12.--15. " INDX_CODE0 ,Index at which DSM code should be freezed when fection value is 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0xAC 8.--11. " INDX_CODE1 ,Index at which DSM code should be freezed when fection value is 1/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0xAC 4.--7. " INDX_CODE2 ,Index at which DSM code should be freezed when fection value is 2/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0xAC 0.--3. " INDX_CODE3 ,Index at which DSM code should be freezed when fection value is 3/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0xB0 "DSM2,DSM Freeze Code 2"
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bitfld.long 0xB0 12.--15. " INDX_CODE4 ,Index at which DSM code should be freezed when fection value is 4/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0xB0 8.--11. " INDX_CODE5 ,Index at which DSM code should be freezed when fection value is 5/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0xB0 4.--7. " INDX_CODE6 ,Index at which DSM code should be freezed when fection value is 6/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0xB0 0.--3. " INDX_CODE7 ,Index at which DSM code should be freezed when fection value is 7/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0xB4 "DSM3,DSM Freeze Code 3"
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bitfld.long 0xB4 12.--15. " INDX_CODE8 ,Index at which DSM code should be freezed when fection value is 8/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0xB4 8.--11. " INDX_CODE9 ,Index at which DSM code should be freezed when fection value is 9/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0xB4 4.--7. " INDX_CODE10 ,Index at which DSM code should be freezed when fection value is 10/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0xB4 0.--3. " INDX_CODE11 ,Index at which DSM code should be freezed when fection value is 11/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0xB8 "DSM4,DSM Freeze Code 4"
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bitfld.long 0xB8 12.--15. " INDX_CODE12 ,Index at which DSM code should be freezed when fection value is 12/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0xB8 8.--11. " INDX_CODE13 ,Index at which DSM code should be freezed when fection value is 13/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0xB8 4.--7. " INDX_CODE14 ,Index at which DSM code should be freezed when fection value is 14/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0xB8 0.--3. " INDX_CODE15 ,Index at which DSM code should be freezed when fection value is 15/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0xBC "DSM5,DSM Freeze Code 5"
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bitfld.long 0xBC 12.--15. " INDX_CODE16 ,Index at which DSM code should be freezed when fection value is 16/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0xBC 8.--11. " INDX_CODE17 ,Index at which DSM code should be freezed when fection value is 17/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0xBC 4.--7. " INDX_CODE18 ,Index at which DSM code should be freezed when fection value is 18/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0xBC 0.--3. " INDX_CODE19 ,Index at which DSM code should be freezed when fection value is 19/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0xC0 "DSM6,DSM Freeze Code 2"
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bitfld.long 0xC0 12.--15. " INDX_CODE20 ,Index at which DSM code should be freezed when fection value is 20/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0xC0 8.--11. " INDX_CODE21 ,Index at which DSM code should be freezed when fection value is 21/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0xC0 4.--7. " INDX_CODE22 ,Index at which DSM code should be freezed when fection value is 22/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0xC0 0.--3. " INDX_CODE23 ,Index at which DSM code should be freezed when fection value is 23/24" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0xC4 "MONI,Agc Gain And Pup Signal Monitor"
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bitfld.long 0xC4 13.--15. " LNA_CODE ,Lna gain code read back" "0,1,2,3,4,5,6,7"
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bitfld.long 0xC4 11.--12. " CBPF_CODE ,Cbpf gain code read back" "0,1,2,3"
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textline " "
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hexmask.long.word 0xC4 0.--10. 1. " PUP_SIG ,Block pup up signals monitor"
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rgroup.long 0xEC++0x0F
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line.long 0x00 "DBG_BB,RX Offcal And RC Cal Code"
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hexmask.long.byte 0x00 8.--15. 1. " RX_OFFSET_I_CODE ,RX offset I code"
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hexmask.long.byte 0x00 0.--7. 1. " RX_OFFSET_Q_CODE ,RX offset Q code"
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line.long 0x04 "DBG_1,FCAL Coarse"
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bitfld.long 0x04 14. " DCCAL_DONE ,Indicates RX DC calibration is done for current packet" "Not done,Done"
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bitfld.long 0x04 13. " KVCAL_DONE ,Indicates TX KV calibration is done for current packet" "Not done,Done"
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textline " "
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bitfld.long 0x04 12. " FCAL_DONE ,Indicates when frequency calibration is done" "Not done,Done"
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hexmask.long.byte 0x04 4.--11. 1. " FCAL_COARSE_CODE ,The FCAL coars code is reflected in this field"
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textline " "
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bitfld.long 0x04 0.--3. " FCAL_FINE_CODE ,The FCAL fine code is reflected in this field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "DBG_2,FCAL Countere Value"
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hexmask.long.word 0x08 0.--15. 1. " FCAL_CNT_LSB ,The 16 LSB bits of the corresponding debug counter"
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line.long 0x0C "DBG_3,VCO OL Count Read Out"
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bitfld.long 0x0C 15. " RD_RCCAL_DONE ,RCCAL done indicator" "Not done,Done"
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bitfld.long 0x0C 10.--14. " RD_RCCAL_CODE ,RCCAL code read out through register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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textline " "
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bitfld.long 0x0C 0.--3. " FCAL_CNT_MSB ,The 4 MSB bits of the corresponding debug counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup.long 0x100++0x03
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line.long 0x00 "READ_IQ_0,I Path ADC Data 0"
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rgroup.long 0x104++0x03
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line.long 0x00 "READ_IQ_1,I Path ADC Data 1"
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rgroup.long 0x108++0x03
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line.long 0x00 "READ_IQ_2,I Path ADC Data 2"
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rgroup.long 0x10C++0x03
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line.long 0x00 "READ_IQ_3,I Path ADC Data 3"
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width 0x0B
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tree.end
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tree "BLESS (BLE Sub System)"
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base ad:0x402EF000
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width 21.
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group.long 0x00++0x03
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line.long 0x00 "WCO_CONFIG,WCO Configuration Register"
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bitfld.long 0x00 31. " ENABLE ,Master enable for WCO oscillator" "Disabled,Enabled"
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hexmask.long.byte 0x00 16.--23. 1. " ENBUS ,Test mode control bits"
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textline " "
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bitfld.long 0x00 2. " EXT_INPUT_EN ,Disables the load resistor and allows external clock input for pad_xin" "Disabled,Enabled"
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bitfld.long 0x00 0. " LPM_EN ,Force block into low power mode" "Not forced,Forced"
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rgroup.long 0x04++0x03
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line.long 0x00 "WCO_STATUS,WCO Status Register"
|
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bitfld.long 0x00 0. " OUT_BLNK_A ,Indicates that WCO clock has transitioned" "Disabled,Enabled"
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group.long 0x60++0x17
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line.long 0x00 "RF_CONFIG,Radio Configuration Register"
|
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bitfld.long 0x00 15. " BPKTCTL_FW_DRIVE ,Enabled FW drives BLERD bpkctl for radio standalone testing" "Disabled,Enabled"
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bitfld.long 0x00 14. " BPKTCTL_FW ,FW drives BLERD bpktctl" "No,Yes"
|
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textline " "
|
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bitfld.long 0x00 8.--11. " DDFT_MUX_CFG2 ,dbg_mux_pin2 selection, combine with BLERD and BLESS" "dbg_pin_mux_2_rd,rxdata,ll_decode_rx_data,dbus_tx_en,fw_clk_en,interrupt_ll_n,ll_st_sm,ll_st_dsm,,,,,,,clk_gate_en_xtal,bb_xo_amp_detect_dft_mux"
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textline " "
|
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bitfld.long 0x00 4.--7. " DDFT_MUX_CFG1 ,dbg_mux_pin1 selection, combine with BLERD and BLESS" "dbg_pin_mux_1_rd,rxclk,bpktctl_to_rd,dbus_rx_en,hw_clk_en,clk_switch_to_sysclk,ll_clk_en_sync,dsm_entry_stat,ll_dsm_xo_on,ll_dsm_xo_off,,,,,,delayed_bg_en"
|
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textline " "
|
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bitfld.long 0x00 0. " RF_ENABLE ,Enables the RF oscillator band gap" "Disabled,Enabled"
|
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line.long 0x04 "XTAL_CLK_DIV_CONFIG,Crystal Clock Divider Configuration Register"
|
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bitfld.long 0x04 2.--3. " LLCLK_DIV ,Link layer clock pre-divider value" "1,/2,/4,/8"
|
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bitfld.long 0x04 0.--1. " SYSCLK_DIV ,System clock pre-divider value" "1,/2,/4,/8"
|
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line.long 0x08 "LL_DSM_INTR_STAT,Link Layer Interrupt Status Register"
|
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eventfld.long 0x08 8. " XTAL_ON_INTR ,Enabled crystal stable signal rising edge interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " DSM_EXITED_INTR ,DSM exited interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
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eventfld.long 0x08 0. " DSM_ENTERED_INTR ,DSM entered interrupt" "No interrupt,Interrupt"
|
|
line.long 0x0C "LL_DSM_CTRL,Link Layer State Machine Control Register"
|
|
bitfld.long 0x0C 3. " XTAL_ON_INTR_MASK ,Masks the crystal stable interrupt" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " DSM_EXITED_INTR_MASK ,Masks the DSM exited interrupt" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DSM_ENTERED_INTR_MASK ,Masks the DSM entered interrupt" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " DSM_EXIT ,DSM exit" "Disabled,Enabled"
|
|
line.long 0x10 "LL_CLK_EN,Link Layer Primary Clock Enable"
|
|
bitfld.long 0x10 1. " CY_CORREL_EN ,Enable cypress correlator logic to bypass MT logic" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " CLK_EN ,Enable the clock to link layer" "Disabled,Enabled"
|
|
line.long 0x14 "LF_CLK_CTRL,BLESS LF Clock Control"
|
|
bitfld.long 0x14 0. " DISABLE_LF_CLK ,LF clock disable" "No,Yes"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "WCO_TRIM,WCO Trim Register"
|
|
bitfld.long 0x00 4.--5. " LPM_GM ,GM setting for LPM" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " XGM ,Amplifier GM setting" "3370nA,2620nA,2250nA,1500nA,1870nA,1120nA,750nA,0nA"
|
|
width 0x0B
|
|
tree.end
|
|
tree "BLESS2 (BLE Sub System Version 2)"
|
|
base ad:0x402EF000
|
|
width 31.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BLE_BLESS_WCO_CONFIG,WCO Configuration Register"
|
|
bitfld.long 0x00 31. " ENABLE ,Master enable for WCO oscillator" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ENBUS ,Test mode control bits"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EXT_INPUT_EN ,Disables the load resistor and allows external clock input for pad_xin" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPM_AUTO ,Automatically control low power mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LPM_EN ,Force block into low power mode" "Not forced,Forced"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "BLE_BLESS_WCO_STATUS,WCO Status Register"
|
|
bitfld.long 0x00 0. " OUT_BLNK_A ,Indicates that WCO clock has transitioned" "Disabled,Enabled"
|
|
group.long 0x0C++0x13
|
|
line.long 0x00 "BLE_BLESS_BIST_MODE_EN,Memory BIST Mode Enable"
|
|
bitfld.long 0x00 0. " MEM_BIST_MODE ,Enables memory BIST mode" "Disabled,Enabled"
|
|
line.long 0x04 "BLE_BLESS_BIST_CMD,Bist Command Register"
|
|
bitfld.long 0x04 0. " SRAM_GO ,Starts SRAM BIST" "Stopped,Started"
|
|
line.long 0x08 "BLE_BLESS_BIST_DATA,BIST Data Register"
|
|
line.long 0x0C "BLE_BLESS_BIST_MASK,BIST Mask Register"
|
|
line.long 0x10 "BLE_BLESS_BIST_CTL,BIST Control Register"
|
|
bitfld.long 0x10 21. " ADDR_START_ENABLED ,ADDR start enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " ROW_FIRST ,Specifies how the SRAM addresses are generated" "Columns,Rows"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " STEPS ,Amount of steps" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x10 0.--5. " SRAMS_ENABLED ,Hot-one mask for the SRAMs" ",ADV_TX_SRAM_MASK,ADV_RX_SRAM_MASK,,CONN_RX_SRAM_MASK,,,,CONN_TX_SRAM_MASK,,,,,,,,DUT_SRAM_MASK,,,,,,,,,,,,,,,WLF_SRAM_MASK,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,ENC_SRAM_MASK"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BLE_BLESS_BIST_STEP0_CTL,BIST Step 0 Control Register"
|
|
bitfld.long 0x00 4. " UP ,Specifies direction in which SRAM BIST steps through addresses" "From the maximum,From the minimum"
|
|
bitfld.long 0x00 0.--3. " OPCODE ,Specifies what sequence of SRAM BIST steps is perfomed" "W0,W1,R0,R1,W0/R0,R0/W1,R1/W0,R0/W1/R1,R1/W0/R0,R0/W1/W0,R1/W0/W1,R0/W1/W0/W1,R1/W0/W1/W0,R0/W1/R1/W0,R1/W0/R0/W1,R0/W1/R1/W0/R0/W1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "BLE_BLESS_BIST_STEP1_CTL,BIST Step 1 Control Register"
|
|
bitfld.long 0x00 4. " UP ,Specifies direction in which SRAM BIST steps through addresses" "From the maximum,From the minimum"
|
|
bitfld.long 0x00 0.--3. " OPCODE ,Specifies what sequence of SRAM BIST steps is perfomed" "W0,W1,R0,R1,W0/R0,R0/W1,R1/W0,R0/W1/R1,R1/W0/R0,R0/W1/W0,R1/W0/W1,R0/W1/W0/W1,R1/W0/W1/W0,R0/W1/R1/W0,R1/W0/R0/W1,R0/W1/R1/W0/R0/W1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "BLE_BLESS_BIST_STEP2_CTL,BIST Step 2 Control Register"
|
|
bitfld.long 0x00 4. " UP ,Specifies direction in which SRAM BIST steps through addresses" "From the maximum,From the minimum"
|
|
bitfld.long 0x00 0.--3. " OPCODE ,Specifies what sequence of SRAM BIST steps is perfomed" "W0,W1,R0,R1,W0/R0,R0/W1,R1/W0,R0/W1/R1,R1/W0/R0,R0/W1/W0,R1/W0/W1,R0/W1/W0/W1,R1/W0/W1/W0,R0/W1/R1/W0,R1/W0/R0/W1,R0/W1/R1/W0/R0/W1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "BLE_BLESS_BIST_STEP3_CTL,BIST Step 3 Control Register"
|
|
bitfld.long 0x00 4. " UP ,Specifies direction in which SRAM BIST steps through addresses" "From the maximum,From the minimum"
|
|
bitfld.long 0x00 0.--3. " OPCODE ,Specifies what sequence of SRAM BIST steps is perfomed" "W0,W1,R0,R1,W0/R0,R0/W1,R1/W0,R0/W1/R1,R1/W0/R0,R0/W1/W0,R1/W0/W1,R0/W1/W0/W1,R1/W0/W1/W0,R0/W1/R1/W0,R1/W0/R0/W1,R0/W1/R1/W0/R0/W1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "BLE_BLESS_BIST_STEP4_CTL,BIST Step 4 Control Register"
|
|
bitfld.long 0x00 4. " UP ,Specifies direction in which SRAM BIST steps through addresses" "From the maximum,From the minimum"
|
|
bitfld.long 0x00 0.--3. " OPCODE ,Specifies what sequence of SRAM BIST steps is perfomed" "W0,W1,R0,R1,W0/R0,R0/W1,R1/W0,R0/W1/R1,R1/W0/R0,R0/W1/W0,R1/W0/W1,R0/W1/W0/W1,R1/W0/W1/W0,R0/W1/R1/W0,R1/W0/R0/W1,R0/W1/R1/W0/R0/W1"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "BLE_BLESS_BIST_STEP5_CTL,BIST Step 5 Control Register"
|
|
bitfld.long 0x00 4. " UP ,Specifies direction in which SRAM BIST steps through addresses" "From the maximum,From the minimum"
|
|
bitfld.long 0x00 0.--3. " OPCODE ,Specifies what sequence of SRAM BIST steps is perfomed" "W0,W1,R0,R1,W0/R0,R0/W1,R1/W0,R0/W1/R1,R1/W0/R0,R0/W1/W0,R1/W0/W1,R0/W1/W0/W1,R1/W0/W1/W0,R0/W1/R1/W0,R1/W0/R0/W1,R0/W1/R1/W0/R0/W1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "BLE_BLESS_BIST_STEP6_CTL,BIST Step 6 Control Register"
|
|
bitfld.long 0x00 4. " UP ,Specifies direction in which SRAM BIST steps through addresses" "From the maximum,From the minimum"
|
|
bitfld.long 0x00 0.--3. " OPCODE ,Specifies what sequence of SRAM BIST steps is perfomed" "W0,W1,R0,R1,W0/R0,R0/W1,R1/W0,R0/W1/R1,R1/W0/R0,R0/W1/W0,R1/W0/W1,R0/W1/W0/W1,R1/W0/W1/W0,R0/W1/R1/W0,R1/W0/R0/W1,R0/W1/R1/W0/R0/W1"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "BLE_BLESS_BIST_STEP7_CTL,BIST Step 7 Control Register"
|
|
bitfld.long 0x00 4. " UP ,Specifies direction in which SRAM BIST steps through addresses" "From the maximum,From the minimum"
|
|
bitfld.long 0x00 0.--3. " OPCODE ,Specifies what sequence of SRAM BIST steps is perfomed" "W0,W1,R0,R1,W0/R0,R0/W1,R1/W0,R0/W1/R1,R1/W0/R0,R0/W1/W0,R1/W0/W1,R0/W1/W0/W1,R1/W0/W1/W0,R0/W1/R1/W0,R1/W0/R0/W1,R0/W1/R1/W0/R0/W1"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "BLE_BLESS_BIST_ADDR_START,BIST Address Start Register"
|
|
hexmask.long.word 0x00 16.--27. 0x01 " ROW_ADDR_START ,Row start address"
|
|
hexmask.long.word 0x00 0.--11. 0x01 " COL_ADDR_START ,Column start address"
|
|
line.long 0x04 "BLE_BLESS_BIST_POL_MASK,BIST Address Polarity Mask Register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " ROW_POLARITY_MASK ,Row address polarity mask"
|
|
hexmask.long.byte 0x04 0.--7. 1. " COL_POLARITY_MASK ,Column address polarity mask"
|
|
line.long 0x08 "BLE_BLESS_BIST_STATUS,BIST Status Register"
|
|
bitfld.long 0x08 24. " FAIL ,BIST fail" "Passed,Failed"
|
|
rbitfld.long 0x08 16.--19. " SRAM ,SRAM identifier" "ADV TX FIFO memory,ADV RX FIFO memory,CONN RX FIFO memory,CONN TX FIFO memory,DUP FIFO memory,WLF FIFO memory,ENC FIFO memory,?..."
|
|
textline " "
|
|
rbitfld.long 0x08 8.--10. " STEP ,BIST step" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x08 0.--2. " SUB_STEP ,BIST substep" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x4C++0x0B
|
|
line.long 0x00 "BLE_BLESS_BIST_DATA_ACT,BIST Data Expected Register"
|
|
line.long 0x04 "BLE_BLESS_BIST_DATA_EXP,BIST Data Actual Register"
|
|
line.long 0x08 "BLE_BLESS_BIST_ADDR,BIST Address Register"
|
|
hexmask.long.word 0x08 16.--27. 1. " ROW_ADDR ,Current row address"
|
|
hexmask.long.word 0x08 0.--11. 1. " COL_ADDR ,Current column address"
|
|
group.long 0x60++0x17
|
|
line.long 0x00 "BLE_BLESS_RF_CONFIG,Radio Configuration Register"
|
|
bitfld.long 0x00 15. " BPKTCTL_FW_DRIVE ,Enabled FW drives BLERD bpkctl for radio standalone testing" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BPKTCTL_FW ,FW drives BLERD bpktctl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " DDFT_MUX_CFG2 ,dbg_mux_pin2 selection" "dbg_pin_mux_2_rd,rxdata,ll_decode_rx_data,dbus_tx_en,fw_clk_en,interrupt_ll_n,ll_st_sm,ll_st_dsm,,,,,,,clk_gate_en_xtal,bb_xo_amp_detect_dft_mux"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " DDFT_MUX_CFG1 ,dbg_mux_pin1 selection" "dbg_pin_mux_1_rd,rxclk,bpktctl_to_rd,dbus_rx_en,hw_clk_en,clk_switch_to_sysclk,ll_clk_en_sync,dsm_entry_stat,ll_dsm_xo_on,ll_dsm_xo_off,,,,,,delayed_bg_en"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RF_ENABLE ,Enables the RF oscillator band gap" "Disabled,Enabled"
|
|
line.long 0x04 "BLE_BLESS_XTAL_CLK_DIV_CONFIG,Crystal Clock Divider Configuration Register"
|
|
bitfld.long 0x04 2.--3. " LLCLK_DIV ,Link layer clock pre-divider value" "/1,/2,/4,/8"
|
|
bitfld.long 0x04 0.--1. " SYSCLK_DIV ,System clock pre-divider value" "/1,/2,/4,/8"
|
|
line.long 0x08 "BLE_BLESS_LL_DSM_INTR_STAT,Link Layer Interrupt Status Register"
|
|
eventfld.long 0x08 8. " XTAL_ON_INTR ,Enabled crystal stable signal rising edge interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " DSM_EXITED_INTR ,DSM exited interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 0. " DSM_ENTERED_INTR ,DSM entered interrupt" "No interrupt,Interrupt"
|
|
line.long 0x0C "BLE_BLESS_LL_DSM_CTRL,Link Layer State Machine Control Register"
|
|
bitfld.long 0x0C 3. " XTAL_ON_INTR_MASK ,Masks the crystal stable interrupt" "Not masked,Masked"
|
|
bitfld.long 0x0C 2. " DSM_EXITED_INTR_MASK ,Masks the DSM exited interrupt" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " DSM_ENTERED_INTR_MASK ,Masks the DSM entered interrupt" "Not masked,Masked"
|
|
bitfld.long 0x0C 0. " DSM_EXIT ,DSM exit" "Disabled,Enabled"
|
|
line.long 0x10 "BLE_BLESS_LL_CLK_EN,Link Layer Primary Clock Enable"
|
|
bitfld.long 0x10 1. " CY_CORREL_EN ,Enable cypress correlator logic to bypass MT logic" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " CLK_EN ,Enable the clock to link layer" "Disabled,Enabled"
|
|
line.long 0x14 "BLE_BLESS_LF_CLK_CTRL,BLESS LF Clock Control"
|
|
bitfld.long 0x14 0. " DISABLE_LF_CLK ,LF clock disable" "No,Yes"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "BLE_BLESS_WCO_TRIM,WCO Trim Register"
|
|
bitfld.long 0x00 4.--5. " LPM_GM ,GM setting for LPM" "0,1,2,3"
|
|
bitfld.long 0x00 0.--2. " XGM ,Amplifier GM setting" "3370nA,2620nA,2250nA,1500nA,1870nA,1120nA,750nA,0nA"
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "CNT (TCPWM - Individual Counter)"
|
|
tree "CNT 0"
|
|
base ad:0x40200100
|
|
width 20.
|
|
if (((per.l(ad:0x40200000))&0x1<<0.)==0x1<<0.)
|
|
if (((per.l(ad:0x40200100))&0x7000000)==0x3000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "X1,X2,X4,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
elif (((per.l(ad:0x40200100))&0x7000000)==(0x4000000||0x5000000))
|
|
if (((per.l(ad:0x40200100))&0x7000000)==0x4000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,8-bit generic control field"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
endif
|
|
elif (((per.l(ad:0x40200100))&0x07000000)==0x06000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
elif (((per.l(ad:0x40200100))&0x07000000)==0x00000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
endif
|
|
if (((per.l(ad:0x40200100))&0x7000000)==0x5000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic counter field"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic counter field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
endif
|
|
if (((per.l(ad:0x40200100+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "CC,Counter Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CC ,Counter compare"
|
|
line.long 0x04 "CC_BUFF,Counter Buffered Compare/capture Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CC ,Additional buffer for counter CC register"
|
|
line.long 0x08 "PERIOD,Counter Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERIOD ,Period value"
|
|
line.long 0x0C "PERIOD_BUFF,Counter Buffered Period Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0"
|
|
bitfld.long 0x00 16.--19. " START_SEL ,Selects one of the 16 triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " STOP_SEL ,Selects one of the 16 triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RELOAD_SEL ,Selects one of the 16 triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " COUNT_SEL ,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Selects one of the 16 input trigger as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1"
|
|
bitfld.long 0x04 8.--9. " START_EDGE ,Start event will start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop event will stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Reload event will initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 2.--3. " COUNT_EDGE ,Counter event will increase or decrease the counter by 1" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Capture event will copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2"
|
|
bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Determines the effect of a counter underflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Determines the effect of a counter overflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Determines the effect of a compare match event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " TC ,Terminal count event" "Not detected,Detected"
|
|
line.long 0x04 "INTR_SET,Interrupt Set Request Register"
|
|
bitfld.long 0x04 1. " CC_MATCH ,Set counter matches CC register event" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " TC ,Set terminal count event" "Not detected,Detected"
|
|
line.long 0x08 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register"
|
|
rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CNT 1"
|
|
base ad:0x40200140
|
|
width 20.
|
|
if (((per.l(ad:0x40200000))&0x1<<1.)==0x1<<1.)
|
|
if (((per.l(ad:0x40200140))&0x7000000)==0x3000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "X1,X2,X4,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
elif (((per.l(ad:0x40200140))&0x7000000)==(0x4000000||0x5000000))
|
|
if (((per.l(ad:0x40200140))&0x7000000)==0x4000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,8-bit generic control field"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
endif
|
|
elif (((per.l(ad:0x40200140))&0x07000000)==0x06000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
elif (((per.l(ad:0x40200140))&0x07000000)==0x00000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
endif
|
|
if (((per.l(ad:0x40200140))&0x7000000)==0x5000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic counter field"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic counter field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
endif
|
|
if (((per.l(ad:0x40200140+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "CC,Counter Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CC ,Counter compare"
|
|
line.long 0x04 "CC_BUFF,Counter Buffered Compare/capture Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CC ,Additional buffer for counter CC register"
|
|
line.long 0x08 "PERIOD,Counter Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERIOD ,Period value"
|
|
line.long 0x0C "PERIOD_BUFF,Counter Buffered Period Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0"
|
|
bitfld.long 0x00 16.--19. " START_SEL ,Selects one of the 16 triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " STOP_SEL ,Selects one of the 16 triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RELOAD_SEL ,Selects one of the 16 triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " COUNT_SEL ,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Selects one of the 16 input trigger as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1"
|
|
bitfld.long 0x04 8.--9. " START_EDGE ,Start event will start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop event will stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Reload event will initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 2.--3. " COUNT_EDGE ,Counter event will increase or decrease the counter by 1" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Capture event will copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2"
|
|
bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Determines the effect of a counter underflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Determines the effect of a counter overflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Determines the effect of a compare match event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " TC ,Terminal count event" "Not detected,Detected"
|
|
line.long 0x04 "INTR_SET,Interrupt Set Request Register"
|
|
bitfld.long 0x04 1. " CC_MATCH ,Set counter matches CC register event" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " TC ,Set terminal count event" "Not detected,Detected"
|
|
line.long 0x08 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register"
|
|
rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CNT 2"
|
|
base ad:0x40200180
|
|
width 20.
|
|
if (((per.l(ad:0x40200000))&0x1<<2.)==0x1<<2.)
|
|
if (((per.l(ad:0x40200180))&0x7000000)==0x3000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "X1,X2,X4,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
elif (((per.l(ad:0x40200180))&0x7000000)==(0x4000000||0x5000000))
|
|
if (((per.l(ad:0x40200180))&0x7000000)==0x4000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,8-bit generic control field"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
endif
|
|
elif (((per.l(ad:0x40200180))&0x07000000)==0x06000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
elif (((per.l(ad:0x40200180))&0x07000000)==0x00000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
endif
|
|
if (((per.l(ad:0x40200180))&0x7000000)==0x5000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic counter field"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic counter field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
endif
|
|
if (((per.l(ad:0x40200180+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "CC,Counter Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CC ,Counter compare"
|
|
line.long 0x04 "CC_BUFF,Counter Buffered Compare/capture Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CC ,Additional buffer for counter CC register"
|
|
line.long 0x08 "PERIOD,Counter Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERIOD ,Period value"
|
|
line.long 0x0C "PERIOD_BUFF,Counter Buffered Period Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0"
|
|
bitfld.long 0x00 16.--19. " START_SEL ,Selects one of the 16 triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " STOP_SEL ,Selects one of the 16 triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RELOAD_SEL ,Selects one of the 16 triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " COUNT_SEL ,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Selects one of the 16 input trigger as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1"
|
|
bitfld.long 0x04 8.--9. " START_EDGE ,Start event will start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop event will stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Reload event will initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 2.--3. " COUNT_EDGE ,Counter event will increase or decrease the counter by 1" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Capture event will copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2"
|
|
bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Determines the effect of a counter underflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Determines the effect of a counter overflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Determines the effect of a compare match event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " TC ,Terminal count event" "Not detected,Detected"
|
|
line.long 0x04 "INTR_SET,Interrupt Set Request Register"
|
|
bitfld.long 0x04 1. " CC_MATCH ,Set counter matches CC register event" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " TC ,Set terminal count event" "Not detected,Detected"
|
|
line.long 0x08 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register"
|
|
rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CNT 3"
|
|
base ad:0x402001C0
|
|
width 20.
|
|
if (((per.l(ad:0x40200000))&0x1<<3.)==0x1<<3.)
|
|
if (((per.l(ad:0x402001C0))&0x7000000)==0x3000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "X1,X2,X4,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
elif (((per.l(ad:0x402001C0))&0x7000000)==(0x4000000||0x5000000))
|
|
if (((per.l(ad:0x402001C0))&0x7000000)==0x4000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,8-bit generic control field"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
endif
|
|
elif (((per.l(ad:0x402001C0))&0x07000000)==0x06000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
elif (((per.l(ad:0x402001C0))&0x07000000)==0x00000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
endif
|
|
if (((per.l(ad:0x402001C0))&0x7000000)==0x5000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic counter field"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic counter field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
endif
|
|
if (((per.l(ad:0x402001C0+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "CC,Counter Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CC ,Counter compare"
|
|
line.long 0x04 "CC_BUFF,Counter Buffered Compare/capture Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CC ,Additional buffer for counter CC register"
|
|
line.long 0x08 "PERIOD,Counter Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERIOD ,Period value"
|
|
line.long 0x0C "PERIOD_BUFF,Counter Buffered Period Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0"
|
|
bitfld.long 0x00 16.--19. " START_SEL ,Selects one of the 16 triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " STOP_SEL ,Selects one of the 16 triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RELOAD_SEL ,Selects one of the 16 triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " COUNT_SEL ,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Selects one of the 16 input trigger as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1"
|
|
bitfld.long 0x04 8.--9. " START_EDGE ,Start event will start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop event will stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Reload event will initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 2.--3. " COUNT_EDGE ,Counter event will increase or decrease the counter by 1" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Capture event will copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2"
|
|
bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Determines the effect of a counter underflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Determines the effect of a counter overflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Determines the effect of a compare match event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " TC ,Terminal count event" "Not detected,Detected"
|
|
line.long 0x04 "INTR_SET,Interrupt Set Request Register"
|
|
bitfld.long 0x04 1. " CC_MATCH ,Set counter matches CC register event" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " TC ,Set terminal count event" "Not detected,Detected"
|
|
line.long 0x08 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register"
|
|
rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "SRSS (System Resources Sub System)"
|
|
base ad:0x400B0000
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWR_CONTROL,Power Mode Control"
|
|
bitfld.long 0x00 31. " HIBERNATE ,Selects between HIBERNATE/DEEPSLEEP modes when Cortex-M0 enters low power mode" "DEPP_SLEEP,HIBERNATE"
|
|
bitfld.long 0x00 29. " LFCLK_SHORT ,Short Vcclfclk and Vccdpslp power rails in DeepSleep power mode" "No short power domains,Short power domains"
|
|
textline " "
|
|
bitfld.long 0x00 28. " HIBERNATE_DISABLE ,Hibernate disable" "No,Yes"
|
|
bitfld.long 0x00 27. " FIMO_DISABLE ,Force IMO disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 25. " HVMON_RELOAD ,Firmware writes 1 to reload HV state in hibernate shadow copy" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 24. " HVMON_ENABLE ,HV state monitoring enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EXT_VCCD ,External VCCD" "No,Yes"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " LPM_READY ,Indicates whether the low power mode regulator is ready to enter DEEPSLEEP mode" "Enter SLEEP mode,Normal operation"
|
|
rbitfld.long 0x00 4. " DEBUG_SESSION ,Indicates whether a debug session is active" "NO_SESSION,SESSION_ACTIVE"
|
|
rbitfld.long 0x00 0.--3. " POWER_MODE ,Current power mode of the device" "RESET,ACTIVE,SLEEP,DEEP_SLEEP,?..."
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "INTR,SRSS Interrupt Register"
|
|
eventfld.long 0x00 1. " LVD ,Indicates an Low Voltage Detect interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_MASK,SRSS Interrupt Mask Register"
|
|
bitfld.long 0x04 1. " LVD ,Propagate interrupt to CPU" "Not masked,Masked"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PWR_KEY_DELAY,Power System Key Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAKEUP_HOLDOFF ,Delay to wait for references to settle on wake up from DeepSleep"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "PWR_BG_CONFIG,Bandgap Trim and Configuration"
|
|
bitfld.long 0x00 18. " VREF_EN[2] ,Reference voltage enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " [1] ,Reference voltage enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " [0] ,Reference voltage enable 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " BG_DFT_VCORE_SEL ,Selects a BG core voltage to output on mux2out" "Vout,Vgnd"
|
|
bitfld.long 0x00 6.--7. " BG_DFT_ICORE_SEL ,Selects a BG core current to output on mux1out" "Iptat,Ictat,inl_cross_over,iref9p6u_dft"
|
|
bitfld.long 0x00 5. " BG_DFT_CORE_SEL ,Selects which BG core signal to output on adft_bg_core" "mux2out,mux1out"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " BG_DFT_VREF_SEL ,Select a voltage reference to output on adft_bg_ref" "vgnd,vref_fast[0],vref_fast[1],vref_fast[2],vref_fast[3],vref_fast[4],vref_fast[5],vref_fast[6],vref_fast[7],vref[0],vref[1],vref[2],vctat,iref_dft,imo_iref,inl_imoref"
|
|
bitfld.long 0x00 0. " BG_DFT_EN ,Enables DFT capability for Bandgap" "Disabled,Enabled"
|
|
line.long 0x04 "PWR_VMON_CONFIG,Voltage Monitoring Trim And Configuration"
|
|
bitfld.long 0x04 8.--9. " VMON_ADFT_SEL ,Selects a signal to output on adft_vmon" "Hi-Z,pbod monitor,hvpbod monitor,lvi monitor"
|
|
bitfld.long 0x04 5.--7. " VMON_DDFT_SEL ,Selects a signal to output on ddft_vmon" "0,pbod_out,pbod monitor,hvpbod_out,hvpbod monitor,lvi_out,lvi monitor,?..."
|
|
textline " "
|
|
bitfld.long 0x04 1.--4. " LVD_SEL ,Threshold selection for Low Voltage Detect circuit" "1.75V,1.8V,1.9V,2.0V,2.1V,2.2V,2.3V,2.4V,2.5V,2.6V,2.7V,2.8V,2.9V,3.0V,3.2V,4.5V"
|
|
bitfld.long 0x04 0. " LVD_EN ,Enable low voltage detect circuit" "Disabled,Enabled"
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "PWR_DDFT_SELECT,Digital DFT Select"
|
|
bitfld.long 0x00 4.--7. " DDFT2_SEL ,Signal select for ddft2 output" "act_power_en_a,power_up_raw,act_power_good_a,fastrefs_valid,vmon,bootref_outen,bootref_refsw,active_inrush_dis,awake,hvpor_reset_n,lpcomp_dis,wakeup_a,vmon_valid,block_rst_awake,slpholdreq_n,io_disable_delayed"
|
|
bitfld.long 0x00 0.--3. " DDFT1_SEL ,Signal select for ddft1 output" "wakeup_a,ipor_reset,hbod_reset_raw_n,lpcomp_dis,power_up_delayed,awake,hvmon_out_of_sync,pbod_reset,hvbod_reset,lpm_ready,io_disable_req_lv,bootref_en,?..."
|
|
line.long 0x04 "PWR_DFT_KEY,DFT Safety Override"
|
|
bitfld.long 0x04 20. " VMON_PD ,Disables the VMON block" "No,Yes"
|
|
bitfld.long 0x04 19. " IO_DISABLE_BYPASS ,Bypasses the IO disable logic" "No bypass,Bypass"
|
|
bitfld.long 0x04 18. " DFT_MODE ,Enable DfT modes" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " BODS_OFF ,Forces all outputs of BOD detectors to be ignored" "Not ignored,Ignored"
|
|
bitfld.long 0x04 16. " HBOD_OFF_AWAKE ,Forces the output of the HBOD to be blocked" "Not blocked,Blocked"
|
|
hexmask.long.word 0x04 0.--15. 1. " KEY16 ,Detect brown-outs firmware"
|
|
line.long 0x08 "PWR_BOD_KEY,BOD Detection Key"
|
|
hexmask.long.word 0x08 0.--15. 1. " KEY16 ,Detect brown-outs firmware"
|
|
line.long 0x0C "PWR_STOP,STOP Mode Register"
|
|
bitfld.long 0x0C 31. " STOP ,STOP mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " FREEZE ,Freeze the configuration enable" "Disbaled,Enabled"
|
|
bitfld.long 0x0C 16. " POLARITY , Polarity enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 8.--15. 1. " UNLOCK ,Unlock"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TOKEN ,Contains a 8-bit token"
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "CLK_SELECT,Clock Select Register"
|
|
bitfld.long 0x00 19.--21. " SYSCLK_DIV ,Select clk_sys prescaler value" "NO_DIV,DIV_BY_2,DIV_BY_4,DIV_BY_8,DIV_BY_16,DIV_BY_32,DIV_BY_64,DIV_BY_128"
|
|
bitfld.long 0x00 18. " HALF_EN ,Half Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " HFCLK_SEL ,Selects the source for HFCLK" "DIRECT_SEL,DBL,PLL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " WDT_LOCK ,Prohibits writing to WDT" "NO_CHG,CLR0,CLR1,SET01"
|
|
bitfld.long 0x00 12.--13. " DPLLREF_SEL ,Selects a source for the reference (tracking) input of DPLL" "DSI_OUT[0],DSI_OUT[1],DSI_OUT[2],DSI_OUT[3]"
|
|
bitfld.long 0x00 9.--11. " DPLLIN_SEL ,Selects a source for the input of DPLL" "IMO,EXTCLK,ECO,,DSI0,DSI1,DSI2,DSI3"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " PLL_SEL ,Selects a source the input of EXCO PLL0" "IMO,EXTCLK,ECO,DPLL,DSI0,DSI1,DSI2,DSI3"
|
|
bitfld.long 0x00 3.--5. " DBL_SEL ,Selects a source the input of EXCO PLL1" "IMO,EXTCLK,ECO,,DSI0,DSI1,DSI2,DSI3"
|
|
bitfld.long 0x00 0.--2. " DIRECT_SEL ,Selects a source for HFCLK" "IMO,EXTCLK,ECO,,DSI0,DSI1,DSI2,DSI3"
|
|
line.long 0x04 "CLK_ILO_CONFIG,ILO Configuration"
|
|
bitfld.long 0x04 31. " ENABLE ,Master enable for ILO oscillator" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " SATBIAS ,PFET bias" "Saturated,Subthreshold"
|
|
bitfld.long 0x04 1. " TURBO ,Turbo mode for faster startup from coma power down" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " PD_MODE ,Power down mode" "Sleep,Coma"
|
|
line.long 0x08 "CLK_IMO_CONFIG,IMO Configuration"
|
|
bitfld.long 0x08 31. " ENABLE ,Master enable for IMO oscillator" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " EN_CLK2X ,Enables main oscillator doubler circuit" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " EN_CLK36 ,Enables 36MHz secondary oscillator" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 28. " TEST_USB_MODE ,Forces IMO into USB mode" "Not forced,Forced"
|
|
bitfld.long 0x08 25.--27. " PUMP_SEL ,Selects operating source for Pump clock" "GND,IMO,DBL,CLK36,FF1,?..."
|
|
bitfld.long 0x08 24. " TEST_FASTBIAS ,Forces the IMO into FIMO mode" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 23. " EN_FASTBIAS ,Forces the FIMO's fast bias circuits to remain powered" "Not forced,Forced"
|
|
bitfld.long 0x08 22. " FLASHPUMP_SEL ,Selects operating source for SPCIF Timer/Flash Pump clock" "GND,CLK36"
|
|
line.long 0x0C "CLK_IMO_SPREAD,IMO Spread Spectrum Configuration"
|
|
bitfld.long 0x0C 30.--31. " SS_MODE ,Spread Spectrum Mode" "Off,Triangle,LFSR,DSI"
|
|
bitfld.long 0x0C 28.--29. " SS_RANGE ,Spread spectrum range" "M1,M2,M4,?..."
|
|
bitfld.long 0x0C 8.--12. " SS_MAX ,Maximum counter value for spread spectrum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--4. " SS_VALUE ,Current offset value for spread spectrum modulation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x10 "CLK_DFT_SELECT,Clock DFT Mode Selection Register"
|
|
bitfld.long 0x10 12.--13. " DFT_DIV2 ,DFT Output Divide Down 2" "NO_DIV,DIV_BY_2,DIV_BY_4,DIV_BY_8"
|
|
bitfld.long 0x10 8.--11. " DFT_SEL2 ,Select signal for DFT 2" "NC,ILO,WCO,IMO,ECO,PLL,DPLL_OUT,DPLL_REF,DBL,IMO2X,IMO36,HFCLK,LFCLK,SYSCLK,EXTCLK,HALFSYSCLK"
|
|
bitfld.long 0x10 4.--5. " DFT_DIV1 ,DFT Output Divide Down 1" "NO_DIV,DIV_BY_2,DIV_BY_4,DIV_BY_8"
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " DFT_SEL2 ,Select signal for DFT 2" "NC,ILO,WCO,IMO,ECO,PLL,DPLL_OUT,DPLL_REF,DBL,IMO2X,IMO36,HFCLK,LFCLK,SYSCLK,EXTCLK,HALFSYSCLK"
|
|
rgroup.long 0x200++0x07
|
|
line.long 0x00 "WDT_CTRLOW,Watchdog Counters 0/1"
|
|
hexmask.long.word 0x00 16.--31. 1. " WDT_CTR1 ,Current value of WDT Counter 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDT_CTR0 ,Current value of WDT Counter 0"
|
|
line.long 0x04 "WDT_CTRHIGH,Watchdog Counter 2"
|
|
group.long 0x208++0x0B
|
|
line.long 0x00 "WDT_MATCH,Watchdog Counter Match Values"
|
|
hexmask.long.word 0x00 16.--31. 1. " WDT_MATCH1 ,Match value for Watchdog Counter 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " WDT_MATCH0 ,Match value for Watchdog Counter 0"
|
|
line.long 0x04 "WDT_CONFIG,Watchdog Counters Configuration"
|
|
bitfld.long 0x04 30.--31. " LFCLK_SEL ,Select source for LFCLK" "ILO,WCO,?..."
|
|
bitfld.long 0x04 24.--28. " WDT_BITS2 ,Bit to observe for WDT_INT2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 16. " WDT_MODE2 ,Watchdog Counter 2 Mode" "Nothing,INT"
|
|
textline " "
|
|
bitfld.long 0x04 11. " WDT_CASCADE1_2 ,Cascade Watchdog Counters 1 & 2" "Independent counters,Cascaded counters"
|
|
bitfld.long 0x04 10. " WDT_CLEAR1 ,Clear Watchdog Counter 1" "No,Yes"
|
|
bitfld.long 0x04 8.--9. " WDT_MODE1 ,Watchdog Counter Action 1" "Nothing,INT,RESET,INT_THEN_RESET"
|
|
textline " "
|
|
bitfld.long 0x04 3. " WDT_CASCADE0_1 ,Cascade Watchdog Counters 0 & 1" "Independent counters,Cascaded counters"
|
|
bitfld.long 0x04 2. " WDT_CLEAR0 ,Clear Watchdog Counter 0" "No,Yes"
|
|
bitfld.long 0x04 0.--1. " WDT_MODE0 ,Watchdog Counter Action 0" "Nothing,INT,RESET,INT_THEN_RESET"
|
|
line.long 0x08 "WDT_CONTROL,Watchdog Counters Control"
|
|
bitfld.long 0x08 19. " WDT_RESET2 ,Resets counter 2" "No reset,Reset"
|
|
bitfld.long 0x08 18. " WDT_INT2 ,WDT Interrupt Request 2" "No request,Request"
|
|
rbitfld.long 0x08 17. " WDT_ENABLED2 ,Indicates actual state of counter 2" "Disbaled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " WDT_ENABLE2 ,Enable Counter 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " WDT_RESET1 ,Resets counter 1" "No reset,Reset"
|
|
bitfld.long 0x08 10. " WDT_INT1 ,WDT Interrupt Request 1" "No request,Request"
|
|
textline " "
|
|
rbitfld.long 0x08 9. " WDT_ENABLED1 ,Indicates actual state of counter 1" "Disbaled,Enabled"
|
|
bitfld.long 0x08 8. " WDT_ENABLE1 ,Enable Counter 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " WDT_RESET0 ,Resets counter 0" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 2. " WDT_INT0 ,WDT Interrupt Request 0" "No request,Request"
|
|
rbitfld.long 0x08 1. " WDT_ENABLED0 ,Indicates actual state of counter 0" "Disbaled,Enabled"
|
|
bitfld.long 0x08 0. " WDT_ENABLE0 ,Enable Counter 0" "Disabled,Enabled"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "RES_CAUSE,Reset Cause Observation Register"
|
|
bitfld.long 0x00 7. " RESET_XRES ,Reset XRES" "No reset,Reset"
|
|
bitfld.long 0x00 6. " RESET_PBOD ,Reset PBOD" "No reset,Reset"
|
|
bitfld.long 0x00 5. " RESET_HVBOD ,Reset HVBOD" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RESET_SOFT ,Reset Soft" "No reset,Reset"
|
|
bitfld.long 0x00 3. " RESET_PROT_FAULT ,A protection violation occurred that requires a reset" "No reset,Reset"
|
|
bitfld.long 0x00 2. " RESET_LOCKUP ,Reset LOCKUP" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RESET_DSBOD ,Reset DSBOD" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RESET_WDT ,Reset WDT" "No reset,Reset"
|
|
group.long 0xFF18++0x017
|
|
line.long 0x00 "PWR_BG_TRIM3,Bandgap Trim Register 3"
|
|
bitfld.long 0x00 3.--6. " INL_CROSS_IMO ,IMO Irefgen INL cross-over point control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--2. " INL_TRIM_IMO ,IMO Irefgen nonlinear current trim" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "PWR_BG_TRIM4,Bandgap Trim Register 4"
|
|
bitfld.long 0x04 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "PWR_BG_TRIM5,Bandgap Trim Register 5"
|
|
bitfld.long 0x08 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "CLK_ILO_TRIM,ILO Trim Register"
|
|
bitfld.long 0x0C 4.--7. " COARSE_TRIM ,Adjusts the bias in the event of high current after fab" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. " TRIM ,Trim bits to control frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "CLK_IMO_TRIM1,IMO Trim Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " OFFSET ,Frequency trim bits"
|
|
line.long 0x14 "CLK_IMO_TRIM2,IMO Trim Register"
|
|
bitfld.long 0x14 0.--5. " FREQ ,Frequency" ",,,3MHz,4MHz,5MHz,6MHz,7MHz,8MHz,9MHz,10MHz,11MHz,12MHz,,13MHz,14MHz,15MHz,16MHz,17MHz,18MHz,19MHz,20MHz,21MHz,22MHz,23MHz,24MHz,,,25MHz,26MHz,27MHz,28MHz,29MHz,30MHz,31MHz,32MHz,33MHz,,,34MHz,35MHz,36MHz,37MHz,38MHz,39MHz,40MHz,,,41MHz,42MHz,43MHz,44MHz,45MHz,46MHz,47MHz,48MHz,?..."
|
|
group.long 0xFF34++0x03
|
|
line.long 0x00 "CLK_IMO_TRIM4,IMO Trim Register"
|
|
bitfld.long 0x00 5.--7. " FSOFFSET ,Full-speed USB offset" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " GAIN ,Gain for IMO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CPUSS (CPU Sub System)"
|
|
base ad:0x40100000
|
|
width 11.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG,Configuration Register"
|
|
bitfld.long 0x00 0. " VECT_IN_RAM ,Vector table location" "Flash,SRAM"
|
|
if (((per.l(ad:0x40100000))&0x20000000)==0x20000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SYSREQ,SYSCALL Control Register"
|
|
bitfld.long 0x00 31. " SYSCALL_REQ ,System call request" "Not requested,Requested"
|
|
rbitfld.long 0x00 30. " HMASTER_0 ,Indicates the source of the write access to the SYSREQ register" "CPU,DAP"
|
|
textline " "
|
|
rbitfld.long 0x00 29. " ROM_ACCESS_EN ,Indicates that executing from boot ROM is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PRIVILEGED ,Indicates whether the system is in privileged or user mode" "User mode,Privileged mode"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DIS_RESET_VECT_REL ,Disable reset vector fetch relocation" "ROM,Flash"
|
|
hexmask.long.word 0x00 0.--15. 1. " SYSCALL_COMMAND ,16-bit opcode of the system call being requested"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SYSREQ,SYSCALL Control Register"
|
|
bitfld.long 0x00 31. " SYSCALL_REQ ,System call request" "Not requested,Requested"
|
|
rbitfld.long 0x00 30. " HMASTER_0 ,Indicates the source of the write access to the SYSREQ register" "CPU,DAP"
|
|
textline " "
|
|
rbitfld.long 0x00 29. " ROM_ACCESS_EN ,Indicates that executing from boot ROM is enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " PRIVILEGED ,Indicates whether the system is in privileged or user mode" "User mode,Privileged mode"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DIS_RESET_VECT_REL ,Disable reset vector fetch relocation" "ROM,Flash"
|
|
hexmask.long.word 0x00 0.--15. 1. " SYSCALL_COMMAND ,16-bit opcode of the system call being requested"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SYSARG,SYSARG Control Register"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "INT_SEL,Interrupt Multiplexer Select Register"
|
|
line.long 0x04 "INT_MODE,DSI Interrupt Pulse Mode Register"
|
|
line.long 0x08 "NMI_MODE,DSI NMI Pulse Mode Register"
|
|
bitfld.long 0x08 0. " DSI_NMI_PULSE ,Specifies DSI NMI format" "0,1"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "FLASH_CTL,FLASH Control Register"
|
|
bitfld.long 0x00 8. " FLASH_INVALIDATE ,Flash invalidate" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PREF_EN ,Prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " FLASH_WS ,Amount of ROM wait states" "0 wait,1 wait,2 wait,Undefined"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "ROM_CTL,ROM Control Register"
|
|
bitfld.long 0x00 0. " ROM_WS ,Amount of ROM wait states" "0 wait,1 wait"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMAC (DMA Controller)"
|
|
base ad:0x40101000
|
|
width 22.
|
|
if (((per.l(ad:0x40101000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
rgroup.long 0x10++0x0F
|
|
line.long 0x00 "STATUS,Status"
|
|
bitfld.long 0x00 31. " ACTIVE ,Specifies if there is a currently active channel in the data transfer engine" "Not active,Active"
|
|
bitfld.long 0x00 30. " PING_PONG ,Specifies whether the PING descriptor or PONG descriptor of the channel is currently in use" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Specifies the priority of the currently active channel" "Highest,2,1,Lowest"
|
|
bitfld.long 0x00 24.--26. " STATE ,State of the data transfer engine" "DEFAULT,Loading descriptor,Loading data,Storing data,Storing descriptor,Wait for trigger,Storing descriptor with error responses,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " CH_ADDR ,Specifies the channel number of the currently active channel" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Specifies the index of the currently active data transfer"
|
|
line.long 0x04 "STATUS_SRC_ADDR,Source Address Status Register"
|
|
line.long 0x08 "STATUS_DST_ADDR,Destination Address Register"
|
|
line.long 0x0C "STATUS_CH_ACT,Channel Activation Status Register"
|
|
bitfld.long 0x0C 7. " CH[7] ,Channel 7 activation status bit" "Not pending,Pending"
|
|
bitfld.long 0x0C 6. " [6] ,Channel 6 activation status bit" "Not pending,Pending"
|
|
bitfld.long 0x0C 5. " [5] ,Channel 5 activation status bit" "Not pending,Pending"
|
|
bitfld.long 0x0C 4. " [4] ,Channel 4 activation status bit" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [3] ,Channel 3 activation status bit" "Not pending,Pending"
|
|
bitfld.long 0x0C 2. " [2] ,Channel 2 activation status bit" "Not pending,Pending"
|
|
bitfld.long 0x0C 1. " [1] ,Channel 1 activation status bit" "Not pending,Pending"
|
|
bitfld.long 0x0C 0. " [0] ,Channel 0 activation status bit" "Not pending,Pending"
|
|
if (((per.l(ad:0x40101000+0x80))&0x80000000)==0x80000000)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH_CTL0,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH_CTL0,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x84))&0x80000000)==0x80000000)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CH_CTL1,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CH_CTL1,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x88))&0x80000000)==0x80000000)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CH_CTL2,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CH_CTL2,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x8C))&0x80000000)==0x80000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CH_CTL3,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CH_CTL3,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x90))&0x80000000)==0x80000000)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH_CTL4,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH_CTL4,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x94))&0x80000000)==0x80000000)
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CH_CTL5,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CH_CTL5,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x98))&0x80000000)==0x80000000)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CH_CTL6,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CH_CTL6,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x9C))&0x80000000)==0x80000000)
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CH_CTL7,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CH_CTL7,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x7F0++0x0B
|
|
line.long 0x00 "INTR,Interrupt Register"
|
|
eventfld.long 0x00 7. " CH[7] ,Channel 7 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,Channel 6 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Channel 5 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Channel 4 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Channel 3 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Channel 2 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Channel 1 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Channel 0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,Interrupt Set Register"
|
|
bitfld.long 0x04 7. " CH[7] ,Channel 7 interrupt set" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " [6] ,Channel 6 interrupt set" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " [5] ,Channel 5 interrupt set" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " [4] ,Channel 4 interrupt set" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Channel 3 interrupt set" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " [2] ,Channel 2 interrupt set" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " [1] ,Channel 1 interrupt set" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " [0] ,Channel 0 interrupt set" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x08 7. " CH[7] ,Mask channel 7 interrupt" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " [6] ,Mask channel 6 interrupt" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " [5] ,Mask channel 5 interrupt" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " [4] ,Mask channel 4 interrupt" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Mask channel 3 interrupt" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " [2] ,Mask channel 2 interrupt" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " [1] ,Mask channel 1 interrupt" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " [0] ,Mask channel 0 interrupt" "Not masked,Masked"
|
|
rgroup.long 0x7FC++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt Masked Register"
|
|
bitfld.long 0x00 7. " CH[7] ,Logical AND of corresponding request and mask field for channel 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Logical AND of corresponding request and mask field for channel 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Logical AND of corresponding request and mask field for channel 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Logical AND of corresponding request and mask field for channel 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Logical AND of corresponding request and mask field for channel 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Logical AND of corresponding request and mask field for channel 2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Logical AND of corresponding request and mask field for channel 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Logical AND of corresponding request and mask field for channel 0" "Not masked,Masked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "DMAD (DMA Descriptor)"
|
|
base ad:0x40101800
|
|
width 21.
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x000000)
|
|
if (((per.l(ad:0x40101000+0x80))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x80))&0x40000000)==0x00000000)
|
|
group.long 0x0++0x07
|
|
line.long 0x00 "DESCR0_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR0_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0x0+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "DESCR0_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "DESCR0_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "DESCR0_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0x0+0x10)++0x07
|
|
line.long 0x00 "DESCR0_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR0_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0x0+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0x0+0x18)++0x03
|
|
line.long 0x00 "DESCR0_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x0+0x18)++0x03
|
|
line.long 0x00 "DESCR0_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR0_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x010000)
|
|
if (((per.l(ad:0x40101000+0x84))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x84))&0x40000000)==0x00000000)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DESCR1_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR1_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0x20+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DESCR1_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DESCR1_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0x20+0x0C)++0x03
|
|
line.long 0x00 "DESCR1_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0x20+0x10)++0x07
|
|
line.long 0x00 "DESCR1_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR1_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0x20+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0x20+0x18)++0x03
|
|
line.long 0x00 "DESCR1_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x20+0x18)++0x03
|
|
line.long 0x00 "DESCR1_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR1_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x020000)
|
|
if (((per.l(ad:0x40101000+0x88))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x88))&0x40000000)==0x00000000)
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "DESCR2_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR2_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0x40+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DESCR2_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DESCR2_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0x40+0x0C)++0x03
|
|
line.long 0x00 "DESCR2_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0x40+0x10)++0x07
|
|
line.long 0x00 "DESCR2_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR2_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0x40+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "DESCR2_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "DESCR2_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR2_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x030000)
|
|
if (((per.l(ad:0x40101000+0x8C))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x8C))&0x40000000)==0x00000000)
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "DESCR3_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR3_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0x60+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DESCR3_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DESCR3_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "DESCR3_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0x60+0x10)++0x07
|
|
line.long 0x00 "DESCR3_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR3_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0x60+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0x60+0x18)++0x03
|
|
line.long 0x00 "DESCR3_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x60+0x18)++0x03
|
|
line.long 0x00 "DESCR3_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR3_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x040000)
|
|
if (((per.l(ad:0x40101000+0x90))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x90))&0x40000000)==0x00000000)
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "DESCR4_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR4_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0x80+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DESCR4_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DESCR4_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "DESCR4_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0x80+0x10)++0x07
|
|
line.long 0x00 "DESCR4_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR4_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0x80+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0x80+0x18)++0x03
|
|
line.long 0x00 "DESCR4_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x80+0x18)++0x03
|
|
line.long 0x00 "DESCR4_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR4_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x050000)
|
|
if (((per.l(ad:0x40101000+0x94))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x94))&0x40000000)==0x00000000)
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "DESCR5_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR5_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0xA0+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "DESCR5_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "DESCR5_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0xA0+0x0C)++0x03
|
|
line.long 0x00 "DESCR5_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0xA0+0x10)++0x07
|
|
line.long 0x00 "DESCR5_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR5_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0xA0+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0xA0+0x18)++0x03
|
|
line.long 0x00 "DESCR5_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0xA0+0x18)++0x03
|
|
line.long 0x00 "DESCR5_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR5_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x060000)
|
|
if (((per.l(ad:0x40101000+0x98))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x98))&0x40000000)==0x00000000)
|
|
group.long 0xC0++0x07
|
|
line.long 0x00 "DESCR6_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR6_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0xC0+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "DESCR6_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "DESCR6_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0xC0+0x0C)++0x03
|
|
line.long 0x00 "DESCR6_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0xC0+0x10)++0x07
|
|
line.long 0x00 "DESCR6_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR6_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0xC0+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0xC0+0x18)++0x03
|
|
line.long 0x00 "DESCR6_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0xC0+0x18)++0x03
|
|
line.long 0x00 "DESCR6_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR6_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x070000)
|
|
if (((per.l(ad:0x40101000+0x9C))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x9C))&0x40000000)==0x00000000)
|
|
group.long 0xE0++0x07
|
|
line.long 0x00 "DESCR7_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR7_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0xE0+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "DESCR7_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "DESCR7_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0xE0+0x0C)++0x03
|
|
line.long 0x00 "DESCR7_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0xE0+0x10)++0x07
|
|
line.long 0x00 "DESCR7_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR7_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0xE0+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0xE0+0x18)++0x03
|
|
line.long 0x00 "DESCR7_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0xE0+0x18)++0x03
|
|
line.long 0x00 "DESCR7_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR7_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("CY8C4*-BL453")||cpuis("CY8C4*-BL483")||cpuis("CY8C4*-BL493")
|
|
tree "CSD (CapSense Sigma Delta)"
|
|
base ad:0x40280000
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CSD_ID,ID and Revision Number"
|
|
hexmask.long.word 0x00 16.--31. 1. " REVISION ,The version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " ID ,The ID of CSD peripheral"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CSD_INTR,CSD Interrupt Request Register"
|
|
eventfld.long 0x00 0. " CSD ,CSD interrupt" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CSD_INTR_SET,CSD Interrupt Set Register"
|
|
bitfld.long 0x00 0. " CSD ,The CSD IRQ set bit" "No effect,Set"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CSD_PWM,CSD PWM Register"
|
|
bitfld.long 0x00 4.--5. " PWM_SEL ,The mode of the PWM modulator" "Off,,Fixed high,Fixed low"
|
|
bitfld.long 0x00 0.--3. " PWM_COUNT ,Pulse width modulation count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif !cpuis("CY8C4*-BL443")
|
|
sif cpuis("CY8C41*-BL*")
|
|
tree "CTBM (Continuous Time Block Mini)"
|
|
base ad:0x40300000
|
|
width 23.
|
|
if (((per.l(ad:0x40300000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTB_CTRL,Global CTB And Power Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DEEPSLEEP_ON ,DeepSleep mode" "Disabled,Enabled"
|
|
line.long 0x04 "OA_RES0_CTRL,Opamp0 And Resistor0 Control"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x04 31. " VALID_SEL0_EN ,Enable UAB valid selection" "Disabled,Enabled"
|
|
bitfld.long 0x04 28.--30. " VALID_SEL0 ,Select which UAB valid to use to sample the comparator output" "Valid 0,Valid 1,?..."
|
|
bitfld.long 0x04 24.--27. " C0_FB ,Feed back cap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 21. " RES0_TAP_OVR ,RES0 tap override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x04 20. " RES0_SWAP ,Swap top and bottom resistor value" "Not swapped,Swapped"
|
|
bitfld.long 0x04 16.--19. " RES0_TAP ,PGA gain" "1.0,1.42,2.0,2.78,4.0,5.82,8.0,5.82,8.0,10.67,16.0,21.33,32.0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " OA0_PUMP_EN ,Opamp0 pump enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--9. " OA0_COMPINT ,Opamp0 comparator edge detect for output and interrupt" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OA0_DSI_LEVEL ,Opamp0 comparator output" "Pulse,Level"
|
|
bitfld.long 0x04 6. " OA0_DSI_BYPASS ,Opamp0 bypass comparator output synchronization" "Synchronized,Bypassed"
|
|
bitfld.long 0x04 5. " OA0_HYST_EN ,Opamp0 hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " OA0_COMP_EN ,Opamp0 comparator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " OA0_DRIVE_STR_SEL ,Opamp0 output strength select" "1x,10x"
|
|
bitfld.long 0x04 0.--1. " OA0_PWR_MODE ,Opamp0 power level" "OFF,Low Power,Medium Power,High Power"
|
|
line.long 0x08 "OA_RES1_CTRL,Opamp1 And Resistor1 Control"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x08 31. " VALID_SEL1_EN ,Enable UAB valid selection" "Disabled,Enabled"
|
|
bitfld.long 0x08 28.--30. " VALID_SEL1 ,Select which UAB valid to use to sample the comparator output" "Valid 0,Valid 1,?..."
|
|
bitfld.long 0x08 24.--27. " C1_FB ,Feed back cap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 21. " RES1_TAP_OVR ,RES1 tap override" "Not override,Override"
|
|
textline " "
|
|
bitfld.long 0x08 20. " RES1_SWAP ,Swap top and bottom resistor value" "Not swapped,Swapped"
|
|
bitfld.long 0x08 16.--19. " RES1_TAP ,PGA gain" "1.0,1.42,2.0,2.78,4.0,5.82,8.0,5.82,8.0,10.67,16.0,21.33,32.0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 11. " OA1_PUMP_EN ,Opamp1 pump enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8.--9. " OA1_COMPINT ,Opamp1 comparator edge detect for output and interrupt" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x08 7. " OA1_DSI_LEVEL ,Opamp1 comparator output" "Pulse,Level"
|
|
bitfld.long 0x08 6. " OA1_DSI_BYPASS ,Opamp1 bypass comparator output synchronization" "Synchronize,Bypass"
|
|
bitfld.long 0x08 5. " OA1_HYST_EN ,Opamp1 hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " OA1_COMP_EN ,Opamp1 comparator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " OA1_DRIVE_STR_SEL ,Opamp1 output strength select" "1x,10x"
|
|
bitfld.long 0x08 0.--1. " OA1_PWR_MODE ,Opamp1 power level" "OFF,Low power,Medium power,High power"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "COMP_STAT,Comparator Status"
|
|
bitfld.long 0x00 16. " OA1_COMP ,Opamp1 current comparator status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OA0_COMP ,Opamp0 current comparator status" "Disabled,Enabled"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " COMP1 ,Comparator 1 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " COMP0 ,Comparator 0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,Interrupt Request Set Register"
|
|
bitfld.long 0x04 1. " COMP1_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " COMP0_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,Interrupt Request Mask"
|
|
bitfld.long 0x08 1. " COMP1_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " COMP0_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt Request Masked"
|
|
bitfld.long 0x00 1. " COMP1_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " COMP0_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DFT_CTRL,Risk Mitigation Bits"
|
|
bitfld.long 0x00 31. " DFT_EN ,Risk mitigation bit 3" "0,1"
|
|
bitfld.long 0x00 0.--2. " DFT_MODE ,Risk mitigation bits 0-2" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x80++0x17
|
|
line.long 0x00 "OA0_SW,Opamp0 Switch Control"
|
|
bitfld.long 0x00 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OA0O_D51 ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 14. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x04 "OA0_SW_CLEAR,Opamp0 Switch Control Clear"
|
|
eventfld.long 0x04 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 18. " OA0O_D51 ,Opamp0 output to sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 14. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x04 8. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
line.long 0x08 "OA1_SW,Opamp1 Switch Control"
|
|
bitfld.long 0x08 21. " OA1O_D82 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OA1O_D62 ,Opamp0 output to sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 18. " OA1O_D52 ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 14. " OA1M_A82 ,Opamp1 negative terminal to opamp1 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 8. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus01" "Not switched,Switched"
|
|
bitfld.long 0x08 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not switched,Switched"
|
|
bitfld.long 0x08 0. " OA1P_A03 ,Opamp1 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x0C "OA1_SW_CLEAR,Opamp1 Switch Control Clear"
|
|
eventfld.long 0x0C 21. " OA1O_D82 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " OA1O_D62 ,Opamp0 output to sarbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 18. " OA1O_D52 ,Opamp0 output to sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 14. " OA1M_A82 ,Opamp1 negative terminal to opamp1 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 8. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus01" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 0. " OA1P_A03 ,Opamp1 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTB_SW_HW_CTRL,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 3. " P3_HW_CTRL ,Pin P3 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " P2_HW_CTRL ,Pin P2 switches" "Not switched,Switched"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CTB_SW_STATUS,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp0 output to sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
group.long 0xF00++0x17
|
|
line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x00 0.--5. " OA0_OFFSET_TRIM ,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "OA0_SLOPE_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x04 0.--5. " OA0_SLOPE_OFFSET_TRIM ,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "OA0_COMP_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x08 0.--1. " OA0_COMP_TRIM ,Opamp0 compenation capacitor trim" "0,1,2,3"
|
|
line.long 0x0C "OA1_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x0C 0.--5. " OA1_OFFSET_TRIM ,Opamp1 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "OA1_SLOPE_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x10 0.--5. " OA1_SLOPE_OFFSET_TRIM ,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "OA1_COMP_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x14 0.--1. " OA1_COMP_TRIM ,Opamp1 compenation capacitor trim" "0,1,2,3"
|
|
else
|
|
group.long 0x80++0x17
|
|
line.long 0x00 "OA0_SW,Opamp0 Switch Control"
|
|
bitfld.long 0x00 30. " RES0_R81 ,Resistor0 tap to opamp0 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " RES0_R71 ,Resistor0 tap to opamp0 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " RES0_R61 ,Resistor0 bottom to VSSA" "Not switched,Switched"
|
|
bitfld.long 0x00 27. " RES0_R41 ,Resistor0 bottom to opamp1 negative terminal" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RES0_R31 ,Resistor0 bottom to opamp0 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 25. " RES0_R11 ,Resistor0 bottom to opamp1 output" "Not switched,Switched"
|
|
bitfld.long 0x00 24. " RES0_R01 ,Resistor0 bottom to pin P1" "Not switched,Switched"
|
|
bitfld.long 0x00 23. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " OA0O_D71 ,Opamp0 output to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 21. " OA0O_D51 ,Opamp0 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 20. " OA0O_D31 ,Opamp0 output to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 19. " OA0M_A91 ,Opamp0 negative terminal to pin P2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x00 17. " OA0M_A71 ,Opamp0 negative terminal to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " OA0M_A61 ,Opamp0 negative terminal to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " OA0M_A51 ,Opamp0 negative terminal to ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OA0M_A41 ,Opamp0 negative terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 13. " OA0M_A31 ,Opamp0 negative terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not switched,Switched"
|
|
bitfld.long 0x00 9. " OA0P_A90 ,Opamp0 positive terminal to uabin1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OA0P_A80 ,Opamp0 positive terminal to uabin0" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " OA0P_A70 ,Opamp0 positive terminal to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 6. " OA0P_A60 ,Opamp0 positive terminal to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 5. " OA0P_A50 ,Opamp0 positive terminal to ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OA0P_A40 ,Opamp0 positive terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not switched,Switched"
|
|
bitfld.long 0x00 1. " OA0P_A10 ,Opamp0 positive terminal to pin P1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x04 "OA0_SW_CLEAR,Opamp0 Switch Control Clear"
|
|
eventfld.long 0x04 30. " RES0_R81 ,Resistor0 tap to opamp0 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 29. " RES0_R71 ,Resistor0 tap to opamp0 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 28. " RES0_R61 ,Resistor0 bottom to VSSA" "Not cleared,Cleared"
|
|
eventfld.long 0x04 27. " RES0_R41 ,Resistor0 bottom to opamp1 negative terminal" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 26. " RES0_R31 ,Resistor0 bottom to opamp0 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 25. " RES0_R11 ,Resistor0 bottom to opamp1 output" "Not cleared,Cleared"
|
|
eventfld.long 0x04 24. " RES0_R01 ,Resistor0 bottom to pin P1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 23. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 22. " OA0O_D71 ,Opamp0 output to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 21. " OA0O_D51 ,Opamp0 output to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x04 20. " OA0O_D31 ,Opamp0 output to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 19. " OA0M_A91 ,Opamp0 negative terminal to pin P2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 18. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x04 17. " OA0M_A71 ,Opamp0 negative terminal to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 16. " OA0M_A61 ,Opamp0 negative terminal to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x04 15. " OA0M_A51 ,Opamp0 negative terminal to ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 14. " OA0M_A41 ,Opamp0 negative terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 13. " OA0M_A31 ,Opamp0 negative terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 11. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 9. " OA0P_A90 ,Opamp0 positive terminal to uabin1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 8. " OA0P_A80 ,Opamp0 positive terminal to uabin0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 7. " OA0P_A70 ,Opamp0 positive terminal to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 6. " OA0P_A60 ,Opamp0 positive terminal to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x04 5. " OA0P_A50 ,Opamp0 positive terminal to ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 4. " OA0P_A40 ,Opamp0 positive terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 1. " OA0P_A10 ,Opamp0 positive terminal to pin P1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
line.long 0x08 "OA1_SW,Opamp1 Switch Control"
|
|
bitfld.long 0x08 31. " RES1_R92 ,Resistor1 tap to opamp0 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 30. " RES1_R82 ,Resistor1 tap to opamp1 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 29. " RES1_R72 ,Resistor1 tap to opamp1 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 28. " RES1_R62 ,Resistor1 bottom to VSSA" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 27. " RES1_R52 ,Resistor1 bottom to resistor0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 26. " RES1_R32 ,Resistor1 bottom to opamp1 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 25. " RES1_R02 ,Resistor1 bottom to pin P4" "Not switched,Switched"
|
|
bitfld.long 0x08 24. " OA10_D82 ,Opamp1 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OA1O_D72 ,Opamp1 output to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 22. " OA1O_D62 ,Opamp1 output to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x08 21. " OA1O_D52 ,Opamp1 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 20. " OA1O_D42 ,Opamp1 output to ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OA1M_A92 ,Opamp1 negative terminal to pin P3" "Not switched,Switched"
|
|
bitfld.long 0x08 18. " OA1M_A82 ,Opamp1 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 17. " OA1M_A72 ,Opamp1 negative terminal to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 16. " OA1M_A62 ,Opamp1 negative terminal to ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OA1M_A52 ,Opamp1 negative terminal to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 14. " OA1M_A42 ,Opamp1 negative terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 13. " OA1M_A32 ,Opamp1 negative terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 12. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OA1P_A93 ,Opamp1 positive terminal to uabin1" "Not switched,Switched"
|
|
bitfld.long 0x08 8. " OA1P_A83 ,Opamp1 positive terminal to uabin0" "Not switched,Switched"
|
|
bitfld.long 0x08 7. " OA1P_A73 ,Opamp1 positive terminal to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 6. " OA1P_A63 ,Opamp1 positive terminal to ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OA1P_A53 ,Opamp1 positive terminal to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 3. " OA1P_A33 ,Opamp1 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 2. " OA1P_A23 ,Opamp1 positive terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not switched,Switched"
|
|
bitfld.long 0x08 0. " OA1P_A03 ,Opamp positive terminal to amuxbusb" "Not switched,Switched"
|
|
line.long 0x0C "OA1_SW_CLEAR,Opamp1 Switch Control Clear"
|
|
eventfld.long 0x0C 31. " RES1_R92 ,Resistor1 tap to opamp0 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 30. " RES1_R82 ,Resistor1 tap to opamp1 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 29. " RES1_R72 ,Resistor1 tap to opamp1 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 28. " RES1_R62 ,Resistor1 bottom to VSSA" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 27. " RES1_R52 ,Resistor1 bottom to resistor0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 26. " RES1_R32 ,Resistor1 bottom to opamp1 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 25. " RES1_R02 ,Resistor1 bottom to pin P4" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 24. " OA10_D82 ,Opamp1 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 23. " OA1O_D72 ,Opamp1 output to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 22. " OA1O_D62 ,Opamp1 output to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 21. " OA1O_D52 ,Opamp1 output to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 20. " OA1O_D42 ,Opamp1 output to ctbbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " OA1M_A92 ,Opamp1 negative terminal to pin P3" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 18. " OA1M_A82 ,Opamp1 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 17. " OA1M_A72 ,Opamp1 negative terminal to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 16. " OA1M_A62 ,Opamp1 negative terminal to ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 15. " OA1M_A52 ,Opamp1 negative terminal to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 14. " OA1M_A42 ,Opamp1 negative terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 13. " OA1M_A32 ,Opamp1 negative terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 12. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 9. " OA1P_A93 ,Opamp1 positive terminal to uabin1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 8. " OA1P_A83 ,Opamp1 positive terminal to uabin0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 7. " OA1P_A73 ,Opamp1 positive terminal to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 6. " OA1P_A63 ,Opamp1 positive terminal to ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 5. " OA1P_A53 ,Opamp1 positive terminal to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 3. " OA1P_A33 ,Opamp1 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 2. " OA1P_A23 ,Opamp1 positive terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 0. " OA1P_A03 ,Opamp positive terminal to amuxbusb" "Not cleared,Cleared"
|
|
line.long 0x10 "CTBBUS_SW,CTB Bus Switch Control"
|
|
bitfld.long 0x10 28. " CB2_G50 ,Ctbbus2 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 27. " CB3_G61 ,Ctbbus3 sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 26. " CB2_G52 ,Ctbbus2 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 25. " CB1_G41 ,Ctbbus1 sarbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 24. " CB0_G32 ,Ctbbus0 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 23. " CB3_G63 ,Ctbbus3 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 22. " CB2_G53 ,Ctbbus2 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 21. " CB1_G43 ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 20. " CB0_G33 ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 19. " CB3_P37 ,P7 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 18. " CB3_P35 ,P5 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 17. " CB3_P33 ,P3 ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 16. " CB3_P31 ,P1 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 15. " CB2_P26 ,P6 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 14. " CB2_P24 ,P4 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 13. " CB2_P22 ,P2 ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 12. " CB2_P20 ,P0 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 11. " CB1_P17 ,P7 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 10. " CB1_P15 ,P5 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 9. " CB1_P13 ,P3 ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 8. " CB1_P11 ,P1 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 7. " CB0_P07 ,P7 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 6. " CB0_P06 ,P6 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 5. " CB0_P05 ,P5 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 4. " CB0_P04 ,P4 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 3. " CB0_P03 ,P3 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 2. " CB0_P02 ,P2 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 1. " CB0_P01 ,P1 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CB0_P00 ,P0 ctbbus0" "Not switched,Switched"
|
|
line.long 0x14 "CTBBUS_SW_CLEAR,CTB Bus Switch Control Clear"
|
|
eventfld.long 0x14 28. " CB2_G50 ,Ctbbus2 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 27. " CB3_G61 ,Ctbbus3 sarbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 26. " CB2_G52 ,Ctbbus2 sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 25. " CB1_G41 ,Ctbbus1 sarbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 24. " CB0_G32 ,Ctbbus0 sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 23. " CB3_G63 ,Ctbbus3 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 22. " CB2_G53 ,Ctbbus2 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 21. " CB1_G43 ,Ctbbus1 right neighbor" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 20. " CB0_G33 ,Ctbbus1 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 19. " CB3_P37 ,P7 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 18. " CB3_P35 ,P5 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 17. " CB3_P33 ,P3 ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 16. " CB3_P31 ,P1 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 15. " CB2_P26 ,P6 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 14. " CB2_P24 ,P4 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 13. " CB2_P22 ,P2 ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 12. " CB2_P20 ,P0 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 11. " CB1_P17 ,P7 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 10. " CB1_P15 ,P5 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 9. " CB1_P13 ,P3 ctbbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 8. " CB1_P11 ,P1 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 7. " CB0_P07 ,P7 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 6. " CB0_P06 ,P6 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 5. " CB0_P05 ,P5 ctbbus0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 4. " CB0_P04 ,P4 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 3. " CB0_P03 ,P3 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 2. " CB0_P02 ,P2 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 1. " CB0_P01 ,P1 ctbbus0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 0. " CB0_P00 ,P0 ctbbus0" "Not cleared,Cleared"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTB_SW_HW_CTRL,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 17. " SARBUS1_HW_CTRL ,Sarbus1 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " SARBUS0_HW_CTRL ,Sarbus0 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " P7_HW_CTRL23 ,For P37" "Not switched,Switched"
|
|
bitfld.long 0x00 14. " P6_HW_CTRL23 ,For P26" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P5_HW_CTRL23 ,For P35" "Not switched,Switched"
|
|
bitfld.long 0x00 12. " P4_HW_CTRL23 ,For P24" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " P3_HW_CTRL23 ,For P33 D52 D62" "Not switched,Switched"
|
|
bitfld.long 0x00 10. " P2_HW_CTRL23 ,For P22 D51" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P1_HW_CTRL23 ,For P31" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " P0_HW_CTRL23 ,For P20" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " P7_HW_CTRL01 ,For P07 P17" "Not switched,Switched"
|
|
bitfld.long 0x00 6. " P6_HW_CTRL01 ,For P06" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5_HW_CTRL01 ,For P05 P15" "Not switched,Switched"
|
|
bitfld.long 0x00 4. " P4_HW_CTRL01 ,For P04" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " P3_HW_CTRL01 ,For P03 P13" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " P2_HW_CTRL01 ,For P02" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1_HW_CTRL01 ,For P01 P11" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " P0_HW_CTRL01 ,For P00" "Not switched,Switched"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CTB_SW_STATUS,CTB Switch Control Status"
|
|
bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp1 output to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp1 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 27. " CB3_G61_STAT ,Ctbbus3 sarbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CB2_G52_STAT ,Ctbbus2 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 25. " CB1_G41_STAT ,Ctbbus1 sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 24. " CB0_G32_STAT ,Ctbbus0 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 23. " CB3_G63_STAT ,Ctbbus3 right neighbor" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CB2_G53_STAT ,Ctbbus2 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 21. " CB1_G43_STAT ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 20. " CB0_G33_STAT ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 19. " CB3_P37_STAT ,P7 ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CB3_P35_STAT ,P5 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 17. " CB3_P33_STAT ,P3 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " CB3_P31_STAT ,P1 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " CB2_P26_STAT ,P6 ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CB2_P24_STAT ,P4 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 13. " CB2_P22_STAT ,P2 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 12. " CB2_P20_STAT ,P0 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " CB1_P17_STAT ,P7 ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CB1_P15_STAT ,P5 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 9. " CB1_P13_STAT ,P3 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " CB1_P11_STAT ,P1 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " CB0_P07_STAT ,P7 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CB0_P06_STAT ,P6 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 5. " CB0_P05_STAT ,P5 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 4. " CB0_P04_STAT ,P4 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " CB0_P03_STAT ,P3 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CB0_P02_STAT ,P2 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 1. " CB0_P01_STAT ,P1 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " CB0_P00_STAT ,P0 ctbbus0" "Not switched,Switched"
|
|
group.long 0xF00++0x1B
|
|
line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x00 0.--5. " OA0_OFFSET_TRIM ,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "OA0_SLOPE_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x04 0.--5. " OA0_SLOPE_OFFSET_T ,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "OA0_COMP_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x08 0.--1. " OA0_COMP_TRIM ,Opamp0 compensation capacitor trim" "0,1,2,3"
|
|
line.long 0x0C "OA1_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x0C 0.--5. " OA1_OFFSET_TRIM ,Opamp1 offs et trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "OA1_SLOPE_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x10 0.--5. " OA1_SLOPE_OFFSET_T ,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "OA1_COMP_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x14 0.--1. " OA1_COMP_TRIM ,Opamp1 compensation capacitor trim" "0,1,2,3"
|
|
line.long 0x18 "RMP_TRIM,Risk Mitigation Bits"
|
|
bitfld.long 0x18 0.--3. " RMP_TRIM ,Risk mitigation trim bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTB_CTRL,Global CTB And Power Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif cpuis("CY8C42*-BL*")
|
|
tree.open "CTBM (Continuous Time Block Mini)"
|
|
tree "CTBM0"
|
|
base ad:0x40300000
|
|
width 23.
|
|
if (((per.l(ad:0x40300000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTB_CTRL,Global CTB And Power Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DEEPSLEEP_ON ,DeepSleep mode" "Disabled,Enabled"
|
|
line.long 0x04 "OA_RES0_CTRL,Opamp0 And Resistor0 Control"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x04 31. " VALID_SEL0_EN ,Enable UAB valid selection" "Disabled,Enabled"
|
|
bitfld.long 0x04 28.--30. " VALID_SEL0 ,Select which UAB valid to use to sample the comparator output" "Valid 0,Valid 1,?..."
|
|
bitfld.long 0x04 24.--27. " C0_FB ,Feed back cap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 21. " RES0_TAP_OVR ,RES0 tap override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x04 20. " RES0_SWAP ,Swap top and bottom resistor value" "Not swapped,Swapped"
|
|
bitfld.long 0x04 16.--19. " RES0_TAP ,PGA gain" "1.0,1.42,2.0,2.78,4.0,5.82,8.0,5.82,8.0,10.67,16.0,21.33,32.0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " OA0_PUMP_EN ,Opamp0 pump enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--9. " OA0_COMPINT ,Opamp0 comparator edge detect for output and interrupt" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OA0_DSI_LEVEL ,Opamp0 comparator output" "Pulse,Level"
|
|
bitfld.long 0x04 6. " OA0_DSI_BYPASS ,Opamp0 bypass comparator output synchronization" "Synchronized,Bypassed"
|
|
bitfld.long 0x04 5. " OA0_HYST_EN ,Opamp0 hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " OA0_COMP_EN ,Opamp0 comparator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " OA0_DRIVE_STR_SEL ,Opamp0 output strength select" "1x,10x"
|
|
bitfld.long 0x04 0.--1. " OA0_PWR_MODE ,Opamp0 power level" "OFF,Low Power,Medium Power,High Power"
|
|
line.long 0x08 "OA_RES1_CTRL,Opamp1 And Resistor1 Control"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x08 31. " VALID_SEL1_EN ,Enable UAB valid selection" "Disabled,Enabled"
|
|
bitfld.long 0x08 28.--30. " VALID_SEL1 ,Select which UAB valid to use to sample the comparator output" "Valid 0,Valid 1,?..."
|
|
bitfld.long 0x08 24.--27. " C1_FB ,Feed back cap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 21. " RES1_TAP_OVR ,RES1 tap override" "Not override,Override"
|
|
textline " "
|
|
bitfld.long 0x08 20. " RES1_SWAP ,Swap top and bottom resistor value" "Not swapped,Swapped"
|
|
bitfld.long 0x08 16.--19. " RES1_TAP ,PGA gain" "1.0,1.42,2.0,2.78,4.0,5.82,8.0,5.82,8.0,10.67,16.0,21.33,32.0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 11. " OA1_PUMP_EN ,Opamp1 pump enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8.--9. " OA1_COMPINT ,Opamp1 comparator edge detect for output and interrupt" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x08 7. " OA1_DSI_LEVEL ,Opamp1 comparator output" "Pulse,Level"
|
|
bitfld.long 0x08 6. " OA1_DSI_BYPASS ,Opamp1 bypass comparator output synchronization" "Synchronize,Bypass"
|
|
bitfld.long 0x08 5. " OA1_HYST_EN ,Opamp1 hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " OA1_COMP_EN ,Opamp1 comparator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " OA1_DRIVE_STR_SEL ,Opamp1 output strength select" "1x,10x"
|
|
bitfld.long 0x08 0.--1. " OA1_PWR_MODE ,Opamp1 power level" "OFF,Low power,Medium power,High power"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "COMP_STAT,Comparator Status"
|
|
bitfld.long 0x00 16. " OA1_COMP ,Opamp1 current comparator status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OA0_COMP ,Opamp0 current comparator status" "Disabled,Enabled"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " COMP1 ,Comparator 1 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " COMP0 ,Comparator 0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,Interrupt Request Set Register"
|
|
bitfld.long 0x04 1. " COMP1_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " COMP0_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,Interrupt Request Mask"
|
|
bitfld.long 0x08 1. " COMP1_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " COMP0_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt Request Masked"
|
|
bitfld.long 0x00 1. " COMP1_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " COMP0_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DFT_CTRL,Risk Mitigation Bits"
|
|
bitfld.long 0x00 31. " DFT_EN ,Risk mitigation bit 3" "0,1"
|
|
bitfld.long 0x00 0.--2. " DFT_MODE ,Risk mitigation bits 0-2" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x80++0x17
|
|
line.long 0x00 "OA0_SW,Opamp0 Switch Control"
|
|
bitfld.long 0x00 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OA0O_D51 ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 14. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x04 "OA0_SW_CLEAR,Opamp0 Switch Control Clear"
|
|
eventfld.long 0x04 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 18. " OA0O_D51 ,Opamp0 output to sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 14. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x04 8. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
line.long 0x08 "OA1_SW,Opamp1 Switch Control"
|
|
bitfld.long 0x08 21. " OA1O_D82 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OA1O_D62 ,Opamp0 output to sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 18. " OA1O_D52 ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 14. " OA1M_A82 ,Opamp1 negative terminal to opamp1 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 8. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus01" "Not switched,Switched"
|
|
bitfld.long 0x08 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not switched,Switched"
|
|
bitfld.long 0x08 0. " OA1P_A03 ,Opamp1 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x0C "OA1_SW_CLEAR,Opamp1 Switch Control Clear"
|
|
eventfld.long 0x0C 21. " OA1O_D82 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " OA1O_D62 ,Opamp0 output to sarbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 18. " OA1O_D52 ,Opamp0 output to sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 14. " OA1M_A82 ,Opamp1 negative terminal to opamp1 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 8. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus01" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 0. " OA1P_A03 ,Opamp1 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTB_SW_HW_CTRL,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 3. " P3_HW_CTRL ,Pin P3 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " P2_HW_CTRL ,Pin P2 switches" "Not switched,Switched"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CTB_SW_STATUS,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp0 output to sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
group.long 0xF00++0x17
|
|
line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x00 0.--5. " OA0_OFFSET_TRIM ,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "OA0_SLOPE_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x04 0.--5. " OA0_SLOPE_OFFSET_TRIM ,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "OA0_COMP_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x08 0.--1. " OA0_COMP_TRIM ,Opamp0 compenation capacitor trim" "0,1,2,3"
|
|
line.long 0x0C "OA1_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x0C 0.--5. " OA1_OFFSET_TRIM ,Opamp1 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "OA1_SLOPE_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x10 0.--5. " OA1_SLOPE_OFFSET_TRIM ,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "OA1_COMP_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x14 0.--1. " OA1_COMP_TRIM ,Opamp1 compenation capacitor trim" "0,1,2,3"
|
|
else
|
|
group.long 0x80++0x17
|
|
line.long 0x00 "OA0_SW,Opamp0 Switch Control"
|
|
bitfld.long 0x00 30. " RES0_R81 ,Resistor0 tap to opamp0 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " RES0_R71 ,Resistor0 tap to opamp0 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " RES0_R61 ,Resistor0 bottom to VSSA" "Not switched,Switched"
|
|
bitfld.long 0x00 27. " RES0_R41 ,Resistor0 bottom to opamp1 negative terminal" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RES0_R31 ,Resistor0 bottom to opamp0 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 25. " RES0_R11 ,Resistor0 bottom to opamp1 output" "Not switched,Switched"
|
|
bitfld.long 0x00 24. " RES0_R01 ,Resistor0 bottom to pin P1" "Not switched,Switched"
|
|
bitfld.long 0x00 23. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " OA0O_D71 ,Opamp0 output to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 21. " OA0O_D51 ,Opamp0 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 20. " OA0O_D31 ,Opamp0 output to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 19. " OA0M_A91 ,Opamp0 negative terminal to pin P2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x00 17. " OA0M_A71 ,Opamp0 negative terminal to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " OA0M_A61 ,Opamp0 negative terminal to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " OA0M_A51 ,Opamp0 negative terminal to ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OA0M_A41 ,Opamp0 negative terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 13. " OA0M_A31 ,Opamp0 negative terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not switched,Switched"
|
|
bitfld.long 0x00 9. " OA0P_A90 ,Opamp0 positive terminal to uabin1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OA0P_A80 ,Opamp0 positive terminal to uabin0" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " OA0P_A70 ,Opamp0 positive terminal to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 6. " OA0P_A60 ,Opamp0 positive terminal to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 5. " OA0P_A50 ,Opamp0 positive terminal to ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OA0P_A40 ,Opamp0 positive terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not switched,Switched"
|
|
bitfld.long 0x00 1. " OA0P_A10 ,Opamp0 positive terminal to pin P1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x04 "OA0_SW_CLEAR,Opamp0 Switch Control Clear"
|
|
eventfld.long 0x04 30. " RES0_R81 ,Resistor0 tap to opamp0 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 29. " RES0_R71 ,Resistor0 tap to opamp0 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 28. " RES0_R61 ,Resistor0 bottom to VSSA" "Not cleared,Cleared"
|
|
eventfld.long 0x04 27. " RES0_R41 ,Resistor0 bottom to opamp1 negative terminal" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 26. " RES0_R31 ,Resistor0 bottom to opamp0 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 25. " RES0_R11 ,Resistor0 bottom to opamp1 output" "Not cleared,Cleared"
|
|
eventfld.long 0x04 24. " RES0_R01 ,Resistor0 bottom to pin P1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 23. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 22. " OA0O_D71 ,Opamp0 output to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 21. " OA0O_D51 ,Opamp0 output to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x04 20. " OA0O_D31 ,Opamp0 output to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 19. " OA0M_A91 ,Opamp0 negative terminal to pin P2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 18. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x04 17. " OA0M_A71 ,Opamp0 negative terminal to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 16. " OA0M_A61 ,Opamp0 negative terminal to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x04 15. " OA0M_A51 ,Opamp0 negative terminal to ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 14. " OA0M_A41 ,Opamp0 negative terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 13. " OA0M_A31 ,Opamp0 negative terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 11. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 9. " OA0P_A90 ,Opamp0 positive terminal to uabin1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 8. " OA0P_A80 ,Opamp0 positive terminal to uabin0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 7. " OA0P_A70 ,Opamp0 positive terminal to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 6. " OA0P_A60 ,Opamp0 positive terminal to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x04 5. " OA0P_A50 ,Opamp0 positive terminal to ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 4. " OA0P_A40 ,Opamp0 positive terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 1. " OA0P_A10 ,Opamp0 positive terminal to pin P1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
line.long 0x08 "OA1_SW,Opamp1 Switch Control"
|
|
bitfld.long 0x08 31. " RES1_R92 ,Resistor1 tap to opamp0 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 30. " RES1_R82 ,Resistor1 tap to opamp1 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 29. " RES1_R72 ,Resistor1 tap to opamp1 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 28. " RES1_R62 ,Resistor1 bottom to VSSA" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 27. " RES1_R52 ,Resistor1 bottom to resistor0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 26. " RES1_R32 ,Resistor1 bottom to opamp1 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 25. " RES1_R02 ,Resistor1 bottom to pin P4" "Not switched,Switched"
|
|
bitfld.long 0x08 24. " OA10_D82 ,Opamp1 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OA1O_D72 ,Opamp1 output to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 22. " OA1O_D62 ,Opamp1 output to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x08 21. " OA1O_D52 ,Opamp1 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 20. " OA1O_D42 ,Opamp1 output to ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OA1M_A92 ,Opamp1 negative terminal to pin P3" "Not switched,Switched"
|
|
bitfld.long 0x08 18. " OA1M_A82 ,Opamp1 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 17. " OA1M_A72 ,Opamp1 negative terminal to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 16. " OA1M_A62 ,Opamp1 negative terminal to ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OA1M_A52 ,Opamp1 negative terminal to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 14. " OA1M_A42 ,Opamp1 negative terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 13. " OA1M_A32 ,Opamp1 negative terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 12. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OA1P_A93 ,Opamp1 positive terminal to uabin1" "Not switched,Switched"
|
|
bitfld.long 0x08 8. " OA1P_A83 ,Opamp1 positive terminal to uabin0" "Not switched,Switched"
|
|
bitfld.long 0x08 7. " OA1P_A73 ,Opamp1 positive terminal to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 6. " OA1P_A63 ,Opamp1 positive terminal to ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OA1P_A53 ,Opamp1 positive terminal to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 3. " OA1P_A33 ,Opamp1 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 2. " OA1P_A23 ,Opamp1 positive terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not switched,Switched"
|
|
bitfld.long 0x08 0. " OA1P_A03 ,Opamp positive terminal to amuxbusb" "Not switched,Switched"
|
|
line.long 0x0C "OA1_SW_CLEAR,Opamp1 Switch Control Clear"
|
|
eventfld.long 0x0C 31. " RES1_R92 ,Resistor1 tap to opamp0 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 30. " RES1_R82 ,Resistor1 tap to opamp1 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 29. " RES1_R72 ,Resistor1 tap to opamp1 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 28. " RES1_R62 ,Resistor1 bottom to VSSA" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 27. " RES1_R52 ,Resistor1 bottom to resistor0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 26. " RES1_R32 ,Resistor1 bottom to opamp1 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 25. " RES1_R02 ,Resistor1 bottom to pin P4" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 24. " OA10_D82 ,Opamp1 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 23. " OA1O_D72 ,Opamp1 output to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 22. " OA1O_D62 ,Opamp1 output to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 21. " OA1O_D52 ,Opamp1 output to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 20. " OA1O_D42 ,Opamp1 output to ctbbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " OA1M_A92 ,Opamp1 negative terminal to pin P3" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 18. " OA1M_A82 ,Opamp1 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 17. " OA1M_A72 ,Opamp1 negative terminal to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 16. " OA1M_A62 ,Opamp1 negative terminal to ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 15. " OA1M_A52 ,Opamp1 negative terminal to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 14. " OA1M_A42 ,Opamp1 negative terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 13. " OA1M_A32 ,Opamp1 negative terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 12. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 9. " OA1P_A93 ,Opamp1 positive terminal to uabin1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 8. " OA1P_A83 ,Opamp1 positive terminal to uabin0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 7. " OA1P_A73 ,Opamp1 positive terminal to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 6. " OA1P_A63 ,Opamp1 positive terminal to ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 5. " OA1P_A53 ,Opamp1 positive terminal to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 3. " OA1P_A33 ,Opamp1 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 2. " OA1P_A23 ,Opamp1 positive terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 0. " OA1P_A03 ,Opamp positive terminal to amuxbusb" "Not cleared,Cleared"
|
|
line.long 0x10 "CTBBUS_SW,CTB Bus Switch Control"
|
|
bitfld.long 0x10 28. " CB2_G50 ,Ctbbus2 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 27. " CB3_G61 ,Ctbbus3 sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 26. " CB2_G52 ,Ctbbus2 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 25. " CB1_G41 ,Ctbbus1 sarbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 24. " CB0_G32 ,Ctbbus0 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 23. " CB3_G63 ,Ctbbus3 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 22. " CB2_G53 ,Ctbbus2 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 21. " CB1_G43 ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 20. " CB0_G33 ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 19. " CB3_P37 ,P7 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 18. " CB3_P35 ,P5 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 17. " CB3_P33 ,P3 ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 16. " CB3_P31 ,P1 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 15. " CB2_P26 ,P6 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 14. " CB2_P24 ,P4 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 13. " CB2_P22 ,P2 ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 12. " CB2_P20 ,P0 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 11. " CB1_P17 ,P7 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 10. " CB1_P15 ,P5 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 9. " CB1_P13 ,P3 ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 8. " CB1_P11 ,P1 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 7. " CB0_P07 ,P7 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 6. " CB0_P06 ,P6 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 5. " CB0_P05 ,P5 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 4. " CB0_P04 ,P4 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 3. " CB0_P03 ,P3 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 2. " CB0_P02 ,P2 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 1. " CB0_P01 ,P1 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CB0_P00 ,P0 ctbbus0" "Not switched,Switched"
|
|
line.long 0x14 "CTBBUS_SW_CLEAR,CTB Bus Switch Control Clear"
|
|
eventfld.long 0x14 28. " CB2_G50 ,Ctbbus2 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 27. " CB3_G61 ,Ctbbus3 sarbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 26. " CB2_G52 ,Ctbbus2 sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 25. " CB1_G41 ,Ctbbus1 sarbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 24. " CB0_G32 ,Ctbbus0 sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 23. " CB3_G63 ,Ctbbus3 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 22. " CB2_G53 ,Ctbbus2 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 21. " CB1_G43 ,Ctbbus1 right neighbor" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 20. " CB0_G33 ,Ctbbus1 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 19. " CB3_P37 ,P7 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 18. " CB3_P35 ,P5 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 17. " CB3_P33 ,P3 ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 16. " CB3_P31 ,P1 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 15. " CB2_P26 ,P6 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 14. " CB2_P24 ,P4 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 13. " CB2_P22 ,P2 ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 12. " CB2_P20 ,P0 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 11. " CB1_P17 ,P7 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 10. " CB1_P15 ,P5 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 9. " CB1_P13 ,P3 ctbbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 8. " CB1_P11 ,P1 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 7. " CB0_P07 ,P7 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 6. " CB0_P06 ,P6 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 5. " CB0_P05 ,P5 ctbbus0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 4. " CB0_P04 ,P4 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 3. " CB0_P03 ,P3 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 2. " CB0_P02 ,P2 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 1. " CB0_P01 ,P1 ctbbus0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 0. " CB0_P00 ,P0 ctbbus0" "Not cleared,Cleared"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTB_SW_HW_CTRL,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 17. " SARBUS1_HW_CTRL ,Sarbus1 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " SARBUS0_HW_CTRL ,Sarbus0 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " P7_HW_CTRL23 ,For P37" "Not switched,Switched"
|
|
bitfld.long 0x00 14. " P6_HW_CTRL23 ,For P26" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P5_HW_CTRL23 ,For P35" "Not switched,Switched"
|
|
bitfld.long 0x00 12. " P4_HW_CTRL23 ,For P24" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " P3_HW_CTRL23 ,For P33 D52 D62" "Not switched,Switched"
|
|
bitfld.long 0x00 10. " P2_HW_CTRL23 ,For P22 D51" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P1_HW_CTRL23 ,For P31" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " P0_HW_CTRL23 ,For P20" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " P7_HW_CTRL01 ,For P07 P17" "Not switched,Switched"
|
|
bitfld.long 0x00 6. " P6_HW_CTRL01 ,For P06" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5_HW_CTRL01 ,For P05 P15" "Not switched,Switched"
|
|
bitfld.long 0x00 4. " P4_HW_CTRL01 ,For P04" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " P3_HW_CTRL01 ,For P03 P13" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " P2_HW_CTRL01 ,For P02" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1_HW_CTRL01 ,For P01 P11" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " P0_HW_CTRL01 ,For P00" "Not switched,Switched"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CTB_SW_STATUS,CTB Switch Control Status"
|
|
bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp1 output to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp1 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 27. " CB3_G61_STAT ,Ctbbus3 sarbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CB2_G52_STAT ,Ctbbus2 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 25. " CB1_G41_STAT ,Ctbbus1 sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 24. " CB0_G32_STAT ,Ctbbus0 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 23. " CB3_G63_STAT ,Ctbbus3 right neighbor" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CB2_G53_STAT ,Ctbbus2 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 21. " CB1_G43_STAT ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 20. " CB0_G33_STAT ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 19. " CB3_P37_STAT ,P7 ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CB3_P35_STAT ,P5 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 17. " CB3_P33_STAT ,P3 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " CB3_P31_STAT ,P1 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " CB2_P26_STAT ,P6 ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CB2_P24_STAT ,P4 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 13. " CB2_P22_STAT ,P2 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 12. " CB2_P20_STAT ,P0 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " CB1_P17_STAT ,P7 ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CB1_P15_STAT ,P5 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 9. " CB1_P13_STAT ,P3 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " CB1_P11_STAT ,P1 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " CB0_P07_STAT ,P7 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CB0_P06_STAT ,P6 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 5. " CB0_P05_STAT ,P5 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 4. " CB0_P04_STAT ,P4 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " CB0_P03_STAT ,P3 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CB0_P02_STAT ,P2 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 1. " CB0_P01_STAT ,P1 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " CB0_P00_STAT ,P0 ctbbus0" "Not switched,Switched"
|
|
group.long 0xF00++0x1B
|
|
line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x00 0.--5. " OA0_OFFSET_TRIM ,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "OA0_SLOPE_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x04 0.--5. " OA0_SLOPE_OFFSET_T ,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "OA0_COMP_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x08 0.--1. " OA0_COMP_TRIM ,Opamp0 compensation capacitor trim" "0,1,2,3"
|
|
line.long 0x0C "OA1_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x0C 0.--5. " OA1_OFFSET_TRIM ,Opamp1 offs et trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "OA1_SLOPE_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x10 0.--5. " OA1_SLOPE_OFFSET_T ,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "OA1_COMP_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x14 0.--1. " OA1_COMP_TRIM ,Opamp1 compensation capacitor trim" "0,1,2,3"
|
|
line.long 0x18 "RMP_TRIM,Risk Mitigation Bits"
|
|
bitfld.long 0x18 0.--3. " RMP_TRIM ,Risk mitigation trim bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTB_CTRL,Global CTB And Power Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CTBM1"
|
|
base ad:0x40310000
|
|
width 23.
|
|
if (((per.l(ad:0x40310000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTB_CTRL,Global CTB And Power Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DEEPSLEEP_ON ,DeepSleep mode" "Disabled,Enabled"
|
|
line.long 0x04 "OA_RES0_CTRL,Opamp0 And Resistor0 Control"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x04 31. " VALID_SEL0_EN ,Enable UAB valid selection" "Disabled,Enabled"
|
|
bitfld.long 0x04 28.--30. " VALID_SEL0 ,Select which UAB valid to use to sample the comparator output" "Valid 0,Valid 1,?..."
|
|
bitfld.long 0x04 24.--27. " C0_FB ,Feed back cap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 21. " RES0_TAP_OVR ,RES0 tap override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x04 20. " RES0_SWAP ,Swap top and bottom resistor value" "Not swapped,Swapped"
|
|
bitfld.long 0x04 16.--19. " RES0_TAP ,PGA gain" "1.0,1.42,2.0,2.78,4.0,5.82,8.0,5.82,8.0,10.67,16.0,21.33,32.0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " OA0_PUMP_EN ,Opamp0 pump enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--9. " OA0_COMPINT ,Opamp0 comparator edge detect for output and interrupt" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OA0_DSI_LEVEL ,Opamp0 comparator output" "Pulse,Level"
|
|
bitfld.long 0x04 6. " OA0_DSI_BYPASS ,Opamp0 bypass comparator output synchronization" "Synchronized,Bypassed"
|
|
bitfld.long 0x04 5. " OA0_HYST_EN ,Opamp0 hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " OA0_COMP_EN ,Opamp0 comparator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " OA0_DRIVE_STR_SEL ,Opamp0 output strength select" "1x,10x"
|
|
bitfld.long 0x04 0.--1. " OA0_PWR_MODE ,Opamp0 power level" "OFF,Low Power,Medium Power,High Power"
|
|
line.long 0x08 "OA_RES1_CTRL,Opamp1 And Resistor1 Control"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x08 31. " VALID_SEL1_EN ,Enable UAB valid selection" "Disabled,Enabled"
|
|
bitfld.long 0x08 28.--30. " VALID_SEL1 ,Select which UAB valid to use to sample the comparator output" "Valid 0,Valid 1,?..."
|
|
bitfld.long 0x08 24.--27. " C1_FB ,Feed back cap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 21. " RES1_TAP_OVR ,RES1 tap override" "Not override,Override"
|
|
textline " "
|
|
bitfld.long 0x08 20. " RES1_SWAP ,Swap top and bottom resistor value" "Not swapped,Swapped"
|
|
bitfld.long 0x08 16.--19. " RES1_TAP ,PGA gain" "1.0,1.42,2.0,2.78,4.0,5.82,8.0,5.82,8.0,10.67,16.0,21.33,32.0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 11. " OA1_PUMP_EN ,Opamp1 pump enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8.--9. " OA1_COMPINT ,Opamp1 comparator edge detect for output and interrupt" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x08 7. " OA1_DSI_LEVEL ,Opamp1 comparator output" "Pulse,Level"
|
|
bitfld.long 0x08 6. " OA1_DSI_BYPASS ,Opamp1 bypass comparator output synchronization" "Synchronize,Bypass"
|
|
bitfld.long 0x08 5. " OA1_HYST_EN ,Opamp1 hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " OA1_COMP_EN ,Opamp1 comparator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " OA1_DRIVE_STR_SEL ,Opamp1 output strength select" "1x,10x"
|
|
bitfld.long 0x08 0.--1. " OA1_PWR_MODE ,Opamp1 power level" "OFF,Low power,Medium power,High power"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "COMP_STAT,Comparator Status"
|
|
bitfld.long 0x00 16. " OA1_COMP ,Opamp1 current comparator status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OA0_COMP ,Opamp0 current comparator status" "Disabled,Enabled"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " COMP1 ,Comparator 1 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " COMP0 ,Comparator 0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,Interrupt Request Set Register"
|
|
bitfld.long 0x04 1. " COMP1_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " COMP0_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,Interrupt Request Mask"
|
|
bitfld.long 0x08 1. " COMP1_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " COMP0_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt Request Masked"
|
|
bitfld.long 0x00 1. " COMP1_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " COMP0_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DFT_CTRL,Risk Mitigation Bits"
|
|
bitfld.long 0x00 31. " DFT_EN ,Risk mitigation bit 3" "0,1"
|
|
bitfld.long 0x00 0.--2. " DFT_MODE ,Risk mitigation bits 0-2" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x80++0x17
|
|
line.long 0x00 "OA0_SW,Opamp0 Switch Control"
|
|
bitfld.long 0x00 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OA0O_D51 ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 14. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x04 "OA0_SW_CLEAR,Opamp0 Switch Control Clear"
|
|
eventfld.long 0x04 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 18. " OA0O_D51 ,Opamp0 output to sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 14. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x04 8. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
line.long 0x08 "OA1_SW,Opamp1 Switch Control"
|
|
bitfld.long 0x08 21. " OA1O_D82 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OA1O_D62 ,Opamp0 output to sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 18. " OA1O_D52 ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 14. " OA1M_A82 ,Opamp1 negative terminal to opamp1 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 8. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus01" "Not switched,Switched"
|
|
bitfld.long 0x08 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not switched,Switched"
|
|
bitfld.long 0x08 0. " OA1P_A03 ,Opamp1 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x0C "OA1_SW_CLEAR,Opamp1 Switch Control Clear"
|
|
eventfld.long 0x0C 21. " OA1O_D82 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " OA1O_D62 ,Opamp0 output to sarbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 18. " OA1O_D52 ,Opamp0 output to sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 14. " OA1M_A82 ,Opamp1 negative terminal to opamp1 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 8. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus01" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 0. " OA1P_A03 ,Opamp1 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTB_SW_HW_CTRL,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 3. " P3_HW_CTRL ,Pin P3 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " P2_HW_CTRL ,Pin P2 switches" "Not switched,Switched"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CTB_SW_STATUS,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp0 output to sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
group.long 0xF00++0x17
|
|
line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x00 0.--5. " OA0_OFFSET_TRIM ,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "OA0_SLOPE_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x04 0.--5. " OA0_SLOPE_OFFSET_TRIM ,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "OA0_COMP_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x08 0.--1. " OA0_COMP_TRIM ,Opamp0 compenation capacitor trim" "0,1,2,3"
|
|
line.long 0x0C "OA1_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x0C 0.--5. " OA1_OFFSET_TRIM ,Opamp1 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "OA1_SLOPE_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x10 0.--5. " OA1_SLOPE_OFFSET_TRIM ,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "OA1_COMP_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x14 0.--1. " OA1_COMP_TRIM ,Opamp1 compenation capacitor trim" "0,1,2,3"
|
|
else
|
|
group.long 0x80++0x17
|
|
line.long 0x00 "OA0_SW,Opamp0 Switch Control"
|
|
bitfld.long 0x00 30. " RES0_R81 ,Resistor0 tap to opamp0 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " RES0_R71 ,Resistor0 tap to opamp0 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " RES0_R61 ,Resistor0 bottom to VSSA" "Not switched,Switched"
|
|
bitfld.long 0x00 27. " RES0_R41 ,Resistor0 bottom to opamp1 negative terminal" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RES0_R31 ,Resistor0 bottom to opamp0 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 25. " RES0_R11 ,Resistor0 bottom to opamp1 output" "Not switched,Switched"
|
|
bitfld.long 0x00 24. " RES0_R01 ,Resistor0 bottom to pin P1" "Not switched,Switched"
|
|
bitfld.long 0x00 23. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " OA0O_D71 ,Opamp0 output to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 21. " OA0O_D51 ,Opamp0 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 20. " OA0O_D31 ,Opamp0 output to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 19. " OA0M_A91 ,Opamp0 negative terminal to pin P2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x00 17. " OA0M_A71 ,Opamp0 negative terminal to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " OA0M_A61 ,Opamp0 negative terminal to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " OA0M_A51 ,Opamp0 negative terminal to ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OA0M_A41 ,Opamp0 negative terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 13. " OA0M_A31 ,Opamp0 negative terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not switched,Switched"
|
|
bitfld.long 0x00 9. " OA0P_A90 ,Opamp0 positive terminal to uabin1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OA0P_A80 ,Opamp0 positive terminal to uabin0" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " OA0P_A70 ,Opamp0 positive terminal to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 6. " OA0P_A60 ,Opamp0 positive terminal to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 5. " OA0P_A50 ,Opamp0 positive terminal to ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OA0P_A40 ,Opamp0 positive terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not switched,Switched"
|
|
bitfld.long 0x00 1. " OA0P_A10 ,Opamp0 positive terminal to pin P1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x04 "OA0_SW_CLEAR,Opamp0 Switch Control Clear"
|
|
eventfld.long 0x04 30. " RES0_R81 ,Resistor0 tap to opamp0 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 29. " RES0_R71 ,Resistor0 tap to opamp0 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 28. " RES0_R61 ,Resistor0 bottom to VSSA" "Not cleared,Cleared"
|
|
eventfld.long 0x04 27. " RES0_R41 ,Resistor0 bottom to opamp1 negative terminal" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 26. " RES0_R31 ,Resistor0 bottom to opamp0 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 25. " RES0_R11 ,Resistor0 bottom to opamp1 output" "Not cleared,Cleared"
|
|
eventfld.long 0x04 24. " RES0_R01 ,Resistor0 bottom to pin P1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 23. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 22. " OA0O_D71 ,Opamp0 output to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 21. " OA0O_D51 ,Opamp0 output to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x04 20. " OA0O_D31 ,Opamp0 output to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 19. " OA0M_A91 ,Opamp0 negative terminal to pin P2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 18. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x04 17. " OA0M_A71 ,Opamp0 negative terminal to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 16. " OA0M_A61 ,Opamp0 negative terminal to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x04 15. " OA0M_A51 ,Opamp0 negative terminal to ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 14. " OA0M_A41 ,Opamp0 negative terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 13. " OA0M_A31 ,Opamp0 negative terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 11. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 9. " OA0P_A90 ,Opamp0 positive terminal to uabin1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 8. " OA0P_A80 ,Opamp0 positive terminal to uabin0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 7. " OA0P_A70 ,Opamp0 positive terminal to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 6. " OA0P_A60 ,Opamp0 positive terminal to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x04 5. " OA0P_A50 ,Opamp0 positive terminal to ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 4. " OA0P_A40 ,Opamp0 positive terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 1. " OA0P_A10 ,Opamp0 positive terminal to pin P1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
line.long 0x08 "OA1_SW,Opamp1 Switch Control"
|
|
bitfld.long 0x08 31. " RES1_R92 ,Resistor1 tap to opamp0 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 30. " RES1_R82 ,Resistor1 tap to opamp1 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 29. " RES1_R72 ,Resistor1 tap to opamp1 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 28. " RES1_R62 ,Resistor1 bottom to VSSA" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 27. " RES1_R52 ,Resistor1 bottom to resistor0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 26. " RES1_R32 ,Resistor1 bottom to opamp1 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 25. " RES1_R02 ,Resistor1 bottom to pin P4" "Not switched,Switched"
|
|
bitfld.long 0x08 24. " OA10_D82 ,Opamp1 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OA1O_D72 ,Opamp1 output to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 22. " OA1O_D62 ,Opamp1 output to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x08 21. " OA1O_D52 ,Opamp1 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 20. " OA1O_D42 ,Opamp1 output to ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OA1M_A92 ,Opamp1 negative terminal to pin P3" "Not switched,Switched"
|
|
bitfld.long 0x08 18. " OA1M_A82 ,Opamp1 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 17. " OA1M_A72 ,Opamp1 negative terminal to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 16. " OA1M_A62 ,Opamp1 negative terminal to ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OA1M_A52 ,Opamp1 negative terminal to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 14. " OA1M_A42 ,Opamp1 negative terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 13. " OA1M_A32 ,Opamp1 negative terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 12. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OA1P_A93 ,Opamp1 positive terminal to uabin1" "Not switched,Switched"
|
|
bitfld.long 0x08 8. " OA1P_A83 ,Opamp1 positive terminal to uabin0" "Not switched,Switched"
|
|
bitfld.long 0x08 7. " OA1P_A73 ,Opamp1 positive terminal to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 6. " OA1P_A63 ,Opamp1 positive terminal to ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OA1P_A53 ,Opamp1 positive terminal to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 3. " OA1P_A33 ,Opamp1 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 2. " OA1P_A23 ,Opamp1 positive terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not switched,Switched"
|
|
bitfld.long 0x08 0. " OA1P_A03 ,Opamp positive terminal to amuxbusb" "Not switched,Switched"
|
|
line.long 0x0C "OA1_SW_CLEAR,Opamp1 Switch Control Clear"
|
|
eventfld.long 0x0C 31. " RES1_R92 ,Resistor1 tap to opamp0 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 30. " RES1_R82 ,Resistor1 tap to opamp1 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 29. " RES1_R72 ,Resistor1 tap to opamp1 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 28. " RES1_R62 ,Resistor1 bottom to VSSA" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 27. " RES1_R52 ,Resistor1 bottom to resistor0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 26. " RES1_R32 ,Resistor1 bottom to opamp1 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 25. " RES1_R02 ,Resistor1 bottom to pin P4" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 24. " OA10_D82 ,Opamp1 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 23. " OA1O_D72 ,Opamp1 output to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 22. " OA1O_D62 ,Opamp1 output to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 21. " OA1O_D52 ,Opamp1 output to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 20. " OA1O_D42 ,Opamp1 output to ctbbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " OA1M_A92 ,Opamp1 negative terminal to pin P3" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 18. " OA1M_A82 ,Opamp1 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 17. " OA1M_A72 ,Opamp1 negative terminal to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 16. " OA1M_A62 ,Opamp1 negative terminal to ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 15. " OA1M_A52 ,Opamp1 negative terminal to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 14. " OA1M_A42 ,Opamp1 negative terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 13. " OA1M_A32 ,Opamp1 negative terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 12. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 9. " OA1P_A93 ,Opamp1 positive terminal to uabin1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 8. " OA1P_A83 ,Opamp1 positive terminal to uabin0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 7. " OA1P_A73 ,Opamp1 positive terminal to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 6. " OA1P_A63 ,Opamp1 positive terminal to ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 5. " OA1P_A53 ,Opamp1 positive terminal to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 3. " OA1P_A33 ,Opamp1 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 2. " OA1P_A23 ,Opamp1 positive terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 0. " OA1P_A03 ,Opamp positive terminal to amuxbusb" "Not cleared,Cleared"
|
|
line.long 0x10 "CTBBUS_SW,CTB Bus Switch Control"
|
|
bitfld.long 0x10 28. " CB2_G50 ,Ctbbus2 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 27. " CB3_G61 ,Ctbbus3 sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 26. " CB2_G52 ,Ctbbus2 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 25. " CB1_G41 ,Ctbbus1 sarbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 24. " CB0_G32 ,Ctbbus0 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 23. " CB3_G63 ,Ctbbus3 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 22. " CB2_G53 ,Ctbbus2 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 21. " CB1_G43 ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 20. " CB0_G33 ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 19. " CB3_P37 ,P7 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 18. " CB3_P35 ,P5 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 17. " CB3_P33 ,P3 ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 16. " CB3_P31 ,P1 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 15. " CB2_P26 ,P6 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 14. " CB2_P24 ,P4 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 13. " CB2_P22 ,P2 ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 12. " CB2_P20 ,P0 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 11. " CB1_P17 ,P7 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 10. " CB1_P15 ,P5 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 9. " CB1_P13 ,P3 ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 8. " CB1_P11 ,P1 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 7. " CB0_P07 ,P7 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 6. " CB0_P06 ,P6 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 5. " CB0_P05 ,P5 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 4. " CB0_P04 ,P4 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 3. " CB0_P03 ,P3 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 2. " CB0_P02 ,P2 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 1. " CB0_P01 ,P1 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CB0_P00 ,P0 ctbbus0" "Not switched,Switched"
|
|
line.long 0x14 "CTBBUS_SW_CLEAR,CTB Bus Switch Control Clear"
|
|
eventfld.long 0x14 28. " CB2_G50 ,Ctbbus2 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 27. " CB3_G61 ,Ctbbus3 sarbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 26. " CB2_G52 ,Ctbbus2 sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 25. " CB1_G41 ,Ctbbus1 sarbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 24. " CB0_G32 ,Ctbbus0 sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 23. " CB3_G63 ,Ctbbus3 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 22. " CB2_G53 ,Ctbbus2 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 21. " CB1_G43 ,Ctbbus1 right neighbor" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 20. " CB0_G33 ,Ctbbus1 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 19. " CB3_P37 ,P7 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 18. " CB3_P35 ,P5 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 17. " CB3_P33 ,P3 ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 16. " CB3_P31 ,P1 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 15. " CB2_P26 ,P6 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 14. " CB2_P24 ,P4 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 13. " CB2_P22 ,P2 ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 12. " CB2_P20 ,P0 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 11. " CB1_P17 ,P7 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 10. " CB1_P15 ,P5 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 9. " CB1_P13 ,P3 ctbbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 8. " CB1_P11 ,P1 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 7. " CB0_P07 ,P7 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 6. " CB0_P06 ,P6 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 5. " CB0_P05 ,P5 ctbbus0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 4. " CB0_P04 ,P4 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 3. " CB0_P03 ,P3 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 2. " CB0_P02 ,P2 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 1. " CB0_P01 ,P1 ctbbus0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 0. " CB0_P00 ,P0 ctbbus0" "Not cleared,Cleared"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTB_SW_HW_CTRL,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 17. " SARBUS1_HW_CTRL ,Sarbus1 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " SARBUS0_HW_CTRL ,Sarbus0 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " P7_HW_CTRL23 ,For P37" "Not switched,Switched"
|
|
bitfld.long 0x00 14. " P6_HW_CTRL23 ,For P26" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P5_HW_CTRL23 ,For P35" "Not switched,Switched"
|
|
bitfld.long 0x00 12. " P4_HW_CTRL23 ,For P24" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " P3_HW_CTRL23 ,For P33 D52 D62" "Not switched,Switched"
|
|
bitfld.long 0x00 10. " P2_HW_CTRL23 ,For P22 D51" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P1_HW_CTRL23 ,For P31" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " P0_HW_CTRL23 ,For P20" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " P7_HW_CTRL01 ,For P07 P17" "Not switched,Switched"
|
|
bitfld.long 0x00 6. " P6_HW_CTRL01 ,For P06" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5_HW_CTRL01 ,For P05 P15" "Not switched,Switched"
|
|
bitfld.long 0x00 4. " P4_HW_CTRL01 ,For P04" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " P3_HW_CTRL01 ,For P03 P13" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " P2_HW_CTRL01 ,For P02" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1_HW_CTRL01 ,For P01 P11" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " P0_HW_CTRL01 ,For P00" "Not switched,Switched"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CTB_SW_STATUS,CTB Switch Control Status"
|
|
bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp1 output to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp1 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 27. " CB3_G61_STAT ,Ctbbus3 sarbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CB2_G52_STAT ,Ctbbus2 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 25. " CB1_G41_STAT ,Ctbbus1 sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 24. " CB0_G32_STAT ,Ctbbus0 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 23. " CB3_G63_STAT ,Ctbbus3 right neighbor" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CB2_G53_STAT ,Ctbbus2 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 21. " CB1_G43_STAT ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 20. " CB0_G33_STAT ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 19. " CB3_P37_STAT ,P7 ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CB3_P35_STAT ,P5 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 17. " CB3_P33_STAT ,P3 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " CB3_P31_STAT ,P1 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " CB2_P26_STAT ,P6 ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CB2_P24_STAT ,P4 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 13. " CB2_P22_STAT ,P2 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 12. " CB2_P20_STAT ,P0 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " CB1_P17_STAT ,P7 ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CB1_P15_STAT ,P5 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 9. " CB1_P13_STAT ,P3 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " CB1_P11_STAT ,P1 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " CB0_P07_STAT ,P7 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CB0_P06_STAT ,P6 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 5. " CB0_P05_STAT ,P5 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 4. " CB0_P04_STAT ,P4 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " CB0_P03_STAT ,P3 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CB0_P02_STAT ,P2 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 1. " CB0_P01_STAT ,P1 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " CB0_P00_STAT ,P0 ctbbus0" "Not switched,Switched"
|
|
group.long 0xF00++0x1B
|
|
line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x00 0.--5. " OA0_OFFSET_TRIM ,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "OA0_SLOPE_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x04 0.--5. " OA0_SLOPE_OFFSET_T ,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "OA0_COMP_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x08 0.--1. " OA0_COMP_TRIM ,Opamp0 compensation capacitor trim" "0,1,2,3"
|
|
line.long 0x0C "OA1_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x0C 0.--5. " OA1_OFFSET_TRIM ,Opamp1 offs et trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "OA1_SLOPE_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x10 0.--5. " OA1_SLOPE_OFFSET_T ,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "OA1_COMP_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x14 0.--1. " OA1_COMP_TRIM ,Opamp1 compensation capacitor trim" "0,1,2,3"
|
|
line.long 0x18 "RMP_TRIM,Risk Mitigation Bits"
|
|
bitfld.long 0x18 0.--3. " RMP_TRIM ,Risk mitigation trim bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTB_CTRL,Global CTB And Power Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree "DSAB (Deep Sleep Amplifier Bias)"
|
|
base ad:0x403F0E00
|
|
width 21.
|
|
if (((per.l(ad:0x403F0E00))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PASS_DSAB_DSAB_CTRL,Global DSAB Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled DSAB" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x00 28. " STARTUP_RM ,Risk mitigation control" "0,Force start"
|
|
bitfld.long 0x00 24. " BYPASS_MODE_EN ,Bypass mode enable" "DSAB,VDDA"
|
|
bitfld.long 0x00 16.--19. " REF_SWAP_EN ,This field provides bitwise selection of the current sources that drive the DSAB ZTC and PTAT outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " SEL_OUT ,Select output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--5. " CURRENT_SEL ,DSAB DAC control field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "PASS_DSAB_DSAB_DFT,DFT Bits"
|
|
bitfld.long 0x04 0.--3. " EN_DFT ,Enable DFT" "Disabled,Enabled,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PASS_DSAB_DSAB_CTRL,Global DSAB Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled DSAB" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("CY8C42*-BL*")
|
|
tree "DSI (Digital System Interconnect)"
|
|
base ad:0x400F4300
|
|
width 10.
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "HC0,DSI0x400F4300 HC0 Tile Configuration"
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "HC1,DSI0x400F4300 HC1 Tile Configuration"
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "HC2,DSI0x400F4300 HC2 Tile Configuration"
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "HC3,DSI0x400F4300 HC3 Tile Configuration"
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "HC4,DSI0x400F4300 HC4 Tile Configuration"
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "HC5,DSI0x400F4300 HC5 Tile Configuration"
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "HC6,DSI0x400F4300 HC6 Tile Configuration"
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "HC7,DSI0x400F4300 HC7 Tile Configuration"
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "HC8,DSI0x400F4300 HC8 Tile Configuration"
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "HC9,DSI0x400F4300 HC9 Tile Configuration"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "HC10,DSI0x400F4300 HC10 Tile Configuration"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "HC11,DSI0x400F4300 HC11 Tile Configuration"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "HC12,DSI0x400F4300 HC12 Tile Configuration"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "HC13,DSI0x400F4300 HC13 Tile Configuration"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "HC14,DSI0x400F4300 HC14 Tile Configuration"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "HC15,DSI0x400F4300 HC15 Tile Configuration"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "HC16,DSI0x400F4300 HC16 Tile Configuration"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "HC17,DSI0x400F4300 HC17 Tile Configuration"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "HC18,DSI0x400F4300 HC18 Tile Configuration"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "HC19,DSI0x400F4300 HC19 Tile Configuration"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "HC20,DSI0x400F4300 HC20 Tile Configuration"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "HC21,DSI0x400F4300 HC21 Tile Configuration"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "HC22,DSI0x400F4300 HC22 Tile Configuration"
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "HC23,DSI0x400F4300 HC23 Tile Configuration"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "HC24,DSI0x400F4300 HC24 Tile Configuration"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "HC25,DSI0x400F4300 HC25 Tile Configuration"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "HC26,DSI0x400F4300 HC26 Tile Configuration"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "HC27,DSI0x400F4300 HC27 Tile Configuration"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "HC28,DSI0x400F4300 HC28 Tile Configuration"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "HC29,DSI0x400F4300 HC29 Tile Configuration"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "HC30,DSI0x400F4300 HC30 Tile Configuration"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "HC31,DSI0x400F4300 HC31 Tile Configuration"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "HC32,DSI0x400F4300 HC32 Tile Configuration"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "HC33,DSI0x400F4300 HC33 Tile Configuration"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "HC34,DSI0x400F4300 HC34 Tile Configuration"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "HC35,DSI0x400F4300 HC35 Tile Configuration"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "HC36,DSI0x400F4300 HC36 Tile Configuration"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "HC37,DSI0x400F4300 HC37 Tile Configuration"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "HC38,DSI0x400F4300 HC38 Tile Configuration"
|
|
group.byte 0x27++0x00
|
|
line.byte 0x00 "HC39,DSI0x400F4300 HC39 Tile Configuration"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "HC40,DSI0x400F4300 HC40 Tile Configuration"
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "HC41,DSI0x400F4300 HC41 Tile Configuration"
|
|
group.byte 0x2A++0x00
|
|
line.byte 0x00 "HC42,DSI0x400F4300 HC42 Tile Configuration"
|
|
group.byte 0x2B++0x00
|
|
line.byte 0x00 "HC43,DSI0x400F4300 HC43 Tile Configuration"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "HC44,DSI0x400F4300 HC44 Tile Configuration"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "HC45,DSI0x400F4300 HC45 Tile Configuration"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "HC46,DSI0x400F4300 HC46 Tile Configuration"
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "HC47,DSI0x400F4300 HC47 Tile Configuration"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "HC48,DSI0x400F4300 HC48 Tile Configuration"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "HC49,DSI0x400F4300 HC49 Tile Configuration"
|
|
group.byte 0x32++0x00
|
|
line.byte 0x00 "HC50,DSI0x400F4300 HC50 Tile Configuration"
|
|
group.byte 0x33++0x00
|
|
line.byte 0x00 "HC51,DSI0x400F4300 HC51 Tile Configuration"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "HC52,DSI0x400F4300 HC52 Tile Configuration"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "HC53,DSI0x400F4300 HC53 Tile Configuration"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "HC54,DSI0x400F4300 HC54 Tile Configuration"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "HC55,DSI0x400F4300 HC55 Tile Configuration"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "HC56,DSI0x400F4300 HC56 Tile Configuration"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "HC57,DSI0x400F4300 HC57 Tile Configuration"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "HC58,DSI0x400F4300 HC58 Tile Configuration"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "HC59,DSI0x400F4300 HC59 Tile Configuration"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "HC60,DSI0x400F4300 HC60 Tile Configuration"
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "HC61,DSI0x400F4300 HC61 Tile Configuration"
|
|
group.byte 0x3E++0x00
|
|
line.byte 0x00 "HC62,DSI0x400F4300 HC62 Tile Configuration"
|
|
group.byte 0x3F++0x00
|
|
line.byte 0x00 "HC63,DSI0x400F4300 HC63 Tile Configuration"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "HC64,DSI0x400F4300 HC64 Tile Configuration"
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "HC65,DSI0x400F4300 HC65 Tile Configuration"
|
|
group.byte 0x42++0x00
|
|
line.byte 0x00 "HC66,DSI0x400F4300 HC66 Tile Configuration"
|
|
group.byte 0x43++0x00
|
|
line.byte 0x00 "HC67,DSI0x400F4300 HC67 Tile Configuration"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "HC68,DSI0x400F4300 HC68 Tile Configuration"
|
|
group.byte 0x45++0x00
|
|
line.byte 0x00 "HC69,DSI0x400F4300 HC69 Tile Configuration"
|
|
group.byte 0x46++0x00
|
|
line.byte 0x00 "HC70,DSI0x400F4300 HC70 Tile Configuration"
|
|
group.byte 0x47++0x00
|
|
line.byte 0x00 "HC71,DSI0x400F4300 HC71 Tile Configuration"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "HC72,DSI0x400F4300 HC72 Tile Configuration"
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "HC73,DSI0x400F4300 HC73 Tile Configuration"
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "HC74,DSI0x400F4300 HC74 Tile Configuration"
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "HC75,DSI0x400F4300 HC75 Tile Configuration"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "HC76,DSI0x400F4300 HC76 Tile Configuration"
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "HC77,DSI0x400F4300 HC77 Tile Configuration"
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "HC78,DSI0x400F4300 HC78 Tile Configuration"
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "HC79,DSI0x400F4300 HC79 Tile Configuration"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "HC80,DSI0x400F4300 HC80 Tile Configuration"
|
|
group.byte 0x51++0x00
|
|
line.byte 0x00 "HC81,DSI0x400F4300 HC81 Tile Configuration"
|
|
group.byte 0x52++0x00
|
|
line.byte 0x00 "HC82,DSI0x400F4300 HC82 Tile Configuration"
|
|
group.byte 0x53++0x00
|
|
line.byte 0x00 "HC83,DSI0x400F4300 HC83 Tile Configuration"
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "HC84,DSI0x400F4300 HC84 Tile Configuration"
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "HC85,DSI0x400F4300 HC85 Tile Configuration"
|
|
group.byte 0x56++0x00
|
|
line.byte 0x00 "HC86,DSI0x400F4300 HC86 Tile Configuration"
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "HC87,DSI0x400F4300 HC87 Tile Configuration"
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "HC88,DSI0x400F4300 HC88 Tile Configuration"
|
|
group.byte 0x59++0x00
|
|
line.byte 0x00 "HC89,DSI0x400F4300 HC89 Tile Configuration"
|
|
group.byte 0x5A++0x00
|
|
line.byte 0x00 "HC90,DSI0x400F4300 HC90 Tile Configuration"
|
|
group.byte 0x5B++0x00
|
|
line.byte 0x00 "HC91,DSI0x400F4300 HC91 Tile Configuration"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "HC92,DSI0x400F4300 HC92 Tile Configuration"
|
|
group.byte 0x5D++0x00
|
|
line.byte 0x00 "HC93,DSI0x400F4300 HC93 Tile Configuration"
|
|
group.byte 0x5E++0x00
|
|
line.byte 0x00 "HC94,DSI0x400F4300 HC94 Tile Configuration"
|
|
group.byte 0x5F++0x00
|
|
line.byte 0x00 "HC95,DSI0x400F4300 HC95 Tile Configuration"
|
|
group.byte 0x60++0x00
|
|
line.byte 0x00 "HC96,DSI0x400F4300 HC96 Tile Configuration"
|
|
group.byte 0x61++0x00
|
|
line.byte 0x00 "HC97,DSI0x400F4300 HC97 Tile Configuration"
|
|
group.byte 0x62++0x00
|
|
line.byte 0x00 "HC98,DSI0x400F4300 HC98 Tile Configuration"
|
|
group.byte 0x63++0x00
|
|
line.byte 0x00 "HC99,DSI0x400F4300 HC99 Tile Configuration"
|
|
group.byte 0x64++0x00
|
|
line.byte 0x00 "HC100,DSI0x400F4300 HC100 Tile Configuration"
|
|
group.byte 0x65++0x00
|
|
line.byte 0x00 "HC101,DSI0x400F4300 HC101 Tile Configuration"
|
|
group.byte 0x66++0x00
|
|
line.byte 0x00 "HC102,DSI0x400F4300 HC102 Tile Configuration"
|
|
group.byte 0x67++0x00
|
|
line.byte 0x00 "HC103,DSI0x400F4300 HC103 Tile Configuration"
|
|
group.byte 0x68++0x00
|
|
line.byte 0x00 "HC104,DSI0x400F4300 HC104 Tile Configuration"
|
|
group.byte 0x69++0x00
|
|
line.byte 0x00 "HC105,DSI0x400F4300 HC105 Tile Configuration"
|
|
group.byte 0x6A++0x00
|
|
line.byte 0x00 "HC106,DSI0x400F4300 HC106 Tile Configuration"
|
|
group.byte 0x6B++0x00
|
|
line.byte 0x00 "HC107,DSI0x400F4300 HC107 Tile Configuration"
|
|
group.byte 0x6C++0x00
|
|
line.byte 0x00 "HC108,DSI0x400F4300 HC108 Tile Configuration"
|
|
group.byte 0x6D++0x00
|
|
line.byte 0x00 "HC109,DSI0x400F4300 HC109 Tile Configuration"
|
|
group.byte 0x6E++0x00
|
|
line.byte 0x00 "HC110,DSI0x400F4300 HC110 Tile Configuration"
|
|
group.byte 0x6F++0x00
|
|
line.byte 0x00 "HC111,DSI0x400F4300 HC111 Tile Configuration"
|
|
group.byte 0x70++0x00
|
|
line.byte 0x00 "HC112,DSI0x400F4300 HC112 Tile Configuration"
|
|
group.byte 0x71++0x00
|
|
line.byte 0x00 "HC113,DSI0x400F4300 HC113 Tile Configuration"
|
|
group.byte 0x72++0x00
|
|
line.byte 0x00 "HC114,DSI0x400F4300 HC114 Tile Configuration"
|
|
group.byte 0x73++0x00
|
|
line.byte 0x00 "HC115,DSI0x400F4300 HC115 Tile Configuration"
|
|
group.byte 0x74++0x00
|
|
line.byte 0x00 "HC116,DSI0x400F4300 HC116 Tile Configuration"
|
|
group.byte 0x75++0x00
|
|
line.byte 0x00 "HC117,DSI0x400F4300 HC117 Tile Configuration"
|
|
group.byte 0x76++0x00
|
|
line.byte 0x00 "HC118,DSI0x400F4300 HC118 Tile Configuration"
|
|
group.byte 0x77++0x00
|
|
line.byte 0x00 "HC119,DSI0x400F4300 HC119 Tile Configuration"
|
|
group.byte 0x78++0x00
|
|
line.byte 0x00 "HC120,DSI0x400F4300 HC120 Tile Configuration"
|
|
group.byte 0x79++0x00
|
|
line.byte 0x00 "HC121,DSI0x400F4300 HC121 Tile Configuration"
|
|
group.byte 0x7A++0x00
|
|
line.byte 0x00 "HC122,DSI0x400F4300 HC122 Tile Configuration"
|
|
group.byte 0x7B++0x00
|
|
line.byte 0x00 "HC123,DSI0x400F4300 HC123 Tile Configuration"
|
|
group.byte 0x7C++0x00
|
|
line.byte 0x00 "HC124,DSI0x400F4300 HC124 Tile Configuration"
|
|
group.byte 0x7D++0x00
|
|
line.byte 0x00 "HC125,DSI0x400F4300 HC125 Tile Configuration"
|
|
group.byte 0x7E++0x00
|
|
line.byte 0x00 "HC126,DSI0x400F4300 HC126 Tile Configuration"
|
|
group.byte 0x7F++0x00
|
|
line.byte 0x00 "HC127,DSI0x400F4300 HC127 Tile Configuration"
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "HV_L0,DSI0x400F4300 HV0 Tile Configuration"
|
|
group.byte 0x81++0x00
|
|
line.byte 0x00 "HV_L1,DSI0x400F4300 HV1 Tile Configuration"
|
|
group.byte 0x82++0x00
|
|
line.byte 0x00 "HV_L2,DSI0x400F4300 HV2 Tile Configuration"
|
|
group.byte 0x83++0x00
|
|
line.byte 0x00 "HV_L3,DSI0x400F4300 HV3 Tile Configuration"
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "HV_L4,DSI0x400F4300 HV4 Tile Configuration"
|
|
group.byte 0x85++0x00
|
|
line.byte 0x00 "HV_L5,DSI0x400F4300 HV5 Tile Configuration"
|
|
group.byte 0x86++0x00
|
|
line.byte 0x00 "HV_L6,DSI0x400F4300 HV6 Tile Configuration"
|
|
group.byte 0x87++0x00
|
|
line.byte 0x00 "HV_L7,DSI0x400F4300 HV7 Tile Configuration"
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "HV_L8,DSI0x400F4300 HV8 Tile Configuration"
|
|
group.byte 0x89++0x00
|
|
line.byte 0x00 "HV_L9,DSI0x400F4300 HV9 Tile Configuration"
|
|
group.byte 0x8A++0x00
|
|
line.byte 0x00 "HV_L10,DSI0x400F4300 HV10 Tile Configuration"
|
|
group.byte 0x8B++0x00
|
|
line.byte 0x00 "HV_L11,DSI0x400F4300 HV11 Tile Configuration"
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "HV_L12,DSI0x400F4300 HV12 Tile Configuration"
|
|
group.byte 0x8D++0x00
|
|
line.byte 0x00 "HV_L13,DSI0x400F4300 HV13 Tile Configuration"
|
|
group.byte 0x8E++0x00
|
|
line.byte 0x00 "HV_L14,DSI0x400F4300 HV14 Tile Configuration"
|
|
group.byte 0x8F++0x00
|
|
line.byte 0x00 "HV_L15,DSI0x400F4300 HV15 Tile Configuration"
|
|
group.byte 0x90++0x00
|
|
line.byte 0x00 "HS0,DSI0x400F4300 HS0 Tile Configuration"
|
|
group.byte 0x91++0x00
|
|
line.byte 0x00 "HS1,DSI0x400F4300 HS1 Tile Configuration"
|
|
group.byte 0x92++0x00
|
|
line.byte 0x00 "HS2,DSI0x400F4300 HS2 Tile Configuration"
|
|
group.byte 0x93++0x00
|
|
line.byte 0x00 "HS3,DSI0x400F4300 HS3 Tile Configuration"
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "HS4,DSI0x400F4300 HS4 Tile Configuration"
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "HS5,DSI0x400F4300 HS5 Tile Configuration"
|
|
group.byte 0x96++0x00
|
|
line.byte 0x00 "HS6,DSI0x400F4300 HS6 Tile Configuration"
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "HS7,DSI0x400F4300 HS7 Tile Configuration"
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "HS8,DSI0x400F4300 HS8 Tile Configuration"
|
|
group.byte 0x99++0x00
|
|
line.byte 0x00 "HS9,DSI0x400F4300 HS9 Tile Configuration"
|
|
group.byte 0x9A++0x00
|
|
line.byte 0x00 "HS10,DSI0x400F4300 HS10 Tile Configuration"
|
|
group.byte 0x9B++0x00
|
|
line.byte 0x00 "HS11,DSI0x400F4300 HS11 Tile Configuration"
|
|
group.byte 0x9C++0x00
|
|
line.byte 0x00 "HS12,DSI0x400F4300 HS12 Tile Configuration"
|
|
group.byte 0x9D++0x00
|
|
line.byte 0x00 "HS13,DSI0x400F4300 HS13 Tile Configuration"
|
|
group.byte 0x9E++0x00
|
|
line.byte 0x00 "HS14,DSI0x400F4300 HS14 Tile Configuration"
|
|
group.byte 0x9F++0x00
|
|
line.byte 0x00 "HS15,DSI0x400F4300 HS15 Tile Configuration"
|
|
group.byte 0xA0++0x00
|
|
line.byte 0x00 "HS16,DSI0x400F4300 HS16 Tile Configuration"
|
|
group.byte 0xA1++0x00
|
|
line.byte 0x00 "HS17,DSI0x400F4300 HS17 Tile Configuration"
|
|
group.byte 0xA2++0x00
|
|
line.byte 0x00 "HS18,DSI0x400F4300 HS18 Tile Configuration"
|
|
group.byte 0xA3++0x00
|
|
line.byte 0x00 "HS19,DSI0x400F4300 HS19 Tile Configuration"
|
|
group.byte 0xA4++0x00
|
|
line.byte 0x00 "HS20,DSI0x400F4300 HS20 Tile Configuration"
|
|
group.byte 0xA5++0x00
|
|
line.byte 0x00 "HS21,DSI0x400F4300 HS21 Tile Configuration"
|
|
group.byte 0xA6++0x00
|
|
line.byte 0x00 "HS22,DSI0x400F4300 HS22 Tile Configuration"
|
|
group.byte 0xA7++0x00
|
|
line.byte 0x00 "HS23,DSI0x400F4300 HS23 Tile Configuration"
|
|
group.byte 0xA8++0x00
|
|
line.byte 0x00 "HV_R0,DSI0x400F4300 HV0 Tile Configuration"
|
|
group.byte 0xA9++0x00
|
|
line.byte 0x00 "HV_R1,DSI0x400F4300 HV1 Tile Configuration"
|
|
group.byte 0xAA++0x00
|
|
line.byte 0x00 "HV_R2,DSI0x400F4300 HV2 Tile Configuration"
|
|
group.byte 0xAB++0x00
|
|
line.byte 0x00 "HV_R3,DSI0x400F4300 HV3 Tile Configuration"
|
|
group.byte 0xAC++0x00
|
|
line.byte 0x00 "HV_R4,DSI0x400F4300 HV4 Tile Configuration"
|
|
group.byte 0xAD++0x00
|
|
line.byte 0x00 "HV_R5,DSI0x400F4300 HV5 Tile Configuration"
|
|
group.byte 0xAE++0x00
|
|
line.byte 0x00 "HV_R6,DSI0x400F4300 HV6 Tile Configuration"
|
|
group.byte 0xAF++0x00
|
|
line.byte 0x00 "HV_R7,DSI0x400F4300 HV7 Tile Configuration"
|
|
group.byte 0xB0++0x00
|
|
line.byte 0x00 "HV_R8,DSI0x400F4300 HV8 Tile Configuration"
|
|
group.byte 0xB1++0x00
|
|
line.byte 0x00 "HV_R9,DSI0x400F4300 HV9 Tile Configuration"
|
|
group.byte 0xB2++0x00
|
|
line.byte 0x00 "HV_R10,DSI0x400F4300 HV10 Tile Configuration"
|
|
group.byte 0xB3++0x00
|
|
line.byte 0x00 "HV_R11,DSI0x400F4300 HV11 Tile Configuration"
|
|
group.byte 0xB4++0x00
|
|
line.byte 0x00 "HV_R12,DSI0x400F4300 HV12 Tile Configuration"
|
|
group.byte 0xB5++0x00
|
|
line.byte 0x00 "HV_R13,DSI0x400F4300 HV13 Tile Configuration"
|
|
group.byte 0xB6++0x00
|
|
line.byte 0x00 "HV_R14,DSI0x400F4300 HV14 Tile Configuration"
|
|
group.byte 0xB7++0x00
|
|
line.byte 0x00 "HV_R15,DSI0x400F4300 HV15 Tile Configuration"
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "DSIINP0,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xC2++0x00
|
|
line.byte 0x00 "DSIINP1,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "DSIINP2,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xC6++0x00
|
|
line.byte 0x00 "DSIINP3,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "DSIINP4,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xCA++0x00
|
|
line.byte 0x00 "DSIINP5,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "DSIOUTP0,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xCE++0x00
|
|
line.byte 0x00 "DSIOUTP1,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "DSIOUTP2,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xD2++0x00
|
|
line.byte 0x00 "DSIOUTP3,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "DSIOUTT0,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xD6++0x00
|
|
line.byte 0x00 "DSIOUTT1,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "DSIOUTT2,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xDA++0x00
|
|
line.byte 0x00 "DSIOUTT3,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xDC++0x00
|
|
line.byte 0x00 "DSIOUTT4,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xDE++0x00
|
|
line.byte 0x00 "DSIOUTT5,DSI PI Tile Configuration for DSI I/O"
|
|
hexmask.byte 0x00 4.--7. 1. " PI_BOT ,RAM configuration for BOTTOM DSI port interface"
|
|
hexmask.byte 0x00 0.--3. 1. " PI_TOP ,RAM configuration for TOP DSI port interface"
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "VS0,DSI VS Tile Configuration"
|
|
hexmask.byte 0x00 4.--7. 1. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation"
|
|
hexmask.byte 0x00 0.--3. 1. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation"
|
|
group.byte 0xE2++0x00
|
|
line.byte 0x00 "VS1,DSI VS Tile Configuration"
|
|
hexmask.byte 0x00 4.--7. 1. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation"
|
|
hexmask.byte 0x00 0.--3. 1. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation"
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "VS2,DSI VS Tile Configuration"
|
|
hexmask.byte 0x00 4.--7. 1. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation"
|
|
hexmask.byte 0x00 0.--3. 1. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation"
|
|
group.byte 0xE6++0x00
|
|
line.byte 0x00 "VS3,DSI VS Tile Configuration"
|
|
hexmask.byte 0x00 4.--7. 1. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation"
|
|
hexmask.byte 0x00 0.--3. 1. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation"
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "VS4,DSI VS Tile Configuration"
|
|
hexmask.byte 0x00 4.--7. 1. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation"
|
|
hexmask.byte 0x00 0.--3. 1. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation"
|
|
group.byte 0xEA++0x00
|
|
line.byte 0x00 "VS5,DSI VS Tile Configuration"
|
|
hexmask.byte 0x00 4.--7. 1. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation"
|
|
hexmask.byte 0x00 0.--3. 1. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation"
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "VS6,DSI VS Tile Configuration"
|
|
hexmask.byte 0x00 4.--7. 1. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation"
|
|
hexmask.byte 0x00 0.--3. 1. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation"
|
|
group.byte 0xEE++0x00
|
|
line.byte 0x00 "VS7,DSI VS Tile Configuration"
|
|
hexmask.byte 0x00 4.--7. 1. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation"
|
|
hexmask.byte 0x00 0.--3. 1. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "GPIO (General Purpose Input/Output)"
|
|
base ad:0x40041000
|
|
width 17.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "INTR_CAUSE,Interrupt Port Cause Register"
|
|
sif cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x00 6. " PORT_INT[6] ,IO port interrupt 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " PORT_INT[5] ,IO port interrupt 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " PORT_INT[4] ,IO port interrupt 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PORT_INT[3] ,IO port interrupt 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PORT_INT[2] ,IO port interrupt 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " PORT_INT[1] ,IO port interrupt 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " PORT_INT[0] ,IO port interrupt 0" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 0.--5. " PORT_INT ,Each IO port has an associated bit field in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
width 0x0B
|
|
tree.open "Port Specific"
|
|
tree "PRT0"
|
|
base ad:0x40040000
|
|
width 10.
|
|
sif (cpu()=="CY8C4A24PVI-431"||cpu()=="CY8C4A24PVI-441"||cpu()=="CY8C4A25PVI-471"||cpu()=="CY8C4A25PVI-481"||cpu()=="CY8C4A45PVI-471"||cpu()=="CY8C4A45PVI-481")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
elif (cpu()=="CY8C4A24LQI-443"||cpu()=="CY8C4A25LQI-473"||cpu()=="CY8C4A25LQI-483"||cpu()=="CY8C4A45LQI-473"||cpu()=="CY8C4A45LQI-483"||cpu()=="CY8C4A24AZI-433"||cpu()=="CY8C4A24AZI-443"||cpu()=="CY8C4A25AZI-473"||cpu()=="CY8C4A25AZI-483"||cpu()=="CY8C4A45AZI-473"||cpu()=="CY8C4A45AZI-483"||cpu()=="CY8C4A24FNI-443"||cpu()=="CY8C4A25FNI-473"||cpu()=="CY8C4A25FNI-483"||cpu()=="CY8C4A45FNI-473"||cpu()=="CY8C4A45FNI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRT1"
|
|
base ad:0x40040100
|
|
width 10.
|
|
sif (cpu()=="CY8C4A24PVI-431"||cpu()=="CY8C4A24PVI-441"||cpu()=="CY8C4A25PVI-471"||cpu()=="CY8C4A25PVI-481"||cpu()=="CY8C4A45PVI-471"||cpu()=="CY8C4A45PVI-481")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
elif (cpu()=="CY8C4A24LQI-443"||cpu()=="CY8C4A25LQI-473"||cpu()=="CY8C4A25LQI-483"||cpu()=="CY8C4A45LQI-473"||cpu()=="CY8C4A45LQI-483"||cpu()=="CY8C4A24AZI-433"||cpu()=="CY8C4A24AZI-443"||cpu()=="CY8C4A25AZI-473"||cpu()=="CY8C4A25AZI-483"||cpu()=="CY8C4A45AZI-473"||cpu()=="CY8C4A45AZI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
elif (cpu()=="CY8C4A24FNI-443"||cpu()=="CY8C4A25FNI-473"||cpu()=="CY8C4A25FNI-483"||cpu()=="CY8C4A45FNI-473"||cpu()=="CY8C4A45FNI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRT2"
|
|
base ad:0x40040200
|
|
width 10.
|
|
sif (cpu()=="CY8C4A24PVI-431"||cpu()=="CY8C4A24PVI-441"||cpu()=="CY8C4A25PVI-471"||cpu()=="CY8C4A25PVI-481"||cpu()=="CY8C4A45PVI-471"||cpu()=="CY8C4A45PVI-481")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
elif (cpu()=="CY8C4A24LQI-443"||cpu()=="CY8C4A25LQI-473"||cpu()=="CY8C4A25LQI-483"||cpu()=="CY8C4A45LQI-473"||cpu()=="CY8C4A45LQI-483"||cpu()=="CY8C4A24AZI-433"||cpu()=="CY8C4A24AZI-443"||cpu()=="CY8C4A25AZI-473"||cpu()=="CY8C4A25AZI-483"||cpu()=="CY8C4A45AZI-473"||cpu()=="CY8C4A45AZI-483"||cpu()=="CY8C4A24FNI-443"||cpu()=="CY8C4A25FNI-473"||cpu()=="CY8C4A25FNI-483"||cpu()=="CY8C4A45FNI-473"||cpu()=="CY8C4A45FNI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRT3"
|
|
base ad:0x40040300
|
|
width 10.
|
|
sif (cpu()=="CY8C4A24PVI-431"||cpu()=="CY8C4A24PVI-441"||cpu()=="CY8C4A25PVI-471"||cpu()=="CY8C4A25PVI-481"||cpu()=="CY8C4A45PVI-471"||cpu()=="CY8C4A45PVI-481")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" ",1,2,3,,,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
elif (cpu()=="CY8C4A24LQI-443"||cpu()=="CY8C4A25LQI-473"||cpu()=="CY8C4A25LQI-483"||cpu()=="CY8C4A45LQI-473"||cpu()=="CY8C4A45LQI-483"||cpu()=="CY8C4A24AZI-433"||cpu()=="CY8C4A24AZI-443"||cpu()=="CY8C4A25AZI-473"||cpu()=="CY8C4A25AZI-483"||cpu()=="CY8C4A45AZI-473"||cpu()=="CY8C4A45AZI-483"||cpu()=="CY8C4A24FNI-443"||cpu()=="CY8C4A25FNI-473"||cpu()=="CY8C4A25FNI-483"||cpu()=="CY8C4A45FNI-473"||cpu()=="CY8C4A45FNI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRT4"
|
|
base ad:0x40040400
|
|
width 10.
|
|
sif (cpu()=="CY8C4A24LQI-443"||cpu()=="CY8C4A25LQI-473"||cpu()=="CY8C4A25LQI-483"||cpu()=="CY8C4A45LQI-473"||cpu()=="CY8C4A45LQI-483"||cpu()=="CY8C4A24AZI-433"||cpu()=="CY8C4A24AZI-443"||cpu()=="CY8C4A25AZI-473"||cpu()=="CY8C4A25AZI-483"||cpu()=="CY8C4A45AZI-473"||cpu()=="CY8C4A45AZI-483"||cpu()=="CY8C4A24FNI-443"||cpu()=="CY8C4A25FNI-473"||cpu()=="CY8C4A25FNI-483"||cpu()=="CY8C4A45FNI-473"||cpu()=="CY8C4A45FNI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,This bit should always be 0" "0,?..."
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRT5"
|
|
base ad:0x40040500
|
|
width 10.
|
|
sif (cpu()=="CY8C4A24PVI-431"||cpu()=="CY8C4A24PVI-441"||cpu()=="CY8C4A25PVI-471"||cpu()=="CY8C4A25PVI-481"||cpu()=="CY8C4A45PVI-471"||cpu()=="CY8C4A45PVI-481")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,,2,3,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
elif (cpu()=="CY8C4A24LQI-443"||cpu()=="CY8C4A25LQI-473"||cpu()=="CY8C4A25LQI-483"||cpu()=="CY8C4A45LQI-473"||cpu()=="CY8C4A45LQI-483"||cpu()=="CY8C4A24AZI-433"||cpu()=="CY8C4A24AZI-443"||cpu()=="CY8C4A25AZI-473"||cpu()=="CY8C4A25AZI-483"||cpu()=="CY8C4A45AZI-473"||cpu()=="CY8C4A45AZI-483"||cpu()=="CY8C4A24FNI-443"||cpu()=="CY8C4A25FNI-473"||cpu()=="CY8C4A25FNI-483"||cpu()=="CY8C4A45FNI-473"||cpu()=="CY8C4A45FNI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,This bit should always be 0" "0,?..."
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRT6"
|
|
base ad:0x40040600
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.open "HSIOM (High Speed IO Matrix)"
|
|
tree "HSIOM"
|
|
base ad:0x40022100
|
|
width 17.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "AMUX_SPLIT_CTL0,AMUX Splitter Cell Control"
|
|
bitfld.long 0x00 6. " SWITCH_BB_S0 ,T-switch control for AMUXBUSB vssa/ground switch" "Open,Closed"
|
|
bitfld.long 0x00 5. " SWITCH_BB_SR ,T-switch control for right AMUXBUSB switch" "Open,Closed"
|
|
bitfld.long 0x00 4. " SWITCH_BB_SL ,T-switch control for left AMUXBUSB switch" "Open,Closed"
|
|
bitfld.long 0x00 2. " SWITCH_AA_S0 ,T-switch control for AMUXBUSA vssa/ground switch" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWITCH_AA_SR ,T-switch control for right AMUXBUSA switch" "Open,Closed"
|
|
bitfld.long 0x00 0. " SWITCH_AA_SL ,T-switch control for left AMUXBUSA switch" "Open,Closed"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "AMUX_SPLIT_CTL1,AMUX Splitter Cell Control"
|
|
bitfld.long 0x00 6. " SWITCH_BB_S0 ,T-switch control for AMUXBUSB vssa/ground switch" "Open,Closed"
|
|
bitfld.long 0x00 5. " SWITCH_BB_SR ,T-switch control for right AMUXBUSB switch" "Open,Closed"
|
|
bitfld.long 0x00 4. " SWITCH_BB_SL ,T-switch control for left AMUXBUSB switch" "Open,Closed"
|
|
bitfld.long 0x00 2. " SWITCH_AA_S0 ,T-switch control for AMUXBUSA vssa/ground switch" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWITCH_AA_SR ,T-switch control for right AMUXBUSA switch" "Open,Closed"
|
|
bitfld.long 0x00 0. " SWITCH_AA_SL ,T-switch control for left AMUXBUSA switch" "Open,Closed"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "AMUX_SPLIT_CTL2,AMUX Splitter Cell Control"
|
|
bitfld.long 0x00 6. " SWITCH_BB_S0 ,T-switch control for AMUXBUSB vssa/ground switch" "Open,Closed"
|
|
bitfld.long 0x00 5. " SWITCH_BB_SR ,T-switch control for right AMUXBUSB switch" "Open,Closed"
|
|
bitfld.long 0x00 4. " SWITCH_BB_SL ,T-switch control for left AMUXBUSB switch" "Open,Closed"
|
|
bitfld.long 0x00 2. " SWITCH_AA_S0 ,T-switch control for AMUXBUSA vssa/ground switch" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWITCH_AA_SR ,T-switch control for right AMUXBUSA switch" "Open,Closed"
|
|
bitfld.long 0x00 0. " SWITCH_AA_SL ,T-switch control for left AMUXBUSA switch" "Open,Closed"
|
|
width 0x0B
|
|
tree.end
|
|
tree "HSIOM - Port Specific"
|
|
base ad:0x40020000
|
|
width 12.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PORT_SEL0,Port Selection Register"
|
|
bitfld.long 0x00 28.--31. " IO7_SEL ,Selects Connection For IO Pad 7 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 24.--27. " IO6_SEL ,Selects Connection For IO Pad 6 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 20.--23. " IO5_SEL ,Selects Connection For IO Pad 5 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 16.--19. " IO4_SEL ,Selects Connection For IO Pad 4 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " IO3_SEL ,Selects Connection For IO Pad 3 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 8.--11. " IO2_SEL ,Selects Connection For IO Pad 2 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 4.--7. " IO1_SEL ,Selects Connection For IO Pad 1 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 0.--3. " IO0_SEL ,Selects Connection For IO Pad 0 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PORT_SEL1,Port Selection Register"
|
|
bitfld.long 0x00 28.--31. " IO7_SEL ,Selects Connection For IO Pad 7 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 24.--27. " IO6_SEL ,Selects Connection For IO Pad 6 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 20.--23. " IO5_SEL ,Selects Connection For IO Pad 5 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 16.--19. " IO4_SEL ,Selects Connection For IO Pad 4 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " IO3_SEL ,Selects Connection For IO Pad 3 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 8.--11. " IO2_SEL ,Selects Connection For IO Pad 2 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 4.--7. " IO1_SEL ,Selects Connection For IO Pad 1 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 0.--3. " IO0_SEL ,Selects Connection For IO Pad 0 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PORT_SEL2,Port Selection Register"
|
|
bitfld.long 0x00 28.--31. " IO7_SEL ,Selects Connection For IO Pad 7 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 24.--27. " IO6_SEL ,Selects Connection For IO Pad 6 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 20.--23. " IO5_SEL ,Selects Connection For IO Pad 5 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 16.--19. " IO4_SEL ,Selects Connection For IO Pad 4 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " IO3_SEL ,Selects Connection For IO Pad 3 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 8.--11. " IO2_SEL ,Selects Connection For IO Pad 2 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 4.--7. " IO1_SEL ,Selects Connection For IO Pad 1 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 0.--3. " IO0_SEL ,Selects Connection For IO Pad 0 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "PORT_SEL3,Port Selection Register"
|
|
bitfld.long 0x00 28.--31. " IO7_SEL ,Selects Connection For IO Pad 7 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 24.--27. " IO6_SEL ,Selects Connection For IO Pad 6 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 20.--23. " IO5_SEL ,Selects Connection For IO Pad 5 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 16.--19. " IO4_SEL ,Selects Connection For IO Pad 4 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " IO3_SEL ,Selects Connection For IO Pad 3 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 8.--11. " IO2_SEL ,Selects Connection For IO Pad 2 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 4.--7. " IO1_SEL ,Selects Connection For IO Pad 1 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 0.--3. " IO0_SEL ,Selects Connection For IO Pad 0 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PORT_SEL4,Port Selection Register"
|
|
bitfld.long 0x00 4.--7. " IO1_SEL ,Selects Connection For IO Pad 1 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM,DS_0,DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 0.--3. " IO0_SEL ,Selects Connection For IO Pad 0 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM,DS_0,DS_1,DS_2,DS_3"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "PORT_SEL5,Port Selection Register"
|
|
bitfld.long 0x00 4.--7. " IO1_SEL ,Selects Connection For IO Pad 1 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM,DS_0,DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 0.--3. " IO0_SEL ,Selects Connection For IO Pad 0 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM,DS_0,DS_1,DS_2,DS_3"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "PORT_SEL6,Port Selection Register"
|
|
bitfld.long 0x00 4.--7. " IO1_SEL ,Selects Connection For IO Pad 1 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM,DS_0,DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 0.--3. " IO0_SEL ,Selects Connection For IO Pad 0 Route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM,DS_0,DS_1,DS_2,DS_3"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif cpuis("CY8C4*-BL463")||cpuis("CY8C4*-BL483")||cpuis("CY8C4*-BL493")
|
|
tree "LCD (Liquid Crystal Display)"
|
|
base ad:0x402A0000
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ID,ID & Revision"
|
|
hexmask.long.word 0x00 16.--31. 1. " REVISION ,Version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " ID ,ID of LCD controller peripheral"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DIVIDER,LCD Divider Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DEAD_DIV ,Length of the dead time period in cycles"
|
|
hexmask.long.word 0x00 0.--15. 1. " SUBFR_DIV ,Input clock frequency divide value"
|
|
if (((per.l(ad:0x402A0000+0x08))&0x4)==0x0)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONTROL,LCD Configuration Register"
|
|
rbitfld.long 0x00 31. " LS_EN_STAT ,LS enable status bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " COM_NUM ,The number of COM connections minus 2" "2 COM's,3 COM's,4 COM's,5 COM's,6 COM's,7 COM's,8 COM's,9 COM's,10 COM's,11 COM's,12 COM's,13 COM's,14 COM's,15 COM's,16 COM's,?..."
|
|
bitfld.long 0x00 5.--6. " BIAS ,PWM bias selection" "HALF,THIRD,FOURTH,FIFTH"
|
|
bitfld.long 0x00 4. " OP_MODE ,Driving mode configuration" "PWM,CORRELATION"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TYPE ,LCD driving waveform type configuration" "TYPE_A,TYPE_B"
|
|
bitfld.long 0x00 2. " LCD_MODE ,HS/LS mode selection" "LS,HS"
|
|
bitfld.long 0x00 0. " LS_EN ,Low speed generator enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONTROL,LCD Configuration Register"
|
|
rbitfld.long 0x00 31. " LS_EN_STAT ,LS enable status bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " COM_NUM ,The number of COM connections minus 2" "2 COM's,3 COM's,4 COM's,5 COM's,6 COM's,7 COM's,8 COM's,9 COM's,10 COM's,11 COM's,12 COM's,13 COM's,14 COM's,15 COM's,16 COM's,?..."
|
|
bitfld.long 0x00 5.--6. " BIAS ,PWM bias selection" "HALF,THIRD,FOURTH,FIFTH"
|
|
bitfld.long 0x00 4. " OP_MODE ,Driving mode configuration" "PWM,CORRELATION"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TYPE ,LCD driving waveform type configuration" "TYPE_A,TYPE_B"
|
|
bitfld.long 0x00 2. " LCD_MODE ,HS/LS mode selection" "LS,HS"
|
|
bitfld.long 0x00 1. " HS_EN ,High speed generator enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DATA0,LCD Pin Data Register"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DATA1,LCD Pin Data Register"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DATA2,LCD Pin Data Register"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DATA3,LCD Pin Data Register"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DATA4,LCD Pin Data Register"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DATA5,LCD Pin Data Register"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DATA6,LCD Pin Data Register"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DATA7,LCD Pin Data Register"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DATA00,LCD Pin Data Registers"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DATA01,LCD Pin Data Registers"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DATA02,LCD Pin Data Registers"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DATA03,LCD Pin Data Registers"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DATA04,LCD Pin Data Registers"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DATA05,LCD Pin Data Registers"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DATA06,LCD Pin Data Registers"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DATA07,LCD Pin Data Registers"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DATA08,LCD Pin Data Registers"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DATA09,LCD Pin Data Registers"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DATA10,LCD Pin Data Registers"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DATA11,LCD Pin Data Registers"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "DATA12,LCD Pin Data Registers"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "DATA13,LCD Pin Data Registers"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "DATA14,LCD Pin Data Registers"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "DATA15,LCD Pin Data Registers"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DATA16,LCD Pin Data Registers"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DATA17,LCD Pin Data Registers"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif !cpuis("CY8C4128LQI-BL443")&&!cpuis("CY8C4128FNI-BL443")
|
|
tree "LPCOMP (Low Power Comparator)"
|
|
base ad:0x402B0000
|
|
width 20.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ID,ID & Revision"
|
|
hexmask.long.word 0x00 16.--31. 1. " REVISION ,Version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " ID ,ID of LPCOMP peripheral"
|
|
if ((((per.l(ad:0x402B0000+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x402B0000+0x04))&0x80)==0x80))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CONFIG,LPCOMP Configuration Register"
|
|
bitfld.long 0x00 21. " DSI_LEVEL2 ,Opamp2 comperator DSI out level" "Pulse,Level"
|
|
bitfld.long 0x00 20. " DSI_BYPASS2 ,Opamp2 bypass comparator output synchronization for DSI output" "Synchronize,Bypass"
|
|
bitfld.long 0x00 16. " DSI_LEVEL1 ,Opamp1 comparator DSI out level" "Pulse,Level"
|
|
bitfld.long 0x00 15. " DSI_BYPASS1 ,Opamp1 bypass comparator output synchronization for DSI output" "Synchronize,Bypass"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ENABLE2 ,Enable comparator 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " OUT2 ,Current output value of the comparator 1" "Low,High"
|
|
bitfld.long 0x00 12.--13. " INTTYPE2 ,Sets which edge in the comparator 1 output triggers an interrupt" "DISABLE,RISING,FALLING,BOTH"
|
|
bitfld.long 0x00 10. " HYST2 ,10mV hysteresis for comparator 1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Sets the operating mode for comparator 1" "SLOW,FAST,ULP,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE1 ,Enable comparator 0" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " OUT1 ,Current output value of the comparator 0" "Low,High"
|
|
bitfld.long 0x00 4.--5. " INTTYPE1 ,Sets which edge in the comparator 0 output triggers an interrupt" "DISABLE,RISING,FALLING,BOTH"
|
|
bitfld.long 0x00 2. " HYST1 ,10mV hysteresis for comparator 0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE1 ,Sets the operating mode for comparator 0" "SLOW,FAST,ULP,?..."
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "INTR,LPCOMP Interrupt Request Register"
|
|
eventfld.long 0x00 1. " COMP2 ,Comparator 1 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " COMP1 ,Comparator 0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,LPCOMP Interrupt Set Register"
|
|
bitfld.long 0x04 1. " COMP2 ,Set COMP2 bit in the interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " COMP1 ,Set COMP1 bit in the interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,LPCOMP Interrupt Request Mask"
|
|
bitfld.long 0x08 1. " COMP2_MASK ,Interrupt mask bit for comparator 1" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " COMP1_MASK ,Interrupt mask bit for comparator 0" "Not masked,Masked"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "INTR_MASKED,LPCOMP Interrupt Request Masked"
|
|
bitfld.long 0x00 1. " COMP2_MASKED ,Logical AND of the comparator 1 interrupt request register bit and the interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " COMP1_MASKED ,Logical AND of the comparator 0 interrupt request register bit and the interrupt mask bit" "Not masked,Masked"
|
|
group.long 0xFF00++0x0F
|
|
line.long 0x00 "TRIM1,LPCOMP Trim Register"
|
|
bitfld.long 0x00 0.--4. " COMP1_TRIMA ,Trim A for comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TRIM2,LPCOMP Trim Register"
|
|
bitfld.long 0x04 0.--4. " COMP1_TRIMB ,Trim B for comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "TRIM3,LPCOMP Trim Register"
|
|
bitfld.long 0x08 0.--4. " COMP2_TRIMA ,Trim A for comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "TRIM4,LPCOMP Trim Register"
|
|
bitfld.long 0x0C 0.--4. " COMP2_TRIMB ,Trim B for comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif ((((per.l(ad:0x402B0000+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x402B0000+0x04))&0x80)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CONFIG,LPCOMP Configuration Register"
|
|
bitfld.long 0x00 21. " DSI_LEVEL2 ,Opamp2 comperator DSI out level" "Pulse,Level"
|
|
bitfld.long 0x00 20. " DSI_BYPASS2 ,Opamp2 bypass comparator output synchronization for DSI output" "Synchronize,Bypass"
|
|
bitfld.long 0x00 16. " DSI_LEVEL1 ,Opamp1 comparator DSI out level" "Pulse,Level"
|
|
bitfld.long 0x00 15. " DSI_BYPASS1 ,Opamp1 bypass comparator output synchronization for DSI output" "Synchronize,Bypass"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ENABLE2 ,Enable comparator 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " OUT2 ,Current output value of the comparator 1" "Low,High"
|
|
bitfld.long 0x00 12.--13. " INTTYPE2 ,Sets which edge in the comparator 1 output triggers an interrupt" "DISABLE,RISING,FALLING,BOTH"
|
|
bitfld.long 0x00 10. " HYST2 ,10mV hysteresis for comparator 1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Sets the operating mode for comparator 1" "SLOW,FAST,ULP,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE1 ,Enable comparator 0" "Disabled,Enabled"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "INTR,LPCOMP Interrupt Request Register"
|
|
eventfld.long 0x00 1. " COMP2 ,Comparator 1 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,LPCOMP Interrupt Set Register"
|
|
bitfld.long 0x04 1. " COMP2 ,Set COMP2 bit in the interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,LPCOMP Interrupt Request Mask"
|
|
bitfld.long 0x08 1. " COMP2_MASK ,Interrupt mask bit for comparator 1" "Not masked,Masked"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "INTR_MASKED,LPCOMP Interrupt Request Masked"
|
|
bitfld.long 0x00 1. " COMP2_MASKED ,Logical AND of the comparator 1 interrupt request register bit and the interrupt mask bit" "Not masked,Masked"
|
|
group.long 0xFF08++0x07
|
|
line.long 0x00 "TRIM3,LPCOMP Trim Register"
|
|
bitfld.long 0x00 0.--4. " COMP2_TRIMA ,Trim A for comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TRIM4,LPCOMP Trim Register"
|
|
bitfld.long 0x04 0.--4. " COMP2_TRIMB ,Trim B for comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif ((((per.l(ad:0x402B0000+0x04))&0x8000)==0x0000)&&(((per.l(ad:0x402B0000+0x04))&0x80)==0x80))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CONFIG,LPCOMP Configuration Register"
|
|
bitfld.long 0x00 21. " DSI_LEVEL2 ,Opamp2 comperator DSI out level" "Pulse,Level"
|
|
bitfld.long 0x00 20. " DSI_BYPASS2 ,Opamp2 bypass comparator output synchronization for DSI output" "Synchronize,Bypass"
|
|
bitfld.long 0x00 16. " DSI_LEVEL1 ,Opamp1 comparator DSI out level" "Pulse,Level"
|
|
bitfld.long 0x00 15. " DSI_BYPASS1 ,Opamp1 bypass comparator output synchronization for DSI output" "Synchronize,Bypass"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ENABLE2 ,Enable comparator 1" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE1 ,Enable comparator 0" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " OUT1 ,Current output value of the comparator 0" "Low,High"
|
|
bitfld.long 0x00 4.--5. " INTTYPE1 ,Sets which edge in the comparator 0 output triggers an interrupt" "DISABLE,RISING,FALLING,BOTH"
|
|
bitfld.long 0x00 2. " HYST1 ,10mV hysteresis for comparator 0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE1 ,Sets the operating mode for comparator 0" "SLOW,FAST,ULP,?..."
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "INTR,LPCOMP Interrupt Request Register"
|
|
eventfld.long 0x00 0. " COMP1 ,Comparator 0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,LPCOMP Interrupt Set Register"
|
|
bitfld.long 0x04 0. " COMP1 ,Set COMP1 bit in the interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,LPCOMP Interrupt Request Mask"
|
|
bitfld.long 0x08 0. " COMP1_MASK ,Interrupt mask bit for comparator 0" "Not masked,Masked"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "INTR_MASKED,LPCOMP Interrupt Request Masked"
|
|
bitfld.long 0x00 0. " COMP1_MASKED ,Logical AND of the comparator 0 interrupt request register bit and the interrupt mask bit" "Not masked,Masked"
|
|
group.long 0xFF00++0x07
|
|
line.long 0x00 "TRIM1,LPCOMP Trim Register"
|
|
bitfld.long 0x00 0.--4. " COMP1_TRIMA ,Trim A for comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TRIM2,LPCOMP Trim Register"
|
|
bitfld.long 0x04 0.--4. " COMP1_TRIMB ,Trim B for comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CONFIG,LPCOMP Configuration Register"
|
|
bitfld.long 0x00 15. " ENABLE2 ,Enable comparator 1" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE1 ,Enable comparator 0" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("CY8C42*-BL*")
|
|
tree "PA (Port Adaptor)"
|
|
base ad:0x400F5000
|
|
width 11.
|
|
group.byte 0x0++0x0E
|
|
line.byte 0x00 "PA0_CFG0,PA Data In Clock Control Register"
|
|
bitfld.byte 0x00 6.--7. " NC ,Spare register bits" "0,1,2,3"
|
|
bitfld.byte 0x00 5. " CLKIN_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " CLKIN_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " CLKIN_EN_MODE ,Select one of four operating modes" "Off,On,Positive edge,Level sensitive"
|
|
bitfld.byte 0x00 0.--1. " CLKIN_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
|
|
line.byte 0x01 "PA0_CFG1,PA Data Out Clock Control Register"
|
|
bitfld.byte 0x01 6.--7. " NC ,Spare register bits" "0,1,2,3"
|
|
bitfld.byte 0x01 5. " CLKOUT_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 4. " CLKOUT_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x01 2.--3. " CLKOUT_EN_MODE ,Select one of four operating modes" "Off,On,Positive edge,Level sensitive"
|
|
bitfld.byte 0x01 0.--1. " CLKOUT_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
|
|
line.byte 0x02 "PA0_CFG2,PA Clock Select Register"
|
|
bitfld.byte 0x02 4.--7. " CLKOUT_SEL ,Select out for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
|
|
bitfld.byte 0x02 0.--3. " CLKIN_SEL ,Select in for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
|
|
line.byte 0x03 "PA0_CFG3,PA Reset Select Register"
|
|
bitfld.byte 0x03 7. " NC7 ,Spare register bit" "0,1"
|
|
bitfld.byte 0x03 6. " RES_OUT_INV ,Select the polarity of the reset control" "Not inverted,Inverted"
|
|
bitfld.byte 0x03 4.--5. " RES_OUT_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
|
|
textline " "
|
|
bitfld.byte 0x03 3. " NC0 ,Spare register bit" "0,1"
|
|
bitfld.byte 0x03 2. " RES_IN_INV ,Select the polarity of the reset control" "Not inverted,Inverted"
|
|
bitfld.byte 0x03 0.--1. " RES_IN_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
|
|
line.byte 0x04 "PA0_CFG4,PA Reset Enable Register"
|
|
bitfld.byte 0x04 3.--7. " NC7654 ,Spare register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.byte 0x04 2. " RES_OE_EN ,Enable the selected reset" "Disabled,Enabled"
|
|
bitfld.byte 0x04 1. " RES_OUT_EN ,Enable the selected reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x04 0. " RES_IN_EN ,Enable the selected reset" "Disabled,Enabled"
|
|
line.byte 0x05 "PA0_CFG5,PA Reset Pin Select Register"
|
|
bitfld.byte 0x05 3.--7. " NC7654 ,Spare register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.byte 0x05 0. " PIN_SEL ,Select port input to route to reset multiplexer" "0,1"
|
|
line.byte 0x06 "PA0_CFG6,PA Input Data Sync Control Register - Low"
|
|
bitfld.byte 0x06 6.--7. " IN_SYNC3 ,Synchronization selection for PA input 3" "Transparent,Single sync,Double sync,"
|
|
bitfld.byte 0x06 4.--5. " IN_SYNC2 ,Synchronization selection for PA input 2" "Transparent,Single sync,Double sync,?..."
|
|
textline " "
|
|
bitfld.byte 0x06 2.--3. " IN_SYNC1 ,Synchronization selection for PA input 1" "Transparent,Single sync,Double sync,"
|
|
bitfld.byte 0x06 0.--1. " IN_SYNC0 ,Synchronization selection for PA input 0" "Transparent,Single sync,Double sync,?..."
|
|
line.byte 0x07 "PA0_CFG7,PA Input Data Sync Control Register - High"
|
|
bitfld.byte 0x07 6.--7. " IN_SYNC7 ,Synchronization selection for PA input 7" "Transparent,Single sync,Double sync,"
|
|
bitfld.byte 0x07 4.--5. " IN_SYNC6 ,Synchronization selection for PA input 6" "Transparent,Single sync,Double sync,?..."
|
|
textline " "
|
|
bitfld.byte 0x07 2.--3. " IN_SYNC5 ,Synchronization selection for PA input 5" "Transparent,Single sync,Double sync,"
|
|
bitfld.byte 0x07 0.--1. " IN_SYNC4 ,Synchronization selection for PA input 4" "Transparent,Single sync,Double sync,?..."
|
|
line.byte 0x08 "PA0_CFG8,PA Output Data Sync Control Register - Low"
|
|
bitfld.byte 0x08 6.--7. " OUT_SYNC3 ,Synchronization selection for PA output 3" "Transparent,Single sync,Clock,Clock inverted"
|
|
bitfld.byte 0x08 4.--5. " OUT_SYNC2 ,Synchronization selection for PA output 2" "Transparent,Single sync,Clock,Clock inverted"
|
|
textline " "
|
|
bitfld.byte 0x08 2.--3. " OUT_SYNC1 ,Synchronization selection for PA output 1" "Transparent,Single sync,Clock,Clock inverted"
|
|
bitfld.byte 0x08 0.--1. " OUT_SYNC0 ,Synchronization selection for PA output 0" "Transparent,Single sync,Clock,Clock inverted"
|
|
line.byte 0x09 "PA0_CFG9,PA Output Data Sync Control Register - High"
|
|
bitfld.byte 0x09 6.--7. " OUT_SYNC7 ,Synchronization selection for PA output 7" "Transparent,Single sync,Clock,Clock inverted"
|
|
bitfld.byte 0x09 4.--5. " OUT_SYNC6 ,Synchronization selection for PA output 6" "Transparent,Single sync,Clock,Clock inverted"
|
|
textline " "
|
|
bitfld.byte 0x09 2.--3. " OUT_SYNC5 ,Synchronization selection for PA output 5" "Transparent,Single sync,Clock,Clock inverted"
|
|
bitfld.byte 0x09 0.--1. " OUT_SYNC4 ,Synchronization selection for PA output 4" "Transparent,Single sync,Clock,Clock inverted"
|
|
line.byte 0x0A "PA0_CFG10,PA Output Data Select Register - Low"
|
|
bitfld.byte 0x0A 6.--7. " DATA_SEL3 ,Data selection for PA output 3" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
bitfld.byte 0x0A 4.--5. " DATA_SEL2 ,Data selection for PA output 2" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
textline " "
|
|
bitfld.byte 0x0A 2.--3. " DATA_SEL1 ,Data selection for PA output 1" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
bitfld.byte 0x0A 0.--1. " DATA_SEL0 ,Data selection for PA output 0" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
line.byte 0x0B "PA0_CFG11,PA Output Data Select Register - High"
|
|
bitfld.byte 0x0B 6.--7. " DATA_SEL7 ,Data selection for PA output 7" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
bitfld.byte 0x0B 4.--5. " DATA_SEL6 ,Data selection for PA output 6" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
textline " "
|
|
bitfld.byte 0x0B 2.--3. " DATA_SEL5 ,Data selection for PA output 5" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
bitfld.byte 0x0B 0.--1. " DATA_SEL4 ,Data selection for PA output 4" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
line.byte 0x0C "PA0_CFG12,PA OE Select Register - Low"
|
|
bitfld.byte 0x0C 6.--7. " OE_SEL3 ,Data selection for PA oe 3" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
bitfld.byte 0x0C 4.--5. " OE_SEL2 ,Data selection for PA oe 2" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
textline " "
|
|
bitfld.byte 0x0C 2.--3. " OE_SEL1 ,Data selection for PA oe 1" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
bitfld.byte 0x0C 0.--1. " OE_SEL0 ,Data selection for PA oe 0" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
line.byte 0x0D "PA0_CFG13,PA OE Select Register - High"
|
|
bitfld.byte 0x0D 6.--7. " OE_SEL7 ,Data selection for PA oe 7" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
bitfld.byte 0x0D 4.--5. " OE_SEL6 ,Data selection for PA oe 6" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
textline " "
|
|
bitfld.byte 0x0D 2.--3. " OE_SEL5 ,Data selection for PA oe 5" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
bitfld.byte 0x0D 0.--1. " OE_SEL4 ,Data selection for PA oe 4" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
line.byte 0x0E "PA0_CFG14,PA OE Sync Register"
|
|
bitfld.byte 0x0E 6.--7. " OE_SYNC3 ,Synchronization options for dsi_to_oe[3]" "Transparent,Single sync,Constant 1,Constant 0"
|
|
bitfld.byte 0x0E 4.--5. " OE_SYNC2 ,Synchronization options for dsi_to_oe[2]" "Transparent,Single sync,Constant 1,Constant 0"
|
|
textline " "
|
|
bitfld.byte 0x0E 2.--3. " OE_SYNC1 ,Synchronization options for dsi_to_oe[1]" "Transparent,Single sync,Constant 1,Constant 0"
|
|
bitfld.byte 0x0E 0.--1. " OE_SYNC0 ,Synchronization options for dsi_to_oe[0]" "Transparent,Single sync,Constant 1,Constant 0"
|
|
group.byte 0x10++0x0E
|
|
line.byte 0x00 "PA1_CFG0,PA Data In Clock Control Register"
|
|
bitfld.byte 0x00 6.--7. " NC ,Spare register bits" "0,1,2,3"
|
|
bitfld.byte 0x00 5. " CLKIN_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " CLKIN_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " CLKIN_EN_MODE ,Select one of four operating modes" "Off,On,Positive edge,Level sensitive"
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bitfld.byte 0x00 0.--1. " CLKIN_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
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line.byte 0x01 "PA1_CFG1,PA Data Out Clock Control Register"
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bitfld.byte 0x01 6.--7. " NC ,Spare register bits" "0,1,2,3"
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bitfld.byte 0x01 5. " CLKOUT_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted"
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bitfld.byte 0x01 4. " CLKOUT_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted"
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textline " "
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bitfld.byte 0x01 2.--3. " CLKOUT_EN_MODE ,Select one of four operating modes" "Off,On,Positive edge,Level sensitive"
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bitfld.byte 0x01 0.--1. " CLKOUT_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
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line.byte 0x02 "PA1_CFG2,PA Clock Select Register"
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bitfld.byte 0x02 4.--7. " CLKOUT_SEL ,Select out for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
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bitfld.byte 0x02 0.--3. " CLKIN_SEL ,Select in for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
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line.byte 0x03 "PA1_CFG3,PA Reset Select Register"
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bitfld.byte 0x03 7. " NC7 ,Spare register bit" "0,1"
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bitfld.byte 0x03 6. " RES_OUT_INV ,Select the polarity of the reset control" "Not inverted,Inverted"
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bitfld.byte 0x03 4.--5. " RES_OUT_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
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textline " "
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bitfld.byte 0x03 3. " NC0 ,Spare register bit" "0,1"
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bitfld.byte 0x03 2. " RES_IN_INV ,Select the polarity of the reset control" "Not inverted,Inverted"
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bitfld.byte 0x03 0.--1. " RES_IN_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
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line.byte 0x04 "PA1_CFG4,PA Reset Enable Register"
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bitfld.byte 0x04 3.--7. " NC7654 ,Spare register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.byte 0x04 2. " RES_OE_EN ,Enable the selected reset" "Disabled,Enabled"
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bitfld.byte 0x04 1. " RES_OUT_EN ,Enable the selected reset" "Disabled,Enabled"
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textline " "
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bitfld.byte 0x04 0. " RES_IN_EN ,Enable the selected reset" "Disabled,Enabled"
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line.byte 0x05 "PA1_CFG5,PA Reset Pin Select Register"
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bitfld.byte 0x05 3.--7. " NC7654 ,Spare register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.byte 0x05 0. " PIN_SEL ,Select port input to route to reset multiplexer" "0,1"
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line.byte 0x06 "PA1_CFG6,PA Input Data Sync Control Register - Low"
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bitfld.byte 0x06 6.--7. " IN_SYNC3 ,Synchronization selection for PA input 3" "Transparent,Single sync,Double sync,"
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bitfld.byte 0x06 4.--5. " IN_SYNC2 ,Synchronization selection for PA input 2" "Transparent,Single sync,Double sync,?..."
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textline " "
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bitfld.byte 0x06 2.--3. " IN_SYNC1 ,Synchronization selection for PA input 1" "Transparent,Single sync,Double sync,"
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bitfld.byte 0x06 0.--1. " IN_SYNC0 ,Synchronization selection for PA input 0" "Transparent,Single sync,Double sync,?..."
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line.byte 0x07 "PA1_CFG7,PA Input Data Sync Control Register - High"
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bitfld.byte 0x07 6.--7. " IN_SYNC7 ,Synchronization selection for PA input 7" "Transparent,Single sync,Double sync,"
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bitfld.byte 0x07 4.--5. " IN_SYNC6 ,Synchronization selection for PA input 6" "Transparent,Single sync,Double sync,?..."
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textline " "
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bitfld.byte 0x07 2.--3. " IN_SYNC5 ,Synchronization selection for PA input 5" "Transparent,Single sync,Double sync,"
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bitfld.byte 0x07 0.--1. " IN_SYNC4 ,Synchronization selection for PA input 4" "Transparent,Single sync,Double sync,?..."
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line.byte 0x08 "PA1_CFG8,PA Output Data Sync Control Register - Low"
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bitfld.byte 0x08 6.--7. " OUT_SYNC3 ,Synchronization selection for PA output 3" "Transparent,Single sync,Clock,Clock inverted"
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bitfld.byte 0x08 4.--5. " OUT_SYNC2 ,Synchronization selection for PA output 2" "Transparent,Single sync,Clock,Clock inverted"
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textline " "
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bitfld.byte 0x08 2.--3. " OUT_SYNC1 ,Synchronization selection for PA output 1" "Transparent,Single sync,Clock,Clock inverted"
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bitfld.byte 0x08 0.--1. " OUT_SYNC0 ,Synchronization selection for PA output 0" "Transparent,Single sync,Clock,Clock inverted"
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line.byte 0x09 "PA1_CFG9,PA Output Data Sync Control Register - High"
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bitfld.byte 0x09 6.--7. " OUT_SYNC7 ,Synchronization selection for PA output 7" "Transparent,Single sync,Clock,Clock inverted"
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bitfld.byte 0x09 4.--5. " OUT_SYNC6 ,Synchronization selection for PA output 6" "Transparent,Single sync,Clock,Clock inverted"
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textline " "
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bitfld.byte 0x09 2.--3. " OUT_SYNC5 ,Synchronization selection for PA output 5" "Transparent,Single sync,Clock,Clock inverted"
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bitfld.byte 0x09 0.--1. " OUT_SYNC4 ,Synchronization selection for PA output 4" "Transparent,Single sync,Clock,Clock inverted"
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line.byte 0x0A "PA1_CFG10,PA Output Data Select Register - Low"
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bitfld.byte 0x0A 6.--7. " DATA_SEL3 ,Data selection for PA output 3" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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bitfld.byte 0x0A 4.--5. " DATA_SEL2 ,Data selection for PA output 2" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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textline " "
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bitfld.byte 0x0A 2.--3. " DATA_SEL1 ,Data selection for PA output 1" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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bitfld.byte 0x0A 0.--1. " DATA_SEL0 ,Data selection for PA output 0" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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line.byte 0x0B "PA1_CFG11,PA Output Data Select Register - High"
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bitfld.byte 0x0B 6.--7. " DATA_SEL7 ,Data selection for PA output 7" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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bitfld.byte 0x0B 4.--5. " DATA_SEL6 ,Data selection for PA output 6" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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textline " "
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bitfld.byte 0x0B 2.--3. " DATA_SEL5 ,Data selection for PA output 5" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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bitfld.byte 0x0B 0.--1. " DATA_SEL4 ,Data selection for PA output 4" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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line.byte 0x0C "PA1_CFG12,PA OE Select Register - Low"
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bitfld.byte 0x0C 6.--7. " OE_SEL3 ,Data selection for PA oe 3" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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bitfld.byte 0x0C 4.--5. " OE_SEL2 ,Data selection for PA oe 2" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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textline " "
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bitfld.byte 0x0C 2.--3. " OE_SEL1 ,Data selection for PA oe 1" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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bitfld.byte 0x0C 0.--1. " OE_SEL0 ,Data selection for PA oe 0" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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line.byte 0x0D "PA1_CFG13,PA OE Select Register - High"
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bitfld.byte 0x0D 6.--7. " OE_SEL7 ,Data selection for PA oe 7" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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bitfld.byte 0x0D 4.--5. " OE_SEL6 ,Data selection for PA oe 6" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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textline " "
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bitfld.byte 0x0D 2.--3. " OE_SEL5 ,Data selection for PA oe 5" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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bitfld.byte 0x0D 0.--1. " OE_SEL4 ,Data selection for PA oe 4" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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line.byte 0x0E "PA1_CFG14,PA OE Sync Register"
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bitfld.byte 0x0E 6.--7. " OE_SYNC3 ,Synchronization options for dsi_to_oe[3]" "Transparent,Single sync,Constant 1,Constant 0"
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bitfld.byte 0x0E 4.--5. " OE_SYNC2 ,Synchronization options for dsi_to_oe[2]" "Transparent,Single sync,Constant 1,Constant 0"
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textline " "
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bitfld.byte 0x0E 2.--3. " OE_SYNC1 ,Synchronization options for dsi_to_oe[1]" "Transparent,Single sync,Constant 1,Constant 0"
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bitfld.byte 0x0E 0.--1. " OE_SYNC0 ,Synchronization options for dsi_to_oe[0]" "Transparent,Single sync,Constant 1,Constant 0"
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group.byte 0x20++0x0E
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line.byte 0x00 "PA2_CFG0,PA Data In Clock Control Register"
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bitfld.byte 0x00 6.--7. " NC ,Spare register bits" "0,1,2,3"
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bitfld.byte 0x00 5. " CLKIN_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted"
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bitfld.byte 0x00 4. " CLKIN_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted"
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textline " "
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bitfld.byte 0x00 2.--3. " CLKIN_EN_MODE ,Select one of four operating modes" "Off,On,Positive edge,Level sensitive"
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bitfld.byte 0x00 0.--1. " CLKIN_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
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line.byte 0x01 "PA2_CFG1,PA Data Out Clock Control Register"
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bitfld.byte 0x01 6.--7. " NC ,Spare register bits" "0,1,2,3"
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bitfld.byte 0x01 5. " CLKOUT_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted"
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bitfld.byte 0x01 4. " CLKOUT_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted"
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textline " "
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bitfld.byte 0x01 2.--3. " CLKOUT_EN_MODE ,Select one of four operating modes" "Off,On,Positive edge,Level sensitive"
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bitfld.byte 0x01 0.--1. " CLKOUT_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
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line.byte 0x02 "PA2_CFG2,PA Clock Select Register"
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bitfld.byte 0x02 4.--7. " CLKOUT_SEL ,Select out for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
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bitfld.byte 0x02 0.--3. " CLKIN_SEL ,Select in for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
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line.byte 0x03 "PA2_CFG3,PA Reset Select Register"
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bitfld.byte 0x03 7. " NC7 ,Spare register bit" "0,1"
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bitfld.byte 0x03 6. " RES_OUT_INV ,Select the polarity of the reset control" "Not inverted,Inverted"
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bitfld.byte 0x03 4.--5. " RES_OUT_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
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textline " "
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bitfld.byte 0x03 3. " NC0 ,Spare register bit" "0,1"
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bitfld.byte 0x03 2. " RES_IN_INV ,Select the polarity of the reset control" "Not inverted,Inverted"
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bitfld.byte 0x03 0.--1. " RES_IN_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
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line.byte 0x04 "PA2_CFG4,PA Reset Enable Register"
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bitfld.byte 0x04 3.--7. " NC7654 ,Spare register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.byte 0x04 2. " RES_OE_EN ,Enable the selected reset" "Disabled,Enabled"
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bitfld.byte 0x04 1. " RES_OUT_EN ,Enable the selected reset" "Disabled,Enabled"
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textline " "
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bitfld.byte 0x04 0. " RES_IN_EN ,Enable the selected reset" "Disabled,Enabled"
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line.byte 0x05 "PA2_CFG5,PA Reset Pin Select Register"
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bitfld.byte 0x05 3.--7. " NC7654 ,Spare register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.byte 0x05 0. " PIN_SEL ,Select port input to route to reset multiplexer" "0,1"
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line.byte 0x06 "PA2_CFG6,PA Input Data Sync Control Register - Low"
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bitfld.byte 0x06 6.--7. " IN_SYNC3 ,Synchronization selection for PA input 3" "Transparent,Single sync,Double sync,"
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bitfld.byte 0x06 4.--5. " IN_SYNC2 ,Synchronization selection for PA input 2" "Transparent,Single sync,Double sync,?..."
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textline " "
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bitfld.byte 0x06 2.--3. " IN_SYNC1 ,Synchronization selection for PA input 1" "Transparent,Single sync,Double sync,"
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bitfld.byte 0x06 0.--1. " IN_SYNC0 ,Synchronization selection for PA input 0" "Transparent,Single sync,Double sync,?..."
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line.byte 0x07 "PA2_CFG7,PA Input Data Sync Control Register - High"
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bitfld.byte 0x07 6.--7. " IN_SYNC7 ,Synchronization selection for PA input 7" "Transparent,Single sync,Double sync,"
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bitfld.byte 0x07 4.--5. " IN_SYNC6 ,Synchronization selection for PA input 6" "Transparent,Single sync,Double sync,?..."
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textline " "
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bitfld.byte 0x07 2.--3. " IN_SYNC5 ,Synchronization selection for PA input 5" "Transparent,Single sync,Double sync,"
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bitfld.byte 0x07 0.--1. " IN_SYNC4 ,Synchronization selection for PA input 4" "Transparent,Single sync,Double sync,?..."
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line.byte 0x08 "PA2_CFG8,PA Output Data Sync Control Register - Low"
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bitfld.byte 0x08 6.--7. " OUT_SYNC3 ,Synchronization selection for PA output 3" "Transparent,Single sync,Clock,Clock inverted"
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bitfld.byte 0x08 4.--5. " OUT_SYNC2 ,Synchronization selection for PA output 2" "Transparent,Single sync,Clock,Clock inverted"
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textline " "
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bitfld.byte 0x08 2.--3. " OUT_SYNC1 ,Synchronization selection for PA output 1" "Transparent,Single sync,Clock,Clock inverted"
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bitfld.byte 0x08 0.--1. " OUT_SYNC0 ,Synchronization selection for PA output 0" "Transparent,Single sync,Clock,Clock inverted"
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line.byte 0x09 "PA2_CFG9,PA Output Data Sync Control Register - High"
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bitfld.byte 0x09 6.--7. " OUT_SYNC7 ,Synchronization selection for PA output 7" "Transparent,Single sync,Clock,Clock inverted"
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bitfld.byte 0x09 4.--5. " OUT_SYNC6 ,Synchronization selection for PA output 6" "Transparent,Single sync,Clock,Clock inverted"
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textline " "
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bitfld.byte 0x09 2.--3. " OUT_SYNC5 ,Synchronization selection for PA output 5" "Transparent,Single sync,Clock,Clock inverted"
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bitfld.byte 0x09 0.--1. " OUT_SYNC4 ,Synchronization selection for PA output 4" "Transparent,Single sync,Clock,Clock inverted"
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line.byte 0x0A "PA2_CFG10,PA Output Data Select Register - Low"
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bitfld.byte 0x0A 6.--7. " DATA_SEL3 ,Data selection for PA output 3" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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bitfld.byte 0x0A 4.--5. " DATA_SEL2 ,Data selection for PA output 2" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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textline " "
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bitfld.byte 0x0A 2.--3. " DATA_SEL1 ,Data selection for PA output 1" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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bitfld.byte 0x0A 0.--1. " DATA_SEL0 ,Data selection for PA output 0" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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line.byte 0x0B "PA2_CFG11,PA Output Data Select Register - High"
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bitfld.byte 0x0B 6.--7. " DATA_SEL7 ,Data selection for PA output 7" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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bitfld.byte 0x0B 4.--5. " DATA_SEL6 ,Data selection for PA output 6" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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textline " "
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bitfld.byte 0x0B 2.--3. " DATA_SEL5 ,Data selection for PA output 5" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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bitfld.byte 0x0B 0.--1. " DATA_SEL4 ,Data selection for PA output 4" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
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line.byte 0x0C "PA2_CFG12,PA OE Select Register - Low"
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bitfld.byte 0x0C 6.--7. " OE_SEL3 ,Data selection for PA oe 3" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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bitfld.byte 0x0C 4.--5. " OE_SEL2 ,Data selection for PA oe 2" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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textline " "
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bitfld.byte 0x0C 2.--3. " OE_SEL1 ,Data selection for PA oe 1" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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bitfld.byte 0x0C 0.--1. " OE_SEL0 ,Data selection for PA oe 0" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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line.byte 0x0D "PA2_CFG13,PA OE Select Register - High"
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bitfld.byte 0x0D 6.--7. " OE_SEL7 ,Data selection for PA oe 7" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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bitfld.byte 0x0D 4.--5. " OE_SEL6 ,Data selection for PA oe 6" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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textline " "
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bitfld.byte 0x0D 2.--3. " OE_SEL5 ,Data selection for PA oe 5" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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bitfld.byte 0x0D 0.--1. " OE_SEL4 ,Data selection for PA oe 4" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
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line.byte 0x0E "PA2_CFG14,PA OE Sync Register"
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bitfld.byte 0x0E 6.--7. " OE_SYNC3 ,Synchronization options for dsi_to_oe[3]" "Transparent,Single sync,Constant 1,Constant 0"
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bitfld.byte 0x0E 4.--5. " OE_SYNC2 ,Synchronization options for dsi_to_oe[2]" "Transparent,Single sync,Constant 1,Constant 0"
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textline " "
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bitfld.byte 0x0E 2.--3. " OE_SYNC1 ,Synchronization options for dsi_to_oe[1]" "Transparent,Single sync,Constant 1,Constant 0"
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bitfld.byte 0x0E 0.--1. " OE_SYNC0 ,Synchronization options for dsi_to_oe[0]" "Transparent,Single sync,Constant 1,Constant 0"
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group.byte 0x30++0x0E
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line.byte 0x00 "PA3_CFG0,PA Data In Clock Control Register"
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bitfld.byte 0x00 6.--7. " NC ,Spare register bits" "0,1,2,3"
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bitfld.byte 0x00 5. " CLKIN_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted"
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bitfld.byte 0x00 4. " CLKIN_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted"
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textline " "
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bitfld.byte 0x00 2.--3. " CLKIN_EN_MODE ,Select one of four operating modes" "Off,On,Positive edge,Level sensitive"
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bitfld.byte 0x00 0.--1. " CLKIN_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
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line.byte 0x01 "PA3_CFG1,PA Data Out Clock Control Register"
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bitfld.byte 0x01 6.--7. " NC ,Spare register bits" "0,1,2,3"
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bitfld.byte 0x01 5. " CLKOUT_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted"
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bitfld.byte 0x01 4. " CLKOUT_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted"
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textline " "
|
|
bitfld.byte 0x01 2.--3. " CLKOUT_EN_MODE ,Select one of four operating modes" "Off,On,Positive edge,Level sensitive"
|
|
bitfld.byte 0x01 0.--1. " CLKOUT_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
|
|
line.byte 0x02 "PA3_CFG2,PA Clock Select Register"
|
|
bitfld.byte 0x02 4.--7. " CLKOUT_SEL ,Select out for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
|
|
bitfld.byte 0x02 0.--3. " CLKIN_SEL ,Select in for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
|
|
line.byte 0x03 "PA3_CFG3,PA Reset Select Register"
|
|
bitfld.byte 0x03 7. " NC7 ,Spare register bit" "0,1"
|
|
bitfld.byte 0x03 6. " RES_OUT_INV ,Select the polarity of the reset control" "Not inverted,Inverted"
|
|
bitfld.byte 0x03 4.--5. " RES_OUT_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
|
|
textline " "
|
|
bitfld.byte 0x03 3. " NC0 ,Spare register bit" "0,1"
|
|
bitfld.byte 0x03 2. " RES_IN_INV ,Select the polarity of the reset control" "Not inverted,Inverted"
|
|
bitfld.byte 0x03 0.--1. " RES_IN_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2"
|
|
line.byte 0x04 "PA3_CFG4,PA Reset Enable Register"
|
|
bitfld.byte 0x04 3.--7. " NC7654 ,Spare register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.byte 0x04 2. " RES_OE_EN ,Enable the selected reset" "Disabled,Enabled"
|
|
bitfld.byte 0x04 1. " RES_OUT_EN ,Enable the selected reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x04 0. " RES_IN_EN ,Enable the selected reset" "Disabled,Enabled"
|
|
line.byte 0x05 "PA3_CFG5,PA Reset Pin Select Register"
|
|
bitfld.byte 0x05 3.--7. " NC7654 ,Spare register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.byte 0x05 0. " PIN_SEL ,Select port input to route to reset multiplexer" "0,1"
|
|
line.byte 0x06 "PA3_CFG6,PA Input Data Sync Control Register - Low"
|
|
bitfld.byte 0x06 6.--7. " IN_SYNC3 ,Synchronization selection for PA input 3" "Transparent,Single sync,Double sync,"
|
|
bitfld.byte 0x06 4.--5. " IN_SYNC2 ,Synchronization selection for PA input 2" "Transparent,Single sync,Double sync,?..."
|
|
textline " "
|
|
bitfld.byte 0x06 2.--3. " IN_SYNC1 ,Synchronization selection for PA input 1" "Transparent,Single sync,Double sync,"
|
|
bitfld.byte 0x06 0.--1. " IN_SYNC0 ,Synchronization selection for PA input 0" "Transparent,Single sync,Double sync,?..."
|
|
line.byte 0x07 "PA3_CFG7,PA Input Data Sync Control Register - High"
|
|
bitfld.byte 0x07 6.--7. " IN_SYNC7 ,Synchronization selection for PA input 7" "Transparent,Single sync,Double sync,"
|
|
bitfld.byte 0x07 4.--5. " IN_SYNC6 ,Synchronization selection for PA input 6" "Transparent,Single sync,Double sync,?..."
|
|
textline " "
|
|
bitfld.byte 0x07 2.--3. " IN_SYNC5 ,Synchronization selection for PA input 5" "Transparent,Single sync,Double sync,"
|
|
bitfld.byte 0x07 0.--1. " IN_SYNC4 ,Synchronization selection for PA input 4" "Transparent,Single sync,Double sync,?..."
|
|
line.byte 0x08 "PA3_CFG8,PA Output Data Sync Control Register - Low"
|
|
bitfld.byte 0x08 6.--7. " OUT_SYNC3 ,Synchronization selection for PA output 3" "Transparent,Single sync,Clock,Clock inverted"
|
|
bitfld.byte 0x08 4.--5. " OUT_SYNC2 ,Synchronization selection for PA output 2" "Transparent,Single sync,Clock,Clock inverted"
|
|
textline " "
|
|
bitfld.byte 0x08 2.--3. " OUT_SYNC1 ,Synchronization selection for PA output 1" "Transparent,Single sync,Clock,Clock inverted"
|
|
bitfld.byte 0x08 0.--1. " OUT_SYNC0 ,Synchronization selection for PA output 0" "Transparent,Single sync,Clock,Clock inverted"
|
|
line.byte 0x09 "PA3_CFG9,PA Output Data Sync Control Register - High"
|
|
bitfld.byte 0x09 6.--7. " OUT_SYNC7 ,Synchronization selection for PA output 7" "Transparent,Single sync,Clock,Clock inverted"
|
|
bitfld.byte 0x09 4.--5. " OUT_SYNC6 ,Synchronization selection for PA output 6" "Transparent,Single sync,Clock,Clock inverted"
|
|
textline " "
|
|
bitfld.byte 0x09 2.--3. " OUT_SYNC5 ,Synchronization selection for PA output 5" "Transparent,Single sync,Clock,Clock inverted"
|
|
bitfld.byte 0x09 0.--1. " OUT_SYNC4 ,Synchronization selection for PA output 4" "Transparent,Single sync,Clock,Clock inverted"
|
|
line.byte 0x0A "PA3_CFG10,PA Output Data Select Register - Low"
|
|
bitfld.byte 0x0A 6.--7. " DATA_SEL3 ,Data selection for PA output 3" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
bitfld.byte 0x0A 4.--5. " DATA_SEL2 ,Data selection for PA output 2" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
textline " "
|
|
bitfld.byte 0x0A 2.--3. " DATA_SEL1 ,Data selection for PA output 1" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
bitfld.byte 0x0A 0.--1. " DATA_SEL0 ,Data selection for PA output 0" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
line.byte 0x0B "PA3_CFG11,PA Output Data Select Register - High"
|
|
bitfld.byte 0x0B 6.--7. " DATA_SEL7 ,Data selection for PA output 7" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
bitfld.byte 0x0B 4.--5. " DATA_SEL6 ,Data selection for PA output 6" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
textline " "
|
|
bitfld.byte 0x0B 2.--3. " DATA_SEL5 ,Data selection for PA output 5" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
bitfld.byte 0x0B 0.--1. " DATA_SEL4 ,Data selection for PA output 4" "DSI output 0,DSI output 1,DSI output 2,DSI output 3"
|
|
line.byte 0x0C "PA3_CFG12,PA OE Select Register - Low"
|
|
bitfld.byte 0x0C 6.--7. " OE_SEL3 ,Data selection for PA oe 3" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
bitfld.byte 0x0C 4.--5. " OE_SEL2 ,Data selection for PA oe 2" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
textline " "
|
|
bitfld.byte 0x0C 2.--3. " OE_SEL1 ,Data selection for PA oe 1" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
bitfld.byte 0x0C 0.--1. " OE_SEL0 ,Data selection for PA oe 0" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
line.byte 0x0D "PA3_CFG13,PA OE Select Register - High"
|
|
bitfld.byte 0x0D 6.--7. " OE_SEL7 ,Data selection for PA oe 7" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
bitfld.byte 0x0D 4.--5. " OE_SEL6 ,Data selection for PA oe 6" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
textline " "
|
|
bitfld.byte 0x0D 2.--3. " OE_SEL5 ,Data selection for PA oe 5" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
bitfld.byte 0x0D 0.--1. " OE_SEL4 ,Data selection for PA oe 4" "Synchronized dsi oe output 0,Synchronized dsi oe output 1,Synchronized dsi oe output 2,Synchronized dsi oe output 3"
|
|
line.byte 0x0E "PA3_CFG14,PA OE Sync Register"
|
|
bitfld.byte 0x0E 6.--7. " OE_SYNC3 ,Synchronization options for dsi_to_oe[3]" "Transparent,Single sync,Constant 1,Constant 0"
|
|
bitfld.byte 0x0E 4.--5. " OE_SYNC2 ,Synchronization options for dsi_to_oe[2]" "Transparent,Single sync,Constant 1,Constant 0"
|
|
textline " "
|
|
bitfld.byte 0x0E 2.--3. " OE_SYNC1 ,Synchronization options for dsi_to_oe[1]" "Transparent,Single sync,Constant 1,Constant 0"
|
|
bitfld.byte 0x0E 0.--1. " OE_SYNC0 ,Synchronization options for dsi_to_oe[0]" "Transparent,Single sync,Constant 1,Constant 0"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "PASS MMIO (Programmable Analog Sub System MMIO)"
|
|
base ad:0x403F0000
|
|
width 12.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "INTR_CAUSE,Interrupt Cause Register"
|
|
bitfld.long 0x00 1. " CTB1_INT ,CTB1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " CTB0_INT ,CTB0 interrupt pending" "Not pending,Pending"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DFT_CTRL,DFT Control Register"
|
|
bitfld.long 0x00 0. " DSAB_ADFT_RES_EN ,Close the switch to connect the DSAB ADFT resistor to the AMUXBUS" "Disabled,Enabled"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "DSAB_TRIM,DSAB Trim Bits"
|
|
bitfld.long 0x00 0.--3. " IBIAS_TRIM ,IBIAS trim" "Highest,14,13,12,11,10,9,8,7,6,5,4,3,2,1,Lowest"
|
|
width 0xB
|
|
tree.end
|
|
tree "PERI (Peripheral Interconnect)"
|
|
base ad:0x40010000
|
|
width 20.
|
|
if (((per.l(ad:0x40010000))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40010000))&0x40000000)==0x40000000)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "DIV_CMD,Divider Command Register"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DIV_CMD,Divider Command Register"
|
|
bitfld.long 0x00 31. " ENABLE ,Clock divider enable command" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PA_SEL_TYPE ,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command" "8.0,16.0,16.5,25.5"
|
|
bitfld.long 0x00 8.--13. " PA_SEL_DIV ,Specifies the divider to which phase alignment is performed for the clock enable command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies the divider type of the divider on which the command is performed" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--5. " SEL_DIV ,Specifies the divider on which the command is performed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40010000))&0x40000000)==0x40000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DIV_CMD,Divider Command Register"
|
|
bitfld.long 0x00 30. " DISABLE ,Clock divider disable command" "No,Yes"
|
|
bitfld.long 0x00 14.--15. " PA_SEL_TYPE ,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command" "8.0,16.0,16.5,25.5"
|
|
bitfld.long 0x00 8.--13. " PA_SEL_DIV ,Specifies the divider to which phase alignment is performed for the clock enable command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies the divider type of the divider on which the command is performed" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--5. " SEL_DIV ,Specifies the divider on which the command is performed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DIV_CMD,Divider Command Register"
|
|
bitfld.long 0x00 31. " ENABLE ,Clock divider enable command" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DISABLE ,Clock divider disable command" "No,Yes"
|
|
bitfld.long 0x00 14.--15. " PA_SEL_TYPE ,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command" "8.0,16.0,16.5,25.5"
|
|
bitfld.long 0x00 8.--13. " PA_SEL_DIV ,Specifies the divider to which phase alignment is performed for the clock enable command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies the divider type of the divider on which the command is performed" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--5. " SEL_DIV ,Specifies the divider on which the command is performed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PCLK_CTL0,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "PCLK_CTL1,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "PCLK_CTL2,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "PCLK_CTL3,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PCLK_CTL4,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "PCLK_CTL5,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PCLK_CTL6,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PCLK_CTL7,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PCLK_CTL8,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PCLK_CTL9,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "PCLK_CTL10,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "PCLK_CTL11,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PCLK_CTL12,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "PCLK_CTL13,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "PCLK_CTL14,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "PCLK_CTL15,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "DIV_16_CTL0,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DIV_16_CTL1,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "DIV_16_CTL2,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "DIV_16_CTL3,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "DIV_16_CTL4,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DIV_16_CTL5,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "DIV_16_CTL6,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "DIV_16_CTL7,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "DIV_16_CTL8,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "DIV_16_CTL9,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "DIV_16_5_CTL0,Divider Control Register For 16.5 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by FRAC5_DIV/32" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
rbitfld.long 0x00 0. " EN ,Divider enable" "Disabled,Enabled"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "DIV_16_5_CTL1,Divider Control Register For 16.5 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by FRAC5_DIV/32" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
rbitfld.long 0x00 0. " EN ,Divider enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PCLK_CTL0,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "PCLK_CTL1,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "PCLK_CTL2,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "PCLK_CTL3,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PCLK_CTL4,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "PCLK_CTL5,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PCLK_CTL6,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PCLK_CTL7,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PCLK_CTL8,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PCLK_CTL9,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "PCLK_CTL10,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "PCLK_CTL11,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PCLK_CTL12,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "PCLK_CTL13,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "PCLK_CTL14,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "PCLK_CTL15,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "PCLK_CTL16,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "DIV_16_CTL0,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DIV_16_CTL1,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "DIV_16_CTL2,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "DIV_16_CTL3,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "DIV_16_CTL4,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DIV_16_CTL5,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "DIV_16_CTL6,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "DIV_16_5_CTL0,Divider Control Register For 16.5 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by FRAC5_DIV/32" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
bitfld.long 0x00 0. " EN ,Divider enable" "Disabled,Enabled"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "DIV_16_5_CTL1,Divider Control Register For 16.5 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by FRAC5_DIV/32" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
bitfld.long 0x00 0. " EN ,Divider enable" "Disabled,Enabled"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "DIV_16_5_CTL2,Divider Control Register For 16.5 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by FRAC5_DIV/32" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
bitfld.long 0x00 0. " EN ,Divider enable" "Disabled,Enabled"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "DIV_24_5_CTL,Divider Control Register For 24.5 Divider"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " INT24_DIV ,23-bit integer division by 1+INT24_DIV"
|
|
bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by FRAC5_DIV/32" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
rbitfld.long 0x00 0. " EN ,Divider enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40010000+0x600))&0x80000000)==0x80000000)
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "TR_CTL,Trigger Control Register"
|
|
bitfld.long 0x00 31. " TR_ACT ,SW sets this field to '1' by to activate a trigger" "Deactivated,Activated"
|
|
bitfld.long 0x00 30. " TR_OUT ,Specifies whether trigger activation is for specific input or output trigger of the trigger multiplexer" "Input,Output"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TR_COUNT ,8-bit amount of cycles a specific trigger is activated"
|
|
bitfld.long 0x00 8.--11. " TR_GROUP ,Specifies the trigger group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " TR_SEL ,7-bit specifies the activated trigger when TR_ACT is '1'"
|
|
else
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "TR_CTL,Trigger Control Register"
|
|
bitfld.long 0x00 31. " TR_ACT ,SW sets this field to '1' by to activate a trigger" "Deactivated,Activated"
|
|
bitfld.long 0x00 30. " TR_OUT ,Specifies whether trigger activation is for specific input or output trigger of the trigger multiplexer" "Input,Output"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TR_COUNT ,8-bit amount of cycles a specific trigger is activated"
|
|
bitfld.long 0x00 8.--11. " TR_GROUP ,Specifies the trigger group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "ROM Table"
|
|
base ad:0xF0000000
|
|
width 20.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ADDR,Link to Cortex M0 ROM Table"
|
|
hexmask.long.tbyte 0x00 12.--31. 1. " ADDR_OFFSET ,Address offset of the Cortex-M0 ROM Table base address"
|
|
bitfld.long 0x00 1. " FORMAT_32BIT ,ROM Table format" "8-bit,32-bit"
|
|
bitfld.long 0x00 0. " PRESENT ,Entry present" "No present,Present"
|
|
rgroup.long 0xFCC++0x07
|
|
line.long 0x00 "DID,Device Type Identifier Register"
|
|
line.long 0x04 "PID4,Peripheral Identification Register 4"
|
|
bitfld.long 0x04 4.--7. " COUNT ,Size of ROM Table" "4KByte,8KByte,16KByte,32KByte,64KByte,128KByte,256KByte,512KByte,1024KByte,2048KByte,4096KByte,8192KByte,16384KByte,32768KByte,65536KByte,131072KByte"
|
|
bitfld.long 0x04 0.--3. " JEP_CONTINUATION ,JEP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFD4++0x03
|
|
line.long 0x00 "PID5,Peripheral Identification Register 5"
|
|
rgroup.long 0xFD8++0x03
|
|
line.long 0x00 "PID6,Peripheral Identification Register 6"
|
|
rgroup.long 0xFDC++0x03
|
|
line.long 0x00 "PID7,Peripheral Identification Register 7"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PN_MIN ,JEP106 part number"
|
|
line.long 0x04 "PID1,Peripheral Identification Register 1"
|
|
bitfld.long 0x04 4.--7. " JEPID_MIN ,JEP106 vendor id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " PN_MAJ ,JEP106 part number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "PID2,Peripheral Identification Register 2"
|
|
bitfld.long 0x08 4.--7. " REV ,Major Revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--2. " JEPID_MAJ ,JEP106 vendor id" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "PID3,Peripheral Identification Register 3"
|
|
bitfld.long 0x0C 4.--7. " REV_AND ,Minor REVision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. " CM ,Customer modified field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xFF0++0x03
|
|
line.long 0x00 "CID0,Component Identification Register 0"
|
|
rgroup.long 0xFF4++0x03
|
|
line.long 0x00 "CID1,Component Identification Register 1"
|
|
rgroup.long 0xFF8++0x03
|
|
line.long 0x00 "CID2,Component Identification Register 2"
|
|
rgroup.long 0xFFC++0x03
|
|
line.long 0x00 "CID3,Component Identification Register 3"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("CY8C42*-BL*")
|
|
tree.open "ROUTE"
|
|
tree "ROUTE0"
|
|
base ad:0x400F3100
|
|
width 22.
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC0,UDB Channel HC Tile Configuration Horizontal Channel 0"
|
|
group.byte 0x101++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC1,UDB Channel HC Tile Configuration Horizontal Channel 1"
|
|
group.byte 0x102++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC2,UDB Channel HC Tile Configuration Horizontal Channel 2"
|
|
group.byte 0x103++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC3,UDB Channel HC Tile Configuration Horizontal Channel 3"
|
|
group.byte 0x104++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC4,UDB Channel HC Tile Configuration Horizontal Channel 4"
|
|
group.byte 0x105++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC5,UDB Channel HC Tile Configuration Horizontal Channel 5"
|
|
group.byte 0x106++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC6,UDB Channel HC Tile Configuration Horizontal Channel 6"
|
|
group.byte 0x107++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC7,UDB Channel HC Tile Configuration Horizontal Channel 7"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC8,UDB Channel HC Tile Configuration Horizontal Channel 8"
|
|
group.byte 0x109++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC9,UDB Channel HC Tile Configuration Horizontal Channel 9"
|
|
group.byte 0x10A++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC10,UDB Channel HC Tile Configuration Horizontal Channel 10"
|
|
group.byte 0x10B++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC11,UDB Channel HC Tile Configuration Horizontal Channel 11"
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC12,UDB Channel HC Tile Configuration Horizontal Channel 12"
|
|
group.byte 0x10D++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC13,UDB Channel HC Tile Configuration Horizontal Channel 13"
|
|
group.byte 0x10E++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC14,UDB Channel HC Tile Configuration Horizontal Channel 14"
|
|
group.byte 0x10F++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC15,UDB Channel HC Tile Configuration Horizontal Channel 15"
|
|
group.byte 0x110++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC16,UDB Channel HC Tile Configuration Horizontal Channel 16"
|
|
group.byte 0x111++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC17,UDB Channel HC Tile Configuration Horizontal Channel 17"
|
|
group.byte 0x112++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC18,UDB Channel HC Tile Configuration Horizontal Channel 18"
|
|
group.byte 0x113++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC19,UDB Channel HC Tile Configuration Horizontal Channel 19"
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC20,UDB Channel HC Tile Configuration Horizontal Channel 20"
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC21,UDB Channel HC Tile Configuration Horizontal Channel 21"
|
|
group.byte 0x116++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC22,UDB Channel HC Tile Configuration Horizontal Channel 22"
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC23,UDB Channel HC Tile Configuration Horizontal Channel 23"
|
|
group.byte 0x118++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC24,UDB Channel HC Tile Configuration Horizontal Channel 24"
|
|
group.byte 0x119++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC25,UDB Channel HC Tile Configuration Horizontal Channel 25"
|
|
group.byte 0x11A++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC26,UDB Channel HC Tile Configuration Horizontal Channel 26"
|
|
group.byte 0x11B++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC27,UDB Channel HC Tile Configuration Horizontal Channel 27"
|
|
group.byte 0x11C++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC28,UDB Channel HC Tile Configuration Horizontal Channel 28"
|
|
group.byte 0x11D++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC29,UDB Channel HC Tile Configuration Horizontal Channel 29"
|
|
group.byte 0x11E++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC30,UDB Channel HC Tile Configuration Horizontal Channel 30"
|
|
group.byte 0x11F++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC31,UDB Channel HC Tile Configuration Horizontal Channel 31"
|
|
group.byte 0x120++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC32,UDB Channel HC Tile Configuration Horizontal Channel 32"
|
|
group.byte 0x121++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC33,UDB Channel HC Tile Configuration Horizontal Channel 33"
|
|
group.byte 0x122++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC34,UDB Channel HC Tile Configuration Horizontal Channel 34"
|
|
group.byte 0x123++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC35,UDB Channel HC Tile Configuration Horizontal Channel 35"
|
|
group.byte 0x124++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC36,UDB Channel HC Tile Configuration Horizontal Channel 36"
|
|
group.byte 0x125++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC37,UDB Channel HC Tile Configuration Horizontal Channel 37"
|
|
group.byte 0x126++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC38,UDB Channel HC Tile Configuration Horizontal Channel 38"
|
|
group.byte 0x127++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC39,UDB Channel HC Tile Configuration Horizontal Channel 39"
|
|
group.byte 0x128++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC40,UDB Channel HC Tile Configuration Horizontal Channel 40"
|
|
group.byte 0x129++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC41,UDB Channel HC Tile Configuration Horizontal Channel 41"
|
|
group.byte 0x12A++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC42,UDB Channel HC Tile Configuration Horizontal Channel 42"
|
|
group.byte 0x12B++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC43,UDB Channel HC Tile Configuration Horizontal Channel 43"
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC44,UDB Channel HC Tile Configuration Horizontal Channel 44"
|
|
group.byte 0x12D++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC45,UDB Channel HC Tile Configuration Horizontal Channel 45"
|
|
group.byte 0x12E++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC46,UDB Channel HC Tile Configuration Horizontal Channel 46"
|
|
group.byte 0x12F++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC47,UDB Channel HC Tile Configuration Horizontal Channel 47"
|
|
group.byte 0x130++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC48,UDB Channel HC Tile Configuration Horizontal Channel 48"
|
|
group.byte 0x131++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC49,UDB Channel HC Tile Configuration Horizontal Channel 49"
|
|
group.byte 0x132++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC50,UDB Channel HC Tile Configuration Horizontal Channel 50"
|
|
group.byte 0x133++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC51,UDB Channel HC Tile Configuration Horizontal Channel 51"
|
|
group.byte 0x134++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC52,UDB Channel HC Tile Configuration Horizontal Channel 52"
|
|
group.byte 0x135++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC53,UDB Channel HC Tile Configuration Horizontal Channel 53"
|
|
group.byte 0x136++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC54,UDB Channel HC Tile Configuration Horizontal Channel 54"
|
|
group.byte 0x137++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC55,UDB Channel HC Tile Configuration Horizontal Channel 55"
|
|
group.byte 0x138++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC56,UDB Channel HC Tile Configuration Horizontal Channel 56"
|
|
group.byte 0x139++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC57,UDB Channel HC Tile Configuration Horizontal Channel 57"
|
|
group.byte 0x13A++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC58,UDB Channel HC Tile Configuration Horizontal Channel 58"
|
|
group.byte 0x13B++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC59,UDB Channel HC Tile Configuration Horizontal Channel 59"
|
|
group.byte 0x13C++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC60,UDB Channel HC Tile Configuration Horizontal Channel 60"
|
|
group.byte 0x13D++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC61,UDB Channel HC Tile Configuration Horizontal Channel 61"
|
|
group.byte 0x13E++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC62,UDB Channel HC Tile Configuration Horizontal Channel 62"
|
|
group.byte 0x13F++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC63,UDB Channel HC Tile Configuration Horizontal Channel 63"
|
|
group.byte 0x140++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC64,UDB Channel HC Tile Configuration Horizontal Channel 64"
|
|
group.byte 0x141++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC65,UDB Channel HC Tile Configuration Horizontal Channel 65"
|
|
group.byte 0x142++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC66,UDB Channel HC Tile Configuration Horizontal Channel 66"
|
|
group.byte 0x143++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC67,UDB Channel HC Tile Configuration Horizontal Channel 67"
|
|
group.byte 0x144++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC68,UDB Channel HC Tile Configuration Horizontal Channel 68"
|
|
group.byte 0x145++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC69,UDB Channel HC Tile Configuration Horizontal Channel 69"
|
|
group.byte 0x146++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC70,UDB Channel HC Tile Configuration Horizontal Channel 70"
|
|
group.byte 0x147++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC71,UDB Channel HC Tile Configuration Horizontal Channel 71"
|
|
group.byte 0x148++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC72,UDB Channel HC Tile Configuration Horizontal Channel 72"
|
|
group.byte 0x149++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC73,UDB Channel HC Tile Configuration Horizontal Channel 73"
|
|
group.byte 0x14A++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC74,UDB Channel HC Tile Configuration Horizontal Channel 74"
|
|
group.byte 0x14B++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC75,UDB Channel HC Tile Configuration Horizontal Channel 75"
|
|
group.byte 0x14C++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC76,UDB Channel HC Tile Configuration Horizontal Channel 76"
|
|
group.byte 0x14D++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC77,UDB Channel HC Tile Configuration Horizontal Channel 77"
|
|
group.byte 0x14E++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC78,UDB Channel HC Tile Configuration Horizontal Channel 78"
|
|
group.byte 0x14F++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC79,UDB Channel HC Tile Configuration Horizontal Channel 79"
|
|
group.byte 0x150++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC80,UDB Channel HC Tile Configuration Horizontal Channel 80"
|
|
group.byte 0x151++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC81,UDB Channel HC Tile Configuration Horizontal Channel 81"
|
|
group.byte 0x152++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC82,UDB Channel HC Tile Configuration Horizontal Channel 82"
|
|
group.byte 0x153++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC83,UDB Channel HC Tile Configuration Horizontal Channel 83"
|
|
group.byte 0x154++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC84,UDB Channel HC Tile Configuration Horizontal Channel 84"
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC85,UDB Channel HC Tile Configuration Horizontal Channel 85"
|
|
group.byte 0x156++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC86,UDB Channel HC Tile Configuration Horizontal Channel 86"
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC87,UDB Channel HC Tile Configuration Horizontal Channel 87"
|
|
group.byte 0x158++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC88,UDB Channel HC Tile Configuration Horizontal Channel 88"
|
|
group.byte 0x159++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC89,UDB Channel HC Tile Configuration Horizontal Channel 89"
|
|
group.byte 0x15A++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC90,UDB Channel HC Tile Configuration Horizontal Channel 90"
|
|
group.byte 0x15B++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC91,UDB Channel HC Tile Configuration Horizontal Channel 91"
|
|
group.byte 0x15C++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC92,UDB Channel HC Tile Configuration Horizontal Channel 92"
|
|
group.byte 0x15D++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC93,UDB Channel HC Tile Configuration Horizontal Channel 93"
|
|
group.byte 0x15E++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC94,UDB Channel HC Tile Configuration Horizontal Channel 94"
|
|
group.byte 0x15F++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC95,UDB Channel HC Tile Configuration Horizontal Channel 95"
|
|
group.byte 0x160++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC96,UDB Channel HC Tile Configuration Horizontal Channel 96"
|
|
group.byte 0x161++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC97,UDB Channel HC Tile Configuration Horizontal Channel 97"
|
|
group.byte 0x162++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC98,UDB Channel HC Tile Configuration Horizontal Channel 98"
|
|
group.byte 0x163++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC99,UDB Channel HC Tile Configuration Horizontal Channel 99"
|
|
group.byte 0x164++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC100,UDB Channel HC Tile Configuration Horizontal Channel 100"
|
|
group.byte 0x165++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC101,UDB Channel HC Tile Configuration Horizontal Channel 101"
|
|
group.byte 0x166++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC102,UDB Channel HC Tile Configuration Horizontal Channel 102"
|
|
group.byte 0x167++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC103,UDB Channel HC Tile Configuration Horizontal Channel 103"
|
|
group.byte 0x168++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC104,UDB Channel HC Tile Configuration Horizontal Channel 104"
|
|
group.byte 0x169++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC105,UDB Channel HC Tile Configuration Horizontal Channel 105"
|
|
group.byte 0x16A++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC106,UDB Channel HC Tile Configuration Horizontal Channel 106"
|
|
group.byte 0x16B++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC107,UDB Channel HC Tile Configuration Horizontal Channel 107"
|
|
group.byte 0x16C++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC108,UDB Channel HC Tile Configuration Horizontal Channel 108"
|
|
group.byte 0x16D++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC109,UDB Channel HC Tile Configuration Horizontal Channel 109"
|
|
group.byte 0x16E++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC110,UDB Channel HC Tile Configuration Horizontal Channel 110"
|
|
group.byte 0x16F++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC111,UDB Channel HC Tile Configuration Horizontal Channel 111"
|
|
group.byte 0x170++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC112,UDB Channel HC Tile Configuration Horizontal Channel 112"
|
|
group.byte 0x171++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC113,UDB Channel HC Tile Configuration Horizontal Channel 113"
|
|
group.byte 0x172++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC114,UDB Channel HC Tile Configuration Horizontal Channel 114"
|
|
group.byte 0x173++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC115,UDB Channel HC Tile Configuration Horizontal Channel 115"
|
|
group.byte 0x174++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC116,UDB Channel HC Tile Configuration Horizontal Channel 116"
|
|
group.byte 0x175++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC117,UDB Channel HC Tile Configuration Horizontal Channel 117"
|
|
group.byte 0x176++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC118,UDB Channel HC Tile Configuration Horizontal Channel 118"
|
|
group.byte 0x177++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC119,UDB Channel HC Tile Configuration Horizontal Channel 119"
|
|
group.byte 0x178++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC120,UDB Channel HC Tile Configuration Horizontal Channel 120"
|
|
group.byte 0x179++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC121,UDB Channel HC Tile Configuration Horizontal Channel 121"
|
|
group.byte 0x17A++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC122,UDB Channel HC Tile Configuration Horizontal Channel 122"
|
|
group.byte 0x17B++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC123,UDB Channel HC Tile Configuration Horizontal Channel 123"
|
|
group.byte 0x17C++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC124,UDB Channel HC Tile Configuration Horizontal Channel 124"
|
|
group.byte 0x17D++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC125,UDB Channel HC Tile Configuration Horizontal Channel 125"
|
|
group.byte 0x17E++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC126,UDB Channel HC Tile Configuration Horizontal Channel 126"
|
|
group.byte 0x17F++0x00
|
|
line.byte 0x00 "P0_ROUTE_HC127,UDB Channel HC Tile Configuration Horizontal Channel 127"
|
|
group.byte 0x180++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L0,UDB Channel HV Tile Configuration Left 0"
|
|
group.byte 0x181++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L1,UDB Channel HV Tile Configuration Left 1"
|
|
group.byte 0x182++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L2,UDB Channel HV Tile Configuration Left 2"
|
|
group.byte 0x183++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L3,UDB Channel HV Tile Configuration Left 3"
|
|
group.byte 0x184++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L4,UDB Channel HV Tile Configuration Left 4"
|
|
group.byte 0x185++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L5,UDB Channel HV Tile Configuration Left 5"
|
|
group.byte 0x186++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L6,UDB Channel HV Tile Configuration Left 6"
|
|
group.byte 0x187++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L7,UDB Channel HV Tile Configuration Left 7"
|
|
group.byte 0x188++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L8,UDB Channel HV Tile Configuration Left 8"
|
|
group.byte 0x189++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L9,UDB Channel HV Tile Configuration Left 9"
|
|
group.byte 0x18A++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L10,UDB Channel HV Tile Configuration Left 10"
|
|
group.byte 0x18B++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L11,UDB Channel HV Tile Configuration Left 11"
|
|
group.byte 0x18C++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L12,UDB Channel HV Tile Configuration Left 12"
|
|
group.byte 0x18D++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L13,UDB Channel HV Tile Configuration Left 13"
|
|
group.byte 0x18E++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L14,UDB Channel HV Tile Configuration Left 14"
|
|
group.byte 0x18F++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_L15,UDB Channel HV Tile Configuration Left 15"
|
|
group.byte 0x190++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS0,UDB Channel HS Tile Configuration Horizontal Segmentation 0"
|
|
group.byte 0x191++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS1,UDB Channel HS Tile Configuration Horizontal Segmentation 1"
|
|
group.byte 0x192++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS2,UDB Channel HS Tile Configuration Horizontal Segmentation 2"
|
|
group.byte 0x193++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS3,UDB Channel HS Tile Configuration Horizontal Segmentation 3"
|
|
group.byte 0x194++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS4,UDB Channel HS Tile Configuration Horizontal Segmentation 4"
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS5,UDB Channel HS Tile Configuration Horizontal Segmentation 5"
|
|
group.byte 0x196++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS6,UDB Channel HS Tile Configuration Horizontal Segmentation 6"
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS7,UDB Channel HS Tile Configuration Horizontal Segmentation 7"
|
|
group.byte 0x198++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS8,UDB Channel HS Tile Configuration Horizontal Segmentation 8"
|
|
group.byte 0x199++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS9,UDB Channel HS Tile Configuration Horizontal Segmentation 9"
|
|
group.byte 0x19A++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS10,UDB Channel HS Tile Configuration Horizontal Segmentation 10"
|
|
group.byte 0x19B++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS11,UDB Channel HS Tile Configuration Horizontal Segmentation 11"
|
|
group.byte 0x19C++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS12,UDB Channel HS Tile Configuration Horizontal Segmentation 12"
|
|
group.byte 0x19D++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS13,UDB Channel HS Tile Configuration Horizontal Segmentation 13"
|
|
group.byte 0x19E++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS14,UDB Channel HS Tile Configuration Horizontal Segmentation 14"
|
|
group.byte 0x19F++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS15,UDB Channel HS Tile Configuration Horizontal Segmentation 15"
|
|
group.byte 0x1A0++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS16,UDB Channel HS Tile Configuration Horizontal Segmentation 16"
|
|
group.byte 0x1A1++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS17,UDB Channel HS Tile Configuration Horizontal Segmentation 17"
|
|
group.byte 0x1A2++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS18,UDB Channel HS Tile Configuration Horizontal Segmentation 18"
|
|
group.byte 0x1A3++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS19,UDB Channel HS Tile Configuration Horizontal Segmentation 19"
|
|
group.byte 0x1A4++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS20,UDB Channel HS Tile Configuration Horizontal Segmentation 20"
|
|
group.byte 0x1A5++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS21,UDB Channel HS Tile Configuration Horizontal Segmentation 21"
|
|
group.byte 0x1A6++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS22,UDB Channel HS Tile Configuration Horizontal Segmentation 22"
|
|
group.byte 0x1A7++0x00
|
|
line.byte 0x00 "P0_ROUTE_HS23,UDB Channel HS Tile Configuration Horizontal Segmentation 23"
|
|
group.byte 0x1A8++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R0,UDB Channel HV Tile Configuration Right 0"
|
|
group.byte 0x1A9++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R1,UDB Channel HV Tile Configuration Right 1"
|
|
group.byte 0x1AA++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R2,UDB Channel HV Tile Configuration Right 2"
|
|
group.byte 0x1AB++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R3,UDB Channel HV Tile Configuration Right 3"
|
|
group.byte 0x1AC++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R4,UDB Channel HV Tile Configuration Right 4"
|
|
group.byte 0x1AD++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R5,UDB Channel HV Tile Configuration Right 5"
|
|
group.byte 0x1AE++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R6,UDB Channel HV Tile Configuration Right 6"
|
|
group.byte 0x1AF++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R7,UDB Channel HV Tile Configuration Right 7"
|
|
group.byte 0x1B0++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R8,UDB Channel HV Tile Configuration Right 8"
|
|
group.byte 0x1B1++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R9,UDB Channel HV Tile Configuration Right 9"
|
|
group.byte 0x1B2++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R10,UDB Channel HV Tile Configuration Right 10"
|
|
group.byte 0x1B3++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R11,UDB Channel HV Tile Configuration Right 11"
|
|
group.byte 0x1B4++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R12,UDB Channel HV Tile Configuration Right 12"
|
|
group.byte 0x1B5++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R13,UDB Channel HV Tile Configuration Right 13"
|
|
group.byte 0x1B6++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R14,UDB Channel HV Tile Configuration Right 14"
|
|
group.byte 0x1B7++0x00
|
|
line.byte 0x00 "P0_ROUTE_HV_R15,UDB Channel HV Tile Configuration Right 15"
|
|
group.word 0x1C0++0x01
|
|
line.word 0x00 "P0_ROUTE_PLD0IN0,UDB Channel PI Tile Configuration PLD Input 00"
|
|
bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1C2++0x01
|
|
line.word 0x00 "P0_ROUTE_PLD0IN1,UDB Channel PI Tile Configuration PLD Input 01"
|
|
bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1C4++0x01
|
|
line.word 0x00 "P0_ROUTE_PLD0IN2,UDB Channel PI Tile Configuration PLD Input 02"
|
|
bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1CA++0x01
|
|
line.word 0x00 "P0_ROUTE_PLD1IN0,UDB Channel PI Tile Configuration PLD Input 10"
|
|
bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1CC++0x01
|
|
line.word 0x00 "P0_ROUTE_PLD1IN1,UDB Channel PI Tile Configuration PLD Input 11"
|
|
bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1CE++0x01
|
|
line.word 0x00 "P0_ROUTE_PLD1IN2,UDB Channel PI Tile Configuration PLD Input 12"
|
|
bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1D0++0x00
|
|
line.byte 0x00 "P0_ROUTE_DPIN0,UDB Channel PI Tile Configuration Datapath Input 0"
|
|
bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1D2++0x00
|
|
line.byte 0x00 "P0_ROUTE_DPIN1,UDB Channel PI Tile Configuration Datapath Input 1"
|
|
bitfld.byte 0x00 4.--5. " PI_BOT2 ,RAM configuration bits (2) for BOTTOM UDB port interface configuration" "0,1,2,3"
|
|
bitfld.byte 0x00 2.--3. " PI_TOP2 ,RAM configuration bits (2) for TOP UDB port interface configuration" "0,1,2,3"
|
|
group.byte 0x1D6++0x00
|
|
line.byte 0x00 "P0_ROUTE_SCIN,UDB Channel PI Tile Configuration Status / Control Blocks Input Control"
|
|
bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1D8++0x00
|
|
line.byte 0x00 "P0_ROUTE_SCION,UDB Channel PI Tile Configuration Status / Control Blocks Input / Output Control"
|
|
bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1DE++0x00
|
|
line.byte 0x00 "P0_ROUTE_RCIN,UDB Channel PI Tile Configuration Reset and Clock Blocks Input Control"
|
|
bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1E0++0x01
|
|
line.word 0x00 "P0_ROUTE_VS0,UDB Channel VS Tile Configuration Vertical Segmentation 0"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1E2++0x01
|
|
line.word 0x00 "P0_ROUTE_VS1,UDB Channel VS Tile Configuration Vertical Segmentation 1"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1E4++0x01
|
|
line.word 0x00 "P0_ROUTE_VS2,UDB Channel VS Tile Configuration Vertical Segmentation 2"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1E6++0x01
|
|
line.word 0x00 "P0_ROUTE_VS3,UDB Channel VS Tile Configuration Vertical Segmentation 3"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1E8++0x01
|
|
line.word 0x00 "P0_ROUTE_VS4,UDB Channel VS Tile Configuration Vertical Segmentation 4"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1EA++0x01
|
|
line.word 0x00 "P0_ROUTE_VS5,UDB Channel VS Tile Configuration Vertical Segmentation 5"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1EC++0x01
|
|
line.word 0x00 "P0_ROUTE_VS6,UDB Channel VS Tile Configuration Vertical Segmentation 6"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1EE++0x01
|
|
line.word 0x00 "P0_ROUTE_VS7,UDB Channel VS Tile Configuration Vertical Segmentation 7"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0xB
|
|
tree.end
|
|
tree "ROUTE1"
|
|
base ad:0x400F3300
|
|
width 22.
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC0,UDB Channel HC Tile Configuration Horizontal Channel 0"
|
|
group.byte 0x101++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC1,UDB Channel HC Tile Configuration Horizontal Channel 1"
|
|
group.byte 0x102++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC2,UDB Channel HC Tile Configuration Horizontal Channel 2"
|
|
group.byte 0x103++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC3,UDB Channel HC Tile Configuration Horizontal Channel 3"
|
|
group.byte 0x104++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC4,UDB Channel HC Tile Configuration Horizontal Channel 4"
|
|
group.byte 0x105++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC5,UDB Channel HC Tile Configuration Horizontal Channel 5"
|
|
group.byte 0x106++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC6,UDB Channel HC Tile Configuration Horizontal Channel 6"
|
|
group.byte 0x107++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC7,UDB Channel HC Tile Configuration Horizontal Channel 7"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC8,UDB Channel HC Tile Configuration Horizontal Channel 8"
|
|
group.byte 0x109++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC9,UDB Channel HC Tile Configuration Horizontal Channel 9"
|
|
group.byte 0x10A++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC10,UDB Channel HC Tile Configuration Horizontal Channel 10"
|
|
group.byte 0x10B++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC11,UDB Channel HC Tile Configuration Horizontal Channel 11"
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC12,UDB Channel HC Tile Configuration Horizontal Channel 12"
|
|
group.byte 0x10D++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC13,UDB Channel HC Tile Configuration Horizontal Channel 13"
|
|
group.byte 0x10E++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC14,UDB Channel HC Tile Configuration Horizontal Channel 14"
|
|
group.byte 0x10F++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC15,UDB Channel HC Tile Configuration Horizontal Channel 15"
|
|
group.byte 0x110++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC16,UDB Channel HC Tile Configuration Horizontal Channel 16"
|
|
group.byte 0x111++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC17,UDB Channel HC Tile Configuration Horizontal Channel 17"
|
|
group.byte 0x112++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC18,UDB Channel HC Tile Configuration Horizontal Channel 18"
|
|
group.byte 0x113++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC19,UDB Channel HC Tile Configuration Horizontal Channel 19"
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC20,UDB Channel HC Tile Configuration Horizontal Channel 20"
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC21,UDB Channel HC Tile Configuration Horizontal Channel 21"
|
|
group.byte 0x116++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC22,UDB Channel HC Tile Configuration Horizontal Channel 22"
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC23,UDB Channel HC Tile Configuration Horizontal Channel 23"
|
|
group.byte 0x118++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC24,UDB Channel HC Tile Configuration Horizontal Channel 24"
|
|
group.byte 0x119++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC25,UDB Channel HC Tile Configuration Horizontal Channel 25"
|
|
group.byte 0x11A++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC26,UDB Channel HC Tile Configuration Horizontal Channel 26"
|
|
group.byte 0x11B++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC27,UDB Channel HC Tile Configuration Horizontal Channel 27"
|
|
group.byte 0x11C++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC28,UDB Channel HC Tile Configuration Horizontal Channel 28"
|
|
group.byte 0x11D++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC29,UDB Channel HC Tile Configuration Horizontal Channel 29"
|
|
group.byte 0x11E++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC30,UDB Channel HC Tile Configuration Horizontal Channel 30"
|
|
group.byte 0x11F++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC31,UDB Channel HC Tile Configuration Horizontal Channel 31"
|
|
group.byte 0x120++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC32,UDB Channel HC Tile Configuration Horizontal Channel 32"
|
|
group.byte 0x121++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC33,UDB Channel HC Tile Configuration Horizontal Channel 33"
|
|
group.byte 0x122++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC34,UDB Channel HC Tile Configuration Horizontal Channel 34"
|
|
group.byte 0x123++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC35,UDB Channel HC Tile Configuration Horizontal Channel 35"
|
|
group.byte 0x124++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC36,UDB Channel HC Tile Configuration Horizontal Channel 36"
|
|
group.byte 0x125++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC37,UDB Channel HC Tile Configuration Horizontal Channel 37"
|
|
group.byte 0x126++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC38,UDB Channel HC Tile Configuration Horizontal Channel 38"
|
|
group.byte 0x127++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC39,UDB Channel HC Tile Configuration Horizontal Channel 39"
|
|
group.byte 0x128++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC40,UDB Channel HC Tile Configuration Horizontal Channel 40"
|
|
group.byte 0x129++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC41,UDB Channel HC Tile Configuration Horizontal Channel 41"
|
|
group.byte 0x12A++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC42,UDB Channel HC Tile Configuration Horizontal Channel 42"
|
|
group.byte 0x12B++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC43,UDB Channel HC Tile Configuration Horizontal Channel 43"
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC44,UDB Channel HC Tile Configuration Horizontal Channel 44"
|
|
group.byte 0x12D++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC45,UDB Channel HC Tile Configuration Horizontal Channel 45"
|
|
group.byte 0x12E++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC46,UDB Channel HC Tile Configuration Horizontal Channel 46"
|
|
group.byte 0x12F++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC47,UDB Channel HC Tile Configuration Horizontal Channel 47"
|
|
group.byte 0x130++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC48,UDB Channel HC Tile Configuration Horizontal Channel 48"
|
|
group.byte 0x131++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC49,UDB Channel HC Tile Configuration Horizontal Channel 49"
|
|
group.byte 0x132++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC50,UDB Channel HC Tile Configuration Horizontal Channel 50"
|
|
group.byte 0x133++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC51,UDB Channel HC Tile Configuration Horizontal Channel 51"
|
|
group.byte 0x134++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC52,UDB Channel HC Tile Configuration Horizontal Channel 52"
|
|
group.byte 0x135++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC53,UDB Channel HC Tile Configuration Horizontal Channel 53"
|
|
group.byte 0x136++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC54,UDB Channel HC Tile Configuration Horizontal Channel 54"
|
|
group.byte 0x137++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC55,UDB Channel HC Tile Configuration Horizontal Channel 55"
|
|
group.byte 0x138++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC56,UDB Channel HC Tile Configuration Horizontal Channel 56"
|
|
group.byte 0x139++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC57,UDB Channel HC Tile Configuration Horizontal Channel 57"
|
|
group.byte 0x13A++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC58,UDB Channel HC Tile Configuration Horizontal Channel 58"
|
|
group.byte 0x13B++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC59,UDB Channel HC Tile Configuration Horizontal Channel 59"
|
|
group.byte 0x13C++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC60,UDB Channel HC Tile Configuration Horizontal Channel 60"
|
|
group.byte 0x13D++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC61,UDB Channel HC Tile Configuration Horizontal Channel 61"
|
|
group.byte 0x13E++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC62,UDB Channel HC Tile Configuration Horizontal Channel 62"
|
|
group.byte 0x13F++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC63,UDB Channel HC Tile Configuration Horizontal Channel 63"
|
|
group.byte 0x140++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC64,UDB Channel HC Tile Configuration Horizontal Channel 64"
|
|
group.byte 0x141++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC65,UDB Channel HC Tile Configuration Horizontal Channel 65"
|
|
group.byte 0x142++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC66,UDB Channel HC Tile Configuration Horizontal Channel 66"
|
|
group.byte 0x143++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC67,UDB Channel HC Tile Configuration Horizontal Channel 67"
|
|
group.byte 0x144++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC68,UDB Channel HC Tile Configuration Horizontal Channel 68"
|
|
group.byte 0x145++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC69,UDB Channel HC Tile Configuration Horizontal Channel 69"
|
|
group.byte 0x146++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC70,UDB Channel HC Tile Configuration Horizontal Channel 70"
|
|
group.byte 0x147++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC71,UDB Channel HC Tile Configuration Horizontal Channel 71"
|
|
group.byte 0x148++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC72,UDB Channel HC Tile Configuration Horizontal Channel 72"
|
|
group.byte 0x149++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC73,UDB Channel HC Tile Configuration Horizontal Channel 73"
|
|
group.byte 0x14A++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC74,UDB Channel HC Tile Configuration Horizontal Channel 74"
|
|
group.byte 0x14B++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC75,UDB Channel HC Tile Configuration Horizontal Channel 75"
|
|
group.byte 0x14C++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC76,UDB Channel HC Tile Configuration Horizontal Channel 76"
|
|
group.byte 0x14D++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC77,UDB Channel HC Tile Configuration Horizontal Channel 77"
|
|
group.byte 0x14E++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC78,UDB Channel HC Tile Configuration Horizontal Channel 78"
|
|
group.byte 0x14F++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC79,UDB Channel HC Tile Configuration Horizontal Channel 79"
|
|
group.byte 0x150++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC80,UDB Channel HC Tile Configuration Horizontal Channel 80"
|
|
group.byte 0x151++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC81,UDB Channel HC Tile Configuration Horizontal Channel 81"
|
|
group.byte 0x152++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC82,UDB Channel HC Tile Configuration Horizontal Channel 82"
|
|
group.byte 0x153++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC83,UDB Channel HC Tile Configuration Horizontal Channel 83"
|
|
group.byte 0x154++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC84,UDB Channel HC Tile Configuration Horizontal Channel 84"
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC85,UDB Channel HC Tile Configuration Horizontal Channel 85"
|
|
group.byte 0x156++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC86,UDB Channel HC Tile Configuration Horizontal Channel 86"
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC87,UDB Channel HC Tile Configuration Horizontal Channel 87"
|
|
group.byte 0x158++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC88,UDB Channel HC Tile Configuration Horizontal Channel 88"
|
|
group.byte 0x159++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC89,UDB Channel HC Tile Configuration Horizontal Channel 89"
|
|
group.byte 0x15A++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC90,UDB Channel HC Tile Configuration Horizontal Channel 90"
|
|
group.byte 0x15B++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC91,UDB Channel HC Tile Configuration Horizontal Channel 91"
|
|
group.byte 0x15C++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC92,UDB Channel HC Tile Configuration Horizontal Channel 92"
|
|
group.byte 0x15D++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC93,UDB Channel HC Tile Configuration Horizontal Channel 93"
|
|
group.byte 0x15E++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC94,UDB Channel HC Tile Configuration Horizontal Channel 94"
|
|
group.byte 0x15F++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC95,UDB Channel HC Tile Configuration Horizontal Channel 95"
|
|
group.byte 0x160++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC96,UDB Channel HC Tile Configuration Horizontal Channel 96"
|
|
group.byte 0x161++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC97,UDB Channel HC Tile Configuration Horizontal Channel 97"
|
|
group.byte 0x162++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC98,UDB Channel HC Tile Configuration Horizontal Channel 98"
|
|
group.byte 0x163++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC99,UDB Channel HC Tile Configuration Horizontal Channel 99"
|
|
group.byte 0x164++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC100,UDB Channel HC Tile Configuration Horizontal Channel 100"
|
|
group.byte 0x165++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC101,UDB Channel HC Tile Configuration Horizontal Channel 101"
|
|
group.byte 0x166++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC102,UDB Channel HC Tile Configuration Horizontal Channel 102"
|
|
group.byte 0x167++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC103,UDB Channel HC Tile Configuration Horizontal Channel 103"
|
|
group.byte 0x168++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC104,UDB Channel HC Tile Configuration Horizontal Channel 104"
|
|
group.byte 0x169++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC105,UDB Channel HC Tile Configuration Horizontal Channel 105"
|
|
group.byte 0x16A++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC106,UDB Channel HC Tile Configuration Horizontal Channel 106"
|
|
group.byte 0x16B++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC107,UDB Channel HC Tile Configuration Horizontal Channel 107"
|
|
group.byte 0x16C++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC108,UDB Channel HC Tile Configuration Horizontal Channel 108"
|
|
group.byte 0x16D++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC109,UDB Channel HC Tile Configuration Horizontal Channel 109"
|
|
group.byte 0x16E++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC110,UDB Channel HC Tile Configuration Horizontal Channel 110"
|
|
group.byte 0x16F++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC111,UDB Channel HC Tile Configuration Horizontal Channel 111"
|
|
group.byte 0x170++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC112,UDB Channel HC Tile Configuration Horizontal Channel 112"
|
|
group.byte 0x171++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC113,UDB Channel HC Tile Configuration Horizontal Channel 113"
|
|
group.byte 0x172++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC114,UDB Channel HC Tile Configuration Horizontal Channel 114"
|
|
group.byte 0x173++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC115,UDB Channel HC Tile Configuration Horizontal Channel 115"
|
|
group.byte 0x174++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC116,UDB Channel HC Tile Configuration Horizontal Channel 116"
|
|
group.byte 0x175++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC117,UDB Channel HC Tile Configuration Horizontal Channel 117"
|
|
group.byte 0x176++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC118,UDB Channel HC Tile Configuration Horizontal Channel 118"
|
|
group.byte 0x177++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC119,UDB Channel HC Tile Configuration Horizontal Channel 119"
|
|
group.byte 0x178++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC120,UDB Channel HC Tile Configuration Horizontal Channel 120"
|
|
group.byte 0x179++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC121,UDB Channel HC Tile Configuration Horizontal Channel 121"
|
|
group.byte 0x17A++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC122,UDB Channel HC Tile Configuration Horizontal Channel 122"
|
|
group.byte 0x17B++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC123,UDB Channel HC Tile Configuration Horizontal Channel 123"
|
|
group.byte 0x17C++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC124,UDB Channel HC Tile Configuration Horizontal Channel 124"
|
|
group.byte 0x17D++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC125,UDB Channel HC Tile Configuration Horizontal Channel 125"
|
|
group.byte 0x17E++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC126,UDB Channel HC Tile Configuration Horizontal Channel 126"
|
|
group.byte 0x17F++0x00
|
|
line.byte 0x00 "P1_ROUTE_HC127,UDB Channel HC Tile Configuration Horizontal Channel 127"
|
|
group.byte 0x180++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L0,UDB Channel HV Tile Configuration Left 0"
|
|
group.byte 0x181++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L1,UDB Channel HV Tile Configuration Left 1"
|
|
group.byte 0x182++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L2,UDB Channel HV Tile Configuration Left 2"
|
|
group.byte 0x183++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L3,UDB Channel HV Tile Configuration Left 3"
|
|
group.byte 0x184++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L4,UDB Channel HV Tile Configuration Left 4"
|
|
group.byte 0x185++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L5,UDB Channel HV Tile Configuration Left 5"
|
|
group.byte 0x186++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L6,UDB Channel HV Tile Configuration Left 6"
|
|
group.byte 0x187++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L7,UDB Channel HV Tile Configuration Left 7"
|
|
group.byte 0x188++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L8,UDB Channel HV Tile Configuration Left 8"
|
|
group.byte 0x189++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L9,UDB Channel HV Tile Configuration Left 9"
|
|
group.byte 0x18A++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L10,UDB Channel HV Tile Configuration Left 10"
|
|
group.byte 0x18B++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L11,UDB Channel HV Tile Configuration Left 11"
|
|
group.byte 0x18C++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L12,UDB Channel HV Tile Configuration Left 12"
|
|
group.byte 0x18D++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L13,UDB Channel HV Tile Configuration Left 13"
|
|
group.byte 0x18E++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L14,UDB Channel HV Tile Configuration Left 14"
|
|
group.byte 0x18F++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_L15,UDB Channel HV Tile Configuration Left 15"
|
|
group.byte 0x190++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS0,UDB Channel HS Tile Configuration Horizontal Segmentation 0"
|
|
group.byte 0x191++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS1,UDB Channel HS Tile Configuration Horizontal Segmentation 1"
|
|
group.byte 0x192++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS2,UDB Channel HS Tile Configuration Horizontal Segmentation 2"
|
|
group.byte 0x193++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS3,UDB Channel HS Tile Configuration Horizontal Segmentation 3"
|
|
group.byte 0x194++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS4,UDB Channel HS Tile Configuration Horizontal Segmentation 4"
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS5,UDB Channel HS Tile Configuration Horizontal Segmentation 5"
|
|
group.byte 0x196++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS6,UDB Channel HS Tile Configuration Horizontal Segmentation 6"
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS7,UDB Channel HS Tile Configuration Horizontal Segmentation 7"
|
|
group.byte 0x198++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS8,UDB Channel HS Tile Configuration Horizontal Segmentation 8"
|
|
group.byte 0x199++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS9,UDB Channel HS Tile Configuration Horizontal Segmentation 9"
|
|
group.byte 0x19A++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS10,UDB Channel HS Tile Configuration Horizontal Segmentation 10"
|
|
group.byte 0x19B++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS11,UDB Channel HS Tile Configuration Horizontal Segmentation 11"
|
|
group.byte 0x19C++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS12,UDB Channel HS Tile Configuration Horizontal Segmentation 12"
|
|
group.byte 0x19D++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS13,UDB Channel HS Tile Configuration Horizontal Segmentation 13"
|
|
group.byte 0x19E++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS14,UDB Channel HS Tile Configuration Horizontal Segmentation 14"
|
|
group.byte 0x19F++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS15,UDB Channel HS Tile Configuration Horizontal Segmentation 15"
|
|
group.byte 0x1A0++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS16,UDB Channel HS Tile Configuration Horizontal Segmentation 16"
|
|
group.byte 0x1A1++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS17,UDB Channel HS Tile Configuration Horizontal Segmentation 17"
|
|
group.byte 0x1A2++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS18,UDB Channel HS Tile Configuration Horizontal Segmentation 18"
|
|
group.byte 0x1A3++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS19,UDB Channel HS Tile Configuration Horizontal Segmentation 19"
|
|
group.byte 0x1A4++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS20,UDB Channel HS Tile Configuration Horizontal Segmentation 20"
|
|
group.byte 0x1A5++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS21,UDB Channel HS Tile Configuration Horizontal Segmentation 21"
|
|
group.byte 0x1A6++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS22,UDB Channel HS Tile Configuration Horizontal Segmentation 22"
|
|
group.byte 0x1A7++0x00
|
|
line.byte 0x00 "P1_ROUTE_HS23,UDB Channel HS Tile Configuration Horizontal Segmentation 23"
|
|
group.byte 0x1A8++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R0,UDB Channel HV Tile Configuration Right 0"
|
|
group.byte 0x1A9++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R1,UDB Channel HV Tile Configuration Right 1"
|
|
group.byte 0x1AA++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R2,UDB Channel HV Tile Configuration Right 2"
|
|
group.byte 0x1AB++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R3,UDB Channel HV Tile Configuration Right 3"
|
|
group.byte 0x1AC++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R4,UDB Channel HV Tile Configuration Right 4"
|
|
group.byte 0x1AD++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R5,UDB Channel HV Tile Configuration Right 5"
|
|
group.byte 0x1AE++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R6,UDB Channel HV Tile Configuration Right 6"
|
|
group.byte 0x1AF++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R7,UDB Channel HV Tile Configuration Right 7"
|
|
group.byte 0x1B0++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R8,UDB Channel HV Tile Configuration Right 8"
|
|
group.byte 0x1B1++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R9,UDB Channel HV Tile Configuration Right 9"
|
|
group.byte 0x1B2++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R10,UDB Channel HV Tile Configuration Right 10"
|
|
group.byte 0x1B3++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R11,UDB Channel HV Tile Configuration Right 11"
|
|
group.byte 0x1B4++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R12,UDB Channel HV Tile Configuration Right 12"
|
|
group.byte 0x1B5++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R13,UDB Channel HV Tile Configuration Right 13"
|
|
group.byte 0x1B6++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R14,UDB Channel HV Tile Configuration Right 14"
|
|
group.byte 0x1B7++0x00
|
|
line.byte 0x00 "P1_ROUTE_HV_R15,UDB Channel HV Tile Configuration Right 15"
|
|
group.word 0x1C0++0x01
|
|
line.word 0x00 "P1_ROUTE_PLD0IN0,UDB Channel PI Tile Configuration PLD Input 00"
|
|
bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1C2++0x01
|
|
line.word 0x00 "P1_ROUTE_PLD0IN1,UDB Channel PI Tile Configuration PLD Input 01"
|
|
bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1C4++0x01
|
|
line.word 0x00 "P1_ROUTE_PLD0IN2,UDB Channel PI Tile Configuration PLD Input 02"
|
|
bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1CA++0x01
|
|
line.word 0x00 "P1_ROUTE_PLD1IN0,UDB Channel PI Tile Configuration PLD Input 10"
|
|
bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1CC++0x01
|
|
line.word 0x00 "P1_ROUTE_PLD1IN1,UDB Channel PI Tile Configuration PLD Input 11"
|
|
bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1CE++0x01
|
|
line.word 0x00 "P1_ROUTE_PLD1IN2,UDB Channel PI Tile Configuration PLD Input 12"
|
|
bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1D0++0x00
|
|
line.byte 0x00 "P1_ROUTE_DPIN0,UDB Channel PI Tile Configuration Datapath Input 0"
|
|
bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1D2++0x00
|
|
line.byte 0x00 "P1_ROUTE_DPIN1,UDB Channel PI Tile Configuration Datapath Input 1"
|
|
bitfld.byte 0x00 4.--5. " PI_BOT2 ,RAM configuration bits (2) for BOTTOM UDB port interface configuration" "0,1,2,3"
|
|
bitfld.byte 0x00 2.--3. " PI_TOP2 ,RAM configuration bits (2) for TOP UDB port interface configuration" "0,1,2,3"
|
|
group.byte 0x1D6++0x00
|
|
line.byte 0x00 "P1_ROUTE_SCIN,UDB Channel PI Tile Configuration Status / Control Blocks Input Control"
|
|
bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1D8++0x00
|
|
line.byte 0x00 "P1_ROUTE_SCION,UDB Channel PI Tile Configuration Status / Control Blocks Input / Output Control"
|
|
bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1DE++0x00
|
|
line.byte 0x00 "P1_ROUTE_RCIN,UDB Channel PI Tile Configuration Reset and Clock Blocks Input Control"
|
|
bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1E0++0x01
|
|
line.word 0x00 "P1_ROUTE_VS0,UDB Channel VS Tile Configuration Vertical Segmentation 0"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1E2++0x01
|
|
line.word 0x00 "P1_ROUTE_VS1,UDB Channel VS Tile Configuration Vertical Segmentation 1"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1E4++0x01
|
|
line.word 0x00 "P1_ROUTE_VS2,UDB Channel VS Tile Configuration Vertical Segmentation 2"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1E6++0x01
|
|
line.word 0x00 "P1_ROUTE_VS3,UDB Channel VS Tile Configuration Vertical Segmentation 3"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1E8++0x01
|
|
line.word 0x00 "P1_ROUTE_VS4,UDB Channel VS Tile Configuration Vertical Segmentation 4"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1EA++0x01
|
|
line.word 0x00 "P1_ROUTE_VS5,UDB Channel VS Tile Configuration Vertical Segmentation 5"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1EC++0x01
|
|
line.word 0x00 "P1_ROUTE_VS6,UDB Channel VS Tile Configuration Vertical Segmentation 6"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x1EE++0x01
|
|
line.word 0x00 "P1_ROUTE_VS7,UDB Channel VS Tile Configuration Vertical Segmentation 7"
|
|
bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "SAR (Successive Approximation Register)"
|
|
base ad:0x403A0000
|
|
width 22.
|
|
if (((per.l(ad:0x403A0000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Analog Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,SAR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SWITCH_DISABLE ,Disable SAR sequencer from enabling routing switches" "Normal mode,Disabled"
|
|
bitfld.long 0x00 29. " DSI_MODE ,SAR sequencer takes configuration from DSI signals" "Normal mode,Ignore mode"
|
|
textline " "
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x00 28. " DSI_SYNC_CONFIG ,Synchronize the DSI config signals" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " DEEPSLEEP_ON ,Enabled during DeepSleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " ICONT_LV ,SARADC low power mode" "NORMAL_PWR,HALF_PWR,THIRD_PWR,QUARTER_PWR"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 21. " REFBUF_EN ,SARREFBUF enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " BOOSTPUMP_EN ,SARDAC internal pump" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PWR_CTRL_VREF ,VREF buffer low power mode" "NORMAL_PWR,HALF_PWR,MORE_PWR,QUARTER_PWR"
|
|
bitfld.long 0x00 13. " SAR_HW_CTRL_NEGVREF ,Hardware control" "Firmware,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " NEG_SEL ,SARADAC internal NEG selection for single ended conversion" "Vssa_kelvin,Art_vssa,P1,P3,P5,P7,Acore,Vref"
|
|
bitfld.long 0x00 7. " VREF_BYP_CAP_EN ,VREF bypass cap enable for when VREF buffer is on" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " VREF_SEL ,SARADAC internal VREF selection" "Vref0,Vref1,Vref2,Vref_aroute,Vbgr,Vref_ext,Vdda_div2,Vdda"
|
|
if (((per.l(ad:0x403A0000+0x04))&0x10000000)==0x10000000)
|
|
if (((per.l(ad:0x403A0000+0x04))&0x400000)==0x400000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SAMPLE_CTRL,Sample Control Register"
|
|
bitfld.long 0x00 31. " EOS_DSI_OUT_EN ,Enable to output EOS_INTR" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 30. " TRIGGER_OUT_EN ,SAR output trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " VALID_IGNORE ,Ignore UAB valid signal" "Not ignored,Ignored"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 22. " UAB_SCAN_MODE ,Select whether uabs are scheduled or unscheduled" "Unscheduled,Scheduled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " DSI_SYNC_TRIGGER ,Hardware trigger signal" "Pulse,Level"
|
|
sif cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 18. " DSI_TRIGGER_LEVEL ,DSI trigger signal input" "Pulse,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSI_TRIGGER_EN ,DSI hardware trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CONTINOUS ,Continous scan" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 8. " AVG_MODE ,Averaging mode" "Accundump,Interleaved"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " AVG_SHIFT ,Averaging shift" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVG_CNT ,Averaging count for channels that have averaging enabled" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " DIFFERENTIAL_SIGNED ,Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NED_ADDR_EN is set to 1" "Unsigned,Signed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINGLE_ENDED_SIGNED ,Output data from a single ended conversion as a signed value" "Unsigned,Signed"
|
|
bitfld.long 0x00 1. " LEFT_ALIGN ,Left align data in data" "Right align,Left align"
|
|
bitfld.long 0x00 0. " SUB_RESOLUTION ,Conversion resolution for channels that have sub-resolution enabled" "8b,10b"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SAMPLE_CTRL,Sample Control Register"
|
|
bitfld.long 0x00 31. " EOS_DSI_OUT_EN ,Enable to output EOS_INTR" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 30. " TRIGGER_OUT_EN ,SAR output trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " VALID_IGNORE ,Ignore UAB valid signal" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 23. " REPEAT_INVALID ,For unscheduled UAB_SCAN_MODE only" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 22. " UAB_SCAN_MODE ,Select whether uabs are scheduled or unscheduled" "UNSCHEDULED,SCHEDULED"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " DSI_SYNC_TRIGGER ,Hardware trigger signal" "Pulse,Level"
|
|
sif (cpuis("CY8C4*-BL*")||cpuis("CY8C4*-4*"))
|
|
textline " "
|
|
bitfld.long 0x00 18. " DSI_TRIGGER_LEVEL ,DSI trigger signal input" "Pulse,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSI_TRIGGER_EN ,DSI hardware trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CONTINOUS ,Continous scan" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 8. " AVG_MODE ,Averaging mode" "Accundump,Interleaved"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " AVG_SHIFT ,Averaging shift" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVG_CNT ,Averaging count for channels that have averaging enabled" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " DIFFERENTIAL_SIGNED ,Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NED_ADDR_EN is set to 1" "Unsigned,Signed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINGLE_ENDED_SIGNED ,Output data from a single ended conversion as a signed value" "Unsigned,Signed"
|
|
bitfld.long 0x00 1. " LEFT_ALIGN ,Left align data in data" "Right align,Left align"
|
|
bitfld.long 0x00 0. " SUB_RESOLUTION ,Conversion resolution for channels that have sub-resolution enabled" "8b,10b"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x403A0000+0x04))&0x400000)==0x400000)
|
|
if (((per.l(ad:0x403A0000+0x04))&0x08000000)==0x08000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SAMPLE_CTRL,Sample Control Register"
|
|
bitfld.long 0x00 31. " EOS_DSI_OUT_EN ,Enable to output EOS_INTR" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 30. " TRIGGER_OUT_EN ,SAR output trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " VALID_IGNORE ,Ignore UAB valid signal" "Not ignored,Ignored"
|
|
bitfld.long 0x00 27. " VALID_SEL_EN ,Enable static UAB valid selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " VALID_SEL ,Static UAB valid select" "UAB0 half 0,UAB0 half 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " UAB_SCAN_MODE ,Select whether uabs are scheduled or unscheduled" "Unscheduled,Scheduled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " DSI_SYNC_TRIGGER ,Hardware trigger signal" "Pulse,Level"
|
|
sif cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 18. " DSI_TRIGGER_LEVEL ,DSI trigger signal input" "Pulse,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSI_TRIGGER_EN ,DSI hardware trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CONTINOUS ,Continous scan" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 8. " AVG_MODE ,Averaging mode" "Accundump,Interleaved"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " AVG_SHIFT ,Averaging shift" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVG_CNT ,Averaging count for channels that have averaging enabled" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " DIFFERENTIAL_SIGNED ,Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NED_ADDR_EN is set to 1" "Unsigned,Signed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINGLE_ENDED_SIGNED ,Output data from a single ended conversion as a signed value" "Unsigned,Signed"
|
|
bitfld.long 0x00 1. " LEFT_ALIGN ,Left align data in data" "Right align,Left align"
|
|
bitfld.long 0x00 0. " SUB_RESOLUTION ,Conversion resolution for channels that have Sub-resolution enabled" "8b,10b"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SAMPLE_CTRL,Sample Control Register"
|
|
bitfld.long 0x00 31. " EOS_DSI_OUT_EN ,Enable to output EOS_INTR" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 30. " TRIGGER_OUT_EN ,SAR output trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " VALID_IGNORE ,Ignore UAB valid signal" "Not ignored,Ignored"
|
|
bitfld.long 0x00 27. " VALID_SEL_EN ,Enable static UAB valid selection" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 22. " UAB_SCAN_MODE ,Select whether uabs are scheduled or unscheduled" "Unscheduled,Scheduled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " DSI_SYNC_TRIGGER ,Hardware trigger signal" "Pulse,Level"
|
|
sif cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 18. " DSI_TRIGGER_LEVEL ,DSI trigger signal input" "Pulse,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSI_TRIGGER_EN ,DSI hardware trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CONTINOUS ,Continous scan" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 8. " AVG_MODE ,Averaging mode" "Accundump,Interleaved"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " AVG_SHIFT ,Averaging shift" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVG_CNT ,Averaging count for channels that have averaging enabled" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " DIFFERENTIAL_SIGNED ,Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NED_ADDR_EN is set to 1" "Unsigned,Signed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINGLE_ENDED_SIGNED ,Output data from a single ended conversion as a signed value" "Unsigned,Signed"
|
|
bitfld.long 0x00 1. " LEFT_ALIGN ,Left align data in data" "Right align,Left align"
|
|
bitfld.long 0x00 0. " SUB_RESOLUTION ,Conversion resolution for channels that have Sub-resolution enabled" "8b,10b"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x403A0000+0x04))&0x08000000)==0x08000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SAMPLE_CTRL,Sample Control Register"
|
|
bitfld.long 0x00 31. " EOS_DSI_OUT_EN ,Enable to output EOS_INTR" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 30. " TRIGGER_OUT_EN ,SAR output trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " VALID_IGNORE ,Ignore UAB valid signal" "Not ignored,Ignored"
|
|
bitfld.long 0x00 27. " VALID_SEL_EN ,Enable static UAB valid selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " VALID_SEL ,Static UAB valid select" "UAB0 half 0,UAB0 half 1,?..."
|
|
bitfld.long 0x00 23. " REPEAT_INVALID ,For unscheduled UAB_SCAN_MODE only" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 22. " UAB_SCAN_MODE ,Select whether uabs are scheduled or unscheduled" "Unscheduled,Scheduled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " DSI_SYNC_TRIGGER ,Hardware trigger signal" "Pulse,Level"
|
|
sif (cpuis("CY8C4*-BL*")||cpuis("CY8C4*-4*"))
|
|
textline " "
|
|
bitfld.long 0x00 18. " DSI_TRIGGER_LEVEL ,DSI trigger signal input" "Pulse,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSI_TRIGGER_EN ,DSI hardware trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CONTINOUS ,Continous scan" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 8. " AVG_MODE ,Averaging mode" "Accundump,Interleaved"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " AVG_SHIFT ,Averaging shift" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVG_CNT ,Averaging count for channels that have averaging enabled" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " DIFFERENTIAL_SIGNED ,Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NED_ADDR_EN is set to 1" "Unsigned,Signed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINGLE_ENDED_SIGNED ,Output data from a single ended conversion as a signed value" "Unsigned,Signed"
|
|
bitfld.long 0x00 1. " LEFT_ALIGN ,Left align data in data" "Right align,Left align"
|
|
bitfld.long 0x00 0. " SUB_RESOLUTION ,Conversion resolution for channels that have Sub-resolution enabled" "8b,10b"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SAMPLE_CTRL,Sample Control Register"
|
|
bitfld.long 0x00 31. " EOS_DSI_OUT_EN ,Enable to output EOS_INTR" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 30. " TRIGGER_OUT_EN ,SAR output trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " VALID_IGNORE ,Ignore UAB valid signal" "Not ignored,Ignored"
|
|
bitfld.long 0x00 27. " VALID_SEL_EN ,Enable static UAB valid selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " REPEAT_INVALID ,For unscheduled UAB_SCAN_MODE only" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 22. " UAB_SCAN_MODE ,Select whether uabs are scheduled or unscheduled" "Unscheduled,Scheduled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " DSI_SYNC_TRIGGER ,Hardware trigger signal" "Pulse,Level"
|
|
sif (cpuis("CY8C4*-BL*")||cpuis("CY8C4*-4*"))
|
|
textline " "
|
|
bitfld.long 0x00 18. " DSI_TRIGGER_LEVEL ,DSI trigger signal input" "Pulse,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSI_TRIGGER_EN ,DSI hardware trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CONTINOUS ,Continous scan" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 8. " AVG_MODE ,Averaging mode" "Accundump,Interleaved"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " AVG_SHIFT ,Averaging shift" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVG_CNT ,Averaging count for channels that have averaging enabled" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " DIFFERENTIAL_SIGNED ,Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NED_ADDR_EN is set to 1" "Unsigned,Signed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINGLE_ENDED_SIGNED ,Output data from a single ended conversion as a signed value" "Unsigned,Signed"
|
|
bitfld.long 0x00 1. " LEFT_ALIGN ,Left align data in data" "Right align,Left align"
|
|
bitfld.long 0x00 0. " SUB_RESOLUTION ,Conversion resolution for channels that have Sub-resolution enabled" "8b,10b"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "SAMPLE_TIME01,Sample Time Specification ST0 And ST1"
|
|
hexmask.long.word 0x00 16.--25. 1. " SAMPLE_TIME1 ,10-bit sample time1"
|
|
hexmask.long.word 0x00 0.--9. 1. " SAMPLE_TIME0 ,10-bit sample time0 in ADC clock cycles"
|
|
line.long 0x04 "SAMPLE_TIME23,Sample Time Specification ST2 And ST3"
|
|
hexmask.long.word 0x04 16.--25. 1. " SAMPLE_TIME3 ,10-bit sample time3"
|
|
hexmask.long.word 0x04 0.--9. 1. " SAMPLE_TIME2 ,10-bit sample time2"
|
|
line.long 0x08 "RANGE_THRES,Global Range Detect Threshold Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " RANGE_HIGH ,16-bit high threshold for range detect"
|
|
hexmask.long.word 0x08 0.--15. 1. " RANGE_LOW ,16-bit low threshold for range detect"
|
|
line.long 0x0C "RANGE_COND,Global Range Detect Mode Register"
|
|
bitfld.long 0x0C 30.--31. " RANGE_COND ,Range condition select" "Below,Inside,Above,Outside"
|
|
line.long 0x10 "CHAN_EN,Enable Bits For The Channels"
|
|
bitfld.long 0x10 15. " CHAN15_EN ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " CHAN14_EN ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " CHAN13_EN ,Channel 13 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 12. " CHAN12_EN ,Channel 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " CHAN11_EN ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " CHAN10_EN ,Channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " CHAN9_EN ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " CHAN8_EN ,Channel 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 7. " CHAN7_EN ,Channel 7 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 6. " CHAN6_EN ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " CHAN5_EN ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " CHAN4_EN ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " CHAN3_EN ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " CHAN2_EN ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " CHAN1_EN ,Channel 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CHAN0_EN ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x14 "START_CTRL,Start Control Register"
|
|
bitfld.long 0x14 0. " FW_TRIGGER ,Firmware trigger" "Scan disabled,Scan enabled"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DFT_CTRL,DFT Control Register"
|
|
bitfld.long 0x00 31. " ADFT_OVERRIDE ,ADFT override" "No override,Override"
|
|
bitfld.long 0x00 29. " DCEN ,Delay control enable for latch" "Double time,Normal time"
|
|
bitfld.long 0x00 28. " EN_CSEL_DFT ,Mux select signal for DAC control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SEL_CSEL_DFT ,DFT bits for DAC array" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--22. " DFT_OUTC ,DFT control for preamp outputs" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " DFT_INC ,DFT control for preamp inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIZ ,DFT control for getting higher input impedance" "0,1"
|
|
bitfld.long 0x00 0. " DLY_INC ,Control for delay circuits on sampling phase" "Normal delay,Double delay"
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<0.))==0x01<<0.)
|
|
if (((per.l(ad:0x403A0000+0x80))&0x0100)==0x0100)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CHAN_CONFIG0,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CHAN_CONFIG0,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<1.))==0x01<<1.)
|
|
if (((per.l(ad:0x403A0000+0x84))&0x0100)==0x0100)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CHAN_CONFIG1,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CHAN_CONFIG1,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<2.))==0x01<<2.)
|
|
if (((per.l(ad:0x403A0000+0x88))&0x0100)==0x0100)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CHAN_CONFIG2,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CHAN_CONFIG2,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<3.))==0x01<<3.)
|
|
if (((per.l(ad:0x403A0000+0x8C))&0x0100)==0x0100)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHAN_CONFIG3,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHAN_CONFIG3,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<4.))==0x01<<4.)
|
|
if (((per.l(ad:0x403A0000+0x90))&0x0100)==0x0100)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CHAN_CONFIG4,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CHAN_CONFIG4,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<5.))==0x01<<5.)
|
|
if (((per.l(ad:0x403A0000+0x94))&0x0100)==0x0100)
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CHAN_CONFIG5,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CHAN_CONFIG5,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<6.))==0x01<<6.)
|
|
if (((per.l(ad:0x403A0000+0x98))&0x0100)==0x0100)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CHAN_CONFIG6,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CHAN_CONFIG6,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<7.))==0x01<<7.)
|
|
if (((per.l(ad:0x403A0000+0x9C))&0x0100)==0x0100)
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CHAN_CONFIG7,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CHAN_CONFIG7,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<8.))==0x01<<8.)
|
|
if (((per.l(ad:0x403A0000+0xA0))&0x0100)==0x0100)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CHAN_CONFIG8,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CHAN_CONFIG8,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<9.))==0x01<<9.)
|
|
if (((per.l(ad:0x403A0000+0xA4))&0x0100)==0x0100)
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CHAN_CONFIG9,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CHAN_CONFIG9,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<10.))==0x01<<10.)
|
|
if (((per.l(ad:0x403A0000+0xA8))&0x0100)==0x0100)
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CHAN_CONFIG10,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CHAN_CONFIG10,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<11.))==0x01<<11.)
|
|
if (((per.l(ad:0x403A0000+0xAC))&0x0100)==0x0100)
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CHAN_CONFIG11,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CHAN_CONFIG11,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<12.))==0x01<<12.)
|
|
if (((per.l(ad:0x403A0000+0xB0))&0x0100)==0x0100)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CHAN_CONFIG12,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CHAN_CONFIG12,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<13.))==0x01<<13.)
|
|
if (((per.l(ad:0x403A0000+0xB4))&0x0100)==0x0100)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CHAN_CONFIG13,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CHAN_CONFIG13,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<14.))==0x01<<14.)
|
|
if (((per.l(ad:0x403A0000+0xB8))&0x0100)==0x0100)
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CHAN_CONFIG14,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CHAN_CONFIG14,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<15.))==0x01<<15.)
|
|
if (((per.l(ad:0x403A0000+0xBC))&0x0100)==0x0100)
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CHAN_CONFIG15,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CHAN_CONFIG15,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CHAN_WORK0,Channel 0 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CHAN_WORK1,Channel 1 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "CHAN_WORK2,Channel 2 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "CHAN_WORK3,Channel 3 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "CHAN_WORK4,Channel 4 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "CHAN_WORK5,Channel 5 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "CHAN_WORK6,Channel 6 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "CHAN_WORK7,Channel 7 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "CHAN_WORK8,Channel 8 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "CHAN_WORK9,Channel 9 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "CHAN_WORK10,Channel 10 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "CHAN_WORK11,Channel 11 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "CHAN_WORK12,Channel 12 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "CHAN_WORK13,Channel 13 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "CHAN_WORK14,Channel 14 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "CHAN_WORK15,Channel 15 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "CHAN_RESULT0,Channel 0 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "CHAN_RESULT1,Channel 1 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "CHAN_RESULT2,Channel 2 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "CHAN_RESULT3,Channel 3 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "CHAN_RESULT4,Channel 4 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "CHAN_RESULT5,Channel 5 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "CHAN_RESULT6,Channel 6 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "CHAN_RESULT7,Channel 7 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "CHAN_RESULT8,Channel 8 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "CHAN_RESULT9,Channel 9 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "CHAN_RESULT10,Channel 10 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1AC++0x03
|
|
line.long 0x00 "CHAN_RESULT11,Channel 11 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "CHAN_RESULT12,Channel 12 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "CHAN_RESULT13,Channel 13 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "CHAN_RESULT14,Channel 14 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "CHAN_RESULT15,Channel 15 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x200++0x07
|
|
line.long 0x00 "CHAN_WORK_VALID,Channel Working Data Register Valid Bits"
|
|
bitfld.long 0x00 15. " CHAN_WORK_VALID[15] ,Corresponding WORK register for channel 15 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 14. " [14] ,Corresponding WORK register for channel 14 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 13. " [13] ,Corresponding WORK register for channel 13 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Corresponding WORK register for channel 12 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 11. " [11] ,Corresponding WORK register for channel 11 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " [10] ,Corresponding WORK register for channel 10 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 9. " [9] ,Corresponding WORK register for channel 9 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 8. " [8] ,Corresponding WORK register for channel 8 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 7. " [7] ,Corresponding WORK register for channel 7 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Corresponding WORK register for channel 6 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " [5] ,Corresponding WORK register for channel 5 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 4. " [4] ,Corresponding WORK register for channel 4 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Corresponding WORK register for channel 3 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 2. " [2] ,Corresponding WORK register for channel 2 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " [1] ,Corresponding WORK register for channel 1 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Corresponding WORK register for channel 0 is valid" "Not valid,Valid"
|
|
line.long 0x04 "CHAN_RESULT_VALID,Channel Result Data Register Updated Bits"
|
|
bitfld.long 0x04 15. " CHAN_RESULT_VALID[15] ,Corresponding RESULT register for channel 15 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 14. " [14] ,Corresponding RESULT register for channel 14 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 13. " [13] ,Corresponding RESULT register for channel 13 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 12. " [12] ,Corresponding RESULT register for channel 12 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 11. " [11] ,Corresponding RESULT register for channel 11 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 10. " [10] ,Corresponding RESULT register for channel 10 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [9] ,Corresponding RESULT register for channel 9 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 8. " [8] ,Corresponding RESULT register for channel 8 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 7. " [7] ,Corresponding RESULT register for channel 7 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 6. " [6] ,Corresponding RESULT register for channel 6 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 5. " [5] ,Corresponding RESULT register for channel 5 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 4. " [4] ,Corresponding RESULT register for channel 4 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Corresponding RESULT register for channel 3 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 2. " [2] ,Corresponding RESULT register for channel 2 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 1. " [1] ,Corresponding RESULT register for channel 1 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 0. " [0] ,Corresponding RESULT register for channel 0 is valid" "Not valid,Valid"
|
|
sif cpuis("CY8C4*-BL*")
|
|
if (((per.l(ad:0x403A0000+0x208))&0x80000000)==0x80000000)
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "STATUS,Current Status Of Internal SAR Registers"
|
|
bitfld.long 0x00 31. " BUSY ,SAR busy" "Idle,Busy"
|
|
bitfld.long 0x00 30. " SW_VREF_NEG ,Current switch status" "Not switched,Switched"
|
|
bitfld.long 0x00 0.--4. " CUR_CHAN ,Current channel being sampled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "STATUS,Current Status Of Internal SAR Registers"
|
|
bitfld.long 0x00 31. " BUSY ,SAR busy" "Idle,Busy"
|
|
bitfld.long 0x00 30. " SW_VREF_NEG ,Current switch status" "Not switched,Switched"
|
|
endif
|
|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "AVG_STAT,Current Averaging Status"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CUR_AVG_CNT ,The current value of the averaging counter"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CUR_AVG_ACCU ,The current value of the averaging accumulator"
|
|
else
|
|
rgroup.long 0x208++0x07
|
|
line.long 0x00 "CHAN_WORK_NEWVALUE,Channel Working Data Register 'New Value' Bits"
|
|
bitfld.long 0x00 15. " CHAN_WORK_NEWVALUE[15] ,Corresponding WORK data register for channel 15 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 14. " [14] ,Corresponding WORK data register for channel 14 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 13. " [13] ,Corresponding WORK data register for channel 13 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Corresponding WORK data register for channel 12 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 11. " [11] ,Corresponding WORK data register for channel 11 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 10. " [10] ,Corresponding WORK data register for channel 10 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 9. " [9] ,Corresponding WORK data register for channel 9 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 8. " [8] ,Corresponding WORK data register for channel 8 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 7. " [7] ,Corresponding WORK data register for channel 7 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Corresponding WORK data register for channel 6 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 5. " [5] ,Corresponding WORK data register for channel 5 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 4. " [4] ,Corresponding WORK data register for channel 4 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Corresponding WORK data register for channel 3 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 2. " [2] ,Corresponding WORK data register for channel 2 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 1. " [1] ,Corresponding WORK data register for channel 1 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Corresponding WORK data register for channel 0 received a new value" "Not received,Received"
|
|
line.long 0x04 "CHAN_RESULT_NEWVALUE,Channel Result Data Register 'New Value' Bits"
|
|
bitfld.long 0x04 15. " CHAN_RESULT_NEWVALUE[15] ,Corresponding RESULT data register for channel 15 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 14. " [14] ,Corresponding RESULT data register for channel 14 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 13. " [13] ,Corresponding RESULT data register for channel 13 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 12. " [12] ,Corresponding RESULT data register for channel 12 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 11. " [11] ,Corresponding RESULT data register for channel 11 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 10. " [10] ,Corresponding RESULT data register for channel 10 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [9] ,Corresponding RESULT data register for channel 9 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 8. " [8] ,Corresponding RESULT data register for channel 8 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 7. " [7] ,Corresponding RESULT data register for channel 7 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 6. " [6] ,Corresponding RESULT data register for channel 6 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 5. " [5] ,Corresponding RESULT data register for channel 5 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 4. " [4] ,Corresponding RESULT data register for channel 4 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Corresponding RESULT data register for channel 3 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 2. " [2] ,Corresponding RESULT data register for channel 2 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 1. " [1] ,Corresponding RESULT data register for channel 1 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 0. " [0] ,Corresponding RESULT data register for channel 0 received a new value" "Not received,Received"
|
|
endif
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 7. " INJ_COLLISION_INTR ,Injection collision interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " INJ_RANGE_INTR ,Injection range detect interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " INJ_SATURATE_INTR ,Injection saturate interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " INJ_EOC_INTR ,Injection end of conversion interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " DSI_COLLISION_INTR ,DSI collision interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " FW_COLLISION_INTR ,Firmware collision interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " OVERFLOW_INTR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " EOS_INTR ,End of scan interrupt" "No interrupt,Interrupt"
|
|
group.long 0x214++0x07
|
|
line.long 0x00 "INTR_SET,Interrupt Set Request Register"
|
|
bitfld.long 0x00 7. " INJ_COLLISION_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INJ_RANGE_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INJ_SATURATE_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INJ_EOC_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " DSI_COLLISION_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " FW_COLLISION_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVERFLOW_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " EOS_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x04 7. " INJ_COLLISION_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " INJ_RANGE_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " INJ_SATURATE_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INJ_EOC_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x04 3. " DSI_COLLISION_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " FW_COLLISION_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OVERFLOW_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " EOS_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt Masked Request Register"
|
|
bitfld.long 0x00 7. " INJ_COLLISION_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " INJ_RANGE_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " INJ_SATURATE_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INJ_EOC_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DSI_COLLISION_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " FW_COLLISION_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVERFLOW_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " EOS_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0x220++0x0B
|
|
line.long 0x00 "SATURATE_INTR,Saturate Interrupt Request Register"
|
|
eventfld.long 0x00 15. " SATURATE_INTR[15] ,Saturate interrupt channel 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Saturate interrupt channel 14" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Saturate interrupt channel 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " [12] ,Saturate interrupt channel 12" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " [11] ,Saturate interrupt channel 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Saturate interrupt channel 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " [9] ,Saturate interrupt channel 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Saturate interrupt channel 8" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " [7] ,Saturate interrupt channel 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " [6] ,Saturate interrupt channel 6" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Saturate interrupt channel 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Saturate interrupt channel 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Saturate interrupt channel 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Saturate interrupt channel 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Saturate interrupt channel 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " [0] ,Saturate interrupt channel 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "SATURATE_INTR_SET,Saturate Interrupt Set Request Register"
|
|
bitfld.long 0x04 15. " SATURATE_SET[15] ,Set corresponding bit in interrupt request register for channel 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " [14] ,Set corresponding bit in interrupt request register for channel 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " [13] ,Set corresponding bit in interrupt request register for channel 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 12. " [12] ,Set corresponding bit in interrupt request register for channel 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " [11] ,Set corresponding bit in interrupt request register for channel 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " [10] ,Set corresponding bit in interrupt request register for channel 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [9] ,Set corresponding bit in interrupt request register for channel 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " [8] ,Set corresponding bit in interrupt request register for channel 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " [7] ,Set corresponding bit in interrupt request register for channel 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 6. " [6] ,Set corresponding bit in interrupt request register for channel 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " [5] ,Set corresponding bit in interrupt request register for channel 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " [4] ,Set corresponding bit in interrupt request register for channel 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Set corresponding bit in interrupt request register for channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " [2] ,Set corresponding bit in interrupt request register for channel 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " [1] ,Set corresponding bit in interrupt request register for channel 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " [0] ,Set corresponding bit in interrupt request register for channel 0" "No interrupt,Interrupt"
|
|
line.long 0x08 "SATURATE_INTR_MASK,Saturate Interrupt Mask Register"
|
|
bitfld.long 0x08 15. " SATURATE_MASK[15] ,Mask bit for corresponding bit in interrupt request register for channel 15" "Not masked,Masked"
|
|
bitfld.long 0x08 14. " [14] ,Mask bit for corresponding bit in interrupt request register for channel 14" "Not masked,Masked"
|
|
bitfld.long 0x08 13. " [13] ,Mask bit for corresponding bit in interrupt request register for channel 13" "Not masked,Masked"
|
|
textline " "
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|
bitfld.long 0x08 12. " [12] ,Mask bit for corresponding bit in interrupt request register for channel 12" "Not masked,Masked"
|
|
bitfld.long 0x08 11. " [11] ,Mask bit for corresponding bit in interrupt request register for channel 11" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " [10] ,Mask bit for corresponding bit in interrupt request register for channel 10" "Not masked,Masked"
|
|
textline " "
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|
bitfld.long 0x08 9. " [9] ,Mask bit for corresponding bit in interrupt request register for channel 9" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " [8] ,Mask bit for corresponding bit in interrupt request register for channel 8" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " [7] ,Mask bit for corresponding bit in interrupt request register for channel 7" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x08 6. " [6] ,Mask bit for corresponding bit in interrupt request register for channel 6" "Not masked,Masked"
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|
bitfld.long 0x08 5. " [5] ,Mask bit for corresponding bit in interrupt request register for channel 5" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " [4] ,Mask bit for corresponding bit in interrupt request register for channel 4" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x08 3. " [3] ,Mask bit for corresponding bit in interrupt request register for channel 3" "Not masked,Masked"
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|
bitfld.long 0x08 2. " [2] ,Mask bit for corresponding bit in interrupt request register for channel 2" "Not masked,Masked"
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bitfld.long 0x08 1. " [1] ,Mask bit for corresponding bit in interrupt request register for channel 1" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x08 0. " [0] ,Mask bit for corresponding bit in interrupt request register for channel 0" "Not masked,Masked"
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|
rgroup.long 0x22C++0x03
|
|
line.long 0x00 "SATURATE_INTR_MASKED,Saturate Interrupt Masked Request Register"
|
|
bitfld.long 0x00 15. " SATURATE_MASKED[15] ,Logical AND of corresponding request and mask bit for channel 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Logical AND of corresponding request and mask bit for channel 14" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " [13] ,Logical AND of corresponding request and mask bit for channel 13" "Not masked,Masked"
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|
textline " "
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|
bitfld.long 0x00 12. " [12] ,Logical AND of corresponding request and mask bit for channel 12" "Not masked,Masked"
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|
bitfld.long 0x00 11. " [11] ,Logical AND of corresponding request and mask bit for channel 11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " [10] ,Logical AND of corresponding request and mask bit for channel 10" "Not masked,Masked"
|
|
textline " "
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|
bitfld.long 0x00 9. " [9] ,Logical AND of corresponding request and mask bit for channel 9" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " [8] ,Logical AND of corresponding request and mask bit for channel 8" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " [7] ,Logical AND of corresponding request and mask bit for channel 7" "Not masked,Masked"
|
|
textline " "
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|
bitfld.long 0x00 6. " [6] ,Logical AND of corresponding request and mask bit for channel 6" "Not masked,Masked"
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|
bitfld.long 0x00 5. " [5] ,Logical AND of corresponding request and mask bit for channel 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Logical AND of corresponding request and mask bit for channel 4" "Not masked,Masked"
|
|
textline " "
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|
bitfld.long 0x00 3. " [3] ,Logical AND of corresponding request and mask bit for channel 3" "Not masked,Masked"
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|
bitfld.long 0x00 2. " [2] ,Logical AND of corresponding request and mask bit for channel 2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Logical AND of corresponding request and mask bit for channel 1" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x00 0. " [0] ,Logical AND of corresponding request and mask bit for channel 0" "Not masked,Masked"
|
|
group.long 0x230++0x0B
|
|
line.long 0x00 "RANGE_INTR,Range Detect Interrupt Request Register"
|
|
eventfld.long 0x00 15. " RANGE_INTR[15] ,Range detect interrupt for channel 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Range detect interrupt for channel 14" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Range detect interrupt for channel 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " [12] ,Range detect interrupt for channel 12" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " [11] ,Range detect interrupt for channel 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Range detect interrupt for channel 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " [9] ,Range detect interrupt for channel 9" "No interrupt,Interrupt"
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|
eventfld.long 0x00 8. " [8] ,Range detect interrupt for channel 8" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " [7] ,Range detect interrupt for channel 7" "No interrupt,Interrupt"
|
|
textline " "
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eventfld.long 0x00 6. " [6] ,Range detect interrupt for channel 6" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Range detect interrupt for channel 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Range detect interrupt for channel 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Range detect interrupt for channel 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Range detect interrupt for channel 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Range detect interrupt for channel 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " [0] ,Range detect interrupt for channel 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "RANGE_INTR_SET,Range Detect Interrupt Set Request Register"
|
|
bitfld.long 0x04 15. " RANGE_SET[15] ,Set corresponding bit in interrupt request register for channel 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " [14] ,Set corresponding bit in interrupt request register for channel 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " [13] ,Set corresponding bit in interrupt request register for channel 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 12. " [12] ,Set corresponding bit in interrupt request register for channel 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " [11] ,Set corresponding bit in interrupt request register for channel 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " [10] ,Set corresponding bit in interrupt request register for channel 10" "No interrupt,Interrupt"
|
|
textline " "
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bitfld.long 0x04 9. " [9] ,Set corresponding bit in interrupt request register for channel 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " [8] ,Set corresponding bit in interrupt request register for channel 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " [7] ,Set corresponding bit in interrupt request register for channel 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 6. " [6] ,Set corresponding bit in interrupt request register for channel 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " [5] ,Set corresponding bit in interrupt request register for channel 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " [4] ,Set corresponding bit in interrupt request register for channel 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Set corresponding bit in interrupt request register for channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " [2] ,Set corresponding bit in interrupt request register for channel 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " [1] ,Set corresponding bit in interrupt request register for channel 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " [0] ,Set corresponding bit in interrupt request register for channel 0" "No interrupt,Interrupt"
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|
line.long 0x08 "RANGE_INTR_MASK,Range Detect Interrupt Mask Register"
|
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bitfld.long 0x08 15. " RANGE_INTR_MASK[15] ,Mask bit for corresponding bit in interrupt request register for channel 15" "Not masked,Masked"
|
|
bitfld.long 0x08 14. " [14] ,Mask bit for corresponding bit in interrupt request register for channel 14" "Not masked,Masked"
|
|
bitfld.long 0x08 13. " [13] ,Mask bit for corresponding bit in interrupt request register for channel 13" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x08 12. " [12] ,Mask bit for corresponding bit in interrupt request register for channel 12" "Not masked,Masked"
|
|
bitfld.long 0x08 11. " [11] ,Mask bit for corresponding bit in interrupt request register for channel 11" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " [10] ,Mask bit for corresponding bit in interrupt request register for channel 10" "Not masked,Masked"
|
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textline " "
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bitfld.long 0x08 9. " [9] ,Mask bit for corresponding bit in interrupt request register for channel 9" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " [8] ,Mask bit for corresponding bit in interrupt request register for channel 8" "Not masked,Masked"
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|
bitfld.long 0x08 7. " [7] ,Mask bit for corresponding bit in interrupt request register for channel 7" "Not masked,Masked"
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textline " "
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bitfld.long 0x08 6. " [6] ,Mask bit for corresponding bit in interrupt request register for channel 6" "Not masked,Masked"
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bitfld.long 0x08 5. " [5] ,Mask bit for corresponding bit in interrupt request register for channel 5" "Not masked,Masked"
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bitfld.long 0x08 4. " [4] ,Mask bit for corresponding bit in interrupt request register for channel 4" "Not masked,Masked"
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textline " "
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bitfld.long 0x08 3. " [3] ,Mask bit for corresponding bit in interrupt request register for channel 3" "Not masked,Masked"
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bitfld.long 0x08 2. " [2] ,Mask bit for corresponding bit in interrupt request register for channel 2" "Not masked,Masked"
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bitfld.long 0x08 1. " [1] ,Mask bit for corresponding bit in interrupt request register for channel 1" "Not masked,Masked"
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textline " "
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bitfld.long 0x08 0. " [0] ,Mask bit for corresponding bit in interrupt request register for channel 0" "Not masked,Masked"
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|
rgroup.long 0x23C++0x07
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line.long 0x00 "RANGE_INTR_MASKED,Range Interrupt Masked Request Register"
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bitfld.long 0x00 15. " RANGE_MASKED[15] ,Logical AND of corresponding request and mask bit for channel 15" "Not masked,Masked"
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|
bitfld.long 0x00 14. " [14] ,Logical AND of corresponding request and mask bit for channel 14" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " [13] ,Logical AND of corresponding request and mask bit for channel 13" "Not masked,Masked"
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textline " "
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bitfld.long 0x00 12. " [12] ,Logical AND of corresponding request and mask bit for channel 12" "Not masked,Masked"
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bitfld.long 0x00 11. " [11] ,Logical AND of corresponding request and mask bit for channel 11" "Not masked,Masked"
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bitfld.long 0x00 10. " [10] ,Logical AND of corresponding request and mask bit for channel 10" "Not masked,Masked"
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|
textline " "
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bitfld.long 0x00 9. " [9] ,Logical AND of corresponding request and mask bit for channel 9" "Not masked,Masked"
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bitfld.long 0x00 8. " [8] ,Logical AND of corresponding request and mask bit for channel 8" "Not masked,Masked"
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bitfld.long 0x00 7. " [7] ,Logical AND of corresponding request and mask bit for channel 7" "Not masked,Masked"
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|
textline " "
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bitfld.long 0x00 6. " [6] ,Logical AND of corresponding request and mask bit for channel 6" "Not masked,Masked"
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|
bitfld.long 0x00 5. " [5] ,Logical AND of corresponding request and mask bit for channel 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Logical AND of corresponding request and mask bit for channel 4" "Not masked,Masked"
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|
textline " "
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bitfld.long 0x00 3. " [3] ,Logical AND of corresponding request and mask bit for channel 3" "Not masked,Masked"
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|
bitfld.long 0x00 2. " [2] ,Logical AND of corresponding request and mask bit for channel 2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Logical AND of corresponding request and mask bit for channel 1" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x00 0. " [0] ,Logical AND of corresponding request and mask bit for channel 0" "Not masked,Masked"
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line.long 0x04 "INTR_CAUSE,Interrupt Cause Register"
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bitfld.long 0x04 31. " RANGE_MASKED_RED ,Reduction OR of all SAR_RANGE_INTR_MASKED bits" "Disabled,Enabled"
|
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bitfld.long 0x04 30. " SATURATE_MASKED_RED ,Reduction OR of all SAR_SATURATION_INTR_MASKED bits" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " INJ_COLLISION_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
|
textline " "
|
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bitfld.long 0x04 6. " INJ_RANGE_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
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bitfld.long 0x04 5. " INJ_SATURATE_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
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bitfld.long 0x04 4. " INJ_EOC_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
|
textline " "
|
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bitfld.long 0x04 3. " DSI_COLLISION_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " FW_COLLISION_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " OVERFLOW_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
|
textline " "
|
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bitfld.long 0x04 0. " EOS_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
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group.long 0x280++0x03
|
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line.long 0x00 "INJ_CHAN_CONFIG,Injection Channel Configuration Register"
|
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bitfld.long 0x00 31. " INJ_START_EN ,Set by firmware to enable the injection channel" "Disabled,Enabled"
|
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bitfld.long 0x00 30. " INJ_TAILGATING ,Injection channel tailgating" "Disabled,Enabled"
|
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bitfld.long 0x00 12.--13. " INJ_SAMPLE_TIME_SEL ,Injection sample time select" "0,1,2,3"
|
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textline " "
|
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bitfld.long 0x00 10. " INJ_AVG_EN ,Averaging enable from this channel" "Disabled,Enabled"
|
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bitfld.long 0x00 9. " INJ_RESOLUTION ,RESOLUTION for this channel" "12B,SUBRES"
|
|
bitfld.long 0x00 8. " INJ_DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x00 4.--6. " INJ_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "SARMUX,CTB0,CTB1,CTB2,CTB3,,AROUTE_VIRT,SARMUX_VIRT"
|
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bitfld.long 0x00 0.--2. " INJ_PIN_ADDR ,Address of the pin to be sampled by this injection channel" "0,1,2,3,4,5,6,7"
|
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rgroup.long 0x290++0x03
|
|
line.long 0x00 "INJ_RESULT,Injection Channel Result Register"
|
|
bitfld.long 0x00 31. " INJ_EOC_INTR_MIR ,Mirror bit of corresponding bit in SAR_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " INJ_RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " INJ_SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_INTR register" "No interrupt,Interrupt"
|
|
textline " "
|
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bitfld.long 0x00 28. " INJ_COLLISION_INTR_MIR ,Mirror bit of corresponding bit in SAR_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " INJ_NEWVALUE ,The data in this register received a new value" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INJ_RESULT ,16-bit SAR conversion result of the channel"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
if (((per.l(ad:0x403A0000+0x2A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2A0++0x03
|
|
line.long 0x00 "STATUS,Current Status Of Internal SAR Registers"
|
|
bitfld.long 0x00 31. " BUSY ,If high then the SAR is busy with a conversion" "Idle,Busy"
|
|
bitfld.long 0x00 30. " SW_VREF_NEG ,The current switch status" "0,1"
|
|
bitfld.long 0x00 0.--4. " CUR_CHAN ,Current channel being sampled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
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else
|
|
rgroup.long 0x2A0++0x03
|
|
line.long 0x00 "STATUS,Current Status Of Internal SAR Registers"
|
|
bitfld.long 0x00 31. " BUSY ,If high then the SAR is busy with a conversion" "Idle,Busy"
|
|
bitfld.long 0x00 30. " SW_VREF_NEG ,The current switch status" "0,1"
|
|
endif
|
|
rgroup.long 0x2A4++0x03
|
|
line.long 0x00 "AVG_STAT,Current Averaging Status"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CUR_AVG_CNT ,7-bit current value of the averaging counter"
|
|
bitfld.long 0x00 23. " INTRLV_BUSY ,If high then the SAR is in the middle of interleaved averaging spanning several scans" "Idle,Busy"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CUR_AVG_ACCU ,20-bit current value of averaging accumulator"
|
|
endif
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "MUX_SWITCH0,SARMUX Firmware Switch Controls"
|
|
bitfld.long 0x00 29. " MUX_FW_P7_COREIO3 ,Firmware control switch between pin P7 and coreio3" "Open,Closed"
|
|
bitfld.long 0x00 28. " MUX_FW_P6_COREIO2 ,Firmware control switch between pin P6 and coreio2" "Open,Closed"
|
|
bitfld.long 0x00 27. " MUX_FW_P5_COREIO1 ,Firmware control switch between pin P5 and coreio1" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 26. " MUX_FW_P4_COREIO0 ,Firmware control switch between pin P4 and coreio0" "Open,Closed"
|
|
bitfld.long 0x00 25. " MUX_FW_SARBUS1_VMINUS ,Firmware control switch between sarbus1 and vminus" "Open,Closed"
|
|
bitfld.long 0x00 24. " MUX_FW_SARBUS0_VMINUS ,Firmware control switch between sarbus0 and vminus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MUX_FW_SARBUS1_VPLUS ,Firmware control switch between sarbus1 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 22. " MUX_FW_SARBUS0_VPLUS ,Firmware control switch between sarbus0 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 21. " MUX_FW_AMUXBUSB_VMINUS ,Firmware control switch between amuxbusb and vminus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MUX_FW_AMUXBUSA_VMINUS ,Firmware control switch between amuxbusa and vminus" "Open,Closed"
|
|
bitfld.long 0x00 19. " MUX_FW_AMUXBUSB_VPLUS ,Firmware control switch between amuxbusb and vplus" "Open,Closed"
|
|
bitfld.long 0x00 18. " MUX_FW_AMUXBUSA_VPLUS ,Firmware control switch between amuxbusa and vplus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MUX_FW_TEMP_VPLUS ,Firmware control switch between temperature sensor and vplus also powers on the temperature sensor" "Open,Closed"
|
|
bitfld.long 0x00 16. " MUX_FW_VSSA_VMINUS ,Firmware control switch between vssa_kelvin and vminus" "Open,Closed"
|
|
bitfld.long 0x00 15. " MUX_FW_P7_VMINUS ,Firmware control switch between pin P7 and vminus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MUX_FW_P6_VMINUS ,Firmware control switch betweeen pin P6 and vminus" "Open,Closed"
|
|
bitfld.long 0x00 13. " MUX_FW_P5_VMINUS ,Firmware control switch betweeen pin P5 and vminus" "Open,Closed"
|
|
bitfld.long 0x00 12. " MUX_FW_P4_VMINUS ,Firmware control switch betweeen pin P4 and vminus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MUX_FW_P3_VMINUS ,Firmware control switch betweeen pin P3 and vminus" "Open,Closed"
|
|
bitfld.long 0x00 10. " MUX_FW_P2_VMINUS ,Firmware control switch betweeen pin P2 and vminus" "Open,Closed"
|
|
bitfld.long 0x00 9. " MUX_FW_P1_VMINUS ,Firmware control switch betweeen pin P1 and vminus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MUX_FW_P0_VMINUS ,Firmware control switch betweeen pin P0 and vminus" "Open,Closed"
|
|
bitfld.long 0x00 7. " MUX_FW_P7_VPLUS ,Firmware control switch betweeen pin P7 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 6. " MUX_FW_P6_VPLUS ,Firmware control switch betweeen pin P6 and vplus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MUX_FW_P5_VPLUS ,Firmware control switch betweeen pin P5 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 4. " MUX_FW_P4_VPLUS ,Firmware control switch betweeen pin P4 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 3. " MUX_FW_P3_VPLUS ,Firmware control switch betweeen pin P3 and vplus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MUX_FW_P2_VPLUS ,Firmware control switch betweeen pin P2 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 1. " MUX_FW_P1_VPLUS ,Firmware control switch betweeen pin P1 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 0. " MUX_FW_P0_VPLUS ,Firmware control switch betweeen pin P0 and vplus" "Open,Closed"
|
|
line.long 0x04 "MUX_SWITCH_CLEAR0,SARMUX Firmware Switch Control Clear"
|
|
eventfld.long 0x04 29. " MUX_FW_P7_COREIO3 ,Firmware control switch between pin P7 and coreio3" "Not cleared,Cleared"
|
|
eventfld.long 0x04 28. " MUX_FW_P6_COREIO2 ,Firmware control switch between pin P6 and coreio2" "Not cleared,Cleared"
|
|
eventfld.long 0x04 27. " MUX_FW_P5_COREIO1 ,Firmware control switch between pin P5 and coreio1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 26. " MUX_FW_P4_COREIO0 ,Firmware control switch between pin P4 and coreio0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 25. " MUX_FW_SARBUS1_VMINUS ,Firmware control switch between sarbus1 and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 24. " MUX_FW_SARBUS0_VMINUS ,Firmware control switch between sarbus0 and vminus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 23. " MUX_FW_SARBUS1_VPLUS ,Firmware control switch between sarbus1 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 22. " MUX_FW_SARBUS0_VPLUS ,Firmware control switch between sarbus0 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 21. " MUX_FW_AMUXBUSB_VMINUS ,Firmware control switch between amuxbusb and vminus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 20. " MUX_FW_AMUXBUSA_VMINUS ,Firmware control switch between amuxbusa and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 19. " MUX_FW_AMUXBUSB_VPLUS ,Firmware control switch between amuxbusb and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 18. " MUX_FW_AMUXBUSA_VPLUS ,Firmware control switch between amuxbusa and vplus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 17. " MUX_FW_TEMP_VPLUS ,Firmware control switch between temperature sensor and vplus also powers on the temperature sensor" "Not cleared,Cleared"
|
|
eventfld.long 0x04 16. " MUX_FW_VSSA_VMINUS ,Firmware control switch between vssa_kelvin and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 15. " MUX_FW_P7_VMINUS ,Firmware control switch between pin P7 and vminus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 14. " MUX_FW_P6_VMINUS ,Firmware control switch betweeen pin P6 and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 13. " MUX_FW_P5_VMINUS ,Firmware control switch betweeen pin P5 and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 12. " MUX_FW_P4_VMINUS ,Firmware control switch betweeen pin P4 and vminus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 11. " MUX_FW_P3_VMINUS ,Firmware control switch betweeen pin P3 and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 10. " MUX_FW_P2_VMINUS ,Firmware control switch betweeen pin P2 and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 9. " MUX_FW_P1_VMINUS ,Firmware control switch betweeen pin P1 and vminus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 8. " MUX_FW_P0_VMINUS ,Firmware control switch betweeen pin P0 and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 7. " MUX_FW_P7_VPLUS ,Firmware control switch betweeen pin P7 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 6. " MUX_FW_P6_VPLUS ,Firmware control switch betweeen pin P6 and vplus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 5. " MUX_FW_P5_VPLUS ,Firmware control switch betweeen pin P5 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 4. " MUX_FW_P4_VPLUS ,Firmware control switch betweeen pin P4 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 3. " MUX_FW_P3_VPLUS ,Firmware control switch betweeen pin P3 and vplus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 2. " MUX_FW_P2_VPLUS ,Firmware control switch betweeen pin P2 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 1. " MUX_FW_P1_VPLUS ,Firmware control switch betweeen pin P1 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 0. " MUX_FW_P0_VPLUS ,Firmware control switch betweeen pin P0 and vplus" "Not cleared,Cleared"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x308++0x07
|
|
line.long 0x00 "MUX_SWITCH1,SARMUX Firmware Switch Controls"
|
|
bitfld.long 0x00 3. " MUX_FW_ADFT1_SARBUS1 ,Switch between adft1 signal and sarbus1 signal" "Open,Closed"
|
|
bitfld.long 0x00 2. " MUX_FW_ADFT0_SARBUS0 ,Switch between adft0 signal and sarbus0 signal" "Open,Closed"
|
|
bitfld.long 0x00 1. " MUX_FW_P5_DFT_INM ,Switch between P5 pin and dft_inm signal" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MUX_FW_P4_DFT_INP ,Switch between P4 pin and dft_inp signal" "Open,Closed"
|
|
line.long 0x04 "MUX_SWITCH_CLEAR1,SARMUX Firmware Switch Control Clear"
|
|
eventfld.long 0x04 3. " MUX_FW_ADFT1_SARBUS1 ,Switch between adft1 signal and sarbus1 signal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " MUX_FW_ADFT0_SARBUS0 ,Switch between adft0 signal and sarbus0 signal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 1. " MUX_FW_P5_DFT_INM ,Switch between P5 pin and dft_inm signal" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 0. " MUX_FW_P4_DFT_INP ,Switch between P4 pin and dft_inp signal" "Not cleared,Cleared"
|
|
endif
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "MUX_SWITCH_HW_CTRL,SARMUX Switch Hardware Control"
|
|
bitfld.long 0x00 23. " MUX_HW_CTRL_SARBUS1 ,Hardware control masked by firmware setting for sarbus1 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 22. " MUX_HW_CTRL_SARBUS0 ,Hardware control masked by firmware setting for sarbus0 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 19. " MUX_HW_CTRL_AMUXBUSB ,Hardware control masked by firmware setting for amuxbusb switches" "Firmware,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MUX_HW_CTRL_AMUXBUSA ,Hardware control masked by firmware setting for amuxbusa switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 17. " MUX_HW_CTRL_TEMP ,Hardware control masked by firmware setting for temp switch" "Firmware,Hardware"
|
|
bitfld.long 0x00 16. " MUX_HW_CTRL_VSSA ,Hardware control masked by firmware setting for vssa switch" "Firmware,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MUX_HW_CTRL_P7 ,Hardware control masked by firmware setting for pin P7 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 6. " MUX_HW_CTRL_P6 ,Hardware control masked by firmware setting for pin P6 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 5. " MUX_HW_CTRL_P5 ,Hardware control masked by firmware setting for pin P5 switches" "Firmware,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MUX_HW_CTRL_P4 ,Hardware control masked by firmware setting for pin P4 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 3. " MUX_HW_CTRL_P3 ,Hardware control masked by firmware setting for pin P3 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 2. " MUX_HW_CTRL_P2 ,Hardware control masked by firmware setting for pin P2 switches" "Firmware,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUX_HW_CTRL_P1 ,Hardware control masked by firmware setting for pin P1 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 0. " MUX_HW_CTRL_P0 ,Hardware control masked by firmware setting for pin P0 switches" "Firmware,Hardware"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "MUX_SWITCH_STATUS,SARMUX Switch Status"
|
|
bitfld.long 0x00 25. " MUX_FW_SARBUS1_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 24. " MUX_FW_SARBUS0_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 23. " MUX_FW_SARBUS1_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MUX_FW_SARBUS0_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 21. " MUX_FW_AMUXBUSB_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 20. " MUX_FW_AMUXBUSA_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MUX_FW_AMUXBUSB_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 18. " MUX_FW_AMUXBUSA_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 17. " MUX_FW_TEMP_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MUX_FW_VSSA_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 15. " MUX_FW_P7_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 14. " MUX_FW_P6_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MUX_FW_P5_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 12. " MUX_FW_P4_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 11. " MUX_FW_P3_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MUX_FW_P2_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 9. " MUX_FW_P1_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 8. " MUX_FW_P0_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MUX_FW_P7_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 6. " MUX_FW_P6_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 5. " MUX_FW_P5_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MUX_FW_P4_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 3. " MUX_FW_P3_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 2. " MUX_FW_P2_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUX_FW_P1_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 0. " MUX_FW_P0_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "PUMP_CTRL,Switch Pump Control"
|
|
bitfld.long 0x00 31. " ENABLED ,SAR pump output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CLOCK_SEL ,Clock select" "External,Internal"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "ANA_TRIM,Analog Trim Register"
|
|
bitfld.long 0x00 3. " TRIMUNIT ,Attenuation cap trimming" "0,1"
|
|
bitfld.long 0x00 0.--2. " CAP_TRIM ,Attenuation cap trimming" "0,1,2,3,4,5,6,7"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0xF04++0x03
|
|
line.long 0x00 "WOUNDING,SAR Wounding Register"
|
|
bitfld.long 0x00 0.--1. " WOUND_RESOLUTION ,Maximum SAR resolution allowed" "12bit,10bit,8bit,8bit"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Analog Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,SAR enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "SCB (Serial Communication Block)"
|
|
tree "SCB0"
|
|
base ad:0x40240000
|
|
if (((per.l(ad:0x40240000))&0x3000000)==0x0000000)
|
|
width 12.
|
|
if (((per.l(ad:0x40240000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40240000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40240000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40240000+0x60))&0xC0000000)==0xC0000000)
|
|
if (((per.l(ad:0x40240000))&0x100)==0x100)&&((((per.l(ad:0x40240000))&0x200)==0x000)||(((per.l(ad:0x40240000+0x60))&0x800)==0x800)||(((per.l(ad:0x40240000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40240000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40240000))&0x100)==0x000)&&(((per.l(ad:0x40240000))&0x200)==0x000)&&(((per.l(ad:0x40240000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40240000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40240000+0x60))&0xC0000000)==0x80000000)
|
|
if (((per.l(ad:0x40240000))&0x100)==0x100)&&((((per.l(ad:0x40240000))&0x200)==0x000)||(((per.l(ad:0x40240000+0x60))&0x800)==0x800)||(((per.l(ad:0x40240000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40240000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif (((per.l(ad:0x40240000))&0x100)==0x000)&&(((per.l(ad:0x40240000))&0x200)==0x000)&&(((per.l(ad:0x40240000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((per.l(ad:0x40240000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40240000+0x60))&0xC0000000)==0x40000000)
|
|
if (((per.l(ad:0x40240000))&0x100)==0x100)&&((((per.l(ad:0x40240000))&0x200)==0x000)||(((per.l(ad:0x40240000+0x60))&0x800)==0x800)||(((per.l(ad:0x40240000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40240000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40240000))&0x100)==0x000)&&(((per.l(ad:0x40240000))&0x200)==0x000)&&(((per.l(ad:0x40240000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40240000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40240000))&0x100)==0x100)&&((((per.l(ad:0x40240000))&0x200)==0x000)||(((per.l(ad:0x40240000+0x60))&0x800)==0x800)||(((per.l(ad:0x40240000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40240000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40240000))&0x100)==0x000)&&(((per.l(ad:0x40240000))&0x200)==0x000)&&(((per.l(ad:0x40240000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40240000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40240000))&0x200)==0x000)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "I2C_STATUS,I2C Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BASE_EZ_ADDR ,I2C slave base EZ address"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CURR_EZ_ADDR ,I2C slave current EZ address"
|
|
bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer"
|
|
textline " "
|
|
bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer"
|
|
bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy"
|
|
else
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "I2C_STATUS,I2C Status Register"
|
|
bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer"
|
|
textline " "
|
|
bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer"
|
|
bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy"
|
|
endif
|
|
if (((per.l(ad:0x40240000+0x60))&0x80000000)==0x80000000)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "I2C_M_CMD,I2C Master Command Register"
|
|
bitfld.long 0x00 4. " M_STOP ,Master transmit STOP" "Disabled,ENABLED"
|
|
bitfld.long 0x00 3. " M_NACK ,Master negative acknowledgement transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " M_ACK ,Master acknowledgement transmit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M_START_ON_IDLE ,Master START on idle" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " M_START ,Master transmit START" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "I2C_M_CMD,I2C Master Command Register"
|
|
endif
|
|
if (((per.l(ad:0x40240000+0x60))&0x40000000)==0x40000000)
|
|
if (((per.l(ad:0x40240000))&0x400)==0x400)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " S_ACK ,Slave acknowledgement transmit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "I2C_CFG,I2C Configuration Register"
|
|
bitfld.long 0x00 28.--29. " SDA_OUT_FILT_SEL ,Selection of cumulative 'i2c_sda_out' filter delay" "0 ns,50 ns,100 ns,150 ns"
|
|
bitfld.long 0x00 20.--21. " SDA_OUT_FILT2_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " SDA_OUT_FILT1_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SDA_OUT_FILT0_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3"
|
|
bitfld.long 0x00 12. " SCL_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns"
|
|
bitfld.long 0x00 8.--9. " SCL_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SDA_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns"
|
|
bitfld.long 0x00 0.--1. " SDA_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
|
|
width 0x0B
|
|
elif (((per.l(ad:0x40240000))&0x3000000)==0x1000000)
|
|
width 22.
|
|
if (((per.l(ad:0x40240000+0x20))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40240000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40240000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40240000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40240000+0x20))&0x3000000)==0x0000000)
|
|
if (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.l(ad:0x40240000+0x20))&0x3000000)==0x2000000)
|
|
if (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.l(ad:0x40240000+0x20))&0x3000000)==0x1000000)
|
|
if (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40240000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40240000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40240000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40240000+0x20))&0x3000000)==0x0000000)
|
|
if (((per.l(ad:0x40240000+0x20))&0x8)==0x0)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
endif
|
|
elif (((per.l(ad:0x40240000+0x20))&0x3000000)==0x2000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
elif (((per.l(ad:0x40240000+0x20))&0x3000000)==0x1000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40240000))&0x200)==0x000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SPI_STATUS,SPI Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " BASE_EZ_ADDR ,SPI base EZ address"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " CURR_EZ_ADDR ,SPI current EZ address"
|
|
bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SPI_STATUS,SPI Status Register"
|
|
bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x40240000))&0x3000000)==0x2000000)
|
|
width 21.
|
|
if (((per.l(ad:0x40240000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40240000))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40240000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40240000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..."
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40240000))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40240000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40240000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "UART_CTRL,UART Control Register"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of UART operation" "UART_STD,UART_SMARTCARD,UART_IRDA,?..."
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
if (((per.l(ad:0x40240000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 5. " PARITY_ENABLED ,Parity generation enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 13. " SKIP_START ,Skips start bit detection for the first received data frame" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LIN_MODE ,Break detection and baud rate detection on the incoming data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PARITY_ENABLED ,Parity checking enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 8. " RETRY_ON_NACK ,Retransmitted when negative acknowledgement is received" "Not retransmitted,Retransmitted"
|
|
rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 6. " POLARITY ,Inverts incoming RX line signal" "Low,High"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "UART_RX_STATUS,UART Receiver Status Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " BR_COUNTER ,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "UART_FLOW_CTRL,UART Flow Control Register"
|
|
bitfld.long 0x00 25. " CTS_ENABLED ,Enable use of CTS input signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CTS_POLARITY ,Polarity of the CTS input signal" "Low,High"
|
|
bitfld.long 0x00 16. " RTS_POLARITY ,Polarity of the RTS output signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
else
|
|
width 18.
|
|
if (((per.l(ad:0x40240000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
endif
|
|
endif
|
|
textline " "
|
|
width 20.
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "TX_CTRL,Transmitter Control Register"
|
|
bitfld.long 0x00 8. " MSB_FIRST ,Least significant bit first or most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TX_FIFO_CTRL,Transmitter FIFO Control Register"
|
|
bitfld.long 0x04 17. " FREEZE ,Freeze will not advance TX FIFO read pointer" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CLEAR ,Transmitter FIFO and transmitter shift register cleared" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO Status Register"
|
|
bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " SR_VALID ,Indicates whether the TX shift registers holds a valid data frame" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " USED ,Amount of entries in the transmitter FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
wgroup.long 0x240++0x03
|
|
line.long 0x00 "TX_FIFO_WR,Transmitter FIFO Write Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,16-bit data frame written into the transmitter FIFO"
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "RX_CTRL,Receiver Control Register"
|
|
bitfld.long 0x00 9. " MEDIAN ,Median filter" "0,Digital 3 taps median filter"
|
|
bitfld.long 0x00 8. " MSB_FIRST ,Least significant bit first or most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "RX_FIFO_CTRL,Receiver FIFO Control Register"
|
|
bitfld.long 0x04 17. " FREEZE ,Freeze will not advance TX FIFO read pointer" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CLEAR ,Transmitter FIFO and transmitter shift register cleared" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO Status Register"
|
|
bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " SR_VALID ,Indicates whether the RX shift registers holds a valid data frame" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " USED ,Amount od enties in the receiver FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "RX_MATCH,Slave Address And Mask Register"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " MASK ,Slave device address mask"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Slave device address"
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "RX_FIFO_RD,Receiver FIFO Read Register"
|
|
in
|
|
hgroup.long 0x344++0x03
|
|
hide.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO Read Register"
|
|
in
|
|
hgroup.long 0x400++0x03
|
|
hide.long 0x00 "EZ_DATA0,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x404++0x03
|
|
hide.long 0x00 "EZ_DATA1,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x408++0x03
|
|
hide.long 0x00 "EZ_DATA2,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x40C++0x03
|
|
hide.long 0x00 "EZ_DATA3,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "EZ_DATA4,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "EZ_DATA5,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "EZ_DATA6,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "EZ_DATA7,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x00 "EZ_DATA8,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x424++0x03
|
|
hide.long 0x00 "EZ_DATA9,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x428++0x03
|
|
hide.long 0x00 "EZ_DATA10,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x42C++0x03
|
|
hide.long 0x00 "EZ_DATA11,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x430++0x03
|
|
hide.long 0x00 "EZ_DATA12,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x434++0x03
|
|
hide.long 0x00 "EZ_DATA13,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x438++0x03
|
|
hide.long 0x00 "EZ_DATA14,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x43C++0x03
|
|
hide.long 0x00 "EZ_DATA15,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x440++0x03
|
|
hide.long 0x00 "EZ_DATA16,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x444++0x03
|
|
hide.long 0x00 "EZ_DATA17,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x448++0x03
|
|
hide.long 0x00 "EZ_DATA18,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x44C++0x03
|
|
hide.long 0x00 "EZ_DATA19,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x450++0x03
|
|
hide.long 0x00 "EZ_DATA20,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x454++0x03
|
|
hide.long 0x00 "EZ_DATA21,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x458++0x03
|
|
hide.long 0x00 "EZ_DATA22,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x45C++0x03
|
|
hide.long 0x00 "EZ_DATA23,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x460++0x03
|
|
hide.long 0x00 "EZ_DATA24,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x464++0x03
|
|
hide.long 0x00 "EZ_DATA25,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x468++0x03
|
|
hide.long 0x00 "EZ_DATA26,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x46C++0x03
|
|
hide.long 0x00 "EZ_DATA27,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x470++0x03
|
|
hide.long 0x00 "EZ_DATA28,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x474++0x03
|
|
hide.long 0x00 "EZ_DATA29,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x478++0x03
|
|
hide.long 0x00 "EZ_DATA30,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x47C++0x03
|
|
hide.long 0x00 "EZ_DATA31,Memory Buffer Registers"
|
|
in
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "INTR_CAUSE,Active Clock Interrupt Signal Register"
|
|
bitfld.long 0x00 5. " SPI_EC ,Externally clocked SPI interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 4. " I2C_EC ,Externally clocked I2C interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RX ,Receiver interrupt active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX ,Transmitter interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S ,Slave interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 0. " M ,Master interrupt active" "Inactive,Active"
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register"
|
|
eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt"
|
|
group.long 0xE88++0x03
|
|
line.long 0x00 "INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xE8C++0x03
|
|
line.long 0x00 "INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xEC0++0x03
|
|
line.long 0x00 "INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register"
|
|
eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt"
|
|
group.long 0xEC8++0x03
|
|
line.long 0x00 "INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xECC++0x03
|
|
line.long 0x00 "INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF00++0x0B
|
|
line.long 0x00 "INTR_M,Master Interrupt Request Register"
|
|
eventfld.long 0x00 9. " SPI_DONE ,SPI master transfer done event" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " I2C_BUS_ERROR ,I2C master bus error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " I2C_STOP ,I2C master STOP" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " I2C_ACK ,I2C master acknowledgement" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " I2C_NACK ,I2C master negative acknowledgement" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " I2C_ARB_LOST ,I2C master lost arbitration" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_M_SET,Master Interrupt Set Request Register"
|
|
bitfld.long 0x04 9. " SPI_DONE ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " I2C_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I2C_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " I2C_ACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I2C_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I2C_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_M_MASK,Master Interrupt Mask Register"
|
|
bitfld.long 0x08 9. " SPI_DONE ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " I2C_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " I2C_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " I2C_ACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " I2C_NACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " I2C_ARB_LOST ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xF0C++0x03
|
|
line.long 0x00 "INTR_M_MASKED,Master Interrupt Masked Request Register"
|
|
bitfld.long 0x00 9. " SPI_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF40++0x0B
|
|
line.long 0x00 "INTR_S,Slave Interrupt Request Register"
|
|
eventfld.long 0x00 11. " SPI_BUS_ERROR ,SPI slave deselected at an unexpected time in the SPI transfer" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " SPI_EZ_STOP ,SPI slave deselected after any EZ SPI transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,SPI slave deselected after a write EZ SPI transfer occurred" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " I2C_BUS_ERROR ,I2C slave bus error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " I2C_GENERAL ,I2C slave general call address received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " I2C_ADDR_MATCH ,I2C slave matching address received" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " I2C_START ,I2C slave START received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " I2C_STOP ,I2C STOP event for I2C transfer intended for this slave" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " I2C_WRITE_STOP ,I2C STOP event for I2C write transfer intended for this slave" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " I2C_ACK ,I2C slave acknowledgement received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " I2C_NACK ,I2C slave negative acknowledgement received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " I2C_ARB_LOST ,I2C slave lost arbitration" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_S_SET,Slave Interrupt Set Request Register"
|
|
bitfld.long 0x04 11. " SPI_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " SPI_EZ_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " SPI_EZ_WRITE_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " I2C_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " I2C_GENERAL ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " I2C_ADDR_MATCH ,Set corresponding bit in interrupt request registe" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I2C_START ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I2C_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " I2C_WRITE_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " I2C_ACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I2C_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I2C_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_S_MASK,Slave Interrupt Mask Register"
|
|
bitfld.long 0x08 11. " SPI_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " SPI_EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " SPI_EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 8. " I2C_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " I2C_GENERAL ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " I2C_ADDR_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 5. " I2C_START ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " I2C_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " I2C_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " I2C_ACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " I2C_NACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " I2C_ARB_LOST ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xF4C++0x03
|
|
line.long 0x00 "INTR_S_MASKED,Slave Interrupt Masked Request Register"
|
|
bitfld.long 0x00 11. " SPI_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " SPI_EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " I2C_GENERAL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " I2C_ADDR_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I2C_START ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " I2C_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF80++0x0B
|
|
line.long 0x00 "INTR_TX,Transmitter Interrupt Request Register"
|
|
eventfld.long 0x00 10. " UART_ARB_LOST ,UART lost arbitration" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " UART_DONE ,UART transmitter done event" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " UART_NACK ,UART transmitter received a negative acknowledgement in smartcard mode" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " BLOCKED ,AHB-Lite write transfer can not get access to the EZ memory" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty TX FIFO" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full TX FIFO" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " EMPTY ,TX FIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " NOT_FULL ,TX FIFO is not full" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " TRIGGER ,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_TX_SET,Transmitter Interrupt Set Request Register"
|
|
bitfld.long 0x04 10. " UART_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " UART_DONE ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " UART_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " BLOCKED ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " UNDERFLOW ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " OVERFLOW ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " EMPTY ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " NOT_FULL ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " TIGGER ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_TX_MASK,Transmitter Interrupt Mask Register"
|
|
bitfld.long 0x08 10. " UART_ARB_LOST ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " UART_DONE ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " UART_NACK ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " BLOCKED ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " UNDERFLOW ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " OVERFLOW ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 4. " EMPTY ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " NOT_FULL ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TRIGGER ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
rgroup.long 0xF8C++0x03
|
|
line.long 0x00 "INTR_TX_MASKED,Transmitter Interrupt Masked Request Register"
|
|
bitfld.long 0x00 10. " UART_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " UART_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " UART_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " NOT_FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xFC0++0x0B
|
|
line.long 0x00 "INTR_RX,Receiver Interrupt Request Register"
|
|
eventfld.long 0x00 11. " BREAK_DETECT ,Break detection successful" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " BAUD_DETECT ,LIN baudrate detection is completed" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " PARITY_ERROR ,Parity error in received data frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " FRAME_ERROR ,Frame error in received data frame" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " BLOCKED ,AHB-Lite read transfer can not get access to the EZ memory" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty RX FIFO" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full RX FIFO" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " FULL ,RX FIFO is full" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " NOT_EMPTY ,RX FIFO is not empty" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TRIGGER ,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_RX_SET,Receiver Interrupt Set Request Register"
|
|
bitfld.long 0x04 11. " BREAK_DETECT ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " BAUD_DETECT ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " PARITY_ERROR ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " FRAME_ERROR ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " BLOCKED ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " UNDERFLOW ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OVERFLOW ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " FULL ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " NOT_EMPTY ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRIGGER ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_RX_MASK,Receiver Interrupt Mask Register"
|
|
bitfld.long 0x08 11. " BREAK_DETECT ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " BAUD_DETECT ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " PARITY_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 8. " FRAME_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " BLOCKED ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " UNDERFLOW ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OVERFLOW ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " FULL ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " NOT_EMPTY ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TRIGGER ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "INTR_RX_MASKED,Receiver Interrupt Masked Request Register"
|
|
bitfld.long 0x00 11. " BREAK_DETECT ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " BAUD_DETECT ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " PARITY_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FRAME_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " NOT_EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCB1"
|
|
base ad:0x40250000
|
|
if (((per.l(ad:0x40250000))&0x3000000)==0x0000000)
|
|
width 12.
|
|
if (((per.l(ad:0x40250000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40250000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40250000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40250000+0x60))&0xC0000000)==0xC0000000)
|
|
if (((per.l(ad:0x40250000))&0x100)==0x100)&&((((per.l(ad:0x40250000))&0x200)==0x000)||(((per.l(ad:0x40250000+0x60))&0x800)==0x800)||(((per.l(ad:0x40250000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40250000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40250000))&0x100)==0x000)&&(((per.l(ad:0x40250000))&0x200)==0x000)&&(((per.l(ad:0x40250000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40250000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40250000+0x60))&0xC0000000)==0x80000000)
|
|
if (((per.l(ad:0x40250000))&0x100)==0x100)&&((((per.l(ad:0x40250000))&0x200)==0x000)||(((per.l(ad:0x40250000+0x60))&0x800)==0x800)||(((per.l(ad:0x40250000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40250000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif (((per.l(ad:0x40250000))&0x100)==0x000)&&(((per.l(ad:0x40250000))&0x200)==0x000)&&(((per.l(ad:0x40250000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((per.l(ad:0x40250000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40250000+0x60))&0xC0000000)==0x40000000)
|
|
if (((per.l(ad:0x40250000))&0x100)==0x100)&&((((per.l(ad:0x40250000))&0x200)==0x000)||(((per.l(ad:0x40250000+0x60))&0x800)==0x800)||(((per.l(ad:0x40250000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40250000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40250000))&0x100)==0x000)&&(((per.l(ad:0x40250000))&0x200)==0x000)&&(((per.l(ad:0x40250000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40250000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40250000))&0x100)==0x100)&&((((per.l(ad:0x40250000))&0x200)==0x000)||(((per.l(ad:0x40250000+0x60))&0x800)==0x800)||(((per.l(ad:0x40250000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40250000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40250000))&0x100)==0x000)&&(((per.l(ad:0x40250000))&0x200)==0x000)&&(((per.l(ad:0x40250000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40250000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40250000))&0x200)==0x000)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "I2C_STATUS,I2C Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BASE_EZ_ADDR ,I2C slave base EZ address"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CURR_EZ_ADDR ,I2C slave current EZ address"
|
|
bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer"
|
|
textline " "
|
|
bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer"
|
|
bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy"
|
|
else
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "I2C_STATUS,I2C Status Register"
|
|
bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer"
|
|
textline " "
|
|
bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer"
|
|
bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy"
|
|
endif
|
|
if (((per.l(ad:0x40250000+0x60))&0x80000000)==0x80000000)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "I2C_M_CMD,I2C Master Command Register"
|
|
bitfld.long 0x00 4. " M_STOP ,Master transmit STOP" "Disabled,ENABLED"
|
|
bitfld.long 0x00 3. " M_NACK ,Master negative acknowledgement transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " M_ACK ,Master acknowledgement transmit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M_START_ON_IDLE ,Master START on idle" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " M_START ,Master transmit START" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "I2C_M_CMD,I2C Master Command Register"
|
|
endif
|
|
if (((per.l(ad:0x40250000+0x60))&0x40000000)==0x40000000)
|
|
if (((per.l(ad:0x40250000))&0x400)==0x400)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " S_ACK ,Slave acknowledgement transmit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "I2C_CFG,I2C Configuration Register"
|
|
bitfld.long 0x00 28.--29. " SDA_OUT_FILT_SEL ,Selection of cumulative 'i2c_sda_out' filter delay" "0 ns,50 ns,100 ns,150 ns"
|
|
bitfld.long 0x00 20.--21. " SDA_OUT_FILT2_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " SDA_OUT_FILT1_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SDA_OUT_FILT0_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3"
|
|
bitfld.long 0x00 12. " SCL_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns"
|
|
bitfld.long 0x00 8.--9. " SCL_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SDA_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns"
|
|
bitfld.long 0x00 0.--1. " SDA_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
|
|
width 0x0B
|
|
elif (((per.l(ad:0x40250000))&0x3000000)==0x1000000)
|
|
width 22.
|
|
if (((per.l(ad:0x40250000+0x20))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40250000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40250000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40250000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40250000+0x20))&0x3000000)==0x0000000)
|
|
if (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.l(ad:0x40250000+0x20))&0x3000000)==0x2000000)
|
|
if (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.l(ad:0x40250000+0x20))&0x3000000)==0x1000000)
|
|
if (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40250000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40250000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40250000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40250000+0x20))&0x3000000)==0x0000000)
|
|
if (((per.l(ad:0x40250000+0x20))&0x8)==0x0)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
endif
|
|
elif (((per.l(ad:0x40250000+0x20))&0x3000000)==0x2000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
elif (((per.l(ad:0x40250000+0x20))&0x3000000)==0x1000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40250000))&0x200)==0x000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SPI_STATUS,SPI Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " BASE_EZ_ADDR ,SPI base EZ address"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " CURR_EZ_ADDR ,SPI current EZ address"
|
|
bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SPI_STATUS,SPI Status Register"
|
|
bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x40250000))&0x3000000)==0x2000000)
|
|
width 21.
|
|
if (((per.l(ad:0x40250000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40250000))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40250000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40250000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..."
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40250000))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40250000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40250000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "UART_CTRL,UART Control Register"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of UART operation" "UART_STD,UART_SMARTCARD,UART_IRDA,?..."
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
if (((per.l(ad:0x40250000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 5. " PARITY_ENABLED ,Parity generation enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 13. " SKIP_START ,Skips start bit detection for the first received data frame" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LIN_MODE ,Break detection and baud rate detection on the incoming data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PARITY_ENABLED ,Parity checking enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 8. " RETRY_ON_NACK ,Retransmitted when negative acknowledgement is received" "Not retransmitted,Retransmitted"
|
|
rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 6. " POLARITY ,Inverts incoming RX line signal" "Low,High"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "UART_RX_STATUS,UART Receiver Status Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " BR_COUNTER ,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "UART_FLOW_CTRL,UART Flow Control Register"
|
|
bitfld.long 0x00 25. " CTS_ENABLED ,Enable use of CTS input signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CTS_POLARITY ,Polarity of the CTS input signal" "Low,High"
|
|
bitfld.long 0x00 16. " RTS_POLARITY ,Polarity of the RTS output signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
else
|
|
width 18.
|
|
if (((per.l(ad:0x40250000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
endif
|
|
endif
|
|
textline " "
|
|
width 20.
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "TX_CTRL,Transmitter Control Register"
|
|
bitfld.long 0x00 8. " MSB_FIRST ,Least significant bit first or most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TX_FIFO_CTRL,Transmitter FIFO Control Register"
|
|
bitfld.long 0x04 17. " FREEZE ,Freeze will not advance TX FIFO read pointer" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CLEAR ,Transmitter FIFO and transmitter shift register cleared" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO Status Register"
|
|
bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " SR_VALID ,Indicates whether the TX shift registers holds a valid data frame" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " USED ,Amount of entries in the transmitter FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
wgroup.long 0x240++0x03
|
|
line.long 0x00 "TX_FIFO_WR,Transmitter FIFO Write Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,16-bit data frame written into the transmitter FIFO"
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "RX_CTRL,Receiver Control Register"
|
|
bitfld.long 0x00 9. " MEDIAN ,Median filter" "0,Digital 3 taps median filter"
|
|
bitfld.long 0x00 8. " MSB_FIRST ,Least significant bit first or most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "RX_FIFO_CTRL,Receiver FIFO Control Register"
|
|
bitfld.long 0x04 17. " FREEZE ,Freeze will not advance TX FIFO read pointer" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CLEAR ,Transmitter FIFO and transmitter shift register cleared" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO Status Register"
|
|
bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " SR_VALID ,Indicates whether the RX shift registers holds a valid data frame" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " USED ,Amount od enties in the receiver FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "RX_MATCH,Slave Address And Mask Register"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " MASK ,Slave device address mask"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Slave device address"
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "RX_FIFO_RD,Receiver FIFO Read Register"
|
|
in
|
|
hgroup.long 0x344++0x03
|
|
hide.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO Read Register"
|
|
in
|
|
hgroup.long 0x400++0x03
|
|
hide.long 0x00 "EZ_DATA0,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x404++0x03
|
|
hide.long 0x00 "EZ_DATA1,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x408++0x03
|
|
hide.long 0x00 "EZ_DATA2,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x40C++0x03
|
|
hide.long 0x00 "EZ_DATA3,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "EZ_DATA4,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "EZ_DATA5,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "EZ_DATA6,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "EZ_DATA7,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x00 "EZ_DATA8,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x424++0x03
|
|
hide.long 0x00 "EZ_DATA9,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x428++0x03
|
|
hide.long 0x00 "EZ_DATA10,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x42C++0x03
|
|
hide.long 0x00 "EZ_DATA11,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x430++0x03
|
|
hide.long 0x00 "EZ_DATA12,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x434++0x03
|
|
hide.long 0x00 "EZ_DATA13,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x438++0x03
|
|
hide.long 0x00 "EZ_DATA14,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x43C++0x03
|
|
hide.long 0x00 "EZ_DATA15,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x440++0x03
|
|
hide.long 0x00 "EZ_DATA16,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x444++0x03
|
|
hide.long 0x00 "EZ_DATA17,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x448++0x03
|
|
hide.long 0x00 "EZ_DATA18,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x44C++0x03
|
|
hide.long 0x00 "EZ_DATA19,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x450++0x03
|
|
hide.long 0x00 "EZ_DATA20,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x454++0x03
|
|
hide.long 0x00 "EZ_DATA21,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x458++0x03
|
|
hide.long 0x00 "EZ_DATA22,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x45C++0x03
|
|
hide.long 0x00 "EZ_DATA23,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x460++0x03
|
|
hide.long 0x00 "EZ_DATA24,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x464++0x03
|
|
hide.long 0x00 "EZ_DATA25,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x468++0x03
|
|
hide.long 0x00 "EZ_DATA26,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x46C++0x03
|
|
hide.long 0x00 "EZ_DATA27,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x470++0x03
|
|
hide.long 0x00 "EZ_DATA28,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x474++0x03
|
|
hide.long 0x00 "EZ_DATA29,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x478++0x03
|
|
hide.long 0x00 "EZ_DATA30,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x47C++0x03
|
|
hide.long 0x00 "EZ_DATA31,Memory Buffer Registers"
|
|
in
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "INTR_CAUSE,Active Clock Interrupt Signal Register"
|
|
bitfld.long 0x00 5. " SPI_EC ,Externally clocked SPI interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 4. " I2C_EC ,Externally clocked I2C interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RX ,Receiver interrupt active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX ,Transmitter interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S ,Slave interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 0. " M ,Master interrupt active" "Inactive,Active"
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register"
|
|
eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt"
|
|
group.long 0xE88++0x03
|
|
line.long 0x00 "INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xE8C++0x03
|
|
line.long 0x00 "INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xEC0++0x03
|
|
line.long 0x00 "INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register"
|
|
eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt"
|
|
group.long 0xEC8++0x03
|
|
line.long 0x00 "INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xECC++0x03
|
|
line.long 0x00 "INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF00++0x0B
|
|
line.long 0x00 "INTR_M,Master Interrupt Request Register"
|
|
eventfld.long 0x00 9. " SPI_DONE ,SPI master transfer done event" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " I2C_BUS_ERROR ,I2C master bus error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " I2C_STOP ,I2C master STOP" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " I2C_ACK ,I2C master acknowledgement" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " I2C_NACK ,I2C master negative acknowledgement" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " I2C_ARB_LOST ,I2C master lost arbitration" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_M_SET,Master Interrupt Set Request Register"
|
|
bitfld.long 0x04 9. " SPI_DONE ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " I2C_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I2C_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " I2C_ACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I2C_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I2C_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_M_MASK,Master Interrupt Mask Register"
|
|
bitfld.long 0x08 9. " SPI_DONE ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " I2C_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " I2C_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " I2C_ACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " I2C_NACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " I2C_ARB_LOST ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xF0C++0x03
|
|
line.long 0x00 "INTR_M_MASKED,Master Interrupt Masked Request Register"
|
|
bitfld.long 0x00 9. " SPI_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF40++0x0B
|
|
line.long 0x00 "INTR_S,Slave Interrupt Request Register"
|
|
eventfld.long 0x00 11. " SPI_BUS_ERROR ,SPI slave deselected at an unexpected time in the SPI transfer" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " SPI_EZ_STOP ,SPI slave deselected after any EZ SPI transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,SPI slave deselected after a write EZ SPI transfer occurred" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " I2C_BUS_ERROR ,I2C slave bus error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " I2C_GENERAL ,I2C slave general call address received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " I2C_ADDR_MATCH ,I2C slave matching address received" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " I2C_START ,I2C slave START received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " I2C_STOP ,I2C STOP event for I2C transfer intended for this slave" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " I2C_WRITE_STOP ,I2C STOP event for I2C write transfer intended for this slave" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " I2C_ACK ,I2C slave acknowledgement received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " I2C_NACK ,I2C slave negative acknowledgement received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " I2C_ARB_LOST ,I2C slave lost arbitration" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_S_SET,Slave Interrupt Set Request Register"
|
|
bitfld.long 0x04 11. " SPI_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " SPI_EZ_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " SPI_EZ_WRITE_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " I2C_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " I2C_GENERAL ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " I2C_ADDR_MATCH ,Set corresponding bit in interrupt request registe" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I2C_START ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I2C_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " I2C_WRITE_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " I2C_ACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I2C_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I2C_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_S_MASK,Slave Interrupt Mask Register"
|
|
bitfld.long 0x08 11. " SPI_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " SPI_EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " SPI_EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 8. " I2C_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " I2C_GENERAL ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " I2C_ADDR_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 5. " I2C_START ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " I2C_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " I2C_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " I2C_ACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " I2C_NACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " I2C_ARB_LOST ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xF4C++0x03
|
|
line.long 0x00 "INTR_S_MASKED,Slave Interrupt Masked Request Register"
|
|
bitfld.long 0x00 11. " SPI_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " SPI_EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " I2C_GENERAL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " I2C_ADDR_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I2C_START ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " I2C_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF80++0x0B
|
|
line.long 0x00 "INTR_TX,Transmitter Interrupt Request Register"
|
|
eventfld.long 0x00 10. " UART_ARB_LOST ,UART lost arbitration" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " UART_DONE ,UART transmitter done event" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " UART_NACK ,UART transmitter received a negative acknowledgement in smartcard mode" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " BLOCKED ,AHB-Lite write transfer can not get access to the EZ memory" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty TX FIFO" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full TX FIFO" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " EMPTY ,TX FIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " NOT_FULL ,TX FIFO is not full" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " TRIGGER ,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_TX_SET,Transmitter Interrupt Set Request Register"
|
|
bitfld.long 0x04 10. " UART_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " UART_DONE ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " UART_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " BLOCKED ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " UNDERFLOW ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " OVERFLOW ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " EMPTY ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " NOT_FULL ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " TIGGER ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_TX_MASK,Transmitter Interrupt Mask Register"
|
|
bitfld.long 0x08 10. " UART_ARB_LOST ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " UART_DONE ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " UART_NACK ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " BLOCKED ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " UNDERFLOW ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " OVERFLOW ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 4. " EMPTY ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " NOT_FULL ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TRIGGER ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
rgroup.long 0xF8C++0x03
|
|
line.long 0x00 "INTR_TX_MASKED,Transmitter Interrupt Masked Request Register"
|
|
bitfld.long 0x00 10. " UART_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " UART_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " UART_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " NOT_FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xFC0++0x0B
|
|
line.long 0x00 "INTR_RX,Receiver Interrupt Request Register"
|
|
eventfld.long 0x00 11. " BREAK_DETECT ,Break detection successful" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " BAUD_DETECT ,LIN baudrate detection is completed" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " PARITY_ERROR ,Parity error in received data frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " FRAME_ERROR ,Frame error in received data frame" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " BLOCKED ,AHB-Lite read transfer can not get access to the EZ memory" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty RX FIFO" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full RX FIFO" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " FULL ,RX FIFO is full" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " NOT_EMPTY ,RX FIFO is not empty" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TRIGGER ,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_RX_SET,Receiver Interrupt Set Request Register"
|
|
bitfld.long 0x04 11. " BREAK_DETECT ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " BAUD_DETECT ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " PARITY_ERROR ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " FRAME_ERROR ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " BLOCKED ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " UNDERFLOW ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OVERFLOW ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " FULL ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " NOT_EMPTY ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRIGGER ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_RX_MASK,Receiver Interrupt Mask Register"
|
|
bitfld.long 0x08 11. " BREAK_DETECT ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " BAUD_DETECT ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " PARITY_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 8. " FRAME_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " BLOCKED ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " UNDERFLOW ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OVERFLOW ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " FULL ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " NOT_EMPTY ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TRIGGER ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "INTR_RX_MASKED,Receiver Interrupt Masked Request Register"
|
|
bitfld.long 0x00 11. " BREAK_DETECT ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " BAUD_DETECT ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " PARITY_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FRAME_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " NOT_EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif cpuis("CY8C4??7*-BL*")
|
|
tree "SFLASH (Supervisory Flash)"
|
|
base ad:0x0FFFF000
|
|
width 32.
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW0,Per Page Write Protection"
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW1,Per Page Write Protection"
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW2,Per Page Write Protection"
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW3,Per Page Write Protection"
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW4,Per Page Write Protection"
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW5,Per Page Write Protection"
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW6,Per Page Write Protection"
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW7,Per Page Write Protection"
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW8,Per Page Write Protection"
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW9,Per Page Write Protection"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW10,Per Page Write Protection"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW11,Per Page Write Protection"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW12,Per Page Write Protection"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW13,Per Page Write Protection"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW14,Per Page Write Protection"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW15,Per Page Write Protection"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW16,Per Page Write Protection"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW17,Per Page Write Protection"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW18,Per Page Write Protection"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW19,Per Page Write Protection"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW20,Per Page Write Protection"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW21,Per Page Write Protection"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW22,Per Page Write Protection"
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW23,Per Page Write Protection"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW24,Per Page Write Protection"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW25,Per Page Write Protection"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW26,Per Page Write Protection"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW27,Per Page Write Protection"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW28,Per Page Write Protection"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW29,Per Page Write Protection"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW30,Per Page Write Protection"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW31,Per Page Write Protection"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW32,Per Page Write Protection"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW33,Per Page Write Protection"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW34,Per Page Write Protection"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW35,Per Page Write Protection"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW36,Per Page Write Protection"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW37,Per Page Write Protection"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW38,Per Page Write Protection"
|
|
group.byte 0x27++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW39,Per Page Write Protection"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW40,Per Page Write Protection"
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW41,Per Page Write Protection"
|
|
group.byte 0x2A++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW42,Per Page Write Protection"
|
|
group.byte 0x2B++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW43,Per Page Write Protection"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW44,Per Page Write Protection"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW45,Per Page Write Protection"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW46,Per Page Write Protection"
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW47,Per Page Write Protection"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW48,Per Page Write Protection"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW49,Per Page Write Protection"
|
|
group.byte 0x32++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW50,Per Page Write Protection"
|
|
group.byte 0x33++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW51,Per Page Write Protection"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW52,Per Page Write Protection"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW53,Per Page Write Protection"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW54,Per Page Write Protection"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW55,Per Page Write Protection"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW56,Per Page Write Protection"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW57,Per Page Write Protection"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW58,Per Page Write Protection"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW59,Per Page Write Protection"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW60,Per Page Write Protection"
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW61,Per Page Write Protection"
|
|
group.byte 0x3E++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW62,Per Page Write Protection"
|
|
group.byte 0x3F++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW63,Per Page Write Protection"
|
|
group.byte 0x7F++0x00
|
|
line.byte 0x00 "PROT_PROTECTION,Protection Level"
|
|
bitfld.byte 0x00 0.--1. " PROT_LEVEL ,Current protection mode" "OPEN,VIRGIN,PROTECTED,KILL"
|
|
tree "8b Addr/Value pair Section Registers"
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B0,8b Addr/Value Pair Section"
|
|
group.byte 0x81++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B1,8b Addr/Value Pair Section"
|
|
group.byte 0x82++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B2,8b Addr/Value Pair Section"
|
|
group.byte 0x83++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B3,8b Addr/Value Pair Section"
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B4,8b Addr/Value Pair Section"
|
|
group.byte 0x85++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B5,8b Addr/Value Pair Section"
|
|
group.byte 0x86++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B6,8b Addr/Value Pair Section"
|
|
group.byte 0x87++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B7,8b Addr/Value Pair Section"
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B8,8b Addr/Value Pair Section"
|
|
group.byte 0x89++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B9,8b Addr/Value Pair Section"
|
|
group.byte 0x8A++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B10,8b Addr/Value Pair Section"
|
|
group.byte 0x8B++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B11,8b Addr/Value Pair Section"
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B12,8b Addr/Value Pair Section"
|
|
group.byte 0x8D++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B13,8b Addr/Value Pair Section"
|
|
group.byte 0x8E++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B14,8b Addr/Value Pair Section"
|
|
group.byte 0x8F++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B15,8b Addr/Value Pair Section"
|
|
group.byte 0x90++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B16,8b Addr/Value Pair Section"
|
|
group.byte 0x91++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B17,8b Addr/Value Pair Section"
|
|
group.byte 0x92++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B18,8b Addr/Value Pair Section"
|
|
group.byte 0x93++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B19,8b Addr/Value Pair Section"
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B20,8b Addr/Value Pair Section"
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B21,8b Addr/Value Pair Section"
|
|
group.byte 0x96++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B22,8b Addr/Value Pair Section"
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B23,8b Addr/Value Pair Section"
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B24,8b Addr/Value Pair Section"
|
|
group.byte 0x99++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B25,8b Addr/Value Pair Section"
|
|
group.byte 0x9A++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B26,8b Addr/Value Pair Section"
|
|
group.byte 0x9B++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B27,8b Addr/Value Pair Section"
|
|
group.byte 0x9C++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B28,8b Addr/Value Pair Section"
|
|
group.byte 0x9D++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B29,8b Addr/Value Pair Section"
|
|
group.byte 0x9E++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B30,8b Addr/Value Pair Section"
|
|
group.byte 0x9F++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B31,8b Addr/Value Pair Section"
|
|
group.byte 0xA0++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B32,8b Addr/Value Pair Section"
|
|
group.byte 0xA1++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B33,8b Addr/Value Pair Section"
|
|
group.byte 0xA2++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B34,8b Addr/Value Pair Section"
|
|
group.byte 0xA3++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B35,8b Addr/Value Pair Section"
|
|
group.byte 0xA4++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B36,8b Addr/Value Pair Section"
|
|
group.byte 0xA5++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B37,8b Addr/Value Pair Section"
|
|
group.byte 0xA6++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B38,8b Addr/Value Pair Section"
|
|
group.byte 0xA7++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B39,8b Addr/Value Pair Section"
|
|
group.byte 0xA8++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B40,8b Addr/Value Pair Section"
|
|
group.byte 0xA9++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B41,8b Addr/Value Pair Section"
|
|
group.byte 0xAA++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B42,8b Addr/Value Pair Section"
|
|
group.byte 0xAB++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B43,8b Addr/Value Pair Section"
|
|
group.byte 0xAC++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B44,8b Addr/Value Pair Section"
|
|
group.byte 0xAD++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B45,8b Addr/Value Pair Section"
|
|
group.byte 0xAE++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B46,8b Addr/Value Pair Section"
|
|
group.byte 0xAF++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B47,8b Addr/Value Pair Section"
|
|
group.byte 0xB0++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B48,8b Addr/Value Pair Section"
|
|
group.byte 0xB1++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B49,8b Addr/Value Pair Section"
|
|
group.byte 0xB2++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B50,8b Addr/Value Pair Section"
|
|
group.byte 0xB3++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B51,8b Addr/Value Pair Section"
|
|
group.byte 0xB4++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B52,8b Addr/Value Pair Section"
|
|
group.byte 0xB5++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B53,8b Addr/Value Pair Section"
|
|
group.byte 0xB6++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B54,8b Addr/Value Pair Section"
|
|
group.byte 0xB7++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B55,8b Addr/Value Pair Section"
|
|
group.byte 0xB8++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B56,8b Addr/Value Pair Section"
|
|
group.byte 0xB9++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B57,8b Addr/Value Pair Section"
|
|
group.byte 0xBA++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B58,8b Addr/Value Pair Section"
|
|
group.byte 0xBB++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B59,8b Addr/Value Pair Section"
|
|
group.byte 0xBC++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B60,8b Addr/Value Pair Section"
|
|
group.byte 0xBD++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B61,8b Addr/Value Pair Section"
|
|
group.byte 0xBE++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B62,8b Addr/Value Pair Section"
|
|
group.byte 0xBF++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B63,8b Addr/Value Pair Section"
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B64,8b Addr/Value Pair Section"
|
|
group.byte 0xC1++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B65,8b Addr/Value Pair Section"
|
|
group.byte 0xC2++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B66,8b Addr/Value Pair Section"
|
|
group.byte 0xC3++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B67,8b Addr/Value Pair Section"
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B68,8b Addr/Value Pair Section"
|
|
group.byte 0xC5++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B69,8b Addr/Value Pair Section"
|
|
group.byte 0xC6++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B70,8b Addr/Value Pair Section"
|
|
group.byte 0xC7++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B71,8b Addr/Value Pair Section"
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B72,8b Addr/Value Pair Section"
|
|
group.byte 0xC9++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B73,8b Addr/Value Pair Section"
|
|
group.byte 0xCA++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B74,8b Addr/Value Pair Section"
|
|
group.byte 0xCB++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B75,8b Addr/Value Pair Section"
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B76,8b Addr/Value Pair Section"
|
|
group.byte 0xCD++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B77,8b Addr/Value Pair Section"
|
|
group.byte 0xCE++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B78,8b Addr/Value Pair Section"
|
|
group.byte 0xCF++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B79,8b Addr/Value Pair Section"
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B80,8b Addr/Value Pair Section"
|
|
group.byte 0xD1++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B81,8b Addr/Value Pair Section"
|
|
group.byte 0xD2++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B82,8b Addr/Value Pair Section"
|
|
group.byte 0xD3++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B83,8b Addr/Value Pair Section"
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B84,8b Addr/Value Pair Section"
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B85,8b Addr/Value Pair Section"
|
|
group.byte 0xD6++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B86,8b Addr/Value Pair Section"
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B87,8b Addr/Value Pair Section"
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B88,8b Addr/Value Pair Section"
|
|
group.byte 0xD9++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B89,8b Addr/Value Pair Section"
|
|
group.byte 0xDA++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B90,8b Addr/Value Pair Section"
|
|
group.byte 0xDB++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B91,8b Addr/Value Pair Section"
|
|
group.byte 0xDC++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B92,8b Addr/Value Pair Section"
|
|
group.byte 0xDD++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B93,8b Addr/Value Pair Section"
|
|
group.byte 0xDE++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B94,8b Addr/Value Pair Section"
|
|
group.byte 0xDF++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B95,8b Addr/Value Pair Section"
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B96,8b Addr/Value Pair Section"
|
|
group.byte 0xE1++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B97,8b Addr/Value Pair Section"
|
|
group.byte 0xE2++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B98,8b Addr/Value Pair Section"
|
|
group.byte 0xE3++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B99,8b Addr/Value Pair Section"
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B100,8b Addr/Value Pair Section"
|
|
group.byte 0xE5++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B101,8b Addr/Value Pair Section"
|
|
group.byte 0xE6++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B102,8b Addr/Value Pair Section"
|
|
group.byte 0xE7++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B103,8b Addr/Value Pair Section"
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B104,8b Addr/Value Pair Section"
|
|
group.byte 0xE9++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B105,8b Addr/Value Pair Section"
|
|
group.byte 0xEA++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B106,8b Addr/Value Pair Section"
|
|
group.byte 0xEB++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B107,8b Addr/Value Pair Section"
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B108,8b Addr/Value Pair Section"
|
|
group.byte 0xED++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B109,8b Addr/Value Pair Section"
|
|
group.byte 0xEE++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B110,8b Addr/Value Pair Section"
|
|
group.byte 0xEF++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B111,8b Addr/Value Pair Section"
|
|
group.byte 0xF0++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B112,8b Addr/Value Pair Section"
|
|
group.byte 0xF1++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B113,8b Addr/Value Pair Section"
|
|
group.byte 0xF2++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B114,8b Addr/Value Pair Section"
|
|
group.byte 0xF3++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B115,8b Addr/Value Pair Section"
|
|
group.byte 0xF4++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B116,8b Addr/Value Pair Section"
|
|
group.byte 0xF5++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B117,8b Addr/Value Pair Section"
|
|
group.byte 0xF6++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B118,8b Addr/Value Pair Section"
|
|
group.byte 0xF7++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B119,8b Addr/Value Pair Section"
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B120,8b Addr/Value Pair Section"
|
|
group.byte 0xF9++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B121,8b Addr/Value Pair Section"
|
|
group.byte 0xFA++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B122,8b Addr/Value Pair Section"
|
|
group.byte 0xFB++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B123,8b Addr/Value Pair Section"
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B124,8b Addr/Value Pair Section"
|
|
group.byte 0xFD++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B125,8b Addr/Value Pair Section"
|
|
group.byte 0xFE++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B126,8b Addr/Value Pair Section"
|
|
group.byte 0xFF++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B127,8b Addr/Value Pair Section"
|
|
tree.end
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "AV_PAIRS_32B0,32b Addr/Value Pair Section"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "AV_PAIRS_32B1,32b Addr/Value Pair Section"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "AV_PAIRS_32B2,32b Addr/Value Pair Section"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "AV_PAIRS_32B3,32b Addr/Value Pair Section"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "AV_PAIRS_32B4,32b Addr/Value Pair Section"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "AV_PAIRS_32B5,32b Addr/Value Pair Section"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "AV_PAIRS_32B6,32b Addr/Value Pair Section"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "AV_PAIRS_32B7,32b Addr/Value Pair Section"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "AV_PAIRS_32B8,32b Addr/Value Pair Section"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "AV_PAIRS_32B9,32b Addr/Value Pair Section"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "AV_PAIRS_32B10,32b Addr/Value Pair Section"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "AV_PAIRS_32B11,32b Addr/Value Pair Section"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "AV_PAIRS_32B12,32b Addr/Value Pair Section"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "AV_PAIRS_32B13,32b Addr/Value Pair Section"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "AV_PAIRS_32B14,32b Addr/Value Pair Section"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "AV_PAIRS_32B15,32b Addr/Value Pair Section"
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "CPUSS_WOUNDING,CPUSS Wounding Register"
|
|
line.long 0x04 "SILICON_ID,Silicon ID"
|
|
hexmask.long.word 0x04 0.--15. 1. " ID ,Silicon ID"
|
|
group.word 0x148++0x0B
|
|
line.word 0x00 "CPUSS_PRIV_RAM,RAM Privileged Limit"
|
|
hexmask.word 0x00 0.--8. 1. " RAM_PROT_LIMIT ,Limit where the privileged are of SRAM starts in increments of 256 bytes"
|
|
line.word 0x02 "CPUSS_PRIV_ROM_BROM,Boot ROM Privileged Limit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " BROM_PROT_LIMIT ,Limit where the privileged area of the boot ROM partition starts in increments of 256 bytes"
|
|
line.word 0x04 "CPUSS_PRIV_FLASH,Flash Privileged Limit"
|
|
hexmask.word 0x04 0.--10. 1. " FLASH_PROT_LIMIT ,Limit where the privileged area of flash starts in increments of 256 bytes"
|
|
line.word 0x06 "CPUSS_PRIV_ROM_SROM,System ROM Privileged Limit"
|
|
hexmask.word 0x06 0.--9. 1. " SROM_PROT_LIMIT ,Limit where the privileged area of system ROM partition starts in increments of 256 bytes"
|
|
line.word 0x08 "HIB_KEY_DELAY,Hibernate Wakeup Value For PWR_KEY_DELAY"
|
|
hexmask.word 0x08 0.--9. 1. " WAKEUP_HOLDOFF ,Delay to wait for references to settle on wakeup from hibernate/DeepSleep"
|
|
line.word 0x0A "DPSLP_KEY_DELAY,DeepSleep Wakeup Value For PWR_KEY_DELAY"
|
|
hexmask.word 0x0A 0.--9. 1. " WAKEUP_HOLDOFF ,Delay to wait for references to settle on wakeup from hibernate/DeepSleep"
|
|
group.byte 0x154++0x00
|
|
line.byte 0x00 "SWD_CONFIG,SWD Pinout Selector"
|
|
bitfld.byte 0x00 0. " SWD_SELECT ,SWD select" "Primary SWD location,Alternate SWD location"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.byte 0x155++0x03
|
|
line.byte 0x00 "INITIAL_SPCIF_TRIM_M1_DAC0,FLASH IDAC Trim Used During Boot"
|
|
bitfld.byte 0x00 5.--7. " SLOPE ,Slope" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--4. " IDAC ,Idac" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0x158++0x07
|
|
line.long 0x00 "SWD_LISTEN,Listen Window Length"
|
|
line.long 0x04 "FLASH_START,Flash Image Start Address"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.byte 0x160++0x03
|
|
line.byte 0x00 "CSD_TRIM1_HVIDAC,CSD Trim Data For HVIDAC Operation"
|
|
line.byte 0x01 "CSD_TRIM2_HVIDAC,CSD Trim Data For HVIDAC Operation"
|
|
line.byte 0x02 "CSD_TRIM1_CSD,CSD Trim Data For (Normal) CSD Operation"
|
|
line.byte 0x03 "CSD_TRIM2_CSD,CSD Trim Data For (Normal) CSD Operation"
|
|
else
|
|
group.byte 0x160++0x01
|
|
line.byte 0x00 "CSDV2_CSD0_ADC_TRIM1,CSDv2 CSD0 ADC Trim 2"
|
|
bitfld.byte 0x00 5.--7. " ADCTRIM_2P4V_2_0 ,1.2V trim data - low order 3 bits of 5 bit field" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--4. " ADCTRIM_1P2V ,1.2V trim data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "CSDV2_CSD0_ADC_TRIM2,CSDv2 CSD0 ADC Trim 1"
|
|
bitfld.byte 0x01 5.--6. " ADCTRIM_2P4V_5_4 ,1.2V trim data - high order 2 bits of 5 bit field" "0,1,2,3"
|
|
bitfld.byte 0x01 0.--4. " ADCTRIM_3P84V_2_0 ,1.2V trim data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word 0x164++0x03
|
|
line.word 0x00 "SAR_TEMP_MULTIPLIER,SAR Temperature Sensor Multiplication Factor"
|
|
line.word 0x02 "SAR_TEMP_OFFSET,SAR Temperature Sensor Offset"
|
|
group.byte 0x169++0x00
|
|
line.byte 0x00 "SKIP_CHECKSUM,Checksum Skip Option Register"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
group.byte 0x16A++0x05
|
|
line.byte 0x00 "INITIAL_PWR_BG_TRIM1,SRSSLT BG Vref Trim Used During Boot"
|
|
bitfld.byte 0x00 0.--5. " REF_ITRIM ,Vref trim used during boot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "INITIAL_PWR_BG_TRIM1_INV,SRSSLT BG Vref Trim Used During Boot"
|
|
bitfld.byte 0x01 0.--5. " REF_ITRIM ,Vref trim used during boot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "INITIAL_PWR_BG_TRIM2,SRSSLT BG Iref Trim Used During Boot"
|
|
bitfld.byte 0x02 0.--5. " REF_ITRIM ,Vref trim used during boot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x03 "INITIAL_PWR_BG_TRIM2_INV,SRSSLT BG Iref Trim Used During Boot"
|
|
bitfld.byte 0x03 0.--5. " REF_ITRIM ,Vreg trim used during boot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x04 "INITIAL_SPCIF_TRIM_M0_DAC0,FLASH IDAC Trim Used During Boot"
|
|
bitfld.byte 0x04 5.--7. " SLOPE ,Slope" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x04 0.--4. " IDAC ,IDAC trim used during boot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x05 "INITIAL_SPCIF_TRIM_M0_DAC0_INV,FLASH IDAC Trim Used During Boot"
|
|
bitfld.byte 0x05 5.--7. " SLOPE ,Slope" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x05 0.--4. " IDAC ,IDAC trim used during boot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.byte 0x170++0x0F
|
|
line.byte 0x00 "PROT_VIRGINKEY0,Virgin Protection Mode Key"
|
|
line.byte 0x01 "PROT_VIRGINKEY1,Virgin Protection Mode Key"
|
|
line.byte 0x02 "PROT_VIRGINKEY2,Virgin Protection Mode Key"
|
|
line.byte 0x03 "PROT_VIRGINKEY3,Virgin Protection Mode Key"
|
|
line.byte 0x04 "PROT_VIRGINKEY4,Virgin Protection Mode Key"
|
|
line.byte 0x05 "PROT_VIRGINKEY5,Virgin Protection Mode Key"
|
|
line.byte 0x06 "PROT_VIRGINKEY6,Virgin Protection Mode Key"
|
|
line.byte 0x07 "PROT_VIRGINKEY7,Virgin Protection Mode Key"
|
|
line.byte 0x08 "DIE_LOT0,Lot Number"
|
|
line.byte 0x09 "DIE_LOT1,Lot Number"
|
|
line.byte 0x0A "DIE_LOT2,Lot Number"
|
|
line.byte 0x0B "DIE_WAFER,Wafer Number"
|
|
line.byte 0x0C "DIE_X,X Position On Wafer"
|
|
line.byte 0x0D "DIE_Y,Y Position On Wafer"
|
|
line.byte 0x0E "DIE_SORT,Sort1/2/3 Pass/fail Bin"
|
|
bitfld.byte 0x0E 5. " ENG_PASS ,ENG pass bin" "Failed,Passed"
|
|
bitfld.byte 0x0E 4. " CHI_PASS ,CHI pass bin" "Failed,Passed"
|
|
bitfld.byte 0x0E 3. " CRI_PASS ,CRI pass bin" "Failed,Passed"
|
|
bitfld.byte 0x0E 2. " S3_PASS ,SORT3 pass bin" "Failed,Passed"
|
|
textline " "
|
|
bitfld.byte 0x0E 1. " S2_PASS ,SORT2 pass bin" "Failed,Passed"
|
|
bitfld.byte 0x0E 0. " S1_PASS ,SORT1 pass bin" "Failed,Passed"
|
|
line.byte 0x0F "DIE_MINOR,Minor Revision Number"
|
|
group.byte 0x180++0x00
|
|
line.byte 0x00 "PE_TE_DATA0,PE/TE Data"
|
|
group.byte 0x181++0x00
|
|
line.byte 0x00 "PE_TE_DATA1,PE/TE Data"
|
|
group.byte 0x182++0x00
|
|
line.byte 0x00 "PE_TE_DATA2,PE/TE Data"
|
|
group.byte 0x183++0x00
|
|
line.byte 0x00 "PE_TE_DATA3,PE/TE Data"
|
|
group.byte 0x184++0x00
|
|
line.byte 0x00 "PE_TE_DATA4,PE/TE Data"
|
|
group.byte 0x185++0x00
|
|
line.byte 0x00 "PE_TE_DATA5,PE/TE Data"
|
|
group.byte 0x186++0x00
|
|
line.byte 0x00 "PE_TE_DATA6,PE/TE Data"
|
|
group.byte 0x187++0x00
|
|
line.byte 0x00 "PE_TE_DATA7,PE/TE Data"
|
|
group.byte 0x188++0x00
|
|
line.byte 0x00 "PE_TE_DATA8,PE/TE Data"
|
|
group.byte 0x189++0x00
|
|
line.byte 0x00 "PE_TE_DATA9,PE/TE Data"
|
|
group.byte 0x18A++0x00
|
|
line.byte 0x00 "PE_TE_DATA10,PE/TE Data"
|
|
group.byte 0x18B++0x00
|
|
line.byte 0x00 "PE_TE_DATA11,PE/TE Data"
|
|
group.byte 0x18C++0x00
|
|
line.byte 0x00 "PE_TE_DATA12,PE/TE Data"
|
|
group.byte 0x18D++0x00
|
|
line.byte 0x00 "PE_TE_DATA13,PE/TE Data"
|
|
group.byte 0x18E++0x00
|
|
line.byte 0x00 "PE_TE_DATA14,PE/TE Data"
|
|
group.byte 0x18F++0x00
|
|
line.byte 0x00 "PE_TE_DATA15,PE/TE Data"
|
|
group.byte 0x190++0x00
|
|
line.byte 0x00 "PE_TE_DATA16,PE/TE Data"
|
|
group.byte 0x191++0x00
|
|
line.byte 0x00 "PE_TE_DATA17,PE/TE Data"
|
|
group.byte 0x192++0x00
|
|
line.byte 0x00 "PE_TE_DATA18,PE/TE Data"
|
|
group.byte 0x193++0x00
|
|
line.byte 0x00 "PE_TE_DATA19,PE/TE Data"
|
|
group.byte 0x194++0x00
|
|
line.byte 0x00 "PE_TE_DATA20,PE/TE Data"
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "PE_TE_DATA21,PE/TE Data"
|
|
group.byte 0x196++0x00
|
|
line.byte 0x00 "PE_TE_DATA22,PE/TE Data"
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "PE_TE_DATA23,PE/TE Data"
|
|
group.byte 0x198++0x00
|
|
line.byte 0x00 "PE_TE_DATA24,PE/TE Data"
|
|
group.byte 0x199++0x00
|
|
line.byte 0x00 "PE_TE_DATA25,PE/TE Data"
|
|
group.byte 0x19A++0x00
|
|
line.byte 0x00 "PE_TE_DATA26,PE/TE Data"
|
|
group.byte 0x19B++0x00
|
|
line.byte 0x00 "PE_TE_DATA27,PE/TE Data"
|
|
group.byte 0x19C++0x00
|
|
line.byte 0x00 "PE_TE_DATA28,PE/TE Data"
|
|
group.byte 0x19D++0x00
|
|
line.byte 0x00 "PE_TE_DATA29,PE/TE Data"
|
|
group.byte 0x19E++0x00
|
|
line.byte 0x00 "PE_TE_DATA30,PE/TE Data"
|
|
group.byte 0x19F++0x00
|
|
line.byte 0x00 "PE_TE_DATA31,PE/TE Data"
|
|
group.long 0x1A0++0x1B
|
|
line.long 0x00 "PP,Preprogram Settings"
|
|
bitfld.long 0x00 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x04 "E,Erase Settings"
|
|
bitfld.long 0x04 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x08 "P,Program Settings"
|
|
bitfld.long 0x08 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x0C "EA_E,Erase All - Erase Settings"
|
|
bitfld.long 0x0C 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x10 "EA_P,Erase All - Program Settings"
|
|
bitfld.long 0x10 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x14 "ES_E,Erase Sector - Erase Settings"
|
|
bitfld.long 0x14 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x18 "ES_P_EO,Erase Sector - Program EO Settings"
|
|
bitfld.long 0x18 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.byte 0x1BC++0x01
|
|
line.byte 0x00 "E_VCTAT,Bandgap Trim Register"
|
|
bitfld.byte 0x00 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "P_VCTAT,Bandgap Trim Register"
|
|
bitfld.byte 0x01 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3"
|
|
bitfld.byte 0x01 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1C0++0x02
|
|
line.byte 0x00 "IMO_MAXF0,Max Frequency For Trim Pair 0"
|
|
bitfld.byte 0x00 0.--5. " MAXFREQ ,Max frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "IMO_ABS0,Value For PWR_BG_TRIM4 0"
|
|
bitfld.byte 0x01 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "IMO_TMPCO0,Value For PWR_BG_TRIM5 0"
|
|
bitfld.byte 0x02 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x1C1++0x02
|
|
line.byte 0x00 "IMO_MAXF1,Max Frequency For Trim Pair 1"
|
|
bitfld.byte 0x00 0.--5. " MAXFREQ ,Max frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "IMO_ABS1,Value For PWR_BG_TRIM4 1"
|
|
bitfld.byte 0x01 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "IMO_TMPCO1,Value For PWR_BG_TRIM5 1"
|
|
bitfld.byte 0x02 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x1C2++0x02
|
|
line.byte 0x00 "IMO_MAXF2,Max Frequency For Trim Pair 2"
|
|
bitfld.byte 0x00 0.--5. " MAXFREQ ,Max frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "IMO_ABS2,Value For PWR_BG_TRIM4 2"
|
|
bitfld.byte 0x01 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "IMO_TMPCO2,Value For PWR_BG_TRIM5 2"
|
|
bitfld.byte 0x02 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x1C3++0x02
|
|
line.byte 0x00 "IMO_MAXF3,Max Frequency For Trim Pair 3"
|
|
bitfld.byte 0x00 0.--5. " MAXFREQ ,Max frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "IMO_ABS3,Value For PWR_BG_TRIM4 3"
|
|
bitfld.byte 0x01 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "IMO_TMPCO3,Value For PWR_BG_TRIM5 3"
|
|
bitfld.byte 0x02 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x1CC++0x01
|
|
line.byte 0x00 "IMO_ABS4,Value For PWR_BG_TRIM4"
|
|
bitfld.byte 0x00 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "IMO_TMPCO4,Value For PWR_BG_TRIM5"
|
|
bitfld.byte 0x01 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x1D0++0x00
|
|
line.byte 0x00 "IMO_TRIM0,IMO Trim Register 0"
|
|
group.byte 0x1D1++0x00
|
|
line.byte 0x00 "IMO_TRIM1,IMO Trim Register 1"
|
|
group.byte 0x1D2++0x00
|
|
line.byte 0x00 "IMO_TRIM2,IMO Trim Register 2"
|
|
group.byte 0x1D3++0x00
|
|
line.byte 0x00 "IMO_TRIM3,IMO Trim Register 3"
|
|
group.byte 0x1D4++0x00
|
|
line.byte 0x00 "IMO_TRIM4,IMO Trim Register 4"
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "IMO_TRIM5,IMO Trim Register 5"
|
|
group.byte 0x1D6++0x00
|
|
line.byte 0x00 "IMO_TRIM6,IMO Trim Register 6"
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "IMO_TRIM7,IMO Trim Register 7"
|
|
group.byte 0x1D8++0x00
|
|
line.byte 0x00 "IMO_TRIM8,IMO Trim Register 8"
|
|
group.byte 0x1D9++0x00
|
|
line.byte 0x00 "IMO_TRIM9,IMO Trim Register 9"
|
|
group.byte 0x1DA++0x00
|
|
line.byte 0x00 "IMO_TRIM10,IMO Trim Register 10"
|
|
group.byte 0x1DB++0x00
|
|
line.byte 0x00 "IMO_TRIM11,IMO Trim Register 11"
|
|
group.byte 0x1DC++0x00
|
|
line.byte 0x00 "IMO_TRIM12,IMO Trim Register 12"
|
|
group.byte 0x1DD++0x00
|
|
line.byte 0x00 "IMO_TRIM13,IMO Trim Register 13"
|
|
group.byte 0x1DE++0x00
|
|
line.byte 0x00 "IMO_TRIM14,IMO Trim Register 14"
|
|
group.byte 0x1DF++0x00
|
|
line.byte 0x00 "IMO_TRIM15,IMO Trim Register 15"
|
|
group.byte 0x1E0++0x00
|
|
line.byte 0x00 "IMO_TRIM16,IMO Trim Register 16"
|
|
group.byte 0x1E1++0x00
|
|
line.byte 0x00 "IMO_TRIM17,IMO Trim Register 17"
|
|
group.byte 0x1E2++0x00
|
|
line.byte 0x00 "IMO_TRIM18,IMO Trim Register 18"
|
|
group.byte 0x1E3++0x00
|
|
line.byte 0x00 "IMO_TRIM19,IMO Trim Register 19"
|
|
group.byte 0x1E4++0x00
|
|
line.byte 0x00 "IMO_TRIM20,IMO Trim Register 20"
|
|
group.byte 0x1E5++0x00
|
|
line.byte 0x00 "IMO_TRIM21,IMO Trim Register 21"
|
|
group.byte 0x1E6++0x00
|
|
line.byte 0x00 "IMO_TRIM22,IMO Trim Register 22"
|
|
group.byte 0x1E7++0x00
|
|
line.byte 0x00 "IMO_TRIM23,IMO Trim Register 23"
|
|
group.byte 0x1E8++0x00
|
|
line.byte 0x00 "IMO_TRIM24,IMO Trim Register 24"
|
|
group.byte 0x1E9++0x00
|
|
line.byte 0x00 "IMO_TRIM25,IMO Trim Register 25"
|
|
group.byte 0x1EA++0x00
|
|
line.byte 0x00 "IMO_TRIM26,IMO Trim Register 26"
|
|
group.byte 0x1EB++0x00
|
|
line.byte 0x00 "IMO_TRIM27,IMO Trim Register 27"
|
|
group.byte 0x1EC++0x00
|
|
line.byte 0x00 "IMO_TRIM28,IMO Trim Register 28"
|
|
group.byte 0x1ED++0x00
|
|
line.byte 0x00 "IMO_TRIM29,IMO Trim Register 29"
|
|
group.byte 0x1EE++0x00
|
|
line.byte 0x00 "IMO_TRIM30,IMO Trim Register 30"
|
|
group.byte 0x1EF++0x00
|
|
line.byte 0x00 "IMO_TRIM31,IMO Trim Register 31"
|
|
group.byte 0x1F0++0x00
|
|
line.byte 0x00 "IMO_TRIM32,IMO Trim Register 32"
|
|
group.byte 0x1F1++0x00
|
|
line.byte 0x00 "IMO_TRIM33,IMO Trim Register 33"
|
|
group.byte 0x1F2++0x00
|
|
line.byte 0x00 "IMO_TRIM34,IMO Trim Register 34"
|
|
group.byte 0x1F3++0x00
|
|
line.byte 0x00 "IMO_TRIM35,IMO Trim Register 35"
|
|
group.byte 0x1F4++0x00
|
|
line.byte 0x00 "IMO_TRIM36,IMO Trim Register 36"
|
|
group.byte 0x1F5++0x00
|
|
line.byte 0x00 "IMO_TRIM37,IMO Trim Register 37"
|
|
group.byte 0x1F6++0x00
|
|
line.byte 0x00 "IMO_TRIM38,IMO Trim Register 38"
|
|
group.byte 0x1F7++0x00
|
|
line.byte 0x00 "IMO_TRIM39,IMO Trim Register 39"
|
|
group.byte 0x1F8++0x00
|
|
line.byte 0x00 "IMO_TRIM40,IMO Trim Register 40"
|
|
group.byte 0x1F9++0x00
|
|
line.byte 0x00 "IMO_TRIM41,IMO Trim Register 41"
|
|
group.byte 0x1FA++0x00
|
|
line.byte 0x00 "IMO_TRIM42,IMO Trim Register 42"
|
|
group.byte 0x1FB++0x00
|
|
line.byte 0x00 "IMO_TRIM43,IMO Trim Register 43"
|
|
group.byte 0x1FC++0x00
|
|
line.byte 0x00 "IMO_TRIM44,IMO Trim Register 44"
|
|
group.byte 0x1FD++0x00
|
|
line.byte 0x00 "IMO_TRIM45,IMO Trim Register 45"
|
|
group.word 0x1FE++0x01
|
|
line.word 0x00 "CHECKSUM,Boot Checksum"
|
|
group.byte 0x200++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH0,Uncommitted Supervisorly Flash 0 In Macro 0"
|
|
group.byte 0x201++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH1,Uncommitted Supervisorly Flash 1 In Macro 0"
|
|
group.byte 0x202++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH2,Uncommitted Supervisorly Flash 2 In Macro 0"
|
|
group.byte 0x203++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH3,Uncommitted Supervisorly Flash 3 In Macro 0"
|
|
group.byte 0x204++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH4,Uncommitted Supervisorly Flash 4 In Macro 0"
|
|
group.byte 0x205++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH5,Uncommitted Supervisorly Flash 5 In Macro 0"
|
|
group.byte 0x206++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH6,Uncommitted Supervisorly Flash 6 In Macro 0"
|
|
group.byte 0x207++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH7,Uncommitted Supervisorly Flash 7 In Macro 0"
|
|
group.byte 0x208++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH8,Uncommitted Supervisorly Flash 8 In Macro 0"
|
|
group.byte 0x209++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH9,Uncommitted Supervisorly Flash 9 In Macro 0"
|
|
group.byte 0x20A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH10,Uncommitted Supervisorly Flash 10 In Macro 0"
|
|
group.byte 0x20B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH11,Uncommitted Supervisorly Flash 11 In Macro 0"
|
|
group.byte 0x20C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH12,Uncommitted Supervisorly Flash 12 In Macro 0"
|
|
group.byte 0x20D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH13,Uncommitted Supervisorly Flash 13 In Macro 0"
|
|
group.byte 0x20E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH14,Uncommitted Supervisorly Flash 14 In Macro 0"
|
|
group.byte 0x20F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH15,Uncommitted Supervisorly Flash 15 In Macro 0"
|
|
group.byte 0x210++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH16,Uncommitted Supervisorly Flash 16 In Macro 0"
|
|
group.byte 0x211++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH17,Uncommitted Supervisorly Flash 17 In Macro 0"
|
|
group.byte 0x212++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH18,Uncommitted Supervisorly Flash 18 In Macro 0"
|
|
group.byte 0x213++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH19,Uncommitted Supervisorly Flash 19 In Macro 0"
|
|
group.byte 0x214++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH20,Uncommitted Supervisorly Flash 20 In Macro 0"
|
|
group.byte 0x215++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH21,Uncommitted Supervisorly Flash 21 In Macro 0"
|
|
group.byte 0x216++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH22,Uncommitted Supervisorly Flash 22 In Macro 0"
|
|
group.byte 0x217++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH23,Uncommitted Supervisorly Flash 23 In Macro 0"
|
|
group.byte 0x218++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH24,Uncommitted Supervisorly Flash 24 In Macro 0"
|
|
group.byte 0x219++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH25,Uncommitted Supervisorly Flash 25 In Macro 0"
|
|
group.byte 0x21A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH26,Uncommitted Supervisorly Flash 26 In Macro 0"
|
|
group.byte 0x21B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH27,Uncommitted Supervisorly Flash 27 In Macro 0"
|
|
group.byte 0x21C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH28,Uncommitted Supervisorly Flash 28 In Macro 0"
|
|
group.byte 0x21D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH29,Uncommitted Supervisorly Flash 29 In Macro 0"
|
|
group.byte 0x21E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH30,Uncommitted Supervisorly Flash 30 In Macro 0"
|
|
group.byte 0x21F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH31,Uncommitted Supervisorly Flash 31 In Macro 0"
|
|
group.byte 0x220++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH32,Uncommitted Supervisorly Flash 32 In Macro 0"
|
|
group.byte 0x221++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH33,Uncommitted Supervisorly Flash 33 In Macro 0"
|
|
group.byte 0x222++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH34,Uncommitted Supervisorly Flash 34 In Macro 0"
|
|
group.byte 0x223++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH35,Uncommitted Supervisorly Flash 35 In Macro 0"
|
|
group.byte 0x224++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH36,Uncommitted Supervisorly Flash 36 In Macro 0"
|
|
group.byte 0x225++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH37,Uncommitted Supervisorly Flash 37 In Macro 0"
|
|
group.byte 0x226++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH38,Uncommitted Supervisorly Flash 38 In Macro 0"
|
|
group.byte 0x227++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH39,Uncommitted Supervisorly Flash 39 In Macro 0"
|
|
group.byte 0x228++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH40,Uncommitted Supervisorly Flash 40 In Macro 0"
|
|
group.byte 0x229++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH41,Uncommitted Supervisorly Flash 41 In Macro 0"
|
|
group.byte 0x22A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH42,Uncommitted Supervisorly Flash 42 In Macro 0"
|
|
group.byte 0x22B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH43,Uncommitted Supervisorly Flash 43 In Macro 0"
|
|
group.byte 0x22C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH44,Uncommitted Supervisorly Flash 44 In Macro 0"
|
|
group.byte 0x22D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH45,Uncommitted Supervisorly Flash 45 In Macro 0"
|
|
group.byte 0x22E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH46,Uncommitted Supervisorly Flash 46 In Macro 0"
|
|
group.byte 0x22F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH47,Uncommitted Supervisorly Flash 47 In Macro 0"
|
|
group.byte 0x230++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH48,Uncommitted Supervisorly Flash 48 In Macro 0"
|
|
group.byte 0x231++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH49,Uncommitted Supervisorly Flash 49 In Macro 0"
|
|
group.byte 0x232++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH50,Uncommitted Supervisorly Flash 50 In Macro 0"
|
|
group.byte 0x233++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH51,Uncommitted Supervisorly Flash 51 In Macro 0"
|
|
group.byte 0x234++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH52,Uncommitted Supervisorly Flash 52 In Macro 0"
|
|
group.byte 0x235++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH53,Uncommitted Supervisorly Flash 53 In Macro 0"
|
|
group.byte 0x236++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH54,Uncommitted Supervisorly Flash 54 In Macro 0"
|
|
group.byte 0x237++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH55,Uncommitted Supervisorly Flash 55 In Macro 0"
|
|
group.byte 0x238++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH56,Uncommitted Supervisorly Flash 56 In Macro 0"
|
|
group.byte 0x239++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH57,Uncommitted Supervisorly Flash 57 In Macro 0"
|
|
group.byte 0x23A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH58,Uncommitted Supervisorly Flash 58 In Macro 0"
|
|
group.byte 0x23B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH59,Uncommitted Supervisorly Flash 59 In Macro 0"
|
|
group.byte 0x23C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH60,Uncommitted Supervisorly Flash 60 In Macro 0"
|
|
group.byte 0x23D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH61,Uncommitted Supervisorly Flash 61 In Macro 0"
|
|
group.byte 0x23E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH62,Uncommitted Supervisorly Flash 62 In Macro 0"
|
|
group.byte 0x23F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH63,Uncommitted Supervisorly Flash 63 In Macro 0"
|
|
group.byte 0x240++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH64,Uncommitted Supervisorly Flash 64 In Macro 0"
|
|
group.byte 0x241++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH65,Uncommitted Supervisorly Flash 65 In Macro 0"
|
|
group.byte 0x242++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH66,Uncommitted Supervisorly Flash 66 In Macro 0"
|
|
group.byte 0x243++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH67,Uncommitted Supervisorly Flash 67 In Macro 0"
|
|
group.byte 0x244++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH68,Uncommitted Supervisorly Flash 68 In Macro 0"
|
|
group.byte 0x245++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH69,Uncommitted Supervisorly Flash 69 In Macro 0"
|
|
group.byte 0x246++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH70,Uncommitted Supervisorly Flash 70 In Macro 0"
|
|
group.byte 0x247++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH71,Uncommitted Supervisorly Flash 71 In Macro 0"
|
|
group.byte 0x248++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH72,Uncommitted Supervisorly Flash 72 In Macro 0"
|
|
group.byte 0x249++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH73,Uncommitted Supervisorly Flash 73 In Macro 0"
|
|
group.byte 0x24A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH74,Uncommitted Supervisorly Flash 74 In Macro 0"
|
|
group.byte 0x24B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH75,Uncommitted Supervisorly Flash 75 In Macro 0"
|
|
group.byte 0x24C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH76,Uncommitted Supervisorly Flash 76 In Macro 0"
|
|
group.byte 0x24D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH77,Uncommitted Supervisorly Flash 77 In Macro 0"
|
|
group.byte 0x24E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH78,Uncommitted Supervisorly Flash 78 In Macro 0"
|
|
group.byte 0x24F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH79,Uncommitted Supervisorly Flash 79 In Macro 0"
|
|
group.byte 0x250++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH80,Uncommitted Supervisorly Flash 80 In Macro 0"
|
|
group.byte 0x251++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH81,Uncommitted Supervisorly Flash 81 In Macro 0"
|
|
group.byte 0x252++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH82,Uncommitted Supervisorly Flash 82 In Macro 0"
|
|
group.byte 0x253++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH83,Uncommitted Supervisorly Flash 83 In Macro 0"
|
|
group.byte 0x254++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH84,Uncommitted Supervisorly Flash 84 In Macro 0"
|
|
group.byte 0x255++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH85,Uncommitted Supervisorly Flash 85 In Macro 0"
|
|
group.byte 0x256++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH86,Uncommitted Supervisorly Flash 86 In Macro 0"
|
|
group.byte 0x257++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH87,Uncommitted Supervisorly Flash 87 In Macro 0"
|
|
group.byte 0x258++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH88,Uncommitted Supervisorly Flash 88 In Macro 0"
|
|
group.byte 0x259++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH89,Uncommitted Supervisorly Flash 89 In Macro 0"
|
|
group.byte 0x25A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH90,Uncommitted Supervisorly Flash 90 In Macro 0"
|
|
group.byte 0x25B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH91,Uncommitted Supervisorly Flash 91 In Macro 0"
|
|
group.byte 0x25C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH92,Uncommitted Supervisorly Flash 92 In Macro 0"
|
|
group.byte 0x25D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH93,Uncommitted Supervisorly Flash 93 In Macro 0"
|
|
group.byte 0x25E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH94,Uncommitted Supervisorly Flash 94 In Macro 0"
|
|
group.byte 0x25F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH95,Uncommitted Supervisorly Flash 95 In Macro 0"
|
|
group.byte 0x260++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH96,Uncommitted Supervisorly Flash 96 In Macro 0"
|
|
group.byte 0x261++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH97,Uncommitted Supervisorly Flash 97 In Macro 0"
|
|
group.byte 0x262++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH98,Uncommitted Supervisorly Flash 98 In Macro 0"
|
|
group.byte 0x263++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH99,Uncommitted Supervisorly Flash 99 In Macro 0"
|
|
group.byte 0x264++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH100,Uncommitted Supervisorly Flash 100 In Macro 0"
|
|
group.byte 0x265++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH101,Uncommitted Supervisorly Flash 101 In Macro 0"
|
|
group.byte 0x266++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH102,Uncommitted Supervisorly Flash 102 In Macro 0"
|
|
group.byte 0x267++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH103,Uncommitted Supervisorly Flash 103 In Macro 0"
|
|
group.byte 0x268++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH104,Uncommitted Supervisorly Flash 104 In Macro 0"
|
|
group.byte 0x269++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH105,Uncommitted Supervisorly Flash 105 In Macro 0"
|
|
group.byte 0x26A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH106,Uncommitted Supervisorly Flash 106 In Macro 0"
|
|
group.byte 0x26B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH107,Uncommitted Supervisorly Flash 107 In Macro 0"
|
|
group.byte 0x26C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH108,Uncommitted Supervisorly Flash 108 In Macro 0"
|
|
group.byte 0x26D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH109,Uncommitted Supervisorly Flash 109 In Macro 0"
|
|
group.byte 0x26E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH110,Uncommitted Supervisorly Flash 110 In Macro 0"
|
|
group.byte 0x26F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH111,Uncommitted Supervisorly Flash 111 In Macro 0"
|
|
group.byte 0x270++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH112,Uncommitted Supervisorly Flash 112 In Macro 0"
|
|
group.byte 0x271++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH113,Uncommitted Supervisorly Flash 113 In Macro 0"
|
|
group.byte 0x272++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH114,Uncommitted Supervisorly Flash 114 In Macro 0"
|
|
group.byte 0x273++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH115,Uncommitted Supervisorly Flash 115 In Macro 0"
|
|
group.byte 0x274++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH116,Uncommitted Supervisorly Flash 116 In Macro 0"
|
|
group.byte 0x275++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH117,Uncommitted Supervisorly Flash 117 In Macro 0"
|
|
group.byte 0x276++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH118,Uncommitted Supervisorly Flash 118 In Macro 0"
|
|
group.byte 0x277++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH119,Uncommitted Supervisorly Flash 119 In Macro 0"
|
|
group.byte 0x278++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH120,Uncommitted Supervisorly Flash 120 In Macro 0"
|
|
group.byte 0x279++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH121,Uncommitted Supervisorly Flash 121 In Macro 0"
|
|
group.byte 0x27A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH122,Uncommitted Supervisorly Flash 122 In Macro 0"
|
|
group.byte 0x27B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH123,Uncommitted Supervisorly Flash 123 In Macro 0"
|
|
group.byte 0x27C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH124,Uncommitted Supervisorly Flash 124 In Macro 0"
|
|
group.byte 0x27D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH125,Uncommitted Supervisorly Flash 125 In Macro 0"
|
|
group.byte 0x27E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH126,Uncommitted Supervisorly Flash 126 In Macro 0"
|
|
group.byte 0x27F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH127,Uncommitted Supervisorly Flash 127 In Macro 0"
|
|
group.byte 0x280++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH128,Uncommitted Supervisorly Flash 128 In Macro 0"
|
|
group.byte 0x281++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH129,Uncommitted Supervisorly Flash 129 In Macro 0"
|
|
group.byte 0x282++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH130,Uncommitted Supervisorly Flash 130 In Macro 0"
|
|
group.byte 0x283++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH131,Uncommitted Supervisorly Flash 131 In Macro 0"
|
|
group.byte 0x284++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH132,Uncommitted Supervisorly Flash 132 In Macro 0"
|
|
group.byte 0x285++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH133,Uncommitted Supervisorly Flash 133 In Macro 0"
|
|
group.byte 0x286++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH134,Uncommitted Supervisorly Flash 134 In Macro 0"
|
|
group.byte 0x287++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH135,Uncommitted Supervisorly Flash 135 In Macro 0"
|
|
group.byte 0x288++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH136,Uncommitted Supervisorly Flash 136 In Macro 0"
|
|
group.byte 0x289++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH137,Uncommitted Supervisorly Flash 137 In Macro 0"
|
|
group.byte 0x28A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH138,Uncommitted Supervisorly Flash 138 In Macro 0"
|
|
group.byte 0x28B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH139,Uncommitted Supervisorly Flash 139 In Macro 0"
|
|
group.byte 0x28C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH140,Uncommitted Supervisorly Flash 140 In Macro 0"
|
|
group.byte 0x28D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH141,Uncommitted Supervisorly Flash 141 In Macro 0"
|
|
group.byte 0x28E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH142,Uncommitted Supervisorly Flash 142 In Macro 0"
|
|
group.byte 0x28F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH143,Uncommitted Supervisorly Flash 143 In Macro 0"
|
|
group.byte 0x290++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH144,Uncommitted Supervisorly Flash 144 In Macro 0"
|
|
group.byte 0x291++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH145,Uncommitted Supervisorly Flash 145 In Macro 0"
|
|
group.byte 0x292++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH146,Uncommitted Supervisorly Flash 146 In Macro 0"
|
|
group.byte 0x293++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH147,Uncommitted Supervisorly Flash 147 In Macro 0"
|
|
group.byte 0x294++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH148,Uncommitted Supervisorly Flash 148 In Macro 0"
|
|
group.byte 0x295++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH149,Uncommitted Supervisorly Flash 149 In Macro 0"
|
|
group.byte 0x296++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH150,Uncommitted Supervisorly Flash 150 In Macro 0"
|
|
group.byte 0x297++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH151,Uncommitted Supervisorly Flash 151 In Macro 0"
|
|
group.byte 0x298++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH152,Uncommitted Supervisorly Flash 152 In Macro 0"
|
|
group.byte 0x299++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH153,Uncommitted Supervisorly Flash 153 In Macro 0"
|
|
group.byte 0x29A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH154,Uncommitted Supervisorly Flash 154 In Macro 0"
|
|
group.byte 0x29B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH155,Uncommitted Supervisorly Flash 155 In Macro 0"
|
|
group.byte 0x29C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH156,Uncommitted Supervisorly Flash 156 In Macro 0"
|
|
group.byte 0x29D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH157,Uncommitted Supervisorly Flash 157 In Macro 0"
|
|
group.byte 0x29E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH158,Uncommitted Supervisorly Flash 158 In Macro 0"
|
|
group.byte 0x29F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH159,Uncommitted Supervisorly Flash 159 In Macro 0"
|
|
group.byte 0x2A0++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH160,Uncommitted Supervisorly Flash 160 In Macro 0"
|
|
group.byte 0x2A1++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH161,Uncommitted Supervisorly Flash 161 In Macro 0"
|
|
group.byte 0x2A2++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH162,Uncommitted Supervisorly Flash 162 In Macro 0"
|
|
group.byte 0x2A3++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH163,Uncommitted Supervisorly Flash 163 In Macro 0"
|
|
group.byte 0x2A4++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH164,Uncommitted Supervisorly Flash 164 In Macro 0"
|
|
group.byte 0x2A5++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH165,Uncommitted Supervisorly Flash 165 In Macro 0"
|
|
group.byte 0x2A6++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH166,Uncommitted Supervisorly Flash 166 In Macro 0"
|
|
group.byte 0x2A7++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH167,Uncommitted Supervisorly Flash 167 In Macro 0"
|
|
group.byte 0x2A8++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH168,Uncommitted Supervisorly Flash 168 In Macro 0"
|
|
group.byte 0x2A9++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH169,Uncommitted Supervisorly Flash 169 In Macro 0"
|
|
group.byte 0x2AA++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH170,Uncommitted Supervisorly Flash 170 In Macro 0"
|
|
group.byte 0x2AB++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH171,Uncommitted Supervisorly Flash 171 In Macro 0"
|
|
group.byte 0x2AC++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH172,Uncommitted Supervisorly Flash 172 In Macro 0"
|
|
group.byte 0x2AD++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH173,Uncommitted Supervisorly Flash 173 In Macro 0"
|
|
group.byte 0x2AE++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH174,Uncommitted Supervisorly Flash 174 In Macro 0"
|
|
group.byte 0x2AF++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH175,Uncommitted Supervisorly Flash 175 In Macro 0"
|
|
group.byte 0x2B0++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH176,Uncommitted Supervisorly Flash 176 In Macro 0"
|
|
group.byte 0x2B1++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH177,Uncommitted Supervisorly Flash 177 In Macro 0"
|
|
group.byte 0x2B2++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH178,Uncommitted Supervisorly Flash 178 In Macro 0"
|
|
group.byte 0x2B3++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH179,Uncommitted Supervisorly Flash 179 In Macro 0"
|
|
group.byte 0x2B4++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH180,Uncommitted Supervisorly Flash 180 In Macro 0"
|
|
group.byte 0x2B5++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH181,Uncommitted Supervisorly Flash 181 In Macro 0"
|
|
group.byte 0x2B6++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH182,Uncommitted Supervisorly Flash 182 In Macro 0"
|
|
group.byte 0x2B7++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH183,Uncommitted Supervisorly Flash 183 In Macro 0"
|
|
group.byte 0x2B8++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH184,Uncommitted Supervisorly Flash 184 In Macro 0"
|
|
group.byte 0x2B9++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH185,Uncommitted Supervisorly Flash 185 In Macro 0"
|
|
group.byte 0x2BA++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH186,Uncommitted Supervisorly Flash 186 In Macro 0"
|
|
group.byte 0x2BB++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH187,Uncommitted Supervisorly Flash 187 In Macro 0"
|
|
group.byte 0x2BC++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH188,Uncommitted Supervisorly Flash 188 In Macro 0"
|
|
group.byte 0x2BD++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH189,Uncommitted Supervisorly Flash 189 In Macro 0"
|
|
group.byte 0x2BE++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH190,Uncommitted Supervisorly Flash 190 In Macro 0"
|
|
group.byte 0x2BF++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH191,Uncommitted Supervisorly Flash 191 In Macro 0"
|
|
group.byte 0x2C0++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH192,Uncommitted Supervisorly Flash 192 In Macro 0"
|
|
group.byte 0x2C1++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH193,Uncommitted Supervisorly Flash 193 In Macro 0"
|
|
group.byte 0x2C2++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH194,Uncommitted Supervisorly Flash 194 In Macro 0"
|
|
group.byte 0x2C3++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH195,Uncommitted Supervisorly Flash 195 In Macro 0"
|
|
group.byte 0x2C4++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH196,Uncommitted Supervisorly Flash 196 In Macro 0"
|
|
group.byte 0x2C5++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH197,Uncommitted Supervisorly Flash 197 In Macro 0"
|
|
group.byte 0x2C6++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH198,Uncommitted Supervisorly Flash 198 In Macro 0"
|
|
group.byte 0x2C7++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH199,Uncommitted Supervisorly Flash 199 In Macro 0"
|
|
group.byte 0x2C8++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH200,Uncommitted Supervisorly Flash 200 In Macro 0"
|
|
group.byte 0x2C9++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH201,Uncommitted Supervisorly Flash 201 In Macro 0"
|
|
group.byte 0x2CA++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH202,Uncommitted Supervisorly Flash 202 In Macro 0"
|
|
group.byte 0x2CB++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH203,Uncommitted Supervisorly Flash 203 In Macro 0"
|
|
group.byte 0x2CC++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH204,Uncommitted Supervisorly Flash 204 In Macro 0"
|
|
group.byte 0x2CD++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH205,Uncommitted Supervisorly Flash 205 In Macro 0"
|
|
group.byte 0x2CE++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH206,Uncommitted Supervisorly Flash 206 In Macro 0"
|
|
group.byte 0x2CF++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH207,Uncommitted Supervisorly Flash 207 In Macro 0"
|
|
group.byte 0x2D0++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH208,Uncommitted Supervisorly Flash 208 In Macro 0"
|
|
group.byte 0x2D1++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH209,Uncommitted Supervisorly Flash 209 In Macro 0"
|
|
group.byte 0x2D2++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH210,Uncommitted Supervisorly Flash 210 In Macro 0"
|
|
group.byte 0x2D3++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH211,Uncommitted Supervisorly Flash 211 In Macro 0"
|
|
group.byte 0x2D4++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH212,Uncommitted Supervisorly Flash 212 In Macro 0"
|
|
group.byte 0x2D5++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH213,Uncommitted Supervisorly Flash 213 In Macro 0"
|
|
group.byte 0x2D6++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH214,Uncommitted Supervisorly Flash 214 In Macro 0"
|
|
group.byte 0x2D7++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH215,Uncommitted Supervisorly Flash 215 In Macro 0"
|
|
group.byte 0x2D8++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH216,Uncommitted Supervisorly Flash 216 In Macro 0"
|
|
group.byte 0x2D9++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH217,Uncommitted Supervisorly Flash 217 In Macro 0"
|
|
group.byte 0x2DA++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH218,Uncommitted Supervisorly Flash 218 In Macro 0"
|
|
group.byte 0x2DB++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH219,Uncommitted Supervisorly Flash 219 In Macro 0"
|
|
group.byte 0x2DC++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH220,Uncommitted Supervisorly Flash 220 In Macro 0"
|
|
group.byte 0x2DD++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH221,Uncommitted Supervisorly Flash 221 In Macro 0"
|
|
group.byte 0x2DE++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH222,Uncommitted Supervisorly Flash 222 In Macro 0"
|
|
group.byte 0x2DF++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH223,Uncommitted Supervisorly Flash 223 In Macro 0"
|
|
group.byte 0x2E0++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH224,Uncommitted Supervisorly Flash 224 In Macro 0"
|
|
group.byte 0x2E1++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH225,Uncommitted Supervisorly Flash 225 In Macro 0"
|
|
group.byte 0x2E2++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH226,Uncommitted Supervisorly Flash 226 In Macro 0"
|
|
group.byte 0x2E3++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH227,Uncommitted Supervisorly Flash 227 In Macro 0"
|
|
group.byte 0x2E4++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH228,Uncommitted Supervisorly Flash 228 In Macro 0"
|
|
group.byte 0x2E5++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH229,Uncommitted Supervisorly Flash 229 In Macro 0"
|
|
group.byte 0x2E6++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH230,Uncommitted Supervisorly Flash 230 In Macro 0"
|
|
group.byte 0x2E7++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH231,Uncommitted Supervisorly Flash 231 In Macro 0"
|
|
group.byte 0x2E8++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH232,Uncommitted Supervisorly Flash 232 In Macro 0"
|
|
group.byte 0x2E9++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH233,Uncommitted Supervisorly Flash 233 In Macro 0"
|
|
group.byte 0x2EA++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH234,Uncommitted Supervisorly Flash 234 In Macro 0"
|
|
group.byte 0x2EB++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH235,Uncommitted Supervisorly Flash 235 In Macro 0"
|
|
group.byte 0x2EC++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH236,Uncommitted Supervisorly Flash 236 In Macro 0"
|
|
group.byte 0x2ED++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH237,Uncommitted Supervisorly Flash 237 In Macro 0"
|
|
group.byte 0x2EE++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH238,Uncommitted Supervisorly Flash 238 In Macro 0"
|
|
group.byte 0x2EF++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH239,Uncommitted Supervisorly Flash 239 In Macro 0"
|
|
group.byte 0x2F0++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH240,Uncommitted Supervisorly Flash 240 In Macro 0"
|
|
group.byte 0x2F1++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH241,Uncommitted Supervisorly Flash 241 In Macro 0"
|
|
group.byte 0x2F2++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH242,Uncommitted Supervisorly Flash 242 In Macro 0"
|
|
group.byte 0x2F3++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH243,Uncommitted Supervisorly Flash 243 In Macro 0"
|
|
group.byte 0x2F4++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH244,Uncommitted Supervisorly Flash 244 In Macro 0"
|
|
group.byte 0x2F5++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH245,Uncommitted Supervisorly Flash 245 In Macro 0"
|
|
group.byte 0x2F6++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH246,Uncommitted Supervisorly Flash 246 In Macro 0"
|
|
group.byte 0x2F7++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH247,Uncommitted Supervisorly Flash 247 In Macro 0"
|
|
group.byte 0x2F8++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH248,Uncommitted Supervisorly Flash 248 In Macro 0"
|
|
group.byte 0x2F9++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH249,Uncommitted Supervisorly Flash 249 In Macro 0"
|
|
group.byte 0x2FA++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH250,Uncommitted Supervisorly Flash 250 In Macro 0"
|
|
group.byte 0x2FB++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH251,Uncommitted Supervisorly Flash 251 In Macro 0"
|
|
group.byte 0x2FC++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH252,Uncommitted Supervisorly Flash 252 In Macro 0"
|
|
group.byte 0x2FD++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH253,Uncommitted Supervisorly Flash 253 In Macro 0"
|
|
group.byte 0x2FE++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH254,Uncommitted Supervisorly Flash 254 In Macro 0"
|
|
group.byte 0x2FF++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH255,Uncommitted Supervisorly Flash 255 In Macro 0"
|
|
group.byte 0x300++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH256,Uncommitted Supervisorly Flash 256 In Macro 0"
|
|
group.byte 0x301++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH257,Uncommitted Supervisorly Flash 257 In Macro 0"
|
|
group.byte 0x302++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH258,Uncommitted Supervisorly Flash 258 In Macro 0"
|
|
group.byte 0x303++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH259,Uncommitted Supervisorly Flash 259 In Macro 0"
|
|
group.byte 0x304++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH260,Uncommitted Supervisorly Flash 260 In Macro 0"
|
|
group.byte 0x305++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH261,Uncommitted Supervisorly Flash 261 In Macro 0"
|
|
group.byte 0x306++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH262,Uncommitted Supervisorly Flash 262 In Macro 0"
|
|
group.byte 0x307++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH263,Uncommitted Supervisorly Flash 263 In Macro 0"
|
|
group.byte 0x308++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH264,Uncommitted Supervisorly Flash 264 In Macro 0"
|
|
group.byte 0x309++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH265,Uncommitted Supervisorly Flash 265 In Macro 0"
|
|
group.byte 0x30A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH266,Uncommitted Supervisorly Flash 266 In Macro 0"
|
|
group.byte 0x30B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH267,Uncommitted Supervisorly Flash 267 In Macro 0"
|
|
group.byte 0x30C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH268,Uncommitted Supervisorly Flash 268 In Macro 0"
|
|
group.byte 0x30D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH269,Uncommitted Supervisorly Flash 269 In Macro 0"
|
|
group.byte 0x30E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH270,Uncommitted Supervisorly Flash 270 In Macro 0"
|
|
group.byte 0x30F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH271,Uncommitted Supervisorly Flash 271 In Macro 0"
|
|
group.byte 0x310++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH272,Uncommitted Supervisorly Flash 272 In Macro 0"
|
|
group.byte 0x311++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH273,Uncommitted Supervisorly Flash 273 In Macro 0"
|
|
group.byte 0x312++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH274,Uncommitted Supervisorly Flash 274 In Macro 0"
|
|
group.byte 0x313++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH275,Uncommitted Supervisorly Flash 275 In Macro 0"
|
|
group.byte 0x314++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH276,Uncommitted Supervisorly Flash 276 In Macro 0"
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH277,Uncommitted Supervisorly Flash 277 In Macro 0"
|
|
group.byte 0x316++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH278,Uncommitted Supervisorly Flash 278 In Macro 0"
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH279,Uncommitted Supervisorly Flash 279 In Macro 0"
|
|
group.byte 0x318++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH280,Uncommitted Supervisorly Flash 280 In Macro 0"
|
|
group.byte 0x319++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH281,Uncommitted Supervisorly Flash 281 In Macro 0"
|
|
group.byte 0x31A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH282,Uncommitted Supervisorly Flash 282 In Macro 0"
|
|
group.byte 0x31B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH283,Uncommitted Supervisorly Flash 283 In Macro 0"
|
|
group.byte 0x31C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH284,Uncommitted Supervisorly Flash 284 In Macro 0"
|
|
group.byte 0x31D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH285,Uncommitted Supervisorly Flash 285 In Macro 0"
|
|
group.byte 0x31E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH286,Uncommitted Supervisorly Flash 286 In Macro 0"
|
|
group.byte 0x31F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH287,Uncommitted Supervisorly Flash 287 In Macro 0"
|
|
group.byte 0x320++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH288,Uncommitted Supervisorly Flash 288 In Macro 0"
|
|
group.byte 0x321++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH289,Uncommitted Supervisorly Flash 289 In Macro 0"
|
|
group.byte 0x322++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH290,Uncommitted Supervisorly Flash 290 In Macro 0"
|
|
group.byte 0x323++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH291,Uncommitted Supervisorly Flash 291 In Macro 0"
|
|
group.byte 0x324++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH292,Uncommitted Supervisorly Flash 292 In Macro 0"
|
|
group.byte 0x325++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH293,Uncommitted Supervisorly Flash 293 In Macro 0"
|
|
group.byte 0x326++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH294,Uncommitted Supervisorly Flash 294 In Macro 0"
|
|
group.byte 0x327++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH295,Uncommitted Supervisorly Flash 295 In Macro 0"
|
|
group.byte 0x328++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH296,Uncommitted Supervisorly Flash 296 In Macro 0"
|
|
group.byte 0x329++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH297,Uncommitted Supervisorly Flash 297 In Macro 0"
|
|
group.byte 0x32A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH298,Uncommitted Supervisorly Flash 298 In Macro 0"
|
|
group.byte 0x32B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH299,Uncommitted Supervisorly Flash 299 In Macro 0"
|
|
group.byte 0x32C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH300,Uncommitted Supervisorly Flash 300 In Macro 0"
|
|
group.byte 0x32D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH301,Uncommitted Supervisorly Flash 301 In Macro 0"
|
|
group.byte 0x32E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH302,Uncommitted Supervisorly Flash 302 In Macro 0"
|
|
group.byte 0x32F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH303,Uncommitted Supervisorly Flash 303 In Macro 0"
|
|
group.byte 0x330++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH304,Uncommitted Supervisorly Flash 304 In Macro 0"
|
|
group.byte 0x331++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH305,Uncommitted Supervisorly Flash 305 In Macro 0"
|
|
group.byte 0x332++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH306,Uncommitted Supervisorly Flash 306 In Macro 0"
|
|
group.byte 0x333++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH307,Uncommitted Supervisorly Flash 307 In Macro 0"
|
|
group.byte 0x334++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH308,Uncommitted Supervisorly Flash 308 In Macro 0"
|
|
group.byte 0x335++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH309,Uncommitted Supervisorly Flash 309 In Macro 0"
|
|
group.byte 0x336++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH310,Uncommitted Supervisorly Flash 310 In Macro 0"
|
|
group.byte 0x337++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH311,Uncommitted Supervisorly Flash 311 In Macro 0"
|
|
group.byte 0x338++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH312,Uncommitted Supervisorly Flash 312 In Macro 0"
|
|
group.byte 0x339++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH313,Uncommitted Supervisorly Flash 313 In Macro 0"
|
|
group.byte 0x33A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH314,Uncommitted Supervisorly Flash 314 In Macro 0"
|
|
group.byte 0x33B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH315,Uncommitted Supervisorly Flash 315 In Macro 0"
|
|
group.byte 0x33C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH316,Uncommitted Supervisorly Flash 316 In Macro 0"
|
|
group.byte 0x33D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH317,Uncommitted Supervisorly Flash 317 In Macro 0"
|
|
group.byte 0x33E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH318,Uncommitted Supervisorly Flash 318 In Macro 0"
|
|
group.byte 0x33F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH319,Uncommitted Supervisorly Flash 319 In Macro 0"
|
|
group.byte 0x340++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH320,Uncommitted Supervisorly Flash 320 In Macro 0"
|
|
group.byte 0x341++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH321,Uncommitted Supervisorly Flash 321 In Macro 0"
|
|
group.byte 0x342++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH322,Uncommitted Supervisorly Flash 322 In Macro 0"
|
|
group.byte 0x343++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH323,Uncommitted Supervisorly Flash 323 In Macro 0"
|
|
group.byte 0x344++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH324,Uncommitted Supervisorly Flash 324 In Macro 0"
|
|
group.byte 0x345++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH325,Uncommitted Supervisorly Flash 325 In Macro 0"
|
|
group.byte 0x346++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH326,Uncommitted Supervisorly Flash 326 In Macro 0"
|
|
group.byte 0x347++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH327,Uncommitted Supervisorly Flash 327 In Macro 0"
|
|
group.byte 0x348++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH328,Uncommitted Supervisorly Flash 328 In Macro 0"
|
|
group.byte 0x349++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH329,Uncommitted Supervisorly Flash 329 In Macro 0"
|
|
group.byte 0x34A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH330,Uncommitted Supervisorly Flash 330 In Macro 0"
|
|
group.byte 0x34B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH331,Uncommitted Supervisorly Flash 331 In Macro 0"
|
|
group.byte 0x34C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH332,Uncommitted Supervisorly Flash 332 In Macro 0"
|
|
group.byte 0x34D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH333,Uncommitted Supervisorly Flash 333 In Macro 0"
|
|
group.byte 0x34E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH334,Uncommitted Supervisorly Flash 334 In Macro 0"
|
|
group.byte 0x34F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH335,Uncommitted Supervisorly Flash 335 In Macro 0"
|
|
group.byte 0x350++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH336,Uncommitted Supervisorly Flash 336 In Macro 0"
|
|
group.byte 0x351++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH337,Uncommitted Supervisorly Flash 337 In Macro 0"
|
|
group.byte 0x352++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH338,Uncommitted Supervisorly Flash 338 In Macro 0"
|
|
group.byte 0x353++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH339,Uncommitted Supervisorly Flash 339 In Macro 0"
|
|
group.byte 0x354++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH340,Uncommitted Supervisorly Flash 340 In Macro 0"
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH341,Uncommitted Supervisorly Flash 341 In Macro 0"
|
|
group.byte 0x356++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH342,Uncommitted Supervisorly Flash 342 In Macro 0"
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH343,Uncommitted Supervisorly Flash 343 In Macro 0"
|
|
group.byte 0x358++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH344,Uncommitted Supervisorly Flash 344 In Macro 0"
|
|
group.byte 0x359++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH345,Uncommitted Supervisorly Flash 345 In Macro 0"
|
|
group.byte 0x35A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH346,Uncommitted Supervisorly Flash 346 In Macro 0"
|
|
group.byte 0x35B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH347,Uncommitted Supervisorly Flash 347 In Macro 0"
|
|
group.byte 0x35C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH348,Uncommitted Supervisorly Flash 348 In Macro 0"
|
|
group.byte 0x35D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH349,Uncommitted Supervisorly Flash 349 In Macro 0"
|
|
group.byte 0x35E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH350,Uncommitted Supervisorly Flash 350 In Macro 0"
|
|
group.byte 0x35F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH351,Uncommitted Supervisorly Flash 351 In Macro 0"
|
|
group.byte 0x360++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH352,Uncommitted Supervisorly Flash 352 In Macro 0"
|
|
group.byte 0x361++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH353,Uncommitted Supervisorly Flash 353 In Macro 0"
|
|
group.byte 0x362++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH354,Uncommitted Supervisorly Flash 354 In Macro 0"
|
|
group.byte 0x363++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH355,Uncommitted Supervisorly Flash 355 In Macro 0"
|
|
group.byte 0x364++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH356,Uncommitted Supervisorly Flash 356 In Macro 0"
|
|
group.byte 0x365++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH357,Uncommitted Supervisorly Flash 357 In Macro 0"
|
|
group.byte 0x366++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH358,Uncommitted Supervisorly Flash 358 In Macro 0"
|
|
group.byte 0x367++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH359,Uncommitted Supervisorly Flash 359 In Macro 0"
|
|
group.byte 0x368++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH360,Uncommitted Supervisorly Flash 360 In Macro 0"
|
|
group.byte 0x369++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH361,Uncommitted Supervisorly Flash 361 In Macro 0"
|
|
group.byte 0x36A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH362,Uncommitted Supervisorly Flash 362 In Macro 0"
|
|
group.byte 0x36B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH363,Uncommitted Supervisorly Flash 363 In Macro 0"
|
|
group.byte 0x36C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH364,Uncommitted Supervisorly Flash 364 In Macro 0"
|
|
group.byte 0x36D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH365,Uncommitted Supervisorly Flash 365 In Macro 0"
|
|
group.byte 0x36E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH366,Uncommitted Supervisorly Flash 366 In Macro 0"
|
|
group.byte 0x36F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH367,Uncommitted Supervisorly Flash 367 In Macro 0"
|
|
group.byte 0x370++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH368,Uncommitted Supervisorly Flash 368 In Macro 0"
|
|
group.byte 0x371++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH369,Uncommitted Supervisorly Flash 369 In Macro 0"
|
|
group.byte 0x372++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH370,Uncommitted Supervisorly Flash 370 In Macro 0"
|
|
group.byte 0x373++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH371,Uncommitted Supervisorly Flash 371 In Macro 0"
|
|
group.byte 0x374++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH372,Uncommitted Supervisorly Flash 372 In Macro 0"
|
|
group.byte 0x375++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH373,Uncommitted Supervisorly Flash 373 In Macro 0"
|
|
group.byte 0x376++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH374,Uncommitted Supervisorly Flash 374 In Macro 0"
|
|
group.byte 0x377++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH375,Uncommitted Supervisorly Flash 375 In Macro 0"
|
|
group.byte 0x378++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH376,Uncommitted Supervisorly Flash 376 In Macro 0"
|
|
group.byte 0x379++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH377,Uncommitted Supervisorly Flash 377 In Macro 0"
|
|
group.byte 0x37A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH378,Uncommitted Supervisorly Flash 378 In Macro 0"
|
|
group.byte 0x37B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH379,Uncommitted Supervisorly Flash 379 In Macro 0"
|
|
group.byte 0x37C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH380,Uncommitted Supervisorly Flash 380 In Macro 0"
|
|
group.byte 0x37D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH381,Uncommitted Supervisorly Flash 381 In Macro 0"
|
|
group.byte 0x37E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH382,Uncommitted Supervisorly Flash 382 In Macro 0"
|
|
group.byte 0x37F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH383,Uncommitted Supervisorly Flash 383 In Macro 0"
|
|
group.byte 0x380++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH384,Uncommitted Supervisorly Flash 384 In Macro 0"
|
|
group.byte 0x381++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH385,Uncommitted Supervisorly Flash 385 In Macro 0"
|
|
group.byte 0x382++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH386,Uncommitted Supervisorly Flash 386 In Macro 0"
|
|
group.byte 0x383++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH387,Uncommitted Supervisorly Flash 387 In Macro 0"
|
|
group.byte 0x384++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH388,Uncommitted Supervisorly Flash 388 In Macro 0"
|
|
group.byte 0x385++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH389,Uncommitted Supervisorly Flash 389 In Macro 0"
|
|
group.byte 0x386++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH390,Uncommitted Supervisorly Flash 390 In Macro 0"
|
|
group.byte 0x387++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH391,Uncommitted Supervisorly Flash 391 In Macro 0"
|
|
group.byte 0x388++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH392,Uncommitted Supervisorly Flash 392 In Macro 0"
|
|
group.byte 0x389++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH393,Uncommitted Supervisorly Flash 393 In Macro 0"
|
|
group.byte 0x38A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH394,Uncommitted Supervisorly Flash 394 In Macro 0"
|
|
group.byte 0x38B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH395,Uncommitted Supervisorly Flash 395 In Macro 0"
|
|
group.byte 0x38C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH396,Uncommitted Supervisorly Flash 396 In Macro 0"
|
|
group.byte 0x38D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH397,Uncommitted Supervisorly Flash 397 In Macro 0"
|
|
group.byte 0x38E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH398,Uncommitted Supervisorly Flash 398 In Macro 0"
|
|
group.byte 0x38F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH399,Uncommitted Supervisorly Flash 399 In Macro 0"
|
|
group.byte 0x390++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH400,Uncommitted Supervisorly Flash 400 In Macro 0"
|
|
group.byte 0x391++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH401,Uncommitted Supervisorly Flash 401 In Macro 0"
|
|
group.byte 0x392++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH402,Uncommitted Supervisorly Flash 402 In Macro 0"
|
|
group.byte 0x393++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH403,Uncommitted Supervisorly Flash 403 In Macro 0"
|
|
group.byte 0x394++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH404,Uncommitted Supervisorly Flash 404 In Macro 0"
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH405,Uncommitted Supervisorly Flash 405 In Macro 0"
|
|
group.byte 0x396++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH406,Uncommitted Supervisorly Flash 406 In Macro 0"
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH407,Uncommitted Supervisorly Flash 407 In Macro 0"
|
|
group.byte 0x398++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH408,Uncommitted Supervisorly Flash 408 In Macro 0"
|
|
group.byte 0x399++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH409,Uncommitted Supervisorly Flash 409 In Macro 0"
|
|
group.byte 0x39A++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH410,Uncommitted Supervisorly Flash 410 In Macro 0"
|
|
group.byte 0x39B++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH411,Uncommitted Supervisorly Flash 411 In Macro 0"
|
|
group.byte 0x39C++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH412,Uncommitted Supervisorly Flash 412 In Macro 0"
|
|
group.byte 0x39D++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH413,Uncommitted Supervisorly Flash 413 In Macro 0"
|
|
group.byte 0x39E++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH414,Uncommitted Supervisorly Flash 414 In Macro 0"
|
|
group.byte 0x39F++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH415,Uncommitted Supervisorly Flash 415 In Macro 0"
|
|
group.byte 0x3A0++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH416,Uncommitted Supervisorly Flash 416 In Macro 0"
|
|
group.byte 0x3A1++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH417,Uncommitted Supervisorly Flash 417 In Macro 0"
|
|
group.byte 0x3A2++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH418,Uncommitted Supervisorly Flash 418 In Macro 0"
|
|
group.byte 0x3A3++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH419,Uncommitted Supervisorly Flash 419 In Macro 0"
|
|
group.byte 0x3A4++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH420,Uncommitted Supervisorly Flash 420 In Macro 0"
|
|
group.byte 0x3A5++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH421,Uncommitted Supervisorly Flash 421 In Macro 0"
|
|
group.byte 0x3A6++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH422,Uncommitted Supervisorly Flash 422 In Macro 0"
|
|
group.byte 0x3A7++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH423,Uncommitted Supervisorly Flash 423 In Macro 0"
|
|
group.byte 0x3A8++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH424,Uncommitted Supervisorly Flash 424 In Macro 0"
|
|
group.byte 0x3A9++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH425,Uncommitted Supervisorly Flash 425 In Macro 0"
|
|
group.byte 0x3AA++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH426,Uncommitted Supervisorly Flash 426 In Macro 0"
|
|
group.byte 0x3AB++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH427,Uncommitted Supervisorly Flash 427 In Macro 0"
|
|
group.byte 0x3AC++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH428,Uncommitted Supervisorly Flash 428 In Macro 0"
|
|
group.byte 0x3AD++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH429,Uncommitted Supervisorly Flash 429 In Macro 0"
|
|
group.byte 0x3AE++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH430,Uncommitted Supervisorly Flash 430 In Macro 0"
|
|
group.byte 0x3AF++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH431,Uncommitted Supervisorly Flash 431 In Macro 0"
|
|
group.byte 0x3B0++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH432,Uncommitted Supervisorly Flash 432 In Macro 0"
|
|
group.byte 0x3B1++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH433,Uncommitted Supervisorly Flash 433 In Macro 0"
|
|
group.byte 0x3B2++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH434,Uncommitted Supervisorly Flash 434 In Macro 0"
|
|
group.byte 0x3B3++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH435,Uncommitted Supervisorly Flash 435 In Macro 0"
|
|
group.byte 0x3B4++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH436,Uncommitted Supervisorly Flash 436 In Macro 0"
|
|
group.byte 0x3B5++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH437,Uncommitted Supervisorly Flash 437 In Macro 0"
|
|
group.byte 0x3B6++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH438,Uncommitted Supervisorly Flash 438 In Macro 0"
|
|
group.byte 0x3B7++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH439,Uncommitted Supervisorly Flash 439 In Macro 0"
|
|
group.byte 0x3B8++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH440,Uncommitted Supervisorly Flash 440 In Macro 0"
|
|
group.byte 0x3B9++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH441,Uncommitted Supervisorly Flash 441 In Macro 0"
|
|
group.byte 0x3BA++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH442,Uncommitted Supervisorly Flash 442 In Macro 0"
|
|
group.byte 0x3BB++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH443,Uncommitted Supervisorly Flash 443 In Macro 0"
|
|
group.byte 0x3BC++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH444,Uncommitted Supervisorly Flash 444 In Macro 0"
|
|
group.byte 0x3BD++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH445,Uncommitted Supervisorly Flash 445 In Macro 0"
|
|
group.byte 0x3BE++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH446,Uncommitted Supervisorly Flash 446 In Macro 0"
|
|
group.byte 0x3BF++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH447,Uncommitted Supervisorly Flash 447 In Macro 0"
|
|
group.byte 0x3C0++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH448,Uncommitted Supervisorly Flash 448 In Macro 0"
|
|
group.byte 0x3C1++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH449,Uncommitted Supervisorly Flash 449 In Macro 0"
|
|
group.byte 0x3C2++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH450,Uncommitted Supervisorly Flash 450 In Macro 0"
|
|
group.byte 0x3C3++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH451,Uncommitted Supervisorly Flash 451 In Macro 0"
|
|
group.byte 0x3C4++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH452,Uncommitted Supervisorly Flash 452 In Macro 0"
|
|
group.byte 0x3C5++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH453,Uncommitted Supervisorly Flash 453 In Macro 0"
|
|
group.byte 0x3C6++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH454,Uncommitted Supervisorly Flash 454 In Macro 0"
|
|
group.byte 0x3C7++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH455,Uncommitted Supervisorly Flash 455 In Macro 0"
|
|
group.byte 0x3C8++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH456,Uncommitted Supervisorly Flash 456 In Macro 0"
|
|
group.byte 0x3C9++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH457,Uncommitted Supervisorly Flash 457 In Macro 0"
|
|
group.byte 0x3CA++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH458,Uncommitted Supervisorly Flash 458 In Macro 0"
|
|
group.byte 0x3CB++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH459,Uncommitted Supervisorly Flash 459 In Macro 0"
|
|
group.byte 0x3CC++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH460,Uncommitted Supervisorly Flash 460 In Macro 0"
|
|
group.byte 0x3CD++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH461,Uncommitted Supervisorly Flash 461 In Macro 0"
|
|
group.byte 0x3CE++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH462,Uncommitted Supervisorly Flash 462 In Macro 0"
|
|
group.byte 0x3CF++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH463,Uncommitted Supervisorly Flash 463 In Macro 0"
|
|
group.byte 0x3D0++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH464,Uncommitted Supervisorly Flash 464 In Macro 0"
|
|
group.byte 0x3D1++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH465,Uncommitted Supervisorly Flash 465 In Macro 0"
|
|
group.byte 0x3D2++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH466,Uncommitted Supervisorly Flash 466 In Macro 0"
|
|
group.byte 0x3D3++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH467,Uncommitted Supervisorly Flash 467 In Macro 0"
|
|
group.byte 0x3D4++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH468,Uncommitted Supervisorly Flash 468 In Macro 0"
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH469,Uncommitted Supervisorly Flash 469 In Macro 0"
|
|
group.byte 0x3D6++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH470,Uncommitted Supervisorly Flash 470 In Macro 0"
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH471,Uncommitted Supervisorly Flash 471 In Macro 0"
|
|
group.byte 0x3D8++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH472,Uncommitted Supervisorly Flash 472 In Macro 0"
|
|
group.byte 0x3D9++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH473,Uncommitted Supervisorly Flash 473 In Macro 0"
|
|
group.byte 0x3DA++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH474,Uncommitted Supervisorly Flash 474 In Macro 0"
|
|
group.byte 0x3DB++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH475,Uncommitted Supervisorly Flash 475 In Macro 0"
|
|
group.byte 0x3DC++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH476,Uncommitted Supervisorly Flash 476 In Macro 0"
|
|
group.byte 0x3DD++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH477,Uncommitted Supervisorly Flash 477 In Macro 0"
|
|
group.byte 0x3DE++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH478,Uncommitted Supervisorly Flash 478 In Macro 0"
|
|
group.byte 0x3DF++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH479,Uncommitted Supervisorly Flash 479 In Macro 0"
|
|
group.byte 0x3E0++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH480,Uncommitted Supervisorly Flash 480 In Macro 0"
|
|
group.byte 0x3E1++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH481,Uncommitted Supervisorly Flash 481 In Macro 0"
|
|
group.byte 0x3E2++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH482,Uncommitted Supervisorly Flash 482 In Macro 0"
|
|
group.byte 0x3E3++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH483,Uncommitted Supervisorly Flash 483 In Macro 0"
|
|
group.byte 0x3E4++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH484,Uncommitted Supervisorly Flash 484 In Macro 0"
|
|
group.byte 0x3E5++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH485,Uncommitted Supervisorly Flash 485 In Macro 0"
|
|
group.byte 0x3E6++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH486,Uncommitted Supervisorly Flash 486 In Macro 0"
|
|
group.byte 0x3E7++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH487,Uncommitted Supervisorly Flash 487 In Macro 0"
|
|
group.byte 0x3E8++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH488,Uncommitted Supervisorly Flash 488 In Macro 0"
|
|
group.byte 0x3E9++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH489,Uncommitted Supervisorly Flash 489 In Macro 0"
|
|
group.byte 0x3EA++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH490,Uncommitted Supervisorly Flash 490 In Macro 0"
|
|
group.byte 0x3EB++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH491,Uncommitted Supervisorly Flash 491 In Macro 0"
|
|
group.byte 0x3EC++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH492,Uncommitted Supervisorly Flash 492 In Macro 0"
|
|
group.byte 0x3ED++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH493,Uncommitted Supervisorly Flash 493 In Macro 0"
|
|
group.byte 0x3EE++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH494,Uncommitted Supervisorly Flash 494 In Macro 0"
|
|
group.byte 0x3EF++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH495,Uncommitted Supervisorly Flash 495 In Macro 0"
|
|
group.byte 0x3F0++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH496,Uncommitted Supervisorly Flash 496 In Macro 0"
|
|
group.byte 0x3F1++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH497,Uncommitted Supervisorly Flash 497 In Macro 0"
|
|
group.byte 0x3F2++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH498,Uncommitted Supervisorly Flash 498 In Macro 0"
|
|
group.byte 0x3F3++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH499,Uncommitted Supervisorly Flash 499 In Macro 0"
|
|
group.byte 0x3F4++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH500,Uncommitted Supervisorly Flash 500 In Macro 0"
|
|
group.byte 0x3F5++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH501,Uncommitted Supervisorly Flash 501 In Macro 0"
|
|
group.byte 0x3F6++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH502,Uncommitted Supervisorly Flash 502 In Macro 0"
|
|
group.byte 0x3F7++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH503,Uncommitted Supervisorly Flash 503 In Macro 0"
|
|
group.byte 0x3F8++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH504,Uncommitted Supervisorly Flash 504 In Macro 0"
|
|
group.byte 0x3F9++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH505,Uncommitted Supervisorly Flash 505 In Macro 0"
|
|
group.byte 0x3FA++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH506,Uncommitted Supervisorly Flash 506 In Macro 0"
|
|
group.byte 0x3FB++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH507,Uncommitted Supervisorly Flash 507 In Macro 0"
|
|
group.byte 0x3FC++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH508,Uncommitted Supervisorly Flash 508 In Macro 0"
|
|
group.byte 0x3FD++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH509,Uncommitted Supervisorly Flash 509 In Macro 0"
|
|
group.byte 0x3FE++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH510,Uncommitted Supervisorly Flash 510 In Macro 0"
|
|
group.byte 0x3FF++0x00
|
|
line.byte 0x00 "MACRO_0_FREE_SFLASH511,Uncommitted Supervisorly Flash 511 In Macro 0"
|
|
group.byte 0x400++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW0,Per Page Write Protection 0"
|
|
group.byte 0x401++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW1,Per Page Write Protection 1"
|
|
group.byte 0x402++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW2,Per Page Write Protection 2"
|
|
group.byte 0x403++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW3,Per Page Write Protection 3"
|
|
group.byte 0x404++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW4,Per Page Write Protection 4"
|
|
group.byte 0x405++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW5,Per Page Write Protection 5"
|
|
group.byte 0x406++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW6,Per Page Write Protection 6"
|
|
group.byte 0x407++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW7,Per Page Write Protection 7"
|
|
group.byte 0x408++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW8,Per Page Write Protection 8"
|
|
group.byte 0x409++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW9,Per Page Write Protection 9"
|
|
group.byte 0x40A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW10,Per Page Write Protection 10"
|
|
group.byte 0x40B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW11,Per Page Write Protection 11"
|
|
group.byte 0x40C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW12,Per Page Write Protection 12"
|
|
group.byte 0x40D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW13,Per Page Write Protection 13"
|
|
group.byte 0x40E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW14,Per Page Write Protection 14"
|
|
group.byte 0x40F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW15,Per Page Write Protection 15"
|
|
group.byte 0x410++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW16,Per Page Write Protection 16"
|
|
group.byte 0x411++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW17,Per Page Write Protection 17"
|
|
group.byte 0x412++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW18,Per Page Write Protection 18"
|
|
group.byte 0x413++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW19,Per Page Write Protection 19"
|
|
group.byte 0x414++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW20,Per Page Write Protection 20"
|
|
group.byte 0x415++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW21,Per Page Write Protection 21"
|
|
group.byte 0x416++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW22,Per Page Write Protection 22"
|
|
group.byte 0x417++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW23,Per Page Write Protection 23"
|
|
group.byte 0x418++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW24,Per Page Write Protection 24"
|
|
group.byte 0x419++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW25,Per Page Write Protection 25"
|
|
group.byte 0x41A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW26,Per Page Write Protection 26"
|
|
group.byte 0x41B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW27,Per Page Write Protection 27"
|
|
group.byte 0x41C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW28,Per Page Write Protection 28"
|
|
group.byte 0x41D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW29,Per Page Write Protection 29"
|
|
group.byte 0x41E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW30,Per Page Write Protection 30"
|
|
group.byte 0x41F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW31,Per Page Write Protection 31"
|
|
group.byte 0x420++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW32,Per Page Write Protection 32"
|
|
group.byte 0x421++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW33,Per Page Write Protection 33"
|
|
group.byte 0x422++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW34,Per Page Write Protection 34"
|
|
group.byte 0x423++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW35,Per Page Write Protection 35"
|
|
group.byte 0x424++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW36,Per Page Write Protection 36"
|
|
group.byte 0x425++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW37,Per Page Write Protection 37"
|
|
group.byte 0x426++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW38,Per Page Write Protection 38"
|
|
group.byte 0x427++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW39,Per Page Write Protection 39"
|
|
group.byte 0x428++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW40,Per Page Write Protection 40"
|
|
group.byte 0x429++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW41,Per Page Write Protection 41"
|
|
group.byte 0x42A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW42,Per Page Write Protection 42"
|
|
group.byte 0x42B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW43,Per Page Write Protection 43"
|
|
group.byte 0x42C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW44,Per Page Write Protection 44"
|
|
group.byte 0x42D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW45,Per Page Write Protection 45"
|
|
group.byte 0x42E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW46,Per Page Write Protection 46"
|
|
group.byte 0x42F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW47,Per Page Write Protection 47"
|
|
group.byte 0x430++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW48,Per Page Write Protection 48"
|
|
group.byte 0x431++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW49,Per Page Write Protection 49"
|
|
group.byte 0x432++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW50,Per Page Write Protection 50"
|
|
group.byte 0x433++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW51,Per Page Write Protection 51"
|
|
group.byte 0x434++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW52,Per Page Write Protection 52"
|
|
group.byte 0x435++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW53,Per Page Write Protection 53"
|
|
group.byte 0x436++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW54,Per Page Write Protection 54"
|
|
group.byte 0x437++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW55,Per Page Write Protection 55"
|
|
group.byte 0x438++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW56,Per Page Write Protection 56"
|
|
group.byte 0x439++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW57,Per Page Write Protection 57"
|
|
group.byte 0x43A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW58,Per Page Write Protection 58"
|
|
group.byte 0x43B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW59,Per Page Write Protection 59"
|
|
group.byte 0x43C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW60,Per Page Write Protection 60"
|
|
group.byte 0x43D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW61,Per Page Write Protection 61"
|
|
group.byte 0x43E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW62,Per Page Write Protection 62"
|
|
group.byte 0x43F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW63,Per Page Write Protection 63"
|
|
group.byte 0x440++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW64,Per Page Write Protection 64"
|
|
group.byte 0x441++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW65,Per Page Write Protection 65"
|
|
group.byte 0x442++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW66,Per Page Write Protection 66"
|
|
group.byte 0x443++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW67,Per Page Write Protection 67"
|
|
group.byte 0x444++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW68,Per Page Write Protection 68"
|
|
group.byte 0x445++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW69,Per Page Write Protection 69"
|
|
group.byte 0x446++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW70,Per Page Write Protection 70"
|
|
group.byte 0x447++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW71,Per Page Write Protection 71"
|
|
group.byte 0x448++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW72,Per Page Write Protection 72"
|
|
group.byte 0x449++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW73,Per Page Write Protection 73"
|
|
group.byte 0x44A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW74,Per Page Write Protection 74"
|
|
group.byte 0x44B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW75,Per Page Write Protection 75"
|
|
group.byte 0x44C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW76,Per Page Write Protection 76"
|
|
group.byte 0x44D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW77,Per Page Write Protection 77"
|
|
group.byte 0x44E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW78,Per Page Write Protection 78"
|
|
group.byte 0x44F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW79,Per Page Write Protection 79"
|
|
group.byte 0x450++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW80,Per Page Write Protection 80"
|
|
group.byte 0x451++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW81,Per Page Write Protection 81"
|
|
group.byte 0x452++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW82,Per Page Write Protection 82"
|
|
group.byte 0x453++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW83,Per Page Write Protection 83"
|
|
group.byte 0x454++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW84,Per Page Write Protection 84"
|
|
group.byte 0x455++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW85,Per Page Write Protection 85"
|
|
group.byte 0x456++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW86,Per Page Write Protection 86"
|
|
group.byte 0x457++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW87,Per Page Write Protection 87"
|
|
group.byte 0x458++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW88,Per Page Write Protection 88"
|
|
group.byte 0x459++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW89,Per Page Write Protection 89"
|
|
group.byte 0x45A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW90,Per Page Write Protection 90"
|
|
group.byte 0x45B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW91,Per Page Write Protection 91"
|
|
group.byte 0x45C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW92,Per Page Write Protection 92"
|
|
group.byte 0x45D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW93,Per Page Write Protection 93"
|
|
group.byte 0x45E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW94,Per Page Write Protection 94"
|
|
group.byte 0x45F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW95,Per Page Write Protection 95"
|
|
group.byte 0x460++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW96,Per Page Write Protection 96"
|
|
group.byte 0x461++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW97,Per Page Write Protection 97"
|
|
group.byte 0x462++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW98,Per Page Write Protection 98"
|
|
group.byte 0x463++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW99,Per Page Write Protection 99"
|
|
group.byte 0x464++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW100,Per Page Write Protection 100"
|
|
group.byte 0x465++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW101,Per Page Write Protection 101"
|
|
group.byte 0x466++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW102,Per Page Write Protection 102"
|
|
group.byte 0x467++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW103,Per Page Write Protection 103"
|
|
group.byte 0x468++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW104,Per Page Write Protection 104"
|
|
group.byte 0x469++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW105,Per Page Write Protection 105"
|
|
group.byte 0x46A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW106,Per Page Write Protection 106"
|
|
group.byte 0x46B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW107,Per Page Write Protection 107"
|
|
group.byte 0x46C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW108,Per Page Write Protection 108"
|
|
group.byte 0x46D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW109,Per Page Write Protection 109"
|
|
group.byte 0x46E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW110,Per Page Write Protection 110"
|
|
group.byte 0x46F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW111,Per Page Write Protection 111"
|
|
group.byte 0x470++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW112,Per Page Write Protection 112"
|
|
group.byte 0x471++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW113,Per Page Write Protection 113"
|
|
group.byte 0x472++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW114,Per Page Write Protection 114"
|
|
group.byte 0x473++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW115,Per Page Write Protection 115"
|
|
group.byte 0x474++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW116,Per Page Write Protection 116"
|
|
group.byte 0x475++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW117,Per Page Write Protection 117"
|
|
group.byte 0x476++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW118,Per Page Write Protection 118"
|
|
group.byte 0x477++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW119,Per Page Write Protection 119"
|
|
group.byte 0x478++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW120,Per Page Write Protection 120"
|
|
group.byte 0x479++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW121,Per Page Write Protection 121"
|
|
group.byte 0x47A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW122,Per Page Write Protection 122"
|
|
group.byte 0x47B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW123,Per Page Write Protection 123"
|
|
group.byte 0x47C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW124,Per Page Write Protection 124"
|
|
group.byte 0x47D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW125,Per Page Write Protection 125"
|
|
group.byte 0x47E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW126,Per Page Write Protection 126"
|
|
group.byte 0x47F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW127,Per Page Write Protection 127"
|
|
group.byte 0x480++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW128,Per Page Write Protection 128"
|
|
group.byte 0x481++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW129,Per Page Write Protection 129"
|
|
group.byte 0x482++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW130,Per Page Write Protection 130"
|
|
group.byte 0x483++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW131,Per Page Write Protection 131"
|
|
group.byte 0x484++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW132,Per Page Write Protection 132"
|
|
group.byte 0x485++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW133,Per Page Write Protection 133"
|
|
group.byte 0x486++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW134,Per Page Write Protection 134"
|
|
group.byte 0x487++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW135,Per Page Write Protection 135"
|
|
group.byte 0x488++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW136,Per Page Write Protection 136"
|
|
group.byte 0x489++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW137,Per Page Write Protection 137"
|
|
group.byte 0x48A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW138,Per Page Write Protection 138"
|
|
group.byte 0x48B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW139,Per Page Write Protection 139"
|
|
group.byte 0x48C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW140,Per Page Write Protection 140"
|
|
group.byte 0x48D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW141,Per Page Write Protection 141"
|
|
group.byte 0x48E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW142,Per Page Write Protection 142"
|
|
group.byte 0x48F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW143,Per Page Write Protection 143"
|
|
group.byte 0x490++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW144,Per Page Write Protection 144"
|
|
group.byte 0x491++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW145,Per Page Write Protection 145"
|
|
group.byte 0x492++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW146,Per Page Write Protection 146"
|
|
group.byte 0x493++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW147,Per Page Write Protection 147"
|
|
group.byte 0x494++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW148,Per Page Write Protection 148"
|
|
group.byte 0x495++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW149,Per Page Write Protection 149"
|
|
group.byte 0x496++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW150,Per Page Write Protection 150"
|
|
group.byte 0x497++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW151,Per Page Write Protection 151"
|
|
group.byte 0x498++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW152,Per Page Write Protection 152"
|
|
group.byte 0x499++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW153,Per Page Write Protection 153"
|
|
group.byte 0x49A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW154,Per Page Write Protection 154"
|
|
group.byte 0x49B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW155,Per Page Write Protection 155"
|
|
group.byte 0x49C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW156,Per Page Write Protection 156"
|
|
group.byte 0x49D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW157,Per Page Write Protection 157"
|
|
group.byte 0x49E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW158,Per Page Write Protection 158"
|
|
group.byte 0x49F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW159,Per Page Write Protection 159"
|
|
group.byte 0x4A0++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW160,Per Page Write Protection 160"
|
|
group.byte 0x4A1++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW161,Per Page Write Protection 161"
|
|
group.byte 0x4A2++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW162,Per Page Write Protection 162"
|
|
group.byte 0x4A3++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW163,Per Page Write Protection 163"
|
|
group.byte 0x4A4++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW164,Per Page Write Protection 164"
|
|
group.byte 0x4A5++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW165,Per Page Write Protection 165"
|
|
group.byte 0x4A6++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW166,Per Page Write Protection 166"
|
|
group.byte 0x4A7++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW167,Per Page Write Protection 167"
|
|
group.byte 0x4A8++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW168,Per Page Write Protection 168"
|
|
group.byte 0x4A9++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW169,Per Page Write Protection 169"
|
|
group.byte 0x4AA++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW170,Per Page Write Protection 170"
|
|
group.byte 0x4AB++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW171,Per Page Write Protection 171"
|
|
group.byte 0x4AC++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW172,Per Page Write Protection 172"
|
|
group.byte 0x4AD++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW173,Per Page Write Protection 173"
|
|
group.byte 0x4AE++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW174,Per Page Write Protection 174"
|
|
group.byte 0x4AF++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW175,Per Page Write Protection 175"
|
|
group.byte 0x4B0++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW176,Per Page Write Protection 176"
|
|
group.byte 0x4B1++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW177,Per Page Write Protection 177"
|
|
group.byte 0x4B2++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW178,Per Page Write Protection 178"
|
|
group.byte 0x4B3++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW179,Per Page Write Protection 179"
|
|
group.byte 0x4B4++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW180,Per Page Write Protection 180"
|
|
group.byte 0x4B5++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW181,Per Page Write Protection 181"
|
|
group.byte 0x4B6++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW182,Per Page Write Protection 182"
|
|
group.byte 0x4B7++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW183,Per Page Write Protection 183"
|
|
group.byte 0x4B8++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW184,Per Page Write Protection 184"
|
|
group.byte 0x4B9++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW185,Per Page Write Protection 185"
|
|
group.byte 0x4BA++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW186,Per Page Write Protection 186"
|
|
group.byte 0x4BB++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW187,Per Page Write Protection 187"
|
|
group.byte 0x4BC++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW188,Per Page Write Protection 188"
|
|
group.byte 0x4BD++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW189,Per Page Write Protection 189"
|
|
group.byte 0x4BE++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW190,Per Page Write Protection 190"
|
|
group.byte 0x4BF++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW191,Per Page Write Protection 191"
|
|
group.byte 0x4C0++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW192,Per Page Write Protection 192"
|
|
group.byte 0x4C1++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW193,Per Page Write Protection 193"
|
|
group.byte 0x4C2++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW194,Per Page Write Protection 194"
|
|
group.byte 0x4C3++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW195,Per Page Write Protection 195"
|
|
group.byte 0x4C4++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW196,Per Page Write Protection 196"
|
|
group.byte 0x4C5++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW197,Per Page Write Protection 197"
|
|
group.byte 0x4C6++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW198,Per Page Write Protection 198"
|
|
group.byte 0x4C7++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW199,Per Page Write Protection 199"
|
|
group.byte 0x4C8++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW200,Per Page Write Protection 200"
|
|
group.byte 0x4C9++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW201,Per Page Write Protection 201"
|
|
group.byte 0x4CA++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW202,Per Page Write Protection 202"
|
|
group.byte 0x4CB++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW203,Per Page Write Protection 203"
|
|
group.byte 0x4CC++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW204,Per Page Write Protection 204"
|
|
group.byte 0x4CD++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW205,Per Page Write Protection 205"
|
|
group.byte 0x4CE++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW206,Per Page Write Protection 206"
|
|
group.byte 0x4CF++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW207,Per Page Write Protection 207"
|
|
group.byte 0x4D0++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW208,Per Page Write Protection 208"
|
|
group.byte 0x4D1++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW209,Per Page Write Protection 209"
|
|
group.byte 0x4D2++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW210,Per Page Write Protection 210"
|
|
group.byte 0x4D3++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW211,Per Page Write Protection 211"
|
|
group.byte 0x4D4++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW212,Per Page Write Protection 212"
|
|
group.byte 0x4D5++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW213,Per Page Write Protection 213"
|
|
group.byte 0x4D6++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW214,Per Page Write Protection 214"
|
|
group.byte 0x4D7++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW215,Per Page Write Protection 215"
|
|
group.byte 0x4D8++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW216,Per Page Write Protection 216"
|
|
group.byte 0x4D9++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW217,Per Page Write Protection 217"
|
|
group.byte 0x4DA++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW218,Per Page Write Protection 218"
|
|
group.byte 0x4DB++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW219,Per Page Write Protection 219"
|
|
group.byte 0x4DC++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW220,Per Page Write Protection 220"
|
|
group.byte 0x4DD++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW221,Per Page Write Protection 221"
|
|
group.byte 0x4DE++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW222,Per Page Write Protection 222"
|
|
group.byte 0x4DF++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW223,Per Page Write Protection 223"
|
|
group.byte 0x4E0++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW224,Per Page Write Protection 224"
|
|
group.byte 0x4E1++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW225,Per Page Write Protection 225"
|
|
group.byte 0x4E2++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW226,Per Page Write Protection 226"
|
|
group.byte 0x4E3++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW227,Per Page Write Protection 227"
|
|
group.byte 0x4E4++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW228,Per Page Write Protection 228"
|
|
group.byte 0x4E5++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW229,Per Page Write Protection 229"
|
|
group.byte 0x4E6++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW230,Per Page Write Protection 230"
|
|
group.byte 0x4E7++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW231,Per Page Write Protection 231"
|
|
group.byte 0x4E8++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW232,Per Page Write Protection 232"
|
|
group.byte 0x4E9++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW233,Per Page Write Protection 233"
|
|
group.byte 0x4EA++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW234,Per Page Write Protection 234"
|
|
group.byte 0x4EB++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW235,Per Page Write Protection 235"
|
|
group.byte 0x4EC++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW236,Per Page Write Protection 236"
|
|
group.byte 0x4ED++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW237,Per Page Write Protection 237"
|
|
group.byte 0x4EE++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW238,Per Page Write Protection 238"
|
|
group.byte 0x4EF++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW239,Per Page Write Protection 239"
|
|
group.byte 0x4F0++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW240,Per Page Write Protection 240"
|
|
group.byte 0x4F1++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW241,Per Page Write Protection 241"
|
|
group.byte 0x4F2++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW242,Per Page Write Protection 242"
|
|
group.byte 0x4F3++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW243,Per Page Write Protection 243"
|
|
group.byte 0x4F4++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW244,Per Page Write Protection 244"
|
|
group.byte 0x4F5++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW245,Per Page Write Protection 245"
|
|
group.byte 0x4F6++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW246,Per Page Write Protection 246"
|
|
group.byte 0x4F7++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW247,Per Page Write Protection 247"
|
|
group.byte 0x4F8++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW248,Per Page Write Protection 248"
|
|
group.byte 0x4F9++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW249,Per Page Write Protection 249"
|
|
group.byte 0x4FA++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW250,Per Page Write Protection 250"
|
|
group.byte 0x4FB++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW251,Per Page Write Protection 251"
|
|
group.byte 0x4FC++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW252,Per Page Write Protection 252"
|
|
group.byte 0x4FD++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW253,Per Page Write Protection 253"
|
|
group.byte 0x4FE++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW254,Per Page Write Protection 254"
|
|
group.byte 0x4FF++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW255,Per Page Write Protection 255"
|
|
group.long 0x5A0++0x1B
|
|
line.long 0x00 "ALT_PP,Preprogram Settings"
|
|
bitfld.long 0x00 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
line.long 0x04 "ALT_E,Erase Settings"
|
|
bitfld.long 0x04 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
line.long 0x08 "ALT_P,Program Settings"
|
|
bitfld.long 0x08 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
line.long 0x0C "ALT_EA_E,Erase All - Erase Settings"
|
|
bitfld.long 0x0C 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
line.long 0x10 "ALT_EA_P,Erase All - Program Settings"
|
|
bitfld.long 0x10 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
line.long 0x14 "ALT_ES_E,Erase Sector - Erase Settings"
|
|
bitfld.long 0x14 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
line.long 0x18 "ALT_ES_P_EO,Erase Sector - Program EO Settings"
|
|
bitfld.long 0x18 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
group.byte 0x5BC++0x01
|
|
line.byte 0x00 "E_VCTAT,Bandgap Trim Register"
|
|
bitfld.byte 0x00 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "P_VCTAT,Bandgap Trim Register"
|
|
bitfld.byte 0x01 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3"
|
|
bitfld.byte 0x01 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.byte 0x1BE++0x01
|
|
line.byte 0x00 "IMO_TRIM_USBMODE_24,USB IMO TRIM 24mhz"
|
|
line.byte 0x01 "IMO_TRIM_USBMODE_48,USB IMO TRIM 48mhz"
|
|
group.byte 0x1CC++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT0,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1CD++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT1,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1CE++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT2,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1CF++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT3,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D0++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT4,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D1++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT5,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D2++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT6,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D3++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT7,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D4++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT8,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT9,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D6++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT10,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT11,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D8++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT12,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D9++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT13,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1DA++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT14,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1DB++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT15,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1DC++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT16,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1DD++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT17,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1DE++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT18,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1DF++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT19,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1E0++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT20,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1E1++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT21,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1E2++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT22,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1E3++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT23,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1E4++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT24,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1E5++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT0,IMO Frequency Trim Register"
|
|
group.byte 0x1E6++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT1,IMO Frequency Trim Register"
|
|
group.byte 0x1E7++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT2,IMO Frequency Trim Register"
|
|
group.byte 0x1E8++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT3,IMO Frequency Trim Register"
|
|
group.byte 0x1E9++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT4,IMO Frequency Trim Register"
|
|
group.byte 0x1EA++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT5,IMO Frequency Trim Register"
|
|
group.byte 0x1EB++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT6,IMO Frequency Trim Register"
|
|
group.byte 0x1EC++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT7,IMO Frequency Trim Register"
|
|
group.byte 0x1ED++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT8,IMO Frequency Trim Register"
|
|
group.byte 0x1EE++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT9,IMO Frequency Trim Register"
|
|
group.byte 0x1EF++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT10,IMO Frequency Trim Register"
|
|
group.byte 0x1F0++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT11,IMO Frequency Trim Register"
|
|
group.byte 0x1F1++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT12,IMO Frequency Trim Register"
|
|
group.byte 0x1F2++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT13,IMO Frequency Trim Register"
|
|
group.byte 0x1F3++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT14,IMO Frequency Trim Register"
|
|
group.byte 0x1F4++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT15,IMO Frequency Trim Register"
|
|
group.byte 0x1F5++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT16,IMO Frequency Trim Register"
|
|
group.byte 0x1F6++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT17,IMO Frequency Trim Register"
|
|
group.byte 0x1F7++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT18,IMO Frequency Trim Register"
|
|
group.byte 0x1F8++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT19,IMO Frequency Trim Register"
|
|
group.byte 0x1F9++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT20,IMO Frequency Trim Register"
|
|
group.byte 0x1FA++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT21,IMO Frequency Trim Register"
|
|
group.byte 0x1FB++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT22,IMO Frequency Trim Register"
|
|
group.byte 0x1FC++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT23,IMO Frequency Trim Register"
|
|
group.byte 0x1FD++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT24,IMO Frequency Trim Register"
|
|
group.word 0x1FE++0x01
|
|
line.word 0x00 "CHECKSUM,Boot Checksum"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif cpuis("CY8C4??8*-BL*")
|
|
tree "SFLASH (Supervisory Flash)"
|
|
base ad:0x0FFFF000
|
|
width 35.
|
|
tree "SFLASH_PROT_ROW"
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW0,Per Page Write Protection 0"
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW1,Per Page Write Protection 1"
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW2,Per Page Write Protection 2"
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW3,Per Page Write Protection 3"
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW4,Per Page Write Protection 4"
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW5,Per Page Write Protection 5"
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW6,Per Page Write Protection 6"
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW7,Per Page Write Protection 7"
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW8,Per Page Write Protection 8"
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW9,Per Page Write Protection 9"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW10,Per Page Write Protection 10"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW11,Per Page Write Protection 11"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW12,Per Page Write Protection 12"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW13,Per Page Write Protection 13"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW14,Per Page Write Protection 14"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW15,Per Page Write Protection 15"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW16,Per Page Write Protection 16"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW17,Per Page Write Protection 17"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW18,Per Page Write Protection 18"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW19,Per Page Write Protection 19"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW20,Per Page Write Protection 20"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW21,Per Page Write Protection 21"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW22,Per Page Write Protection 22"
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW23,Per Page Write Protection 23"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW24,Per Page Write Protection 24"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW25,Per Page Write Protection 25"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW26,Per Page Write Protection 26"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW27,Per Page Write Protection 27"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW28,Per Page Write Protection 28"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW29,Per Page Write Protection 29"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW30,Per Page Write Protection 30"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW31,Per Page Write Protection 31"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW32,Per Page Write Protection 32"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW33,Per Page Write Protection 33"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW34,Per Page Write Protection 34"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW35,Per Page Write Protection 35"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW36,Per Page Write Protection 36"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW37,Per Page Write Protection 37"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW38,Per Page Write Protection 38"
|
|
group.byte 0x27++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW39,Per Page Write Protection 39"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW40,Per Page Write Protection 40"
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW41,Per Page Write Protection 41"
|
|
group.byte 0x2A++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW42,Per Page Write Protection 42"
|
|
group.byte 0x2B++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW43,Per Page Write Protection 43"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW44,Per Page Write Protection 44"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW45,Per Page Write Protection 45"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW46,Per Page Write Protection 46"
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW47,Per Page Write Protection 47"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW48,Per Page Write Protection 48"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW49,Per Page Write Protection 49"
|
|
group.byte 0x32++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW50,Per Page Write Protection 50"
|
|
group.byte 0x33++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW51,Per Page Write Protection 51"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW52,Per Page Write Protection 52"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW53,Per Page Write Protection 53"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW54,Per Page Write Protection 54"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW55,Per Page Write Protection 55"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW56,Per Page Write Protection 56"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW57,Per Page Write Protection 57"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW58,Per Page Write Protection 58"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW59,Per Page Write Protection 59"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW60,Per Page Write Protection 60"
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW61,Per Page Write Protection 61"
|
|
group.byte 0x3E++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW62,Per Page Write Protection 62"
|
|
group.byte 0x3F++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW63,Per Page Write Protection 63"
|
|
tree.end
|
|
textline " "
|
|
group.byte 0xFF++0x00
|
|
line.byte 0x00 "SFLASH_PROT_PROTECTION,Protection Level"
|
|
bitfld.byte 0x00 0.--1. " PROT_LEVEL ,Current Protection Mode" "OPEN,VIRGIN,PROTECTED,KILL"
|
|
tree "SFLASH_AV_PAIRS_8B"
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B0,8b Addr/Value pair Section 0"
|
|
group.byte 0x101++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B1,8b Addr/Value pair Section 1"
|
|
group.byte 0x102++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B2,8b Addr/Value pair Section 2"
|
|
group.byte 0x103++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B3,8b Addr/Value pair Section 3"
|
|
group.byte 0x104++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B4,8b Addr/Value pair Section 4"
|
|
group.byte 0x105++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B5,8b Addr/Value pair Section 5"
|
|
group.byte 0x106++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B6,8b Addr/Value pair Section 6"
|
|
group.byte 0x107++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B7,8b Addr/Value pair Section 7"
|
|
group.byte 0x108++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B8,8b Addr/Value pair Section 8"
|
|
group.byte 0x109++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B9,8b Addr/Value pair Section 9"
|
|
group.byte 0x10A++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B10,8b Addr/Value pair Section 10"
|
|
group.byte 0x10B++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B11,8b Addr/Value pair Section 11"
|
|
group.byte 0x10C++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B12,8b Addr/Value pair Section 12"
|
|
group.byte 0x10D++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B13,8b Addr/Value pair Section 13"
|
|
group.byte 0x10E++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B14,8b Addr/Value pair Section 14"
|
|
group.byte 0x10F++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B15,8b Addr/Value pair Section 15"
|
|
group.byte 0x110++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B16,8b Addr/Value pair Section 16"
|
|
group.byte 0x111++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B17,8b Addr/Value pair Section 17"
|
|
group.byte 0x112++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B18,8b Addr/Value pair Section 18"
|
|
group.byte 0x113++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B19,8b Addr/Value pair Section 19"
|
|
group.byte 0x114++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B20,8b Addr/Value pair Section 20"
|
|
group.byte 0x115++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B21,8b Addr/Value pair Section 21"
|
|
group.byte 0x116++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B22,8b Addr/Value pair Section 22"
|
|
group.byte 0x117++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B23,8b Addr/Value pair Section 23"
|
|
group.byte 0x118++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B24,8b Addr/Value pair Section 24"
|
|
group.byte 0x119++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B25,8b Addr/Value pair Section 25"
|
|
group.byte 0x11A++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B26,8b Addr/Value pair Section 26"
|
|
group.byte 0x11B++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B27,8b Addr/Value pair Section 27"
|
|
group.byte 0x11C++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B28,8b Addr/Value pair Section 28"
|
|
group.byte 0x11D++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B29,8b Addr/Value pair Section 29"
|
|
group.byte 0x11E++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B30,8b Addr/Value pair Section 30"
|
|
group.byte 0x11F++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B31,8b Addr/Value pair Section 31"
|
|
group.byte 0x120++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B32,8b Addr/Value pair Section 32"
|
|
group.byte 0x121++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B33,8b Addr/Value pair Section 33"
|
|
group.byte 0x122++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B34,8b Addr/Value pair Section 34"
|
|
group.byte 0x123++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B35,8b Addr/Value pair Section 35"
|
|
group.byte 0x124++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B36,8b Addr/Value pair Section 36"
|
|
group.byte 0x125++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B37,8b Addr/Value pair Section 37"
|
|
group.byte 0x126++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B38,8b Addr/Value pair Section 38"
|
|
group.byte 0x127++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B39,8b Addr/Value pair Section 39"
|
|
group.byte 0x128++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B40,8b Addr/Value pair Section 40"
|
|
group.byte 0x129++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B41,8b Addr/Value pair Section 41"
|
|
group.byte 0x12A++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B42,8b Addr/Value pair Section 42"
|
|
group.byte 0x12B++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B43,8b Addr/Value pair Section 43"
|
|
group.byte 0x12C++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B44,8b Addr/Value pair Section 44"
|
|
group.byte 0x12D++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B45,8b Addr/Value pair Section 45"
|
|
group.byte 0x12E++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B46,8b Addr/Value pair Section 46"
|
|
group.byte 0x12F++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B47,8b Addr/Value pair Section 47"
|
|
group.byte 0x130++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B48,8b Addr/Value pair Section 48"
|
|
group.byte 0x131++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B49,8b Addr/Value pair Section 49"
|
|
group.byte 0x132++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B50,8b Addr/Value pair Section 50"
|
|
group.byte 0x133++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B51,8b Addr/Value pair Section 51"
|
|
group.byte 0x134++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B52,8b Addr/Value pair Section 52"
|
|
group.byte 0x135++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B53,8b Addr/Value pair Section 53"
|
|
group.byte 0x136++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B54,8b Addr/Value pair Section 54"
|
|
group.byte 0x137++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B55,8b Addr/Value pair Section 55"
|
|
group.byte 0x138++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B56,8b Addr/Value pair Section 56"
|
|
group.byte 0x139++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B57,8b Addr/Value pair Section 57"
|
|
group.byte 0x13A++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B58,8b Addr/Value pair Section 58"
|
|
group.byte 0x13B++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B59,8b Addr/Value pair Section 59"
|
|
group.byte 0x13C++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B60,8b Addr/Value pair Section 60"
|
|
group.byte 0x13D++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B61,8b Addr/Value pair Section 61"
|
|
group.byte 0x13E++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B62,8b Addr/Value pair Section 62"
|
|
group.byte 0x13F++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B63,8b Addr/Value pair Section 63"
|
|
group.byte 0x140++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B64,8b Addr/Value pair Section 64"
|
|
group.byte 0x141++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B65,8b Addr/Value pair Section 65"
|
|
group.byte 0x142++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B66,8b Addr/Value pair Section 66"
|
|
group.byte 0x143++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B67,8b Addr/Value pair Section 67"
|
|
group.byte 0x144++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B68,8b Addr/Value pair Section 68"
|
|
group.byte 0x145++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B69,8b Addr/Value pair Section 69"
|
|
group.byte 0x146++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B70,8b Addr/Value pair Section 70"
|
|
group.byte 0x147++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B71,8b Addr/Value pair Section 71"
|
|
group.byte 0x148++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B72,8b Addr/Value pair Section 72"
|
|
group.byte 0x149++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B73,8b Addr/Value pair Section 73"
|
|
group.byte 0x14A++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B74,8b Addr/Value pair Section 74"
|
|
group.byte 0x14B++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B75,8b Addr/Value pair Section 75"
|
|
group.byte 0x14C++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B76,8b Addr/Value pair Section 76"
|
|
group.byte 0x14D++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B77,8b Addr/Value pair Section 77"
|
|
group.byte 0x14E++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B78,8b Addr/Value pair Section 78"
|
|
group.byte 0x14F++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B79,8b Addr/Value pair Section 79"
|
|
group.byte 0x150++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B80,8b Addr/Value pair Section 80"
|
|
group.byte 0x151++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B81,8b Addr/Value pair Section 81"
|
|
group.byte 0x152++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B82,8b Addr/Value pair Section 82"
|
|
group.byte 0x153++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B83,8b Addr/Value pair Section 83"
|
|
group.byte 0x154++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B84,8b Addr/Value pair Section 84"
|
|
group.byte 0x155++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B85,8b Addr/Value pair Section 85"
|
|
group.byte 0x156++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B86,8b Addr/Value pair Section 86"
|
|
group.byte 0x157++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B87,8b Addr/Value pair Section 87"
|
|
group.byte 0x158++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B88,8b Addr/Value pair Section 88"
|
|
group.byte 0x159++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B89,8b Addr/Value pair Section 89"
|
|
group.byte 0x15A++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B90,8b Addr/Value pair Section 90"
|
|
group.byte 0x15B++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B91,8b Addr/Value pair Section 91"
|
|
group.byte 0x15C++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B92,8b Addr/Value pair Section 92"
|
|
group.byte 0x15D++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B93,8b Addr/Value pair Section 93"
|
|
group.byte 0x15E++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B94,8b Addr/Value pair Section 94"
|
|
group.byte 0x15F++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B95,8b Addr/Value pair Section 95"
|
|
group.byte 0x160++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B96,8b Addr/Value pair Section 96"
|
|
group.byte 0x161++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B97,8b Addr/Value pair Section 97"
|
|
group.byte 0x162++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B98,8b Addr/Value pair Section 98"
|
|
group.byte 0x163++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B99,8b Addr/Value pair Section 99"
|
|
group.byte 0x164++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B100,8b Addr/Value pair Section 100"
|
|
group.byte 0x165++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B101,8b Addr/Value pair Section 101"
|
|
group.byte 0x166++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B102,8b Addr/Value pair Section 102"
|
|
group.byte 0x167++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B103,8b Addr/Value pair Section 103"
|
|
group.byte 0x168++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B104,8b Addr/Value pair Section 104"
|
|
group.byte 0x169++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B105,8b Addr/Value pair Section 105"
|
|
group.byte 0x16A++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B106,8b Addr/Value pair Section 106"
|
|
group.byte 0x16B++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B107,8b Addr/Value pair Section 107"
|
|
group.byte 0x16C++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B108,8b Addr/Value pair Section 108"
|
|
group.byte 0x16D++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B109,8b Addr/Value pair Section 109"
|
|
group.byte 0x16E++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B110,8b Addr/Value pair Section 110"
|
|
group.byte 0x16F++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B111,8b Addr/Value pair Section 111"
|
|
group.byte 0x170++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B112,8b Addr/Value pair Section 112"
|
|
group.byte 0x171++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B113,8b Addr/Value pair Section 113"
|
|
group.byte 0x172++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B114,8b Addr/Value pair Section 114"
|
|
group.byte 0x173++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B115,8b Addr/Value pair Section 115"
|
|
group.byte 0x174++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B116,8b Addr/Value pair Section 116"
|
|
group.byte 0x175++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B117,8b Addr/Value pair Section 117"
|
|
group.byte 0x176++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B118,8b Addr/Value pair Section 118"
|
|
group.byte 0x177++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B119,8b Addr/Value pair Section 119"
|
|
group.byte 0x178++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B120,8b Addr/Value pair Section 120"
|
|
group.byte 0x179++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B121,8b Addr/Value pair Section 121"
|
|
group.byte 0x17A++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B122,8b Addr/Value pair Section 122"
|
|
group.byte 0x17B++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B123,8b Addr/Value pair Section 123"
|
|
group.byte 0x17C++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B124,8b Addr/Value pair Section 124"
|
|
group.byte 0x17D++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B125,8b Addr/Value pair Section 125"
|
|
group.byte 0x17E++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B126,8b Addr/Value pair Section 126"
|
|
group.byte 0x17F++0x00
|
|
line.byte 0x00 "SFLASH_AV_PAIRS_8B127,8b Addr/Value pair Section 127"
|
|
tree.end
|
|
textline " "
|
|
tree "SFLASH_AV_PAIRS_32B"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B0,32b Addr/Value pair Section 0"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B1,32b Addr/Value pair Section 1"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B2,32b Addr/Value pair Section 2"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B3,32b Addr/Value pair Section 3"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B4,32b Addr/Value pair Section 4"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B5,32b Addr/Value pair Section 5"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B6,32b Addr/Value pair Section 6"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B7,32b Addr/Value pair Section 7"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B8,32b Addr/Value pair Section 8"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B9,32b Addr/Value pair Section 9"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B10,32b Addr/Value pair Section 10"
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B11,32b Addr/Value pair Section 11"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B12,32b Addr/Value pair Section 12"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B13,32b Addr/Value pair Section 13"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B14,32b Addr/Value pair Section 14"
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "SFLASH_AV_PAIRS_32B15,32b Addr/Value pair Section 15"
|
|
tree.end
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "SFLASH_CPUSS_WOUNDING,CPUSS Wounding Register"
|
|
endif
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "SFLASH_SILICON_ID,Silicon ID"
|
|
hexmask.long.word 0x00 0.--15. 1. " ID ,Silicon ID"
|
|
group.word 0x248++0x0B
|
|
line.word 0x00 "SFLASH_CPUSS_PRIV_RAM,RAM Privileged Limit"
|
|
hexmask.word 0x00 0.--8. 1. " RAM_PROT_LIMIT ,Indicates the limit where the privileged area of SRAM starts in increments of 256 Bytes"
|
|
line.word 0x02 "SFLASH_CPUSS_PRIV_ROM_BROM,Boot ROM Privileged Limit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " BROM_PROT_LIMIT ,Indicates the limit where the privileged area of the Boot ROM partition starts in increments of 256 Bytes"
|
|
line.word 0x04 "SFLASH_CPUSS_PRIV_FLASH,Flash Privileged Limit"
|
|
hexmask.word 0x04 0.--10. 1. " FLASH_PROT_LIMIT ,Indicates the limit where the privileged area of flash starts in increments of 256 Bytes"
|
|
line.word 0x06 "SFLASH_CPUSS_PRIV_ROM_SROM,System ROM Privileged Limit"
|
|
hexmask.word 0x06 0.--9. 1. " SROM_PROT_LIMIT ,Indicates the limit where the privileged area of System ROM partition starts in increments of 256 Bytes"
|
|
line.word 0x08 "SFLASH_HIB_KEY_DELAY,Hibernate wakeup value for PWR_KEY_DELAY"
|
|
hexmask.word 0x08 0.--9. 1. " WAKEUP_HOLDOFF ,Delay to wait for references to settle on wakeup from hibernate/deepsleep"
|
|
line.word 0x0A "SFLASH_DPSLP_KEY_DELAY,DeepSleep wakeup value for PWR_KEY_DELAY"
|
|
hexmask.word 0x0A 0.--9. 1. " WAKEUP_HOLDOFF ,Delay to wait for references to settle on wakeup from hibernate/deepsleep"
|
|
group.byte 0x254++0x01
|
|
line.byte 0x00 "SFLASH_SWD_CONFIG,SWD pinout selector"
|
|
bitfld.byte 0x00 0. " SWD_SELECT ,SWD pinout select bit" "Primary,Alternate"
|
|
line.byte 0x01 "SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0,FLASH IDAC trim used during boot"
|
|
bitfld.byte 0x01 5.--7. " SLOPE ,See SPCIF_TRIM1" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x01 0.--4. " IDAC ,See SPCIF_TRIM1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x258++0x07
|
|
line.long 0x00 "SFLASH_SWD_LISTEN,Listen Window Length"
|
|
line.long 0x04 "SFLASH_FLASH_START,Flash Image Start Address"
|
|
group.byte 0x260++0x03
|
|
line.byte 0x00 "SFLASH_CSD_TRIM1_HVIDAC,CSD Trim Data for HVIDAC operation"
|
|
line.byte 0x01 "SFLASH_CSD_TRIM2_HVIDAC,CSD Trim Data for HVIDAC operation"
|
|
line.byte 0x02 "SFLASH_CSD_TRIM1_CSD,CSD Trim Data for CSD operation"
|
|
line.byte 0x03 "SFLASH_CSD_TRIM2_CSD,CSD Trim Data for CSD operation"
|
|
group.word 0x264++0x03
|
|
line.word 0x00 "SFLASH_SAR_TEMP_MULTIPLIER,SAR Temperature Sensor Multiplication Factor"
|
|
line.word 0x02 "SFLASH_SAR_TEMP_OFFSET,SAR Temperature Sensor Offset"
|
|
group.byte 0x269++0x14
|
|
line.byte 0x00 "SFLASH_SKIP_CHECKSUM,Checksum Skip Option Register"
|
|
line.byte 0x01 "SFLASH_PROT_VIRGINKEY0,Virgin Protection Mode Key 0"
|
|
line.byte 0x02 "SFLASH_PROT_VIRGINKEY1,Virgin Protection Mode Key 1"
|
|
line.byte 0x03 "SFLASH_PROT_VIRGINKEY2,Virgin Protection Mode Key 2"
|
|
line.byte 0x04 "SFLASH_PROT_VIRGINKEY3,Virgin Protection Mode Key 3"
|
|
line.byte 0x05 "SFLASH_PROT_VIRGINKEY4,Virgin Protection Mode Key 4"
|
|
line.byte 0x06 "SFLASH_PROT_VIRGINKEY5,Virgin Protection Mode Key 5"
|
|
line.byte 0x07 "SFLASH_PROT_VIRGINKEY6,Virgin Protection Mode Key 6"
|
|
line.byte 0x08 "SFLASH_PROT_VIRGINKEY7,Virgin Protection Mode Key 7"
|
|
line.byte 0x09 "SFLASH_DIE_LOT0,Lot Number 0"
|
|
line.byte 0x0A "SFLASH_DIE_LOT1,Lot Number 1"
|
|
line.byte 0x0B "SFLASH_DIE_LOT2,Lot Number 2"
|
|
line.byte 0x0C "SFLASH_DIE_WAFER,Wafer Number"
|
|
line.byte 0x0D "SFLASH_DIE_X,X Position on Wafer, CRI Pass/Fail Bin"
|
|
line.byte 0x0E "SFLASH_DIE_Y,Y Position on Wafer, CHI Pass/Fail Bin"
|
|
line.byte 0x0F "SFLASH_DIE_SORT,Sort1/2/3 Pass/Fail Bin"
|
|
bitfld.byte 0x0F 5. " ENG_PASS ,ENG Pass Bin" "Failed,Passed"
|
|
bitfld.byte 0x0F 4. " CHI_PASS ,CHI Pass Bin or Fail Bin" "Failed,Passed"
|
|
bitfld.byte 0x0F 3. " CRI_PASS ,CRI Pass Bin or Fail Bin" "Failed,Passed"
|
|
bitfld.byte 0x0F 2. " S3_PASS ,SORT3 Pass Bin or Fail Bin" "Failed,Passed"
|
|
textline " "
|
|
bitfld.byte 0x0F 1. " S2_PASS ,SORT2 Pass Bin or Fail Bin" "Failed,Passed"
|
|
bitfld.byte 0x0F 0. " S1_PASS ,SORT1 Pass Bin or Fail Bin" "Failed,Passed"
|
|
line.byte 0x10 "SFLASH_DIE_MINOR,Minor Revision Number"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
line.byte 0x11 "SFLASH_CSD1_TRIM1_HVIDAC,CSD1 Trim Data for HVIDAC operation"
|
|
line.byte 0x12 "SFLASH_CSD1_TRIM2_HVIDAC,CSD1 Trim Data for HVIDAC operation"
|
|
line.byte 0x13 "SFLASH_CSD1_TRIM1_CSD,CSD1 Trim Data for (normal) CSD operation"
|
|
line.byte 0x14 "SFLASH_CSD1_TRIM2_CSD,CSD1 Trim Data for (normal) CSD operation"
|
|
endif
|
|
tree "SFLASH_PE_TE_DATA"
|
|
group.byte 0x300++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA0,PE/TE Data 0"
|
|
group.byte 0x301++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA1,PE/TE Data 1"
|
|
group.byte 0x302++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA2,PE/TE Data 2"
|
|
group.byte 0x303++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA3,PE/TE Data 3"
|
|
group.byte 0x304++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA4,PE/TE Data 4"
|
|
group.byte 0x305++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA5,PE/TE Data 5"
|
|
group.byte 0x306++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA6,PE/TE Data 6"
|
|
group.byte 0x307++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA7,PE/TE Data 7"
|
|
group.byte 0x308++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA8,PE/TE Data 8"
|
|
group.byte 0x309++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA9,PE/TE Data 9"
|
|
group.byte 0x30A++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA10,PE/TE Data 10"
|
|
group.byte 0x30B++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA11,PE/TE Data 11"
|
|
group.byte 0x30C++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA12,PE/TE Data 12"
|
|
group.byte 0x30D++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA13,PE/TE Data 13"
|
|
group.byte 0x30E++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA14,PE/TE Data 14"
|
|
group.byte 0x30F++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA15,PE/TE Data 15"
|
|
group.byte 0x310++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA16,PE/TE Data 16"
|
|
group.byte 0x311++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA17,PE/TE Data 17"
|
|
group.byte 0x312++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA18,PE/TE Data 18"
|
|
group.byte 0x313++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA19,PE/TE Data 19"
|
|
group.byte 0x314++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA20,PE/TE Data 20"
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA21,PE/TE Data 21"
|
|
group.byte 0x316++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA22,PE/TE Data 22"
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA23,PE/TE Data 23"
|
|
group.byte 0x318++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA24,PE/TE Data 24"
|
|
group.byte 0x319++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA25,PE/TE Data 25"
|
|
group.byte 0x31A++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA26,PE/TE Data 26"
|
|
group.byte 0x31B++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA27,PE/TE Data 27"
|
|
group.byte 0x31C++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA28,PE/TE Data 28"
|
|
group.byte 0x31D++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA29,PE/TE Data 29"
|
|
group.byte 0x31E++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA30,PE/TE Data 30"
|
|
group.byte 0x31F++0x00
|
|
line.byte 0x00 "SFLASH_PE_TE_DATA31,PE/TE Data 31"
|
|
tree.end
|
|
textline " "
|
|
group.long 0x320++0x1B
|
|
line.long 0x00 "SFLASH_PP,Preprogram Settings"
|
|
bitfld.long 0x00 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x04 "SFLASH_E,Erase Settings"
|
|
bitfld.long 0x04 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x08 "SFLASH_P,Program Settings"
|
|
bitfld.long 0x08 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x0C "SFLASH_EA_E,Erase All - Erase Settings"
|
|
bitfld.long 0x0C 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x10 "SFLASH_EA_P,Erase All - Program Settings"
|
|
bitfld.long 0x10 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x14 "SFLASH_ES_E,Erase Sector - Erase Settings"
|
|
bitfld.long 0x14 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x18 "SFLASH_ES_P_EO,Erase Sector - Program EO Settings"
|
|
bitfld.long 0x18 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
group.byte 0x33C++0x11
|
|
line.byte 0x00 "SFLASH_E_VCTAT,Bandgap Trim Register"
|
|
bitfld.byte 0x00 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SFLASH_P_VCTAT,Bandgap Trim Register"
|
|
bitfld.byte 0x01 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3"
|
|
bitfld.byte 0x01 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x02 "SFLASH_IMO_TRIM_USBMODE_24,USB IMO TRIM 24MHz"
|
|
line.byte 0x03 "SFLASH_IMO_TRIM_USBMODE_48,USB IMO TRIM 48MHz"
|
|
line.byte 0x04 "SFLASH_IMO_MAXF0,Max frequency for trim pair"
|
|
bitfld.byte 0x04 0.--5. " MAXFREQ ,Max frequency at which IMO_ABS/TMPCO3 is valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x05 "SFLASH_IMO_ABS0,Value for PWR_BG_TRIM4"
|
|
bitfld.byte 0x05 0.--5. " ABS_TRIM_IMO ,MO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x06 "SFLASH_IMO_TMPCO0,Value for PWR_BG_TRIM5"
|
|
bitfld.byte 0x06 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x07 "SFLASH_IMO_MAXF1,Max frequency for trim pair"
|
|
bitfld.byte 0x07 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x08 "SFLASH_IMO_ABS1,Value for PWR_BG_TRIM4"
|
|
bitfld.byte 0x08 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x09 "SFLASH_IMO_TMPCO1,Value for PWR_BG_TRIM5"
|
|
bitfld.byte 0x09 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x0A "SFLASH_IMO_MAXF2,Max frequency for trim pair"
|
|
bitfld.byte 0x0A 0.--5. " MAXFREQ ,Max frequency at which IMO_ABS/TMPCO3 is valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x0B "SFLASH_IMO_ABS2,Value for PWR_BG_TRIM4"
|
|
bitfld.byte 0x0B 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x0C "SFLASH_IMO_TMPCO2,Value for PWR_BG_TRIM5"
|
|
bitfld.byte 0x0C 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x0D " SFLASH_IMO_MAXF3,Max frequency for trim pair"
|
|
bitfld.byte 0x0D 0.--5. " MAXFREQ ,Max frequency at which IMO_ABS/TMPCO3 is valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x0E "SFLASH_IMO_ABS3,Value for PWR_BG_TRIM4"
|
|
bitfld.byte 0x0E 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x0F "SFLASH_IMO_TMPCO3,Value for PWR_BG_TRIM5"
|
|
bitfld.byte 0x0F 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x10 "SFLASH_IMO_ABS4,Value for PWR_BG_TRIM4"
|
|
bitfld.byte 0x10 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x11 "SFLASH_IMO_TMPCO4,Value for PWR_BG_TRIM5"
|
|
bitfld.byte 0x11 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
tree "SFLASH_IMO_TRIM"
|
|
group.byte 0x350++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM0,IMO Trim Register 0"
|
|
group.byte 0x351++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM1,IMO Trim Register 1"
|
|
group.byte 0x352++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM2,IMO Trim Register 2"
|
|
group.byte 0x353++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM3,IMO Trim Register 3"
|
|
group.byte 0x354++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM4,IMO Trim Register 4"
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM5,IMO Trim Register 5"
|
|
group.byte 0x356++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM6,IMO Trim Register 6"
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM7,IMO Trim Register 7"
|
|
group.byte 0x358++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM8,IMO Trim Register 8"
|
|
group.byte 0x359++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM9,IMO Trim Register 9"
|
|
group.byte 0x35A++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM10,IMO Trim Register 10"
|
|
group.byte 0x35B++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM11,IMO Trim Register 11"
|
|
group.byte 0x35C++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM12,IMO Trim Register 12"
|
|
group.byte 0x35D++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM13,IMO Trim Register 13"
|
|
group.byte 0x35E++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM14,IMO Trim Register 14"
|
|
group.byte 0x35F++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM15,IMO Trim Register 15"
|
|
group.byte 0x360++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM16,IMO Trim Register 16"
|
|
group.byte 0x361++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM17,IMO Trim Register 17"
|
|
group.byte 0x362++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM18,IMO Trim Register 18"
|
|
group.byte 0x363++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM19,IMO Trim Register 19"
|
|
group.byte 0x364++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM20,IMO Trim Register 20"
|
|
group.byte 0x365++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM21,IMO Trim Register 21"
|
|
group.byte 0x366++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM22,IMO Trim Register 22"
|
|
group.byte 0x367++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM23,IMO Trim Register 23"
|
|
group.byte 0x368++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM24,IMO Trim Register 24"
|
|
group.byte 0x369++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM25,IMO Trim Register 25"
|
|
group.byte 0x36A++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM26,IMO Trim Register 26"
|
|
group.byte 0x36B++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM27,IMO Trim Register 27"
|
|
group.byte 0x36C++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM28,IMO Trim Register 28"
|
|
group.byte 0x36D++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM29,IMO Trim Register 29"
|
|
group.byte 0x36E++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM30,IMO Trim Register 30"
|
|
group.byte 0x36F++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM31,IMO Trim Register 31"
|
|
group.byte 0x370++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM32,IMO Trim Register 32"
|
|
group.byte 0x371++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM33,IMO Trim Register 33"
|
|
group.byte 0x372++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM34,IMO Trim Register 34"
|
|
group.byte 0x373++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM35,IMO Trim Register 35"
|
|
group.byte 0x374++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM36,IMO Trim Register 36"
|
|
group.byte 0x375++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM37,IMO Trim Register 37"
|
|
group.byte 0x376++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM38,IMO Trim Register 38"
|
|
group.byte 0x377++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM39,IMO Trim Register 39"
|
|
group.byte 0x378++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM40,IMO Trim Register 40"
|
|
group.byte 0x379++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM41,IMO Trim Register 41"
|
|
group.byte 0x37A++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM42,IMO Trim Register 42"
|
|
group.byte 0x37B++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM43,IMO Trim Register 43"
|
|
group.byte 0x37C++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM44,IMO Trim Register 44"
|
|
group.byte 0x37D++0x00
|
|
line.byte 0x00 "SFLASH_IMO_TRIM45,IMO Trim Register 45"
|
|
tree.end
|
|
textline " "
|
|
group.word 0x3FE++0x01
|
|
line.word 0x00 "SFLASH_CHECKSUM,Boot Checksum"
|
|
tree "SFLASH_MACRO_0_FREE_SFLASH"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.byte 0x400++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH0,Uncommitted Supervisorly Flash in Macro 0"
|
|
group.byte 0x401++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1,Uncommitted Supervisorly Flash in Macro 1"
|
|
group.byte 0x402++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH2,Uncommitted Supervisorly Flash in Macro 2"
|
|
group.byte 0x403++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH3,Uncommitted Supervisorly Flash in Macro 3"
|
|
group.byte 0x404++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH4,Uncommitted Supervisorly Flash in Macro 4"
|
|
group.byte 0x405++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH5,Uncommitted Supervisorly Flash in Macro 5"
|
|
group.byte 0x406++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH6,Uncommitted Supervisorly Flash in Macro 6"
|
|
group.byte 0x407++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH7,Uncommitted Supervisorly Flash in Macro 7"
|
|
group.byte 0x408++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH8,Uncommitted Supervisorly Flash in Macro 8"
|
|
group.byte 0x409++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH9,Uncommitted Supervisorly Flash in Macro 9"
|
|
group.byte 0x40A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH10,Uncommitted Supervisorly Flash in Macro 10"
|
|
group.byte 0x40B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH11,Uncommitted Supervisorly Flash in Macro 11"
|
|
group.byte 0x40C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH12,Uncommitted Supervisorly Flash in Macro 12"
|
|
group.byte 0x40D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH13,Uncommitted Supervisorly Flash in Macro 13"
|
|
group.byte 0x40E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH14,Uncommitted Supervisorly Flash in Macro 14"
|
|
group.byte 0x40F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH15,Uncommitted Supervisorly Flash in Macro 15"
|
|
group.byte 0x410++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH16,Uncommitted Supervisorly Flash in Macro 16"
|
|
group.byte 0x411++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH17,Uncommitted Supervisorly Flash in Macro 17"
|
|
group.byte 0x412++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH18,Uncommitted Supervisorly Flash in Macro 18"
|
|
group.byte 0x413++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH19,Uncommitted Supervisorly Flash in Macro 19"
|
|
group.byte 0x414++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH20,Uncommitted Supervisorly Flash in Macro 20"
|
|
group.byte 0x415++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH21,Uncommitted Supervisorly Flash in Macro 21"
|
|
group.byte 0x416++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH22,Uncommitted Supervisorly Flash in Macro 22"
|
|
group.byte 0x417++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH23,Uncommitted Supervisorly Flash in Macro 23"
|
|
group.byte 0x418++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH24,Uncommitted Supervisorly Flash in Macro 24"
|
|
group.byte 0x419++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH25,Uncommitted Supervisorly Flash in Macro 25"
|
|
group.byte 0x41A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH26,Uncommitted Supervisorly Flash in Macro 26"
|
|
group.byte 0x41B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH27,Uncommitted Supervisorly Flash in Macro 27"
|
|
group.byte 0x41C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH28,Uncommitted Supervisorly Flash in Macro 28"
|
|
group.byte 0x41D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH29,Uncommitted Supervisorly Flash in Macro 29"
|
|
group.byte 0x41E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH30,Uncommitted Supervisorly Flash in Macro 30"
|
|
group.byte 0x41F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH31,Uncommitted Supervisorly Flash in Macro 31"
|
|
group.byte 0x420++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH32,Uncommitted Supervisorly Flash in Macro 32"
|
|
group.byte 0x421++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH33,Uncommitted Supervisorly Flash in Macro 33"
|
|
group.byte 0x422++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH34,Uncommitted Supervisorly Flash in Macro 34"
|
|
group.byte 0x423++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH35,Uncommitted Supervisorly Flash in Macro 35"
|
|
group.byte 0x424++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH36,Uncommitted Supervisorly Flash in Macro 36"
|
|
group.byte 0x425++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH37,Uncommitted Supervisorly Flash in Macro 37"
|
|
group.byte 0x426++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH38,Uncommitted Supervisorly Flash in Macro 38"
|
|
group.byte 0x427++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH39,Uncommitted Supervisorly Flash in Macro 39"
|
|
group.byte 0x428++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH40,Uncommitted Supervisorly Flash in Macro 40"
|
|
group.byte 0x429++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH41,Uncommitted Supervisorly Flash in Macro 41"
|
|
group.byte 0x42A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH42,Uncommitted Supervisorly Flash in Macro 42"
|
|
group.byte 0x42B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH43,Uncommitted Supervisorly Flash in Macro 43"
|
|
group.byte 0x42C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH44,Uncommitted Supervisorly Flash in Macro 44"
|
|
group.byte 0x42D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH45,Uncommitted Supervisorly Flash in Macro 45"
|
|
group.byte 0x42E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH46,Uncommitted Supervisorly Flash in Macro 46"
|
|
group.byte 0x42F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH47,Uncommitted Supervisorly Flash in Macro 47"
|
|
group.byte 0x430++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH48,Uncommitted Supervisorly Flash in Macro 48"
|
|
group.byte 0x431++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH49,Uncommitted Supervisorly Flash in Macro 49"
|
|
group.byte 0x432++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH50,Uncommitted Supervisorly Flash in Macro 50"
|
|
group.byte 0x433++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH51,Uncommitted Supervisorly Flash in Macro 51"
|
|
group.byte 0x434++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH52,Uncommitted Supervisorly Flash in Macro 52"
|
|
group.byte 0x435++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH53,Uncommitted Supervisorly Flash in Macro 53"
|
|
group.byte 0x436++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH54,Uncommitted Supervisorly Flash in Macro 54"
|
|
group.byte 0x437++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH55,Uncommitted Supervisorly Flash in Macro 55"
|
|
group.byte 0x438++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH56,Uncommitted Supervisorly Flash in Macro 56"
|
|
group.byte 0x439++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH57,Uncommitted Supervisorly Flash in Macro 57"
|
|
group.byte 0x43A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH58,Uncommitted Supervisorly Flash in Macro 58"
|
|
group.byte 0x43B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH59,Uncommitted Supervisorly Flash in Macro 59"
|
|
group.byte 0x43C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH60,Uncommitted Supervisorly Flash in Macro 60"
|
|
group.byte 0x43D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH61,Uncommitted Supervisorly Flash in Macro 61"
|
|
group.byte 0x43E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH62,Uncommitted Supervisorly Flash in Macro 62"
|
|
group.byte 0x43F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH63,Uncommitted Supervisorly Flash in Macro 63"
|
|
group.byte 0x440++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH64,Uncommitted Supervisorly Flash in Macro 64"
|
|
group.byte 0x441++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH65,Uncommitted Supervisorly Flash in Macro 65"
|
|
group.byte 0x442++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH66,Uncommitted Supervisorly Flash in Macro 66"
|
|
group.byte 0x443++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH67,Uncommitted Supervisorly Flash in Macro 67"
|
|
group.byte 0x444++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH68,Uncommitted Supervisorly Flash in Macro 68"
|
|
group.byte 0x445++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH69,Uncommitted Supervisorly Flash in Macro 69"
|
|
group.byte 0x446++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH70,Uncommitted Supervisorly Flash in Macro 70"
|
|
group.byte 0x447++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH71,Uncommitted Supervisorly Flash in Macro 71"
|
|
group.byte 0x448++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH72,Uncommitted Supervisorly Flash in Macro 72"
|
|
group.byte 0x449++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH73,Uncommitted Supervisorly Flash in Macro 73"
|
|
group.byte 0x44A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH74,Uncommitted Supervisorly Flash in Macro 74"
|
|
group.byte 0x44B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH75,Uncommitted Supervisorly Flash in Macro 75"
|
|
group.byte 0x44C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH76,Uncommitted Supervisorly Flash in Macro 76"
|
|
group.byte 0x44D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH77,Uncommitted Supervisorly Flash in Macro 77"
|
|
group.byte 0x44E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH78,Uncommitted Supervisorly Flash in Macro 78"
|
|
group.byte 0x44F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH79,Uncommitted Supervisorly Flash in Macro 79"
|
|
group.byte 0x450++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH80,Uncommitted Supervisorly Flash in Macro 80"
|
|
group.byte 0x451++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH81,Uncommitted Supervisorly Flash in Macro 81"
|
|
group.byte 0x452++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH82,Uncommitted Supervisorly Flash in Macro 82"
|
|
group.byte 0x453++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH83,Uncommitted Supervisorly Flash in Macro 83"
|
|
group.byte 0x454++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH84,Uncommitted Supervisorly Flash in Macro 84"
|
|
group.byte 0x455++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH85,Uncommitted Supervisorly Flash in Macro 85"
|
|
group.byte 0x456++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH86,Uncommitted Supervisorly Flash in Macro 86"
|
|
group.byte 0x457++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH87,Uncommitted Supervisorly Flash in Macro 87"
|
|
group.byte 0x458++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH88,Uncommitted Supervisorly Flash in Macro 88"
|
|
group.byte 0x459++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH89,Uncommitted Supervisorly Flash in Macro 89"
|
|
group.byte 0x45A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH90,Uncommitted Supervisorly Flash in Macro 90"
|
|
group.byte 0x45B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH91,Uncommitted Supervisorly Flash in Macro 91"
|
|
group.byte 0x45C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH92,Uncommitted Supervisorly Flash in Macro 92"
|
|
group.byte 0x45D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH93,Uncommitted Supervisorly Flash in Macro 93"
|
|
group.byte 0x45E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH94,Uncommitted Supervisorly Flash in Macro 94"
|
|
group.byte 0x45F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH95,Uncommitted Supervisorly Flash in Macro 95"
|
|
group.byte 0x460++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH96,Uncommitted Supervisorly Flash in Macro 96"
|
|
group.byte 0x461++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH97,Uncommitted Supervisorly Flash in Macro 97"
|
|
group.byte 0x462++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH98,Uncommitted Supervisorly Flash in Macro 98"
|
|
group.byte 0x463++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH99,Uncommitted Supervisorly Flash in Macro 99"
|
|
group.byte 0x464++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH100,Uncommitted Supervisorly Flash in Macro 100"
|
|
group.byte 0x465++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH101,Uncommitted Supervisorly Flash in Macro 101"
|
|
group.byte 0x466++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH102,Uncommitted Supervisorly Flash in Macro 102"
|
|
group.byte 0x467++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH103,Uncommitted Supervisorly Flash in Macro 103"
|
|
group.byte 0x468++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH104,Uncommitted Supervisorly Flash in Macro 104"
|
|
group.byte 0x469++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH105,Uncommitted Supervisorly Flash in Macro 105"
|
|
group.byte 0x46A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH106,Uncommitted Supervisorly Flash in Macro 106"
|
|
group.byte 0x46B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH107,Uncommitted Supervisorly Flash in Macro 107"
|
|
group.byte 0x46C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH108,Uncommitted Supervisorly Flash in Macro 108"
|
|
group.byte 0x46D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH109,Uncommitted Supervisorly Flash in Macro 109"
|
|
group.byte 0x46E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH110,Uncommitted Supervisorly Flash in Macro 110"
|
|
group.byte 0x46F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH111,Uncommitted Supervisorly Flash in Macro 111"
|
|
group.byte 0x470++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH112,Uncommitted Supervisorly Flash in Macro 112"
|
|
group.byte 0x471++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH113,Uncommitted Supervisorly Flash in Macro 113"
|
|
group.byte 0x472++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH114,Uncommitted Supervisorly Flash in Macro 114"
|
|
group.byte 0x473++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH115,Uncommitted Supervisorly Flash in Macro 115"
|
|
group.byte 0x474++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH116,Uncommitted Supervisorly Flash in Macro 116"
|
|
group.byte 0x475++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH117,Uncommitted Supervisorly Flash in Macro 117"
|
|
group.byte 0x476++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH118,Uncommitted Supervisorly Flash in Macro 118"
|
|
group.byte 0x477++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH119,Uncommitted Supervisorly Flash in Macro 119"
|
|
group.byte 0x478++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH120,Uncommitted Supervisorly Flash in Macro 120"
|
|
group.byte 0x479++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH121,Uncommitted Supervisorly Flash in Macro 121"
|
|
group.byte 0x47A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH122,Uncommitted Supervisorly Flash in Macro 122"
|
|
group.byte 0x47B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH123,Uncommitted Supervisorly Flash in Macro 123"
|
|
group.byte 0x47C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH124,Uncommitted Supervisorly Flash in Macro 124"
|
|
group.byte 0x47D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH125,Uncommitted Supervisorly Flash in Macro 125"
|
|
group.byte 0x47E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH126,Uncommitted Supervisorly Flash in Macro 126"
|
|
group.byte 0x47F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH127,Uncommitted Supervisorly Flash in Macro 127"
|
|
group.byte 0x480++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH128,Uncommitted Supervisorly Flash in Macro 128"
|
|
group.byte 0x481++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH129,Uncommitted Supervisorly Flash in Macro 129"
|
|
group.byte 0x482++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH130,Uncommitted Supervisorly Flash in Macro 130"
|
|
group.byte 0x483++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH131,Uncommitted Supervisorly Flash in Macro 131"
|
|
group.byte 0x484++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH132,Uncommitted Supervisorly Flash in Macro 132"
|
|
group.byte 0x485++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH133,Uncommitted Supervisorly Flash in Macro 133"
|
|
group.byte 0x486++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH134,Uncommitted Supervisorly Flash in Macro 134"
|
|
group.byte 0x487++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH135,Uncommitted Supervisorly Flash in Macro 135"
|
|
group.byte 0x488++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH136,Uncommitted Supervisorly Flash in Macro 136"
|
|
group.byte 0x489++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH137,Uncommitted Supervisorly Flash in Macro 137"
|
|
group.byte 0x48A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH138,Uncommitted Supervisorly Flash in Macro 138"
|
|
group.byte 0x48B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH139,Uncommitted Supervisorly Flash in Macro 139"
|
|
group.byte 0x48C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH140,Uncommitted Supervisorly Flash in Macro 140"
|
|
group.byte 0x48D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH141,Uncommitted Supervisorly Flash in Macro 141"
|
|
group.byte 0x48E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH142,Uncommitted Supervisorly Flash in Macro 142"
|
|
group.byte 0x48F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH143,Uncommitted Supervisorly Flash in Macro 143"
|
|
group.byte 0x490++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH144,Uncommitted Supervisorly Flash in Macro 144"
|
|
group.byte 0x491++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH145,Uncommitted Supervisorly Flash in Macro 145"
|
|
group.byte 0x492++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH146,Uncommitted Supervisorly Flash in Macro 146"
|
|
group.byte 0x493++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH147,Uncommitted Supervisorly Flash in Macro 147"
|
|
group.byte 0x494++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH148,Uncommitted Supervisorly Flash in Macro 148"
|
|
group.byte 0x495++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH149,Uncommitted Supervisorly Flash in Macro 149"
|
|
group.byte 0x496++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH150,Uncommitted Supervisorly Flash in Macro 150"
|
|
group.byte 0x497++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH151,Uncommitted Supervisorly Flash in Macro 151"
|
|
group.byte 0x498++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH152,Uncommitted Supervisorly Flash in Macro 152"
|
|
group.byte 0x499++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH153,Uncommitted Supervisorly Flash in Macro 153"
|
|
group.byte 0x49A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH154,Uncommitted Supervisorly Flash in Macro 154"
|
|
group.byte 0x49B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH155,Uncommitted Supervisorly Flash in Macro 155"
|
|
group.byte 0x49C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH156,Uncommitted Supervisorly Flash in Macro 156"
|
|
group.byte 0x49D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH157,Uncommitted Supervisorly Flash in Macro 157"
|
|
group.byte 0x49E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH158,Uncommitted Supervisorly Flash in Macro 158"
|
|
group.byte 0x49F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH159,Uncommitted Supervisorly Flash in Macro 159"
|
|
group.byte 0x4A0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH160,Uncommitted Supervisorly Flash in Macro 160"
|
|
group.byte 0x4A1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH161,Uncommitted Supervisorly Flash in Macro 161"
|
|
group.byte 0x4A2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH162,Uncommitted Supervisorly Flash in Macro 162"
|
|
group.byte 0x4A3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH163,Uncommitted Supervisorly Flash in Macro 163"
|
|
group.byte 0x4A4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH164,Uncommitted Supervisorly Flash in Macro 164"
|
|
group.byte 0x4A5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH165,Uncommitted Supervisorly Flash in Macro 165"
|
|
group.byte 0x4A6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH166,Uncommitted Supervisorly Flash in Macro 166"
|
|
group.byte 0x4A7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH167,Uncommitted Supervisorly Flash in Macro 167"
|
|
group.byte 0x4A8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH168,Uncommitted Supervisorly Flash in Macro 168"
|
|
group.byte 0x4A9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH169,Uncommitted Supervisorly Flash in Macro 169"
|
|
group.byte 0x4AA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH170,Uncommitted Supervisorly Flash in Macro 170"
|
|
group.byte 0x4AB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH171,Uncommitted Supervisorly Flash in Macro 171"
|
|
group.byte 0x4AC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH172,Uncommitted Supervisorly Flash in Macro 172"
|
|
group.byte 0x4AD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH173,Uncommitted Supervisorly Flash in Macro 173"
|
|
group.byte 0x4AE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH174,Uncommitted Supervisorly Flash in Macro 174"
|
|
group.byte 0x4AF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH175,Uncommitted Supervisorly Flash in Macro 175"
|
|
group.byte 0x4B0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH176,Uncommitted Supervisorly Flash in Macro 176"
|
|
group.byte 0x4B1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH177,Uncommitted Supervisorly Flash in Macro 177"
|
|
group.byte 0x4B2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH178,Uncommitted Supervisorly Flash in Macro 178"
|
|
group.byte 0x4B3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH179,Uncommitted Supervisorly Flash in Macro 179"
|
|
group.byte 0x4B4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH180,Uncommitted Supervisorly Flash in Macro 180"
|
|
group.byte 0x4B5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH181,Uncommitted Supervisorly Flash in Macro 181"
|
|
group.byte 0x4B6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH182,Uncommitted Supervisorly Flash in Macro 182"
|
|
group.byte 0x4B7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH183,Uncommitted Supervisorly Flash in Macro 183"
|
|
group.byte 0x4B8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH184,Uncommitted Supervisorly Flash in Macro 184"
|
|
group.byte 0x4B9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH185,Uncommitted Supervisorly Flash in Macro 185"
|
|
group.byte 0x4BA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH186,Uncommitted Supervisorly Flash in Macro 186"
|
|
group.byte 0x4BB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH187,Uncommitted Supervisorly Flash in Macro 187"
|
|
group.byte 0x4BC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH188,Uncommitted Supervisorly Flash in Macro 188"
|
|
group.byte 0x4BD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH189,Uncommitted Supervisorly Flash in Macro 189"
|
|
group.byte 0x4BE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH190,Uncommitted Supervisorly Flash in Macro 190"
|
|
group.byte 0x4BF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH191,Uncommitted Supervisorly Flash in Macro 191"
|
|
group.byte 0x4C0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH192,Uncommitted Supervisorly Flash in Macro 192"
|
|
group.byte 0x4C1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH193,Uncommitted Supervisorly Flash in Macro 193"
|
|
group.byte 0x4C2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH194,Uncommitted Supervisorly Flash in Macro 194"
|
|
group.byte 0x4C3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH195,Uncommitted Supervisorly Flash in Macro 195"
|
|
group.byte 0x4C4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH196,Uncommitted Supervisorly Flash in Macro 196"
|
|
group.byte 0x4C5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH197,Uncommitted Supervisorly Flash in Macro 197"
|
|
group.byte 0x4C6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH198,Uncommitted Supervisorly Flash in Macro 198"
|
|
group.byte 0x4C7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH199,Uncommitted Supervisorly Flash in Macro 199"
|
|
group.byte 0x4C8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH200,Uncommitted Supervisorly Flash in Macro 200"
|
|
group.byte 0x4C9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH201,Uncommitted Supervisorly Flash in Macro 201"
|
|
group.byte 0x4CA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH202,Uncommitted Supervisorly Flash in Macro 202"
|
|
group.byte 0x4CB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH203,Uncommitted Supervisorly Flash in Macro 203"
|
|
group.byte 0x4CC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH204,Uncommitted Supervisorly Flash in Macro 204"
|
|
group.byte 0x4CD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH205,Uncommitted Supervisorly Flash in Macro 205"
|
|
group.byte 0x4CE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH206,Uncommitted Supervisorly Flash in Macro 206"
|
|
group.byte 0x4CF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH207,Uncommitted Supervisorly Flash in Macro 207"
|
|
group.byte 0x4D0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH208,Uncommitted Supervisorly Flash in Macro 208"
|
|
group.byte 0x4D1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH209,Uncommitted Supervisorly Flash in Macro 209"
|
|
group.byte 0x4D2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH210,Uncommitted Supervisorly Flash in Macro 210"
|
|
group.byte 0x4D3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH211,Uncommitted Supervisorly Flash in Macro 211"
|
|
group.byte 0x4D4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH212,Uncommitted Supervisorly Flash in Macro 212"
|
|
group.byte 0x4D5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH213,Uncommitted Supervisorly Flash in Macro 213"
|
|
group.byte 0x4D6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH214,Uncommitted Supervisorly Flash in Macro 214"
|
|
group.byte 0x4D7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH215,Uncommitted Supervisorly Flash in Macro 215"
|
|
group.byte 0x4D8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH216,Uncommitted Supervisorly Flash in Macro 216"
|
|
group.byte 0x4D9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH217,Uncommitted Supervisorly Flash in Macro 217"
|
|
group.byte 0x4DA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH218,Uncommitted Supervisorly Flash in Macro 218"
|
|
group.byte 0x4DB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH219,Uncommitted Supervisorly Flash in Macro 219"
|
|
group.byte 0x4DC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH220,Uncommitted Supervisorly Flash in Macro 220"
|
|
group.byte 0x4DD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH221,Uncommitted Supervisorly Flash in Macro 221"
|
|
group.byte 0x4DE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH222,Uncommitted Supervisorly Flash in Macro 222"
|
|
group.byte 0x4DF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH223,Uncommitted Supervisorly Flash in Macro 223"
|
|
group.byte 0x4E0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH224,Uncommitted Supervisorly Flash in Macro 224"
|
|
group.byte 0x4E1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH225,Uncommitted Supervisorly Flash in Macro 225"
|
|
group.byte 0x4E2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH226,Uncommitted Supervisorly Flash in Macro 226"
|
|
group.byte 0x4E3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH227,Uncommitted Supervisorly Flash in Macro 227"
|
|
group.byte 0x4E4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH228,Uncommitted Supervisorly Flash in Macro 228"
|
|
group.byte 0x4E5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH229,Uncommitted Supervisorly Flash in Macro 229"
|
|
group.byte 0x4E6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH230,Uncommitted Supervisorly Flash in Macro 230"
|
|
group.byte 0x4E7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH231,Uncommitted Supervisorly Flash in Macro 231"
|
|
group.byte 0x4E8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH232,Uncommitted Supervisorly Flash in Macro 232"
|
|
group.byte 0x4E9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH233,Uncommitted Supervisorly Flash in Macro 233"
|
|
group.byte 0x4EA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH234,Uncommitted Supervisorly Flash in Macro 234"
|
|
group.byte 0x4EB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH235,Uncommitted Supervisorly Flash in Macro 235"
|
|
group.byte 0x4EC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH236,Uncommitted Supervisorly Flash in Macro 236"
|
|
group.byte 0x4ED++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH237,Uncommitted Supervisorly Flash in Macro 237"
|
|
group.byte 0x4EE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH238,Uncommitted Supervisorly Flash in Macro 238"
|
|
group.byte 0x4EF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH239,Uncommitted Supervisorly Flash in Macro 239"
|
|
group.byte 0x4F0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH240,Uncommitted Supervisorly Flash in Macro 240"
|
|
group.byte 0x4F1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH241,Uncommitted Supervisorly Flash in Macro 241"
|
|
group.byte 0x4F2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH242,Uncommitted Supervisorly Flash in Macro 242"
|
|
group.byte 0x4F3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH243,Uncommitted Supervisorly Flash in Macro 243"
|
|
group.byte 0x4F4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH244,Uncommitted Supervisorly Flash in Macro 244"
|
|
group.byte 0x4F5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH245,Uncommitted Supervisorly Flash in Macro 245"
|
|
group.byte 0x4F6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH246,Uncommitted Supervisorly Flash in Macro 246"
|
|
group.byte 0x4F7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH247,Uncommitted Supervisorly Flash in Macro 247"
|
|
group.byte 0x4F8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH248,Uncommitted Supervisorly Flash in Macro 248"
|
|
group.byte 0x4F9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH249,Uncommitted Supervisorly Flash in Macro 249"
|
|
group.byte 0x4FA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH250,Uncommitted Supervisorly Flash in Macro 250"
|
|
group.byte 0x4FB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH251,Uncommitted Supervisorly Flash in Macro 251"
|
|
group.byte 0x4FC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH252,Uncommitted Supervisorly Flash in Macro 252"
|
|
group.byte 0x4FD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH253,Uncommitted Supervisorly Flash in Macro 253"
|
|
group.byte 0x4FE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH254,Uncommitted Supervisorly Flash in Macro 254"
|
|
group.byte 0x4FF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH255,Uncommitted Supervisorly Flash in Macro 255"
|
|
group.byte 0x500++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH256,Uncommitted Supervisorly Flash in Macro 256"
|
|
group.byte 0x501++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH257,Uncommitted Supervisorly Flash in Macro 257"
|
|
group.byte 0x502++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH258,Uncommitted Supervisorly Flash in Macro 258"
|
|
group.byte 0x503++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH259,Uncommitted Supervisorly Flash in Macro 259"
|
|
group.byte 0x504++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH260,Uncommitted Supervisorly Flash in Macro 260"
|
|
group.byte 0x505++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH261,Uncommitted Supervisorly Flash in Macro 261"
|
|
group.byte 0x506++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH262,Uncommitted Supervisorly Flash in Macro 262"
|
|
group.byte 0x507++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH263,Uncommitted Supervisorly Flash in Macro 263"
|
|
group.byte 0x508++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH264,Uncommitted Supervisorly Flash in Macro 264"
|
|
group.byte 0x509++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH265,Uncommitted Supervisorly Flash in Macro 265"
|
|
group.byte 0x50A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH266,Uncommitted Supervisorly Flash in Macro 266"
|
|
group.byte 0x50B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH267,Uncommitted Supervisorly Flash in Macro 267"
|
|
group.byte 0x50C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH268,Uncommitted Supervisorly Flash in Macro 268"
|
|
group.byte 0x50D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH269,Uncommitted Supervisorly Flash in Macro 269"
|
|
group.byte 0x50E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH270,Uncommitted Supervisorly Flash in Macro 270"
|
|
group.byte 0x50F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH271,Uncommitted Supervisorly Flash in Macro 271"
|
|
group.byte 0x510++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH272,Uncommitted Supervisorly Flash in Macro 272"
|
|
group.byte 0x511++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH273,Uncommitted Supervisorly Flash in Macro 273"
|
|
group.byte 0x512++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH274,Uncommitted Supervisorly Flash in Macro 274"
|
|
group.byte 0x513++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH275,Uncommitted Supervisorly Flash in Macro 275"
|
|
group.byte 0x514++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH276,Uncommitted Supervisorly Flash in Macro 276"
|
|
group.byte 0x515++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH277,Uncommitted Supervisorly Flash in Macro 277"
|
|
group.byte 0x516++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH278,Uncommitted Supervisorly Flash in Macro 278"
|
|
group.byte 0x517++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH279,Uncommitted Supervisorly Flash in Macro 279"
|
|
group.byte 0x518++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH280,Uncommitted Supervisorly Flash in Macro 280"
|
|
group.byte 0x519++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH281,Uncommitted Supervisorly Flash in Macro 281"
|
|
group.byte 0x51A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH282,Uncommitted Supervisorly Flash in Macro 282"
|
|
group.byte 0x51B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH283,Uncommitted Supervisorly Flash in Macro 283"
|
|
group.byte 0x51C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH284,Uncommitted Supervisorly Flash in Macro 284"
|
|
group.byte 0x51D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH285,Uncommitted Supervisorly Flash in Macro 285"
|
|
group.byte 0x51E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH286,Uncommitted Supervisorly Flash in Macro 286"
|
|
group.byte 0x51F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH287,Uncommitted Supervisorly Flash in Macro 287"
|
|
group.byte 0x520++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH288,Uncommitted Supervisorly Flash in Macro 288"
|
|
group.byte 0x521++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH289,Uncommitted Supervisorly Flash in Macro 289"
|
|
group.byte 0x522++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH290,Uncommitted Supervisorly Flash in Macro 290"
|
|
group.byte 0x523++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH291,Uncommitted Supervisorly Flash in Macro 291"
|
|
group.byte 0x524++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH292,Uncommitted Supervisorly Flash in Macro 292"
|
|
group.byte 0x525++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH293,Uncommitted Supervisorly Flash in Macro 293"
|
|
group.byte 0x526++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH294,Uncommitted Supervisorly Flash in Macro 294"
|
|
group.byte 0x527++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH295,Uncommitted Supervisorly Flash in Macro 295"
|
|
group.byte 0x528++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH296,Uncommitted Supervisorly Flash in Macro 296"
|
|
group.byte 0x529++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH297,Uncommitted Supervisorly Flash in Macro 297"
|
|
group.byte 0x52A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH298,Uncommitted Supervisorly Flash in Macro 298"
|
|
group.byte 0x52B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH299,Uncommitted Supervisorly Flash in Macro 299"
|
|
group.byte 0x52C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH300,Uncommitted Supervisorly Flash in Macro 300"
|
|
group.byte 0x52D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH301,Uncommitted Supervisorly Flash in Macro 301"
|
|
group.byte 0x52E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH302,Uncommitted Supervisorly Flash in Macro 302"
|
|
group.byte 0x52F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH303,Uncommitted Supervisorly Flash in Macro 303"
|
|
group.byte 0x530++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH304,Uncommitted Supervisorly Flash in Macro 304"
|
|
group.byte 0x531++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH305,Uncommitted Supervisorly Flash in Macro 305"
|
|
group.byte 0x532++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH306,Uncommitted Supervisorly Flash in Macro 306"
|
|
group.byte 0x533++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH307,Uncommitted Supervisorly Flash in Macro 307"
|
|
group.byte 0x534++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH308,Uncommitted Supervisorly Flash in Macro 308"
|
|
group.byte 0x535++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH309,Uncommitted Supervisorly Flash in Macro 309"
|
|
group.byte 0x536++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH310,Uncommitted Supervisorly Flash in Macro 310"
|
|
group.byte 0x537++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH311,Uncommitted Supervisorly Flash in Macro 311"
|
|
group.byte 0x538++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH312,Uncommitted Supervisorly Flash in Macro 312"
|
|
group.byte 0x539++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH313,Uncommitted Supervisorly Flash in Macro 313"
|
|
group.byte 0x53A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH314,Uncommitted Supervisorly Flash in Macro 314"
|
|
group.byte 0x53B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH315,Uncommitted Supervisorly Flash in Macro 315"
|
|
group.byte 0x53C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH316,Uncommitted Supervisorly Flash in Macro 316"
|
|
group.byte 0x53D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH317,Uncommitted Supervisorly Flash in Macro 317"
|
|
group.byte 0x53E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH318,Uncommitted Supervisorly Flash in Macro 318"
|
|
group.byte 0x53F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH319,Uncommitted Supervisorly Flash in Macro 319"
|
|
group.byte 0x540++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH320,Uncommitted Supervisorly Flash in Macro 320"
|
|
group.byte 0x541++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH321,Uncommitted Supervisorly Flash in Macro 321"
|
|
group.byte 0x542++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH322,Uncommitted Supervisorly Flash in Macro 322"
|
|
group.byte 0x543++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH323,Uncommitted Supervisorly Flash in Macro 323"
|
|
group.byte 0x544++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH324,Uncommitted Supervisorly Flash in Macro 324"
|
|
group.byte 0x545++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH325,Uncommitted Supervisorly Flash in Macro 325"
|
|
group.byte 0x546++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH326,Uncommitted Supervisorly Flash in Macro 326"
|
|
group.byte 0x547++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH327,Uncommitted Supervisorly Flash in Macro 327"
|
|
group.byte 0x548++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH328,Uncommitted Supervisorly Flash in Macro 328"
|
|
group.byte 0x549++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH329,Uncommitted Supervisorly Flash in Macro 329"
|
|
group.byte 0x54A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH330,Uncommitted Supervisorly Flash in Macro 330"
|
|
group.byte 0x54B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH331,Uncommitted Supervisorly Flash in Macro 331"
|
|
group.byte 0x54C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH332,Uncommitted Supervisorly Flash in Macro 332"
|
|
group.byte 0x54D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH333,Uncommitted Supervisorly Flash in Macro 333"
|
|
group.byte 0x54E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH334,Uncommitted Supervisorly Flash in Macro 334"
|
|
group.byte 0x54F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH335,Uncommitted Supervisorly Flash in Macro 335"
|
|
group.byte 0x550++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH336,Uncommitted Supervisorly Flash in Macro 336"
|
|
group.byte 0x551++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH337,Uncommitted Supervisorly Flash in Macro 337"
|
|
group.byte 0x552++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH338,Uncommitted Supervisorly Flash in Macro 338"
|
|
group.byte 0x553++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH339,Uncommitted Supervisorly Flash in Macro 339"
|
|
group.byte 0x554++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH340,Uncommitted Supervisorly Flash in Macro 340"
|
|
group.byte 0x555++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH341,Uncommitted Supervisorly Flash in Macro 341"
|
|
group.byte 0x556++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH342,Uncommitted Supervisorly Flash in Macro 342"
|
|
group.byte 0x557++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH343,Uncommitted Supervisorly Flash in Macro 343"
|
|
group.byte 0x558++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH344,Uncommitted Supervisorly Flash in Macro 344"
|
|
group.byte 0x559++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH345,Uncommitted Supervisorly Flash in Macro 345"
|
|
group.byte 0x55A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH346,Uncommitted Supervisorly Flash in Macro 346"
|
|
group.byte 0x55B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH347,Uncommitted Supervisorly Flash in Macro 347"
|
|
group.byte 0x55C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH348,Uncommitted Supervisorly Flash in Macro 348"
|
|
group.byte 0x55D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH349,Uncommitted Supervisorly Flash in Macro 349"
|
|
group.byte 0x55E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH350,Uncommitted Supervisorly Flash in Macro 350"
|
|
group.byte 0x55F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH351,Uncommitted Supervisorly Flash in Macro 351"
|
|
group.byte 0x560++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH352,Uncommitted Supervisorly Flash in Macro 352"
|
|
group.byte 0x561++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH353,Uncommitted Supervisorly Flash in Macro 353"
|
|
group.byte 0x562++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH354,Uncommitted Supervisorly Flash in Macro 354"
|
|
group.byte 0x563++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH355,Uncommitted Supervisorly Flash in Macro 355"
|
|
group.byte 0x564++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH356,Uncommitted Supervisorly Flash in Macro 356"
|
|
group.byte 0x565++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH357,Uncommitted Supervisorly Flash in Macro 357"
|
|
group.byte 0x566++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH358,Uncommitted Supervisorly Flash in Macro 358"
|
|
group.byte 0x567++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH359,Uncommitted Supervisorly Flash in Macro 359"
|
|
group.byte 0x568++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH360,Uncommitted Supervisorly Flash in Macro 360"
|
|
group.byte 0x569++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH361,Uncommitted Supervisorly Flash in Macro 361"
|
|
group.byte 0x56A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH362,Uncommitted Supervisorly Flash in Macro 362"
|
|
group.byte 0x56B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH363,Uncommitted Supervisorly Flash in Macro 363"
|
|
group.byte 0x56C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH364,Uncommitted Supervisorly Flash in Macro 364"
|
|
group.byte 0x56D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH365,Uncommitted Supervisorly Flash in Macro 365"
|
|
group.byte 0x56E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH366,Uncommitted Supervisorly Flash in Macro 366"
|
|
group.byte 0x56F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH367,Uncommitted Supervisorly Flash in Macro 367"
|
|
group.byte 0x570++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH368,Uncommitted Supervisorly Flash in Macro 368"
|
|
group.byte 0x571++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH369,Uncommitted Supervisorly Flash in Macro 369"
|
|
group.byte 0x572++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH370,Uncommitted Supervisorly Flash in Macro 370"
|
|
group.byte 0x573++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH371,Uncommitted Supervisorly Flash in Macro 371"
|
|
group.byte 0x574++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH372,Uncommitted Supervisorly Flash in Macro 372"
|
|
group.byte 0x575++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH373,Uncommitted Supervisorly Flash in Macro 373"
|
|
group.byte 0x576++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH374,Uncommitted Supervisorly Flash in Macro 374"
|
|
group.byte 0x577++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH375,Uncommitted Supervisorly Flash in Macro 375"
|
|
group.byte 0x578++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH376,Uncommitted Supervisorly Flash in Macro 376"
|
|
group.byte 0x579++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH377,Uncommitted Supervisorly Flash in Macro 377"
|
|
group.byte 0x57A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH378,Uncommitted Supervisorly Flash in Macro 378"
|
|
group.byte 0x57B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH379,Uncommitted Supervisorly Flash in Macro 379"
|
|
group.byte 0x57C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH380,Uncommitted Supervisorly Flash in Macro 380"
|
|
group.byte 0x57D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH381,Uncommitted Supervisorly Flash in Macro 381"
|
|
group.byte 0x57E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH382,Uncommitted Supervisorly Flash in Macro 382"
|
|
group.byte 0x57F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH383,Uncommitted Supervisorly Flash in Macro 383"
|
|
group.byte 0x580++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH384,Uncommitted Supervisorly Flash in Macro 384"
|
|
group.byte 0x581++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH385,Uncommitted Supervisorly Flash in Macro 385"
|
|
group.byte 0x582++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH386,Uncommitted Supervisorly Flash in Macro 386"
|
|
group.byte 0x583++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH387,Uncommitted Supervisorly Flash in Macro 387"
|
|
group.byte 0x584++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH388,Uncommitted Supervisorly Flash in Macro 388"
|
|
group.byte 0x585++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH389,Uncommitted Supervisorly Flash in Macro 389"
|
|
group.byte 0x586++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH390,Uncommitted Supervisorly Flash in Macro 390"
|
|
group.byte 0x587++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH391,Uncommitted Supervisorly Flash in Macro 391"
|
|
group.byte 0x588++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH392,Uncommitted Supervisorly Flash in Macro 392"
|
|
group.byte 0x589++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH393,Uncommitted Supervisorly Flash in Macro 393"
|
|
group.byte 0x58A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH394,Uncommitted Supervisorly Flash in Macro 394"
|
|
group.byte 0x58B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH395,Uncommitted Supervisorly Flash in Macro 395"
|
|
group.byte 0x58C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH396,Uncommitted Supervisorly Flash in Macro 396"
|
|
group.byte 0x58D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH397,Uncommitted Supervisorly Flash in Macro 397"
|
|
group.byte 0x58E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH398,Uncommitted Supervisorly Flash in Macro 398"
|
|
group.byte 0x58F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH399,Uncommitted Supervisorly Flash in Macro 399"
|
|
group.byte 0x590++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH400,Uncommitted Supervisorly Flash in Macro 400"
|
|
group.byte 0x591++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH401,Uncommitted Supervisorly Flash in Macro 401"
|
|
group.byte 0x592++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH402,Uncommitted Supervisorly Flash in Macro 402"
|
|
group.byte 0x593++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH403,Uncommitted Supervisorly Flash in Macro 403"
|
|
group.byte 0x594++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH404,Uncommitted Supervisorly Flash in Macro 404"
|
|
group.byte 0x595++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH405,Uncommitted Supervisorly Flash in Macro 405"
|
|
group.byte 0x596++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH406,Uncommitted Supervisorly Flash in Macro 406"
|
|
group.byte 0x597++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH407,Uncommitted Supervisorly Flash in Macro 407"
|
|
group.byte 0x598++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH408,Uncommitted Supervisorly Flash in Macro 408"
|
|
group.byte 0x599++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH409,Uncommitted Supervisorly Flash in Macro 409"
|
|
group.byte 0x59A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH410,Uncommitted Supervisorly Flash in Macro 410"
|
|
group.byte 0x59B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH411,Uncommitted Supervisorly Flash in Macro 411"
|
|
group.byte 0x59C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH412,Uncommitted Supervisorly Flash in Macro 412"
|
|
group.byte 0x59D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH413,Uncommitted Supervisorly Flash in Macro 413"
|
|
group.byte 0x59E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH414,Uncommitted Supervisorly Flash in Macro 414"
|
|
group.byte 0x59F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH415,Uncommitted Supervisorly Flash in Macro 415"
|
|
group.byte 0x5A0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH416,Uncommitted Supervisorly Flash in Macro 416"
|
|
group.byte 0x5A1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH417,Uncommitted Supervisorly Flash in Macro 417"
|
|
group.byte 0x5A2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH418,Uncommitted Supervisorly Flash in Macro 418"
|
|
group.byte 0x5A3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH419,Uncommitted Supervisorly Flash in Macro 419"
|
|
group.byte 0x5A4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH420,Uncommitted Supervisorly Flash in Macro 420"
|
|
group.byte 0x5A5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH421,Uncommitted Supervisorly Flash in Macro 421"
|
|
group.byte 0x5A6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH422,Uncommitted Supervisorly Flash in Macro 422"
|
|
group.byte 0x5A7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH423,Uncommitted Supervisorly Flash in Macro 423"
|
|
group.byte 0x5A8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH424,Uncommitted Supervisorly Flash in Macro 424"
|
|
group.byte 0x5A9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH425,Uncommitted Supervisorly Flash in Macro 425"
|
|
group.byte 0x5AA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH426,Uncommitted Supervisorly Flash in Macro 426"
|
|
group.byte 0x5AB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH427,Uncommitted Supervisorly Flash in Macro 427"
|
|
group.byte 0x5AC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH428,Uncommitted Supervisorly Flash in Macro 428"
|
|
group.byte 0x5AD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH429,Uncommitted Supervisorly Flash in Macro 429"
|
|
group.byte 0x5AE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH430,Uncommitted Supervisorly Flash in Macro 430"
|
|
group.byte 0x5AF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH431,Uncommitted Supervisorly Flash in Macro 431"
|
|
group.byte 0x5B0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH432,Uncommitted Supervisorly Flash in Macro 432"
|
|
group.byte 0x5B1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH433,Uncommitted Supervisorly Flash in Macro 433"
|
|
group.byte 0x5B2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH434,Uncommitted Supervisorly Flash in Macro 434"
|
|
group.byte 0x5B3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH435,Uncommitted Supervisorly Flash in Macro 435"
|
|
group.byte 0x5B4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH436,Uncommitted Supervisorly Flash in Macro 436"
|
|
group.byte 0x5B5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH437,Uncommitted Supervisorly Flash in Macro 437"
|
|
group.byte 0x5B6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH438,Uncommitted Supervisorly Flash in Macro 438"
|
|
group.byte 0x5B7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH439,Uncommitted Supervisorly Flash in Macro 439"
|
|
group.byte 0x5B8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH440,Uncommitted Supervisorly Flash in Macro 440"
|
|
group.byte 0x5B9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH441,Uncommitted Supervisorly Flash in Macro 441"
|
|
group.byte 0x5BA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH442,Uncommitted Supervisorly Flash in Macro 442"
|
|
group.byte 0x5BB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH443,Uncommitted Supervisorly Flash in Macro 443"
|
|
group.byte 0x5BC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH444,Uncommitted Supervisorly Flash in Macro 444"
|
|
group.byte 0x5BD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH445,Uncommitted Supervisorly Flash in Macro 445"
|
|
group.byte 0x5BE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH446,Uncommitted Supervisorly Flash in Macro 446"
|
|
group.byte 0x5BF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH447,Uncommitted Supervisorly Flash in Macro 447"
|
|
group.byte 0x5C0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH448,Uncommitted Supervisorly Flash in Macro 448"
|
|
group.byte 0x5C1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH449,Uncommitted Supervisorly Flash in Macro 449"
|
|
group.byte 0x5C2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH450,Uncommitted Supervisorly Flash in Macro 450"
|
|
group.byte 0x5C3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH451,Uncommitted Supervisorly Flash in Macro 451"
|
|
group.byte 0x5C4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH452,Uncommitted Supervisorly Flash in Macro 452"
|
|
group.byte 0x5C5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH453,Uncommitted Supervisorly Flash in Macro 453"
|
|
group.byte 0x5C6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH454,Uncommitted Supervisorly Flash in Macro 454"
|
|
group.byte 0x5C7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH455,Uncommitted Supervisorly Flash in Macro 455"
|
|
group.byte 0x5C8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH456,Uncommitted Supervisorly Flash in Macro 456"
|
|
group.byte 0x5C9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH457,Uncommitted Supervisorly Flash in Macro 457"
|
|
group.byte 0x5CA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH458,Uncommitted Supervisorly Flash in Macro 458"
|
|
group.byte 0x5CB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH459,Uncommitted Supervisorly Flash in Macro 459"
|
|
group.byte 0x5CC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH460,Uncommitted Supervisorly Flash in Macro 460"
|
|
group.byte 0x5CD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH461,Uncommitted Supervisorly Flash in Macro 461"
|
|
group.byte 0x5CE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH462,Uncommitted Supervisorly Flash in Macro 462"
|
|
group.byte 0x5CF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH463,Uncommitted Supervisorly Flash in Macro 463"
|
|
group.byte 0x5D0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH464,Uncommitted Supervisorly Flash in Macro 464"
|
|
group.byte 0x5D1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH465,Uncommitted Supervisorly Flash in Macro 465"
|
|
group.byte 0x5D2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH466,Uncommitted Supervisorly Flash in Macro 466"
|
|
group.byte 0x5D3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH467,Uncommitted Supervisorly Flash in Macro 467"
|
|
group.byte 0x5D4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH468,Uncommitted Supervisorly Flash in Macro 468"
|
|
group.byte 0x5D5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH469,Uncommitted Supervisorly Flash in Macro 469"
|
|
group.byte 0x5D6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH470,Uncommitted Supervisorly Flash in Macro 470"
|
|
group.byte 0x5D7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH471,Uncommitted Supervisorly Flash in Macro 471"
|
|
group.byte 0x5D8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH472,Uncommitted Supervisorly Flash in Macro 472"
|
|
group.byte 0x5D9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH473,Uncommitted Supervisorly Flash in Macro 473"
|
|
group.byte 0x5DA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH474,Uncommitted Supervisorly Flash in Macro 474"
|
|
group.byte 0x5DB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH475,Uncommitted Supervisorly Flash in Macro 475"
|
|
group.byte 0x5DC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH476,Uncommitted Supervisorly Flash in Macro 476"
|
|
group.byte 0x5DD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH477,Uncommitted Supervisorly Flash in Macro 477"
|
|
group.byte 0x5DE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH478,Uncommitted Supervisorly Flash in Macro 478"
|
|
group.byte 0x5DF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH479,Uncommitted Supervisorly Flash in Macro 479"
|
|
group.byte 0x5E0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH480,Uncommitted Supervisorly Flash in Macro 480"
|
|
group.byte 0x5E1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH481,Uncommitted Supervisorly Flash in Macro 481"
|
|
group.byte 0x5E2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH482,Uncommitted Supervisorly Flash in Macro 482"
|
|
group.byte 0x5E3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH483,Uncommitted Supervisorly Flash in Macro 483"
|
|
group.byte 0x5E4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH484,Uncommitted Supervisorly Flash in Macro 484"
|
|
group.byte 0x5E5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH485,Uncommitted Supervisorly Flash in Macro 485"
|
|
group.byte 0x5E6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH486,Uncommitted Supervisorly Flash in Macro 486"
|
|
group.byte 0x5E7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH487,Uncommitted Supervisorly Flash in Macro 487"
|
|
group.byte 0x5E8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH488,Uncommitted Supervisorly Flash in Macro 488"
|
|
group.byte 0x5E9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH489,Uncommitted Supervisorly Flash in Macro 489"
|
|
group.byte 0x5EA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH490,Uncommitted Supervisorly Flash in Macro 490"
|
|
group.byte 0x5EB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH491,Uncommitted Supervisorly Flash in Macro 491"
|
|
group.byte 0x5EC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH492,Uncommitted Supervisorly Flash in Macro 492"
|
|
group.byte 0x5ED++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH493,Uncommitted Supervisorly Flash in Macro 493"
|
|
group.byte 0x5EE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH494,Uncommitted Supervisorly Flash in Macro 494"
|
|
group.byte 0x5EF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH495,Uncommitted Supervisorly Flash in Macro 495"
|
|
group.byte 0x5F0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH496,Uncommitted Supervisorly Flash in Macro 496"
|
|
group.byte 0x5F1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH497,Uncommitted Supervisorly Flash in Macro 497"
|
|
group.byte 0x5F2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH498,Uncommitted Supervisorly Flash in Macro 498"
|
|
group.byte 0x5F3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH499,Uncommitted Supervisorly Flash in Macro 499"
|
|
group.byte 0x5F4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH500,Uncommitted Supervisorly Flash in Macro 500"
|
|
group.byte 0x5F5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH501,Uncommitted Supervisorly Flash in Macro 501"
|
|
group.byte 0x5F6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH502,Uncommitted Supervisorly Flash in Macro 502"
|
|
group.byte 0x5F7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH503,Uncommitted Supervisorly Flash in Macro 503"
|
|
group.byte 0x5F8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH504,Uncommitted Supervisorly Flash in Macro 504"
|
|
group.byte 0x5F9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH505,Uncommitted Supervisorly Flash in Macro 505"
|
|
group.byte 0x5FA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH506,Uncommitted Supervisorly Flash in Macro 506"
|
|
group.byte 0x5FB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH507,Uncommitted Supervisorly Flash in Macro 507"
|
|
group.byte 0x5FC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH508,Uncommitted Supervisorly Flash in Macro 508"
|
|
group.byte 0x5FD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH509,Uncommitted Supervisorly Flash in Macro 509"
|
|
group.byte 0x5FE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH510,Uncommitted Supervisorly Flash in Macro 510"
|
|
group.byte 0x5FF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH511,Uncommitted Supervisorly Flash in Macro 511"
|
|
group.byte 0x600++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH512,Uncommitted Supervisorly Flash in Macro 512"
|
|
group.byte 0x601++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH513,Uncommitted Supervisorly Flash in Macro 513"
|
|
group.byte 0x602++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH514,Uncommitted Supervisorly Flash in Macro 514"
|
|
group.byte 0x603++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH515,Uncommitted Supervisorly Flash in Macro 515"
|
|
group.byte 0x604++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH516,Uncommitted Supervisorly Flash in Macro 516"
|
|
group.byte 0x605++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH517,Uncommitted Supervisorly Flash in Macro 517"
|
|
group.byte 0x606++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH518,Uncommitted Supervisorly Flash in Macro 518"
|
|
group.byte 0x607++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH519,Uncommitted Supervisorly Flash in Macro 519"
|
|
group.byte 0x608++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH520,Uncommitted Supervisorly Flash in Macro 520"
|
|
group.byte 0x609++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH521,Uncommitted Supervisorly Flash in Macro 521"
|
|
group.byte 0x60A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH522,Uncommitted Supervisorly Flash in Macro 522"
|
|
group.byte 0x60B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH523,Uncommitted Supervisorly Flash in Macro 523"
|
|
group.byte 0x60C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH524,Uncommitted Supervisorly Flash in Macro 524"
|
|
group.byte 0x60D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH525,Uncommitted Supervisorly Flash in Macro 525"
|
|
group.byte 0x60E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH526,Uncommitted Supervisorly Flash in Macro 526"
|
|
group.byte 0x60F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH527,Uncommitted Supervisorly Flash in Macro 527"
|
|
group.byte 0x610++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH528,Uncommitted Supervisorly Flash in Macro 528"
|
|
group.byte 0x611++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH529,Uncommitted Supervisorly Flash in Macro 529"
|
|
group.byte 0x612++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH530,Uncommitted Supervisorly Flash in Macro 530"
|
|
group.byte 0x613++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH531,Uncommitted Supervisorly Flash in Macro 531"
|
|
group.byte 0x614++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH532,Uncommitted Supervisorly Flash in Macro 532"
|
|
group.byte 0x615++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH533,Uncommitted Supervisorly Flash in Macro 533"
|
|
group.byte 0x616++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH534,Uncommitted Supervisorly Flash in Macro 534"
|
|
group.byte 0x617++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH535,Uncommitted Supervisorly Flash in Macro 535"
|
|
group.byte 0x618++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH536,Uncommitted Supervisorly Flash in Macro 536"
|
|
group.byte 0x619++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH537,Uncommitted Supervisorly Flash in Macro 537"
|
|
group.byte 0x61A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH538,Uncommitted Supervisorly Flash in Macro 538"
|
|
group.byte 0x61B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH539,Uncommitted Supervisorly Flash in Macro 539"
|
|
group.byte 0x61C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH540,Uncommitted Supervisorly Flash in Macro 540"
|
|
group.byte 0x61D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH541,Uncommitted Supervisorly Flash in Macro 541"
|
|
group.byte 0x61E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH542,Uncommitted Supervisorly Flash in Macro 542"
|
|
group.byte 0x61F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH543,Uncommitted Supervisorly Flash in Macro 543"
|
|
group.byte 0x620++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH544,Uncommitted Supervisorly Flash in Macro 544"
|
|
group.byte 0x621++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH545,Uncommitted Supervisorly Flash in Macro 545"
|
|
group.byte 0x622++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH546,Uncommitted Supervisorly Flash in Macro 546"
|
|
group.byte 0x623++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH547,Uncommitted Supervisorly Flash in Macro 547"
|
|
group.byte 0x624++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH548,Uncommitted Supervisorly Flash in Macro 548"
|
|
group.byte 0x625++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH549,Uncommitted Supervisorly Flash in Macro 549"
|
|
group.byte 0x626++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH550,Uncommitted Supervisorly Flash in Macro 550"
|
|
group.byte 0x627++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH551,Uncommitted Supervisorly Flash in Macro 551"
|
|
group.byte 0x628++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH552,Uncommitted Supervisorly Flash in Macro 552"
|
|
group.byte 0x629++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH553,Uncommitted Supervisorly Flash in Macro 553"
|
|
group.byte 0x62A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH554,Uncommitted Supervisorly Flash in Macro 554"
|
|
group.byte 0x62B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH555,Uncommitted Supervisorly Flash in Macro 555"
|
|
group.byte 0x62C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH556,Uncommitted Supervisorly Flash in Macro 556"
|
|
group.byte 0x62D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH557,Uncommitted Supervisorly Flash in Macro 557"
|
|
group.byte 0x62E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH558,Uncommitted Supervisorly Flash in Macro 558"
|
|
group.byte 0x62F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH559,Uncommitted Supervisorly Flash in Macro 559"
|
|
group.byte 0x630++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH560,Uncommitted Supervisorly Flash in Macro 560"
|
|
group.byte 0x631++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH561,Uncommitted Supervisorly Flash in Macro 561"
|
|
group.byte 0x632++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH562,Uncommitted Supervisorly Flash in Macro 562"
|
|
group.byte 0x633++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH563,Uncommitted Supervisorly Flash in Macro 563"
|
|
group.byte 0x634++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH564,Uncommitted Supervisorly Flash in Macro 564"
|
|
group.byte 0x635++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH565,Uncommitted Supervisorly Flash in Macro 565"
|
|
group.byte 0x636++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH566,Uncommitted Supervisorly Flash in Macro 566"
|
|
group.byte 0x637++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH567,Uncommitted Supervisorly Flash in Macro 567"
|
|
group.byte 0x638++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH568,Uncommitted Supervisorly Flash in Macro 568"
|
|
group.byte 0x639++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH569,Uncommitted Supervisorly Flash in Macro 569"
|
|
group.byte 0x63A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH570,Uncommitted Supervisorly Flash in Macro 570"
|
|
group.byte 0x63B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH571,Uncommitted Supervisorly Flash in Macro 571"
|
|
group.byte 0x63C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH572,Uncommitted Supervisorly Flash in Macro 572"
|
|
group.byte 0x63D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH573,Uncommitted Supervisorly Flash in Macro 573"
|
|
group.byte 0x63E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH574,Uncommitted Supervisorly Flash in Macro 574"
|
|
group.byte 0x63F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH575,Uncommitted Supervisorly Flash in Macro 575"
|
|
group.byte 0x640++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH576,Uncommitted Supervisorly Flash in Macro 576"
|
|
group.byte 0x641++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH577,Uncommitted Supervisorly Flash in Macro 577"
|
|
group.byte 0x642++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH578,Uncommitted Supervisorly Flash in Macro 578"
|
|
group.byte 0x643++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH579,Uncommitted Supervisorly Flash in Macro 579"
|
|
group.byte 0x644++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH580,Uncommitted Supervisorly Flash in Macro 580"
|
|
group.byte 0x645++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH581,Uncommitted Supervisorly Flash in Macro 581"
|
|
group.byte 0x646++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH582,Uncommitted Supervisorly Flash in Macro 582"
|
|
group.byte 0x647++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH583,Uncommitted Supervisorly Flash in Macro 583"
|
|
group.byte 0x648++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH584,Uncommitted Supervisorly Flash in Macro 584"
|
|
group.byte 0x649++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH585,Uncommitted Supervisorly Flash in Macro 585"
|
|
group.byte 0x64A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH586,Uncommitted Supervisorly Flash in Macro 586"
|
|
group.byte 0x64B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH587,Uncommitted Supervisorly Flash in Macro 587"
|
|
group.byte 0x64C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH588,Uncommitted Supervisorly Flash in Macro 588"
|
|
group.byte 0x64D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH589,Uncommitted Supervisorly Flash in Macro 589"
|
|
group.byte 0x64E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH590,Uncommitted Supervisorly Flash in Macro 590"
|
|
group.byte 0x64F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH591,Uncommitted Supervisorly Flash in Macro 591"
|
|
group.byte 0x650++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH592,Uncommitted Supervisorly Flash in Macro 592"
|
|
group.byte 0x651++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH593,Uncommitted Supervisorly Flash in Macro 593"
|
|
group.byte 0x652++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH594,Uncommitted Supervisorly Flash in Macro 594"
|
|
group.byte 0x653++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH595,Uncommitted Supervisorly Flash in Macro 595"
|
|
group.byte 0x654++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH596,Uncommitted Supervisorly Flash in Macro 596"
|
|
group.byte 0x655++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH597,Uncommitted Supervisorly Flash in Macro 597"
|
|
group.byte 0x656++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH598,Uncommitted Supervisorly Flash in Macro 598"
|
|
group.byte 0x657++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH599,Uncommitted Supervisorly Flash in Macro 599"
|
|
group.byte 0x658++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH600,Uncommitted Supervisorly Flash in Macro 600"
|
|
group.byte 0x659++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH601,Uncommitted Supervisorly Flash in Macro 601"
|
|
group.byte 0x65A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH602,Uncommitted Supervisorly Flash in Macro 602"
|
|
group.byte 0x65B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH603,Uncommitted Supervisorly Flash in Macro 603"
|
|
group.byte 0x65C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH604,Uncommitted Supervisorly Flash in Macro 604"
|
|
group.byte 0x65D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH605,Uncommitted Supervisorly Flash in Macro 605"
|
|
group.byte 0x65E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH606,Uncommitted Supervisorly Flash in Macro 606"
|
|
group.byte 0x65F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH607,Uncommitted Supervisorly Flash in Macro 607"
|
|
group.byte 0x660++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH608,Uncommitted Supervisorly Flash in Macro 608"
|
|
group.byte 0x661++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH609,Uncommitted Supervisorly Flash in Macro 609"
|
|
group.byte 0x662++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH610,Uncommitted Supervisorly Flash in Macro 610"
|
|
group.byte 0x663++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH611,Uncommitted Supervisorly Flash in Macro 611"
|
|
group.byte 0x664++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH612,Uncommitted Supervisorly Flash in Macro 612"
|
|
group.byte 0x665++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH613,Uncommitted Supervisorly Flash in Macro 613"
|
|
group.byte 0x666++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH614,Uncommitted Supervisorly Flash in Macro 614"
|
|
group.byte 0x667++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH615,Uncommitted Supervisorly Flash in Macro 615"
|
|
group.byte 0x668++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH616,Uncommitted Supervisorly Flash in Macro 616"
|
|
group.byte 0x669++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH617,Uncommitted Supervisorly Flash in Macro 617"
|
|
group.byte 0x66A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH618,Uncommitted Supervisorly Flash in Macro 618"
|
|
group.byte 0x66B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH619,Uncommitted Supervisorly Flash in Macro 619"
|
|
group.byte 0x66C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH620,Uncommitted Supervisorly Flash in Macro 620"
|
|
group.byte 0x66D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH621,Uncommitted Supervisorly Flash in Macro 621"
|
|
group.byte 0x66E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH622,Uncommitted Supervisorly Flash in Macro 622"
|
|
group.byte 0x66F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH623,Uncommitted Supervisorly Flash in Macro 623"
|
|
group.byte 0x670++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH624,Uncommitted Supervisorly Flash in Macro 624"
|
|
group.byte 0x671++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH625,Uncommitted Supervisorly Flash in Macro 625"
|
|
group.byte 0x672++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH626,Uncommitted Supervisorly Flash in Macro 626"
|
|
group.byte 0x673++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH627,Uncommitted Supervisorly Flash in Macro 627"
|
|
group.byte 0x674++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH628,Uncommitted Supervisorly Flash in Macro 628"
|
|
group.byte 0x675++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH629,Uncommitted Supervisorly Flash in Macro 629"
|
|
group.byte 0x676++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH630,Uncommitted Supervisorly Flash in Macro 630"
|
|
group.byte 0x677++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH631,Uncommitted Supervisorly Flash in Macro 631"
|
|
group.byte 0x678++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH632,Uncommitted Supervisorly Flash in Macro 632"
|
|
group.byte 0x679++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH633,Uncommitted Supervisorly Flash in Macro 633"
|
|
group.byte 0x67A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH634,Uncommitted Supervisorly Flash in Macro 634"
|
|
group.byte 0x67B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH635,Uncommitted Supervisorly Flash in Macro 635"
|
|
group.byte 0x67C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH636,Uncommitted Supervisorly Flash in Macro 636"
|
|
group.byte 0x67D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH637,Uncommitted Supervisorly Flash in Macro 637"
|
|
group.byte 0x67E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH638,Uncommitted Supervisorly Flash in Macro 638"
|
|
group.byte 0x67F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH639,Uncommitted Supervisorly Flash in Macro 639"
|
|
group.byte 0x680++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH640,Uncommitted Supervisorly Flash in Macro 640"
|
|
group.byte 0x681++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH641,Uncommitted Supervisorly Flash in Macro 641"
|
|
group.byte 0x682++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH642,Uncommitted Supervisorly Flash in Macro 642"
|
|
group.byte 0x683++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH643,Uncommitted Supervisorly Flash in Macro 643"
|
|
group.byte 0x684++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH644,Uncommitted Supervisorly Flash in Macro 644"
|
|
group.byte 0x685++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH645,Uncommitted Supervisorly Flash in Macro 645"
|
|
group.byte 0x686++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH646,Uncommitted Supervisorly Flash in Macro 646"
|
|
group.byte 0x687++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH647,Uncommitted Supervisorly Flash in Macro 647"
|
|
group.byte 0x688++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH648,Uncommitted Supervisorly Flash in Macro 648"
|
|
group.byte 0x689++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH649,Uncommitted Supervisorly Flash in Macro 649"
|
|
group.byte 0x68A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH650,Uncommitted Supervisorly Flash in Macro 650"
|
|
group.byte 0x68B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH651,Uncommitted Supervisorly Flash in Macro 651"
|
|
group.byte 0x68C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH652,Uncommitted Supervisorly Flash in Macro 652"
|
|
group.byte 0x68D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH653,Uncommitted Supervisorly Flash in Macro 653"
|
|
group.byte 0x68E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH654,Uncommitted Supervisorly Flash in Macro 654"
|
|
group.byte 0x68F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH655,Uncommitted Supervisorly Flash in Macro 655"
|
|
group.byte 0x690++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH656,Uncommitted Supervisorly Flash in Macro 656"
|
|
group.byte 0x691++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH657,Uncommitted Supervisorly Flash in Macro 657"
|
|
group.byte 0x692++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH658,Uncommitted Supervisorly Flash in Macro 658"
|
|
group.byte 0x693++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH659,Uncommitted Supervisorly Flash in Macro 659"
|
|
group.byte 0x694++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH660,Uncommitted Supervisorly Flash in Macro 660"
|
|
group.byte 0x695++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH661,Uncommitted Supervisorly Flash in Macro 661"
|
|
group.byte 0x696++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH662,Uncommitted Supervisorly Flash in Macro 662"
|
|
group.byte 0x697++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH663,Uncommitted Supervisorly Flash in Macro 663"
|
|
group.byte 0x698++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH664,Uncommitted Supervisorly Flash in Macro 664"
|
|
group.byte 0x699++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH665,Uncommitted Supervisorly Flash in Macro 665"
|
|
group.byte 0x69A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH666,Uncommitted Supervisorly Flash in Macro 666"
|
|
group.byte 0x69B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH667,Uncommitted Supervisorly Flash in Macro 667"
|
|
group.byte 0x69C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH668,Uncommitted Supervisorly Flash in Macro 668"
|
|
group.byte 0x69D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH669,Uncommitted Supervisorly Flash in Macro 669"
|
|
group.byte 0x69E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH670,Uncommitted Supervisorly Flash in Macro 670"
|
|
group.byte 0x69F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH671,Uncommitted Supervisorly Flash in Macro 671"
|
|
group.byte 0x6A0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH672,Uncommitted Supervisorly Flash in Macro 672"
|
|
group.byte 0x6A1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH673,Uncommitted Supervisorly Flash in Macro 673"
|
|
group.byte 0x6A2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH674,Uncommitted Supervisorly Flash in Macro 674"
|
|
group.byte 0x6A3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH675,Uncommitted Supervisorly Flash in Macro 675"
|
|
group.byte 0x6A4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH676,Uncommitted Supervisorly Flash in Macro 676"
|
|
group.byte 0x6A5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH677,Uncommitted Supervisorly Flash in Macro 677"
|
|
group.byte 0x6A6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH678,Uncommitted Supervisorly Flash in Macro 678"
|
|
group.byte 0x6A7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH679,Uncommitted Supervisorly Flash in Macro 679"
|
|
group.byte 0x6A8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH680,Uncommitted Supervisorly Flash in Macro 680"
|
|
group.byte 0x6A9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH681,Uncommitted Supervisorly Flash in Macro 681"
|
|
group.byte 0x6AA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH682,Uncommitted Supervisorly Flash in Macro 682"
|
|
group.byte 0x6AB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH683,Uncommitted Supervisorly Flash in Macro 683"
|
|
group.byte 0x6AC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH684,Uncommitted Supervisorly Flash in Macro 684"
|
|
group.byte 0x6AD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH685,Uncommitted Supervisorly Flash in Macro 685"
|
|
group.byte 0x6AE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH686,Uncommitted Supervisorly Flash in Macro 686"
|
|
group.byte 0x6AF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH687,Uncommitted Supervisorly Flash in Macro 687"
|
|
group.byte 0x6B0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH688,Uncommitted Supervisorly Flash in Macro 688"
|
|
group.byte 0x6B1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH689,Uncommitted Supervisorly Flash in Macro 689"
|
|
group.byte 0x6B2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH690,Uncommitted Supervisorly Flash in Macro 690"
|
|
group.byte 0x6B3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH691,Uncommitted Supervisorly Flash in Macro 691"
|
|
group.byte 0x6B4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH692,Uncommitted Supervisorly Flash in Macro 692"
|
|
group.byte 0x6B5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH693,Uncommitted Supervisorly Flash in Macro 693"
|
|
group.byte 0x6B6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH694,Uncommitted Supervisorly Flash in Macro 694"
|
|
group.byte 0x6B7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH695,Uncommitted Supervisorly Flash in Macro 695"
|
|
group.byte 0x6B8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH696,Uncommitted Supervisorly Flash in Macro 696"
|
|
group.byte 0x6B9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH697,Uncommitted Supervisorly Flash in Macro 697"
|
|
group.byte 0x6BA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH698,Uncommitted Supervisorly Flash in Macro 698"
|
|
group.byte 0x6BB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH699,Uncommitted Supervisorly Flash in Macro 699"
|
|
group.byte 0x6BC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH700,Uncommitted Supervisorly Flash in Macro 700"
|
|
group.byte 0x6BD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH701,Uncommitted Supervisorly Flash in Macro 701"
|
|
group.byte 0x6BE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH702,Uncommitted Supervisorly Flash in Macro 702"
|
|
group.byte 0x6BF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH703,Uncommitted Supervisorly Flash in Macro 703"
|
|
group.byte 0x6C0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH704,Uncommitted Supervisorly Flash in Macro 704"
|
|
group.byte 0x6C1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH705,Uncommitted Supervisorly Flash in Macro 705"
|
|
group.byte 0x6C2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH706,Uncommitted Supervisorly Flash in Macro 706"
|
|
group.byte 0x6C3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH707,Uncommitted Supervisorly Flash in Macro 707"
|
|
group.byte 0x6C4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH708,Uncommitted Supervisorly Flash in Macro 708"
|
|
group.byte 0x6C5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH709,Uncommitted Supervisorly Flash in Macro 709"
|
|
group.byte 0x6C6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH710,Uncommitted Supervisorly Flash in Macro 710"
|
|
group.byte 0x6C7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH711,Uncommitted Supervisorly Flash in Macro 711"
|
|
group.byte 0x6C8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH712,Uncommitted Supervisorly Flash in Macro 712"
|
|
group.byte 0x6C9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH713,Uncommitted Supervisorly Flash in Macro 713"
|
|
group.byte 0x6CA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH714,Uncommitted Supervisorly Flash in Macro 714"
|
|
group.byte 0x6CB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH715,Uncommitted Supervisorly Flash in Macro 715"
|
|
group.byte 0x6CC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH716,Uncommitted Supervisorly Flash in Macro 716"
|
|
group.byte 0x6CD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH717,Uncommitted Supervisorly Flash in Macro 717"
|
|
group.byte 0x6CE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH718,Uncommitted Supervisorly Flash in Macro 718"
|
|
group.byte 0x6CF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH719,Uncommitted Supervisorly Flash in Macro 719"
|
|
group.byte 0x6D0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH720,Uncommitted Supervisorly Flash in Macro 720"
|
|
group.byte 0x6D1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH721,Uncommitted Supervisorly Flash in Macro 721"
|
|
group.byte 0x6D2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH722,Uncommitted Supervisorly Flash in Macro 722"
|
|
group.byte 0x6D3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH723,Uncommitted Supervisorly Flash in Macro 723"
|
|
group.byte 0x6D4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH724,Uncommitted Supervisorly Flash in Macro 724"
|
|
group.byte 0x6D5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH725,Uncommitted Supervisorly Flash in Macro 725"
|
|
group.byte 0x6D6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH726,Uncommitted Supervisorly Flash in Macro 726"
|
|
group.byte 0x6D7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH727,Uncommitted Supervisorly Flash in Macro 727"
|
|
group.byte 0x6D8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH728,Uncommitted Supervisorly Flash in Macro 728"
|
|
group.byte 0x6D9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH729,Uncommitted Supervisorly Flash in Macro 729"
|
|
group.byte 0x6DA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH730,Uncommitted Supervisorly Flash in Macro 730"
|
|
group.byte 0x6DB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH731,Uncommitted Supervisorly Flash in Macro 731"
|
|
group.byte 0x6DC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH732,Uncommitted Supervisorly Flash in Macro 732"
|
|
group.byte 0x6DD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH733,Uncommitted Supervisorly Flash in Macro 733"
|
|
group.byte 0x6DE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH734,Uncommitted Supervisorly Flash in Macro 734"
|
|
group.byte 0x6DF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH735,Uncommitted Supervisorly Flash in Macro 735"
|
|
group.byte 0x6E0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH736,Uncommitted Supervisorly Flash in Macro 736"
|
|
group.byte 0x6E1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH737,Uncommitted Supervisorly Flash in Macro 737"
|
|
group.byte 0x6E2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH738,Uncommitted Supervisorly Flash in Macro 738"
|
|
group.byte 0x6E3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH739,Uncommitted Supervisorly Flash in Macro 739"
|
|
group.byte 0x6E4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH740,Uncommitted Supervisorly Flash in Macro 740"
|
|
group.byte 0x6E5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH741,Uncommitted Supervisorly Flash in Macro 741"
|
|
group.byte 0x6E6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH742,Uncommitted Supervisorly Flash in Macro 742"
|
|
group.byte 0x6E7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH743,Uncommitted Supervisorly Flash in Macro 743"
|
|
group.byte 0x6E8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH744,Uncommitted Supervisorly Flash in Macro 744"
|
|
group.byte 0x6E9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH745,Uncommitted Supervisorly Flash in Macro 745"
|
|
group.byte 0x6EA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH746,Uncommitted Supervisorly Flash in Macro 746"
|
|
group.byte 0x6EB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH747,Uncommitted Supervisorly Flash in Macro 747"
|
|
group.byte 0x6EC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH748,Uncommitted Supervisorly Flash in Macro 748"
|
|
group.byte 0x6ED++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH749,Uncommitted Supervisorly Flash in Macro 749"
|
|
group.byte 0x6EE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH750,Uncommitted Supervisorly Flash in Macro 750"
|
|
group.byte 0x6EF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH751,Uncommitted Supervisorly Flash in Macro 751"
|
|
group.byte 0x6F0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH752,Uncommitted Supervisorly Flash in Macro 752"
|
|
group.byte 0x6F1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH753,Uncommitted Supervisorly Flash in Macro 753"
|
|
group.byte 0x6F2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH754,Uncommitted Supervisorly Flash in Macro 754"
|
|
group.byte 0x6F3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH755,Uncommitted Supervisorly Flash in Macro 755"
|
|
group.byte 0x6F4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH756,Uncommitted Supervisorly Flash in Macro 756"
|
|
group.byte 0x6F5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH757,Uncommitted Supervisorly Flash in Macro 757"
|
|
group.byte 0x6F6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH758,Uncommitted Supervisorly Flash in Macro 758"
|
|
group.byte 0x6F7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH759,Uncommitted Supervisorly Flash in Macro 759"
|
|
group.byte 0x6F8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH760,Uncommitted Supervisorly Flash in Macro 760"
|
|
group.byte 0x6F9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH761,Uncommitted Supervisorly Flash in Macro 761"
|
|
group.byte 0x6FA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH762,Uncommitted Supervisorly Flash in Macro 762"
|
|
group.byte 0x6FB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH763,Uncommitted Supervisorly Flash in Macro 763"
|
|
group.byte 0x6FC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH764,Uncommitted Supervisorly Flash in Macro 764"
|
|
group.byte 0x6FD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH765,Uncommitted Supervisorly Flash in Macro 765"
|
|
group.byte 0x6FE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH766,Uncommitted Supervisorly Flash in Macro 766"
|
|
group.byte 0x6FF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH767,Uncommitted Supervisorly Flash in Macro 767"
|
|
group.byte 0x700++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH768,Uncommitted Supervisorly Flash in Macro 768"
|
|
group.byte 0x701++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH769,Uncommitted Supervisorly Flash in Macro 769"
|
|
group.byte 0x702++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH770,Uncommitted Supervisorly Flash in Macro 770"
|
|
group.byte 0x703++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH771,Uncommitted Supervisorly Flash in Macro 771"
|
|
group.byte 0x704++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH772,Uncommitted Supervisorly Flash in Macro 772"
|
|
group.byte 0x705++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH773,Uncommitted Supervisorly Flash in Macro 773"
|
|
group.byte 0x706++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH774,Uncommitted Supervisorly Flash in Macro 774"
|
|
group.byte 0x707++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH775,Uncommitted Supervisorly Flash in Macro 775"
|
|
group.byte 0x708++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH776,Uncommitted Supervisorly Flash in Macro 776"
|
|
group.byte 0x709++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH777,Uncommitted Supervisorly Flash in Macro 777"
|
|
group.byte 0x70A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH778,Uncommitted Supervisorly Flash in Macro 778"
|
|
group.byte 0x70B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH779,Uncommitted Supervisorly Flash in Macro 779"
|
|
group.byte 0x70C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH780,Uncommitted Supervisorly Flash in Macro 780"
|
|
group.byte 0x70D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH781,Uncommitted Supervisorly Flash in Macro 781"
|
|
group.byte 0x70E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH782,Uncommitted Supervisorly Flash in Macro 782"
|
|
group.byte 0x70F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH783,Uncommitted Supervisorly Flash in Macro 783"
|
|
group.byte 0x710++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH784,Uncommitted Supervisorly Flash in Macro 784"
|
|
group.byte 0x711++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH785,Uncommitted Supervisorly Flash in Macro 785"
|
|
group.byte 0x712++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH786,Uncommitted Supervisorly Flash in Macro 786"
|
|
group.byte 0x713++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH787,Uncommitted Supervisorly Flash in Macro 787"
|
|
group.byte 0x714++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH788,Uncommitted Supervisorly Flash in Macro 788"
|
|
group.byte 0x715++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH789,Uncommitted Supervisorly Flash in Macro 789"
|
|
group.byte 0x716++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH790,Uncommitted Supervisorly Flash in Macro 790"
|
|
group.byte 0x717++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH791,Uncommitted Supervisorly Flash in Macro 791"
|
|
group.byte 0x718++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH792,Uncommitted Supervisorly Flash in Macro 792"
|
|
group.byte 0x719++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH793,Uncommitted Supervisorly Flash in Macro 793"
|
|
group.byte 0x71A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH794,Uncommitted Supervisorly Flash in Macro 794"
|
|
group.byte 0x71B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH795,Uncommitted Supervisorly Flash in Macro 795"
|
|
group.byte 0x71C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH796,Uncommitted Supervisorly Flash in Macro 796"
|
|
group.byte 0x71D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH797,Uncommitted Supervisorly Flash in Macro 797"
|
|
group.byte 0x71E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH798,Uncommitted Supervisorly Flash in Macro 798"
|
|
group.byte 0x71F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH799,Uncommitted Supervisorly Flash in Macro 799"
|
|
group.byte 0x720++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH800,Uncommitted Supervisorly Flash in Macro 800"
|
|
group.byte 0x721++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH801,Uncommitted Supervisorly Flash in Macro 801"
|
|
group.byte 0x722++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH802,Uncommitted Supervisorly Flash in Macro 802"
|
|
group.byte 0x723++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH803,Uncommitted Supervisorly Flash in Macro 803"
|
|
group.byte 0x724++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH804,Uncommitted Supervisorly Flash in Macro 804"
|
|
group.byte 0x725++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH805,Uncommitted Supervisorly Flash in Macro 805"
|
|
group.byte 0x726++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH806,Uncommitted Supervisorly Flash in Macro 806"
|
|
group.byte 0x727++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH807,Uncommitted Supervisorly Flash in Macro 807"
|
|
group.byte 0x728++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH808,Uncommitted Supervisorly Flash in Macro 808"
|
|
group.byte 0x729++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH809,Uncommitted Supervisorly Flash in Macro 809"
|
|
group.byte 0x72A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH810,Uncommitted Supervisorly Flash in Macro 810"
|
|
group.byte 0x72B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH811,Uncommitted Supervisorly Flash in Macro 811"
|
|
group.byte 0x72C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH812,Uncommitted Supervisorly Flash in Macro 812"
|
|
group.byte 0x72D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH813,Uncommitted Supervisorly Flash in Macro 813"
|
|
group.byte 0x72E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH814,Uncommitted Supervisorly Flash in Macro 814"
|
|
group.byte 0x72F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH815,Uncommitted Supervisorly Flash in Macro 815"
|
|
group.byte 0x730++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH816,Uncommitted Supervisorly Flash in Macro 816"
|
|
group.byte 0x731++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH817,Uncommitted Supervisorly Flash in Macro 817"
|
|
group.byte 0x732++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH818,Uncommitted Supervisorly Flash in Macro 818"
|
|
group.byte 0x733++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH819,Uncommitted Supervisorly Flash in Macro 819"
|
|
group.byte 0x734++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH820,Uncommitted Supervisorly Flash in Macro 820"
|
|
group.byte 0x735++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH821,Uncommitted Supervisorly Flash in Macro 821"
|
|
group.byte 0x736++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH822,Uncommitted Supervisorly Flash in Macro 822"
|
|
group.byte 0x737++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH823,Uncommitted Supervisorly Flash in Macro 823"
|
|
group.byte 0x738++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH824,Uncommitted Supervisorly Flash in Macro 824"
|
|
group.byte 0x739++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH825,Uncommitted Supervisorly Flash in Macro 825"
|
|
group.byte 0x73A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH826,Uncommitted Supervisorly Flash in Macro 826"
|
|
group.byte 0x73B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH827,Uncommitted Supervisorly Flash in Macro 827"
|
|
group.byte 0x73C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH828,Uncommitted Supervisorly Flash in Macro 828"
|
|
group.byte 0x73D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH829,Uncommitted Supervisorly Flash in Macro 829"
|
|
group.byte 0x73E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH830,Uncommitted Supervisorly Flash in Macro 830"
|
|
group.byte 0x73F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH831,Uncommitted Supervisorly Flash in Macro 831"
|
|
group.byte 0x740++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH832,Uncommitted Supervisorly Flash in Macro 832"
|
|
group.byte 0x741++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH833,Uncommitted Supervisorly Flash in Macro 833"
|
|
group.byte 0x742++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH834,Uncommitted Supervisorly Flash in Macro 834"
|
|
group.byte 0x743++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH835,Uncommitted Supervisorly Flash in Macro 835"
|
|
group.byte 0x744++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH836,Uncommitted Supervisorly Flash in Macro 836"
|
|
group.byte 0x745++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH837,Uncommitted Supervisorly Flash in Macro 837"
|
|
group.byte 0x746++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH838,Uncommitted Supervisorly Flash in Macro 838"
|
|
group.byte 0x747++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH839,Uncommitted Supervisorly Flash in Macro 839"
|
|
group.byte 0x748++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH840,Uncommitted Supervisorly Flash in Macro 840"
|
|
group.byte 0x749++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH841,Uncommitted Supervisorly Flash in Macro 841"
|
|
group.byte 0x74A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH842,Uncommitted Supervisorly Flash in Macro 842"
|
|
group.byte 0x74B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH843,Uncommitted Supervisorly Flash in Macro 843"
|
|
group.byte 0x74C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH844,Uncommitted Supervisorly Flash in Macro 844"
|
|
group.byte 0x74D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH845,Uncommitted Supervisorly Flash in Macro 845"
|
|
group.byte 0x74E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH846,Uncommitted Supervisorly Flash in Macro 846"
|
|
group.byte 0x74F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH847,Uncommitted Supervisorly Flash in Macro 847"
|
|
group.byte 0x750++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH848,Uncommitted Supervisorly Flash in Macro 848"
|
|
group.byte 0x751++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH849,Uncommitted Supervisorly Flash in Macro 849"
|
|
group.byte 0x752++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH850,Uncommitted Supervisorly Flash in Macro 850"
|
|
group.byte 0x753++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH851,Uncommitted Supervisorly Flash in Macro 851"
|
|
group.byte 0x754++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH852,Uncommitted Supervisorly Flash in Macro 852"
|
|
group.byte 0x755++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH853,Uncommitted Supervisorly Flash in Macro 853"
|
|
group.byte 0x756++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH854,Uncommitted Supervisorly Flash in Macro 854"
|
|
group.byte 0x757++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH855,Uncommitted Supervisorly Flash in Macro 855"
|
|
group.byte 0x758++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH856,Uncommitted Supervisorly Flash in Macro 856"
|
|
group.byte 0x759++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH857,Uncommitted Supervisorly Flash in Macro 857"
|
|
group.byte 0x75A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH858,Uncommitted Supervisorly Flash in Macro 858"
|
|
group.byte 0x75B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH859,Uncommitted Supervisorly Flash in Macro 859"
|
|
group.byte 0x75C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH860,Uncommitted Supervisorly Flash in Macro 860"
|
|
group.byte 0x75D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH861,Uncommitted Supervisorly Flash in Macro 861"
|
|
group.byte 0x75E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH862,Uncommitted Supervisorly Flash in Macro 862"
|
|
group.byte 0x75F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH863,Uncommitted Supervisorly Flash in Macro 863"
|
|
group.byte 0x760++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH864,Uncommitted Supervisorly Flash in Macro 864"
|
|
group.byte 0x761++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH865,Uncommitted Supervisorly Flash in Macro 865"
|
|
group.byte 0x762++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH866,Uncommitted Supervisorly Flash in Macro 866"
|
|
group.byte 0x763++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH867,Uncommitted Supervisorly Flash in Macro 867"
|
|
group.byte 0x764++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH868,Uncommitted Supervisorly Flash in Macro 868"
|
|
group.byte 0x765++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH869,Uncommitted Supervisorly Flash in Macro 869"
|
|
group.byte 0x766++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH870,Uncommitted Supervisorly Flash in Macro 870"
|
|
group.byte 0x767++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH871,Uncommitted Supervisorly Flash in Macro 871"
|
|
group.byte 0x768++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH872,Uncommitted Supervisorly Flash in Macro 872"
|
|
group.byte 0x769++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH873,Uncommitted Supervisorly Flash in Macro 873"
|
|
group.byte 0x76A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH874,Uncommitted Supervisorly Flash in Macro 874"
|
|
group.byte 0x76B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH875,Uncommitted Supervisorly Flash in Macro 875"
|
|
group.byte 0x76C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH876,Uncommitted Supervisorly Flash in Macro 876"
|
|
group.byte 0x76D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH877,Uncommitted Supervisorly Flash in Macro 877"
|
|
group.byte 0x76E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH878,Uncommitted Supervisorly Flash in Macro 878"
|
|
group.byte 0x76F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH879,Uncommitted Supervisorly Flash in Macro 879"
|
|
group.byte 0x770++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH880,Uncommitted Supervisorly Flash in Macro 880"
|
|
group.byte 0x771++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH881,Uncommitted Supervisorly Flash in Macro 881"
|
|
group.byte 0x772++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH882,Uncommitted Supervisorly Flash in Macro 882"
|
|
group.byte 0x773++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH883,Uncommitted Supervisorly Flash in Macro 883"
|
|
group.byte 0x774++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH884,Uncommitted Supervisorly Flash in Macro 884"
|
|
group.byte 0x775++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH885,Uncommitted Supervisorly Flash in Macro 885"
|
|
group.byte 0x776++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH886,Uncommitted Supervisorly Flash in Macro 886"
|
|
group.byte 0x777++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH887,Uncommitted Supervisorly Flash in Macro 887"
|
|
group.byte 0x778++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH888,Uncommitted Supervisorly Flash in Macro 888"
|
|
group.byte 0x779++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH889,Uncommitted Supervisorly Flash in Macro 889"
|
|
group.byte 0x77A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH890,Uncommitted Supervisorly Flash in Macro 890"
|
|
group.byte 0x77B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH891,Uncommitted Supervisorly Flash in Macro 891"
|
|
group.byte 0x77C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH892,Uncommitted Supervisorly Flash in Macro 892"
|
|
group.byte 0x77D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH893,Uncommitted Supervisorly Flash in Macro 893"
|
|
group.byte 0x77E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH894,Uncommitted Supervisorly Flash in Macro 894"
|
|
group.byte 0x77F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH895,Uncommitted Supervisorly Flash in Macro 895"
|
|
group.byte 0x780++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH896,Uncommitted Supervisorly Flash in Macro 896"
|
|
group.byte 0x781++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH897,Uncommitted Supervisorly Flash in Macro 897"
|
|
group.byte 0x782++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH898,Uncommitted Supervisorly Flash in Macro 898"
|
|
group.byte 0x783++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH899,Uncommitted Supervisorly Flash in Macro 899"
|
|
group.byte 0x784++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH900,Uncommitted Supervisorly Flash in Macro 900"
|
|
group.byte 0x785++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH901,Uncommitted Supervisorly Flash in Macro 901"
|
|
group.byte 0x786++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH902,Uncommitted Supervisorly Flash in Macro 902"
|
|
group.byte 0x787++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH903,Uncommitted Supervisorly Flash in Macro 903"
|
|
group.byte 0x788++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH904,Uncommitted Supervisorly Flash in Macro 904"
|
|
group.byte 0x789++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH905,Uncommitted Supervisorly Flash in Macro 905"
|
|
group.byte 0x78A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH906,Uncommitted Supervisorly Flash in Macro 906"
|
|
group.byte 0x78B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH907,Uncommitted Supervisorly Flash in Macro 907"
|
|
group.byte 0x78C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH908,Uncommitted Supervisorly Flash in Macro 908"
|
|
group.byte 0x78D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH909,Uncommitted Supervisorly Flash in Macro 909"
|
|
group.byte 0x78E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH910,Uncommitted Supervisorly Flash in Macro 910"
|
|
group.byte 0x78F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH911,Uncommitted Supervisorly Flash in Macro 911"
|
|
group.byte 0x790++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH912,Uncommitted Supervisorly Flash in Macro 912"
|
|
group.byte 0x791++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH913,Uncommitted Supervisorly Flash in Macro 913"
|
|
group.byte 0x792++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH914,Uncommitted Supervisorly Flash in Macro 914"
|
|
group.byte 0x793++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH915,Uncommitted Supervisorly Flash in Macro 915"
|
|
group.byte 0x794++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH916,Uncommitted Supervisorly Flash in Macro 916"
|
|
group.byte 0x795++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH917,Uncommitted Supervisorly Flash in Macro 917"
|
|
group.byte 0x796++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH918,Uncommitted Supervisorly Flash in Macro 918"
|
|
group.byte 0x797++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH919,Uncommitted Supervisorly Flash in Macro 919"
|
|
group.byte 0x798++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH920,Uncommitted Supervisorly Flash in Macro 920"
|
|
group.byte 0x799++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH921,Uncommitted Supervisorly Flash in Macro 921"
|
|
group.byte 0x79A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH922,Uncommitted Supervisorly Flash in Macro 922"
|
|
group.byte 0x79B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH923,Uncommitted Supervisorly Flash in Macro 923"
|
|
group.byte 0x79C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH924,Uncommitted Supervisorly Flash in Macro 924"
|
|
group.byte 0x79D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH925,Uncommitted Supervisorly Flash in Macro 925"
|
|
group.byte 0x79E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH926,Uncommitted Supervisorly Flash in Macro 926"
|
|
group.byte 0x79F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH927,Uncommitted Supervisorly Flash in Macro 927"
|
|
group.byte 0x7A0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH928,Uncommitted Supervisorly Flash in Macro 928"
|
|
group.byte 0x7A1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH929,Uncommitted Supervisorly Flash in Macro 929"
|
|
group.byte 0x7A2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH930,Uncommitted Supervisorly Flash in Macro 930"
|
|
group.byte 0x7A3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH931,Uncommitted Supervisorly Flash in Macro 931"
|
|
group.byte 0x7A4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH932,Uncommitted Supervisorly Flash in Macro 932"
|
|
group.byte 0x7A5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH933,Uncommitted Supervisorly Flash in Macro 933"
|
|
group.byte 0x7A6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH934,Uncommitted Supervisorly Flash in Macro 934"
|
|
group.byte 0x7A7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH935,Uncommitted Supervisorly Flash in Macro 935"
|
|
group.byte 0x7A8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH936,Uncommitted Supervisorly Flash in Macro 936"
|
|
group.byte 0x7A9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH937,Uncommitted Supervisorly Flash in Macro 937"
|
|
group.byte 0x7AA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH938,Uncommitted Supervisorly Flash in Macro 938"
|
|
group.byte 0x7AB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH939,Uncommitted Supervisorly Flash in Macro 939"
|
|
group.byte 0x7AC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH940,Uncommitted Supervisorly Flash in Macro 940"
|
|
group.byte 0x7AD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH941,Uncommitted Supervisorly Flash in Macro 941"
|
|
group.byte 0x7AE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH942,Uncommitted Supervisorly Flash in Macro 942"
|
|
group.byte 0x7AF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH943,Uncommitted Supervisorly Flash in Macro 943"
|
|
group.byte 0x7B0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH944,Uncommitted Supervisorly Flash in Macro 944"
|
|
group.byte 0x7B1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH945,Uncommitted Supervisorly Flash in Macro 945"
|
|
group.byte 0x7B2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH946,Uncommitted Supervisorly Flash in Macro 946"
|
|
group.byte 0x7B3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH947,Uncommitted Supervisorly Flash in Macro 947"
|
|
group.byte 0x7B4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH948,Uncommitted Supervisorly Flash in Macro 948"
|
|
group.byte 0x7B5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH949,Uncommitted Supervisorly Flash in Macro 949"
|
|
group.byte 0x7B6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH950,Uncommitted Supervisorly Flash in Macro 950"
|
|
group.byte 0x7B7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH951,Uncommitted Supervisorly Flash in Macro 951"
|
|
group.byte 0x7B8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH952,Uncommitted Supervisorly Flash in Macro 952"
|
|
group.byte 0x7B9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH953,Uncommitted Supervisorly Flash in Macro 953"
|
|
group.byte 0x7BA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH954,Uncommitted Supervisorly Flash in Macro 954"
|
|
group.byte 0x7BB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH955,Uncommitted Supervisorly Flash in Macro 955"
|
|
group.byte 0x7BC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH956,Uncommitted Supervisorly Flash in Macro 956"
|
|
group.byte 0x7BD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH957,Uncommitted Supervisorly Flash in Macro 957"
|
|
group.byte 0x7BE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH958,Uncommitted Supervisorly Flash in Macro 958"
|
|
group.byte 0x7BF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH959,Uncommitted Supervisorly Flash in Macro 959"
|
|
group.byte 0x7C0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH960,Uncommitted Supervisorly Flash in Macro 960"
|
|
group.byte 0x7C1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH961,Uncommitted Supervisorly Flash in Macro 961"
|
|
group.byte 0x7C2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH962,Uncommitted Supervisorly Flash in Macro 962"
|
|
group.byte 0x7C3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH963,Uncommitted Supervisorly Flash in Macro 963"
|
|
group.byte 0x7C4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH964,Uncommitted Supervisorly Flash in Macro 964"
|
|
group.byte 0x7C5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH965,Uncommitted Supervisorly Flash in Macro 965"
|
|
group.byte 0x7C6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH966,Uncommitted Supervisorly Flash in Macro 966"
|
|
group.byte 0x7C7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH967,Uncommitted Supervisorly Flash in Macro 967"
|
|
group.byte 0x7C8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH968,Uncommitted Supervisorly Flash in Macro 968"
|
|
group.byte 0x7C9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH969,Uncommitted Supervisorly Flash in Macro 969"
|
|
group.byte 0x7CA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH970,Uncommitted Supervisorly Flash in Macro 970"
|
|
group.byte 0x7CB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH971,Uncommitted Supervisorly Flash in Macro 971"
|
|
group.byte 0x7CC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH972,Uncommitted Supervisorly Flash in Macro 972"
|
|
group.byte 0x7CD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH973,Uncommitted Supervisorly Flash in Macro 973"
|
|
group.byte 0x7CE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH974,Uncommitted Supervisorly Flash in Macro 974"
|
|
group.byte 0x7CF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH975,Uncommitted Supervisorly Flash in Macro 975"
|
|
group.byte 0x7D0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH976,Uncommitted Supervisorly Flash in Macro 976"
|
|
group.byte 0x7D1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH977,Uncommitted Supervisorly Flash in Macro 977"
|
|
group.byte 0x7D2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH978,Uncommitted Supervisorly Flash in Macro 978"
|
|
group.byte 0x7D3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH979,Uncommitted Supervisorly Flash in Macro 979"
|
|
group.byte 0x7D4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH980,Uncommitted Supervisorly Flash in Macro 980"
|
|
group.byte 0x7D5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH981,Uncommitted Supervisorly Flash in Macro 981"
|
|
group.byte 0x7D6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH982,Uncommitted Supervisorly Flash in Macro 982"
|
|
group.byte 0x7D7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH983,Uncommitted Supervisorly Flash in Macro 983"
|
|
group.byte 0x7D8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH984,Uncommitted Supervisorly Flash in Macro 984"
|
|
group.byte 0x7D9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH985,Uncommitted Supervisorly Flash in Macro 985"
|
|
group.byte 0x7DA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH986,Uncommitted Supervisorly Flash in Macro 986"
|
|
group.byte 0x7DB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH987,Uncommitted Supervisorly Flash in Macro 987"
|
|
group.byte 0x7DC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH988,Uncommitted Supervisorly Flash in Macro 988"
|
|
group.byte 0x7DD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH989,Uncommitted Supervisorly Flash in Macro 989"
|
|
group.byte 0x7DE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH990,Uncommitted Supervisorly Flash in Macro 990"
|
|
group.byte 0x7DF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH991,Uncommitted Supervisorly Flash in Macro 991"
|
|
group.byte 0x7E0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH992,Uncommitted Supervisorly Flash in Macro 992"
|
|
group.byte 0x7E1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH993,Uncommitted Supervisorly Flash in Macro 993"
|
|
group.byte 0x7E2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH994,Uncommitted Supervisorly Flash in Macro 994"
|
|
group.byte 0x7E3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH995,Uncommitted Supervisorly Flash in Macro 995"
|
|
group.byte 0x7E4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH996,Uncommitted Supervisorly Flash in Macro 996"
|
|
group.byte 0x7E5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH997,Uncommitted Supervisorly Flash in Macro 997"
|
|
group.byte 0x7E6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH998,Uncommitted Supervisorly Flash in Macro 998"
|
|
group.byte 0x7E7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH999,Uncommitted Supervisorly Flash in Macro 999"
|
|
group.byte 0x7E8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1000,Uncommitted Supervisorly Flash in Macro 1000"
|
|
group.byte 0x7E9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1001,Uncommitted Supervisorly Flash in Macro 1001"
|
|
group.byte 0x7EA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1002,Uncommitted Supervisorly Flash in Macro 1002"
|
|
group.byte 0x7EB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1003,Uncommitted Supervisorly Flash in Macro 1003"
|
|
group.byte 0x7EC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1004,Uncommitted Supervisorly Flash in Macro 1004"
|
|
group.byte 0x7ED++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1005,Uncommitted Supervisorly Flash in Macro 1005"
|
|
group.byte 0x7EE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1006,Uncommitted Supervisorly Flash in Macro 1006"
|
|
group.byte 0x7EF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1007,Uncommitted Supervisorly Flash in Macro 1007"
|
|
group.byte 0x7F0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1008,Uncommitted Supervisorly Flash in Macro 1008"
|
|
group.byte 0x7F1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1009,Uncommitted Supervisorly Flash in Macro 1009"
|
|
group.byte 0x7F2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1010,Uncommitted Supervisorly Flash in Macro 1010"
|
|
group.byte 0x7F3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1011,Uncommitted Supervisorly Flash in Macro 1011"
|
|
group.byte 0x7F4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1012,Uncommitted Supervisorly Flash in Macro 1012"
|
|
group.byte 0x7F5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1013,Uncommitted Supervisorly Flash in Macro 1013"
|
|
group.byte 0x7F6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1014,Uncommitted Supervisorly Flash in Macro 1014"
|
|
group.byte 0x7F7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1015,Uncommitted Supervisorly Flash in Macro 1015"
|
|
group.byte 0x7F8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1016,Uncommitted Supervisorly Flash in Macro 1016"
|
|
group.byte 0x7F9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1017,Uncommitted Supervisorly Flash in Macro 1017"
|
|
group.byte 0x7FA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1018,Uncommitted Supervisorly Flash in Macro 1018"
|
|
group.byte 0x7FB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1019,Uncommitted Supervisorly Flash in Macro 1019"
|
|
group.byte 0x7FC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1020,Uncommitted Supervisorly Flash in Macro 1020"
|
|
group.byte 0x7FD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1021,Uncommitted Supervisorly Flash in Macro 1021"
|
|
group.byte 0x7FE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1022,Uncommitted Supervisorly Flash in Macro 1022"
|
|
group.byte 0x7FF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1023,Uncommitted Supervisorly Flash in Macro 1023"
|
|
else
|
|
group.byte 0x350++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH0,Uncommitted Supervisorly Flash in Macro 0"
|
|
group.byte 0x351++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1,Uncommitted Supervisorly Flash in Macro 1"
|
|
group.byte 0x352++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH2,Uncommitted Supervisorly Flash in Macro 2"
|
|
group.byte 0x353++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH3,Uncommitted Supervisorly Flash in Macro 3"
|
|
group.byte 0x354++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH4,Uncommitted Supervisorly Flash in Macro 4"
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH5,Uncommitted Supervisorly Flash in Macro 5"
|
|
group.byte 0x356++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH6,Uncommitted Supervisorly Flash in Macro 6"
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH7,Uncommitted Supervisorly Flash in Macro 7"
|
|
group.byte 0x358++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH8,Uncommitted Supervisorly Flash in Macro 8"
|
|
group.byte 0x359++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH9,Uncommitted Supervisorly Flash in Macro 9"
|
|
group.byte 0x35A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH10,Uncommitted Supervisorly Flash in Macro 10"
|
|
group.byte 0x35B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH11,Uncommitted Supervisorly Flash in Macro 11"
|
|
group.byte 0x35C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH12,Uncommitted Supervisorly Flash in Macro 12"
|
|
group.byte 0x35D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH13,Uncommitted Supervisorly Flash in Macro 13"
|
|
group.byte 0x35E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH14,Uncommitted Supervisorly Flash in Macro 14"
|
|
group.byte 0x35F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH15,Uncommitted Supervisorly Flash in Macro 15"
|
|
group.byte 0x360++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH16,Uncommitted Supervisorly Flash in Macro 16"
|
|
group.byte 0x361++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH17,Uncommitted Supervisorly Flash in Macro 17"
|
|
group.byte 0x362++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH18,Uncommitted Supervisorly Flash in Macro 18"
|
|
group.byte 0x363++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH19,Uncommitted Supervisorly Flash in Macro 19"
|
|
group.byte 0x364++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH20,Uncommitted Supervisorly Flash in Macro 20"
|
|
group.byte 0x365++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH21,Uncommitted Supervisorly Flash in Macro 21"
|
|
group.byte 0x366++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH22,Uncommitted Supervisorly Flash in Macro 22"
|
|
group.byte 0x367++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH23,Uncommitted Supervisorly Flash in Macro 23"
|
|
group.byte 0x368++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH24,Uncommitted Supervisorly Flash in Macro 24"
|
|
group.byte 0x369++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH25,Uncommitted Supervisorly Flash in Macro 25"
|
|
group.byte 0x36A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH26,Uncommitted Supervisorly Flash in Macro 26"
|
|
group.byte 0x36B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH27,Uncommitted Supervisorly Flash in Macro 27"
|
|
group.byte 0x36C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH28,Uncommitted Supervisorly Flash in Macro 28"
|
|
group.byte 0x36D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH29,Uncommitted Supervisorly Flash in Macro 29"
|
|
group.byte 0x36E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH30,Uncommitted Supervisorly Flash in Macro 30"
|
|
group.byte 0x36F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH31,Uncommitted Supervisorly Flash in Macro 31"
|
|
group.byte 0x370++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH32,Uncommitted Supervisorly Flash in Macro 32"
|
|
group.byte 0x371++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH33,Uncommitted Supervisorly Flash in Macro 33"
|
|
group.byte 0x372++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH34,Uncommitted Supervisorly Flash in Macro 34"
|
|
group.byte 0x373++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH35,Uncommitted Supervisorly Flash in Macro 35"
|
|
group.byte 0x374++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH36,Uncommitted Supervisorly Flash in Macro 36"
|
|
group.byte 0x375++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH37,Uncommitted Supervisorly Flash in Macro 37"
|
|
group.byte 0x376++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH38,Uncommitted Supervisorly Flash in Macro 38"
|
|
group.byte 0x377++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH39,Uncommitted Supervisorly Flash in Macro 39"
|
|
group.byte 0x378++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH40,Uncommitted Supervisorly Flash in Macro 40"
|
|
group.byte 0x379++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH41,Uncommitted Supervisorly Flash in Macro 41"
|
|
group.byte 0x37A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH42,Uncommitted Supervisorly Flash in Macro 42"
|
|
group.byte 0x37B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH43,Uncommitted Supervisorly Flash in Macro 43"
|
|
group.byte 0x37C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH44,Uncommitted Supervisorly Flash in Macro 44"
|
|
group.byte 0x37D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH45,Uncommitted Supervisorly Flash in Macro 45"
|
|
group.byte 0x37E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH46,Uncommitted Supervisorly Flash in Macro 46"
|
|
group.byte 0x37F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH47,Uncommitted Supervisorly Flash in Macro 47"
|
|
group.byte 0x380++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH48,Uncommitted Supervisorly Flash in Macro 48"
|
|
group.byte 0x381++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH49,Uncommitted Supervisorly Flash in Macro 49"
|
|
group.byte 0x382++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH50,Uncommitted Supervisorly Flash in Macro 50"
|
|
group.byte 0x383++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH51,Uncommitted Supervisorly Flash in Macro 51"
|
|
group.byte 0x384++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH52,Uncommitted Supervisorly Flash in Macro 52"
|
|
group.byte 0x385++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH53,Uncommitted Supervisorly Flash in Macro 53"
|
|
group.byte 0x386++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH54,Uncommitted Supervisorly Flash in Macro 54"
|
|
group.byte 0x387++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH55,Uncommitted Supervisorly Flash in Macro 55"
|
|
group.byte 0x388++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH56,Uncommitted Supervisorly Flash in Macro 56"
|
|
group.byte 0x389++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH57,Uncommitted Supervisorly Flash in Macro 57"
|
|
group.byte 0x38A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH58,Uncommitted Supervisorly Flash in Macro 58"
|
|
group.byte 0x38B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH59,Uncommitted Supervisorly Flash in Macro 59"
|
|
group.byte 0x38C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH60,Uncommitted Supervisorly Flash in Macro 60"
|
|
group.byte 0x38D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH61,Uncommitted Supervisorly Flash in Macro 61"
|
|
group.byte 0x38E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH62,Uncommitted Supervisorly Flash in Macro 62"
|
|
group.byte 0x38F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH63,Uncommitted Supervisorly Flash in Macro 63"
|
|
group.byte 0x390++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH64,Uncommitted Supervisorly Flash in Macro 64"
|
|
group.byte 0x391++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH65,Uncommitted Supervisorly Flash in Macro 65"
|
|
group.byte 0x392++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH66,Uncommitted Supervisorly Flash in Macro 66"
|
|
group.byte 0x393++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH67,Uncommitted Supervisorly Flash in Macro 67"
|
|
group.byte 0x394++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH68,Uncommitted Supervisorly Flash in Macro 68"
|
|
group.byte 0x395++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH69,Uncommitted Supervisorly Flash in Macro 69"
|
|
group.byte 0x396++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH70,Uncommitted Supervisorly Flash in Macro 70"
|
|
group.byte 0x397++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH71,Uncommitted Supervisorly Flash in Macro 71"
|
|
group.byte 0x398++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH72,Uncommitted Supervisorly Flash in Macro 72"
|
|
group.byte 0x399++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH73,Uncommitted Supervisorly Flash in Macro 73"
|
|
group.byte 0x39A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH74,Uncommitted Supervisorly Flash in Macro 74"
|
|
group.byte 0x39B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH75,Uncommitted Supervisorly Flash in Macro 75"
|
|
group.byte 0x39C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH76,Uncommitted Supervisorly Flash in Macro 76"
|
|
group.byte 0x39D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH77,Uncommitted Supervisorly Flash in Macro 77"
|
|
group.byte 0x39E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH78,Uncommitted Supervisorly Flash in Macro 78"
|
|
group.byte 0x39F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH79,Uncommitted Supervisorly Flash in Macro 79"
|
|
group.byte 0x3A0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH80,Uncommitted Supervisorly Flash in Macro 80"
|
|
group.byte 0x3A1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH81,Uncommitted Supervisorly Flash in Macro 81"
|
|
group.byte 0x3A2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH82,Uncommitted Supervisorly Flash in Macro 82"
|
|
group.byte 0x3A3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH83,Uncommitted Supervisorly Flash in Macro 83"
|
|
group.byte 0x3A4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH84,Uncommitted Supervisorly Flash in Macro 84"
|
|
group.byte 0x3A5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH85,Uncommitted Supervisorly Flash in Macro 85"
|
|
group.byte 0x3A6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH86,Uncommitted Supervisorly Flash in Macro 86"
|
|
group.byte 0x3A7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH87,Uncommitted Supervisorly Flash in Macro 87"
|
|
group.byte 0x3A8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH88,Uncommitted Supervisorly Flash in Macro 88"
|
|
group.byte 0x3A9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH89,Uncommitted Supervisorly Flash in Macro 89"
|
|
group.byte 0x3AA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH90,Uncommitted Supervisorly Flash in Macro 90"
|
|
group.byte 0x3AB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH91,Uncommitted Supervisorly Flash in Macro 91"
|
|
group.byte 0x3AC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH92,Uncommitted Supervisorly Flash in Macro 92"
|
|
group.byte 0x3AD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH93,Uncommitted Supervisorly Flash in Macro 93"
|
|
group.byte 0x3AE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH94,Uncommitted Supervisorly Flash in Macro 94"
|
|
group.byte 0x3AF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH95,Uncommitted Supervisorly Flash in Macro 95"
|
|
group.byte 0x3B0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH96,Uncommitted Supervisorly Flash in Macro 96"
|
|
group.byte 0x3B1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH97,Uncommitted Supervisorly Flash in Macro 97"
|
|
group.byte 0x3B2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH98,Uncommitted Supervisorly Flash in Macro 98"
|
|
group.byte 0x3B3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH99,Uncommitted Supervisorly Flash in Macro 99"
|
|
group.byte 0x3B4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH100,Uncommitted Supervisorly Flash in Macro 100"
|
|
group.byte 0x3B5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH101,Uncommitted Supervisorly Flash in Macro 101"
|
|
group.byte 0x3B6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH102,Uncommitted Supervisorly Flash in Macro 102"
|
|
group.byte 0x3B7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH103,Uncommitted Supervisorly Flash in Macro 103"
|
|
group.byte 0x3B8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH104,Uncommitted Supervisorly Flash in Macro 104"
|
|
group.byte 0x3B9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH105,Uncommitted Supervisorly Flash in Macro 105"
|
|
group.byte 0x3BA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH106,Uncommitted Supervisorly Flash in Macro 106"
|
|
group.byte 0x3BB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH107,Uncommitted Supervisorly Flash in Macro 107"
|
|
group.byte 0x3BC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH108,Uncommitted Supervisorly Flash in Macro 108"
|
|
group.byte 0x3BD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH109,Uncommitted Supervisorly Flash in Macro 109"
|
|
group.byte 0x3BE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH110,Uncommitted Supervisorly Flash in Macro 110"
|
|
group.byte 0x3BF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH111,Uncommitted Supervisorly Flash in Macro 111"
|
|
group.byte 0x3C0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH112,Uncommitted Supervisorly Flash in Macro 112"
|
|
group.byte 0x3C1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH113,Uncommitted Supervisorly Flash in Macro 113"
|
|
group.byte 0x3C2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH114,Uncommitted Supervisorly Flash in Macro 114"
|
|
group.byte 0x3C3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH115,Uncommitted Supervisorly Flash in Macro 115"
|
|
group.byte 0x3C4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH116,Uncommitted Supervisorly Flash in Macro 116"
|
|
group.byte 0x3C5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH117,Uncommitted Supervisorly Flash in Macro 117"
|
|
group.byte 0x3C6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH118,Uncommitted Supervisorly Flash in Macro 118"
|
|
group.byte 0x3C7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH119,Uncommitted Supervisorly Flash in Macro 119"
|
|
group.byte 0x3C8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH120,Uncommitted Supervisorly Flash in Macro 120"
|
|
group.byte 0x3C9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH121,Uncommitted Supervisorly Flash in Macro 121"
|
|
group.byte 0x3CA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH122,Uncommitted Supervisorly Flash in Macro 122"
|
|
group.byte 0x3CB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH123,Uncommitted Supervisorly Flash in Macro 123"
|
|
group.byte 0x3CC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH124,Uncommitted Supervisorly Flash in Macro 124"
|
|
group.byte 0x3CD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH125,Uncommitted Supervisorly Flash in Macro 125"
|
|
group.byte 0x3CE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH126,Uncommitted Supervisorly Flash in Macro 126"
|
|
group.byte 0x3CF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH127,Uncommitted Supervisorly Flash in Macro 127"
|
|
group.byte 0x3D0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH128,Uncommitted Supervisorly Flash in Macro 128"
|
|
group.byte 0x3D1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH129,Uncommitted Supervisorly Flash in Macro 129"
|
|
group.byte 0x3D2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH130,Uncommitted Supervisorly Flash in Macro 130"
|
|
group.byte 0x3D3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH131,Uncommitted Supervisorly Flash in Macro 131"
|
|
group.byte 0x3D4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH132,Uncommitted Supervisorly Flash in Macro 132"
|
|
group.byte 0x3D5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH133,Uncommitted Supervisorly Flash in Macro 133"
|
|
group.byte 0x3D6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH134,Uncommitted Supervisorly Flash in Macro 134"
|
|
group.byte 0x3D7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH135,Uncommitted Supervisorly Flash in Macro 135"
|
|
group.byte 0x3D8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH136,Uncommitted Supervisorly Flash in Macro 136"
|
|
group.byte 0x3D9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH137,Uncommitted Supervisorly Flash in Macro 137"
|
|
group.byte 0x3DA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH138,Uncommitted Supervisorly Flash in Macro 138"
|
|
group.byte 0x3DB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH139,Uncommitted Supervisorly Flash in Macro 139"
|
|
group.byte 0x3DC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH140,Uncommitted Supervisorly Flash in Macro 140"
|
|
group.byte 0x3DD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH141,Uncommitted Supervisorly Flash in Macro 141"
|
|
group.byte 0x3DE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH142,Uncommitted Supervisorly Flash in Macro 142"
|
|
group.byte 0x3DF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH143,Uncommitted Supervisorly Flash in Macro 143"
|
|
group.byte 0x3E0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH144,Uncommitted Supervisorly Flash in Macro 144"
|
|
group.byte 0x3E1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH145,Uncommitted Supervisorly Flash in Macro 145"
|
|
group.byte 0x3E2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH146,Uncommitted Supervisorly Flash in Macro 146"
|
|
group.byte 0x3E3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH147,Uncommitted Supervisorly Flash in Macro 147"
|
|
group.byte 0x3E4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH148,Uncommitted Supervisorly Flash in Macro 148"
|
|
group.byte 0x3E5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH149,Uncommitted Supervisorly Flash in Macro 149"
|
|
group.byte 0x3E6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH150,Uncommitted Supervisorly Flash in Macro 150"
|
|
group.byte 0x3E7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH151,Uncommitted Supervisorly Flash in Macro 151"
|
|
group.byte 0x3E8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH152,Uncommitted Supervisorly Flash in Macro 152"
|
|
group.byte 0x3E9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH153,Uncommitted Supervisorly Flash in Macro 153"
|
|
group.byte 0x3EA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH154,Uncommitted Supervisorly Flash in Macro 154"
|
|
group.byte 0x3EB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH155,Uncommitted Supervisorly Flash in Macro 155"
|
|
group.byte 0x3EC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH156,Uncommitted Supervisorly Flash in Macro 156"
|
|
group.byte 0x3ED++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH157,Uncommitted Supervisorly Flash in Macro 157"
|
|
group.byte 0x3EE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH158,Uncommitted Supervisorly Flash in Macro 158"
|
|
group.byte 0x3EF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH159,Uncommitted Supervisorly Flash in Macro 159"
|
|
group.byte 0x3F0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH160,Uncommitted Supervisorly Flash in Macro 160"
|
|
group.byte 0x3F1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH161,Uncommitted Supervisorly Flash in Macro 161"
|
|
group.byte 0x3F2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH162,Uncommitted Supervisorly Flash in Macro 162"
|
|
group.byte 0x3F3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH163,Uncommitted Supervisorly Flash in Macro 163"
|
|
group.byte 0x3F4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH164,Uncommitted Supervisorly Flash in Macro 164"
|
|
group.byte 0x3F5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH165,Uncommitted Supervisorly Flash in Macro 165"
|
|
group.byte 0x3F6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH166,Uncommitted Supervisorly Flash in Macro 166"
|
|
group.byte 0x3F7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH167,Uncommitted Supervisorly Flash in Macro 167"
|
|
group.byte 0x3F8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH168,Uncommitted Supervisorly Flash in Macro 168"
|
|
group.byte 0x3F9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH169,Uncommitted Supervisorly Flash in Macro 169"
|
|
group.byte 0x3FA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH170,Uncommitted Supervisorly Flash in Macro 170"
|
|
group.byte 0x3FB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH171,Uncommitted Supervisorly Flash in Macro 171"
|
|
group.byte 0x3FC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH172,Uncommitted Supervisorly Flash in Macro 172"
|
|
group.byte 0x3FD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH173,Uncommitted Supervisorly Flash in Macro 173"
|
|
group.byte 0x3FE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH174,Uncommitted Supervisorly Flash in Macro 174"
|
|
group.byte 0x3FF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH175,Uncommitted Supervisorly Flash in Macro 175"
|
|
group.byte 0x400++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH176,Uncommitted Supervisorly Flash in Macro 176"
|
|
group.byte 0x401++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH177,Uncommitted Supervisorly Flash in Macro 177"
|
|
group.byte 0x402++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH178,Uncommitted Supervisorly Flash in Macro 178"
|
|
group.byte 0x403++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH179,Uncommitted Supervisorly Flash in Macro 179"
|
|
group.byte 0x404++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH180,Uncommitted Supervisorly Flash in Macro 180"
|
|
group.byte 0x405++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH181,Uncommitted Supervisorly Flash in Macro 181"
|
|
group.byte 0x406++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH182,Uncommitted Supervisorly Flash in Macro 182"
|
|
group.byte 0x407++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH183,Uncommitted Supervisorly Flash in Macro 183"
|
|
group.byte 0x408++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH184,Uncommitted Supervisorly Flash in Macro 184"
|
|
group.byte 0x409++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH185,Uncommitted Supervisorly Flash in Macro 185"
|
|
group.byte 0x40A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH186,Uncommitted Supervisorly Flash in Macro 186"
|
|
group.byte 0x40B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH187,Uncommitted Supervisorly Flash in Macro 187"
|
|
group.byte 0x40C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH188,Uncommitted Supervisorly Flash in Macro 188"
|
|
group.byte 0x40D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH189,Uncommitted Supervisorly Flash in Macro 189"
|
|
group.byte 0x40E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH190,Uncommitted Supervisorly Flash in Macro 190"
|
|
group.byte 0x40F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH191,Uncommitted Supervisorly Flash in Macro 191"
|
|
group.byte 0x410++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH192,Uncommitted Supervisorly Flash in Macro 192"
|
|
group.byte 0x411++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH193,Uncommitted Supervisorly Flash in Macro 193"
|
|
group.byte 0x412++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH194,Uncommitted Supervisorly Flash in Macro 194"
|
|
group.byte 0x413++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH195,Uncommitted Supervisorly Flash in Macro 195"
|
|
group.byte 0x414++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH196,Uncommitted Supervisorly Flash in Macro 196"
|
|
group.byte 0x415++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH197,Uncommitted Supervisorly Flash in Macro 197"
|
|
group.byte 0x416++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH198,Uncommitted Supervisorly Flash in Macro 198"
|
|
group.byte 0x417++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH199,Uncommitted Supervisorly Flash in Macro 199"
|
|
group.byte 0x418++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH200,Uncommitted Supervisorly Flash in Macro 200"
|
|
group.byte 0x419++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH201,Uncommitted Supervisorly Flash in Macro 201"
|
|
group.byte 0x41A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH202,Uncommitted Supervisorly Flash in Macro 202"
|
|
group.byte 0x41B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH203,Uncommitted Supervisorly Flash in Macro 203"
|
|
group.byte 0x41C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH204,Uncommitted Supervisorly Flash in Macro 204"
|
|
group.byte 0x41D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH205,Uncommitted Supervisorly Flash in Macro 205"
|
|
group.byte 0x41E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH206,Uncommitted Supervisorly Flash in Macro 206"
|
|
group.byte 0x41F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH207,Uncommitted Supervisorly Flash in Macro 207"
|
|
group.byte 0x420++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH208,Uncommitted Supervisorly Flash in Macro 208"
|
|
group.byte 0x421++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH209,Uncommitted Supervisorly Flash in Macro 209"
|
|
group.byte 0x422++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH210,Uncommitted Supervisorly Flash in Macro 210"
|
|
group.byte 0x423++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH211,Uncommitted Supervisorly Flash in Macro 211"
|
|
group.byte 0x424++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH212,Uncommitted Supervisorly Flash in Macro 212"
|
|
group.byte 0x425++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH213,Uncommitted Supervisorly Flash in Macro 213"
|
|
group.byte 0x426++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH214,Uncommitted Supervisorly Flash in Macro 214"
|
|
group.byte 0x427++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH215,Uncommitted Supervisorly Flash in Macro 215"
|
|
group.byte 0x428++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH216,Uncommitted Supervisorly Flash in Macro 216"
|
|
group.byte 0x429++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH217,Uncommitted Supervisorly Flash in Macro 217"
|
|
group.byte 0x42A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH218,Uncommitted Supervisorly Flash in Macro 218"
|
|
group.byte 0x42B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH219,Uncommitted Supervisorly Flash in Macro 219"
|
|
group.byte 0x42C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH220,Uncommitted Supervisorly Flash in Macro 220"
|
|
group.byte 0x42D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH221,Uncommitted Supervisorly Flash in Macro 221"
|
|
group.byte 0x42E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH222,Uncommitted Supervisorly Flash in Macro 222"
|
|
group.byte 0x42F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH223,Uncommitted Supervisorly Flash in Macro 223"
|
|
group.byte 0x430++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH224,Uncommitted Supervisorly Flash in Macro 224"
|
|
group.byte 0x431++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH225,Uncommitted Supervisorly Flash in Macro 225"
|
|
group.byte 0x432++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH226,Uncommitted Supervisorly Flash in Macro 226"
|
|
group.byte 0x433++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH227,Uncommitted Supervisorly Flash in Macro 227"
|
|
group.byte 0x434++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH228,Uncommitted Supervisorly Flash in Macro 228"
|
|
group.byte 0x435++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH229,Uncommitted Supervisorly Flash in Macro 229"
|
|
group.byte 0x436++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH230,Uncommitted Supervisorly Flash in Macro 230"
|
|
group.byte 0x437++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH231,Uncommitted Supervisorly Flash in Macro 231"
|
|
group.byte 0x438++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH232,Uncommitted Supervisorly Flash in Macro 232"
|
|
group.byte 0x439++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH233,Uncommitted Supervisorly Flash in Macro 233"
|
|
group.byte 0x43A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH234,Uncommitted Supervisorly Flash in Macro 234"
|
|
group.byte 0x43B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH235,Uncommitted Supervisorly Flash in Macro 235"
|
|
group.byte 0x43C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH236,Uncommitted Supervisorly Flash in Macro 236"
|
|
group.byte 0x43D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH237,Uncommitted Supervisorly Flash in Macro 237"
|
|
group.byte 0x43E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH238,Uncommitted Supervisorly Flash in Macro 238"
|
|
group.byte 0x43F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH239,Uncommitted Supervisorly Flash in Macro 239"
|
|
group.byte 0x440++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH240,Uncommitted Supervisorly Flash in Macro 240"
|
|
group.byte 0x441++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH241,Uncommitted Supervisorly Flash in Macro 241"
|
|
group.byte 0x442++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH242,Uncommitted Supervisorly Flash in Macro 242"
|
|
group.byte 0x443++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH243,Uncommitted Supervisorly Flash in Macro 243"
|
|
group.byte 0x444++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH244,Uncommitted Supervisorly Flash in Macro 244"
|
|
group.byte 0x445++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH245,Uncommitted Supervisorly Flash in Macro 245"
|
|
group.byte 0x446++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH246,Uncommitted Supervisorly Flash in Macro 246"
|
|
group.byte 0x447++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH247,Uncommitted Supervisorly Flash in Macro 247"
|
|
group.byte 0x448++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH248,Uncommitted Supervisorly Flash in Macro 248"
|
|
group.byte 0x449++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH249,Uncommitted Supervisorly Flash in Macro 249"
|
|
group.byte 0x44A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH250,Uncommitted Supervisorly Flash in Macro 250"
|
|
group.byte 0x44B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH251,Uncommitted Supervisorly Flash in Macro 251"
|
|
group.byte 0x44C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH252,Uncommitted Supervisorly Flash in Macro 252"
|
|
group.byte 0x44D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH253,Uncommitted Supervisorly Flash in Macro 253"
|
|
group.byte 0x44E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH254,Uncommitted Supervisorly Flash in Macro 254"
|
|
group.byte 0x44F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH255,Uncommitted Supervisorly Flash in Macro 255"
|
|
group.byte 0x450++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH256,Uncommitted Supervisorly Flash in Macro 256"
|
|
group.byte 0x451++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH257,Uncommitted Supervisorly Flash in Macro 257"
|
|
group.byte 0x452++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH258,Uncommitted Supervisorly Flash in Macro 258"
|
|
group.byte 0x453++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH259,Uncommitted Supervisorly Flash in Macro 259"
|
|
group.byte 0x454++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH260,Uncommitted Supervisorly Flash in Macro 260"
|
|
group.byte 0x455++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH261,Uncommitted Supervisorly Flash in Macro 261"
|
|
group.byte 0x456++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH262,Uncommitted Supervisorly Flash in Macro 262"
|
|
group.byte 0x457++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH263,Uncommitted Supervisorly Flash in Macro 263"
|
|
group.byte 0x458++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH264,Uncommitted Supervisorly Flash in Macro 264"
|
|
group.byte 0x459++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH265,Uncommitted Supervisorly Flash in Macro 265"
|
|
group.byte 0x45A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH266,Uncommitted Supervisorly Flash in Macro 266"
|
|
group.byte 0x45B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH267,Uncommitted Supervisorly Flash in Macro 267"
|
|
group.byte 0x45C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH268,Uncommitted Supervisorly Flash in Macro 268"
|
|
group.byte 0x45D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH269,Uncommitted Supervisorly Flash in Macro 269"
|
|
group.byte 0x45E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH270,Uncommitted Supervisorly Flash in Macro 270"
|
|
group.byte 0x45F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH271,Uncommitted Supervisorly Flash in Macro 271"
|
|
group.byte 0x460++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH272,Uncommitted Supervisorly Flash in Macro 272"
|
|
group.byte 0x461++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH273,Uncommitted Supervisorly Flash in Macro 273"
|
|
group.byte 0x462++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH274,Uncommitted Supervisorly Flash in Macro 274"
|
|
group.byte 0x463++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH275,Uncommitted Supervisorly Flash in Macro 275"
|
|
group.byte 0x464++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH276,Uncommitted Supervisorly Flash in Macro 276"
|
|
group.byte 0x465++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH277,Uncommitted Supervisorly Flash in Macro 277"
|
|
group.byte 0x466++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH278,Uncommitted Supervisorly Flash in Macro 278"
|
|
group.byte 0x467++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH279,Uncommitted Supervisorly Flash in Macro 279"
|
|
group.byte 0x468++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH280,Uncommitted Supervisorly Flash in Macro 280"
|
|
group.byte 0x469++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH281,Uncommitted Supervisorly Flash in Macro 281"
|
|
group.byte 0x46A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH282,Uncommitted Supervisorly Flash in Macro 282"
|
|
group.byte 0x46B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH283,Uncommitted Supervisorly Flash in Macro 283"
|
|
group.byte 0x46C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH284,Uncommitted Supervisorly Flash in Macro 284"
|
|
group.byte 0x46D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH285,Uncommitted Supervisorly Flash in Macro 285"
|
|
group.byte 0x46E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH286,Uncommitted Supervisorly Flash in Macro 286"
|
|
group.byte 0x46F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH287,Uncommitted Supervisorly Flash in Macro 287"
|
|
group.byte 0x470++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH288,Uncommitted Supervisorly Flash in Macro 288"
|
|
group.byte 0x471++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH289,Uncommitted Supervisorly Flash in Macro 289"
|
|
group.byte 0x472++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH290,Uncommitted Supervisorly Flash in Macro 290"
|
|
group.byte 0x473++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH291,Uncommitted Supervisorly Flash in Macro 291"
|
|
group.byte 0x474++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH292,Uncommitted Supervisorly Flash in Macro 292"
|
|
group.byte 0x475++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH293,Uncommitted Supervisorly Flash in Macro 293"
|
|
group.byte 0x476++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH294,Uncommitted Supervisorly Flash in Macro 294"
|
|
group.byte 0x477++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH295,Uncommitted Supervisorly Flash in Macro 295"
|
|
group.byte 0x478++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH296,Uncommitted Supervisorly Flash in Macro 296"
|
|
group.byte 0x479++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH297,Uncommitted Supervisorly Flash in Macro 297"
|
|
group.byte 0x47A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH298,Uncommitted Supervisorly Flash in Macro 298"
|
|
group.byte 0x47B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH299,Uncommitted Supervisorly Flash in Macro 299"
|
|
group.byte 0x47C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH300,Uncommitted Supervisorly Flash in Macro 300"
|
|
group.byte 0x47D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH301,Uncommitted Supervisorly Flash in Macro 301"
|
|
group.byte 0x47E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH302,Uncommitted Supervisorly Flash in Macro 302"
|
|
group.byte 0x47F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH303,Uncommitted Supervisorly Flash in Macro 303"
|
|
group.byte 0x480++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH304,Uncommitted Supervisorly Flash in Macro 304"
|
|
group.byte 0x481++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH305,Uncommitted Supervisorly Flash in Macro 305"
|
|
group.byte 0x482++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH306,Uncommitted Supervisorly Flash in Macro 306"
|
|
group.byte 0x483++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH307,Uncommitted Supervisorly Flash in Macro 307"
|
|
group.byte 0x484++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH308,Uncommitted Supervisorly Flash in Macro 308"
|
|
group.byte 0x485++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH309,Uncommitted Supervisorly Flash in Macro 309"
|
|
group.byte 0x486++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH310,Uncommitted Supervisorly Flash in Macro 310"
|
|
group.byte 0x487++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH311,Uncommitted Supervisorly Flash in Macro 311"
|
|
group.byte 0x488++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH312,Uncommitted Supervisorly Flash in Macro 312"
|
|
group.byte 0x489++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH313,Uncommitted Supervisorly Flash in Macro 313"
|
|
group.byte 0x48A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH314,Uncommitted Supervisorly Flash in Macro 314"
|
|
group.byte 0x48B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH315,Uncommitted Supervisorly Flash in Macro 315"
|
|
group.byte 0x48C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH316,Uncommitted Supervisorly Flash in Macro 316"
|
|
group.byte 0x48D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH317,Uncommitted Supervisorly Flash in Macro 317"
|
|
group.byte 0x48E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH318,Uncommitted Supervisorly Flash in Macro 318"
|
|
group.byte 0x48F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH319,Uncommitted Supervisorly Flash in Macro 319"
|
|
group.byte 0x490++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH320,Uncommitted Supervisorly Flash in Macro 320"
|
|
group.byte 0x491++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH321,Uncommitted Supervisorly Flash in Macro 321"
|
|
group.byte 0x492++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH322,Uncommitted Supervisorly Flash in Macro 322"
|
|
group.byte 0x493++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH323,Uncommitted Supervisorly Flash in Macro 323"
|
|
group.byte 0x494++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH324,Uncommitted Supervisorly Flash in Macro 324"
|
|
group.byte 0x495++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH325,Uncommitted Supervisorly Flash in Macro 325"
|
|
group.byte 0x496++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH326,Uncommitted Supervisorly Flash in Macro 326"
|
|
group.byte 0x497++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH327,Uncommitted Supervisorly Flash in Macro 327"
|
|
group.byte 0x498++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH328,Uncommitted Supervisorly Flash in Macro 328"
|
|
group.byte 0x499++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH329,Uncommitted Supervisorly Flash in Macro 329"
|
|
group.byte 0x49A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH330,Uncommitted Supervisorly Flash in Macro 330"
|
|
group.byte 0x49B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH331,Uncommitted Supervisorly Flash in Macro 331"
|
|
group.byte 0x49C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH332,Uncommitted Supervisorly Flash in Macro 332"
|
|
group.byte 0x49D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH333,Uncommitted Supervisorly Flash in Macro 333"
|
|
group.byte 0x49E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH334,Uncommitted Supervisorly Flash in Macro 334"
|
|
group.byte 0x49F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH335,Uncommitted Supervisorly Flash in Macro 335"
|
|
group.byte 0x4A0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH336,Uncommitted Supervisorly Flash in Macro 336"
|
|
group.byte 0x4A1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH337,Uncommitted Supervisorly Flash in Macro 337"
|
|
group.byte 0x4A2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH338,Uncommitted Supervisorly Flash in Macro 338"
|
|
group.byte 0x4A3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH339,Uncommitted Supervisorly Flash in Macro 339"
|
|
group.byte 0x4A4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH340,Uncommitted Supervisorly Flash in Macro 340"
|
|
group.byte 0x4A5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH341,Uncommitted Supervisorly Flash in Macro 341"
|
|
group.byte 0x4A6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH342,Uncommitted Supervisorly Flash in Macro 342"
|
|
group.byte 0x4A7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH343,Uncommitted Supervisorly Flash in Macro 343"
|
|
group.byte 0x4A8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH344,Uncommitted Supervisorly Flash in Macro 344"
|
|
group.byte 0x4A9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH345,Uncommitted Supervisorly Flash in Macro 345"
|
|
group.byte 0x4AA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH346,Uncommitted Supervisorly Flash in Macro 346"
|
|
group.byte 0x4AB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH347,Uncommitted Supervisorly Flash in Macro 347"
|
|
group.byte 0x4AC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH348,Uncommitted Supervisorly Flash in Macro 348"
|
|
group.byte 0x4AD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH349,Uncommitted Supervisorly Flash in Macro 349"
|
|
group.byte 0x4AE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH350,Uncommitted Supervisorly Flash in Macro 350"
|
|
group.byte 0x4AF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH351,Uncommitted Supervisorly Flash in Macro 351"
|
|
group.byte 0x4B0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH352,Uncommitted Supervisorly Flash in Macro 352"
|
|
group.byte 0x4B1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH353,Uncommitted Supervisorly Flash in Macro 353"
|
|
group.byte 0x4B2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH354,Uncommitted Supervisorly Flash in Macro 354"
|
|
group.byte 0x4B3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH355,Uncommitted Supervisorly Flash in Macro 355"
|
|
group.byte 0x4B4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH356,Uncommitted Supervisorly Flash in Macro 356"
|
|
group.byte 0x4B5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH357,Uncommitted Supervisorly Flash in Macro 357"
|
|
group.byte 0x4B6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH358,Uncommitted Supervisorly Flash in Macro 358"
|
|
group.byte 0x4B7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH359,Uncommitted Supervisorly Flash in Macro 359"
|
|
group.byte 0x4B8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH360,Uncommitted Supervisorly Flash in Macro 360"
|
|
group.byte 0x4B9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH361,Uncommitted Supervisorly Flash in Macro 361"
|
|
group.byte 0x4BA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH362,Uncommitted Supervisorly Flash in Macro 362"
|
|
group.byte 0x4BB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH363,Uncommitted Supervisorly Flash in Macro 363"
|
|
group.byte 0x4BC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH364,Uncommitted Supervisorly Flash in Macro 364"
|
|
group.byte 0x4BD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH365,Uncommitted Supervisorly Flash in Macro 365"
|
|
group.byte 0x4BE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH366,Uncommitted Supervisorly Flash in Macro 366"
|
|
group.byte 0x4BF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH367,Uncommitted Supervisorly Flash in Macro 367"
|
|
group.byte 0x4C0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH368,Uncommitted Supervisorly Flash in Macro 368"
|
|
group.byte 0x4C1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH369,Uncommitted Supervisorly Flash in Macro 369"
|
|
group.byte 0x4C2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH370,Uncommitted Supervisorly Flash in Macro 370"
|
|
group.byte 0x4C3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH371,Uncommitted Supervisorly Flash in Macro 371"
|
|
group.byte 0x4C4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH372,Uncommitted Supervisorly Flash in Macro 372"
|
|
group.byte 0x4C5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH373,Uncommitted Supervisorly Flash in Macro 373"
|
|
group.byte 0x4C6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH374,Uncommitted Supervisorly Flash in Macro 374"
|
|
group.byte 0x4C7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH375,Uncommitted Supervisorly Flash in Macro 375"
|
|
group.byte 0x4C8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH376,Uncommitted Supervisorly Flash in Macro 376"
|
|
group.byte 0x4C9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH377,Uncommitted Supervisorly Flash in Macro 377"
|
|
group.byte 0x4CA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH378,Uncommitted Supervisorly Flash in Macro 378"
|
|
group.byte 0x4CB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH379,Uncommitted Supervisorly Flash in Macro 379"
|
|
group.byte 0x4CC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH380,Uncommitted Supervisorly Flash in Macro 380"
|
|
group.byte 0x4CD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH381,Uncommitted Supervisorly Flash in Macro 381"
|
|
group.byte 0x4CE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH382,Uncommitted Supervisorly Flash in Macro 382"
|
|
group.byte 0x4CF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH383,Uncommitted Supervisorly Flash in Macro 383"
|
|
group.byte 0x4D0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH384,Uncommitted Supervisorly Flash in Macro 384"
|
|
group.byte 0x4D1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH385,Uncommitted Supervisorly Flash in Macro 385"
|
|
group.byte 0x4D2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH386,Uncommitted Supervisorly Flash in Macro 386"
|
|
group.byte 0x4D3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH387,Uncommitted Supervisorly Flash in Macro 387"
|
|
group.byte 0x4D4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH388,Uncommitted Supervisorly Flash in Macro 388"
|
|
group.byte 0x4D5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH389,Uncommitted Supervisorly Flash in Macro 389"
|
|
group.byte 0x4D6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH390,Uncommitted Supervisorly Flash in Macro 390"
|
|
group.byte 0x4D7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH391,Uncommitted Supervisorly Flash in Macro 391"
|
|
group.byte 0x4D8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH392,Uncommitted Supervisorly Flash in Macro 392"
|
|
group.byte 0x4D9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH393,Uncommitted Supervisorly Flash in Macro 393"
|
|
group.byte 0x4DA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH394,Uncommitted Supervisorly Flash in Macro 394"
|
|
group.byte 0x4DB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH395,Uncommitted Supervisorly Flash in Macro 395"
|
|
group.byte 0x4DC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH396,Uncommitted Supervisorly Flash in Macro 396"
|
|
group.byte 0x4DD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH397,Uncommitted Supervisorly Flash in Macro 397"
|
|
group.byte 0x4DE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH398,Uncommitted Supervisorly Flash in Macro 398"
|
|
group.byte 0x4DF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH399,Uncommitted Supervisorly Flash in Macro 399"
|
|
group.byte 0x4E0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH400,Uncommitted Supervisorly Flash in Macro 400"
|
|
group.byte 0x4E1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH401,Uncommitted Supervisorly Flash in Macro 401"
|
|
group.byte 0x4E2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH402,Uncommitted Supervisorly Flash in Macro 402"
|
|
group.byte 0x4E3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH403,Uncommitted Supervisorly Flash in Macro 403"
|
|
group.byte 0x4E4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH404,Uncommitted Supervisorly Flash in Macro 404"
|
|
group.byte 0x4E5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH405,Uncommitted Supervisorly Flash in Macro 405"
|
|
group.byte 0x4E6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH406,Uncommitted Supervisorly Flash in Macro 406"
|
|
group.byte 0x4E7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH407,Uncommitted Supervisorly Flash in Macro 407"
|
|
group.byte 0x4E8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH408,Uncommitted Supervisorly Flash in Macro 408"
|
|
group.byte 0x4E9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH409,Uncommitted Supervisorly Flash in Macro 409"
|
|
group.byte 0x4EA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH410,Uncommitted Supervisorly Flash in Macro 410"
|
|
group.byte 0x4EB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH411,Uncommitted Supervisorly Flash in Macro 411"
|
|
group.byte 0x4EC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH412,Uncommitted Supervisorly Flash in Macro 412"
|
|
group.byte 0x4ED++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH413,Uncommitted Supervisorly Flash in Macro 413"
|
|
group.byte 0x4EE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH414,Uncommitted Supervisorly Flash in Macro 414"
|
|
group.byte 0x4EF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH415,Uncommitted Supervisorly Flash in Macro 415"
|
|
group.byte 0x4F0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH416,Uncommitted Supervisorly Flash in Macro 416"
|
|
group.byte 0x4F1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH417,Uncommitted Supervisorly Flash in Macro 417"
|
|
group.byte 0x4F2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH418,Uncommitted Supervisorly Flash in Macro 418"
|
|
group.byte 0x4F3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH419,Uncommitted Supervisorly Flash in Macro 419"
|
|
group.byte 0x4F4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH420,Uncommitted Supervisorly Flash in Macro 420"
|
|
group.byte 0x4F5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH421,Uncommitted Supervisorly Flash in Macro 421"
|
|
group.byte 0x4F6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH422,Uncommitted Supervisorly Flash in Macro 422"
|
|
group.byte 0x4F7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH423,Uncommitted Supervisorly Flash in Macro 423"
|
|
group.byte 0x4F8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH424,Uncommitted Supervisorly Flash in Macro 424"
|
|
group.byte 0x4F9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH425,Uncommitted Supervisorly Flash in Macro 425"
|
|
group.byte 0x4FA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH426,Uncommitted Supervisorly Flash in Macro 426"
|
|
group.byte 0x4FB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH427,Uncommitted Supervisorly Flash in Macro 427"
|
|
group.byte 0x4FC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH428,Uncommitted Supervisorly Flash in Macro 428"
|
|
group.byte 0x4FD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH429,Uncommitted Supervisorly Flash in Macro 429"
|
|
group.byte 0x4FE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH430,Uncommitted Supervisorly Flash in Macro 430"
|
|
group.byte 0x4FF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH431,Uncommitted Supervisorly Flash in Macro 431"
|
|
group.byte 0x500++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH432,Uncommitted Supervisorly Flash in Macro 432"
|
|
group.byte 0x501++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH433,Uncommitted Supervisorly Flash in Macro 433"
|
|
group.byte 0x502++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH434,Uncommitted Supervisorly Flash in Macro 434"
|
|
group.byte 0x503++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH435,Uncommitted Supervisorly Flash in Macro 435"
|
|
group.byte 0x504++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH436,Uncommitted Supervisorly Flash in Macro 436"
|
|
group.byte 0x505++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH437,Uncommitted Supervisorly Flash in Macro 437"
|
|
group.byte 0x506++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH438,Uncommitted Supervisorly Flash in Macro 438"
|
|
group.byte 0x507++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH439,Uncommitted Supervisorly Flash in Macro 439"
|
|
group.byte 0x508++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH440,Uncommitted Supervisorly Flash in Macro 440"
|
|
group.byte 0x509++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH441,Uncommitted Supervisorly Flash in Macro 441"
|
|
group.byte 0x50A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH442,Uncommitted Supervisorly Flash in Macro 442"
|
|
group.byte 0x50B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH443,Uncommitted Supervisorly Flash in Macro 443"
|
|
group.byte 0x50C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH444,Uncommitted Supervisorly Flash in Macro 444"
|
|
group.byte 0x50D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH445,Uncommitted Supervisorly Flash in Macro 445"
|
|
group.byte 0x50E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH446,Uncommitted Supervisorly Flash in Macro 446"
|
|
group.byte 0x50F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH447,Uncommitted Supervisorly Flash in Macro 447"
|
|
group.byte 0x510++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH448,Uncommitted Supervisorly Flash in Macro 448"
|
|
group.byte 0x511++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH449,Uncommitted Supervisorly Flash in Macro 449"
|
|
group.byte 0x512++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH450,Uncommitted Supervisorly Flash in Macro 450"
|
|
group.byte 0x513++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH451,Uncommitted Supervisorly Flash in Macro 451"
|
|
group.byte 0x514++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH452,Uncommitted Supervisorly Flash in Macro 452"
|
|
group.byte 0x515++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH453,Uncommitted Supervisorly Flash in Macro 453"
|
|
group.byte 0x516++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH454,Uncommitted Supervisorly Flash in Macro 454"
|
|
group.byte 0x517++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH455,Uncommitted Supervisorly Flash in Macro 455"
|
|
group.byte 0x518++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH456,Uncommitted Supervisorly Flash in Macro 456"
|
|
group.byte 0x519++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH457,Uncommitted Supervisorly Flash in Macro 457"
|
|
group.byte 0x51A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH458,Uncommitted Supervisorly Flash in Macro 458"
|
|
group.byte 0x51B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH459,Uncommitted Supervisorly Flash in Macro 459"
|
|
group.byte 0x51C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH460,Uncommitted Supervisorly Flash in Macro 460"
|
|
group.byte 0x51D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH461,Uncommitted Supervisorly Flash in Macro 461"
|
|
group.byte 0x51E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH462,Uncommitted Supervisorly Flash in Macro 462"
|
|
group.byte 0x51F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH463,Uncommitted Supervisorly Flash in Macro 463"
|
|
group.byte 0x520++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH464,Uncommitted Supervisorly Flash in Macro 464"
|
|
group.byte 0x521++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH465,Uncommitted Supervisorly Flash in Macro 465"
|
|
group.byte 0x522++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH466,Uncommitted Supervisorly Flash in Macro 466"
|
|
group.byte 0x523++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH467,Uncommitted Supervisorly Flash in Macro 467"
|
|
group.byte 0x524++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH468,Uncommitted Supervisorly Flash in Macro 468"
|
|
group.byte 0x525++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH469,Uncommitted Supervisorly Flash in Macro 469"
|
|
group.byte 0x526++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH470,Uncommitted Supervisorly Flash in Macro 470"
|
|
group.byte 0x527++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH471,Uncommitted Supervisorly Flash in Macro 471"
|
|
group.byte 0x528++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH472,Uncommitted Supervisorly Flash in Macro 472"
|
|
group.byte 0x529++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH473,Uncommitted Supervisorly Flash in Macro 473"
|
|
group.byte 0x52A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH474,Uncommitted Supervisorly Flash in Macro 474"
|
|
group.byte 0x52B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH475,Uncommitted Supervisorly Flash in Macro 475"
|
|
group.byte 0x52C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH476,Uncommitted Supervisorly Flash in Macro 476"
|
|
group.byte 0x52D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH477,Uncommitted Supervisorly Flash in Macro 477"
|
|
group.byte 0x52E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH478,Uncommitted Supervisorly Flash in Macro 478"
|
|
group.byte 0x52F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH479,Uncommitted Supervisorly Flash in Macro 479"
|
|
group.byte 0x530++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH480,Uncommitted Supervisorly Flash in Macro 480"
|
|
group.byte 0x531++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH481,Uncommitted Supervisorly Flash in Macro 481"
|
|
group.byte 0x532++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH482,Uncommitted Supervisorly Flash in Macro 482"
|
|
group.byte 0x533++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH483,Uncommitted Supervisorly Flash in Macro 483"
|
|
group.byte 0x534++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH484,Uncommitted Supervisorly Flash in Macro 484"
|
|
group.byte 0x535++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH485,Uncommitted Supervisorly Flash in Macro 485"
|
|
group.byte 0x536++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH486,Uncommitted Supervisorly Flash in Macro 486"
|
|
group.byte 0x537++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH487,Uncommitted Supervisorly Flash in Macro 487"
|
|
group.byte 0x538++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH488,Uncommitted Supervisorly Flash in Macro 488"
|
|
group.byte 0x539++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH489,Uncommitted Supervisorly Flash in Macro 489"
|
|
group.byte 0x53A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH490,Uncommitted Supervisorly Flash in Macro 490"
|
|
group.byte 0x53B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH491,Uncommitted Supervisorly Flash in Macro 491"
|
|
group.byte 0x53C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH492,Uncommitted Supervisorly Flash in Macro 492"
|
|
group.byte 0x53D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH493,Uncommitted Supervisorly Flash in Macro 493"
|
|
group.byte 0x53E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH494,Uncommitted Supervisorly Flash in Macro 494"
|
|
group.byte 0x53F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH495,Uncommitted Supervisorly Flash in Macro 495"
|
|
group.byte 0x540++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH496,Uncommitted Supervisorly Flash in Macro 496"
|
|
group.byte 0x541++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH497,Uncommitted Supervisorly Flash in Macro 497"
|
|
group.byte 0x542++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH498,Uncommitted Supervisorly Flash in Macro 498"
|
|
group.byte 0x543++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH499,Uncommitted Supervisorly Flash in Macro 499"
|
|
group.byte 0x544++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH500,Uncommitted Supervisorly Flash in Macro 500"
|
|
group.byte 0x545++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH501,Uncommitted Supervisorly Flash in Macro 501"
|
|
group.byte 0x546++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH502,Uncommitted Supervisorly Flash in Macro 502"
|
|
group.byte 0x547++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH503,Uncommitted Supervisorly Flash in Macro 503"
|
|
group.byte 0x548++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH504,Uncommitted Supervisorly Flash in Macro 504"
|
|
group.byte 0x549++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH505,Uncommitted Supervisorly Flash in Macro 505"
|
|
group.byte 0x54A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH506,Uncommitted Supervisorly Flash in Macro 506"
|
|
group.byte 0x54B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH507,Uncommitted Supervisorly Flash in Macro 507"
|
|
group.byte 0x54C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH508,Uncommitted Supervisorly Flash in Macro 508"
|
|
group.byte 0x54D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH509,Uncommitted Supervisorly Flash in Macro 509"
|
|
group.byte 0x54E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH510,Uncommitted Supervisorly Flash in Macro 510"
|
|
group.byte 0x54F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH511,Uncommitted Supervisorly Flash in Macro 511"
|
|
group.byte 0x550++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH512,Uncommitted Supervisorly Flash in Macro 512"
|
|
group.byte 0x551++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH513,Uncommitted Supervisorly Flash in Macro 513"
|
|
group.byte 0x552++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH514,Uncommitted Supervisorly Flash in Macro 514"
|
|
group.byte 0x553++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH515,Uncommitted Supervisorly Flash in Macro 515"
|
|
group.byte 0x554++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH516,Uncommitted Supervisorly Flash in Macro 516"
|
|
group.byte 0x555++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH517,Uncommitted Supervisorly Flash in Macro 517"
|
|
group.byte 0x556++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH518,Uncommitted Supervisorly Flash in Macro 518"
|
|
group.byte 0x557++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH519,Uncommitted Supervisorly Flash in Macro 519"
|
|
group.byte 0x558++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH520,Uncommitted Supervisorly Flash in Macro 520"
|
|
group.byte 0x559++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH521,Uncommitted Supervisorly Flash in Macro 521"
|
|
group.byte 0x55A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH522,Uncommitted Supervisorly Flash in Macro 522"
|
|
group.byte 0x55B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH523,Uncommitted Supervisorly Flash in Macro 523"
|
|
group.byte 0x55C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH524,Uncommitted Supervisorly Flash in Macro 524"
|
|
group.byte 0x55D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH525,Uncommitted Supervisorly Flash in Macro 525"
|
|
group.byte 0x55E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH526,Uncommitted Supervisorly Flash in Macro 526"
|
|
group.byte 0x55F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH527,Uncommitted Supervisorly Flash in Macro 527"
|
|
group.byte 0x560++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH528,Uncommitted Supervisorly Flash in Macro 528"
|
|
group.byte 0x561++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH529,Uncommitted Supervisorly Flash in Macro 529"
|
|
group.byte 0x562++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH530,Uncommitted Supervisorly Flash in Macro 530"
|
|
group.byte 0x563++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH531,Uncommitted Supervisorly Flash in Macro 531"
|
|
group.byte 0x564++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH532,Uncommitted Supervisorly Flash in Macro 532"
|
|
group.byte 0x565++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH533,Uncommitted Supervisorly Flash in Macro 533"
|
|
group.byte 0x566++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH534,Uncommitted Supervisorly Flash in Macro 534"
|
|
group.byte 0x567++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH535,Uncommitted Supervisorly Flash in Macro 535"
|
|
group.byte 0x568++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH536,Uncommitted Supervisorly Flash in Macro 536"
|
|
group.byte 0x569++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH537,Uncommitted Supervisorly Flash in Macro 537"
|
|
group.byte 0x56A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH538,Uncommitted Supervisorly Flash in Macro 538"
|
|
group.byte 0x56B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH539,Uncommitted Supervisorly Flash in Macro 539"
|
|
group.byte 0x56C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH540,Uncommitted Supervisorly Flash in Macro 540"
|
|
group.byte 0x56D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH541,Uncommitted Supervisorly Flash in Macro 541"
|
|
group.byte 0x56E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH542,Uncommitted Supervisorly Flash in Macro 542"
|
|
group.byte 0x56F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH543,Uncommitted Supervisorly Flash in Macro 543"
|
|
group.byte 0x570++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH544,Uncommitted Supervisorly Flash in Macro 544"
|
|
group.byte 0x571++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH545,Uncommitted Supervisorly Flash in Macro 545"
|
|
group.byte 0x572++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH546,Uncommitted Supervisorly Flash in Macro 546"
|
|
group.byte 0x573++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH547,Uncommitted Supervisorly Flash in Macro 547"
|
|
group.byte 0x574++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH548,Uncommitted Supervisorly Flash in Macro 548"
|
|
group.byte 0x575++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH549,Uncommitted Supervisorly Flash in Macro 549"
|
|
group.byte 0x576++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH550,Uncommitted Supervisorly Flash in Macro 550"
|
|
group.byte 0x577++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH551,Uncommitted Supervisorly Flash in Macro 551"
|
|
group.byte 0x578++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH552,Uncommitted Supervisorly Flash in Macro 552"
|
|
group.byte 0x579++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH553,Uncommitted Supervisorly Flash in Macro 553"
|
|
group.byte 0x57A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH554,Uncommitted Supervisorly Flash in Macro 554"
|
|
group.byte 0x57B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH555,Uncommitted Supervisorly Flash in Macro 555"
|
|
group.byte 0x57C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH556,Uncommitted Supervisorly Flash in Macro 556"
|
|
group.byte 0x57D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH557,Uncommitted Supervisorly Flash in Macro 557"
|
|
group.byte 0x57E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH558,Uncommitted Supervisorly Flash in Macro 558"
|
|
group.byte 0x57F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH559,Uncommitted Supervisorly Flash in Macro 559"
|
|
group.byte 0x580++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH560,Uncommitted Supervisorly Flash in Macro 560"
|
|
group.byte 0x581++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH561,Uncommitted Supervisorly Flash in Macro 561"
|
|
group.byte 0x582++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH562,Uncommitted Supervisorly Flash in Macro 562"
|
|
group.byte 0x583++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH563,Uncommitted Supervisorly Flash in Macro 563"
|
|
group.byte 0x584++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH564,Uncommitted Supervisorly Flash in Macro 564"
|
|
group.byte 0x585++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH565,Uncommitted Supervisorly Flash in Macro 565"
|
|
group.byte 0x586++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH566,Uncommitted Supervisorly Flash in Macro 566"
|
|
group.byte 0x587++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH567,Uncommitted Supervisorly Flash in Macro 567"
|
|
group.byte 0x588++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH568,Uncommitted Supervisorly Flash in Macro 568"
|
|
group.byte 0x589++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH569,Uncommitted Supervisorly Flash in Macro 569"
|
|
group.byte 0x58A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH570,Uncommitted Supervisorly Flash in Macro 570"
|
|
group.byte 0x58B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH571,Uncommitted Supervisorly Flash in Macro 571"
|
|
group.byte 0x58C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH572,Uncommitted Supervisorly Flash in Macro 572"
|
|
group.byte 0x58D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH573,Uncommitted Supervisorly Flash in Macro 573"
|
|
group.byte 0x58E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH574,Uncommitted Supervisorly Flash in Macro 574"
|
|
group.byte 0x58F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH575,Uncommitted Supervisorly Flash in Macro 575"
|
|
group.byte 0x590++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH576,Uncommitted Supervisorly Flash in Macro 576"
|
|
group.byte 0x591++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH577,Uncommitted Supervisorly Flash in Macro 577"
|
|
group.byte 0x592++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH578,Uncommitted Supervisorly Flash in Macro 578"
|
|
group.byte 0x593++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH579,Uncommitted Supervisorly Flash in Macro 579"
|
|
group.byte 0x594++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH580,Uncommitted Supervisorly Flash in Macro 580"
|
|
group.byte 0x595++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH581,Uncommitted Supervisorly Flash in Macro 581"
|
|
group.byte 0x596++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH582,Uncommitted Supervisorly Flash in Macro 582"
|
|
group.byte 0x597++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH583,Uncommitted Supervisorly Flash in Macro 583"
|
|
group.byte 0x598++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH584,Uncommitted Supervisorly Flash in Macro 584"
|
|
group.byte 0x599++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH585,Uncommitted Supervisorly Flash in Macro 585"
|
|
group.byte 0x59A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH586,Uncommitted Supervisorly Flash in Macro 586"
|
|
group.byte 0x59B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH587,Uncommitted Supervisorly Flash in Macro 587"
|
|
group.byte 0x59C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH588,Uncommitted Supervisorly Flash in Macro 588"
|
|
group.byte 0x59D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH589,Uncommitted Supervisorly Flash in Macro 589"
|
|
group.byte 0x59E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH590,Uncommitted Supervisorly Flash in Macro 590"
|
|
group.byte 0x59F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH591,Uncommitted Supervisorly Flash in Macro 591"
|
|
group.byte 0x5A0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH592,Uncommitted Supervisorly Flash in Macro 592"
|
|
group.byte 0x5A1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH593,Uncommitted Supervisorly Flash in Macro 593"
|
|
group.byte 0x5A2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH594,Uncommitted Supervisorly Flash in Macro 594"
|
|
group.byte 0x5A3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH595,Uncommitted Supervisorly Flash in Macro 595"
|
|
group.byte 0x5A4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH596,Uncommitted Supervisorly Flash in Macro 596"
|
|
group.byte 0x5A5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH597,Uncommitted Supervisorly Flash in Macro 597"
|
|
group.byte 0x5A6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH598,Uncommitted Supervisorly Flash in Macro 598"
|
|
group.byte 0x5A7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH599,Uncommitted Supervisorly Flash in Macro 599"
|
|
group.byte 0x5A8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH600,Uncommitted Supervisorly Flash in Macro 600"
|
|
group.byte 0x5A9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH601,Uncommitted Supervisorly Flash in Macro 601"
|
|
group.byte 0x5AA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH602,Uncommitted Supervisorly Flash in Macro 602"
|
|
group.byte 0x5AB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH603,Uncommitted Supervisorly Flash in Macro 603"
|
|
group.byte 0x5AC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH604,Uncommitted Supervisorly Flash in Macro 604"
|
|
group.byte 0x5AD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH605,Uncommitted Supervisorly Flash in Macro 605"
|
|
group.byte 0x5AE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH606,Uncommitted Supervisorly Flash in Macro 606"
|
|
group.byte 0x5AF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH607,Uncommitted Supervisorly Flash in Macro 607"
|
|
group.byte 0x5B0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH608,Uncommitted Supervisorly Flash in Macro 608"
|
|
group.byte 0x5B1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH609,Uncommitted Supervisorly Flash in Macro 609"
|
|
group.byte 0x5B2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH610,Uncommitted Supervisorly Flash in Macro 610"
|
|
group.byte 0x5B3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH611,Uncommitted Supervisorly Flash in Macro 611"
|
|
group.byte 0x5B4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH612,Uncommitted Supervisorly Flash in Macro 612"
|
|
group.byte 0x5B5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH613,Uncommitted Supervisorly Flash in Macro 613"
|
|
group.byte 0x5B6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH614,Uncommitted Supervisorly Flash in Macro 614"
|
|
group.byte 0x5B7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH615,Uncommitted Supervisorly Flash in Macro 615"
|
|
group.byte 0x5B8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH616,Uncommitted Supervisorly Flash in Macro 616"
|
|
group.byte 0x5B9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH617,Uncommitted Supervisorly Flash in Macro 617"
|
|
group.byte 0x5BA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH618,Uncommitted Supervisorly Flash in Macro 618"
|
|
group.byte 0x5BB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH619,Uncommitted Supervisorly Flash in Macro 619"
|
|
group.byte 0x5BC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH620,Uncommitted Supervisorly Flash in Macro 620"
|
|
group.byte 0x5BD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH621,Uncommitted Supervisorly Flash in Macro 621"
|
|
group.byte 0x5BE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH622,Uncommitted Supervisorly Flash in Macro 622"
|
|
group.byte 0x5BF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH623,Uncommitted Supervisorly Flash in Macro 623"
|
|
group.byte 0x5C0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH624,Uncommitted Supervisorly Flash in Macro 624"
|
|
group.byte 0x5C1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH625,Uncommitted Supervisorly Flash in Macro 625"
|
|
group.byte 0x5C2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH626,Uncommitted Supervisorly Flash in Macro 626"
|
|
group.byte 0x5C3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH627,Uncommitted Supervisorly Flash in Macro 627"
|
|
group.byte 0x5C4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH628,Uncommitted Supervisorly Flash in Macro 628"
|
|
group.byte 0x5C5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH629,Uncommitted Supervisorly Flash in Macro 629"
|
|
group.byte 0x5C6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH630,Uncommitted Supervisorly Flash in Macro 630"
|
|
group.byte 0x5C7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH631,Uncommitted Supervisorly Flash in Macro 631"
|
|
group.byte 0x5C8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH632,Uncommitted Supervisorly Flash in Macro 632"
|
|
group.byte 0x5C9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH633,Uncommitted Supervisorly Flash in Macro 633"
|
|
group.byte 0x5CA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH634,Uncommitted Supervisorly Flash in Macro 634"
|
|
group.byte 0x5CB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH635,Uncommitted Supervisorly Flash in Macro 635"
|
|
group.byte 0x5CC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH636,Uncommitted Supervisorly Flash in Macro 636"
|
|
group.byte 0x5CD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH637,Uncommitted Supervisorly Flash in Macro 637"
|
|
group.byte 0x5CE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH638,Uncommitted Supervisorly Flash in Macro 638"
|
|
group.byte 0x5CF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH639,Uncommitted Supervisorly Flash in Macro 639"
|
|
group.byte 0x5D0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH640,Uncommitted Supervisorly Flash in Macro 640"
|
|
group.byte 0x5D1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH641,Uncommitted Supervisorly Flash in Macro 641"
|
|
group.byte 0x5D2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH642,Uncommitted Supervisorly Flash in Macro 642"
|
|
group.byte 0x5D3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH643,Uncommitted Supervisorly Flash in Macro 643"
|
|
group.byte 0x5D4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH644,Uncommitted Supervisorly Flash in Macro 644"
|
|
group.byte 0x5D5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH645,Uncommitted Supervisorly Flash in Macro 645"
|
|
group.byte 0x5D6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH646,Uncommitted Supervisorly Flash in Macro 646"
|
|
group.byte 0x5D7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH647,Uncommitted Supervisorly Flash in Macro 647"
|
|
group.byte 0x5D8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH648,Uncommitted Supervisorly Flash in Macro 648"
|
|
group.byte 0x5D9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH649,Uncommitted Supervisorly Flash in Macro 649"
|
|
group.byte 0x5DA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH650,Uncommitted Supervisorly Flash in Macro 650"
|
|
group.byte 0x5DB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH651,Uncommitted Supervisorly Flash in Macro 651"
|
|
group.byte 0x5DC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH652,Uncommitted Supervisorly Flash in Macro 652"
|
|
group.byte 0x5DD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH653,Uncommitted Supervisorly Flash in Macro 653"
|
|
group.byte 0x5DE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH654,Uncommitted Supervisorly Flash in Macro 654"
|
|
group.byte 0x5DF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH655,Uncommitted Supervisorly Flash in Macro 655"
|
|
group.byte 0x5E0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH656,Uncommitted Supervisorly Flash in Macro 656"
|
|
group.byte 0x5E1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH657,Uncommitted Supervisorly Flash in Macro 657"
|
|
group.byte 0x5E2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH658,Uncommitted Supervisorly Flash in Macro 658"
|
|
group.byte 0x5E3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH659,Uncommitted Supervisorly Flash in Macro 659"
|
|
group.byte 0x5E4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH660,Uncommitted Supervisorly Flash in Macro 660"
|
|
group.byte 0x5E5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH661,Uncommitted Supervisorly Flash in Macro 661"
|
|
group.byte 0x5E6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH662,Uncommitted Supervisorly Flash in Macro 662"
|
|
group.byte 0x5E7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH663,Uncommitted Supervisorly Flash in Macro 663"
|
|
group.byte 0x5E8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH664,Uncommitted Supervisorly Flash in Macro 664"
|
|
group.byte 0x5E9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH665,Uncommitted Supervisorly Flash in Macro 665"
|
|
group.byte 0x5EA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH666,Uncommitted Supervisorly Flash in Macro 666"
|
|
group.byte 0x5EB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH667,Uncommitted Supervisorly Flash in Macro 667"
|
|
group.byte 0x5EC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH668,Uncommitted Supervisorly Flash in Macro 668"
|
|
group.byte 0x5ED++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH669,Uncommitted Supervisorly Flash in Macro 669"
|
|
group.byte 0x5EE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH670,Uncommitted Supervisorly Flash in Macro 670"
|
|
group.byte 0x5EF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH671,Uncommitted Supervisorly Flash in Macro 671"
|
|
group.byte 0x5F0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH672,Uncommitted Supervisorly Flash in Macro 672"
|
|
group.byte 0x5F1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH673,Uncommitted Supervisorly Flash in Macro 673"
|
|
group.byte 0x5F2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH674,Uncommitted Supervisorly Flash in Macro 674"
|
|
group.byte 0x5F3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH675,Uncommitted Supervisorly Flash in Macro 675"
|
|
group.byte 0x5F4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH676,Uncommitted Supervisorly Flash in Macro 676"
|
|
group.byte 0x5F5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH677,Uncommitted Supervisorly Flash in Macro 677"
|
|
group.byte 0x5F6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH678,Uncommitted Supervisorly Flash in Macro 678"
|
|
group.byte 0x5F7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH679,Uncommitted Supervisorly Flash in Macro 679"
|
|
group.byte 0x5F8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH680,Uncommitted Supervisorly Flash in Macro 680"
|
|
group.byte 0x5F9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH681,Uncommitted Supervisorly Flash in Macro 681"
|
|
group.byte 0x5FA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH682,Uncommitted Supervisorly Flash in Macro 682"
|
|
group.byte 0x5FB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH683,Uncommitted Supervisorly Flash in Macro 683"
|
|
group.byte 0x5FC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH684,Uncommitted Supervisorly Flash in Macro 684"
|
|
group.byte 0x5FD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH685,Uncommitted Supervisorly Flash in Macro 685"
|
|
group.byte 0x5FE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH686,Uncommitted Supervisorly Flash in Macro 686"
|
|
group.byte 0x5FF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH687,Uncommitted Supervisorly Flash in Macro 687"
|
|
group.byte 0x600++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH688,Uncommitted Supervisorly Flash in Macro 688"
|
|
group.byte 0x601++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH689,Uncommitted Supervisorly Flash in Macro 689"
|
|
group.byte 0x602++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH690,Uncommitted Supervisorly Flash in Macro 690"
|
|
group.byte 0x603++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH691,Uncommitted Supervisorly Flash in Macro 691"
|
|
group.byte 0x604++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH692,Uncommitted Supervisorly Flash in Macro 692"
|
|
group.byte 0x605++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH693,Uncommitted Supervisorly Flash in Macro 693"
|
|
group.byte 0x606++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH694,Uncommitted Supervisorly Flash in Macro 694"
|
|
group.byte 0x607++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH695,Uncommitted Supervisorly Flash in Macro 695"
|
|
group.byte 0x608++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH696,Uncommitted Supervisorly Flash in Macro 696"
|
|
group.byte 0x609++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH697,Uncommitted Supervisorly Flash in Macro 697"
|
|
group.byte 0x60A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH698,Uncommitted Supervisorly Flash in Macro 698"
|
|
group.byte 0x60B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH699,Uncommitted Supervisorly Flash in Macro 699"
|
|
group.byte 0x60C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH700,Uncommitted Supervisorly Flash in Macro 700"
|
|
group.byte 0x60D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH701,Uncommitted Supervisorly Flash in Macro 701"
|
|
group.byte 0x60E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH702,Uncommitted Supervisorly Flash in Macro 702"
|
|
group.byte 0x60F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH703,Uncommitted Supervisorly Flash in Macro 703"
|
|
group.byte 0x610++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH704,Uncommitted Supervisorly Flash in Macro 704"
|
|
group.byte 0x611++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH705,Uncommitted Supervisorly Flash in Macro 705"
|
|
group.byte 0x612++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH706,Uncommitted Supervisorly Flash in Macro 706"
|
|
group.byte 0x613++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH707,Uncommitted Supervisorly Flash in Macro 707"
|
|
group.byte 0x614++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH708,Uncommitted Supervisorly Flash in Macro 708"
|
|
group.byte 0x615++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH709,Uncommitted Supervisorly Flash in Macro 709"
|
|
group.byte 0x616++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH710,Uncommitted Supervisorly Flash in Macro 710"
|
|
group.byte 0x617++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH711,Uncommitted Supervisorly Flash in Macro 711"
|
|
group.byte 0x618++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH712,Uncommitted Supervisorly Flash in Macro 712"
|
|
group.byte 0x619++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH713,Uncommitted Supervisorly Flash in Macro 713"
|
|
group.byte 0x61A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH714,Uncommitted Supervisorly Flash in Macro 714"
|
|
group.byte 0x61B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH715,Uncommitted Supervisorly Flash in Macro 715"
|
|
group.byte 0x61C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH716,Uncommitted Supervisorly Flash in Macro 716"
|
|
group.byte 0x61D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH717,Uncommitted Supervisorly Flash in Macro 717"
|
|
group.byte 0x61E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH718,Uncommitted Supervisorly Flash in Macro 718"
|
|
group.byte 0x61F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH719,Uncommitted Supervisorly Flash in Macro 719"
|
|
group.byte 0x620++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH720,Uncommitted Supervisorly Flash in Macro 720"
|
|
group.byte 0x621++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH721,Uncommitted Supervisorly Flash in Macro 721"
|
|
group.byte 0x622++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH722,Uncommitted Supervisorly Flash in Macro 722"
|
|
group.byte 0x623++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH723,Uncommitted Supervisorly Flash in Macro 723"
|
|
group.byte 0x624++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH724,Uncommitted Supervisorly Flash in Macro 724"
|
|
group.byte 0x625++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH725,Uncommitted Supervisorly Flash in Macro 725"
|
|
group.byte 0x626++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH726,Uncommitted Supervisorly Flash in Macro 726"
|
|
group.byte 0x627++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH727,Uncommitted Supervisorly Flash in Macro 727"
|
|
group.byte 0x628++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH728,Uncommitted Supervisorly Flash in Macro 728"
|
|
group.byte 0x629++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH729,Uncommitted Supervisorly Flash in Macro 729"
|
|
group.byte 0x62A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH730,Uncommitted Supervisorly Flash in Macro 730"
|
|
group.byte 0x62B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH731,Uncommitted Supervisorly Flash in Macro 731"
|
|
group.byte 0x62C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH732,Uncommitted Supervisorly Flash in Macro 732"
|
|
group.byte 0x62D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH733,Uncommitted Supervisorly Flash in Macro 733"
|
|
group.byte 0x62E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH734,Uncommitted Supervisorly Flash in Macro 734"
|
|
group.byte 0x62F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH735,Uncommitted Supervisorly Flash in Macro 735"
|
|
group.byte 0x630++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH736,Uncommitted Supervisorly Flash in Macro 736"
|
|
group.byte 0x631++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH737,Uncommitted Supervisorly Flash in Macro 737"
|
|
group.byte 0x632++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH738,Uncommitted Supervisorly Flash in Macro 738"
|
|
group.byte 0x633++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH739,Uncommitted Supervisorly Flash in Macro 739"
|
|
group.byte 0x634++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH740,Uncommitted Supervisorly Flash in Macro 740"
|
|
group.byte 0x635++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH741,Uncommitted Supervisorly Flash in Macro 741"
|
|
group.byte 0x636++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH742,Uncommitted Supervisorly Flash in Macro 742"
|
|
group.byte 0x637++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH743,Uncommitted Supervisorly Flash in Macro 743"
|
|
group.byte 0x638++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH744,Uncommitted Supervisorly Flash in Macro 744"
|
|
group.byte 0x639++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH745,Uncommitted Supervisorly Flash in Macro 745"
|
|
group.byte 0x63A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH746,Uncommitted Supervisorly Flash in Macro 746"
|
|
group.byte 0x63B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH747,Uncommitted Supervisorly Flash in Macro 747"
|
|
group.byte 0x63C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH748,Uncommitted Supervisorly Flash in Macro 748"
|
|
group.byte 0x63D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH749,Uncommitted Supervisorly Flash in Macro 749"
|
|
group.byte 0x63E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH750,Uncommitted Supervisorly Flash in Macro 750"
|
|
group.byte 0x63F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH751,Uncommitted Supervisorly Flash in Macro 751"
|
|
group.byte 0x640++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH752,Uncommitted Supervisorly Flash in Macro 752"
|
|
group.byte 0x641++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH753,Uncommitted Supervisorly Flash in Macro 753"
|
|
group.byte 0x642++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH754,Uncommitted Supervisorly Flash in Macro 754"
|
|
group.byte 0x643++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH755,Uncommitted Supervisorly Flash in Macro 755"
|
|
group.byte 0x644++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH756,Uncommitted Supervisorly Flash in Macro 756"
|
|
group.byte 0x645++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH757,Uncommitted Supervisorly Flash in Macro 757"
|
|
group.byte 0x646++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH758,Uncommitted Supervisorly Flash in Macro 758"
|
|
group.byte 0x647++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH759,Uncommitted Supervisorly Flash in Macro 759"
|
|
group.byte 0x648++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH760,Uncommitted Supervisorly Flash in Macro 760"
|
|
group.byte 0x649++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH761,Uncommitted Supervisorly Flash in Macro 761"
|
|
group.byte 0x64A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH762,Uncommitted Supervisorly Flash in Macro 762"
|
|
group.byte 0x64B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH763,Uncommitted Supervisorly Flash in Macro 763"
|
|
group.byte 0x64C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH764,Uncommitted Supervisorly Flash in Macro 764"
|
|
group.byte 0x64D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH765,Uncommitted Supervisorly Flash in Macro 765"
|
|
group.byte 0x64E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH766,Uncommitted Supervisorly Flash in Macro 766"
|
|
group.byte 0x64F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH767,Uncommitted Supervisorly Flash in Macro 767"
|
|
group.byte 0x650++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH768,Uncommitted Supervisorly Flash in Macro 768"
|
|
group.byte 0x651++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH769,Uncommitted Supervisorly Flash in Macro 769"
|
|
group.byte 0x652++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH770,Uncommitted Supervisorly Flash in Macro 770"
|
|
group.byte 0x653++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH771,Uncommitted Supervisorly Flash in Macro 771"
|
|
group.byte 0x654++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH772,Uncommitted Supervisorly Flash in Macro 772"
|
|
group.byte 0x655++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH773,Uncommitted Supervisorly Flash in Macro 773"
|
|
group.byte 0x656++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH774,Uncommitted Supervisorly Flash in Macro 774"
|
|
group.byte 0x657++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH775,Uncommitted Supervisorly Flash in Macro 775"
|
|
group.byte 0x658++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH776,Uncommitted Supervisorly Flash in Macro 776"
|
|
group.byte 0x659++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH777,Uncommitted Supervisorly Flash in Macro 777"
|
|
group.byte 0x65A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH778,Uncommitted Supervisorly Flash in Macro 778"
|
|
group.byte 0x65B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH779,Uncommitted Supervisorly Flash in Macro 779"
|
|
group.byte 0x65C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH780,Uncommitted Supervisorly Flash in Macro 780"
|
|
group.byte 0x65D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH781,Uncommitted Supervisorly Flash in Macro 781"
|
|
group.byte 0x65E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH782,Uncommitted Supervisorly Flash in Macro 782"
|
|
group.byte 0x65F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH783,Uncommitted Supervisorly Flash in Macro 783"
|
|
group.byte 0x660++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH784,Uncommitted Supervisorly Flash in Macro 784"
|
|
group.byte 0x661++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH785,Uncommitted Supervisorly Flash in Macro 785"
|
|
group.byte 0x662++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH786,Uncommitted Supervisorly Flash in Macro 786"
|
|
group.byte 0x663++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH787,Uncommitted Supervisorly Flash in Macro 787"
|
|
group.byte 0x664++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH788,Uncommitted Supervisorly Flash in Macro 788"
|
|
group.byte 0x665++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH789,Uncommitted Supervisorly Flash in Macro 789"
|
|
group.byte 0x666++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH790,Uncommitted Supervisorly Flash in Macro 790"
|
|
group.byte 0x667++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH791,Uncommitted Supervisorly Flash in Macro 791"
|
|
group.byte 0x668++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH792,Uncommitted Supervisorly Flash in Macro 792"
|
|
group.byte 0x669++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH793,Uncommitted Supervisorly Flash in Macro 793"
|
|
group.byte 0x66A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH794,Uncommitted Supervisorly Flash in Macro 794"
|
|
group.byte 0x66B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH795,Uncommitted Supervisorly Flash in Macro 795"
|
|
group.byte 0x66C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH796,Uncommitted Supervisorly Flash in Macro 796"
|
|
group.byte 0x66D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH797,Uncommitted Supervisorly Flash in Macro 797"
|
|
group.byte 0x66E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH798,Uncommitted Supervisorly Flash in Macro 798"
|
|
group.byte 0x66F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH799,Uncommitted Supervisorly Flash in Macro 799"
|
|
group.byte 0x670++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH800,Uncommitted Supervisorly Flash in Macro 800"
|
|
group.byte 0x671++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH801,Uncommitted Supervisorly Flash in Macro 801"
|
|
group.byte 0x672++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH802,Uncommitted Supervisorly Flash in Macro 802"
|
|
group.byte 0x673++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH803,Uncommitted Supervisorly Flash in Macro 803"
|
|
group.byte 0x674++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH804,Uncommitted Supervisorly Flash in Macro 804"
|
|
group.byte 0x675++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH805,Uncommitted Supervisorly Flash in Macro 805"
|
|
group.byte 0x676++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH806,Uncommitted Supervisorly Flash in Macro 806"
|
|
group.byte 0x677++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH807,Uncommitted Supervisorly Flash in Macro 807"
|
|
group.byte 0x678++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH808,Uncommitted Supervisorly Flash in Macro 808"
|
|
group.byte 0x679++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH809,Uncommitted Supervisorly Flash in Macro 809"
|
|
group.byte 0x67A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH810,Uncommitted Supervisorly Flash in Macro 810"
|
|
group.byte 0x67B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH811,Uncommitted Supervisorly Flash in Macro 811"
|
|
group.byte 0x67C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH812,Uncommitted Supervisorly Flash in Macro 812"
|
|
group.byte 0x67D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH813,Uncommitted Supervisorly Flash in Macro 813"
|
|
group.byte 0x67E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH814,Uncommitted Supervisorly Flash in Macro 814"
|
|
group.byte 0x67F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH815,Uncommitted Supervisorly Flash in Macro 815"
|
|
group.byte 0x680++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH816,Uncommitted Supervisorly Flash in Macro 816"
|
|
group.byte 0x681++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH817,Uncommitted Supervisorly Flash in Macro 817"
|
|
group.byte 0x682++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH818,Uncommitted Supervisorly Flash in Macro 818"
|
|
group.byte 0x683++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH819,Uncommitted Supervisorly Flash in Macro 819"
|
|
group.byte 0x684++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH820,Uncommitted Supervisorly Flash in Macro 820"
|
|
group.byte 0x685++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH821,Uncommitted Supervisorly Flash in Macro 821"
|
|
group.byte 0x686++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH822,Uncommitted Supervisorly Flash in Macro 822"
|
|
group.byte 0x687++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH823,Uncommitted Supervisorly Flash in Macro 823"
|
|
group.byte 0x688++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH824,Uncommitted Supervisorly Flash in Macro 824"
|
|
group.byte 0x689++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH825,Uncommitted Supervisorly Flash in Macro 825"
|
|
group.byte 0x68A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH826,Uncommitted Supervisorly Flash in Macro 826"
|
|
group.byte 0x68B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH827,Uncommitted Supervisorly Flash in Macro 827"
|
|
group.byte 0x68C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH828,Uncommitted Supervisorly Flash in Macro 828"
|
|
group.byte 0x68D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH829,Uncommitted Supervisorly Flash in Macro 829"
|
|
group.byte 0x68E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH830,Uncommitted Supervisorly Flash in Macro 830"
|
|
group.byte 0x68F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH831,Uncommitted Supervisorly Flash in Macro 831"
|
|
group.byte 0x690++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH832,Uncommitted Supervisorly Flash in Macro 832"
|
|
group.byte 0x691++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH833,Uncommitted Supervisorly Flash in Macro 833"
|
|
group.byte 0x692++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH834,Uncommitted Supervisorly Flash in Macro 834"
|
|
group.byte 0x693++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH835,Uncommitted Supervisorly Flash in Macro 835"
|
|
group.byte 0x694++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH836,Uncommitted Supervisorly Flash in Macro 836"
|
|
group.byte 0x695++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH837,Uncommitted Supervisorly Flash in Macro 837"
|
|
group.byte 0x696++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH838,Uncommitted Supervisorly Flash in Macro 838"
|
|
group.byte 0x697++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH839,Uncommitted Supervisorly Flash in Macro 839"
|
|
group.byte 0x698++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH840,Uncommitted Supervisorly Flash in Macro 840"
|
|
group.byte 0x699++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH841,Uncommitted Supervisorly Flash in Macro 841"
|
|
group.byte 0x69A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH842,Uncommitted Supervisorly Flash in Macro 842"
|
|
group.byte 0x69B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH843,Uncommitted Supervisorly Flash in Macro 843"
|
|
group.byte 0x69C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH844,Uncommitted Supervisorly Flash in Macro 844"
|
|
group.byte 0x69D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH845,Uncommitted Supervisorly Flash in Macro 845"
|
|
group.byte 0x69E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH846,Uncommitted Supervisorly Flash in Macro 846"
|
|
group.byte 0x69F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH847,Uncommitted Supervisorly Flash in Macro 847"
|
|
group.byte 0x6A0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH848,Uncommitted Supervisorly Flash in Macro 848"
|
|
group.byte 0x6A1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH849,Uncommitted Supervisorly Flash in Macro 849"
|
|
group.byte 0x6A2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH850,Uncommitted Supervisorly Flash in Macro 850"
|
|
group.byte 0x6A3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH851,Uncommitted Supervisorly Flash in Macro 851"
|
|
group.byte 0x6A4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH852,Uncommitted Supervisorly Flash in Macro 852"
|
|
group.byte 0x6A5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH853,Uncommitted Supervisorly Flash in Macro 853"
|
|
group.byte 0x6A6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH854,Uncommitted Supervisorly Flash in Macro 854"
|
|
group.byte 0x6A7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH855,Uncommitted Supervisorly Flash in Macro 855"
|
|
group.byte 0x6A8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH856,Uncommitted Supervisorly Flash in Macro 856"
|
|
group.byte 0x6A9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH857,Uncommitted Supervisorly Flash in Macro 857"
|
|
group.byte 0x6AA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH858,Uncommitted Supervisorly Flash in Macro 858"
|
|
group.byte 0x6AB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH859,Uncommitted Supervisorly Flash in Macro 859"
|
|
group.byte 0x6AC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH860,Uncommitted Supervisorly Flash in Macro 860"
|
|
group.byte 0x6AD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH861,Uncommitted Supervisorly Flash in Macro 861"
|
|
group.byte 0x6AE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH862,Uncommitted Supervisorly Flash in Macro 862"
|
|
group.byte 0x6AF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH863,Uncommitted Supervisorly Flash in Macro 863"
|
|
group.byte 0x6B0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH864,Uncommitted Supervisorly Flash in Macro 864"
|
|
group.byte 0x6B1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH865,Uncommitted Supervisorly Flash in Macro 865"
|
|
group.byte 0x6B2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH866,Uncommitted Supervisorly Flash in Macro 866"
|
|
group.byte 0x6B3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH867,Uncommitted Supervisorly Flash in Macro 867"
|
|
group.byte 0x6B4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH868,Uncommitted Supervisorly Flash in Macro 868"
|
|
group.byte 0x6B5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH869,Uncommitted Supervisorly Flash in Macro 869"
|
|
group.byte 0x6B6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH870,Uncommitted Supervisorly Flash in Macro 870"
|
|
group.byte 0x6B7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH871,Uncommitted Supervisorly Flash in Macro 871"
|
|
group.byte 0x6B8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH872,Uncommitted Supervisorly Flash in Macro 872"
|
|
group.byte 0x6B9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH873,Uncommitted Supervisorly Flash in Macro 873"
|
|
group.byte 0x6BA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH874,Uncommitted Supervisorly Flash in Macro 874"
|
|
group.byte 0x6BB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH875,Uncommitted Supervisorly Flash in Macro 875"
|
|
group.byte 0x6BC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH876,Uncommitted Supervisorly Flash in Macro 876"
|
|
group.byte 0x6BD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH877,Uncommitted Supervisorly Flash in Macro 877"
|
|
group.byte 0x6BE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH878,Uncommitted Supervisorly Flash in Macro 878"
|
|
group.byte 0x6BF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH879,Uncommitted Supervisorly Flash in Macro 879"
|
|
group.byte 0x6C0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH880,Uncommitted Supervisorly Flash in Macro 880"
|
|
group.byte 0x6C1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH881,Uncommitted Supervisorly Flash in Macro 881"
|
|
group.byte 0x6C2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH882,Uncommitted Supervisorly Flash in Macro 882"
|
|
group.byte 0x6C3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH883,Uncommitted Supervisorly Flash in Macro 883"
|
|
group.byte 0x6C4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH884,Uncommitted Supervisorly Flash in Macro 884"
|
|
group.byte 0x6C5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH885,Uncommitted Supervisorly Flash in Macro 885"
|
|
group.byte 0x6C6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH886,Uncommitted Supervisorly Flash in Macro 886"
|
|
group.byte 0x6C7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH887,Uncommitted Supervisorly Flash in Macro 887"
|
|
group.byte 0x6C8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH888,Uncommitted Supervisorly Flash in Macro 888"
|
|
group.byte 0x6C9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH889,Uncommitted Supervisorly Flash in Macro 889"
|
|
group.byte 0x6CA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH890,Uncommitted Supervisorly Flash in Macro 890"
|
|
group.byte 0x6CB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH891,Uncommitted Supervisorly Flash in Macro 891"
|
|
group.byte 0x6CC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH892,Uncommitted Supervisorly Flash in Macro 892"
|
|
group.byte 0x6CD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH893,Uncommitted Supervisorly Flash in Macro 893"
|
|
group.byte 0x6CE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH894,Uncommitted Supervisorly Flash in Macro 894"
|
|
group.byte 0x6CF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH895,Uncommitted Supervisorly Flash in Macro 895"
|
|
group.byte 0x6D0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH896,Uncommitted Supervisorly Flash in Macro 896"
|
|
group.byte 0x6D1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH897,Uncommitted Supervisorly Flash in Macro 897"
|
|
group.byte 0x6D2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH898,Uncommitted Supervisorly Flash in Macro 898"
|
|
group.byte 0x6D3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH899,Uncommitted Supervisorly Flash in Macro 899"
|
|
group.byte 0x6D4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH900,Uncommitted Supervisorly Flash in Macro 900"
|
|
group.byte 0x6D5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH901,Uncommitted Supervisorly Flash in Macro 901"
|
|
group.byte 0x6D6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH902,Uncommitted Supervisorly Flash in Macro 902"
|
|
group.byte 0x6D7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH903,Uncommitted Supervisorly Flash in Macro 903"
|
|
group.byte 0x6D8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH904,Uncommitted Supervisorly Flash in Macro 904"
|
|
group.byte 0x6D9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH905,Uncommitted Supervisorly Flash in Macro 905"
|
|
group.byte 0x6DA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH906,Uncommitted Supervisorly Flash in Macro 906"
|
|
group.byte 0x6DB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH907,Uncommitted Supervisorly Flash in Macro 907"
|
|
group.byte 0x6DC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH908,Uncommitted Supervisorly Flash in Macro 908"
|
|
group.byte 0x6DD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH909,Uncommitted Supervisorly Flash in Macro 909"
|
|
group.byte 0x6DE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH910,Uncommitted Supervisorly Flash in Macro 910"
|
|
group.byte 0x6DF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH911,Uncommitted Supervisorly Flash in Macro 911"
|
|
group.byte 0x6E0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH912,Uncommitted Supervisorly Flash in Macro 912"
|
|
group.byte 0x6E1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH913,Uncommitted Supervisorly Flash in Macro 913"
|
|
group.byte 0x6E2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH914,Uncommitted Supervisorly Flash in Macro 914"
|
|
group.byte 0x6E3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH915,Uncommitted Supervisorly Flash in Macro 915"
|
|
group.byte 0x6E4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH916,Uncommitted Supervisorly Flash in Macro 916"
|
|
group.byte 0x6E5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH917,Uncommitted Supervisorly Flash in Macro 917"
|
|
group.byte 0x6E6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH918,Uncommitted Supervisorly Flash in Macro 918"
|
|
group.byte 0x6E7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH919,Uncommitted Supervisorly Flash in Macro 919"
|
|
group.byte 0x6E8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH920,Uncommitted Supervisorly Flash in Macro 920"
|
|
group.byte 0x6E9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH921,Uncommitted Supervisorly Flash in Macro 921"
|
|
group.byte 0x6EA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH922,Uncommitted Supervisorly Flash in Macro 922"
|
|
group.byte 0x6EB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH923,Uncommitted Supervisorly Flash in Macro 923"
|
|
group.byte 0x6EC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH924,Uncommitted Supervisorly Flash in Macro 924"
|
|
group.byte 0x6ED++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH925,Uncommitted Supervisorly Flash in Macro 925"
|
|
group.byte 0x6EE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH926,Uncommitted Supervisorly Flash in Macro 926"
|
|
group.byte 0x6EF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH927,Uncommitted Supervisorly Flash in Macro 927"
|
|
group.byte 0x6F0++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH928,Uncommitted Supervisorly Flash in Macro 928"
|
|
group.byte 0x6F1++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH929,Uncommitted Supervisorly Flash in Macro 929"
|
|
group.byte 0x6F2++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH930,Uncommitted Supervisorly Flash in Macro 930"
|
|
group.byte 0x6F3++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH931,Uncommitted Supervisorly Flash in Macro 931"
|
|
group.byte 0x6F4++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH932,Uncommitted Supervisorly Flash in Macro 932"
|
|
group.byte 0x6F5++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH933,Uncommitted Supervisorly Flash in Macro 933"
|
|
group.byte 0x6F6++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH934,Uncommitted Supervisorly Flash in Macro 934"
|
|
group.byte 0x6F7++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH935,Uncommitted Supervisorly Flash in Macro 935"
|
|
group.byte 0x6F8++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH936,Uncommitted Supervisorly Flash in Macro 936"
|
|
group.byte 0x6F9++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH937,Uncommitted Supervisorly Flash in Macro 937"
|
|
group.byte 0x6FA++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH938,Uncommitted Supervisorly Flash in Macro 938"
|
|
group.byte 0x6FB++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH939,Uncommitted Supervisorly Flash in Macro 939"
|
|
group.byte 0x6FC++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH940,Uncommitted Supervisorly Flash in Macro 940"
|
|
group.byte 0x6FD++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH941,Uncommitted Supervisorly Flash in Macro 941"
|
|
group.byte 0x6FE++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH942,Uncommitted Supervisorly Flash in Macro 942"
|
|
group.byte 0x6FF++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH943,Uncommitted Supervisorly Flash in Macro 943"
|
|
group.byte 0x700++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH944,Uncommitted Supervisorly Flash in Macro 944"
|
|
group.byte 0x701++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH945,Uncommitted Supervisorly Flash in Macro 945"
|
|
group.byte 0x702++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH946,Uncommitted Supervisorly Flash in Macro 946"
|
|
group.byte 0x703++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH947,Uncommitted Supervisorly Flash in Macro 947"
|
|
group.byte 0x704++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH948,Uncommitted Supervisorly Flash in Macro 948"
|
|
group.byte 0x705++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH949,Uncommitted Supervisorly Flash in Macro 949"
|
|
group.byte 0x706++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH950,Uncommitted Supervisorly Flash in Macro 950"
|
|
group.byte 0x707++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH951,Uncommitted Supervisorly Flash in Macro 951"
|
|
group.byte 0x708++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH952,Uncommitted Supervisorly Flash in Macro 952"
|
|
group.byte 0x709++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH953,Uncommitted Supervisorly Flash in Macro 953"
|
|
group.byte 0x70A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH954,Uncommitted Supervisorly Flash in Macro 954"
|
|
group.byte 0x70B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH955,Uncommitted Supervisorly Flash in Macro 955"
|
|
group.byte 0x70C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH956,Uncommitted Supervisorly Flash in Macro 956"
|
|
group.byte 0x70D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH957,Uncommitted Supervisorly Flash in Macro 957"
|
|
group.byte 0x70E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH958,Uncommitted Supervisorly Flash in Macro 958"
|
|
group.byte 0x70F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH959,Uncommitted Supervisorly Flash in Macro 959"
|
|
group.byte 0x710++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH960,Uncommitted Supervisorly Flash in Macro 960"
|
|
group.byte 0x711++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH961,Uncommitted Supervisorly Flash in Macro 961"
|
|
group.byte 0x712++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH962,Uncommitted Supervisorly Flash in Macro 962"
|
|
group.byte 0x713++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH963,Uncommitted Supervisorly Flash in Macro 963"
|
|
group.byte 0x714++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH964,Uncommitted Supervisorly Flash in Macro 964"
|
|
group.byte 0x715++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH965,Uncommitted Supervisorly Flash in Macro 965"
|
|
group.byte 0x716++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH966,Uncommitted Supervisorly Flash in Macro 966"
|
|
group.byte 0x717++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH967,Uncommitted Supervisorly Flash in Macro 967"
|
|
group.byte 0x718++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH968,Uncommitted Supervisorly Flash in Macro 968"
|
|
group.byte 0x719++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH969,Uncommitted Supervisorly Flash in Macro 969"
|
|
group.byte 0x71A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH970,Uncommitted Supervisorly Flash in Macro 970"
|
|
group.byte 0x71B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH971,Uncommitted Supervisorly Flash in Macro 971"
|
|
group.byte 0x71C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH972,Uncommitted Supervisorly Flash in Macro 972"
|
|
group.byte 0x71D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH973,Uncommitted Supervisorly Flash in Macro 973"
|
|
group.byte 0x71E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH974,Uncommitted Supervisorly Flash in Macro 974"
|
|
group.byte 0x71F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH975,Uncommitted Supervisorly Flash in Macro 975"
|
|
group.byte 0x720++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH976,Uncommitted Supervisorly Flash in Macro 976"
|
|
group.byte 0x721++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH977,Uncommitted Supervisorly Flash in Macro 977"
|
|
group.byte 0x722++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH978,Uncommitted Supervisorly Flash in Macro 978"
|
|
group.byte 0x723++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH979,Uncommitted Supervisorly Flash in Macro 979"
|
|
group.byte 0x724++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH980,Uncommitted Supervisorly Flash in Macro 980"
|
|
group.byte 0x725++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH981,Uncommitted Supervisorly Flash in Macro 981"
|
|
group.byte 0x726++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH982,Uncommitted Supervisorly Flash in Macro 982"
|
|
group.byte 0x727++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH983,Uncommitted Supervisorly Flash in Macro 983"
|
|
group.byte 0x728++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH984,Uncommitted Supervisorly Flash in Macro 984"
|
|
group.byte 0x729++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH985,Uncommitted Supervisorly Flash in Macro 985"
|
|
group.byte 0x72A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH986,Uncommitted Supervisorly Flash in Macro 986"
|
|
group.byte 0x72B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH987,Uncommitted Supervisorly Flash in Macro 987"
|
|
group.byte 0x72C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH988,Uncommitted Supervisorly Flash in Macro 988"
|
|
group.byte 0x72D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH989,Uncommitted Supervisorly Flash in Macro 989"
|
|
group.byte 0x72E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH990,Uncommitted Supervisorly Flash in Macro 990"
|
|
group.byte 0x72F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH991,Uncommitted Supervisorly Flash in Macro 991"
|
|
group.byte 0x730++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH992,Uncommitted Supervisorly Flash in Macro 992"
|
|
group.byte 0x731++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH993,Uncommitted Supervisorly Flash in Macro 993"
|
|
group.byte 0x732++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH994,Uncommitted Supervisorly Flash in Macro 994"
|
|
group.byte 0x733++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH995,Uncommitted Supervisorly Flash in Macro 995"
|
|
group.byte 0x734++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH996,Uncommitted Supervisorly Flash in Macro 996"
|
|
group.byte 0x735++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH997,Uncommitted Supervisorly Flash in Macro 997"
|
|
group.byte 0x736++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH998,Uncommitted Supervisorly Flash in Macro 998"
|
|
group.byte 0x737++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH999,Uncommitted Supervisorly Flash in Macro 999"
|
|
group.byte 0x738++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1000,Uncommitted Supervisorly Flash in Macro 1000"
|
|
group.byte 0x739++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1001,Uncommitted Supervisorly Flash in Macro 1001"
|
|
group.byte 0x73A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1002,Uncommitted Supervisorly Flash in Macro 1002"
|
|
group.byte 0x73B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1003,Uncommitted Supervisorly Flash in Macro 1003"
|
|
group.byte 0x73C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1004,Uncommitted Supervisorly Flash in Macro 1004"
|
|
group.byte 0x73D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1005,Uncommitted Supervisorly Flash in Macro 1005"
|
|
group.byte 0x73E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1006,Uncommitted Supervisorly Flash in Macro 1006"
|
|
group.byte 0x73F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1007,Uncommitted Supervisorly Flash in Macro 1007"
|
|
group.byte 0x740++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1008,Uncommitted Supervisorly Flash in Macro 1008"
|
|
group.byte 0x741++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1009,Uncommitted Supervisorly Flash in Macro 1009"
|
|
group.byte 0x742++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1010,Uncommitted Supervisorly Flash in Macro 1010"
|
|
group.byte 0x743++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1011,Uncommitted Supervisorly Flash in Macro 1011"
|
|
group.byte 0x744++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1012,Uncommitted Supervisorly Flash in Macro 1012"
|
|
group.byte 0x745++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1013,Uncommitted Supervisorly Flash in Macro 1013"
|
|
group.byte 0x746++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1014,Uncommitted Supervisorly Flash in Macro 1014"
|
|
group.byte 0x747++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1015,Uncommitted Supervisorly Flash in Macro 1015"
|
|
group.byte 0x748++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1016,Uncommitted Supervisorly Flash in Macro 1016"
|
|
group.byte 0x749++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1017,Uncommitted Supervisorly Flash in Macro 1017"
|
|
group.byte 0x74A++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1018,Uncommitted Supervisorly Flash in Macro 1018"
|
|
group.byte 0x74B++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1019,Uncommitted Supervisorly Flash in Macro 1019"
|
|
group.byte 0x74C++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1020,Uncommitted Supervisorly Flash in Macro 1020"
|
|
group.byte 0x74D++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1021,Uncommitted Supervisorly Flash in Macro 1021"
|
|
group.byte 0x74E++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1022,Uncommitted Supervisorly Flash in Macro 1022"
|
|
group.byte 0x74F++0x00
|
|
line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1023,Uncommitted Supervisorly Flash in Macro 1023"
|
|
endif
|
|
tree.end
|
|
textline " "
|
|
tree "SFLASH_ALT_PROT_ROW"
|
|
group.byte 0x800++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW0,Per Page Write Protection 0"
|
|
group.byte 0x801++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW1,Per Page Write Protection 1"
|
|
group.byte 0x802++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW2,Per Page Write Protection 2"
|
|
group.byte 0x803++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW3,Per Page Write Protection 3"
|
|
group.byte 0x804++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW4,Per Page Write Protection 4"
|
|
group.byte 0x805++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW5,Per Page Write Protection 5"
|
|
group.byte 0x806++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW6,Per Page Write Protection 6"
|
|
group.byte 0x807++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW7,Per Page Write Protection 7"
|
|
group.byte 0x808++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW8,Per Page Write Protection 8"
|
|
group.byte 0x809++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW9,Per Page Write Protection 9"
|
|
group.byte 0x80A++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW10,Per Page Write Protection 10"
|
|
group.byte 0x80B++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW11,Per Page Write Protection 11"
|
|
group.byte 0x80C++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW12,Per Page Write Protection 12"
|
|
group.byte 0x80D++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW13,Per Page Write Protection 13"
|
|
group.byte 0x80E++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW14,Per Page Write Protection 14"
|
|
group.byte 0x80F++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW15,Per Page Write Protection 15"
|
|
group.byte 0x810++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW16,Per Page Write Protection 16"
|
|
group.byte 0x811++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW17,Per Page Write Protection 17"
|
|
group.byte 0x812++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW18,Per Page Write Protection 18"
|
|
group.byte 0x813++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW19,Per Page Write Protection 19"
|
|
group.byte 0x814++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW20,Per Page Write Protection 20"
|
|
group.byte 0x815++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW21,Per Page Write Protection 21"
|
|
group.byte 0x816++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW22,Per Page Write Protection 22"
|
|
group.byte 0x817++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW23,Per Page Write Protection 23"
|
|
group.byte 0x818++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW24,Per Page Write Protection 24"
|
|
group.byte 0x819++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW25,Per Page Write Protection 25"
|
|
group.byte 0x81A++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW26,Per Page Write Protection 26"
|
|
group.byte 0x81B++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW27,Per Page Write Protection 27"
|
|
group.byte 0x81C++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW28,Per Page Write Protection 28"
|
|
group.byte 0x81D++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW29,Per Page Write Protection 29"
|
|
group.byte 0x81E++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW30,Per Page Write Protection 30"
|
|
group.byte 0x81F++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW31,Per Page Write Protection 31"
|
|
group.byte 0x820++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW32,Per Page Write Protection 32"
|
|
group.byte 0x821++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW33,Per Page Write Protection 33"
|
|
group.byte 0x822++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW34,Per Page Write Protection 34"
|
|
group.byte 0x823++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW35,Per Page Write Protection 35"
|
|
group.byte 0x824++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW36,Per Page Write Protection 36"
|
|
group.byte 0x825++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW37,Per Page Write Protection 37"
|
|
group.byte 0x826++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW38,Per Page Write Protection 38"
|
|
group.byte 0x827++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW39,Per Page Write Protection 39"
|
|
group.byte 0x828++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW40,Per Page Write Protection 40"
|
|
group.byte 0x829++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW41,Per Page Write Protection 41"
|
|
group.byte 0x82A++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW42,Per Page Write Protection 42"
|
|
group.byte 0x82B++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW43,Per Page Write Protection 43"
|
|
group.byte 0x82C++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW44,Per Page Write Protection 44"
|
|
group.byte 0x82D++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW45,Per Page Write Protection 45"
|
|
group.byte 0x82E++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW46,Per Page Write Protection 46"
|
|
group.byte 0x82F++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW47,Per Page Write Protection 47"
|
|
group.byte 0x830++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW48,Per Page Write Protection 48"
|
|
group.byte 0x831++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW49,Per Page Write Protection 49"
|
|
group.byte 0x832++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW50,Per Page Write Protection 50"
|
|
group.byte 0x833++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW51,Per Page Write Protection 51"
|
|
group.byte 0x834++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW52,Per Page Write Protection 52"
|
|
group.byte 0x835++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW53,Per Page Write Protection 53"
|
|
group.byte 0x836++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW54,Per Page Write Protection 54"
|
|
group.byte 0x837++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW55,Per Page Write Protection 55"
|
|
group.byte 0x838++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW56,Per Page Write Protection 56"
|
|
group.byte 0x839++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW57,Per Page Write Protection 57"
|
|
group.byte 0x83A++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW58,Per Page Write Protection 58"
|
|
group.byte 0x83B++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW59,Per Page Write Protection 59"
|
|
group.byte 0x83C++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW60,Per Page Write Protection 60"
|
|
group.byte 0x83D++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW61,Per Page Write Protection 61"
|
|
group.byte 0x83E++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW62,Per Page Write Protection 62"
|
|
group.byte 0x83F++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW63,Per Page Write Protection 63"
|
|
group.byte 0x840++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW64,Per Page Write Protection 64"
|
|
group.byte 0x841++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW65,Per Page Write Protection 65"
|
|
group.byte 0x842++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW66,Per Page Write Protection 66"
|
|
group.byte 0x843++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW67,Per Page Write Protection 67"
|
|
group.byte 0x844++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW68,Per Page Write Protection 68"
|
|
group.byte 0x845++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW69,Per Page Write Protection 69"
|
|
group.byte 0x846++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW70,Per Page Write Protection 70"
|
|
group.byte 0x847++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW71,Per Page Write Protection 71"
|
|
group.byte 0x848++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW72,Per Page Write Protection 72"
|
|
group.byte 0x849++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW73,Per Page Write Protection 73"
|
|
group.byte 0x84A++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW74,Per Page Write Protection 74"
|
|
group.byte 0x84B++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW75,Per Page Write Protection 75"
|
|
group.byte 0x84C++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW76,Per Page Write Protection 76"
|
|
group.byte 0x84D++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW77,Per Page Write Protection 77"
|
|
group.byte 0x84E++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW78,Per Page Write Protection 78"
|
|
group.byte 0x84F++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW79,Per Page Write Protection 79"
|
|
group.byte 0x850++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW80,Per Page Write Protection 80"
|
|
group.byte 0x851++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW81,Per Page Write Protection 81"
|
|
group.byte 0x852++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW82,Per Page Write Protection 82"
|
|
group.byte 0x853++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW83,Per Page Write Protection 83"
|
|
group.byte 0x854++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW84,Per Page Write Protection 84"
|
|
group.byte 0x855++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW85,Per Page Write Protection 85"
|
|
group.byte 0x856++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW86,Per Page Write Protection 86"
|
|
group.byte 0x857++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW87,Per Page Write Protection 87"
|
|
group.byte 0x858++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW88,Per Page Write Protection 88"
|
|
group.byte 0x859++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW89,Per Page Write Protection 89"
|
|
group.byte 0x85A++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW90,Per Page Write Protection 90"
|
|
group.byte 0x85B++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW91,Per Page Write Protection 91"
|
|
group.byte 0x85C++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW92,Per Page Write Protection 92"
|
|
group.byte 0x85D++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW93,Per Page Write Protection 93"
|
|
group.byte 0x85E++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW94,Per Page Write Protection 94"
|
|
group.byte 0x85F++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW95,Per Page Write Protection 95"
|
|
group.byte 0x860++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW96,Per Page Write Protection 96"
|
|
group.byte 0x861++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW97,Per Page Write Protection 97"
|
|
group.byte 0x862++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW98,Per Page Write Protection 98"
|
|
group.byte 0x863++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW99,Per Page Write Protection 99"
|
|
group.byte 0x864++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW100,Per Page Write Protection 100"
|
|
group.byte 0x865++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW101,Per Page Write Protection 101"
|
|
group.byte 0x866++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW102,Per Page Write Protection 102"
|
|
group.byte 0x867++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW103,Per Page Write Protection 103"
|
|
group.byte 0x868++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW104,Per Page Write Protection 104"
|
|
group.byte 0x869++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW105,Per Page Write Protection 105"
|
|
group.byte 0x86A++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW106,Per Page Write Protection 106"
|
|
group.byte 0x86B++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW107,Per Page Write Protection 107"
|
|
group.byte 0x86C++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW108,Per Page Write Protection 108"
|
|
group.byte 0x86D++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW109,Per Page Write Protection 109"
|
|
group.byte 0x86E++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW110,Per Page Write Protection 110"
|
|
group.byte 0x86F++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW111,Per Page Write Protection 111"
|
|
group.byte 0x870++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW112,Per Page Write Protection 112"
|
|
group.byte 0x871++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW113,Per Page Write Protection 113"
|
|
group.byte 0x872++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW114,Per Page Write Protection 114"
|
|
group.byte 0x873++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW115,Per Page Write Protection 115"
|
|
group.byte 0x874++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW116,Per Page Write Protection 116"
|
|
group.byte 0x875++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW117,Per Page Write Protection 117"
|
|
group.byte 0x876++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW118,Per Page Write Protection 118"
|
|
group.byte 0x877++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW119,Per Page Write Protection 119"
|
|
group.byte 0x878++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW120,Per Page Write Protection 120"
|
|
group.byte 0x879++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW121,Per Page Write Protection 121"
|
|
group.byte 0x87A++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW122,Per Page Write Protection 122"
|
|
group.byte 0x87B++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW123,Per Page Write Protection 123"
|
|
group.byte 0x87C++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW124,Per Page Write Protection 124"
|
|
group.byte 0x87D++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW125,Per Page Write Protection 125"
|
|
group.byte 0x87E++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW126,Per Page Write Protection 126"
|
|
group.byte 0x87F++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW127,Per Page Write Protection 127"
|
|
group.byte 0x880++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW128,Per Page Write Protection 128"
|
|
group.byte 0x881++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW129,Per Page Write Protection 129"
|
|
group.byte 0x882++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW130,Per Page Write Protection 130"
|
|
group.byte 0x883++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW131,Per Page Write Protection 131"
|
|
group.byte 0x884++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW132,Per Page Write Protection 132"
|
|
group.byte 0x885++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW133,Per Page Write Protection 133"
|
|
group.byte 0x886++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW134,Per Page Write Protection 134"
|
|
group.byte 0x887++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW135,Per Page Write Protection 135"
|
|
group.byte 0x888++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW136,Per Page Write Protection 136"
|
|
group.byte 0x889++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW137,Per Page Write Protection 137"
|
|
group.byte 0x88A++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW138,Per Page Write Protection 138"
|
|
group.byte 0x88B++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW139,Per Page Write Protection 139"
|
|
group.byte 0x88C++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW140,Per Page Write Protection 140"
|
|
group.byte 0x88D++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW141,Per Page Write Protection 141"
|
|
group.byte 0x88E++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW142,Per Page Write Protection 142"
|
|
group.byte 0x88F++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW143,Per Page Write Protection 143"
|
|
group.byte 0x890++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW144,Per Page Write Protection 144"
|
|
group.byte 0x891++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW145,Per Page Write Protection 145"
|
|
group.byte 0x892++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW146,Per Page Write Protection 146"
|
|
group.byte 0x893++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW147,Per Page Write Protection 147"
|
|
group.byte 0x894++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW148,Per Page Write Protection 148"
|
|
group.byte 0x895++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW149,Per Page Write Protection 149"
|
|
group.byte 0x896++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW150,Per Page Write Protection 150"
|
|
group.byte 0x897++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW151,Per Page Write Protection 151"
|
|
group.byte 0x898++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW152,Per Page Write Protection 152"
|
|
group.byte 0x899++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW153,Per Page Write Protection 153"
|
|
group.byte 0x89A++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW154,Per Page Write Protection 154"
|
|
group.byte 0x89B++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW155,Per Page Write Protection 155"
|
|
group.byte 0x89C++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW156,Per Page Write Protection 156"
|
|
group.byte 0x89D++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW157,Per Page Write Protection 157"
|
|
group.byte 0x89E++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW158,Per Page Write Protection 158"
|
|
group.byte 0x89F++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW159,Per Page Write Protection 159"
|
|
group.byte 0x8A0++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW160,Per Page Write Protection 160"
|
|
group.byte 0x8A1++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW161,Per Page Write Protection 161"
|
|
group.byte 0x8A2++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW162,Per Page Write Protection 162"
|
|
group.byte 0x8A3++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW163,Per Page Write Protection 163"
|
|
group.byte 0x8A4++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW164,Per Page Write Protection 164"
|
|
group.byte 0x8A5++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW165,Per Page Write Protection 165"
|
|
group.byte 0x8A6++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW166,Per Page Write Protection 166"
|
|
group.byte 0x8A7++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW167,Per Page Write Protection 167"
|
|
group.byte 0x8A8++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW168,Per Page Write Protection 168"
|
|
group.byte 0x8A9++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW169,Per Page Write Protection 169"
|
|
group.byte 0x8AA++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW170,Per Page Write Protection 170"
|
|
group.byte 0x8AB++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW171,Per Page Write Protection 171"
|
|
group.byte 0x8AC++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW172,Per Page Write Protection 172"
|
|
group.byte 0x8AD++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW173,Per Page Write Protection 173"
|
|
group.byte 0x8AE++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW174,Per Page Write Protection 174"
|
|
group.byte 0x8AF++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW175,Per Page Write Protection 175"
|
|
group.byte 0x8B0++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW176,Per Page Write Protection 176"
|
|
group.byte 0x8B1++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW177,Per Page Write Protection 177"
|
|
group.byte 0x8B2++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW178,Per Page Write Protection 178"
|
|
group.byte 0x8B3++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW179,Per Page Write Protection 179"
|
|
group.byte 0x8B4++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW180,Per Page Write Protection 180"
|
|
group.byte 0x8B5++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW181,Per Page Write Protection 181"
|
|
group.byte 0x8B6++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW182,Per Page Write Protection 182"
|
|
group.byte 0x8B7++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW183,Per Page Write Protection 183"
|
|
group.byte 0x8B8++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW184,Per Page Write Protection 184"
|
|
group.byte 0x8B9++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW185,Per Page Write Protection 185"
|
|
group.byte 0x8BA++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW186,Per Page Write Protection 186"
|
|
group.byte 0x8BB++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW187,Per Page Write Protection 187"
|
|
group.byte 0x8BC++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW188,Per Page Write Protection 188"
|
|
group.byte 0x8BD++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW189,Per Page Write Protection 189"
|
|
group.byte 0x8BE++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW190,Per Page Write Protection 190"
|
|
group.byte 0x8BF++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW191,Per Page Write Protection 191"
|
|
group.byte 0x8C0++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW192,Per Page Write Protection 192"
|
|
group.byte 0x8C1++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW193,Per Page Write Protection 193"
|
|
group.byte 0x8C2++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW194,Per Page Write Protection 194"
|
|
group.byte 0x8C3++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW195,Per Page Write Protection 195"
|
|
group.byte 0x8C4++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW196,Per Page Write Protection 196"
|
|
group.byte 0x8C5++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW197,Per Page Write Protection 197"
|
|
group.byte 0x8C6++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW198,Per Page Write Protection 198"
|
|
group.byte 0x8C7++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW199,Per Page Write Protection 199"
|
|
group.byte 0x8C8++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW200,Per Page Write Protection 200"
|
|
group.byte 0x8C9++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW201,Per Page Write Protection 201"
|
|
group.byte 0x8CA++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW202,Per Page Write Protection 202"
|
|
group.byte 0x8CB++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW203,Per Page Write Protection 203"
|
|
group.byte 0x8CC++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW204,Per Page Write Protection 204"
|
|
group.byte 0x8CD++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW205,Per Page Write Protection 205"
|
|
group.byte 0x8CE++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW206,Per Page Write Protection 206"
|
|
group.byte 0x8CF++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW207,Per Page Write Protection 207"
|
|
group.byte 0x8D0++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW208,Per Page Write Protection 208"
|
|
group.byte 0x8D1++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW209,Per Page Write Protection 209"
|
|
group.byte 0x8D2++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW210,Per Page Write Protection 210"
|
|
group.byte 0x8D3++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW211,Per Page Write Protection 211"
|
|
group.byte 0x8D4++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW212,Per Page Write Protection 212"
|
|
group.byte 0x8D5++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW213,Per Page Write Protection 213"
|
|
group.byte 0x8D6++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW214,Per Page Write Protection 214"
|
|
group.byte 0x8D7++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW215,Per Page Write Protection 215"
|
|
group.byte 0x8D8++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW216,Per Page Write Protection 216"
|
|
group.byte 0x8D9++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW217,Per Page Write Protection 217"
|
|
group.byte 0x8DA++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW218,Per Page Write Protection 218"
|
|
group.byte 0x8DB++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW219,Per Page Write Protection 219"
|
|
group.byte 0x8DC++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW220,Per Page Write Protection 220"
|
|
group.byte 0x8DD++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW221,Per Page Write Protection 221"
|
|
group.byte 0x8DE++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW222,Per Page Write Protection 222"
|
|
group.byte 0x8DF++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW223,Per Page Write Protection 223"
|
|
group.byte 0x8E0++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW224,Per Page Write Protection 224"
|
|
group.byte 0x8E1++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW225,Per Page Write Protection 225"
|
|
group.byte 0x8E2++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW226,Per Page Write Protection 226"
|
|
group.byte 0x8E3++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW227,Per Page Write Protection 227"
|
|
group.byte 0x8E4++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW228,Per Page Write Protection 228"
|
|
group.byte 0x8E5++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW229,Per Page Write Protection 229"
|
|
group.byte 0x8E6++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW230,Per Page Write Protection 230"
|
|
group.byte 0x8E7++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW231,Per Page Write Protection 231"
|
|
group.byte 0x8E8++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW232,Per Page Write Protection 232"
|
|
group.byte 0x8E9++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW233,Per Page Write Protection 233"
|
|
group.byte 0x8EA++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW234,Per Page Write Protection 234"
|
|
group.byte 0x8EB++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW235,Per Page Write Protection 235"
|
|
group.byte 0x8EC++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW236,Per Page Write Protection 236"
|
|
group.byte 0x8ED++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW237,Per Page Write Protection 237"
|
|
group.byte 0x8EE++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW238,Per Page Write Protection 238"
|
|
group.byte 0x8EF++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW239,Per Page Write Protection 239"
|
|
group.byte 0x8F0++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW240,Per Page Write Protection 240"
|
|
group.byte 0x8F1++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW241,Per Page Write Protection 241"
|
|
group.byte 0x8F2++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW242,Per Page Write Protection 242"
|
|
group.byte 0x8F3++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW243,Per Page Write Protection 243"
|
|
group.byte 0x8F4++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW244,Per Page Write Protection 244"
|
|
group.byte 0x8F5++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW245,Per Page Write Protection 245"
|
|
group.byte 0x8F6++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW246,Per Page Write Protection 246"
|
|
group.byte 0x8F7++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW247,Per Page Write Protection 247"
|
|
group.byte 0x8F8++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW248,Per Page Write Protection 248"
|
|
group.byte 0x8F9++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW249,Per Page Write Protection 249"
|
|
group.byte 0x8FA++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW250,Per Page Write Protection 250"
|
|
group.byte 0x8FB++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW251,Per Page Write Protection 251"
|
|
group.byte 0x8FC++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW252,Per Page Write Protection 252"
|
|
group.byte 0x8FD++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW253,Per Page Write Protection 253"
|
|
group.byte 0x8FE++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW254,Per Page Write Protection 254"
|
|
group.byte 0x8FF++0x00
|
|
line.byte 0x00 "SFLASH_ALT_PROT_ROW255,Per Page Write Protection 255"
|
|
tree.end
|
|
textline " "
|
|
group.long 0xB20++0x1B
|
|
line.long 0x00 "SFLASH_ALT_PP,Preprogram Settings"
|
|
bitfld.long 0x00 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x04 "SFLASH_ALT_E,Erase Settings"
|
|
bitfld.long 0x04 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x08 "SFLASH_ALT_P,Program Settings"
|
|
bitfld.long 0x08 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x0C "SFLASH_ALT_EA_E,Erase All - Erase Settings"
|
|
bitfld.long 0x0C 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x10 "SFLASH_ALT_EA_P,Erase All - Program Settings"
|
|
bitfld.long 0x10 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x14 "SFLASH_ALT_ES_E,Erase Sector - Erase Settings"
|
|
bitfld.long 0x14 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x18 "SFLASH_ALT_ES_P_EO,Erase Sector - Program EO Settings"
|
|
bitfld.long 0x18 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
group.byte 0xB3C++0x01
|
|
line.byte 0x00 "SFLASH_ALT_E_VCTAT,Bandgap Trim Register"
|
|
bitfld.byte 0x00 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "SFLASH_ALT_P_VCTAT,Bandgap Trim Register"
|
|
bitfld.byte 0x01 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3"
|
|
bitfld.byte 0x01 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "SPCIF (SPC Interface)"
|
|
base ad:0x40110000
|
|
width 19.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GEOMETRY,Flash/NVL Geometry Information"
|
|
bitfld.long 0x00 31. " DE_CPD_LP ,Busy wait loop copy to SRAM" "Not copied,Copied"
|
|
sif cpuis("CY8C4*-BL*")
|
|
hexmask.long.byte 0x00 24.--30. 1. " NVL ,NVLatch size in byte multiples"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 22.--23. " FLASH_ROW ,Page size in 64 byte multiplies" "64 bytes,128 bytes,192 bytes,256 bytes"
|
|
rbitfld.long 0x00 20.--21. " NUM_FLASH ,Number of flash macros" "0,1,2,3"
|
|
sif cpuis("CY8C4*-BL*")
|
|
rbitfld.long 0x00 16.--19. " SFLASH ,Supervisory flash capacity in 256 byte multiplies" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " FLASH ,Regular flash capacity in 256 byte multiplies"
|
|
else
|
|
rbitfld.long 0x00 14.--19. " SFLASH ,Supervisory flash capacity in 256 byte multiplies" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,4352 bytes,4608 bytes,4864 bytes,5120 bytes,5376 bytes,5632 bytes,5888 bytes,6144 bytes,6400 bytes,6656 bytes,6912 bytes,7168 bytes,7424 bytes,7680 bytes,7936 bytes,8192 bytes,8448 bytes,8704 bytes,8960 bytes,9216 bytes,9472 bytes,9728 bytes,9984 bytes,10240 bytes,10496 bytes,10752 bytes,11008 bytes,11264 bytes,11520 bytes,11776 bytes,12032 bytes,12288 bytes,12544 bytes,12800 bytes,13056 bytes,13312 bytes,13568 bytes,13824 bytes,14080 bytes,14336 bytes,14592 bytes,14848 bytes,15104 bytes,15360 bytes,15616 bytes,15872 bytes,16128 bytes,16384 bytes"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--13. 1. " FLASH ,Regular flash capacity in 256 byte multiplies"
|
|
endif
|
|
group.long 0x7F0++0x0B
|
|
line.long 0x00 "INTR,SPCIF Interrupt Request Register"
|
|
eventfld.long 0x00 0. " TIMER ,Timer count value reaches '0'" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,SPCIF Interrupt Set Request Register"
|
|
bitfld.long 0x04 0. " TIMER ,Set corresponding INTR field" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,SPCIF Interrupt Mask Register"
|
|
bitfld.long 0x08 0. " TIMER ,Mask for corresponding field in INTR register" "Not masked,Masked"
|
|
rgroup.long 0x7FC++0x03
|
|
line.long 0x00 "INTR_MASKED,SPCIF Interrupt Masked Request Register"
|
|
bitfld.long 0x00 0. " TIMER ,Logical AND of corresponding and mask field" "Not masked,Masked"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TCPWM (Timer Counter PWM)"
|
|
base ad:0x40200000
|
|
width 12.
|
|
sif (cpuis("CY8C4A24*"))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,TCPWM Control Register 0"
|
|
bitfld.long 0x00 3. " COUNTER_ENABLED[3] ,Counter enable for counter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " COUNTER_ENABLED[2] ,Counter enable for counter 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COUNTER_ENABLED[1] ,Counter enable for counter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COUNTER_ENABLED[0] ,Counter enable for counter 0" "Disabled,Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMD,TCPWM Command Register"
|
|
bitfld.long 0x00 27. " COUNTER_START[3] ,Counter 3 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 26. " COUNTER_START[2] ,Counter 2 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 25. " COUNTER_START[1] ,Counter 1 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 24. " COUNTER_START[0] ,Counter 0 SW start trigger" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 19. " COUNTER_STOP[3] ,Counter 3 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 18. " COUNTER_STOP[2] ,Counter 2 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 17. " COUNTER_STOP[1] ,Counter 1 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 16. " COUNTER_STOP[0] ,Counter 0 SW stop trigger" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COUNTER_RELOAD[3] ,Counter 3 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 10. " COUNTER_RELOAD[2] ,Counter 2 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 9. " COUNTER_RELOAD[1] ,Counter 1 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 8. " COUNTER_RELOAD[0] ,Counter 0 SW reload trigger" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COUNTER_CAPTURE[3] ,Counter 3 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 2. " COUNTER_CAPTURE[2] ,Counter 2 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 1. " COUNTER_CAPTURE[1] ,Counter 1 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 0. " COUNTER_CAPTURE[0] ,Counter 0 SW capture trigger" "Not captured,Captured"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "INTR_CAUSE,TCPWM Counter Interrupt Cause Register"
|
|
bitfld.long 0x00 3. " COUNTER_INT[3] ,Counter 3 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " COUNTER_INT[2] ,Counter 2 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " COUNTER_INT[1] ,Counter 1 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " COUNTER_INT[0] ,Counter 0 interrupt signal active" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,TCPWM Control Register 0"
|
|
bitfld.long 0x00 7. " COUNTER_ENABLED[7] ,Counter enable for counter 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " COUNTER_ENABLED[6] ,Counter enable for counter 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " COUNTER_ENABLED[5] ,Counter enable for counter 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " COUNTER_ENABLED[4] ,Counter enable for counter 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COUNTER_ENABLED[3] ,Counter enable for counter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " COUNTER_ENABLED[2] ,Counter enable for counter 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COUNTER_ENABLED[1] ,Counter enable for counter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COUNTER_ENABLED[0] ,Counter enable for counter 0" "Disabled,Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMD,TCPWM Command Register"
|
|
bitfld.long 0x00 31. " COUNTER_START[7] ,Counter 7 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 30. " COUNTER_START[6] ,Counter 6 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 29. " COUNTER_START[5] ,Counter 5 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 28. " COUNTER_START[4] ,Counter 4 SW start trigger" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 27. " COUNTER_START[3] ,Counter 3 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 26. " COUNTER_START[2] ,Counter 2 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 25. " COUNTER_START[1] ,Counter 1 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 24. " COUNTER_START[0] ,Counter 0 SW start trigger" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 23. " COUNTER_STOP[7] ,Counter 7 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 22. " COUNTER_STOP[6] ,Counter 6 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 21. " COUNTER_STOP[5] ,Counter 5 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 20. " COUNTER_STOP[4] ,Counter 4 SW stop trigger" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 19. " COUNTER_STOP[3] ,Counter 3 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 18. " COUNTER_STOP[2] ,Counter 2 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 17. " COUNTER_STOP[1] ,Counter 1 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 16. " COUNTER_STOP[0] ,Counter 0 SW stop trigger" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 15. " COUNTER_RELOAD[7] ,Counter 7 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 14. " COUNTER_RELOAD[6] ,Counter 6 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 13. " COUNTER_RELOAD[5] ,Counter 5 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 12. " COUNTER_RELOAD[4] ,Counter 4 SW reload trigger" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COUNTER_RELOAD[3] ,Counter 3 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 10. " COUNTER_RELOAD[2] ,Counter 2 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 9. " COUNTER_RELOAD[1] ,Counter 1 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 8. " COUNTER_RELOAD[0] ,Counter 0 SW reload trigger" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x00 7. " COUNTER_CAPTURE[7] ,Counter 7 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 6. " COUNTER_CAPTURE[6] ,Counter 6 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 5. " COUNTER_CAPTURE[5] ,Counter 5 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 4. " COUNTER_CAPTURE[4] ,Counter 4 SW capture trigger" "Not captured,Captured"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COUNTER_CAPTURE[3] ,Counter 3 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 2. " COUNTER_CAPTURE[2] ,Counter 2 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 1. " COUNTER_CAPTURE[1] ,Counter 1 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 0. " COUNTER_CAPTURE[0] ,Counter 0 SW capture trigger" "Not captured,Captured"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "INTR_CAUSE,TCPWM Counter Interrupt Cause Register"
|
|
bitfld.long 0x00 7. " COUNTER_INT[7] ,Counter 7 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " COUNTER_INT[6] ,Counter 6 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " COUNTER_INT[5] ,Counter 5 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " COUNTER_INT[4] ,Counter 4 interrupt signal active" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COUNTER_INT[3] ,Counter 3 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " COUNTER_INT[2] ,Counter 2 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " COUNTER_INT[1] ,Counter 1 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " COUNTER_INT[0] ,Counter 0 interrupt signal active" "No interrupt,Interrupt"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TST (Test)"
|
|
base ad:0x40030000
|
|
width 12.
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TST_MODE,Test Mode Control Register"
|
|
bitfld.long 0x00 31. " TEST_MODE ,Test mode" "Normal mode,Test mode"
|
|
rbitfld.long 0x00 30. " POR_BYPASS ,POR bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 2. " SWD_CONNECTED ,SWD connect" "Not connected,Connected"
|
|
width 0xB
|
|
tree.end
|
|
sif cpuis("CY8C42*-BL*")
|
|
tree "UDBIF (UDB Interface)"
|
|
base ad:0x400F7000
|
|
width 13.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "BANK_CTL,Bank Control"
|
|
bitfld.byte 0x00 7. " GLBL_WR ,UDB array global writing option" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " PIPE ,Pipelining control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " LOCK ,UDB array configuration locking" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BANK_EN ,Enable bank" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " ROUTE_EN ,Enable routing" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " DIS_COR ,Selection of Clear-On-Read" "Enabled,Disabled"
|
|
line.byte 0x01 "WAIT_CFG,Wait States Configuration"
|
|
bitfld.byte 0x01 6.--7. " WR_WRK_WAIT ,Write work wait states" "1 state,2 states,3 states,0 states"
|
|
bitfld.byte 0x01 4.--5. " RD_WRK_WAIT ,Read work wait states" "1 state,2 states,3 states,0 states"
|
|
textline " "
|
|
bitfld.byte 0x01 2.--3. " WR_CFG_WAIT ,Write configuration wait states" "1 state,2 states,3 states,0 states"
|
|
bitfld.byte 0x01 0.--1. " RD_CFG_WAIT ,Read configuration wait states" "5 states,4 states,3 states,1 state"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "INT_CLK_CTL,Interrupt Synchronizer Clock Control"
|
|
bitfld.byte 0x00 0. " EN_HFCLK ,This bit enables the interrupt synchronizer in the UDB interface" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UDB (Universal Digital Block)"
|
|
base ad:0x400F8000
|
|
width 9.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "INT_CFG,UDB Subsystem Interrupt Configuration"
|
|
hexmask.long.byte 0x00 0.--7. 1. " INT_MODE_CFG ,Interrupt mode"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UDBSNG (Single UDB)"
|
|
tree "UDB P0 U0"
|
|
base ad:0x400F3000
|
|
width 22.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PLD_IT0,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT0T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT0T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT0T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT0T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT0T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT0T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT0T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT0T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT0T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT0T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT0T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT0T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT0T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT0T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT0T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT0T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT0C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT0C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT0C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT0C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT0C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT0C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT0C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT0C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT0C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT0C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT0C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT0C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT0C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT0C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT0C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT0C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PLD_IT1,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT1T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT1T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT1T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT1T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT1T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT1T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT1T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT1T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT1T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT1T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT1T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT1T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT1T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT1T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT1T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT1T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT1C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT1C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT1C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT1C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT1C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT1C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT1C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT1C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT1C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT1C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT1C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT1C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT1C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT1C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT1C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT1C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "PLD_IT2,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT2T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT2T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT2T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT2T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT2T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT2T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT2T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT2T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT2T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT2T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT2T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT2T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT2T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT2T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT2T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT2T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT2C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT2C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT2C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT2C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT2C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT2C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT2C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT2C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT2C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT2C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT2C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT2C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT2C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT2C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT2C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT2C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PLD_IT3,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT3T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT3T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT3T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT3T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT3T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT3T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT3T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT3T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT3T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT3T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT3T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT3T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT3T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT3T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT3T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT3T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT3C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT3C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT3C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT3C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT3C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT3C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT3C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT3C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT3C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT3C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT3C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT3C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT3C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT3C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT3C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT3C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PLD_IT4,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT4T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT4T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT4T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT4T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT4T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT4T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT4T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT4T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT4T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT4T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT4T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT4T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT4T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT4T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT4T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT4T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT4C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT4C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT4C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT4C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT4C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT4C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT4C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT4C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT4C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT4C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT4C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT4C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT4C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT4C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT4C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT4C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PLD_IT5,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT5T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT5T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT5T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT5T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT5T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT5T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT5T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT5T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT5T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT5T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT5T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT5T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT5T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT5T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT5T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT5T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT5C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT5C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT5C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT5C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT5C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT5C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT5C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT5C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT5C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT5C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT5C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT5C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT5C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT5C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT5C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT5C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PLD_IT6,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT6T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT6T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT6T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT6T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT6T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT6T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT6T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT6T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT6T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT6T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT6T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT6T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT6T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT6T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT6T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT6T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT6C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT6C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT6C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT6C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT6C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT6C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT6C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT6C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT6C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT6C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT6C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT6C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT6C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT6C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT6C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT6C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PLD_IT7,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT7T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT7T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT7T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT7T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT7T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT7T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT7T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT7T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT7T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT7T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT7T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT7T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT7T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT7T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT7T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT7T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT7C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT7C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT7C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT7C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT7C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT7C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT7C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT7C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT7C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT7C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT7C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT7C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT7C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT7C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT7C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT7C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PLD_IT8,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT8T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT8T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT8T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT8T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT8T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT8T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT8T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT8T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT8T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT8T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT8T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT8T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT8T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT8T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT8T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT8T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT8C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT8C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT8C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT8C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT8C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT8C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT8C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT8C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT8C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT8C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT8C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT8C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT8C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT8C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT8C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT8C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PLD_IT9,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT9T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT9T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT9T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT9T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT9T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT9T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT9T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT9T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT9T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT9T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT9T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT9T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT9T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT9T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT9T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT9T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT9C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT9C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT9C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT9C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT9C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT9C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT9C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT9C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT9C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT9C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT9C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT9C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT9C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT9C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT9C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT9C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PLD_IT10,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT10T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT10T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT10T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT10T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT10T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT10T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT10T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT10T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT10T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT10T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT10T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT10T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT10T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT10T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT10T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT10T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT10C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT10C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT10C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT10C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT10C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT10C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT10C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT10C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT10C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT10C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT10C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT10C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT10C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT10C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT10C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT10C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PLD_IT11,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT11T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT11T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT11T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT11T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT11T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT11T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT11T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT11T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT11T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT11T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT11T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT11T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT11T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT11T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT11T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT11T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT11C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT11C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT11C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT11C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT11C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT11C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT11C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT11C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT11C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT11C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT11C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT11C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT11C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT11C_2 ,PLD0 complement input term 2" "0,1"
|
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bitfld.long 0x00 1. " PLD0_IT11C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT11C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "PLD_ORT0,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT0_7 ,PLD1 OR term 7" "0,1"
|
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bitfld.word 0x00 14. " PLD1_ORT_PT0_6 ,PLD1 OR term 6" "0,1"
|
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bitfld.word 0x00 13. " PLD1_ORT_PT0_5 ,PLD1 OR term 5" "0,1"
|
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bitfld.word 0x00 12. " PLD1_ORT_PT0_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT0_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT0_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT0_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT0_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT0_7 ,PLD0 OR term 7" "0,1"
|
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bitfld.word 0x00 6. " PLD0_ORT_PT0_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT0_5 ,PLD0 OR term 5" "0,1"
|
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bitfld.word 0x00 4. " PLD0_ORT_PT0_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT0_3 ,PLD0 OR term 3" "0,1"
|
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bitfld.word 0x00 2. " PLD0_ORT_PT0_2 ,PLD0 OR term 2" "0,1"
|
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bitfld.word 0x00 1. " PLD0_ORT_PT0_1 ,PLD0 OR term 1" "0,1"
|
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bitfld.word 0x00 0. " PLD0_ORT_PT0_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x32++0x01
|
|
line.word 0x00 "PLD_ORT1,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT1_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT1_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT1_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT1_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT1_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT1_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT1_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT1_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT1_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT1_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT1_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT1_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT1_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT1_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT1_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT1_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "PLD_ORT2,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT2_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT2_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT2_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT2_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT2_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT2_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT2_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT2_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT2_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT2_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT2_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT2_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT2_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT2_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT2_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT2_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "PLD_ORT3,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT3_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT3_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT3_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT3_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT3_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT3_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT3_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT3_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT3_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT3_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT3_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT3_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT3_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT3_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT3_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT3_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x38++0x07
|
|
line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell Configuration For Carry Enable And Constant"
|
|
bitfld.word 0x00 15. " PLD1_MC3_DFF_C ,PLD1 MC3 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " PLD1_MC3_CEN ,PLD1 MC3 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " PLD1_MC2_DFF_C ,PLD1 MC2 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 12. " PLD1_MC2_CEN ,PLD1 MC2 carry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_MC1_DFF_C ,PLD1 MC1 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " PLD1_MC1_CEN ,PLD1 MC1 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " PLD1_MC0_DFF_C ,PLD1 MC0 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 8. " PLD1_MC0_CEN ,PLD1 MC0 carry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_MC3_DFF_C ,PLD0 MC3 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 6. " PLD0_MC3_CEN ,PLD0 MC3 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " PLD0_MC2_DFF_C ,PLD0 MC2 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 4. " PLD0_MC2_CEN ,PLD0 MC2 carry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_MC1_DFF_C ,PLD0 MC1 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 2. " PLD0_MC1_CEN ,PLD0 MC1 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " PLD0_MC0_DFF_C ,PLD0 MC0 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 0. " PLD0_MC0_CEN ,PLD0_MC0 carry enable" "Disabled,Enabled"
|
|
line.word 0x02 "PLD_MC_CFG_XORFB,PLD Macro Cell XOR Feedback"
|
|
bitfld.word 0x02 14.--15. " PLD1_MC3_XORFB ,PLD1 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 12.--13. " PLD1_MC2_XORFB ,PLD1 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 10.--11. " PLD1_MC1_XORFB ,PLD1 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 8.--9. " PLD1_MC0_XORFB ,PLD1 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
textline " "
|
|
bitfld.word 0x02 6.--7. " PLD0_MC3_XORFB ,PLD0 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 4.--5. " PLD0_MC2_XORFB ,PLD0 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 2.--3. " PLD0_MC1_XORFB ,PLD0 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 0.--1. " PLD0_MC0_XORFB ,PLD0 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
line.word 0x04 "PLD_MC_SET_RESET,PLD Macro Cell Set Reset Selection"
|
|
bitfld.word 0x04 15. " PLD1_MC3_RESET_SEL ,PLD1 MC3 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 14. " PLD1_MC3_SET_SEL ,PLD1 MC3 set select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 13. " PLD1_MC2_RESET_SEL ,PLD1 MC2 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 12. " PLD1_MC2_SET_SEL ,PLD1 MC2 set select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 11. " PLD1_MC1_RESET_SEL ,PLD1 MC1 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 10. " PLD1_MC1_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 9. " PLD1_MC0_RESET_SEL ,PLD1 MC0 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 8. " PLD1_MC0_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 7. " PLD0_MC3_RESET_SEL ,PLD0 MC3 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 6. " PLD0_MC3_SET_SEL ,PLD0 MC3 set select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 5. " PLD0_MC2_RESET_SEL ,PLD0 MC2 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 4. " PLD0_MC2_SET_SEL ,PLD0 MC2 set select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 3. " PLD0_MC1_RESET_SEL ,PLD0 MC1 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 2. " PLD0_MC1_SET_SEL ,PLD0 MC1 set select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 1. " PLD0_MC0_RESET_SEL ,Reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 0. " PLD0_MC0_SET_SEL ,PLD0 MC0 set select enable" "Disabled,Enabled"
|
|
line.word 0x06 "PLD_MC_CFG_BYPASS,PLD Macro Cell Bypass Control"
|
|
bitfld.word 0x06 15. " NC15 ,Spare register bit NC15" "0,1"
|
|
bitfld.word 0x06 14. " PLD1_MC3_BYPASS ,PLD1 MC3 bypass selection" "REGISTER,COMBINATIONAL"
|
|
bitfld.word 0x06 13. " NC13 ,Spare register bit NC13" "0,1"
|
|
bitfld.word 0x06 12. " PLD1_MC2_BYPASS ,PLD1 MC2 bypass selection" "REGISTER,COMBINATIONAL"
|
|
textline " "
|
|
bitfld.word 0x06 11. " NC11 ,Spare register bit NC11" "0,1"
|
|
bitfld.word 0x06 10. " PLD1_MC1_BYPASS ,PLD1 MC1 bypass selection" "REGISTER,COMBINATIONAL"
|
|
bitfld.word 0x06 9. " NC9 ,Spare register bit NC9" "0,1"
|
|
bitfld.word 0x06 8. " PLD1_MC0_BYPASS ,PLD1 MC0 bypass selection" "REGISTER,COMBINATIONAL"
|
|
textline " "
|
|
bitfld.word 0x06 7. " NC7 ,Spare register bit NC7" "0,1"
|
|
bitfld.word 0x06 6. " PLD0_MC3_BYPASS ,PLD0 MC3 bypass selection" "REGISTER,COMBINATIONAL"
|
|
bitfld.word 0x06 5. " NC5 ,Spare register bit NC5" "0,1"
|
|
bitfld.word 0x06 4. " PLD0_MC2_BYPASS ,PLD0 MC2 bypass selection" "REGISTER,COMBINATIONAL"
|
|
textline " "
|
|
bitfld.word 0x06 3. " NC3 ,Spare register bit NC3" "0,1"
|
|
bitfld.word 0x06 2. " PLD0_MC1_BYPASS ,PLD0 MC1 bypass selection" "REGISTER,COMBINATIONAL"
|
|
bitfld.word 0x06 1. " NC1 ,Spare register bit NC1" "0,1"
|
|
bitfld.word 0x06 0. " PLD0_MC0_BYPASS ,PLD0 MC0 bypass selection" "REGISTER,COMBINATIONAL"
|
|
group.byte 0x40++0x17
|
|
line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0. Address Bits 0 And 1 To The Dynamic Configuration RAM"
|
|
bitfld.byte 0x00 4.--6. " RAD1 ,Datapath permutable input mux RAD1" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
bitfld.byte 0x00 0.--2. " RAD0 ,Datapath permutable input mux RAD0" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
line.byte 0x01 "CFG1,Datapath Input Selection - RAD2. Address Bit 2 To The Dynamic Configuration RAM"
|
|
bitfld.byte 0x01 7. " DP_RTE_BYPASS4 ,Dp_in bypass control 4" "DP_IN4_ROUTE,DP_IN4_BYPASS"
|
|
bitfld.byte 0x01 6. " DP_RTE_BYPASS3 ,Dp_in bypass control 3" "DP_IN3_ROUTE,DP_IN3_BYPASS"
|
|
bitfld.byte 0x01 5. " DP_RTE_BYPASS2 ,Dp_in bypass control 2" "DP_IN2_ROUTE,DP_IN2_BYPASS"
|
|
bitfld.byte 0x01 4. " DP_RTE_BYPASS1 ,Dp_in bypass control 1" "DP_IN1_ROUTE,DP_IN1_BYPASS"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " DP_RTE_BYPASS0 ,Dp_in bypass control 0" "DP_IN0_ROUTE,DP_IN0_BYPASS"
|
|
bitfld.byte 0x01 0.--2. " RAD2 ,Datapath permutable input mux 2" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
line.byte 0x02 "CFG2,Datapath Input Selection - F1_LD, F0_LD"
|
|
bitfld.byte 0x02 7. " NC7 ,Spare register bit NC7" "0,1"
|
|
bitfld.byte 0x02 4.--6. " F1_LD ,Datapath permutable input mux F1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
bitfld.byte 0x02 3. " DP_RTE_BYPASS5 ,Dp_in bypass control 5" "DP_IN5_ROUTE,DP_IN5_BYPASS"
|
|
bitfld.byte 0x02 0.--2. " F0_LD ,Datapath permutable input mux F0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
line.byte 0x03 "CFG3,Datapath Input Selection - D1_LD, D0_LD"
|
|
bitfld.byte 0x03 4.--6. " D1_LD ,Datapath permutable input mux D1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
bitfld.byte 0x03 0.--2. " D0_LD ,Datapath permutable input mux D0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
line.byte 0x04 "CFG4,Datapath Input Selection - CI_MUX SI_MUX"
|
|
bitfld.byte 0x04 4.--6. " CI_MUX ,Datapath permutable input mux CI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
bitfld.byte 0x04 0.--2. " SI_MUX ,Datapath permutable input mux SI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
line.byte 0x05 "CFG5,Datapath Output Selection For OUT1 OUT0"
|
|
bitfld.byte 0x05 4.--7. " OUT1 ,Datapath permutable output mux OUT1" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
|
|
bitfld.byte 0x05 0.--3. " OUT0 ,Datapath permutable output mux OUT0" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
|
|
line.byte 0x06 "CFG6,Datapath Output Selection For OUT3 OUT2"
|
|
bitfld.byte 0x06 4.--7. " OUT3 ,Datapath permutable output mux OUT3" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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bitfld.byte 0x06 0.--3. " OUT2 ,Datapath permutable output mux OUT2" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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|
line.byte 0x07 "CFG7,Datapath Output Selection For OUT5 OUT4"
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|
bitfld.byte 0x07 4.--7. " OUT5 ,Datapath permutable output mux OUT5" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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|
bitfld.byte 0x07 0.--3. " OUT4 ,Datapath permutable output mux OUT4" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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|
line.byte 0x08 "CFG8,Datapath Output Synchronization Option"
|
|
bitfld.byte 0x08 7. " NC7 ,Spare register bit NC7" "0,1"
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|
bitfld.byte 0x08 6. " NC6 ,Spare register bit NC6" "0,1"
|
|
bitfld.byte 0x08 0.--5. " OUT_SYNC ,Datapath output synchronization" "REGISTERED,COMBINATIONAL,?..."
|
|
line.byte 0x09 "CFG9,Datapath ALU Mask"
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|
line.byte 0x0A "CFG10,Datapath Compare 0 Mask"
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|
line.byte 0x0B "CFG11,Datapath Compare 1 Mask"
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|
line.byte 0x0C "CFG12,Datapath Mask Enables And Shift In Configuration"
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|
bitfld.byte 0x0C 7. " CMASK1_EN ,Datapath mask CMASK1 enable" "Disabled,Enabled"
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|
bitfld.byte 0x0C 6. " CMASK0_EN ,Datapath mask CMASK0 enable" "Disabled,Enabled"
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|
bitfld.byte 0x0C 5. " AMASK_EN ,Datapath mask AMASK enable" "Disabled,Enabled"
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|
bitfld.byte 0x0C 4. " DEF_SI ,Datapath default shift value" "DEFAULT_0,DEFAULT_1"
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|
textline " "
|
|
bitfld.byte 0x0C 2.--3. " SI_SELB ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN"
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|
bitfld.byte 0x0C 0.--1. " SI_SELA ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN"
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|
line.byte 0x0D "CFG13,Datapath Carry In And Compare Configuration"
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bitfld.byte 0x0D 6.--7. " CMP_SELB ,Datapath compare select B" "A1_D1,A1_A0,A0_D1,A0_A0"
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bitfld.byte 0x0D 4.--5. " CMP_SELA ,Datapath compare select A" "A1_D1,A1_A0,A0_D1,A0_A0"
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bitfld.byte 0x0D 2.--3. " CI_SELB ,Datapath carry in source select B" "DEFAULT,REGISTERED,ROUTE,CHAIN"
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bitfld.byte 0x0D 0.--1. " CI_SELA ,Datapath carry in source select A" "DEFAULT,REGISTERED,ROUTE,CHAIN"
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line.byte 0x0E "CFG14,Datapath Chaining And MSB Configuration"
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bitfld.byte 0x0E 7. " MSB_EN ,Datapath MSB selection enable" "Disabled,Enabled"
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|
bitfld.byte 0x0E 4.--6. " MSB_SEL ,Datapath MSB selection" "BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7"
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bitfld.byte 0x0E 3. " CHAIN_CMSB ,Datapath CRC MSB chaining enable" "Disabled,Enabled"
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bitfld.byte 0x0E 2. " CHAIN_FB ,Datapath CRC feedback chaining enable" "Disabled,Enabled"
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|
textline " "
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|
bitfld.byte 0x0E 1. " CHAIN1 ,Datapath condition chaining enable 1" "Disabled,Enabled"
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bitfld.byte 0x0E 0. " CHAIN0 ,Datapath condition chaining enable 0" "Disabled,Enabled"
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line.byte 0x0F "CFG15,Datapath FIFO, Shift And Parallel Input Control"
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bitfld.byte 0x0F 7. " PI_SEL ,Datapath parallel input selection" "NORMAL,PARALLEL"
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bitfld.byte 0x0F 6. " SHIFT_SEL ,Datapath shift out selection" "SOL_MSB,SOR"
|
|
bitfld.byte 0x0F 5. " PI_DYN ,Enable for dynamic control of parallel data input (Pi) mux" "Disabled,Enabled"
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bitfld.byte 0x0F 4. " MSB_SI ,Arithmetic shift right operation shift in selection" "DEFAULT,MSB"
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textline " "
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bitfld.byte 0x0F 2.--3. " F1_INSEL ,Datapath FIFO configuration 1" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU"
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bitfld.byte 0x0F 0.--1. " F0_INSEL ,Datapath FIFO configuration 0" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU"
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line.byte 0x10 "CFG16,Datapath FIFO And Register Access Configuration Control"
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bitfld.byte 0x10 7. " F1_CK_INV ,FIFO 1 clock Inverted" "NORMAL,Inverted"
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bitfld.byte 0x10 6. " F0_CK_INV ,FIFO 0 clock Inverted" "NORMAL,Inverted"
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bitfld.byte 0x10 5. " FIFO_FAST ,FIFO fast mode" "Disabled,Enabled"
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bitfld.byte 0x10 4. " FIFO_CAP ,FIFO software capture mode" "Disabled,Enabled"
|
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textline " "
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bitfld.byte 0x10 3. " FIFO_EDGE ,Edge/level sensitive FIFO write control (Fx_ld)" "LEVEL,EDGE"
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bitfld.byte 0x10 2. " FIFO_ASYNC ,Asynchronous FIFO clocking support" "Disabled,Enabled"
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bitfld.byte 0x10 1. " EXT_CRCPRS ,External CRC/PRS mode" "INTERNAL,EXTERNAL"
|
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bitfld.byte 0x10 0. " WRK16_CONCAT ,Datapath register access mode" "DEFAULT,CONCATENATE"
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line.byte 0x11 "CFG17,Datapath FIFO Control"
|
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bitfld.byte 0x11 4. " FIFO_ADD_SYNC ,Sync flip-flop to FIFO block status" "Disabled,Enabled"
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bitfld.byte 0x11 3. " NC3 ,Spare register bit NC3" "0,1"
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bitfld.byte 0x11 2. " NC2 ,Spare register bit NC2" "0,1"
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bitfld.byte 0x11 1. " F1_DYN ,FIFO 1 direction" "STATIC,DYNAMIC"
|
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textline " "
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bitfld.byte 0x11 0. " F0_DYN ,FIFO 0 direction" "STATIC,DYNAMIC"
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line.byte 0x12 "CFG18,Control Register Mode 0"
|
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line.byte 0x13 "CFG19,Control Register Mode 1"
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line.byte 0x14 "CFG20,Status Register Input Mode Selection"
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bitfld.byte 0x14 7. " STAT_MD[7] ,Bit 7 status input mode select" "Transparent,Sticky cleared"
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bitfld.byte 0x14 6. " [6] ,Bit 6 status input mode select" "Transparent,Sticky cleared"
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bitfld.byte 0x14 5. " [5] ,Bit 5 status input mode select" "Transparent,Sticky cleared"
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bitfld.byte 0x14 4. " [4] ,Bit 4 status input mode select" "Transparent,Sticky cleared"
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textline " "
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bitfld.byte 0x14 3. " [3] ,Bit 3 status input mode select" "Transparent,Sticky cleared"
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bitfld.byte 0x14 2. " [2] ,Bit 2 status input mode select" "Transparent,Sticky cleared"
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bitfld.byte 0x14 1. " [1] ,Bit 1 status input mode select" "Transparent,Sticky cleared"
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bitfld.byte 0x14 0. " [0] ,Bit 0 status input mode select" "Transparent,Sticky cleared"
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line.byte 0x15 "CFG21,Spare Register Bits"
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bitfld.byte 0x15 1. " NC1 ,Spare register bit NC1" "0,1"
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bitfld.byte 0x15 0. " NC0 ,Spare register bit NC0" "0,1"
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line.byte 0x16 "CFG22,SC Block Configuration Control"
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bitfld.byte 0x16 4. " SC_EXT_RES ,Control register external reset operation" "Disabled,Enabled"
|
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bitfld.byte 0x16 3. " SC_SYNC_MD ,SC sync mode" "NORMAL,SYNC_MODE"
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bitfld.byte 0x16 2. " SC_INT_MD ,SC interrupt mode" "NORMAL,INT_MODE"
|
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bitfld.byte 0x16 0.--1. " SC_OUT_CTL ,Output source for the status and control routing connections" "CONTROL,PARALLEL,COUNTER,?..."
|
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line.byte 0x17 "CFG23,Counter Control"
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bitfld.byte 0x17 6. " ALT_CNT ,Alternate operating mode of the counter" "DEFAULT_MODE,ALT_MODE"
|
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bitfld.byte 0x17 5. " ROUTE_EN ,Counter enable signal for routing input" "Disabled,Enabled"
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bitfld.byte 0x17 4. " ROUTE_LD ,Counter load signal for routing input" "Disabled,Enabled"
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bitfld.byte 0x17 2.--3. " CNT_EN_SEL ,Routing inputs for the counter enable signal" "SC_IN4,SC_IN5,SC_IN6,SC_IO"
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textline " "
|
|
bitfld.byte 0x17 0.--1. " CNT_LD_SEL ,Routing inputs for the counter load signal" "SC_IN0,SC_IN1,SC_IN2,SC_IN3"
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if (((per.b(ad:0x400F3000+0x5F))&0x01)==0x01)
|
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group.byte 0x58++0x03
|
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line.byte 0x00 "CFG24,PLD0 Clock And Reset Control"
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bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
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bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
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bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
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|
textline " "
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bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
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bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
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line.byte 0x01 "CFG25,PLD1 Clock And Reset Control"
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bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
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bitfld.byte 0x01 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
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bitfld.byte 0x01 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
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textline " "
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bitfld.byte 0x01 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
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bitfld.byte 0x01 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
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line.byte 0x02 "CFG26,Datapath Clock And Reset Control"
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bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
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bitfld.byte 0x02 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
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bitfld.byte 0x02 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
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textline " "
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bitfld.byte 0x02 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
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bitfld.byte 0x02 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
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line.byte 0x03 "CFG27,Status/control Clock And Reset Control"
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bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
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bitfld.byte 0x03 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
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bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
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textline " "
|
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bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
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bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
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else
|
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group.byte 0x58++0x03
|
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line.byte 0x00 "CFG24,PLD0 Clock And Reset Control"
|
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bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
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bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
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bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
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bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
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bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
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line.byte 0x01 "CFG25,PLD1 Clock And Reset Control"
|
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bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
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bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
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line.byte 0x02 "CFG26,Datapath Clock And Reset Control"
|
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bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
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bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
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line.byte 0x03 "CFG27,Status/control Clock And Reset Control"
|
|
rbitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
endif
|
|
group.byte 0x5C++0x01
|
|
line.byte 0x00 "CFG28,Clock Selection For PLD1 And PLD0"
|
|
bitfld.byte 0x00 4.--7. " PLD1_CK_SEL ,PLD1 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
bitfld.byte 0x00 0.--3. " PLD0_CK_SEL ,PLD0 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
line.byte 0x01 "CFG29,Clock Selection For Datapath, Status And Control"
|
|
bitfld.byte 0x01 4.--7. " SC_CK_SEL ,SC clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
bitfld.byte 0x01 0.--3. " DP_CK_SEL ,DP clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
if (((per.b(ad:0x400F3000+0x5F))&0x01)==0x01)
|
|
group.byte 0x5E++0x01
|
|
line.byte 0x00 "CFG30,Reset Control"
|
|
bitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED"
|
|
rbitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x01 "CFG31,Reset Control"
|
|
bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
bitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED"
|
|
bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE"
|
|
else
|
|
group.byte 0x5E++0x01
|
|
line.byte 0x00 "CFG30,Reset Control"
|
|
rbitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted"
|
|
rbitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED"
|
|
bitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x01 "CFG31,Reset Control"
|
|
bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
rbitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED"
|
|
bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE"
|
|
endif
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DCFG0,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x62++0x01
|
|
line.word 0x00 "DCFG1,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "DCFG2,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x66++0x01
|
|
line.word 0x00 "DCFG3,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "DCFG4,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x6A++0x01
|
|
line.word 0x00 "DCFG5,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "DCFG6,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x6E++0x01
|
|
line.word 0x00 "DCFG7,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UDB P0 U1"
|
|
base ad:0x400F3080
|
|
width 22.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PLD_IT0,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT0T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT0T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT0T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT0T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT0T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT0T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT0T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT0T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT0T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT0T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT0T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT0T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT0T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT0T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT0T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT0T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT0C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT0C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT0C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT0C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT0C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT0C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT0C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT0C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT0C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT0C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT0C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT0C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT0C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT0C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT0C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT0C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PLD_IT1,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT1T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT1T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT1T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT1T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT1T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT1T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT1T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT1T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT1T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT1T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT1T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT1T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT1T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT1T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT1T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT1T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT1C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT1C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT1C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT1C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT1C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT1C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT1C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT1C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT1C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT1C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT1C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT1C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT1C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT1C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT1C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT1C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "PLD_IT2,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT2T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT2T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT2T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT2T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT2T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT2T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT2T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT2T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT2T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT2T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT2T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT2T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT2T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT2T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT2T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT2T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT2C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT2C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT2C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT2C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT2C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT2C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT2C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT2C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT2C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT2C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT2C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT2C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT2C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT2C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT2C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT2C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PLD_IT3,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT3T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT3T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT3T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT3T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT3T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT3T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT3T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT3T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT3T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT3T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT3T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT3T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT3T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT3T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT3T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT3T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT3C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT3C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT3C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT3C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT3C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT3C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT3C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT3C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT3C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT3C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT3C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT3C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT3C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT3C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT3C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT3C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PLD_IT4,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT4T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT4T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT4T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT4T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT4T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT4T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT4T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT4T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT4T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT4T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT4T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT4T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT4T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT4T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT4T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT4T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT4C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT4C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT4C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT4C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT4C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT4C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT4C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT4C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT4C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT4C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT4C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT4C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT4C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT4C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT4C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT4C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PLD_IT5,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT5T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT5T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT5T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT5T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT5T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT5T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT5T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT5T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT5T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT5T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT5T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT5T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT5T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT5T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT5T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT5T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT5C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT5C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT5C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT5C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT5C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT5C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT5C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT5C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT5C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT5C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT5C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT5C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT5C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT5C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT5C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT5C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PLD_IT6,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT6T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT6T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT6T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT6T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT6T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT6T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT6T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT6T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT6T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT6T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT6T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT6T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT6T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT6T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT6T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT6T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT6C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT6C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT6C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT6C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT6C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT6C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT6C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT6C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT6C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT6C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT6C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT6C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT6C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT6C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT6C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT6C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PLD_IT7,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT7T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT7T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT7T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT7T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT7T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT7T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT7T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT7T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT7T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT7T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT7T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT7T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT7T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT7T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT7T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT7T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT7C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT7C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT7C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT7C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT7C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT7C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT7C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT7C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT7C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT7C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT7C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT7C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT7C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT7C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT7C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT7C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PLD_IT8,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT8T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT8T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT8T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT8T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT8T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT8T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT8T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT8T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT8T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT8T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT8T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT8T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT8T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT8T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT8T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT8T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT8C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT8C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT8C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT8C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT8C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT8C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT8C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT8C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT8C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT8C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT8C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT8C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT8C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT8C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT8C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT8C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PLD_IT9,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT9T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT9T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT9T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT9T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT9T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT9T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT9T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT9T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT9T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT9T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT9T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT9T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT9T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT9T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT9T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT9T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT9C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT9C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT9C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT9C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT9C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT9C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT9C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT9C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT9C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT9C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT9C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT9C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT9C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT9C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT9C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT9C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PLD_IT10,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT10T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT10T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT10T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT10T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT10T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT10T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT10T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT10T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT10T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT10T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT10T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT10T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT10T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT10T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT10T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT10T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT10C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT10C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT10C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT10C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT10C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT10C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT10C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT10C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT10C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT10C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT10C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT10C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT10C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT10C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT10C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT10C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PLD_IT11,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT11T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT11T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT11T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT11T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT11T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT11T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT11T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT11T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT11T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT11T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT11T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT11T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT11T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT11T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT11T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT11T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT11C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT11C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT11C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT11C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT11C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT11C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT11C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT11C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT11C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT11C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT11C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT11C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT11C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT11C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT11C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT11C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "PLD_ORT0,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT0_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT0_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT0_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT0_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT0_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT0_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT0_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT0_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT0_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT0_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT0_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT0_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT0_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT0_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT0_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT0_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x32++0x01
|
|
line.word 0x00 "PLD_ORT1,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT1_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT1_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT1_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT1_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT1_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT1_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT1_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT1_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT1_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT1_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT1_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT1_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT1_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT1_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT1_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT1_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "PLD_ORT2,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT2_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT2_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT2_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT2_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT2_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT2_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT2_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT2_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT2_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT2_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT2_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT2_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT2_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT2_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT2_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT2_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "PLD_ORT3,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT3_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT3_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT3_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT3_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT3_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT3_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT3_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT3_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT3_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT3_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT3_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT3_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT3_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT3_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT3_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT3_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x38++0x07
|
|
line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell Configuration For Carry Enable And Constant"
|
|
bitfld.word 0x00 15. " PLD1_MC3_DFF_C ,PLD1 MC3 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " PLD1_MC3_CEN ,PLD1 MC3 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " PLD1_MC2_DFF_C ,PLD1 MC2 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 12. " PLD1_MC2_CEN ,PLD1 MC2 carry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_MC1_DFF_C ,PLD1 MC1 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " PLD1_MC1_CEN ,PLD1 MC1 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " PLD1_MC0_DFF_C ,PLD1 MC0 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 8. " PLD1_MC0_CEN ,PLD1 MC0 carry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_MC3_DFF_C ,PLD0 MC3 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 6. " PLD0_MC3_CEN ,PLD0 MC3 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " PLD0_MC2_DFF_C ,PLD0 MC2 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 4. " PLD0_MC2_CEN ,PLD0 MC2 carry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_MC1_DFF_C ,PLD0 MC1 DFF constant" "Not inverted,Inverted"
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bitfld.word 0x00 2. " PLD0_MC1_CEN ,PLD0 MC1 carry enable" "Disabled,Enabled"
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bitfld.word 0x00 1. " PLD0_MC0_DFF_C ,PLD0 MC0 DFF constant" "Not inverted,Inverted"
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bitfld.word 0x00 0. " PLD0_MC0_CEN ,PLD0_MC0 carry enable" "Disabled,Enabled"
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line.word 0x02 "PLD_MC_CFG_XORFB,PLD Macro Cell XOR Feedback"
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bitfld.word 0x02 14.--15. " PLD1_MC3_XORFB ,PLD1 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
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bitfld.word 0x02 12.--13. " PLD1_MC2_XORFB ,PLD1 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
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bitfld.word 0x02 10.--11. " PLD1_MC1_XORFB ,PLD1 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
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bitfld.word 0x02 8.--9. " PLD1_MC0_XORFB ,PLD1 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
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textline " "
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bitfld.word 0x02 6.--7. " PLD0_MC3_XORFB ,PLD0 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
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bitfld.word 0x02 4.--5. " PLD0_MC2_XORFB ,PLD0 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
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bitfld.word 0x02 2.--3. " PLD0_MC1_XORFB ,PLD0 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
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bitfld.word 0x02 0.--1. " PLD0_MC0_XORFB ,PLD0 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
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line.word 0x04 "PLD_MC_SET_RESET,PLD Macro Cell Set Reset Selection"
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bitfld.word 0x04 15. " PLD1_MC3_RESET_SEL ,PLD1 MC3 reset select enable" "Disabled,Enabled"
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bitfld.word 0x04 14. " PLD1_MC3_SET_SEL ,PLD1 MC3 set select enable" "Disabled,Enabled"
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bitfld.word 0x04 13. " PLD1_MC2_RESET_SEL ,PLD1 MC2 reset select enable" "Disabled,Enabled"
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bitfld.word 0x04 12. " PLD1_MC2_SET_SEL ,PLD1 MC2 set select enable" "Disabled,Enabled"
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textline " "
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bitfld.word 0x04 11. " PLD1_MC1_RESET_SEL ,PLD1 MC1 reset select enable" "Disabled,Enabled"
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bitfld.word 0x04 10. " PLD1_MC1_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled"
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bitfld.word 0x04 9. " PLD1_MC0_RESET_SEL ,PLD1 MC0 reset select enable" "Disabled,Enabled"
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bitfld.word 0x04 8. " PLD1_MC0_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled"
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textline " "
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bitfld.word 0x04 7. " PLD0_MC3_RESET_SEL ,PLD0 MC3 reset select enable" "Disabled,Enabled"
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bitfld.word 0x04 6. " PLD0_MC3_SET_SEL ,PLD0 MC3 set select enable" "Disabled,Enabled"
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bitfld.word 0x04 5. " PLD0_MC2_RESET_SEL ,PLD0 MC2 reset select enable" "Disabled,Enabled"
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bitfld.word 0x04 4. " PLD0_MC2_SET_SEL ,PLD0 MC2 set select enable" "Disabled,Enabled"
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textline " "
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bitfld.word 0x04 3. " PLD0_MC1_RESET_SEL ,PLD0 MC1 reset select enable" "Disabled,Enabled"
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bitfld.word 0x04 2. " PLD0_MC1_SET_SEL ,PLD0 MC1 set select enable" "Disabled,Enabled"
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bitfld.word 0x04 1. " PLD0_MC0_RESET_SEL ,Reset select enable" "Disabled,Enabled"
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bitfld.word 0x04 0. " PLD0_MC0_SET_SEL ,PLD0 MC0 set select enable" "Disabled,Enabled"
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line.word 0x06 "PLD_MC_CFG_BYPASS,PLD Macro Cell Bypass Control"
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bitfld.word 0x06 15. " NC15 ,Spare register bit NC15" "0,1"
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bitfld.word 0x06 14. " PLD1_MC3_BYPASS ,PLD1 MC3 bypass selection" "REGISTER,COMBINATIONAL"
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bitfld.word 0x06 13. " NC13 ,Spare register bit NC13" "0,1"
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bitfld.word 0x06 12. " PLD1_MC2_BYPASS ,PLD1 MC2 bypass selection" "REGISTER,COMBINATIONAL"
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textline " "
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bitfld.word 0x06 11. " NC11 ,Spare register bit NC11" "0,1"
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bitfld.word 0x06 10. " PLD1_MC1_BYPASS ,PLD1 MC1 bypass selection" "REGISTER,COMBINATIONAL"
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bitfld.word 0x06 9. " NC9 ,Spare register bit NC9" "0,1"
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bitfld.word 0x06 8. " PLD1_MC0_BYPASS ,PLD1 MC0 bypass selection" "REGISTER,COMBINATIONAL"
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textline " "
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bitfld.word 0x06 7. " NC7 ,Spare register bit NC7" "0,1"
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bitfld.word 0x06 6. " PLD0_MC3_BYPASS ,PLD0 MC3 bypass selection" "REGISTER,COMBINATIONAL"
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bitfld.word 0x06 5. " NC5 ,Spare register bit NC5" "0,1"
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bitfld.word 0x06 4. " PLD0_MC2_BYPASS ,PLD0 MC2 bypass selection" "REGISTER,COMBINATIONAL"
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textline " "
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bitfld.word 0x06 3. " NC3 ,Spare register bit NC3" "0,1"
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bitfld.word 0x06 2. " PLD0_MC1_BYPASS ,PLD0 MC1 bypass selection" "REGISTER,COMBINATIONAL"
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bitfld.word 0x06 1. " NC1 ,Spare register bit NC1" "0,1"
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bitfld.word 0x06 0. " PLD0_MC0_BYPASS ,PLD0 MC0 bypass selection" "REGISTER,COMBINATIONAL"
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group.byte 0x40++0x17
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line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0. Address Bits 0 And 1 To The Dynamic Configuration RAM"
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bitfld.byte 0x00 4.--6. " RAD1 ,Datapath permutable input mux RAD1" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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bitfld.byte 0x00 0.--2. " RAD0 ,Datapath permutable input mux RAD0" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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line.byte 0x01 "CFG1,Datapath Input Selection - RAD2. Address Bit 2 To The Dynamic Configuration RAM"
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bitfld.byte 0x01 7. " DP_RTE_BYPASS4 ,Dp_in bypass control 4" "DP_IN4_ROUTE,DP_IN4_BYPASS"
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bitfld.byte 0x01 6. " DP_RTE_BYPASS3 ,Dp_in bypass control 3" "DP_IN3_ROUTE,DP_IN3_BYPASS"
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bitfld.byte 0x01 5. " DP_RTE_BYPASS2 ,Dp_in bypass control 2" "DP_IN2_ROUTE,DP_IN2_BYPASS"
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bitfld.byte 0x01 4. " DP_RTE_BYPASS1 ,Dp_in bypass control 1" "DP_IN1_ROUTE,DP_IN1_BYPASS"
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textline " "
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bitfld.byte 0x01 3. " DP_RTE_BYPASS0 ,Dp_in bypass control 0" "DP_IN0_ROUTE,DP_IN0_BYPASS"
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bitfld.byte 0x01 0.--2. " RAD2 ,Datapath permutable input mux 2" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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line.byte 0x02 "CFG2,Datapath Input Selection - F1_LD, F0_LD"
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bitfld.byte 0x02 7. " NC7 ,Spare register bit NC7" "0,1"
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bitfld.byte 0x02 4.--6. " F1_LD ,Datapath permutable input mux F1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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bitfld.byte 0x02 3. " DP_RTE_BYPASS5 ,Dp_in bypass control 5" "DP_IN5_ROUTE,DP_IN5_BYPASS"
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bitfld.byte 0x02 0.--2. " F0_LD ,Datapath permutable input mux F0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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line.byte 0x03 "CFG3,Datapath Input Selection - D1_LD, D0_LD"
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bitfld.byte 0x03 4.--6. " D1_LD ,Datapath permutable input mux D1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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bitfld.byte 0x03 0.--2. " D0_LD ,Datapath permutable input mux D0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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line.byte 0x04 "CFG4,Datapath Input Selection - CI_MUX SI_MUX"
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bitfld.byte 0x04 4.--6. " CI_MUX ,Datapath permutable input mux CI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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bitfld.byte 0x04 0.--2. " SI_MUX ,Datapath permutable input mux SI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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line.byte 0x05 "CFG5,Datapath Output Selection For OUT1 OUT0"
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bitfld.byte 0x05 4.--7. " OUT1 ,Datapath permutable output mux OUT1" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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bitfld.byte 0x05 0.--3. " OUT0 ,Datapath permutable output mux OUT0" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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line.byte 0x06 "CFG6,Datapath Output Selection For OUT3 OUT2"
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bitfld.byte 0x06 4.--7. " OUT3 ,Datapath permutable output mux OUT3" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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bitfld.byte 0x06 0.--3. " OUT2 ,Datapath permutable output mux OUT2" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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line.byte 0x07 "CFG7,Datapath Output Selection For OUT5 OUT4"
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bitfld.byte 0x07 4.--7. " OUT5 ,Datapath permutable output mux OUT5" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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bitfld.byte 0x07 0.--3. " OUT4 ,Datapath permutable output mux OUT4" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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line.byte 0x08 "CFG8,Datapath Output Synchronization Option"
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bitfld.byte 0x08 7. " NC7 ,Spare register bit NC7" "0,1"
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bitfld.byte 0x08 6. " NC6 ,Spare register bit NC6" "0,1"
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bitfld.byte 0x08 0.--5. " OUT_SYNC ,Datapath output synchronization" "REGISTERED,COMBINATIONAL,?..."
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line.byte 0x09 "CFG9,Datapath ALU Mask"
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line.byte 0x0A "CFG10,Datapath Compare 0 Mask"
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line.byte 0x0B "CFG11,Datapath Compare 1 Mask"
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line.byte 0x0C "CFG12,Datapath Mask Enables And Shift In Configuration"
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bitfld.byte 0x0C 7. " CMASK1_EN ,Datapath mask CMASK1 enable" "Disabled,Enabled"
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bitfld.byte 0x0C 6. " CMASK0_EN ,Datapath mask CMASK0 enable" "Disabled,Enabled"
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bitfld.byte 0x0C 5. " AMASK_EN ,Datapath mask AMASK enable" "Disabled,Enabled"
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bitfld.byte 0x0C 4. " DEF_SI ,Datapath default shift value" "DEFAULT_0,DEFAULT_1"
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textline " "
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bitfld.byte 0x0C 2.--3. " SI_SELB ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN"
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bitfld.byte 0x0C 0.--1. " SI_SELA ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN"
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line.byte 0x0D "CFG13,Datapath Carry In And Compare Configuration"
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bitfld.byte 0x0D 6.--7. " CMP_SELB ,Datapath compare select B" "A1_D1,A1_A0,A0_D1,A0_A0"
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bitfld.byte 0x0D 4.--5. " CMP_SELA ,Datapath compare select A" "A1_D1,A1_A0,A0_D1,A0_A0"
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bitfld.byte 0x0D 2.--3. " CI_SELB ,Datapath carry in source select B" "DEFAULT,REGISTERED,ROUTE,CHAIN"
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bitfld.byte 0x0D 0.--1. " CI_SELA ,Datapath carry in source select A" "DEFAULT,REGISTERED,ROUTE,CHAIN"
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line.byte 0x0E "CFG14,Datapath Chaining And MSB Configuration"
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bitfld.byte 0x0E 7. " MSB_EN ,Datapath MSB selection enable" "Disabled,Enabled"
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bitfld.byte 0x0E 4.--6. " MSB_SEL ,Datapath MSB selection" "BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7"
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bitfld.byte 0x0E 3. " CHAIN_CMSB ,Datapath CRC MSB chaining enable" "Disabled,Enabled"
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bitfld.byte 0x0E 2. " CHAIN_FB ,Datapath CRC feedback chaining enable" "Disabled,Enabled"
|
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textline " "
|
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bitfld.byte 0x0E 1. " CHAIN1 ,Datapath condition chaining enable 1" "Disabled,Enabled"
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bitfld.byte 0x0E 0. " CHAIN0 ,Datapath condition chaining enable 0" "Disabled,Enabled"
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line.byte 0x0F "CFG15,Datapath FIFO, Shift And Parallel Input Control"
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bitfld.byte 0x0F 7. " PI_SEL ,Datapath parallel input selection" "NORMAL,PARALLEL"
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bitfld.byte 0x0F 6. " SHIFT_SEL ,Datapath shift out selection" "SOL_MSB,SOR"
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bitfld.byte 0x0F 5. " PI_DYN ,Enable for dynamic control of parallel data input (Pi) mux" "Disabled,Enabled"
|
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bitfld.byte 0x0F 4. " MSB_SI ,Arithmetic shift right operation shift in selection" "DEFAULT,MSB"
|
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textline " "
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bitfld.byte 0x0F 2.--3. " F1_INSEL ,Datapath FIFO configuration 1" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU"
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bitfld.byte 0x0F 0.--1. " F0_INSEL ,Datapath FIFO configuration 0" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU"
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line.byte 0x10 "CFG16,Datapath FIFO And Register Access Configuration Control"
|
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bitfld.byte 0x10 7. " F1_CK_INV ,FIFO 1 clock Inverted" "NORMAL,Inverted"
|
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bitfld.byte 0x10 6. " F0_CK_INV ,FIFO 0 clock Inverted" "NORMAL,Inverted"
|
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bitfld.byte 0x10 5. " FIFO_FAST ,FIFO fast mode" "Disabled,Enabled"
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bitfld.byte 0x10 4. " FIFO_CAP ,FIFO software capture mode" "Disabled,Enabled"
|
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textline " "
|
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bitfld.byte 0x10 3. " FIFO_EDGE ,Edge/level sensitive FIFO write control (Fx_ld)" "LEVEL,EDGE"
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bitfld.byte 0x10 2. " FIFO_ASYNC ,Asynchronous FIFO clocking support" "Disabled,Enabled"
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bitfld.byte 0x10 1. " EXT_CRCPRS ,External CRC/PRS mode" "INTERNAL,EXTERNAL"
|
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bitfld.byte 0x10 0. " WRK16_CONCAT ,Datapath register access mode" "DEFAULT,CONCATENATE"
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line.byte 0x11 "CFG17,Datapath FIFO Control"
|
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bitfld.byte 0x11 4. " FIFO_ADD_SYNC ,Sync flip-flop to FIFO block status" "Disabled,Enabled"
|
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bitfld.byte 0x11 3. " NC3 ,Spare register bit NC3" "0,1"
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bitfld.byte 0x11 2. " NC2 ,Spare register bit NC2" "0,1"
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bitfld.byte 0x11 1. " F1_DYN ,FIFO 1 direction" "STATIC,DYNAMIC"
|
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textline " "
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bitfld.byte 0x11 0. " F0_DYN ,FIFO 0 direction" "STATIC,DYNAMIC"
|
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line.byte 0x12 "CFG18,Control Register Mode 0"
|
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line.byte 0x13 "CFG19,Control Register Mode 1"
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line.byte 0x14 "CFG20,Status Register Input Mode Selection"
|
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bitfld.byte 0x14 7. " STAT_MD[7] ,Bit 7 status input mode select" "Transparent,Sticky cleared"
|
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bitfld.byte 0x14 6. " [6] ,Bit 6 status input mode select" "Transparent,Sticky cleared"
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bitfld.byte 0x14 5. " [5] ,Bit 5 status input mode select" "Transparent,Sticky cleared"
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bitfld.byte 0x14 4. " [4] ,Bit 4 status input mode select" "Transparent,Sticky cleared"
|
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textline " "
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bitfld.byte 0x14 3. " [3] ,Bit 3 status input mode select" "Transparent,Sticky cleared"
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bitfld.byte 0x14 2. " [2] ,Bit 2 status input mode select" "Transparent,Sticky cleared"
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bitfld.byte 0x14 1. " [1] ,Bit 1 status input mode select" "Transparent,Sticky cleared"
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bitfld.byte 0x14 0. " [0] ,Bit 0 status input mode select" "Transparent,Sticky cleared"
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line.byte 0x15 "CFG21,Spare Register Bits"
|
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bitfld.byte 0x15 1. " NC1 ,Spare register bit NC1" "0,1"
|
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bitfld.byte 0x15 0. " NC0 ,Spare register bit NC0" "0,1"
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line.byte 0x16 "CFG22,SC Block Configuration Control"
|
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bitfld.byte 0x16 4. " SC_EXT_RES ,Control register external reset operation" "Disabled,Enabled"
|
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bitfld.byte 0x16 3. " SC_SYNC_MD ,SC sync mode" "NORMAL,SYNC_MODE"
|
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bitfld.byte 0x16 2. " SC_INT_MD ,SC interrupt mode" "NORMAL,INT_MODE"
|
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bitfld.byte 0x16 0.--1. " SC_OUT_CTL ,Output source for the status and control routing connections" "CONTROL,PARALLEL,COUNTER,?..."
|
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line.byte 0x17 "CFG23,Counter Control"
|
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bitfld.byte 0x17 6. " ALT_CNT ,Alternate operating mode of the counter" "DEFAULT_MODE,ALT_MODE"
|
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bitfld.byte 0x17 5. " ROUTE_EN ,Counter enable signal for routing input" "Disabled,Enabled"
|
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bitfld.byte 0x17 4. " ROUTE_LD ,Counter load signal for routing input" "Disabled,Enabled"
|
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bitfld.byte 0x17 2.--3. " CNT_EN_SEL ,Routing inputs for the counter enable signal" "SC_IN4,SC_IN5,SC_IN6,SC_IO"
|
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textline " "
|
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bitfld.byte 0x17 0.--1. " CNT_LD_SEL ,Routing inputs for the counter load signal" "SC_IN0,SC_IN1,SC_IN2,SC_IN3"
|
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if (((per.b(ad:0x400F3080+0x5F))&0x01)==0x01)
|
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group.byte 0x58++0x03
|
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line.byte 0x00 "CFG24,PLD0 Clock And Reset Control"
|
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bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
|
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bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
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bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
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bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
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bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
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line.byte 0x01 "CFG25,PLD1 Clock And Reset Control"
|
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bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
|
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bitfld.byte 0x01 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
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bitfld.byte 0x01 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
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bitfld.byte 0x01 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
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bitfld.byte 0x01 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
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line.byte 0x02 "CFG26,Datapath Clock And Reset Control"
|
|
bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
|
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bitfld.byte 0x02 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
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bitfld.byte 0x02 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x02 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
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bitfld.byte 0x02 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x03 "CFG27,Status/control Clock And Reset Control"
|
|
bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
|
|
bitfld.byte 0x03 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
else
|
|
group.byte 0x58++0x03
|
|
line.byte 0x00 "CFG24,PLD0 Clock And Reset Control"
|
|
bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x01 "CFG25,PLD1 Clock And Reset Control"
|
|
bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x02 "CFG26,Datapath Clock And Reset Control"
|
|
bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x03 "CFG27,Status/control Clock And Reset Control"
|
|
rbitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
endif
|
|
group.byte 0x5C++0x01
|
|
line.byte 0x00 "CFG28,Clock Selection For PLD1 And PLD0"
|
|
bitfld.byte 0x00 4.--7. " PLD1_CK_SEL ,PLD1 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
bitfld.byte 0x00 0.--3. " PLD0_CK_SEL ,PLD0 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
line.byte 0x01 "CFG29,Clock Selection For Datapath, Status And Control"
|
|
bitfld.byte 0x01 4.--7. " SC_CK_SEL ,SC clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
bitfld.byte 0x01 0.--3. " DP_CK_SEL ,DP clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
if (((per.b(ad:0x400F3080+0x5F))&0x01)==0x01)
|
|
group.byte 0x5E++0x01
|
|
line.byte 0x00 "CFG30,Reset Control"
|
|
bitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED"
|
|
rbitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x01 "CFG31,Reset Control"
|
|
bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
bitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED"
|
|
bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE"
|
|
else
|
|
group.byte 0x5E++0x01
|
|
line.byte 0x00 "CFG30,Reset Control"
|
|
rbitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted"
|
|
rbitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED"
|
|
bitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x01 "CFG31,Reset Control"
|
|
bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
rbitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED"
|
|
bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE"
|
|
endif
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DCFG0,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x62++0x01
|
|
line.word 0x00 "DCFG1,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "DCFG2,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x66++0x01
|
|
line.word 0x00 "DCFG3,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "DCFG4,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x6A++0x01
|
|
line.word 0x00 "DCFG5,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "DCFG6,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x6E++0x01
|
|
line.word 0x00 "DCFG7,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UDB P1 U0"
|
|
base ad:0x400F3200
|
|
width 22.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PLD_IT0,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT0T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT0T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT0T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT0T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT0T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT0T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT0T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT0T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT0T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT0T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT0T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT0T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT0T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT0T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT0T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT0T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT0C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT0C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT0C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT0C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT0C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT0C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT0C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT0C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT0C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT0C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT0C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT0C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT0C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT0C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT0C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT0C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PLD_IT1,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT1T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT1T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT1T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT1T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT1T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT1T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT1T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT1T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT1T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT1T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT1T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT1T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT1T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT1T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT1T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT1T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT1C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT1C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT1C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT1C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT1C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT1C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT1C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT1C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT1C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT1C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT1C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT1C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT1C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT1C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT1C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT1C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "PLD_IT2,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT2T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT2T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT2T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT2T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT2T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT2T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT2T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT2T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT2T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT2T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT2T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT2T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT2T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT2T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT2T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT2T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT2C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT2C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT2C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT2C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT2C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT2C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT2C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT2C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT2C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT2C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT2C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT2C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT2C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT2C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT2C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT2C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PLD_IT3,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT3T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT3T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT3T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT3T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT3T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT3T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT3T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT3T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT3T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT3T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT3T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT3T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT3T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT3T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT3T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT3T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT3C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT3C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT3C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT3C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT3C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT3C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT3C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT3C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT3C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT3C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT3C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT3C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT3C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT3C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT3C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT3C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PLD_IT4,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT4T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT4T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT4T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT4T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT4T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT4T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT4T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT4T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT4T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT4T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT4T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT4T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT4T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT4T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT4T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT4T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT4C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT4C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT4C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT4C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT4C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT4C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT4C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT4C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT4C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT4C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT4C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT4C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT4C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT4C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT4C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT4C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PLD_IT5,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT5T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT5T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT5T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT5T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT5T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT5T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT5T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT5T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT5T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT5T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT5T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT5T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT5T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT5T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT5T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT5T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT5C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT5C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT5C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT5C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT5C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT5C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT5C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT5C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT5C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT5C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT5C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT5C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT5C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT5C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT5C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT5C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PLD_IT6,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT6T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT6T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT6T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT6T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT6T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT6T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT6T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT6T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT6T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT6T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT6T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT6T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT6T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT6T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT6T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT6T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT6C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT6C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT6C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT6C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT6C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT6C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT6C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT6C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT6C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT6C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT6C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT6C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT6C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT6C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT6C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT6C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PLD_IT7,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT7T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT7T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT7T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT7T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT7T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT7T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT7T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT7T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT7T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT7T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT7T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT7T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT7T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT7T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT7T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT7T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT7C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT7C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT7C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT7C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT7C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT7C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT7C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT7C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT7C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT7C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT7C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT7C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT7C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT7C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT7C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT7C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PLD_IT8,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT8T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT8T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT8T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT8T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT8T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT8T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT8T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT8T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT8T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT8T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT8T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT8T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT8T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT8T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT8T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT8T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT8C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT8C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT8C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT8C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT8C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT8C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT8C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT8C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT8C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT8C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT8C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT8C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT8C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT8C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT8C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT8C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PLD_IT9,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT9T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT9T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT9T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT9T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT9T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT9T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT9T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT9T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT9T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT9T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT9T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT9T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT9T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT9T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT9T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT9T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT9C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT9C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT9C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT9C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT9C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT9C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT9C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT9C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT9C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT9C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT9C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT9C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT9C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT9C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT9C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT9C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PLD_IT10,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT10T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT10T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT10T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT10T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT10T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT10T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT10T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT10T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT10T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT10T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT10T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT10T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT10T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT10T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT10T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT10T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT10C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT10C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT10C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT10C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT10C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT10C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT10C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT10C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT10C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT10C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT10C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT10C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT10C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT10C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT10C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT10C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PLD_IT11,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT11T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT11T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT11T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT11T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT11T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT11T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT11T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT11T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT11T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT11T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT11T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT11T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT11T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT11T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT11T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT11T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT11C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT11C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT11C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT11C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT11C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT11C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT11C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT11C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT11C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT11C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT11C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT11C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT11C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT11C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT11C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT11C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "PLD_ORT0,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT0_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT0_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT0_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT0_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT0_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT0_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT0_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT0_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT0_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT0_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT0_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT0_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT0_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT0_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT0_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT0_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x32++0x01
|
|
line.word 0x00 "PLD_ORT1,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT1_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT1_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT1_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT1_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT1_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT1_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT1_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT1_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT1_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT1_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT1_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT1_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT1_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT1_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT1_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT1_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "PLD_ORT2,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT2_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT2_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT2_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT2_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT2_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT2_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT2_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT2_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT2_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT2_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT2_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT2_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT2_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT2_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT2_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT2_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "PLD_ORT3,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT3_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT3_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT3_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT3_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT3_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT3_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT3_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT3_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT3_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT3_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT3_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT3_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT3_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT3_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT3_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT3_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x38++0x07
|
|
line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell Configuration For Carry Enable And Constant"
|
|
bitfld.word 0x00 15. " PLD1_MC3_DFF_C ,PLD1 MC3 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " PLD1_MC3_CEN ,PLD1 MC3 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " PLD1_MC2_DFF_C ,PLD1 MC2 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 12. " PLD1_MC2_CEN ,PLD1 MC2 carry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_MC1_DFF_C ,PLD1 MC1 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " PLD1_MC1_CEN ,PLD1 MC1 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " PLD1_MC0_DFF_C ,PLD1 MC0 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 8. " PLD1_MC0_CEN ,PLD1 MC0 carry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_MC3_DFF_C ,PLD0 MC3 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 6. " PLD0_MC3_CEN ,PLD0 MC3 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " PLD0_MC2_DFF_C ,PLD0 MC2 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 4. " PLD0_MC2_CEN ,PLD0 MC2 carry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_MC1_DFF_C ,PLD0 MC1 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 2. " PLD0_MC1_CEN ,PLD0 MC1 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " PLD0_MC0_DFF_C ,PLD0 MC0 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 0. " PLD0_MC0_CEN ,PLD0_MC0 carry enable" "Disabled,Enabled"
|
|
line.word 0x02 "PLD_MC_CFG_XORFB,PLD Macro Cell XOR Feedback"
|
|
bitfld.word 0x02 14.--15. " PLD1_MC3_XORFB ,PLD1 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 12.--13. " PLD1_MC2_XORFB ,PLD1 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 10.--11. " PLD1_MC1_XORFB ,PLD1 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 8.--9. " PLD1_MC0_XORFB ,PLD1 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
textline " "
|
|
bitfld.word 0x02 6.--7. " PLD0_MC3_XORFB ,PLD0 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 4.--5. " PLD0_MC2_XORFB ,PLD0 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 2.--3. " PLD0_MC1_XORFB ,PLD0 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 0.--1. " PLD0_MC0_XORFB ,PLD0 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
line.word 0x04 "PLD_MC_SET_RESET,PLD Macro Cell Set Reset Selection"
|
|
bitfld.word 0x04 15. " PLD1_MC3_RESET_SEL ,PLD1 MC3 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 14. " PLD1_MC3_SET_SEL ,PLD1 MC3 set select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 13. " PLD1_MC2_RESET_SEL ,PLD1 MC2 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 12. " PLD1_MC2_SET_SEL ,PLD1 MC2 set select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 11. " PLD1_MC1_RESET_SEL ,PLD1 MC1 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 10. " PLD1_MC1_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 9. " PLD1_MC0_RESET_SEL ,PLD1 MC0 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 8. " PLD1_MC0_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 7. " PLD0_MC3_RESET_SEL ,PLD0 MC3 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 6. " PLD0_MC3_SET_SEL ,PLD0 MC3 set select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 5. " PLD0_MC2_RESET_SEL ,PLD0 MC2 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 4. " PLD0_MC2_SET_SEL ,PLD0 MC2 set select enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 3. " PLD0_MC1_RESET_SEL ,PLD0 MC1 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 2. " PLD0_MC1_SET_SEL ,PLD0 MC1 set select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 1. " PLD0_MC0_RESET_SEL ,Reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 0. " PLD0_MC0_SET_SEL ,PLD0 MC0 set select enable" "Disabled,Enabled"
|
|
line.word 0x06 "PLD_MC_CFG_BYPASS,PLD Macro Cell Bypass Control"
|
|
bitfld.word 0x06 15. " NC15 ,Spare register bit NC15" "0,1"
|
|
bitfld.word 0x06 14. " PLD1_MC3_BYPASS ,PLD1 MC3 bypass selection" "REGISTER,COMBINATIONAL"
|
|
bitfld.word 0x06 13. " NC13 ,Spare register bit NC13" "0,1"
|
|
bitfld.word 0x06 12. " PLD1_MC2_BYPASS ,PLD1 MC2 bypass selection" "REGISTER,COMBINATIONAL"
|
|
textline " "
|
|
bitfld.word 0x06 11. " NC11 ,Spare register bit NC11" "0,1"
|
|
bitfld.word 0x06 10. " PLD1_MC1_BYPASS ,PLD1 MC1 bypass selection" "REGISTER,COMBINATIONAL"
|
|
bitfld.word 0x06 9. " NC9 ,Spare register bit NC9" "0,1"
|
|
bitfld.word 0x06 8. " PLD1_MC0_BYPASS ,PLD1 MC0 bypass selection" "REGISTER,COMBINATIONAL"
|
|
textline " "
|
|
bitfld.word 0x06 7. " NC7 ,Spare register bit NC7" "0,1"
|
|
bitfld.word 0x06 6. " PLD0_MC3_BYPASS ,PLD0 MC3 bypass selection" "REGISTER,COMBINATIONAL"
|
|
bitfld.word 0x06 5. " NC5 ,Spare register bit NC5" "0,1"
|
|
bitfld.word 0x06 4. " PLD0_MC2_BYPASS ,PLD0 MC2 bypass selection" "REGISTER,COMBINATIONAL"
|
|
textline " "
|
|
bitfld.word 0x06 3. " NC3 ,Spare register bit NC3" "0,1"
|
|
bitfld.word 0x06 2. " PLD0_MC1_BYPASS ,PLD0 MC1 bypass selection" "REGISTER,COMBINATIONAL"
|
|
bitfld.word 0x06 1. " NC1 ,Spare register bit NC1" "0,1"
|
|
bitfld.word 0x06 0. " PLD0_MC0_BYPASS ,PLD0 MC0 bypass selection" "REGISTER,COMBINATIONAL"
|
|
group.byte 0x40++0x17
|
|
line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0. Address Bits 0 And 1 To The Dynamic Configuration RAM"
|
|
bitfld.byte 0x00 4.--6. " RAD1 ,Datapath permutable input mux RAD1" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
bitfld.byte 0x00 0.--2. " RAD0 ,Datapath permutable input mux RAD0" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
line.byte 0x01 "CFG1,Datapath Input Selection - RAD2. Address Bit 2 To The Dynamic Configuration RAM"
|
|
bitfld.byte 0x01 7. " DP_RTE_BYPASS4 ,Dp_in bypass control 4" "DP_IN4_ROUTE,DP_IN4_BYPASS"
|
|
bitfld.byte 0x01 6. " DP_RTE_BYPASS3 ,Dp_in bypass control 3" "DP_IN3_ROUTE,DP_IN3_BYPASS"
|
|
bitfld.byte 0x01 5. " DP_RTE_BYPASS2 ,Dp_in bypass control 2" "DP_IN2_ROUTE,DP_IN2_BYPASS"
|
|
bitfld.byte 0x01 4. " DP_RTE_BYPASS1 ,Dp_in bypass control 1" "DP_IN1_ROUTE,DP_IN1_BYPASS"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " DP_RTE_BYPASS0 ,Dp_in bypass control 0" "DP_IN0_ROUTE,DP_IN0_BYPASS"
|
|
bitfld.byte 0x01 0.--2. " RAD2 ,Datapath permutable input mux 2" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
line.byte 0x02 "CFG2,Datapath Input Selection - F1_LD, F0_LD"
|
|
bitfld.byte 0x02 7. " NC7 ,Spare register bit NC7" "0,1"
|
|
bitfld.byte 0x02 4.--6. " F1_LD ,Datapath permutable input mux F1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
bitfld.byte 0x02 3. " DP_RTE_BYPASS5 ,Dp_in bypass control 5" "DP_IN5_ROUTE,DP_IN5_BYPASS"
|
|
bitfld.byte 0x02 0.--2. " F0_LD ,Datapath permutable input mux F0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
line.byte 0x03 "CFG3,Datapath Input Selection - D1_LD, D0_LD"
|
|
bitfld.byte 0x03 4.--6. " D1_LD ,Datapath permutable input mux D1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
bitfld.byte 0x03 0.--2. " D0_LD ,Datapath permutable input mux D0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
line.byte 0x04 "CFG4,Datapath Input Selection - CI_MUX SI_MUX"
|
|
bitfld.byte 0x04 4.--6. " CI_MUX ,Datapath permutable input mux CI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
bitfld.byte 0x04 0.--2. " SI_MUX ,Datapath permutable input mux SI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
|
line.byte 0x05 "CFG5,Datapath Output Selection For OUT1 OUT0"
|
|
bitfld.byte 0x05 4.--7. " OUT1 ,Datapath permutable output mux OUT1" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
|
|
bitfld.byte 0x05 0.--3. " OUT0 ,Datapath permutable output mux OUT0" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
|
|
line.byte 0x06 "CFG6,Datapath Output Selection For OUT3 OUT2"
|
|
bitfld.byte 0x06 4.--7. " OUT3 ,Datapath permutable output mux OUT3" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
|
|
bitfld.byte 0x06 0.--3. " OUT2 ,Datapath permutable output mux OUT2" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
|
|
line.byte 0x07 "CFG7,Datapath Output Selection For OUT5 OUT4"
|
|
bitfld.byte 0x07 4.--7. " OUT5 ,Datapath permutable output mux OUT5" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
|
|
bitfld.byte 0x07 0.--3. " OUT4 ,Datapath permutable output mux OUT4" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
|
|
line.byte 0x08 "CFG8,Datapath Output Synchronization Option"
|
|
bitfld.byte 0x08 7. " NC7 ,Spare register bit NC7" "0,1"
|
|
bitfld.byte 0x08 6. " NC6 ,Spare register bit NC6" "0,1"
|
|
bitfld.byte 0x08 0.--5. " OUT_SYNC ,Datapath output synchronization" "REGISTERED,COMBINATIONAL,?..."
|
|
line.byte 0x09 "CFG9,Datapath ALU Mask"
|
|
line.byte 0x0A "CFG10,Datapath Compare 0 Mask"
|
|
line.byte 0x0B "CFG11,Datapath Compare 1 Mask"
|
|
line.byte 0x0C "CFG12,Datapath Mask Enables And Shift In Configuration"
|
|
bitfld.byte 0x0C 7. " CMASK1_EN ,Datapath mask CMASK1 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0C 6. " CMASK0_EN ,Datapath mask CMASK0 enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0C 5. " AMASK_EN ,Datapath mask AMASK enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0C 4. " DEF_SI ,Datapath default shift value" "DEFAULT_0,DEFAULT_1"
|
|
textline " "
|
|
bitfld.byte 0x0C 2.--3. " SI_SELB ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN"
|
|
bitfld.byte 0x0C 0.--1. " SI_SELA ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN"
|
|
line.byte 0x0D "CFG13,Datapath Carry In And Compare Configuration"
|
|
bitfld.byte 0x0D 6.--7. " CMP_SELB ,Datapath compare select B" "A1_D1,A1_A0,A0_D1,A0_A0"
|
|
bitfld.byte 0x0D 4.--5. " CMP_SELA ,Datapath compare select A" "A1_D1,A1_A0,A0_D1,A0_A0"
|
|
bitfld.byte 0x0D 2.--3. " CI_SELB ,Datapath carry in source select B" "DEFAULT,REGISTERED,ROUTE,CHAIN"
|
|
bitfld.byte 0x0D 0.--1. " CI_SELA ,Datapath carry in source select A" "DEFAULT,REGISTERED,ROUTE,CHAIN"
|
|
line.byte 0x0E "CFG14,Datapath Chaining And MSB Configuration"
|
|
bitfld.byte 0x0E 7. " MSB_EN ,Datapath MSB selection enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0E 4.--6. " MSB_SEL ,Datapath MSB selection" "BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7"
|
|
bitfld.byte 0x0E 3. " CHAIN_CMSB ,Datapath CRC MSB chaining enable" "Disabled,Enabled"
|
|
bitfld.byte 0x0E 2. " CHAIN_FB ,Datapath CRC feedback chaining enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0E 1. " CHAIN1 ,Datapath condition chaining enable 1" "Disabled,Enabled"
|
|
bitfld.byte 0x0E 0. " CHAIN0 ,Datapath condition chaining enable 0" "Disabled,Enabled"
|
|
line.byte 0x0F "CFG15,Datapath FIFO, Shift And Parallel Input Control"
|
|
bitfld.byte 0x0F 7. " PI_SEL ,Datapath parallel input selection" "NORMAL,PARALLEL"
|
|
bitfld.byte 0x0F 6. " SHIFT_SEL ,Datapath shift out selection" "SOL_MSB,SOR"
|
|
bitfld.byte 0x0F 5. " PI_DYN ,Enable for dynamic control of parallel data input (Pi) mux" "Disabled,Enabled"
|
|
bitfld.byte 0x0F 4. " MSB_SI ,Arithmetic shift right operation shift in selection" "DEFAULT,MSB"
|
|
textline " "
|
|
bitfld.byte 0x0F 2.--3. " F1_INSEL ,Datapath FIFO configuration 1" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU"
|
|
bitfld.byte 0x0F 0.--1. " F0_INSEL ,Datapath FIFO configuration 0" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU"
|
|
line.byte 0x10 "CFG16,Datapath FIFO And Register Access Configuration Control"
|
|
bitfld.byte 0x10 7. " F1_CK_INV ,FIFO 1 clock Inverted" "NORMAL,Inverted"
|
|
bitfld.byte 0x10 6. " F0_CK_INV ,FIFO 0 clock Inverted" "NORMAL,Inverted"
|
|
bitfld.byte 0x10 5. " FIFO_FAST ,FIFO fast mode" "Disabled,Enabled"
|
|
bitfld.byte 0x10 4. " FIFO_CAP ,FIFO software capture mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x10 3. " FIFO_EDGE ,Edge/level sensitive FIFO write control (Fx_ld)" "LEVEL,EDGE"
|
|
bitfld.byte 0x10 2. " FIFO_ASYNC ,Asynchronous FIFO clocking support" "Disabled,Enabled"
|
|
bitfld.byte 0x10 1. " EXT_CRCPRS ,External CRC/PRS mode" "INTERNAL,EXTERNAL"
|
|
bitfld.byte 0x10 0. " WRK16_CONCAT ,Datapath register access mode" "DEFAULT,CONCATENATE"
|
|
line.byte 0x11 "CFG17,Datapath FIFO Control"
|
|
bitfld.byte 0x11 4. " FIFO_ADD_SYNC ,Sync flip-flop to FIFO block status" "Disabled,Enabled"
|
|
bitfld.byte 0x11 3. " NC3 ,Spare register bit NC3" "0,1"
|
|
bitfld.byte 0x11 2. " NC2 ,Spare register bit NC2" "0,1"
|
|
bitfld.byte 0x11 1. " F1_DYN ,FIFO 1 direction" "STATIC,DYNAMIC"
|
|
textline " "
|
|
bitfld.byte 0x11 0. " F0_DYN ,FIFO 0 direction" "STATIC,DYNAMIC"
|
|
line.byte 0x12 "CFG18,Control Register Mode 0"
|
|
line.byte 0x13 "CFG19,Control Register Mode 1"
|
|
line.byte 0x14 "CFG20,Status Register Input Mode Selection"
|
|
bitfld.byte 0x14 7. " STAT_MD[7] ,Bit 7 status input mode select" "Transparent,Sticky cleared"
|
|
bitfld.byte 0x14 6. " [6] ,Bit 6 status input mode select" "Transparent,Sticky cleared"
|
|
bitfld.byte 0x14 5. " [5] ,Bit 5 status input mode select" "Transparent,Sticky cleared"
|
|
bitfld.byte 0x14 4. " [4] ,Bit 4 status input mode select" "Transparent,Sticky cleared"
|
|
textline " "
|
|
bitfld.byte 0x14 3. " [3] ,Bit 3 status input mode select" "Transparent,Sticky cleared"
|
|
bitfld.byte 0x14 2. " [2] ,Bit 2 status input mode select" "Transparent,Sticky cleared"
|
|
bitfld.byte 0x14 1. " [1] ,Bit 1 status input mode select" "Transparent,Sticky cleared"
|
|
bitfld.byte 0x14 0. " [0] ,Bit 0 status input mode select" "Transparent,Sticky cleared"
|
|
line.byte 0x15 "CFG21,Spare Register Bits"
|
|
bitfld.byte 0x15 1. " NC1 ,Spare register bit NC1" "0,1"
|
|
bitfld.byte 0x15 0. " NC0 ,Spare register bit NC0" "0,1"
|
|
line.byte 0x16 "CFG22,SC Block Configuration Control"
|
|
bitfld.byte 0x16 4. " SC_EXT_RES ,Control register external reset operation" "Disabled,Enabled"
|
|
bitfld.byte 0x16 3. " SC_SYNC_MD ,SC sync mode" "NORMAL,SYNC_MODE"
|
|
bitfld.byte 0x16 2. " SC_INT_MD ,SC interrupt mode" "NORMAL,INT_MODE"
|
|
bitfld.byte 0x16 0.--1. " SC_OUT_CTL ,Output source for the status and control routing connections" "CONTROL,PARALLEL,COUNTER,?..."
|
|
line.byte 0x17 "CFG23,Counter Control"
|
|
bitfld.byte 0x17 6. " ALT_CNT ,Alternate operating mode of the counter" "DEFAULT_MODE,ALT_MODE"
|
|
bitfld.byte 0x17 5. " ROUTE_EN ,Counter enable signal for routing input" "Disabled,Enabled"
|
|
bitfld.byte 0x17 4. " ROUTE_LD ,Counter load signal for routing input" "Disabled,Enabled"
|
|
bitfld.byte 0x17 2.--3. " CNT_EN_SEL ,Routing inputs for the counter enable signal" "SC_IN4,SC_IN5,SC_IN6,SC_IO"
|
|
textline " "
|
|
bitfld.byte 0x17 0.--1. " CNT_LD_SEL ,Routing inputs for the counter load signal" "SC_IN0,SC_IN1,SC_IN2,SC_IN3"
|
|
if (((per.b(ad:0x400F3200+0x5F))&0x01)==0x01)
|
|
group.byte 0x58++0x03
|
|
line.byte 0x00 "CFG24,PLD0 Clock And Reset Control"
|
|
bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
|
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bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x01 "CFG25,PLD1 Clock And Reset Control"
|
|
bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
|
|
bitfld.byte 0x01 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x01 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x01 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x02 "CFG26,Datapath Clock And Reset Control"
|
|
bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
|
|
bitfld.byte 0x02 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x02 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x02 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x02 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x03 "CFG27,Status/control Clock And Reset Control"
|
|
bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
|
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bitfld.byte 0x03 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
else
|
|
group.byte 0x58++0x03
|
|
line.byte 0x00 "CFG24,PLD0 Clock And Reset Control"
|
|
bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x01 "CFG25,PLD1 Clock And Reset Control"
|
|
bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x02 "CFG26,Datapath Clock And Reset Control"
|
|
bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x03 "CFG27,Status/control Clock And Reset Control"
|
|
rbitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
endif
|
|
group.byte 0x5C++0x01
|
|
line.byte 0x00 "CFG28,Clock Selection For PLD1 And PLD0"
|
|
bitfld.byte 0x00 4.--7. " PLD1_CK_SEL ,PLD1 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
bitfld.byte 0x00 0.--3. " PLD0_CK_SEL ,PLD0 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
line.byte 0x01 "CFG29,Clock Selection For Datapath, Status And Control"
|
|
bitfld.byte 0x01 4.--7. " SC_CK_SEL ,SC clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
bitfld.byte 0x01 0.--3. " DP_CK_SEL ,DP clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
if (((per.b(ad:0x400F3200+0x5F))&0x01)==0x01)
|
|
group.byte 0x5E++0x01
|
|
line.byte 0x00 "CFG30,Reset Control"
|
|
bitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED"
|
|
rbitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x01 "CFG31,Reset Control"
|
|
bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
bitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED"
|
|
bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE"
|
|
else
|
|
group.byte 0x5E++0x01
|
|
line.byte 0x00 "CFG30,Reset Control"
|
|
rbitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted"
|
|
rbitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED"
|
|
bitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x01 "CFG31,Reset Control"
|
|
bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
rbitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED"
|
|
bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE"
|
|
endif
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DCFG0,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x62++0x01
|
|
line.word 0x00 "DCFG1,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "DCFG2,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x66++0x01
|
|
line.word 0x00 "DCFG3,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "DCFG4,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x6A++0x01
|
|
line.word 0x00 "DCFG5,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "DCFG6,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x6E++0x01
|
|
line.word 0x00 "DCFG7,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UDB P1 U1"
|
|
base ad:0x400F3280
|
|
width 22.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PLD_IT0,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT0T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT0T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT0T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT0T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT0T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT0T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT0T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT0T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT0T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT0T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT0T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT0T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT0T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT0T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT0T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT0T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT0C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT0C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT0C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT0C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT0C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT0C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT0C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT0C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT0C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT0C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT0C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT0C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT0C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT0C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT0C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT0C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "PLD_IT1,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT1T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT1T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT1T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT1T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT1T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT1T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT1T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT1T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT1T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT1T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT1T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT1T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT1T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT1T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT1T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT1T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT1C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT1C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT1C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT1C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT1C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT1C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT1C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT1C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT1C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT1C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT1C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT1C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT1C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT1C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT1C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT1C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "PLD_IT2,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT2T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT2T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT2T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT2T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT2T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT2T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT2T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT2T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT2T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT2T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT2T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT2T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT2T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT2T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT2T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT2T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT2C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT2C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT2C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT2C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT2C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT2C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT2C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT2C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT2C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT2C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT2C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT2C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT2C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT2C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT2C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT2C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "PLD_IT3,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT3T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT3T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT3T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT3T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT3T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT3T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT3T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT3T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT3T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT3T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT3T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT3T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT3T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT3T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT3T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT3T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT3C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT3C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT3C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT3C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT3C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT3C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT3C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT3C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT3C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT3C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT3C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT3C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT3C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT3C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT3C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT3C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PLD_IT4,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT4T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT4T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT4T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT4T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT4T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT4T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT4T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT4T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT4T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT4T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT4T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT4T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT4T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT4T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT4T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT4T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT4C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT4C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT4C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT4C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT4C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT4C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT4C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT4C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT4C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT4C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT4C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT4C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT4C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT4C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT4C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT4C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PLD_IT5,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT5T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT5T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT5T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT5T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT5T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT5T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT5T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT5T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT5T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT5T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT5T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT5T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT5T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT5T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT5T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT5T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT5C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT5C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT5C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT5C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT5C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT5C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT5C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT5C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT5C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT5C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT5C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT5C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT5C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT5C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT5C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT5C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PLD_IT6,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT6T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT6T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT6T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT6T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT6T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT6T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT6T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT6T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT6T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT6T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT6T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT6T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT6T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT6T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT6T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT6T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT6C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT6C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT6C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT6C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT6C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT6C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT6C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT6C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT6C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT6C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT6C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT6C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT6C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT6C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT6C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT6C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "PLD_IT7,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT7T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT7T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT7T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT7T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT7T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT7T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT7T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT7T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT7T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT7T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT7T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT7T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT7T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT7T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT7T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT7T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT7C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT7C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT7C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT7C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT7C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT7C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT7C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT7C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT7C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT7C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT7C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT7C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT7C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT7C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT7C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT7C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PLD_IT8,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT8T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT8T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT8T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT8T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT8T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT8T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT8T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT8T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT8T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT8T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT8T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT8T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT8T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT8T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT8T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT8T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT8C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT8C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT8C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT8C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT8C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT8C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT8C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT8C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT8C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT8C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT8C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT8C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT8C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT8C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT8C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT8C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PLD_IT9,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT9T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT9T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT9T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT9T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT9T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT9T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT9T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT9T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT9T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT9T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT9T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT9T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT9T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT9T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT9T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT9T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT9C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT9C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT9C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT9C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT9C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT9C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT9C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT9C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT9C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT9C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT9C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT9C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT9C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT9C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT9C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT9C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PLD_IT10,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT10T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT10T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT10T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT10T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT10T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT10T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT10T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT10T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT10T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT10T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT10T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT10T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT10T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT10T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT10T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT10T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT10C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT10C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT10C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT10C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT10C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT10C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT10C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT10C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT10C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT10C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT10C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT10C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT10C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT10C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT10C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT10C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PLD_IT11,PLD Input Terms"
|
|
bitfld.long 0x00 31. " PLD1_IT11T_7 ,PLD1 true input term 7" "0,1"
|
|
bitfld.long 0x00 30. " PLD1_IT11T_6 ,PLD1 true input term 6" "0,1"
|
|
bitfld.long 0x00 29. " PLD1_IT11T_5 ,PLD1 true input term 5" "0,1"
|
|
bitfld.long 0x00 28. " PLD1_IT11T_4 ,PLD1 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PLD1_IT11T_3 ,PLD1 true input term 3" "0,1"
|
|
bitfld.long 0x00 26. " PLD1_IT11T_2 ,PLD1 true input term 2" "0,1"
|
|
bitfld.long 0x00 25. " PLD1_IT11T_1 ,PLD1 true input term 1" "0,1"
|
|
bitfld.long 0x00 24. " PLD1_IT11T_0 ,PLD1 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PLD0_IT11T_7 ,PLD0 true input term 7" "0,1"
|
|
bitfld.long 0x00 22. " PLD0_IT11T_6 ,PLD0 true input term 6" "0,1"
|
|
bitfld.long 0x00 21. " PLD0_IT11T_5 ,PLD0 true input term 5" "0,1"
|
|
bitfld.long 0x00 20. " PLD0_IT11T_4 ,PLD0 true input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PLD0_IT11T_3 ,PLD0 true input term 3" "0,1"
|
|
bitfld.long 0x00 18. " PLD0_IT11T_2 ,PLD0 true input term 2" "0,1"
|
|
bitfld.long 0x00 17. " PLD0_IT11T_1 ,PLD0 true input term 1" "0,1"
|
|
bitfld.long 0x00 16. " PLD0_IT11T_0 ,PLD0 true input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PLD1_IT11C_7 ,PLD1 complement input term 7" "0,1"
|
|
bitfld.long 0x00 14. " PLD1_IT11C_6 ,PLD1 complement input term 6" "0,1"
|
|
bitfld.long 0x00 13. " PLD1_IT11C_5 ,PLD1 complement input term 5" "0,1"
|
|
bitfld.long 0x00 12. " PLD1_IT11C_4 ,PLD1 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PLD1_IT11C_3 ,PLD1 complement input term 3" "0,1"
|
|
bitfld.long 0x00 10. " PLD1_IT11C_2 ,PLD1 complement input term 2" "0,1"
|
|
bitfld.long 0x00 9. " PLD1_IT11C_1 ,PLD1 complement input term 1" "0,1"
|
|
bitfld.long 0x00 8. " PLD1_IT11C_0 ,PLD1 complement input term 0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLD0_IT11C_7 ,PLD0 complement input term 7" "0,1"
|
|
bitfld.long 0x00 6. " PLD0_IT11C_6 ,PLD0 complement input term 6" "0,1"
|
|
bitfld.long 0x00 5. " PLD0_IT11C_5 ,PLD0 complement input term 5" "0,1"
|
|
bitfld.long 0x00 4. " PLD0_IT11C_4 ,PLD0 complement input term 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PLD0_IT11C_3 ,PLD0 complement input term 3" "0,1"
|
|
bitfld.long 0x00 2. " PLD0_IT11C_2 ,PLD0 complement input term 2" "0,1"
|
|
bitfld.long 0x00 1. " PLD0_IT11C_1 ,PLD0 complement input term 1" "0,1"
|
|
bitfld.long 0x00 0. " PLD0_IT11C_0 ,PLD0 complement input term 0" "0,1"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "PLD_ORT0,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT0_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT0_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT0_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT0_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT0_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT0_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT0_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT0_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT0_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT0_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT0_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT0_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT0_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT0_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT0_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT0_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x32++0x01
|
|
line.word 0x00 "PLD_ORT1,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT1_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT1_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT1_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT1_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT1_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT1_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT1_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT1_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT1_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT1_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT1_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT1_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT1_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT1_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT1_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT1_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "PLD_ORT2,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT2_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT2_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT2_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT2_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT2_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT2_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT2_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT2_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT2_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT2_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT2_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT2_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT2_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT2_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT2_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT2_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x36++0x01
|
|
line.word 0x00 "PLD_ORT3,PLD OR Terms"
|
|
bitfld.word 0x00 15. " PLD1_ORT_PT3_7 ,PLD1 OR term 7" "0,1"
|
|
bitfld.word 0x00 14. " PLD1_ORT_PT3_6 ,PLD1 OR term 6" "0,1"
|
|
bitfld.word 0x00 13. " PLD1_ORT_PT3_5 ,PLD1 OR term 5" "0,1"
|
|
bitfld.word 0x00 12. " PLD1_ORT_PT3_4 ,PLD1 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_ORT_PT3_3 ,PLD1 OR term 3" "0,1"
|
|
bitfld.word 0x00 10. " PLD1_ORT_PT3_2 ,PLD1 OR term 2" "0,1"
|
|
bitfld.word 0x00 9. " PLD1_ORT_PT3_1 ,PLD1 OR term 1" "0,1"
|
|
bitfld.word 0x00 8. " PLD1_ORT_PT3_0 ,PLD1 OR term 0" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_ORT_PT3_7 ,PLD0 OR term 7" "0,1"
|
|
bitfld.word 0x00 6. " PLD0_ORT_PT3_6 ,PLD0 OR term 6" "0,1"
|
|
bitfld.word 0x00 5. " PLD0_ORT_PT3_5 ,PLD0 OR term 5" "0,1"
|
|
bitfld.word 0x00 4. " PLD0_ORT_PT3_4 ,PLD0 OR term 4" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_ORT_PT3_3 ,PLD0 OR term 3" "0,1"
|
|
bitfld.word 0x00 2. " PLD0_ORT_PT3_2 ,PLD0 OR term 2" "0,1"
|
|
bitfld.word 0x00 1. " PLD0_ORT_PT3_1 ,PLD0 OR term 1" "0,1"
|
|
bitfld.word 0x00 0. " PLD0_ORT_PT3_0 ,PLD0 OR term 0" "0,1"
|
|
group.word 0x38++0x07
|
|
line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell Configuration For Carry Enable And Constant"
|
|
bitfld.word 0x00 15. " PLD1_MC3_DFF_C ,PLD1 MC3 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 14. " PLD1_MC3_CEN ,PLD1 MC3 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " PLD1_MC2_DFF_C ,PLD1 MC2 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 12. " PLD1_MC2_CEN ,PLD1 MC2 carry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PLD1_MC1_DFF_C ,PLD1 MC1 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " PLD1_MC1_CEN ,PLD1 MC1 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " PLD1_MC0_DFF_C ,PLD1 MC0 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 8. " PLD1_MC0_CEN ,PLD1 MC0 carry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " PLD0_MC3_DFF_C ,PLD0 MC3 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 6. " PLD0_MC3_CEN ,PLD0 MC3 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " PLD0_MC2_DFF_C ,PLD0 MC2 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 4. " PLD0_MC2_CEN ,PLD0 MC2 carry enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " PLD0_MC1_DFF_C ,PLD0 MC1 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 2. " PLD0_MC1_CEN ,PLD0 MC1 carry enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " PLD0_MC0_DFF_C ,PLD0 MC0 DFF constant" "Not inverted,Inverted"
|
|
bitfld.word 0x00 0. " PLD0_MC0_CEN ,PLD0_MC0 carry enable" "Disabled,Enabled"
|
|
line.word 0x02 "PLD_MC_CFG_XORFB,PLD Macro Cell XOR Feedback"
|
|
bitfld.word 0x02 14.--15. " PLD1_MC3_XORFB ,PLD1 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 12.--13. " PLD1_MC2_XORFB ,PLD1 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 10.--11. " PLD1_MC1_XORFB ,PLD1 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 8.--9. " PLD1_MC0_XORFB ,PLD1 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
textline " "
|
|
bitfld.word 0x02 6.--7. " PLD0_MC3_XORFB ,PLD0 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 4.--5. " PLD0_MC2_XORFB ,PLD0 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 2.--3. " PLD0_MC1_XORFB ,PLD0 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
bitfld.word 0x02 0.--1. " PLD0_MC0_XORFB ,PLD0 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L"
|
|
line.word 0x04 "PLD_MC_SET_RESET,PLD Macro Cell Set Reset Selection"
|
|
bitfld.word 0x04 15. " PLD1_MC3_RESET_SEL ,PLD1 MC3 reset select enable" "Disabled,Enabled"
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|
bitfld.word 0x04 14. " PLD1_MC3_SET_SEL ,PLD1 MC3 set select enable" "Disabled,Enabled"
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bitfld.word 0x04 13. " PLD1_MC2_RESET_SEL ,PLD1 MC2 reset select enable" "Disabled,Enabled"
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bitfld.word 0x04 12. " PLD1_MC2_SET_SEL ,PLD1 MC2 set select enable" "Disabled,Enabled"
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|
textline " "
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bitfld.word 0x04 11. " PLD1_MC1_RESET_SEL ,PLD1 MC1 reset select enable" "Disabled,Enabled"
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|
bitfld.word 0x04 10. " PLD1_MC1_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled"
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bitfld.word 0x04 9. " PLD1_MC0_RESET_SEL ,PLD1 MC0 reset select enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 8. " PLD1_MC0_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled"
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|
textline " "
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bitfld.word 0x04 7. " PLD0_MC3_RESET_SEL ,PLD0 MC3 reset select enable" "Disabled,Enabled"
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bitfld.word 0x04 6. " PLD0_MC3_SET_SEL ,PLD0 MC3 set select enable" "Disabled,Enabled"
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|
bitfld.word 0x04 5. " PLD0_MC2_RESET_SEL ,PLD0 MC2 reset select enable" "Disabled,Enabled"
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|
bitfld.word 0x04 4. " PLD0_MC2_SET_SEL ,PLD0 MC2 set select enable" "Disabled,Enabled"
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|
textline " "
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bitfld.word 0x04 3. " PLD0_MC1_RESET_SEL ,PLD0 MC1 reset select enable" "Disabled,Enabled"
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|
bitfld.word 0x04 2. " PLD0_MC1_SET_SEL ,PLD0 MC1 set select enable" "Disabled,Enabled"
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bitfld.word 0x04 1. " PLD0_MC0_RESET_SEL ,Reset select enable" "Disabled,Enabled"
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|
bitfld.word 0x04 0. " PLD0_MC0_SET_SEL ,PLD0 MC0 set select enable" "Disabled,Enabled"
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line.word 0x06 "PLD_MC_CFG_BYPASS,PLD Macro Cell Bypass Control"
|
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bitfld.word 0x06 15. " NC15 ,Spare register bit NC15" "0,1"
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bitfld.word 0x06 14. " PLD1_MC3_BYPASS ,PLD1 MC3 bypass selection" "REGISTER,COMBINATIONAL"
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bitfld.word 0x06 13. " NC13 ,Spare register bit NC13" "0,1"
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bitfld.word 0x06 12. " PLD1_MC2_BYPASS ,PLD1 MC2 bypass selection" "REGISTER,COMBINATIONAL"
|
|
textline " "
|
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bitfld.word 0x06 11. " NC11 ,Spare register bit NC11" "0,1"
|
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bitfld.word 0x06 10. " PLD1_MC1_BYPASS ,PLD1 MC1 bypass selection" "REGISTER,COMBINATIONAL"
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bitfld.word 0x06 9. " NC9 ,Spare register bit NC9" "0,1"
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bitfld.word 0x06 8. " PLD1_MC0_BYPASS ,PLD1 MC0 bypass selection" "REGISTER,COMBINATIONAL"
|
|
textline " "
|
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bitfld.word 0x06 7. " NC7 ,Spare register bit NC7" "0,1"
|
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bitfld.word 0x06 6. " PLD0_MC3_BYPASS ,PLD0 MC3 bypass selection" "REGISTER,COMBINATIONAL"
|
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bitfld.word 0x06 5. " NC5 ,Spare register bit NC5" "0,1"
|
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bitfld.word 0x06 4. " PLD0_MC2_BYPASS ,PLD0 MC2 bypass selection" "REGISTER,COMBINATIONAL"
|
|
textline " "
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bitfld.word 0x06 3. " NC3 ,Spare register bit NC3" "0,1"
|
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bitfld.word 0x06 2. " PLD0_MC1_BYPASS ,PLD0 MC1 bypass selection" "REGISTER,COMBINATIONAL"
|
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bitfld.word 0x06 1. " NC1 ,Spare register bit NC1" "0,1"
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bitfld.word 0x06 0. " PLD0_MC0_BYPASS ,PLD0 MC0 bypass selection" "REGISTER,COMBINATIONAL"
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group.byte 0x40++0x17
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line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0. Address Bits 0 And 1 To The Dynamic Configuration RAM"
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bitfld.byte 0x00 4.--6. " RAD1 ,Datapath permutable input mux RAD1" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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bitfld.byte 0x00 0.--2. " RAD0 ,Datapath permutable input mux RAD0" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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line.byte 0x01 "CFG1,Datapath Input Selection - RAD2. Address Bit 2 To The Dynamic Configuration RAM"
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bitfld.byte 0x01 7. " DP_RTE_BYPASS4 ,Dp_in bypass control 4" "DP_IN4_ROUTE,DP_IN4_BYPASS"
|
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bitfld.byte 0x01 6. " DP_RTE_BYPASS3 ,Dp_in bypass control 3" "DP_IN3_ROUTE,DP_IN3_BYPASS"
|
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bitfld.byte 0x01 5. " DP_RTE_BYPASS2 ,Dp_in bypass control 2" "DP_IN2_ROUTE,DP_IN2_BYPASS"
|
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bitfld.byte 0x01 4. " DP_RTE_BYPASS1 ,Dp_in bypass control 1" "DP_IN1_ROUTE,DP_IN1_BYPASS"
|
|
textline " "
|
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bitfld.byte 0x01 3. " DP_RTE_BYPASS0 ,Dp_in bypass control 0" "DP_IN0_ROUTE,DP_IN0_BYPASS"
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bitfld.byte 0x01 0.--2. " RAD2 ,Datapath permutable input mux 2" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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line.byte 0x02 "CFG2,Datapath Input Selection - F1_LD, F0_LD"
|
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bitfld.byte 0x02 7. " NC7 ,Spare register bit NC7" "0,1"
|
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bitfld.byte 0x02 4.--6. " F1_LD ,Datapath permutable input mux F1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
|
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bitfld.byte 0x02 3. " DP_RTE_BYPASS5 ,Dp_in bypass control 5" "DP_IN5_ROUTE,DP_IN5_BYPASS"
|
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bitfld.byte 0x02 0.--2. " F0_LD ,Datapath permutable input mux F0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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line.byte 0x03 "CFG3,Datapath Input Selection - D1_LD, D0_LD"
|
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bitfld.byte 0x03 4.--6. " D1_LD ,Datapath permutable input mux D1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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bitfld.byte 0x03 0.--2. " D0_LD ,Datapath permutable input mux D0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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line.byte 0x04 "CFG4,Datapath Input Selection - CI_MUX SI_MUX"
|
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bitfld.byte 0x04 4.--6. " CI_MUX ,Datapath permutable input mux CI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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bitfld.byte 0x04 0.--2. " SI_MUX ,Datapath permutable input mux SI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..."
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line.byte 0x05 "CFG5,Datapath Output Selection For OUT1 OUT0"
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bitfld.byte 0x05 4.--7. " OUT1 ,Datapath permutable output mux OUT1" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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bitfld.byte 0x05 0.--3. " OUT0 ,Datapath permutable output mux OUT0" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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line.byte 0x06 "CFG6,Datapath Output Selection For OUT3 OUT2"
|
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bitfld.byte 0x06 4.--7. " OUT3 ,Datapath permutable output mux OUT3" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
|
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bitfld.byte 0x06 0.--3. " OUT2 ,Datapath permutable output mux OUT2" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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line.byte 0x07 "CFG7,Datapath Output Selection For OUT5 OUT4"
|
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bitfld.byte 0x07 4.--7. " OUT5 ,Datapath permutable output mux OUT5" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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bitfld.byte 0x07 0.--3. " OUT4 ,Datapath permutable output mux OUT4" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT"
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line.byte 0x08 "CFG8,Datapath Output Synchronization Option"
|
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bitfld.byte 0x08 7. " NC7 ,Spare register bit NC7" "0,1"
|
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bitfld.byte 0x08 6. " NC6 ,Spare register bit NC6" "0,1"
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bitfld.byte 0x08 0.--5. " OUT_SYNC ,Datapath output synchronization" "REGISTERED,COMBINATIONAL,?..."
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line.byte 0x09 "CFG9,Datapath ALU Mask"
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line.byte 0x0A "CFG10,Datapath Compare 0 Mask"
|
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line.byte 0x0B "CFG11,Datapath Compare 1 Mask"
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line.byte 0x0C "CFG12,Datapath Mask Enables And Shift In Configuration"
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bitfld.byte 0x0C 7. " CMASK1_EN ,Datapath mask CMASK1 enable" "Disabled,Enabled"
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bitfld.byte 0x0C 6. " CMASK0_EN ,Datapath mask CMASK0 enable" "Disabled,Enabled"
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bitfld.byte 0x0C 5. " AMASK_EN ,Datapath mask AMASK enable" "Disabled,Enabled"
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bitfld.byte 0x0C 4. " DEF_SI ,Datapath default shift value" "DEFAULT_0,DEFAULT_1"
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textline " "
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bitfld.byte 0x0C 2.--3. " SI_SELB ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN"
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bitfld.byte 0x0C 0.--1. " SI_SELA ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN"
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line.byte 0x0D "CFG13,Datapath Carry In And Compare Configuration"
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bitfld.byte 0x0D 6.--7. " CMP_SELB ,Datapath compare select B" "A1_D1,A1_A0,A0_D1,A0_A0"
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bitfld.byte 0x0D 4.--5. " CMP_SELA ,Datapath compare select A" "A1_D1,A1_A0,A0_D1,A0_A0"
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bitfld.byte 0x0D 2.--3. " CI_SELB ,Datapath carry in source select B" "DEFAULT,REGISTERED,ROUTE,CHAIN"
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bitfld.byte 0x0D 0.--1. " CI_SELA ,Datapath carry in source select A" "DEFAULT,REGISTERED,ROUTE,CHAIN"
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line.byte 0x0E "CFG14,Datapath Chaining And MSB Configuration"
|
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bitfld.byte 0x0E 7. " MSB_EN ,Datapath MSB selection enable" "Disabled,Enabled"
|
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bitfld.byte 0x0E 4.--6. " MSB_SEL ,Datapath MSB selection" "BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7"
|
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bitfld.byte 0x0E 3. " CHAIN_CMSB ,Datapath CRC MSB chaining enable" "Disabled,Enabled"
|
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bitfld.byte 0x0E 2. " CHAIN_FB ,Datapath CRC feedback chaining enable" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.byte 0x0E 1. " CHAIN1 ,Datapath condition chaining enable 1" "Disabled,Enabled"
|
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bitfld.byte 0x0E 0. " CHAIN0 ,Datapath condition chaining enable 0" "Disabled,Enabled"
|
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line.byte 0x0F "CFG15,Datapath FIFO, Shift And Parallel Input Control"
|
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bitfld.byte 0x0F 7. " PI_SEL ,Datapath parallel input selection" "NORMAL,PARALLEL"
|
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bitfld.byte 0x0F 6. " SHIFT_SEL ,Datapath shift out selection" "SOL_MSB,SOR"
|
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bitfld.byte 0x0F 5. " PI_DYN ,Enable for dynamic control of parallel data input (Pi) mux" "Disabled,Enabled"
|
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bitfld.byte 0x0F 4. " MSB_SI ,Arithmetic shift right operation shift in selection" "DEFAULT,MSB"
|
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textline " "
|
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bitfld.byte 0x0F 2.--3. " F1_INSEL ,Datapath FIFO configuration 1" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU"
|
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bitfld.byte 0x0F 0.--1. " F0_INSEL ,Datapath FIFO configuration 0" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU"
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line.byte 0x10 "CFG16,Datapath FIFO And Register Access Configuration Control"
|
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bitfld.byte 0x10 7. " F1_CK_INV ,FIFO 1 clock Inverted" "NORMAL,Inverted"
|
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bitfld.byte 0x10 6. " F0_CK_INV ,FIFO 0 clock Inverted" "NORMAL,Inverted"
|
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bitfld.byte 0x10 5. " FIFO_FAST ,FIFO fast mode" "Disabled,Enabled"
|
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bitfld.byte 0x10 4. " FIFO_CAP ,FIFO software capture mode" "Disabled,Enabled"
|
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textline " "
|
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bitfld.byte 0x10 3. " FIFO_EDGE ,Edge/level sensitive FIFO write control (Fx_ld)" "LEVEL,EDGE"
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bitfld.byte 0x10 2. " FIFO_ASYNC ,Asynchronous FIFO clocking support" "Disabled,Enabled"
|
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bitfld.byte 0x10 1. " EXT_CRCPRS ,External CRC/PRS mode" "INTERNAL,EXTERNAL"
|
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bitfld.byte 0x10 0. " WRK16_CONCAT ,Datapath register access mode" "DEFAULT,CONCATENATE"
|
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line.byte 0x11 "CFG17,Datapath FIFO Control"
|
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bitfld.byte 0x11 4. " FIFO_ADD_SYNC ,Sync flip-flop to FIFO block status" "Disabled,Enabled"
|
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bitfld.byte 0x11 3. " NC3 ,Spare register bit NC3" "0,1"
|
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bitfld.byte 0x11 2. " NC2 ,Spare register bit NC2" "0,1"
|
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bitfld.byte 0x11 1. " F1_DYN ,FIFO 1 direction" "STATIC,DYNAMIC"
|
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textline " "
|
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bitfld.byte 0x11 0. " F0_DYN ,FIFO 0 direction" "STATIC,DYNAMIC"
|
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line.byte 0x12 "CFG18,Control Register Mode 0"
|
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line.byte 0x13 "CFG19,Control Register Mode 1"
|
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line.byte 0x14 "CFG20,Status Register Input Mode Selection"
|
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bitfld.byte 0x14 7. " STAT_MD[7] ,Bit 7 status input mode select" "Transparent,Sticky cleared"
|
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bitfld.byte 0x14 6. " [6] ,Bit 6 status input mode select" "Transparent,Sticky cleared"
|
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bitfld.byte 0x14 5. " [5] ,Bit 5 status input mode select" "Transparent,Sticky cleared"
|
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bitfld.byte 0x14 4. " [4] ,Bit 4 status input mode select" "Transparent,Sticky cleared"
|
|
textline " "
|
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bitfld.byte 0x14 3. " [3] ,Bit 3 status input mode select" "Transparent,Sticky cleared"
|
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bitfld.byte 0x14 2. " [2] ,Bit 2 status input mode select" "Transparent,Sticky cleared"
|
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bitfld.byte 0x14 1. " [1] ,Bit 1 status input mode select" "Transparent,Sticky cleared"
|
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bitfld.byte 0x14 0. " [0] ,Bit 0 status input mode select" "Transparent,Sticky cleared"
|
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line.byte 0x15 "CFG21,Spare Register Bits"
|
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bitfld.byte 0x15 1. " NC1 ,Spare register bit NC1" "0,1"
|
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bitfld.byte 0x15 0. " NC0 ,Spare register bit NC0" "0,1"
|
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line.byte 0x16 "CFG22,SC Block Configuration Control"
|
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bitfld.byte 0x16 4. " SC_EXT_RES ,Control register external reset operation" "Disabled,Enabled"
|
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bitfld.byte 0x16 3. " SC_SYNC_MD ,SC sync mode" "NORMAL,SYNC_MODE"
|
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bitfld.byte 0x16 2. " SC_INT_MD ,SC interrupt mode" "NORMAL,INT_MODE"
|
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bitfld.byte 0x16 0.--1. " SC_OUT_CTL ,Output source for the status and control routing connections" "CONTROL,PARALLEL,COUNTER,?..."
|
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line.byte 0x17 "CFG23,Counter Control"
|
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bitfld.byte 0x17 6. " ALT_CNT ,Alternate operating mode of the counter" "DEFAULT_MODE,ALT_MODE"
|
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bitfld.byte 0x17 5. " ROUTE_EN ,Counter enable signal for routing input" "Disabled,Enabled"
|
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bitfld.byte 0x17 4. " ROUTE_LD ,Counter load signal for routing input" "Disabled,Enabled"
|
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bitfld.byte 0x17 2.--3. " CNT_EN_SEL ,Routing inputs for the counter enable signal" "SC_IN4,SC_IN5,SC_IN6,SC_IO"
|
|
textline " "
|
|
bitfld.byte 0x17 0.--1. " CNT_LD_SEL ,Routing inputs for the counter load signal" "SC_IN0,SC_IN1,SC_IN2,SC_IN3"
|
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if (((per.b(ad:0x400F3280+0x5F))&0x01)==0x01)
|
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group.byte 0x58++0x03
|
|
line.byte 0x00 "CFG24,PLD0 Clock And Reset Control"
|
|
bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
|
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bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
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bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
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bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
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line.byte 0x01 "CFG25,PLD1 Clock And Reset Control"
|
|
bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
|
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bitfld.byte 0x01 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x01 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x01 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x02 "CFG26,Datapath Clock And Reset Control"
|
|
bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
|
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bitfld.byte 0x02 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
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bitfld.byte 0x02 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x02 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x02 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x03 "CFG27,Status/control Clock And Reset Control"
|
|
bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3"
|
|
bitfld.byte 0x03 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
else
|
|
group.byte 0x58++0x03
|
|
line.byte 0x00 "CFG24,PLD0 Clock And Reset Control"
|
|
bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x01 "CFG25,PLD1 Clock And Reset Control"
|
|
bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x02 "CFG26,Datapath Clock And Reset Control"
|
|
bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x03 "CFG27,Status/control Clock And Reset Control"
|
|
rbitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset"
|
|
bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted"
|
|
bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL"
|
|
bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
endif
|
|
group.byte 0x5C++0x01
|
|
line.byte 0x00 "CFG28,Clock Selection For PLD1 And PLD0"
|
|
bitfld.byte 0x00 4.--7. " PLD1_CK_SEL ,PLD1 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
bitfld.byte 0x00 0.--3. " PLD0_CK_SEL ,PLD0 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
line.byte 0x01 "CFG29,Clock Selection For Datapath, Status And Control"
|
|
bitfld.byte 0x01 4.--7. " SC_CK_SEL ,SC clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
bitfld.byte 0x01 0.--3. " DP_CK_SEL ,DP clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..."
|
|
if (((per.b(ad:0x400F3280+0x5F))&0x01)==0x01)
|
|
group.byte 0x5E++0x01
|
|
line.byte 0x00 "CFG30,Reset Control"
|
|
bitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED"
|
|
rbitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x01 "CFG31,Reset Control"
|
|
bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
bitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED"
|
|
bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE"
|
|
else
|
|
group.byte 0x5E++0x01
|
|
line.byte 0x00 "CFG30,Reset Control"
|
|
rbitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted"
|
|
rbitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED"
|
|
bitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
line.byte 0x01 "CFG31,Reset Control"
|
|
bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3"
|
|
rbitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED"
|
|
bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE"
|
|
endif
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "DCFG0,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x62++0x01
|
|
line.word 0x00 "DCFG1,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "DCFG2,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x66++0x01
|
|
line.word 0x00 "DCFG3,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "DCFG4,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x6A++0x01
|
|
line.word 0x00 "DCFG5,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "DCFG6,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
group.word 0x6E++0x01
|
|
line.word 0x00 "DCFG7,Dynamic Configuration RAM"
|
|
bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR"
|
|
bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1"
|
|
bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1"
|
|
bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP"
|
|
textline " "
|
|
bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0"
|
|
bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1"
|
|
bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B"
|
|
bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "WRK8 (UDB 8-Bit Working)"
|
|
base ad:0x400F0000
|
|
width 15.
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "UDB_W8_A00,Accumulator 0"
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "UDB_W8_A01,Accumulator 0"
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "UDB_W8_A02,Accumulator 0"
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "UDB_W8_A03,Accumulator 0"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "UDB_W8_A10,Accumulator 1"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "UDB_W8_A11,Accumulator 1"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "UDB_W8_A12,Accumulator 1"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "UDB_W8_A13,Accumulator 1"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "UDB_W8_D00,Data 0"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "UDB_W8_D01,Data 0"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "UDB_W8_D02,Data 0"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "UDB_W8_D03,Data 0"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "UDB_W8_D10,Data 1"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "UDB_W8_D11,Data 1"
|
|
group.byte 0x32++0x00
|
|
line.byte 0x00 "UDB_W8_D12,Data 1"
|
|
group.byte 0x33++0x00
|
|
line.byte 0x00 "UDB_W8_D13,Data 1"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "UDB_W8_F00,Fifo 0"
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "UDB_W8_F01,Fifo 0"
|
|
group.byte 0x42++0x00
|
|
line.byte 0x00 "UDB_W8_F02,Fifo 0"
|
|
group.byte 0x43++0x00
|
|
line.byte 0x00 "UDB_W8_F03,Fifo 0"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "UDB_W8_F10,Fifo 1"
|
|
group.byte 0x51++0x00
|
|
line.byte 0x00 "UDB_W8_F11,Fifo 1"
|
|
group.byte 0x52++0x00
|
|
line.byte 0x00 "UDB_W8_F12,Fifo 1"
|
|
group.byte 0x53++0x00
|
|
line.byte 0x00 "UDB_W8_F13,Fifo 1"
|
|
rgroup.byte 0x60++0x00
|
|
line.byte 0x00 "UDB_W8_ST0,Status Register 0"
|
|
rgroup.byte 0x61++0x00
|
|
line.byte 0x00 "UDB_W8_ST1,Status Register 1"
|
|
rgroup.byte 0x62++0x00
|
|
line.byte 0x00 "UDB_W8_ST2,Status Register 2"
|
|
rgroup.byte 0x63++0x00
|
|
line.byte 0x00 "UDB_W8_ST3,Status Register 3"
|
|
group.byte 0x70++0x00
|
|
line.byte 0x00 "UDB_W8_CTL0,Control Register 0"
|
|
group.byte 0x71++0x00
|
|
line.byte 0x00 "UDB_W8_CTL1,Control Register 1"
|
|
group.byte 0x72++0x00
|
|
line.byte 0x00 "UDB_W8_CTL2,Control Register 2"
|
|
group.byte 0x73++0x00
|
|
line.byte 0x00 "UDB_W8_CTL3,Control Register 3"
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "UDB_W8_MSK0,Interrupt Mask 0"
|
|
group.byte 0x81++0x00
|
|
line.byte 0x00 "UDB_W8_MSK1,Interrupt Mask 1"
|
|
group.byte 0x82++0x00
|
|
line.byte 0x00 "UDB_W8_MSK2,Interrupt Mask 2"
|
|
group.byte 0x83++0x00
|
|
line.byte 0x00 "UDB_W8_MSK3,Interrupt Mask 3"
|
|
group.byte 0x90++0x00
|
|
line.byte 0x00 "UDB_W8_ACTL0,Auxiliary Control 0"
|
|
bitfld.byte 0x00 5. " CNT_START ,Control register counter enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " INT_EN ,Enable interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid"
|
|
bitfld.byte 0x00 2. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FIFO1_CLR ,FIFO 1 clear" "Normal,Cleared"
|
|
bitfld.byte 0x00 0. " FIFO0_CLR ,FIFO 0 clear" "Normal,Cleared"
|
|
group.byte 0x91++0x00
|
|
line.byte 0x00 "UDB_W8_ACTL1,Auxiliary Control 1"
|
|
bitfld.byte 0x00 5. " CNT_START ,Control register counter enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " INT_EN ,Enable interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid"
|
|
bitfld.byte 0x00 2. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FIFO1_CLR ,FIFO 1 clear" "Normal,Cleared"
|
|
bitfld.byte 0x00 0. " FIFO0_CLR ,FIFO 0 clear" "Normal,Cleared"
|
|
group.byte 0x92++0x00
|
|
line.byte 0x00 "UDB_W8_ACTL2,Auxiliary Control 2"
|
|
bitfld.byte 0x00 5. " CNT_START ,Control register counter enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " INT_EN ,Enable interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid"
|
|
bitfld.byte 0x00 2. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FIFO1_CLR ,FIFO 1 clear" "Normal,Cleared"
|
|
bitfld.byte 0x00 0. " FIFO0_CLR ,FIFO 0 clear" "Normal,Cleared"
|
|
group.byte 0x93++0x00
|
|
line.byte 0x00 "UDB_W8_ACTL3,Auxiliary Control 3"
|
|
bitfld.byte 0x00 5. " CNT_START ,Control register counter enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " INT_EN ,Enable interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid"
|
|
bitfld.byte 0x00 2. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FIFO1_CLR ,FIFO 1 clear" "Normal,Cleared"
|
|
bitfld.byte 0x00 0. " FIFO0_CLR ,FIFO 0 clear" "Normal,Cleared"
|
|
rgroup.byte 0xA0++0x00
|
|
line.byte 0x00 "UDB_W8_MC0,PLD Macrocell Reading 0"
|
|
bitfld.byte 0x00 4.--7. " PLD1_MC ,Read macrocell 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PLD0_MC ,Read macrocell 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0xA1++0x00
|
|
line.byte 0x00 "UDB_W8_MC1,PLD Macrocell Reading 1"
|
|
bitfld.byte 0x00 4.--7. " PLD1_MC ,Read macrocell 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PLD0_MC ,Read macrocell 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0xA2++0x00
|
|
line.byte 0x00 "UDB_W8_MC2,PLD Macrocell Reading 2"
|
|
bitfld.byte 0x00 4.--7. " PLD1_MC ,Read macrocell 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PLD0_MC ,Read macrocell 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.byte 0xA3++0x00
|
|
line.byte 0x00 "UDB_W8_MC3,PLD Macrocell Reading 3"
|
|
bitfld.byte 0x00 4.--7. " PLD1_MC ,Read macrocell 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 0.--3. " PLD0_MC ,Read macrocell 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0xB
|
|
tree.end
|
|
tree "WRK16CAT (UDB 16-bit Concatenated Working)"
|
|
base ad:0x400F1000
|
|
width 22.
|
|
group.word 0x0++0x01
|
|
line.word 0x00 "UDB_CAT16_A0,Accumulator Registers (A1,A0)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " A1 ,Accumulator 1 register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " A0 ,Accumulator 0 register"
|
|
group.word 0x2++0x01
|
|
line.word 0x00 "UDB_CAT16_A1,Accumulator Registers (A1,A0)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " A1 ,Accumulator 1 register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " A0 ,Accumulator 0 register"
|
|
group.word 0x4++0x01
|
|
line.word 0x00 "UDB_CAT16_A2,Accumulator Registers (A1,A0)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " A1 ,Accumulator 1 register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " A0 ,Accumulator 0 register"
|
|
group.word 0x6++0x01
|
|
line.word 0x00 "UDB_CAT16_A3,Accumulator Registers (A1,A0)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " A1 ,Accumulator 1 register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " A0 ,Accumulator 0 register"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "UDB_CAT16_D0,Data Registers (D1,D0)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " D1 ,Data 1 register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D0 ,Data 0 register"
|
|
group.word 0x42++0x01
|
|
line.word 0x00 "UDB_CAT16_D1,Data Registers (D1,D0)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " D1 ,Data 1 register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D0 ,Data 0 register"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "UDB_CAT16_D2,Data Registers (D1,D0)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " D1 ,Data 1 register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D0 ,Data 0 register"
|
|
group.word 0x46++0x01
|
|
line.word 0x00 "UDB_CAT16_D3,Data Registers (D1,D0)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " D1 ,Data 1 register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D0 ,Data 0 register"
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "UDB_CAT16_F0,Fifos (F1,F0)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " F1 ,FIFO 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " F0 ,FIFO 0"
|
|
group.word 0x82++0x01
|
|
line.word 0x00 "UDB_CAT16_F1,Fifos (F1,F0)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " F1 ,FIFO 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " F0 ,FIFO 0"
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "UDB_CAT16_F2,Fifos (F1,F0)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " F1 ,FIFO 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " F0 ,FIFO 0"
|
|
group.word 0x86++0x01
|
|
line.word 0x00 "UDB_CAT16_F3,Fifos (F1,F0)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " F1 ,FIFO 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " F0 ,FIFO 0"
|
|
rgroup.word 0xC0++0x01
|
|
line.word 0x00 "UDB_CAT16_CTL_ST0,Status And Control Registers (CTL,ST)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CTL ,Control register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ST ,Status register"
|
|
rgroup.word 0xC2++0x01
|
|
line.word 0x00 "UDB_CAT16_CTL_ST1,Status And Control Registers (CTL,ST)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CTL ,Control register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ST ,Status register"
|
|
rgroup.word 0xC4++0x01
|
|
line.word 0x00 "UDB_CAT16_CTL_ST2,Status And Control Registers (CTL,ST)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CTL ,Control register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ST ,Status register"
|
|
rgroup.word 0xC6++0x01
|
|
line.word 0x00 "UDB_CAT16_CTL_ST3,Status And Control Registers (CTL,ST)"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CTL ,Control register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ST ,Status register"
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "UDB_CAT16_ACTL_MSK0,Mask And Auxiliary Control Registers (ACTL,MSK)"
|
|
bitfld.word 0x00 13. " CNT_START ,Control register counter enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " INT_EN ,Enable interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid"
|
|
bitfld.word 0x00 10. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid"
|
|
textline " "
|
|
bitfld.word 0x00 9. " FIFO1_CLR ,FIFO 1 clear" "Normal,Cleared"
|
|
bitfld.word 0x00 8. " FIFO0_CLR ,FIFO 0 clear" "Normal,Cleared"
|
|
hexmask.word.byte 0x00 0.--7. 1. " MSK ,Interrupt mask register"
|
|
group.word 0x102++0x01
|
|
line.word 0x00 "UDB_CAT16_ACTL_MSK1,Mask And Auxiliary Control Registers (ACTL,MSK)"
|
|
bitfld.word 0x00 13. " CNT_START ,Control register counter enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " INT_EN ,Enable interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid"
|
|
bitfld.word 0x00 10. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid"
|
|
textline " "
|
|
bitfld.word 0x00 9. " FIFO1_CLR ,FIFO 1 clear" "Normal,Cleared"
|
|
bitfld.word 0x00 8. " FIFO0_CLR ,FIFO 0 clear" "Normal,Cleared"
|
|
hexmask.word.byte 0x00 0.--7. 1. " MSK ,Interrupt mask register"
|
|
group.word 0x104++0x01
|
|
line.word 0x00 "UDB_CAT16_ACTL_MSK2,Mask And Auxiliary Control Registers (ACTL,MSK)"
|
|
bitfld.word 0x00 13. " CNT_START ,Control register counter enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " INT_EN ,Enable interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid"
|
|
bitfld.word 0x00 10. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid"
|
|
textline " "
|
|
bitfld.word 0x00 9. " FIFO1_CLR ,FIFO 1 clear" "Normal,Cleared"
|
|
bitfld.word 0x00 8. " FIFO0_CLR ,FIFO 0 clear" "Normal,Cleared"
|
|
hexmask.word.byte 0x00 0.--7. 1. " MSK ,Interrupt mask register"
|
|
group.word 0x106++0x01
|
|
line.word 0x00 "UDB_CAT16_ACTL_MSK3,Mask And Auxiliary Control Registers (ACTL,MSK)"
|
|
bitfld.word 0x00 13. " CNT_START ,Control register counter enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " INT_EN ,Enable interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid"
|
|
bitfld.word 0x00 10. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid"
|
|
textline " "
|
|
bitfld.word 0x00 9. " FIFO1_CLR ,FIFO 1 clear" "Normal,Cleared"
|
|
bitfld.word 0x00 8. " FIFO0_CLR ,FIFO 0 clear" "Normal,Cleared"
|
|
hexmask.word.byte 0x00 0.--7. 1. " MSK ,Interrupt mask register"
|
|
rgroup.word 0x140++0x01
|
|
line.word 0x00 "UDB_CAT16_MC0,PLD Macrocell Read Registers (00,MC)"
|
|
bitfld.word 0x00 4.--7. " PLD1_MC ,PLD1 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PLD0_MC ,PLD0 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word 0x142++0x01
|
|
line.word 0x00 "UDB_CAT16_MC1,PLD Macrocell Read Registers (00,MC)"
|
|
bitfld.word 0x00 4.--7. " PLD1_MC ,PLD1 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PLD0_MC ,PLD0 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word 0x144++0x01
|
|
line.word 0x00 "UDB_CAT16_MC2,PLD Macrocell Read Registers (00,MC)"
|
|
bitfld.word 0x00 4.--7. " PLD1_MC ,PLD1 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PLD0_MC ,PLD0 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word 0x146++0x01
|
|
line.word 0x00 "UDB_CAT16_MC3,PLD Macrocell Read Registers (00,MC)"
|
|
bitfld.word 0x00 4.--7. " PLD1_MC ,PLD1 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 0.--3. " PLD0_MC ,PLD0 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
tree "WRK16DEF (UDB 16-bit Working)"
|
|
base ad:0x400F1000
|
|
width 16.
|
|
group.word 0x0++0x01
|
|
line.word 0x00 "UDB_W16_A00,Accumulator 0"
|
|
hexmask.word.byte 0x00 8.--15. 1. " A0_MS ,Accumulator 0 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " A0_LS ,Accumulator 0 for udb[n]"
|
|
group.word 0x2++0x01
|
|
line.word 0x00 "UDB_W16_A01,Accumulator 0"
|
|
hexmask.word.byte 0x00 8.--15. 1. " A0_MS ,Accumulator 0 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " A0_LS ,Accumulator 0 for udb[n]"
|
|
group.word 0x4++0x01
|
|
line.word 0x00 "UDB_W16_A02,Accumulator 0"
|
|
hexmask.word.byte 0x00 8.--15. 1. " A0_MS ,Accumulator 0 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " A0_LS ,Accumulator 0 for udb[n]"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "UDB_W16_A10,Accumulator 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " A1_MS ,Accumulator 1 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " A1_LS ,Accumulator 1 for udb[n]"
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "UDB_W16_A11,Accumulator 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " A1_MS ,Accumulator 1 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " A1_LS ,Accumulator 1 for udb[n]"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "UDB_W16_A12,Accumulator 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " A1_MS ,Accumulator 1 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " A1_LS ,Accumulator 1 for udb[n]"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "UDB_W16_D00,Data 0"
|
|
hexmask.word.byte 0x00 8.--15. 1. " D0_MS ,Data 0 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D0_LS ,Data 0 for udb[n]"
|
|
group.word 0x42++0x01
|
|
line.word 0x00 "UDB_W16_D01,Data 0"
|
|
hexmask.word.byte 0x00 8.--15. 1. " D0_MS ,Data 0 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D0_LS ,Data 0 for udb[n]"
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "UDB_W16_D02,Data 0"
|
|
hexmask.word.byte 0x00 8.--15. 1. " D0_MS ,Data 0 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D0_LS ,Data 0 for udb[n]"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "UDB_W16_D10,Data 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " D1_MS ,Data 1 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D1_LS ,Data 1 for udb[n]"
|
|
group.word 0x62++0x01
|
|
line.word 0x00 "UDB_W16_D11,Data 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " D1_MS ,Data 1 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D1_LS ,Data 1 for udb[n]"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "UDB_W16_D12,Data 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " D1_MS ,Data 1 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " D1_LS ,Data 1 for udb[n]"
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "UDB_W16_F00,FIFO 0"
|
|
hexmask.word.byte 0x00 8.--15. 1. " F0_MS ,Fifo 0 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " F0_LS ,Fifo 0 for udb[n]"
|
|
group.word 0x82++0x01
|
|
line.word 0x00 "UDB_W16_F01,FIFO 0"
|
|
hexmask.word.byte 0x00 8.--15. 1. " F0_MS ,Fifo 0 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " F0_LS ,Fifo 0 for udb[n]"
|
|
group.word 0x84++0x01
|
|
line.word 0x00 "UDB_W16_F02,FIFO 0"
|
|
hexmask.word.byte 0x00 8.--15. 1. " F0_MS ,Fifo 0 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " F0_LS ,Fifo 0 for udb[n]"
|
|
group.word 0xA0++0x01
|
|
line.word 0x00 "UDB_W16_F10,FIFO 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " F1_MS ,Fifo 1 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " F1_LS ,Fifo 1 for udb[n]"
|
|
group.word 0xA2++0x01
|
|
line.word 0x00 "UDB_W16_F11,FIFO 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " F1_MS ,Fifo 1 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " F1_LS ,Fifo 1 for udb[n]"
|
|
group.word 0xA4++0x01
|
|
line.word 0x00 "UDB_W16_F12,FIFO 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " F1_MS ,Fifo 1 for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " F1_LS ,Fifo 1 for udb[n]"
|
|
rgroup.word 0xC0++0x01
|
|
line.word 0x00 "UDB_W16_ST0,Status Register 0"
|
|
hexmask.word.byte 0x00 8.--15. 1. " ST_MS ,Status register for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ST_LS ,Status register for udb[n]"
|
|
rgroup.word 0xC2++0x01
|
|
line.word 0x00 "UDB_W16_ST1,Status Register 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " ST_MS ,Status register for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ST_LS ,Status register for udb[n]"
|
|
rgroup.word 0xC4++0x01
|
|
line.word 0x00 "UDB_W16_ST2,Status Register 2"
|
|
hexmask.word.byte 0x00 8.--15. 1. " ST_MS ,Status register for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ST_LS ,Status register for udb[n]"
|
|
group.word 0xE0++0x01
|
|
line.word 0x00 "UDB_W16_CTL0,Control Register 0"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CTL_MS ,Control register for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CTL_LS ,Control register for udb[n]"
|
|
group.word 0xE2++0x01
|
|
line.word 0x00 "UDB_W16_CTL1,Control Register 1"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CTL_MS ,Control register for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CTL_LS ,Control register for udb[n]"
|
|
group.word 0xE4++0x01
|
|
line.word 0x00 "UDB_W16_CTL2,Control Register 2"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CTL_MS ,Control register for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CTL_LS ,Control register for udb[n]"
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "UDB_W16_MSK0,Interrupt Mask 0"
|
|
hexmask.word.byte 0x00 8.--14. 1. " MSK_MS ,Interrupt mask register for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--6. 1. " MSK_LS ,Interrupt mask register for udb[n]"
|
|
group.word 0x102++0x01
|
|
line.word 0x00 "UDB_W16_MSK1,Interrupt Mask 1"
|
|
hexmask.word.byte 0x00 8.--14. 1. " MSK_MS ,Interrupt mask register for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--6. 1. " MSK_LS ,Interrupt mask register for udb[n]"
|
|
group.word 0x104++0x01
|
|
line.word 0x00 "UDB_W16_MSK2,Interrupt Mask 2"
|
|
hexmask.word.byte 0x00 8.--14. 1. " MSK_MS ,Interrupt mask register for udb[n+1]"
|
|
hexmask.word.byte 0x00 0.--6. 1. " MSK_LS ,Interrupt mask register for udb[n]"
|
|
group.word 0x120++0x01
|
|
line.word 0x00 "UDB_W16_ACTL0,Auxiliary Control 0"
|
|
bitfld.word 0x00 13. " CNT_START_MS ,Control register counter MS enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " INT_EN_MS ,Enable interrupt MS" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FIFO1_LVL_MS ,FIFO 1 fill status level MS control" "Normal,Mid"
|
|
bitfld.word 0x00 10. " FIFO0_LVL_MS ,FIFO 0 fill status level MS control" "Normal,Mid"
|
|
textline " "
|
|
bitfld.word 0x00 9. " FIFO1_CLR_MS ,FIFO 1 clear MS" "Normal,Cleared"
|
|
bitfld.word 0x00 8. " FIFO0_CLR_MS ,FIFO 0 clear MS" "Normal,Cleared"
|
|
bitfld.word 0x00 5. " CNT_START_LS ,Control register counter LS enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " INT_EN_LS ,Enable interrupt LS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FIFO1_LVL_LS ,FIFO 1 fill status level LS control" "Normal,Mid"
|
|
bitfld.word 0x00 2. " FIFO0_LVL_LS ,FIFO fill status level control" "Normal,Mid"
|
|
bitfld.word 0x00 1. " FIFO1_CLR_LS ,FIFO 1 clear LS" "Normal,Cleared"
|
|
bitfld.word 0x00 0. " FIFO0_CLR_LS ,FIFO 0 clear LS" "Normal,Cleared"
|
|
group.word 0x122++0x01
|
|
line.word 0x00 "UDB_W16_ACTL1,Auxiliary Control 1"
|
|
bitfld.word 0x00 13. " CNT_START_MS ,Control register counter MS enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " INT_EN_MS ,Enable interrupt MS" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FIFO1_LVL_MS ,FIFO 1 fill status level MS control" "Normal,Mid"
|
|
bitfld.word 0x00 10. " FIFO0_LVL_MS ,FIFO 0 fill status level MS control" "Normal,Mid"
|
|
textline " "
|
|
bitfld.word 0x00 9. " FIFO1_CLR_MS ,FIFO 1 clear MS" "Normal,Cleared"
|
|
bitfld.word 0x00 8. " FIFO0_CLR_MS ,FIFO 0 clear MS" "Normal,Cleared"
|
|
bitfld.word 0x00 5. " CNT_START_LS ,Control register counter LS enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " INT_EN_LS ,Enable interrupt LS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FIFO1_LVL_LS ,FIFO 1 fill status level LS control" "Normal,Mid"
|
|
bitfld.word 0x00 2. " FIFO0_LVL_LS ,FIFO fill status level control" "Normal,Mid"
|
|
bitfld.word 0x00 1. " FIFO1_CLR_LS ,FIFO 1 clear LS" "Normal,Cleared"
|
|
bitfld.word 0x00 0. " FIFO0_CLR_LS ,FIFO 0 clear LS" "Normal,Cleared"
|
|
group.word 0x124++0x01
|
|
line.word 0x00 "UDB_W16_ACTL2,Auxiliary Control 2"
|
|
bitfld.word 0x00 13. " CNT_START_MS ,Control register counter MS enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " INT_EN_MS ,Enable interrupt MS" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " FIFO1_LVL_MS ,FIFO 1 fill status level MS control" "Normal,Mid"
|
|
bitfld.word 0x00 10. " FIFO0_LVL_MS ,FIFO 0 fill status level MS control" "Normal,Mid"
|
|
textline " "
|
|
bitfld.word 0x00 9. " FIFO1_CLR_MS ,FIFO 1 clear MS" "Normal,Cleared"
|
|
bitfld.word 0x00 8. " FIFO0_CLR_MS ,FIFO 0 clear MS" "Normal,Cleared"
|
|
bitfld.word 0x00 5. " CNT_START_LS ,Control register counter LS enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " INT_EN_LS ,Enable interrupt LS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FIFO1_LVL_LS ,FIFO 1 fill status level LS control" "Normal,Mid"
|
|
bitfld.word 0x00 2. " FIFO0_LVL_LS ,FIFO fill status level control" "Normal,Mid"
|
|
bitfld.word 0x00 1. " FIFO1_CLR_LS ,FIFO 1 clear LS" "Normal,Cleared"
|
|
bitfld.word 0x00 0. " FIFO0_CLR_LS ,FIFO 0 clear LS" "Normal,Cleared"
|
|
rgroup.word 0x140++0x01
|
|
line.word 0x00 "UDB_W16_MC0,PLD Macrocell Reading 0"
|
|
bitfld.word 0x00 12.--15. " PLD1_MC_MS ,Read macrocell 1 for udb[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 8.--11. " PLD0_MC_MS ,Read macrocell 0 for udb[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 4.--7. " PLD1_MC_LS ,Read macrocell 1 for udb[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " PLD0_MC_LS ,Read macrocell 0 for udb[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rgroup.word 0x142++0x01
|
|
line.word 0x00 "UDB_W16_MC1,PLD Macrocell Reading 1"
|
|
bitfld.word 0x00 12.--15. " PLD1_MC_MS ,Read macrocell 1 for udb[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 8.--11. " PLD0_MC_MS ,Read macrocell 0 for udb[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 4.--7. " PLD1_MC_LS ,Read macrocell 1 for udb[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " PLD0_MC_LS ,Read macrocell 0 for udb[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
rgroup.word 0x144++0x01
|
|
line.word 0x00 "UDB_W16_MC2,PLD Macrocell Reading 2"
|
|
bitfld.word 0x00 12.--15. " PLD1_MC_MS ,Read macrocell 1 for udb[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 8.--11. " PLD0_MC_MS ,Read macrocell 0 for udb[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.word 0x00 4.--7. " PLD1_MC_LS ,Read macrocell 1 for udb[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.word 0x00 0.--3. " PLD0_MC_LS ,Read macrocell 0 for udb[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
width 0x0B
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|
tree.end
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|
tree "WRK32 (UDB 32-bit Working)"
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|
base ad:0x400F2000
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|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UDB_W32_A0,Accumulator 0"
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|
hexmask.long.byte 0x00 24.--31. 1. " A0_3 ,Accumulator 0 for udb[n+3]"
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hexmask.long.byte 0x00 16.--23. 1. " A0_2 ,Accumulator 0 for udb[n+2]"
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|
hexmask.long.byte 0x00 8.--15. 1. " A0_1 ,Accumulator 0 for udb[n+1]"
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|
hexmask.long.byte 0x00 0.--7. 1. " A0_0 ,Accumulator 0 for udb[n]"
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|
group.long 0x40++0x03
|
|
line.long 0x00 "UDB_W32_A1,Accumulator 1"
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|
hexmask.long.byte 0x00 24.--31. 1. " A1_3 ,Accumulator 1 for udb[n+3]"
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|
hexmask.long.byte 0x00 16.--23. 1. " A1_2 ,Accumulator 1 for udb[n+2]"
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|
hexmask.long.byte 0x00 8.--15. 1. " A1_1 ,Accumulator 1 for udb[n+1]"
|
|
hexmask.long.byte 0x00 0.--7. 1. " A1_0 ,Accumulator 1 for udb[n]"
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|
group.long 0x80++0x03
|
|
line.long 0x00 "UDB_W32_D0,Data 0"
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|
hexmask.long.byte 0x00 24.--31. 1. " D0_3 ,Data 0 for udb[n+3]"
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|
hexmask.long.byte 0x00 16.--23. 1. " D0_2 ,Data 0 for udb[n+2]"
|
|
hexmask.long.byte 0x00 8.--15. 1. " D0_1 ,Data 0 for udb[n+1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " D0_0 ,Data 0 for udb[n]"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "UDB_W32_D1,Data 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " D1_3 ,Data 1 for udb[n+3]"
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|
hexmask.long.byte 0x00 16.--23. 1. " D1_2 ,Data 1 for udb[n+2]"
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|
hexmask.long.byte 0x00 8.--15. 1. " D1_1 ,Data 1 for udb[n+1]"
|
|
hexmask.long.byte 0x00 0.--7. 1. " D1_0 ,Data 1 for udb[n]"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "UDB_W32_F0,FIFO 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " F0_3 ,Fifo 0 for udb[n+3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. " F0_2 ,Fifo 0 for udb[n+2]"
|
|
hexmask.long.byte 0x00 8.--15. 1. " F0_1 ,Fifo 0 for udb[n+1]"
|
|
hexmask.long.byte 0x00 0.--7. 1. " F0_0 ,Fifo 0 for udb[n]"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "UDB_W32_F1,FIFO 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. " F1_3 ,Fifo 1 for udb[n+3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. " F1_2 ,Fifo 1 for udb[n+2]"
|
|
hexmask.long.byte 0x00 8.--15. 1. " F1_1 ,Fifo 1 for udb[n+1]"
|
|
hexmask.long.byte 0x00 0.--7. 1. " F1_0 ,Fifo 1 for udb[n]"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "UDB_W32_ST,Status Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ST_3 ,Status register for udb[n+3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ST_2 ,Status register for udb[n+2]"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ST_1 ,Status register for udb[n+1]"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ST_0 ,Status register for udb[n]"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "UDB_W32_CTL,Status Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CTL_3 ,Control register for udb[n+3]"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CTL_2 ,Control register for udb[n+2]"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CTL_1 ,Control register for udb[n+1]"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CTL_0 ,Control register for udb[n]"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "UDB_W32_MSK,Interrupt Mask"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MSK_3 ,Interrupt mask register 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MSK_2 ,Interrupt mask register 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " MSK_1 ,Interrupt mask register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MSK_0 ,Interrupt mask register 0"
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "UDB_W32_ACTL,Auxiliary Control"
|
|
bitfld.long 0x00 29. " CNT_START_3 ,Control register counter 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INT_EN_3 ,Enable interrupt 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " FIFO1_LVL_3 ,FIFO 1 fill status level 3 control" "Normal,Mid"
|
|
bitfld.long 0x00 26. " FIFO0_LVL_3 ,FIFO 0 fill status level 3 control" "Normal,Mid"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FIFO1_CLR_3 ,FIFO 1 clear" "Normal,Cleared"
|
|
bitfld.long 0x00 24. " FIFO0_CLR_3 ,FIFO 0 clear" "Normal,Cleared"
|
|
bitfld.long 0x00 21. " CNT_START_2 ,Control register counter 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " INT_EN_2 ,Enable interrupt 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FIFO1_LVL_2 ,FIFO 1 fill status level 2 control" "Normal,Mid"
|
|
bitfld.long 0x00 18. " FIFO0_LVL_2 ,FIFO 0 fill status level 2 control" "Normal,Mid"
|
|
bitfld.long 0x00 17. " FIFO1_CLR_2 ,FIFO 1 clear 2" "Normal,Cleared"
|
|
bitfld.long 0x00 16. " FIFO0_CLR_2 ,FIFO 0 clear 2" "Normal,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CNT_START_1 ,Control register counter 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " INT_EN_1 ,Enable interrupt 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " FIFO1_LVL_1 ,FIFO fill status level control" "Normal,Mid"
|
|
bitfld.long 0x00 10. " FIFO0_LVL_1 ,FIFO fill status level 1 control" "Normal,Mid"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FIFO1_CLR_1 ,FIFO 1 clear 1" "Normal,Cleared"
|
|
bitfld.long 0x00 8. " FIFO0_CLR_1 ,FIFO 0 clear 1" "Normal,Cleared"
|
|
bitfld.long 0x00 5. " CNT_START_0 ,Control register counter 0 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " INT_EN_0 ,Enable interrupt 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FIFO1_LVL_0 ,FIFO 1 fill status level 0 control" "Normal,Mid"
|
|
bitfld.long 0x00 2. " FIFO0_LVL_0 ,FIFO 0 fill status level 0 control" "Normal,Mid"
|
|
bitfld.long 0x00 1. " FIFO1_CLR_0 ,FIFO 1 clear 0" "Normal,Cleared"
|
|
bitfld.long 0x00 0. " FIFO0_CLR_0 ,FIFO 0 clear 0" "Normal,Cleared"
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "UDB_W32_MC,PLD Macrocell Reading"
|
|
bitfld.long 0x00 28.--31. " PLD1_MC_3 ,Read macrocell 1 for udb[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " PLD0_MC_3 ,Read macrocell 0 for udb[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " PLD1_MC_2 ,Read macrocell 1 for udb[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " PLD0_MC_2 ,Read macrocell 0 for udb[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " PLD1_MC_1 ,Read macrocell 1 for udb[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " PLD0_MC_1 ,Read macrocell 0 for udb[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " PLD1_MC_0 ,Read macrocell 1 for udb[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " PLD0_MC_0 ,Read macrocell 0 for udb[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
textline ""
|