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Gen4_R-Car_Trace32/2_Trunk/perpsoc4hvpa144k.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: PSOC4HVPA144K On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2023-10-30 NEJ
; @Manufacturer: INFINEON - Infineon Technologies AG
; @Doc: Generated (TRACE32, build: 164352.), based on:
; psoc4hvpa144k.svd (Ver. 1.0)
; @Core: Cortex-M0+
; @Chip: CY8C4126LCE-HV403, CY8C4126LCE-HV413, CY8C4126LCE-HV423, CY8C4127LCE-HV403,
; CY8C4127LCE-HV413, CY8C4127LCE-HV423, CY8C4147LCE-HV403, CY8C4147LCE-HV413,
; CY8C4147LCE-HV423
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perpsoc4hvpa144k.per 16952 2023-11-08 13:36:10Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
sif (CORENAME()=="CORTEXM0+")
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
endif
tree "CPUSS (CPU Subsystem)"
base ad:0x40100000
group.long 0x0++0xB
line.long 0x0 "CONFIG,Configuration register"
bitfld.long 0x0 0. "VECT_IN_RAM,0': Vector Table is located at 0x0000:0000 in flash" "0,1"
line.long 0x4 "SYSREQ,SYSCALL control register"
bitfld.long 0x4 31. "SYSCALL_REQ,CPU/DAP writes a '1' to this field to request a SystemCall. The HMASTER_0 field indicates the source of the write access. Setting this field to '1' immediate results in a NMI. The SystemCall NMI interrupt handler sets this field to '0' after.." "0,1"
newline
rbitfld.long 0x4 30. "HMASTER_0,Indicates the source of the write access to the SYSREQ register." "0,1"
newline
rbitfld.long 0x4 29. "ROM_ACCESS_EN,Indicates that executing from Boot ROM is enabled. HW sets this field to '1' on reset or when the SystemCall NMI vector is fetched from Boot ROM. HW sets this field to '0' when the CPU is NOT executing from either Boot or System ROM. This.." "0,1"
newline
bitfld.long 0x4 28. "PRIVILEGED,Indicates whether the system is in privileged ('1') or user mode ('0'). Only CPU SW executing from ROM can set this field to '1' when ROM_ACCESS_EN is '1' (the CPU is executing a SystemCall NMI interrupt handler). Any other write to this field.." "0,1"
newline
bitfld.long 0x4 27. "DIS_RESET_VECT_REL,Disable Reset Vector fetch relocation:" "0,1"
newline
bitfld.long 0x4 26. "EXTERNAL_SYS_REQ,External HW SYS REQ. This bit is set by HW to cause a SYSCALL to BOOTROM. This bit may only be cleared by SW. When this bit is set the SYSCALL_COMMAND PRIVILEDGED HMASTER0 and SYSCALL_ARG content are invalid." "0,1"
newline
hexmask.long.word 0x4 0.--15. 1. "SYSCALL_COMMAND,Opcode of the system call being requested."
line.long 0x8 "SYSARG,SYSARG control register"
hexmask.long 0x8 0.--31. 1. "SYSCALL_ARG,Argument to System Call specified in SYSREQ. Semantics of argument depends on system call made. Typically a pointer to a parameter block."
group.long 0x20++0xB
line.long 0x0 "INT_SEL,Interrupt multiplexer select register"
hexmask.long 0x0 0.--31. 1. "DSI,Specifies interrupt source:"
line.long 0x4 "INT_MODE,DSI interrupt pulse mode register"
hexmask.long 0x4 0.--31. 1. "DSI_INT_PULSE,Specifies DSI interrupt format:"
line.long 0x8 "NMI_MODE,DSI NMI pulse mode register"
bitfld.long 0x8 0. "DSI_NMI_PULSE,Specifies DSI NMI format:" "0,1"
group.long 0x30++0xF
line.long 0x0 "FLASH_CTL,FLASH control register"
bitfld.long 0x0 21. "FLASH_ERR_SILENT,Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error a FLASH macro main interface internal error a FLASH macro main interface memory hole access a M0S8.." "0: Bus transfer has a bus error,1: Bus transfer does NOT have a bus error; i"
newline
bitfld.long 0x0 20. "FLASH_ECC_INJ_EN,Enable error injection for FLASH main interface." "0,1"
newline
bitfld.long 0x0 16.--17. "ARB,Arbitration policy:" "0: CPU has priority,1: DW/DMA has priority,2: Roundrobin,3: Roundrobin"
newline
bitfld.long 0x0 8. "FLASH_INVALIDATE,1': Invalidates the content of the flash controller's buffers." "0,1"
newline
bitfld.long 0x0 4. "PREF_EN,Prefetch enable:" "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "FLASH_WS,Amount of ROM wait states:"
line.long 0x4 "ROM_CTL,ROM control register"
bitfld.long 0x4 16.--17. "ARB,Arbitration policy:" "0: CPU has priority,1: DW/DMA has priority,2: Roundrobin,3: Roundrobin"
newline
bitfld.long 0x4 0. "ROM_WS,Amount of ROM wait states:" "0,1"
line.long 0x8 "RAM_CTL,RAM control register"
bitfld.long 0x8 16.--17. "ARB,`" "0,1,2,3"
newline
bitfld.long 0x8 6. "ECC_BIST_SWITCH,ECC_BIST_SWITCH: Substitutes Syndrome bits for normal data path during BIST testing. Data bits 31:25 on the SRAM data path both to and from the SRAM are replaced with the SRAM Syndrome data bits 38:32 during BIST testing when this bit is.." "0,1"
newline
bitfld.long 0x8 4. "ECC_INJ_EN,Enable error injection." "0: Syndrome is source from ECC Syndrome hardware,1: ECC_TEST"
newline
bitfld.long 0x8 2. "ECC_AUTO_CORRECT,HW ECC autocorrect functionality:" "0,1"
newline
bitfld.long 0x8 0. "ECC_ENABLE,Enable ECC operation:" "0,1"
line.long 0xC "DMAC_CTL,DMA controller register"
bitfld.long 0xC 16.--17. "ARB,Arbitration policy:" "0: CPU has priority,1: DW/DMA has priority,2: Roundrobin,3: Roundrobin"
group.long 0xA4++0xF
line.long 0x0 "RAM1_CTL,RAM 1 control register"
bitfld.long 0x0 16.--17. "ARB,Arbitration policy:" "0: CPU has priority,1: DW/DMA has priority,2: Roundrobin,3: Roundrobin"
newline
bitfld.long 0x0 6. "ECC_BIST_SWITCH,ECC_BIST_SWITCH: Substitutes Syndrome bits for normal data path during BIST testing. Data bits 31:25 on the SRAM data path both to and from the SRAM are replaced with the SRAM Syndrome data bits 38:32 during BIST testing when this bit is.." "0,1"
newline
bitfld.long 0x0 4. "ECC_INJ_EN,Enable error injection." "0: Syndrome is source from ECC Syndrome hardware,1: ECC_TEST"
newline
bitfld.long 0x0 2. "ECC_AUTO_CORRECT,HW ECC autocorrect functionality:" "0,1"
newline
bitfld.long 0x0 0. "ECC_ENABLE,Enable ECC operation:" "0,1"
line.long 0x4 "FLASHC1_CTL,FLASH Control1 control register"
bitfld.long 0x4 21. "FLASH_ERR_SILENT,Specifies bus transfer behavior for a non-recoverable error on the FLASH macro main interface (either a non-correctable ECC error a FLASH macro main interface internal error a FLASH macro main interface memory hole access a M0S8.." "0: Bus transfer has a bus error,1: Bus transfer does NOT have a bus error; i"
newline
bitfld.long 0x4 20. "FLASH_ECC_INJ_EN,Enable error injection for FLASH main interface." "0,1"
newline
bitfld.long 0x4 16.--17. "ARB,Arbitration policy:" "0: CPU has priority,1: DW/DMA has priority,2: Roundrobin,3: Roundrobin"
newline
bitfld.long 0x4 8. "FLASH_INVALIDATE,1': Invalidates the content of the flash controller's buffers." "0,1"
newline
bitfld.long 0x4 4. "PREF_EN,Prefetch enable:" "0,1"
newline
hexmask.long.byte 0x4 0.--3. 1. "FLASH_WS,Amount of ROM wait states:"
line.long 0x8 "FAULT_CTL,Fault Control Register"
bitfld.long 0x8 16.--17. "ARB,Arbitration policy:" "0: CPU has priority,1: DW/DMA has priority,2: Roundrobin,3: Roundrobin"
line.long 0xC "MTB_CTL,MTB control register"
bitfld.long 0xC 0. "CPU_HALT_TSTOP_EN,1': Enable CPU Halt to stop MTB trace. (HALTED output of CM0+ can stop the trace when high/'1')" "0,1"
rgroup.long 0xC4++0x3
line.long 0x0 "DAP_CTL,SWD DP Instance ID"
hexmask.long.byte 0x0 0.--3. 1. "INSTANCE_ID,Specifies the SWD DP Instance ID"
rgroup.long 0xD0++0x7
line.long 0x0 "RAM_STATUS,RAM Controller 0 Status"
bitfld.long 0x0 0. "WB_EMPTY,Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode." "0,1"
line.long 0x4 "RAM1_STATUS,RAM Controller 1 Status"
bitfld.long 0x4 0. "WB_EMPTY,Write buffer empty. This information is used when entering DeepSleep power mode: WB_EMPTY must be '1' before a transition to system DeepSleep power mode." "0,1"
group.long 0xE0++0x7
line.long 0x0 "BOOT_RESULT_0,Boot Result Register 0"
hexmask.long 0x0 0.--31. 1. "BOOT_RESULT,See m0s8srom BROS for details of register content after boot. Register Content only valid if there is an error indication from the boot process in CPUSS.SYSARGS."
line.long 0x4 "BOOT_RESULT_1,Boot Result Register 1"
hexmask.long 0x4 0.--31. 1. "BOOT_RESULT,See m0s8srom BROS for details of register content after boot. Register Content only valid if there is an error indication from the boot process in CPUSS.SYSARGS."
repeat 24. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x100)++0x3
line.long 0x0 "SL_CTL[$1],Slave control register"
bitfld.long 0x0 16.--17. "ARB,Arbitration policy:" "0: CPU priority,1: DMA priority,2: Roundrobin,3: Roundrobin"
repeat.end
group.long 0x200++0x3
line.long 0x0 "RAM_ECC_STATUS0,RAM ECC Status 0"
bitfld.long 0x0 31. "ECC_CAPTURE_ADDR_SYNDROME_VALID,ECC Capture address and Syndrome valid." "0: ECC_CAPTURE_ADDR_31_2 not valid,1: ECC_CAPTURE_ADDR_31_2 valid"
newline
hexmask.long 0x0 0.--29. 1. "ECC_CAPTURE_ADDR_31_2,Snapshot of CPUSS Address which caused the first correctable/un-correctable error interrupt. When first correctable/un-correctable error interrupt is generated ECC_CAPTURE_ADDR_SYNDROME_VALID is transitioned from 0 to 1 and this.."
rgroup.long 0x204++0x3
line.long 0x0 "RAM_ECC_STATUS1,RAM ECC Status 1"
hexmask.long.byte 0x0 0.--6. 1. "ECC_CAPTURE_SYNDROME,Snapshot of CPUSS Syndrome which caused the first correctable/un-correctable error interrupt. When first correctable/un-correctable error interrupt is generated ECC_CAPTURE_ADDR_SYNDROME_VALID is transitioned from 0 to 1 and this.."
group.long 0x208++0x3
line.long 0x0 "RAM1_ECC_STATUS0,RAM1 ECC Status 0"
bitfld.long 0x0 31. "ECC_CAPTURE_ADDR_SYNDROME_VALID,ECC Capture address and Syndrome valid." "0: ECC_CAPTURE_ADDR_31_2 not valid,1: ECC_CAPTURE_ADDR_31_2 valid"
newline
hexmask.long 0x0 0.--29. 1. "ECC_CAPTURE_ADDR_31_2,Snapshot of CPUSS Address which caused the first correctable/un-correctable error interrupt. When first correctable/un-correctable error interrupt is generated ECC_CAPTURE_ADDR_SYNDROME_VALID is transitioned from 0 to 1 and this.."
rgroup.long 0x20C++0x3
line.long 0x0 "RAM1_ECC_STATUS1,RAM1 ECC Status 1"
hexmask.long.byte 0x0 0.--6. 1. "ECC_CAPTURE_SYNDROME,Snapshot of CPUSS Syndrome which caused the first correctable/un-correctable error interrupt. When first correctable/un-correctable error interrupt is generated ECC_CAPTURE_ADDR_SYNDROME_VALID is transitioned from 0 to 1 and this.."
group.long 0x210++0x3
line.long 0x0 "ECC_TEST,ECC Test"
hexmask.long.byte 0x0 25.--31. 1. "SYND_DATA,ECC syndrome to use for error injection at address WORD_ADDR."
newline
hexmask.long 0x0 0.--24. 1. "WORD_ADDR,Specifies the word address where an error will be injected."
group.long 0x300++0xB
line.long 0x0 "INTR,Interrupt register"
bitfld.long 0x0 3. "SRAM1_NC_ERROR,Uncorrectable ECC Error For SRAM1 - interrupt signaled on interrupt_sram1_nc_ecc" "?,1: interrupt signaled on interrupt_sram1_nc_ecc"
newline
bitfld.long 0x0 2. "SRAM1_C_ERROR,Correctable ECC Error For SRAM1 - interrupt signaled on interrupt_sram1_c_ecc" "?,1: interrupt signaled on interrupt_sram1_c_ecc"
newline
bitfld.long 0x0 1. "SRAM0_NC_ERROR,Uncorrectable ECC Error For SRAM - interrupt signaled on interrupt_sram_nc_ecc" "0,1"
newline
bitfld.long 0x0 0. "SRAM0_C_ERROR,Correctable ECC Error For SRAM - interrupt signaled on interrupt_sram_nc_ecc" "0,1"
line.long 0x4 "INTR_SET,Interrupt set register"
bitfld.long 0x4 3. "SRAM1_NC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "SRAM1_C_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "SRAM0_NC_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "SRAM0_C_ERROR,SW writes a '1' to this field to set the corresponding field in interrupt request register." "0,1"
line.long 0x8 "INTR_MASK,Interrupt mask register"
bitfld.long 0x8 3. "SRAM1_NC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "SRAM1_C_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "SRAM0_NC_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "SRAM0_C_ERROR,Mask bit for corresponding field in interrupt request register." "0,1"
rgroup.long 0x30C++0x3
line.long 0x0 "INTR_MASKED,Interrupt masked register"
bitfld.long 0x0 3. "SRAM1_NC_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "SRAM1_C_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "SRAM0_NC_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "SRAM0_C_ERROR,Logical and of corresponding request and mask bits." "0,1"
group.long 0x400++0x3
line.long 0x0 "EXT_MS_CTL,External master control register"
bitfld.long 0x0 16.--17. "ARB,Arbitration policy:" "0: EXTM0/DMAC has priority,1: EXTM1 has priority,2: Roundrobin,3: Roundrobin"
group.long 0x500++0xF
line.long 0x0 "FLASHC_BERR_STATUS,Flash Bus Error Status"
bitfld.long 0x0 3. "FLASH_PROT_VIO,A M0S8 protection violation occurred in Flash Controller." "0,1"
newline
bitfld.long 0x0 2. "FLASH_MEMORY_HOLE,An access to a non-existent Flash Address occurred." "0,1"
newline
bitfld.long 0x0 1. "FLASH_UNCORRECTABLE,An Uncorrectable Read error occurred when accessing a Flash Macro." "0,1"
newline
bitfld.long 0x0 0. "INTERNAL_ERROR,Specifies/registers the occurrence of a FLASH macro interface internal error (typically the result of a read access while a program erase operation is ongoing) as a result of a CM0+ access." "0,1"
line.long 0x4 "FLASHC1_BERR_STATUS,Flash 1 Bus Error Status"
bitfld.long 0x4 3. "FLASH_PROT_VIO,See the Explanation for FLASHC_BERR_STATUS" "0,1"
newline
bitfld.long 0x4 2. "FLASH_MEMORY_HOLE,See the Explanation for FLASHC_BERR_STATUS" "0,1"
newline
bitfld.long 0x4 1. "FLASH_UNCORRECTABLE,See the Explanation for FLASHC_BERR_STATUS" "0,1"
newline
bitfld.long 0x4 0. "INTERNAL_ERROR,See the Explanation for FLASHC_BERR_STATUS" "0,1"
line.long 0x8 "FLASHC_ECC_CTL,Flash ECC Control"
hexmask.long.byte 0x8 24.--31. 1. "PARITY,ECC parity to use for ECC error injection at address WORD_ADDR."
newline
hexmask.long.tbyte 0x8 0.--23. 1. "FLASH_WORD_ADDR,Specifies the word address where an error will be injected."
line.long 0xC "FLASHC1_ECC_CTL,Flash 1 ECC Control"
hexmask.long.byte 0xC 24.--31. 1. "PARITY,See the Explanation for FLASHC_ECC_CTL"
newline
hexmask.long.tbyte 0xC 0.--23. 1. "FLASH_WORD_ADDR,See the Explanation for FLASHC_ECC_CTL"
tree.end
tree "DMAC (Direct Memory Access)"
base ad:0x40101000
group.long 0x0++0x3
line.long 0x0 "CTL,Control register"
bitfld.long 0x0 31. "ENABLED,0': IP is disabled. Non-retainable MMIO registers and logic functionality are reset (retainable MMIO registers are NOT reset):" "0,1"
rgroup.long 0x10++0xF
line.long 0x0 "STATUS,Status register"
bitfld.long 0x0 31. "ACTIVE,Specifies if there is a currently active (pending) channel in the data transfer engine:" "0,1"
bitfld.long 0x0 30. "PING_PONG,Specifies the descriptor of the channel is currently in use." "0,1"
bitfld.long 0x0 28.--29. "PRIO,Specifies the priority of the currently active channel." "0,1,2,3"
bitfld.long 0x0 24.--26. "STATE,State of the data transfer engine." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 16.--20. 1. "CH_ADDR,Specifies the channel number of the currently active channel. E.g. if we have 32 channels the channel number address with CH_ADDR_WIDTH is LOG2 (32) = 5 and this field is a 5-bit field. If channel 7 is active STATUS.ACTIVE is '1' and.."
hexmask.long.word 0x0 0.--15. 1. "DATA_NR,Specifies the index of the currently active data transfer. This value increases from '0' to CONTROL.DATA_NR."
line.long 0x4 "STATUS_SRC_ADDR,Source address status register"
hexmask.long 0x4 0.--31. 1. "ADDR,Base address or current address of source location of currently active channel. The specific address information is cycle dependent. This field is provided for debug purposes. Functionally no assumption should be made on whether the base or current.."
line.long 0x8 "STATUS_DST_ADDR,Destination address register"
hexmask.long 0x8 0.--31. 1. "ADDR,Base address or current address of destination location of currently active channel. The specific address information is cycle dependent. This field is provided for debug purposes. Functionally no assumption should be made on whether the base or.."
line.long 0xC "STATUS_CH_ACT,Channel activation status register"
hexmask.long 0xC 0.--31. 1. "CH,Channel activation status. Bit i is associated to channel i with i = 0 ... CH_NR-1."
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x80)++0x3
line.long 0x0 "CH_CTL[$1],Channel control register"
bitfld.long 0x0 31. "ENABLED,'0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled the data transfer(s) are aborted." "0,1"
bitfld.long 0x0 30. "PING_PONG,Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This.." "0,1"
bitfld.long 0x0 28.--29. "PRIO,Channel priority with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same.." "0,1,2,3"
repeat.end
group.long 0x7F0++0xB
line.long 0x0 "INTR,Interrupt register"
hexmask.long 0x0 0.--31. 1. "CH,Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit."
line.long 0x4 "INTR_SET,Interrupt set register"
hexmask.long 0x4 0.--31. 1. "CH,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)."
line.long 0x8 "INTR_MASK,Interrupt mask register"
hexmask.long 0x8 0.--31. 1. "CH,Mask for corresponding field in INTR register."
rgroup.long 0x7FC++0x3
line.long 0x0 "INTR_MASKED,Interrupt masked register"
hexmask.long 0x0 0.--31. 1. "CH,Logical BITWISE AND of corresponding request and mask fields."
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40101800 ad:0x40101820 ad:0x40101840 ad:0x40101860 ad:0x40101880 ad:0x401018A0 ad:0x401018C0 ad:0x401018E0)
tree "DESCR[$1]"
base $2
group.long ($2)++0x1F
line.long 0x0 "PING_SRC,Ping source address"
hexmask.long 0x0 0.--31. 1. "ADDR,Base address of source location. The effective source location is calculated by adding on offset (derived from PING.STATUS.CURR_DATA_NR) to this base address."
line.long 0x4 "PING_DST,Ping destination address"
hexmask.long 0x4 0.--31. 1. "ADDR,Base address of destination location. The effective destination location is calculated by adding on offset (derived from PING.STATUS.CURR_DATA_NR) to this base address."
line.long 0x8 "PING_CTL,Ping control word"
bitfld.long 0x8 30.--31. "OPCODE,Specifies the specific data transfer (only when the VALID bit of the descriptor's STATUS word is '1'):" "0,1,2,3"
bitfld.long 0x8 29. "FLIPPING,'1': On completion of the current descriptor structure the current descriptor identifier CH_CTLi.PING_PONG is flipped/inverted. In DMA mode descriptor list transfer flipping of the current descriptor identifier can be used to construct a.." "0,1"
bitfld.long 0x8 28. "PREEMPTABLE,'1': Transfer is preemptable. In DMA mode (OPCODE is '1' or '2') multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field.." "0,1"
bitfld.long 0x8 27. "SET_CAUSE,'1': On completion of the current descriptor structure the interrupt cause field of the channel is set to '1' (INTR.CH[i])." "0,1"
bitfld.long 0x8 26. "INV_DESCR,'1': On completion of the current descriptor structure the VALID bit of the descriptor's STATUS word is set to '0'." "0,1"
bitfld.long 0x8 24.--25. "WAIT_FOR_DEACT,Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the.." "0,1,2,3"
newline
bitfld.long 0x8 23. "SRC_ADDR_INCR,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not." "0,1"
bitfld.long 0x8 22. "SRC_TRANSFER_SIZE,Specifies the bus transfer size to the source location:" "0,1"
bitfld.long 0x8 21. "DST_ADDR_INCR,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not." "0,1"
bitfld.long 0x8 20. "DST_TRANSFER_SIZE,Specifies the bus transfer size to the destination location:" "0,1"
bitfld.long 0x8 16.--17. "DATA_SIZE,Specifies the data element size:" "0,1,2,3"
hexmask.long.word 0x8 0.--15. 1. "DATA_NR,Number of data elements that are transferred by a single descriptor."
line.long 0xC "PING_STATUS,Ping status word"
bitfld.long 0xC 31. "VALID,'0': Invalid cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code (and the interrupt cause bit is set to '1')." "0,1"
bitfld.long 0xC 16.--18. "RESPONSE,Response code (the first two codes NO_ERROR and DONE are the result of normal behavior the other codes are the result of erroneous behavior)." "0,1,2,3,4,5,6,7"
hexmask.long.word 0xC 0.--15. 1. "CURR_DATA_NR,Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field:"
line.long 0x10 "PONG_SRC,Pong source address"
hexmask.long 0x10 0.--31. 1. "ADDR,See description of PING_SRC."
line.long 0x14 "PONG_DST,Pong destination address"
hexmask.long 0x14 0.--31. 1. "ADDR,See description of PING_DST."
line.long 0x18 "PONG_CTL,Pong control word"
bitfld.long 0x18 30.--31. "OPCODE,See description of PING_CTL." "0,1,2,3"
bitfld.long 0x18 29. "FLIPPING,See description of PING_CTL." "0,1"
bitfld.long 0x18 28. "PREEMPTABLE,See description of PING_CTL." "0,1"
bitfld.long 0x18 27. "SET_CAUSE,See description of PING_CTL." "0,1"
bitfld.long 0x18 26. "INV_DESCR,See description of PING_CTL." "0,1"
bitfld.long 0x18 24.--25. "WAIT_FOR_DEACT,See description of PING_CTL." "0,1,2,3"
newline
bitfld.long 0x18 23. "SRC_ADDR_INCR,See description of PING_CTL." "0,1"
bitfld.long 0x18 22. "SRC_TRANSFER_SIZE,See description of PING_CTL." "0,1"
bitfld.long 0x18 21. "DST_ADDR_INCR,See description of PING_CTL." "0,1"
bitfld.long 0x18 20. "DST_TRANSFER_SIZE,See description of PING_CTL." "0,1"
bitfld.long 0x18 16.--17. "DATA_SIZE,See description of PING_CTL." "0,1,2,3"
hexmask.long.word 0x18 0.--15. 1. "DATA_NR,See description of PING_CTL."
line.long 0x1C "PONG_STATUS,Pong status word"
bitfld.long 0x1C 31. "VALID,See description of PING_STATUS." "0,1"
bitfld.long 0x1C 16.--18. "RESPONSE,See description of PING_STATUS." "0,1,2,3,4,5,6,7"
hexmask.long.word 0x1C 0.--15. 1. "CURR_DATA_NR,See description of PING_STATUS."
tree.end
repeat.end
tree.end
tree "FAULT (FAULT Structures)"
base ad:0x40130000
repeat 2. (list 0x0 0x1)(list ad:0x40130000 ad:0x40130100)
tree "STRUCT[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CTL,Fault control"
bitfld.long 0x0 2. "RESET_REQ_EN,Reset request enable:" "0,1"
bitfld.long 0x0 1. "OUT_EN,IO output signal enable:" "0,1"
bitfld.long 0x0 0. "TR_EN,Trigger output enable:" "0,1"
group.long ($2+0xC)++0x3
line.long 0x0 "STATUS,Fault status"
bitfld.long 0x0 31. "VALID,Valid indication:" "0,1"
hexmask.long.byte 0x0 0.--6. 1. "IDX,The fault source index for which fault information is captured in DATA0 through DATA1. The fault information is fault source specific and differs per product. The encoding will align with the definition in the Product Srpeadsheet."
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x10)++0x3
line.long 0x0 "DATA[$1],Fault data"
hexmask.long 0x0 0.--31. 1. "DATA,Captured fault source data."
repeat.end
rgroup.long ($2+0x40)++0x3
line.long 0x0 "PENDING0,Fault pending 0"
hexmask.long 0x0 0.--31. 1. "SOURCE,Bit mask of source causing the Fault. See the Product Spreadsheet Fault tab to determine the bit ordering."
group.long ($2+0x50)++0x3
line.long 0x0 "MASK0,Fault mask 0"
hexmask.long 0x0 0.--31. 1. "SOURCE,Fault source enables:"
group.long ($2+0xC0)++0xB
line.long 0x0 "INTR,Interrupt"
bitfld.long 0x0 0. "FAULT,This interrupt cause field is activated (HW sets the field to '1') when an enabled (MASK0 pending fault source is captured:" "0,1"
line.long 0x4 "INTR_SET,Interrupt set"
bitfld.long 0x4 0. "FAULT,SW writes a '1' to this field to set the corresponding field in the INTR register." "0,1"
line.long 0x8 "INTR_MASK,Interrupt mask"
bitfld.long 0x8 0. "FAULT,Mask bit for corresponding field in the INTR register." "0,1"
rgroup.long ($2+0xCC)++0x3
line.long 0x0 "INTR_MASKED,Interrupt masked"
bitfld.long 0x0 0. "FAULT,Logical and of corresponding INTR and INTR_MASK fields." "0,1"
tree.end
repeat.end
tree.end
tree "GPIO (General Purpose IO)"
base ad:0x40040000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40040000 ad:0x40040100 ad:0x40040200)
tree "PRT[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "DR,Port output data register"
bitfld.long 0x0 7. "DATA7,IO pad 7 output data." "0,1"
newline
bitfld.long 0x0 6. "DATA6,IO pad 6 output data." "0,1"
newline
bitfld.long 0x0 5. "DATA5,IO pad 5 output data." "0,1"
newline
bitfld.long 0x0 4. "DATA4,IO pad 4 output data." "0,1"
newline
bitfld.long 0x0 3. "DATA3,IO pad 3 output data." "0,1"
newline
bitfld.long 0x0 2. "DATA2,IO pad 2 output data." "0,1"
newline
bitfld.long 0x0 1. "DATA1,IO pad 1 output data." "0,1"
newline
bitfld.long 0x0 0. "DATA0,IO pad 0 output data." "0,1"
rgroup.long ($2+0x4)++0x3
line.long 0x0 "PS,Port IO pad state register"
bitfld.long 0x0 8. "FLT_DATA,Reads of this register return the logical state of the filtered pin." "0,1"
newline
bitfld.long 0x0 7. "DATA7,IO pad 7 state." "0,1"
newline
bitfld.long 0x0 6. "DATA6,IO pad 6 state." "0,1"
newline
bitfld.long 0x0 5. "DATA5,IO pad 5 state." "0,1"
newline
bitfld.long 0x0 4. "DATA4,IO pad 4 state." "0,1"
newline
bitfld.long 0x0 3. "DATA3,IO pad 3 state." "0,1"
newline
bitfld.long 0x0 2. "DATA2,IO pad 2 state." "0,1"
newline
bitfld.long 0x0 1. "DATA1,IO pad 1 state." "0,1"
newline
bitfld.long 0x0 0. "DATA0,IO pad 0 state:" "0: Logic low,1: Logic high"
group.long ($2+0x8)++0x13
line.long 0x0 "PC,Port configuration register"
bitfld.long 0x0 30.--31. "PORT_IB_MODE_SEL,This field selects the input buffer reference. The size (1 or 2 bits) and functionality is dependent on the IO cell." "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "PORT_SLEW_CTL,Slew control. Only used in the O_Z drive mode (mode 4: strong pull down open drain): This field is intended for I2C functionality. See BROS 001-70428 for more details." "0: HS mode (100pf < Cb < 400pF 1.71<VDDD<5.5..,1: HS mode (Cb<100pf 1.71<VDDD<5.5 Vext>2.8..,2: HS mode (100pf<Cb<400pf 1.71<VDDD<5.5 Vext<3.3)..,3: HS mode (Cb<100pf 1.71<VDDD<5.5 Vext<=2.8.."
newline
bitfld.long 0x0 27. "PORT_HYST_TRIM,This field is used to improve the hysteresis (to 10 percent of vddio) of the selectable trip point input buffer. The voltage reference comes from the VREFGEN block and is only available when using the VREFGEN block:" "0,1"
newline
bitfld.long 0x0 25. "PORT_SLOW,This field controls the output edge rate of all pins on the port:" "0,1"
newline
bitfld.long 0x0 24. "PORT_VTRIP_SEL,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage. Note: this bit is ignored for SIO ports the VTRIP_SEL settings in the SIO register are used instead (a separate VTRIP_SEL is provided for each pin pair)." "0: input buffer functions as a CMOS input buffer,1: input buffer functions as a LVTTL input buffer"
newline
bitfld.long 0x0 21.--23. "DM7,The GPIO drive mode for IO pad 7." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DM6,The GPIO drive mode for IO pad 6." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15.--17. "DM5,The GPIO drive mode for IO pad 5." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12.--14. "DM4,The GPIO drive mode for IO pad 4." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 9.--11. "DM3,The GPIO drive mode for IO pad 3." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--8. "DM2,The GPIO drive mode for IO pad 2." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3.--5. "DM1,The GPIO drive mode for IO pad 1." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "DM0,The GPIO drive mode for IO pad 0." "0: Mode 0 (analog mode): Output buffer off (high..,1: Mode 1: Output buffer off (high Z). Input buffer..,2: Mode 2: Strong pull down ('0') weak/resistive..,3: Mode 3: Weak/resistive pull down (PD) strong..,4: Mode 4: Strong pull down ('0') open drain (pull..,5: Mode 5: Open drain (pull down off) strong pull..,6: Mode 6: Strong pull down ('0') strong pull up..,7: Mode 7: Weak/resistive pull down (PD).."
line.long 0x4 "INTR_CFG,Port interrupt configuration register"
bitfld.long 0x4 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 16.--17. "FLT_EDGE_SEL,Same for the glitch filtered pin (selected by FLT_SELECT)." "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
newline
bitfld.long 0x4 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pad 7." "0,1,2,3"
newline
bitfld.long 0x4 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pad 6." "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pad 5." "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pad 4." "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pad 3." "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pad 2." "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pad 1." "0,1,2,3"
newline
bitfld.long 0x4 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pad 0." "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
line.long 0x8 "INTR,Port interrupt status register"
rbitfld.long 0x8 24. "PS_FLT_DATA,This is a duplicate of the contents of the PS register provided here to allow reading of both pin state and interrupt state of the port in a single read operation." "0,1"
newline
rbitfld.long 0x8 23. "PS_DATA7,N/A" "0,1"
newline
rbitfld.long 0x8 22. "PS_DATA6,N/A" "0,1"
newline
rbitfld.long 0x8 21. "PS_DATA5,N/A" "0,1"
newline
rbitfld.long 0x8 20. "PS_DATA4,N/A" "0,1"
newline
rbitfld.long 0x8 19. "PS_DATA3,N/A" "0,1"
newline
rbitfld.long 0x8 18. "PS_DATA2,N/A" "0,1"
newline
rbitfld.long 0x8 17. "PS_DATA1,N/A" "0,1"
newline
rbitfld.long 0x8 16. "PS_DATA0,`" "0,1"
newline
bitfld.long 0x8 8. "FLT_DATA,Deglitched interrupt pending (selected by FLT_SELECT)." "0,1"
newline
bitfld.long 0x8 7. "DATA7,Interrupt pending on IO pad 7. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 6. "DATA6,Interrupt pending on IO pad 6. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 5. "DATA5,Interrupt pending on IO pad 5. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 4. "DATA4,Interrupt pending on IO pad 4. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 3. "DATA3,Interrupt pending on IO pad 3. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 2. "DATA2,Interrupt pending on IO pad 2. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 1. "DATA1,Interrupt pending on IO pad 1. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 0. "DATA0,Interrupt pending on IO pad 0. Firmware writes 1 to clear the interrupt." "0,1"
line.long 0xC "SIO,Port SIO configuration register"
bitfld.long 0xC 29.--31. "PAIR_VOH67_SEL,See corresponding definition for IO pads 6 and 7." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 27.--28. "PAIR_VREF67_SEL,See corresponding definition for IO pads 6 and 7." "0,1,2,3"
newline
bitfld.long 0xC 26. "PAIR_VTRIP67_SEL,See corresponding definition for IO pads 6 and 7." "0,1"
newline
bitfld.long 0xC 25. "PAIR_IBUF67_SEL,See corresponding definition for IO pads 6 and 7." "0,1"
newline
bitfld.long 0xC 24. "PAIR_VREG67_EN,See corresponding definition for IO pads 6 and 7." "0,1"
newline
bitfld.long 0xC 21.--23. "PAIR_VOH45_SEL,See corresponding definition for IO pads 4 and 5." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 19.--20. "PAIR_VREF45_SEL,See corresponding definition for IO pads 4 and 5." "0,1,2,3"
newline
bitfld.long 0xC 18. "PAIR_VTRIP45_SEL,See corresponding definition for IO pads 4 and 5." "0,1"
newline
bitfld.long 0xC 17. "PAIR_IBUF45_SEL,See corresponding definition for IO pads 4 and 5." "0,1"
newline
bitfld.long 0xC 16. "PAIR_VREG45_EN,See corresponding definition for IO pads 4 and 5." "0,1"
newline
bitfld.long 0xC 13.--15. "PAIR_VOH23_SEL,See corresponding definition for IO pads 2 and 3." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 11.--12. "PAIR_VREF23_SEL,See corresponding definition for IO pads 2 and 3." "0,1,2,3"
newline
bitfld.long 0xC 10. "PAIR_VTRIP23_SEL,See corresponding definition for IO pads 2 and 3." "0,1"
newline
bitfld.long 0xC 9. "PAIR_IBUF23_SEL,See corresponding definition for IO pads 2 and 3." "0,1"
newline
bitfld.long 0xC 8. "PAIR_VREG23_EN,See corresponding definition for IO pads 2 and 3." "0,1"
newline
bitfld.long 0xC 5.--7. "PAIR_VOH01_SEL,Selects regulated Voh output level and trip point of input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL)." "0: Voh = 1*reference; e,1: Voh = 1,2: Voh = 1,3: Voh = 1,4: Voh = 2,5: Voh = 2,6: Voh = 2,7: Voh = 4"
newline
bitfld.long 0xC 3.--4. "PAIR_VREF01_SEL,Selects reference voltage Vref for trip-point of input buffer:" "0: trip-point reference of SRSS internal referece..,1: trip-point reference of SRSS internal referece..,2: trip-point reference of AMUXBUS_A,3: trip-point reference of AMUXBUS_B"
newline
bitfld.long 0xC 2. "PAIR_VTRIP01_SEL,Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'):" "0: input buffer functions as a CMOS input buffer,1: input buffer functions as a LVTTL input buffer"
newline
bitfld.long 0xC 1. "PAIR_IBUF01_SEL,Selects input buffer mode:" "0: singled ended input buffer,1: differential input buffer"
newline
bitfld.long 0xC 0. "PAIR_VREG01_EN,Selects output buffer mode:" "0: unregulated output buffer,1: regulated output buffer"
line.long 0x10 "PC2,Port configuration register 2"
bitfld.long 0x10 7. "INP_DIS7,Disables the input buffer for IO pad 7." "0,1"
newline
bitfld.long 0x10 6. "INP_DIS6,Disables the input buffer for IO pad 6." "0,1"
newline
bitfld.long 0x10 5. "INP_DIS5,Disables the input buffer for IO pad 5." "0,1"
newline
bitfld.long 0x10 4. "INP_DIS4,Disables the input buffer for IO pad 4." "0,1"
newline
bitfld.long 0x10 3. "INP_DIS3,Disables the input buffer for IO pad 3." "0,1"
newline
bitfld.long 0x10 2. "INP_DIS2,Disables the input buffer for IO pad 2." "0,1"
newline
bitfld.long 0x10 1. "INP_DIS1,Disables the input buffer for IO pad 1." "0,1"
newline
bitfld.long 0x10 0. "INP_DIS0,Disables the input buffer for IO pad 0 independent of the port control drive mode (PC.DM). This bit should be set when analog signals are present on the pin and PC.DM != 0 is required to use the output driver." "0,1"
group.long ($2+0x40)++0x13
line.long 0x0 "DR_SET,Port output data set register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,IO pad i:"
line.long 0x4 "DR_CLR,Port output data clear register"
hexmask.long.byte 0x4 0.--7. 1. "DATA,IO pad i:"
line.long 0x8 "DR_INV,Port output data invert register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,IO pad i:"
line.long 0xC "DS,Port drive strength register"
bitfld.long 0xC 17. "PORT_V1P2_IB_MODE_SEL,For GPIOV1P2 cell " "0: vtrip_sel register controls the vtrip_sel of the..,1: vddio detect cell output controls the vtrip_sel.."
newline
bitfld.long 0xC 16. "PORT_V1P2_VTRIP_SEL,For GPIOV1P2:" "0: VDDIO 1,1: VDDIO 1"
newline
bitfld.long 0xC 14.--15. "DS7,The GPIO drive strength for IO pad 7." "0,1,2,3"
newline
bitfld.long 0xC 12.--13. "DS6,The GPIO drive strength for IO pad 6." "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "DS5,The GPIO drive strength for IO pad 5." "0,1,2,3"
newline
bitfld.long 0xC 8.--9. "DS4,The GPIO drive strength for IO pad 4." "0,1,2,3"
newline
bitfld.long 0xC 6.--7. "DS3,The GPIO drive strength for IO pad 3." "0,1,2,3"
newline
bitfld.long 0xC 4.--5. "DS2,The GPIO drive strength for IO pad 2." "0,1,2,3"
newline
bitfld.long 0xC 2.--3. "DS1,The GPIO drive strength for IO pad 1." "0,1,2,3"
newline
bitfld.long 0xC 0.--1. "DS0,The GPIO drive strength for IO pad 0." "0: 1 ma drive nominal - changes with external R/C..,1: 2 ma drive nominal - changes with external R/C..,2: 4 ma drive nominal - changes with external R/C..,3: 8 ma drive nominal - changes with external R/C.."
line.long 0x10 "FILT_CONFIG,IO filter config register"
bitfld.long 0x10 23. "FILT7_EN,Filter selection for IO pad 7" "0,1"
newline
bitfld.long 0x10 22. "FILT6_EN,Filter selection for IO pad 6" "0,1"
newline
bitfld.long 0x10 21. "FILT5_EN,Filter selection for IO pad 5" "0,1"
newline
bitfld.long 0x10 20. "FILT4_EN,Filter selection for IO pad 4" "0,1"
newline
bitfld.long 0x10 19. "FILT3_EN,Filter selection for IO pad 3" "0,1"
newline
bitfld.long 0x10 18. "FILT2_EN,Filter selection for IO pad 2" "0,1"
newline
bitfld.long 0x10 17. "FILT1_EN,Filter selection for IO pad 1" "0,1"
newline
bitfld.long 0x10 16. "FILT0_EN,Filter selection for IO pad 0" "0,1"
newline
bitfld.long 0x10 14.--15. "TRIM7,trim bits for 50ns filter on IO pad 7" "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "TRIM6,trim bits for 50ns filter on IO pad 6" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "TRIM5,trim bits for 50ns filter on IO pad 5" "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "TRIM4,trim bits for 50ns filter on IO pad 4" "0,1,2,3"
newline
bitfld.long 0x10 6.--7. "TRIM3,trim bits for 50ns filter on IO pad 3" "0,1,2,3"
newline
bitfld.long 0x10 4.--5. "TRIM2,trim bits for 50ns filter on IO pad 2" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "TRIM1,trim bits for 50ns filter on IO pad 1" "0,1,2,3"
newline
bitfld.long 0x10 0.--1. "TRIM0,trim bits for 50ns filter on IO pad 0" "0,1,2,3"
group.long ($2+0x80)++0x3
line.long 0x0 "VREFGEN,Reference generator configuration register"
bitfld.long 0x0 8. "VREFGEN_EN,Reference generator enable:" "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "REF_SEL,Reference selection. A reference Voltage vinref is created using a Voltage vddio:"
tree.end
repeat.end
base ad:0x40040000
rgroup.long 0x1000++0x3
line.long 0x0 "INTR_CAUSE,Interrupt port cause register"
hexmask.long 0x0 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'gpio_interrupts[i]' for IO port i). The register is used when the system uses a shared/combined interrupt line.."
group.long 0x1010++0x3
line.long 0x0 "DFT_IO_TEST,IO SELF TEST control register for DfT purposes only"
bitfld.long 0x0 28. "DFT_ANA_POL_2,'analog_pol' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 27. "DFT_ANA_SEL_2,'analog_sel' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 26. "DFT_ANALOG_EN_2,'analog_en' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 25. "DFT_OE_N_2,'oe_n' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
newline
bitfld.long 0x0 24. "DFT_HLD_OVR_2,'hld_ovr' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 20. "DFT_ANA_POL_1,'analog_pol' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 19. "DFT_ANA_SEL_1,'analog_sel' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 18. "DFT_ANALOG_EN_1,'analog_en' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
newline
bitfld.long 0x0 17. "DFT_OE_N_1,'oe_n' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 16. "DFT_HLD_OVR_1,'hld_ovr' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 12. "DFT_ANA_POL_0,'analog_pol' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 11. "DFT_ANA_SEL_0,'analog_sel' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
newline
bitfld.long 0x0 10. "DFT_ANALOG_EN_0,'analog_en' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 9. "DFT_OE_N_0,'oe_n' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 8. "DFT_HLD_OVR_0,'hld_ovr' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 0.--1. "DFT_IO_TEST_MODE,DfT IO SELF TEST mode:" "0: Functional mode: disables the DfT IO SELF TEST;..,1: select this mode during ADFT testing to control..,2: select this mode for testing analog switches to..,3: select this mode for generic testing to control.."
rgroup.long 0x1020++0x3
line.long 0x0 "GPIOV1P2_DET,GPIOV1P2 Detect output"
bitfld.long 0x0 0. "DET,Indicates HI when VDDIO is in 1.8V range and LOW when VDDIO is in 1.2V range." "0,1"
tree.end
tree "HSIOM (High Speed IO Matrix)"
base ad:0x40020000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40020000 ad:0x40020100 ad:0x40020200)
tree "PRT[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "PORT_SEL,Port selection register"
hexmask.long.byte 0x0 28.--31. 1. "IO7_SEL,Selects connection for IO pad 7 route."
hexmask.long.byte 0x0 24.--27. 1. "IO6_SEL,Selects connection for IO pad 6 route."
hexmask.long.byte 0x0 20.--23. 1. "IO5_SEL,Selects connection for IO pad 5 route."
hexmask.long.byte 0x0 16.--19. 1. "IO4_SEL,Selects connection for IO pad 4 route."
hexmask.long.byte 0x0 12.--15. 1. "IO3_SEL,Selects connection for IO pad 3 route."
hexmask.long.byte 0x0 8.--11. 1. "IO2_SEL,Selects connection for IO pad 2 route."
hexmask.long.byte 0x0 4.--7. 1. "IO1_SEL,Selects connection for IO pad 1 route."
hexmask.long.byte 0x0 0.--3. 1. "IO0_SEL,Selects connection for IO pad 0 route."
tree.end
repeat.end
base ad:0x40020000
group.long 0x2000++0x3
line.long 0x0 "PUMP_CTL,Pump control"
bitfld.long 0x0 31. "ENABLED,Pump enabled:" "0,1"
bitfld.long 0x0 0. "CLOCK_SEL,Clock select:" "0,1"
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "AMUX_SPLIT_CTL[$1],AMUX splitter cell control"
bitfld.long 0x0 6. "SWITCH_BB_S0,T-switch control for AMUXBUSB vssa/ground switch." "0,1"
bitfld.long 0x0 5. "SWITCH_BB_SR,T-switch control for Right AMUXBUSB switch." "0,1"
bitfld.long 0x0 4. "SWITCH_BB_SL,T-switch control for Left AMUXBUSB switch." "0,1"
bitfld.long 0x0 2. "SWITCH_AA_S0,T-switch control for AMUXBUSA vssa/ground switch:" "0,1"
bitfld.long 0x0 1. "SWITCH_AA_SR,T-switch control for Right AMUXBUSA switch:" "0,1"
bitfld.long 0x0 0. "SWITCH_AA_SL,T-switch control for Left AMUXBUSA switch:" "0,1"
repeat.end
tree.end
tree "HVSS (High Voltage Subsystem)"
base ad:0x40060000
rgroup.long 0x0++0x3
line.long 0x0 "HVREG_STATUS,HVREG Status"
bitfld.long 0x0 0. "PWR_GOOD,High if regulator is settled and operating within normal limits" "0,1"
group.long 0x4++0x3
line.long 0x0 "HVREG_BIST,HVREG Bist"
bitfld.long 0x0 8. "EN_BURN_IN,Enable burn-in test mode with Vccd(1.8V) domain" "0,1"
newline
bitfld.long 0x0 4. "HVREG_DDFT,Enable HVREG DDFT outputs to DDFT interface when '1'" "0,1"
newline
bitfld.long 0x0 0.--2. "HVREG_ADFT,Controls ADFT switches" "0: Normal operation amuxbus_a=Z,1: Bias current monitor (NMOS drain) on amuxbus_a,2: N/A,3: N/A,4: N/A,5: N/A,6: N/A,7: N/A"
group.long 0x10++0x3
line.long 0x0 "RDIV_CTL,Resistor Attenuator Control"
bitfld.long 0x0 5. "RDIV_SCALE_1,VS1 attenuation" "0,1"
newline
bitfld.long 0x0 4. "RDIV_SCALE_0,VS0 attenuation" "0,1"
newline
bitfld.long 0x0 2. "RDIV_ACT_EN,Power modes where RDIV is enabled" "0: Enable in Active and Deep-Sleep modes,1: Enable in Active mode only"
newline
bitfld.long 0x0 1. "RDIV_EN_1,Enable VS1" "0: Disabled,1: Enabled during power modes selected by RDIVacten"
newline
bitfld.long 0x0 0. "RDIV_EN_0,Enable VS0" "0: Disabled,1: Enabled during power modes selected by RDIVacten"
group.long 0x20++0x7
line.long 0x0 "LIN_CTL,LIN Phy Control"
bitfld.long 0x0 31. "LIN_EN,Master enable of the LIN interface." "0: Interface is reset and LIN pin is in Hi-Z state,1: Enable the LIN interface"
newline
bitfld.long 0x0 8. "USE_ALT_INTERFACE,Selects Primary or Alternate interface for Phy. The primary use is to enable compliance testing by directly manipulating the Phy interface through GPIOs." "0: Primary interface,1: Alternate interface"
newline
bitfld.long 0x0 4. "SL_ROUND,0=Normal; 1=More moderate (rounded) for lower EMI" "0: Normal; 1=More moderate,?"
newline
bitfld.long 0x0 0.--2. "LIN_MODE,N/A" "0: OFF (TX off Rx off Bias Circuits Off) LIN pin..,1: TX off RX on LIN pin recessive (typically used..,2: TX off RX off Bias circuits on (faster turn-on..,3: TX on RX on TX w/weak pull-down (broken wire..,4: TX on RX on 1.0V/us TX edge rate,5: TX on RX on 1.5V/us TX edge rate,6: TX on RX on 2.0V/us TX edge rate,7: Fast mode (non-lin compliant up to 100kb/s.."
line.long 0x4 "LIN_TIMER,LIN Timer Control"
bitfld.long 0x4 31. "FAULT_TIMER_EN,Dominant state fault timer is running req'd for full LIN compatibility" "0,1"
newline
bitfld.long 0x4 30. "WAKEUP_TIMER_EN,Wakeup timer is running required for full LIN compatibility if using Deep-sleep power mode" "0,1"
newline
hexmask.long.word 0x4 16.--27. 1. "FAULT_TIMER,Number of LF_CLK edges before fault interrupt is triggered"
newline
hexmask.long.word 0x4 0.--11. 1. "WAKEUP_TIMER,Number of LF_CLK edges before wakeup interrupt is triggered"
rgroup.long 0x28++0x3
line.long 0x0 "LIN_STATUS,LIN Status"
bitfld.long 0x0 0. "LIN_RXD,Current state of LIN pin except in lin_mode 0 or 2 when RXD = 1." "0,1"
group.long 0x2C++0xF
line.long 0x0 "LIN_BIST,LIN BIST Control"
bitfld.long 0x0 5. "LIN_DFT_START,Delay line input" "0,1"
newline
bitfld.long 0x0 4. "LIN_DDFT,Enable LIN DDFT outputs to DDFT interface" "0: dft<0>,1: dft<1>"
newline
bitfld.long 0x0 0.--2. "LIN_ADFT,Enables Test Modes" "0: Normal Operation (DFT disabled) amuxbus_a=Z..,1: amuxbus_a=Iwave (PMOS drain) dft<1:0>=0,2: amuxbus_a=ErrBuff dft<1:0>=0,3: OUTFET = 1/10 (amuxbus_a=Z dft<1:0>=0),4: amuxbus_a=Ibias monitor (PMOS drain) dft<1:0>=0,5: Not used (amuxbus_a=Z dft<1:0>=0),6: amuxbus_a = Z dft<1> = LIN_DFT_START dft<0> =..,7: amuxbus_a = Z dft<1> = LIN_DFT_START dft<0> =.."
line.long 0x4 "LIN_INTR,LIN Interrupt Request Register"
bitfld.long 0x4 1. "FAULT,Interface asserted state for too long (dominant state timeout)" "0,1"
newline
bitfld.long 0x4 0. "WAKEUP,Master asserted dominant state wakeup (wakeup timer timeout)" "0,1"
line.long 0x8 "LIN_INTR_SET,LIN Interrupt set register"
bitfld.long 0x8 1. "FAULT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "WAKEUP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0xC "LIN_INTR_MASK,LIN Interrupt mask register"
bitfld.long 0xC 1. "FAULT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0xC 0. "WAKEUP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0x3C++0x3
line.long 0x0 "LIN_INTR_MASKED,LIN Interrupt masked register"
bitfld.long 0x0 1. "FAULT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "WAKEUP,Logical and of corresponding request and mask bits." "0,1"
group.long 0x40++0x3
line.long 0x0 "HVSS_DDFT,HVSS DDFT Control"
bitfld.long 0x0 0. "LSOUT_DDFT,Enable LSOUT DDFT output to DDFT interface" "?,1: lsout_ddft"
group.long 0xFF00++0x7
line.long 0x0 "HVREG_TRIM,HVREG Trim Settings. first byte"
hexmask.long.byte 0x0 0.--7. 1. "TRIM,N/A"
line.long 0x4 "LIN_TRIM,LIN Trim Settings"
hexmask.long.byte 0x4 0.--7. 1. "SLEW_CTL,N/A"
tree.end
tree "LIN (Local Interconnect Network)"
base ad:0x402D0000
group.long 0x0++0x7
line.long 0x0 "ERROR_CTL,Error control"
bitfld.long 0x0 31. "ENABLED,Error injection enable:" "0,1"
bitfld.long 0x0 23. "TX_CHECKSUM_STOP_ERROR,The checksum field STOP bits are inverted to '0'." "0,1"
bitfld.long 0x0 22. "TX_CHECKSUM_ERROR,The checksum field is inverted." "0,1"
bitfld.long 0x0 21. "TX_DATA_STOP_ERROR,The data field STOP bits are inverted to '0'." "0,1"
bitfld.long 0x0 19. "TX_PID_STOP_ERROR,The PID field STOP bits are inverted to '0'." "0,1"
newline
bitfld.long 0x0 18. "TX_PARITY_ERROR,In LIN mode the PID parity bit P[1] is inverted from !(ID[5] ^ ID[4] ^ ID[3] ^ ID[1]) to (ID[5] ^ ID[4] ^ ID[3] ^ ID[1])." "0,1"
bitfld.long 0x0 17. "TX_SYNC_STOP_ERROR,The synchronization field STOP bits are inverted to '0'." "0,1"
bitfld.long 0x0 16. "TX_SYNC_ERROR,The synchronization field is changed from 0x55 to 0x00." "0,1"
hexmask.long.byte 0x0 0.--4. 1. "CH_IDX,Specifies the channel index of the channel to which HW injected channel transmitter errors applies."
line.long 0x4 "TEST_CTL,Test control"
bitfld.long 0x4 31. "ENABLED,Test enable:" "0,1"
bitfld.long 0x4 16. "MODE,Test mode:" "0,1"
hexmask.long.byte 0x4 0.--4. 1. "CH_IDX,Specifies the channel index of the channel to which test applies. The channel IO signals of channel indices CH_IDX and CH_NR-1 are connected as specified by MODE. CH_IDX should be in the range [0 CH_NR-2] as channel index CH_NR-1 is always.."
repeat 2. (list 0x0 0x1)(list ad:0x402D8000 ad:0x402D8100)
tree "CH[$1]"
base $2
group.long ($2)++0x7
line.long 0x0 "CTL0,Control 0"
bitfld.long 0x0 31. "ENABLED,Channel enable:" "0,1"
bitfld.long 0x0 30. "FILTER_EN,RX filter (for 'lin_rx_in'):" "0,1"
bitfld.long 0x0 29. "PARITY_EN,Parity generation enable:" "0,1"
bitfld.long 0x0 28. "PARITY,Parity mode:" "0,1"
newline
bitfld.long 0x0 27. "BIT_ERROR_IGNORE,Specifies behavior on a detected bit error during header or response transmission:" "0,1"
bitfld.long 0x0 24. "MODE,Mode of operation:" "0: LIN mode.,1: UART mode."
hexmask.long.byte 0x0 16.--20. 1. "BREAK_WAKEUP_LENGTH,Break/wakeup length (minus 1) in bit periods:"
bitfld.long 0x0 8.--9. "BREAK_DELIMITER_LENGTH,In LIN mode this field specifies the break delimiter length:" "0,1,2,3"
newline
bitfld.long 0x0 4. "AUTO_EN,LIN transceiver auto enable:" "0,1"
bitfld.long 0x0 0.--1. "STOP_BITS,STOP bit periods:" "0,1,2,3"
line.long 0x4 "CTL1,Control 1"
bitfld.long 0x4 24.--25. "FRAME_TIMEOUT_SEL,Specifies the frame timeout mode:" "0,1,2,3"
hexmask.long.byte 0x4 16.--23. 1. "FRAME_TIMEOUT,Specifies the maximum allowed length (timeout value) for a frame frame header or frame response in bit periods. The LIN specification prescribes to set the maximum length to 1.4x the nominal length (Theader_max = 1.4 x Theader_nom and.."
bitfld.long 0x4 8. "CHECKSUM_ENHANCED,Checksum mode:" "0,1"
bitfld.long 0x4 0.--2. "DATA_NR,Number of data fields (minus 1) in the response (not including the checksum):" "0,1,2,3,4,5,6,7"
rgroup.long ($2+0x8)++0x3
line.long 0x0 "STATUS,Status"
bitfld.long 0x0 28. "RX_RESPONSE_CHECKSUM_ERROR,Copy of INTR.RX_RESPONSE_CHECKSUM_ERROR." "0,1"
bitfld.long 0x0 27. "RX_RESPONSE_FRAME_ERROR,Copy of INTR.RX_RESPONSE_FRAME_ERROR." "0,1"
bitfld.long 0x0 26. "RX_HEADER_PARITY_ERROR,Copy of INTR.RX_HEADER_PARITY_ERROR." "0,1"
bitfld.long 0x0 25. "RX_HEADER_SYNC_ERROR,Copy of INTR.RX_HEADER_SYNC_ERROR." "0,1"
newline
bitfld.long 0x0 24. "RX_HEADER_FRAME_ERROR,Copy of INTR.RX_HEADER_FRAME_ERROR." "0,1"
bitfld.long 0x0 17. "TX_RESPONSE_BIT_ERROR,Copy of INTR.TX_RESPONSE_BIT_ERROR." "0,1"
bitfld.long 0x0 16. "TX_HEADER_BIT_ERROR,Copy of INTR.TX_HEADER_BIT_ERROR." "0,1"
bitfld.long 0x0 13. "RX_DONE,Receiver done:" "0,1"
newline
bitfld.long 0x0 12. "TX_DONE,Transmitter done:" "0,1"
bitfld.long 0x0 9. "RX_BUSY,Receiver busy." "0,1"
bitfld.long 0x0 8. "TX_BUSY,Transmitter busy." "0,1"
bitfld.long 0x0 5. "RX_DATA0_FRAME_ERROR,Frame response first data field frame error. HW sets this field to '1' when the received STOP bits of the first response data field have an unexpected value (only after a RX_HEADER command) and this data byte is 0x00. HW clears.." "0,1"
newline
bitfld.long 0x0 4. "HEADER_RESPONSE,Frame header / response identifier (only valid when TX_BUSY or RX_BUSY is '1'):" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "DATA_IDX,Number of transferred data and checksum fields in the response (also acts as an index/address into response data field and checksum field registers (DATA0 DATA1 PID_CHECKSUM)) :"
group.long ($2+0x10)++0x3
line.long 0x0 "CMD,Command"
bitfld.long 0x0 9. "RX_RESPONSE,SW sets this field to '1' to receive a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (NOT set to '0' when an error is detected)." "0,1"
bitfld.long 0x0 8. "RX_HEADER,SW sets this field to '1' to receive a header. HW sets this field to '0' on successful completion of the ANY of the legal command sequences (NOT set to '0' when an error is detected in LIN mode)." "0,1"
bitfld.long 0x0 2. "TX_WAKEUP,SW sets this field to '1' to transmit a wakeup signal. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected)." "0,1"
bitfld.long 0x0 1. "TX_RESPONSE,SW sets this field to '1' to transmit a response. HW sets this field to '0' on successful completion of ANY of the legal command sequences (also set to '0' when an error is detected)." "0,1"
newline
bitfld.long 0x0 0. "TX_HEADER,SW sets this field to '1' to transmit a header. HW sets this field to '0' on successful completion of ANY of the following legal command sequences (also set to '0' when an error is detected):" "0,1"
group.long ($2+0x60)++0x3
line.long 0x0 "TX_RX_STATUS,TX/RX status"
bitfld.long 0x0 26. "EN_OUT,LIN transceiver enable ('en_out' 'lin_en_out'). This field controls the enable (or low active sleep enable) of the external transceiver:" "0,1"
rbitfld.long 0x0 24. "TX_OUT,LIN transmitter output ('tx_out' 'lin_tx_out')." "0,1"
rbitfld.long 0x0 17. "RX_IN,LIN receiver input ('rx_in' 'lin_rx_in' in functional mode)." "0,1"
rbitfld.long 0x0 16. "TX_IN,LIN transmitter input ('tx_in' 'lin_tx_in' in functional mode). TX_IN and RX_IN can be used to determine a wakeup source. Note that wakeup source detection relies on the external transceiver functionality." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "SYNC_COUNTER,Synchronization counter in LIN channel clock periods. After the receipt of a synchronization field this fields reflects the duration of the synchronization field. Ideally SYNC_COUNTER = 8*16 = 128 (the synchronization fields consists of.."
group.long ($2+0x80)++0xB
line.long 0x0 "PID_CHECKSUM,PID and checksum"
hexmask.long.byte 0x0 8.--15. 1. "CHECKSUM,Checksum."
hexmask.long.byte 0x0 0.--7. 1. "PID,Header protected identifier (PID)."
line.long 0x4 "DATA0,Response data 0"
hexmask.long.byte 0x4 24.--31. 1. "DATA4,Data field 4."
hexmask.long.byte 0x4 16.--23. 1. "DATA3,Data field 3."
hexmask.long.byte 0x4 8.--15. 1. "DATA2,Data field 2."
hexmask.long.byte 0x4 0.--7. 1. "DATA1,Data field 1."
line.long 0x8 "DATA1,Response data 1"
hexmask.long.byte 0x8 24.--31. 1. "DATA8,Data field 8."
hexmask.long.byte 0x8 16.--23. 1. "DATA7,Data field 7."
hexmask.long.byte 0x8 8.--15. 1. "DATA6,Data field 6."
hexmask.long.byte 0x8 0.--7. 1. "DATA5,Data field 5."
group.long ($2+0xC0)++0xB
line.long 0x0 "INTR,Interrupt"
bitfld.long 0x0 28. "RX_RESPONSE_CHECKSUM_ERROR,HW sets this field to '1' when the calculated checksum over the received PID and data fields is not the same as the received checksum." "0,1"
bitfld.long 0x0 27. "RX_RESPONSE_FRAME_ERROR,HW sets this field to '1' when the received START or STOP bits have an unexpected value (during response reception). HW does NOT use this field for the STOP bits of the first data field after a RX_HEADER command if the received.." "0,1"
bitfld.long 0x0 26. "RX_HEADER_PARITY_ERROR,HW sets this field to '1' when the received PID field has a parity error." "0,1"
bitfld.long 0x0 25. "RX_HEADER_SYNC_ERROR,HW sets this field to '1' when the received synchronization field is not received within the synchronization counter range [106 152] (see TX_RX_STATUS.SYNC_COUNTER)." "0,1"
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bitfld.long 0x0 24. "RX_HEADER_FRAME_ERROR,HW sets this field to '1' when the received START or STOP bits have an unexpected value (during header reception)." "0,1"
bitfld.long 0x0 17. "TX_RESPONSE_BIT_ERROR,HW sets this field to '1' when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during response transmission)." "0,1"
bitfld.long 0x0 16. "TX_HEADER_BIT_ERROR,HW sets this field to '1' when a transmitted 'lin_tx_out' value does NOT match a received 'lin_rx_in' value (during header transmission). This specific test allows for delay through the external transceiver. This mismatch is an.." "0,1"
bitfld.long 0x0 14. "TIMEOUT,HW sets this field to '1' when a frame frame header or frame response timeout is detected (per CTL.FRAME_TIMEOUT_SEL)." "0,1"
newline
bitfld.long 0x0 13. "RX_NOISE_DETECT,HW sets this field to '1' when isolated '0' or '1' 'in_rx_in' values are observed or when during sampling the last three 'lin_rx_in' values do NOT all have the same value. This mismatch is an indication of noise on the LIN line." "0,1"
bitfld.long 0x0 11. "RX_HEADER_SYNC_DONE,HW sets this field to '1' when a synchronization field is received (including trailing STOP bits)." "0,1"
bitfld.long 0x0 10. "RX_BREAK_WAKEUP_DONE,HW sets this field to '1' when a break or wakeup signal is received (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal." "0,1"
bitfld.long 0x0 9. "RX_RESPONSE_DONE,HW sets this field to '1' when a frame response (data fields and checksum field) is received (the CMD.RX_RESPONSE is completed). If CTL.AUTO_EN is '1' this includes the 4-bit period external transceiver disable post-amble." "0,1"
newline
bitfld.long 0x0 8. "RX_HEADER_DONE,HW sets this field to '1' when a frame header (break field synchronization field and PID field) is received (the CMD.RX_HEADER is completed). Specifically:" "0,1"
bitfld.long 0x0 2. "TX_WAKEUP_DONE,HW sets this field to '1' when a wakeup signal is transmitted (per CTL.BREAK_WAKEUP_LENGTH). This cause is activated on a transition from dominant/'0' state to recessive/'1' state; i.e. at the end of the wakeup signal." "0,1"
bitfld.long 0x0 1. "TX_RESPONSE_DONE,HW sets this field to '1' when a frame response (data fields and checksum field) is transmitted (the CMD.TX_RESPONSE is completed). If CTL.AUTO_EN is '1' this includes the 4-bit period external transceiver disable post-amble." "0,1"
bitfld.long 0x0 0. "TX_HEADER_DONE,HW sets this field to '1' when a frame header (break field synchronization field and PID field) is transmitted (the CMD.TX_HEADER is completed). Specifically:" "0,1"
line.long 0x4 "INTR_SET,Interrupt set"
bitfld.long 0x4 28. "RX_RESPONSE_CHECKSUM_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
bitfld.long 0x4 27. "RX_RESPONSE_FRAME_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
bitfld.long 0x4 26. "RX_HEADER_PARITY_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
bitfld.long 0x4 25. "RX_HEADER_SYNC_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
newline
bitfld.long 0x4 24. "RX_HEADER_FRAME_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
bitfld.long 0x4 17. "TX_RESPONSE_BIT_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
bitfld.long 0x4 16. "TX_HEADER_BIT_ERROR,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
bitfld.long 0x4 14. "TIMEOUT,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 13. "RX_NOISE_DETECT,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
bitfld.long 0x4 11. "RX_HEADER_SYNC_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
bitfld.long 0x4 10. "RX_BREAK_WAKEUP_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
bitfld.long 0x4 9. "RX_RESPONSE_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 8. "RX_HEADER_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
bitfld.long 0x4 2. "TX_WAKEUP_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
bitfld.long 0x4 1. "TX_RESPONSE_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
bitfld.long 0x4 0. "TX_HEADER_DONE,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)." "0,1"
line.long 0x8 "INTR_MASK,Interrupt mask"
bitfld.long 0x8 28. "RX_RESPONSE_CHECKSUM_ERROR,Mask for corresponding field in INTR register." "0,1"
bitfld.long 0x8 27. "RX_RESPONSE_FRAME_ERROR,Mask for corresponding field in INTR register." "0,1"
bitfld.long 0x8 26. "RX_HEADER_PARITY_ERROR,Mask for corresponding field in INTR register." "0,1"
bitfld.long 0x8 25. "RX_HEADER_SYNC_ERROR,Mask for corresponding field in INTR register." "0,1"
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bitfld.long 0x8 24. "RX_HEADER_FRAME_ERROR,Mask for corresponding field in INTR register." "0,1"
bitfld.long 0x8 17. "TX_RESPONSE_BIT_ERROR,Mask for corresponding field in INTR register." "0,1"
bitfld.long 0x8 16. "TX_HEADER_BIT_ERROR,Mask for corresponding field in INTR register." "0,1"
bitfld.long 0x8 14. "TIMEOUT,Mask for corresponding field in INTR register." "0,1"
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bitfld.long 0x8 13. "RX_NOISE_DETECT,Mask for corresponding field in INTR register." "0,1"
bitfld.long 0x8 11. "RX_HEADER_SYNC_DONE,Mask for corresponding field in INTR register." "0,1"
bitfld.long 0x8 10. "RX_BREAK_WAKEUP_DONE,Mask for corresponding field in INTR register." "0,1"
bitfld.long 0x8 9. "RX_RESPONSE_DONE,Mask for corresponding field in INTR register." "0,1"
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bitfld.long 0x8 8. "RX_HEADER_DONE,Mask for corresponding field in INTR register." "0,1"
bitfld.long 0x8 2. "TX_WAKEUP_DONE,Mask for corresponding field in INTR register." "0,1"
bitfld.long 0x8 1. "TX_RESPONSE_DONE,Mask for corresponding field in INTR register." "0,1"
bitfld.long 0x8 0. "TX_HEADER_DONE,Mask for corresponding field in INTR register." "0,1"
rgroup.long ($2+0xCC)++0x3
line.long 0x0 "INTR_MASKED,Interrupt masked"
bitfld.long 0x0 28. "RX_RESPONSE_CHECKSUM_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
bitfld.long 0x0 27. "RX_RESPONSE_FRAME_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
bitfld.long 0x0 26. "RX_HEADER_PARITY_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
bitfld.long 0x0 25. "RX_HEADER_SYNC_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
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bitfld.long 0x0 24. "RX_HEADER_FRAME_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
bitfld.long 0x0 17. "TX_RESPONSE_BIT_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
bitfld.long 0x0 16. "TX_HEADER_BIT_ERROR,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
bitfld.long 0x0 14. "TIMEOUT,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
newline
bitfld.long 0x0 13. "RX_NOISE_DETECT,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
bitfld.long 0x0 11. "RX_HEADER_SYNC_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
bitfld.long 0x0 10. "RX_BREAK_WAKEUP_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
bitfld.long 0x0 9. "RX_RESPONSE_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
newline
bitfld.long 0x0 8. "RX_HEADER_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
bitfld.long 0x0 2. "TX_WAKEUP_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
bitfld.long 0x0 1. "TX_RESPONSE_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
bitfld.long 0x0 0. "TX_HEADER_DONE,Logical AND of corresponding INTR and INTR_MASK fields." "0,1"
tree.end
repeat.end
tree.end
tree "PACSS (Precision Analog Channel Subsystem)"
base ad:0x40300000
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40300000 ad:0x40310000 ad:0x40320000 ad:0x40330000)
tree "DCHAN[$1]"
base $2
group.long ($2)++0x37
line.long 0x0 "DCHAN_CTL,Digital Channel Control"
bitfld.long 0x0 31. "ENABLE,Enable Digital Channel" "0,1"
newline
bitfld.long 0x0 30. "SEC_EN,Secondary Channel Enable" "0: digital channel is configured as primary channel,1: digital channel is configured as secondary channel"
newline
hexmask.long.byte 0x0 4.--9. 1. "FIR_NUM_TAPS,FIR number of Taps."
newline
bitfld.long 0x0 2. "FIR_EN,FIR Enable" "0: Disabled,1: Enabled"
newline
bitfld.long 0x0 1. "PP_EN,Post Processor Enable" "0,1"
newline
bitfld.long 0x0 0. "AGC_GAIN_EN,AGC Gain Enable" "0: Digital channel uses gain values from dchan..,1: Digital channel uses gain values provided from AGC"
line.long 0x4 "SMP_CTL,Sample Control"
bitfld.long 0x4 30. "MOV_SUM,Moving Sum" "0: Off,1: When AVG_MODE is enabled"
newline
bitfld.long 0x4 28.--29. "AVG_MODE,N/A" "0,1,2,3"
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hexmask.long.byte 0x4 20.--27. 1. "CH_SEL_DLY,Channel Selection Delay. The value written to this field plus 1 is the number of DSM clock cycles that will be inserted after the virtual channel configuration is loaded and before the decimator is started. Ex: write 7 for 8 clock cycles."
newline
bitfld.long 0x4 19. "AAF_SHORT_R_EN,Automatically short the Anti-Aliasing Filter resistor during the channel selection delay. The expectation is that his will decrease the required settling time. Has no affect if BYPASS_AAF=1" "0,1"
newline
bitfld.long 0x4 18. "BYPASS_AAF,Bypass the Anti-Aliasing Filter" "0,1"
newline
hexmask.long.byte 0x4 12.--16. 1. "NEG_PIN_SEL,Negative Pin Select"
newline
hexmask.long.byte 0x4 4.--10. 1. "POS_PIN_SEL,Positive Pin Select ( Sequencer controlled)"
newline
bitfld.long 0x4 0. "ACHAN_SEL,Analog Channel Selection" "0: Analog Channel 0,1: Analog Channel 1"
line.long 0x8 "SMP_REF_CTL,Sample Reference Control"
bitfld.long 0x8 18. "RS_PULLUP_EN,Resistor Pull-up Enable" "0,1"
newline
bitfld.long 0x8 16.--17. "RS_PULLUP_SEL,Resistor Pull-up Select" "0: RSH[1] Pull-up Selected,1: RSH[0] Pull-up Selected,2: RSL[1] Pull-up Selected,3: RSL[0] Pull-up Selected"
newline
bitfld.long 0x8 8. "VREF_BUF_EN,VREF Buffer Enable" "0,1"
newline
bitfld.long 0x8 4.--5. "VREFL_SEL,VREFL selection" "0: VREFL,1: VSSA_SRSS,2: VSSA_KELVIN,3: VTS_RET"
newline
bitfld.long 0x8 0.--2. "VREFH_SEL,VREFH selection" "0: VREFH Direct (HPBGR),1: VREFH Buffered (HPBGR),2: VREF SRSS,3: VTS_REF,4: VDDA/4,5: VDDA/3,?,?"
line.long 0xC "DEC_CTL,Decimator Control"
hexmask.long.byte 0xC 28.--31. 1. "RR_SHIFTR,Rate Reducer Output Right Shift"
newline
hexmask.long.byte 0xC 24.--27. 1. "DEC_SHIFTR,Decimator Output Right Shift"
newline
hexmask.long.byte 0xC 20.--23. 1. "SHIFTL,Shift Left (Scaler)"
newline
hexmask.long.byte 0xC 12.--16. 1. "DR2,Decimation Ratio 2"
newline
bitfld.long 0xC 11. "SAT_EN,Saturation Enable" "0,1"
newline
hexmask.long.byte 0xC 4.--10. 1. "DR,Decimation Ratio"
newline
bitfld.long 0xC 3. "GCOR_EN,Gain Correction Enable" "0,1"
newline
bitfld.long 0xC 2. "OCOR_EN,Offset Correction Enable" "0,1"
newline
bitfld.long 0xC 1. "CONV_MODE,Conversion Mode" "0: Incremental,1: Continuous"
newline
bitfld.long 0xC 0. "SINC_MODE,Decimator Sinc Mode" "0: Sinc3,1: Sinc4"
line.long 0x10 "PP_CTL,Post Processing Control"
hexmask.long.byte 0x10 24.--31. 1. "RANGE_CNT_VAL,Range Detection Count Value"
newline
bitfld.long 0x10 20.--21. "RANGE_COND,Range Condition Select" "0: result < RANGE_LOW,1: RANGE_LOW <= result < RANGE_HIGH,2: RANGE_HIGH <= result,3: result < RANGE_LOW"
newline
bitfld.long 0x10 16.--17. "RANGE_DET_EN,N/A" "0,1,2,3"
newline
bitfld.long 0x10 8. "CLAMP,Clamp" "0: Disabled,1: Clamps Result Data to 24-bits"
newline
hexmask.long.byte 0x10 0.--3. 1. "PP_SHIFTR,Post Processor Right Shift"
line.long 0x14 "OFST_COR,Offset Correction register"
hexmask.long.byte 0x14 16.--19. 1. "OCOR_SCLR,Decimator Offset Correction Coefficient Scaler"
newline
hexmask.long.word 0x14 0.--15. 1. "OCOR,Decimator Offset Correction Coefficient"
line.long 0x18 "GAIN_COR,Gain Correction register"
hexmask.long.byte 0x18 16.--19. 1. "GVAL,Number of valid bits minus one in Gain Coefficient registers GCOR"
newline
hexmask.long.word 0x18 0.--15. 1. "GCOR,Decimator Gain Correction Coefficient"
line.long 0x1C "RANGE_LOW,Range Detect low value register."
hexmask.long 0x1C 0.--31. 1. "RANGE_LOW,Low threshold for range detect"
line.long 0x20 "RANGE_HIGH,Range detect high value register."
hexmask.long 0x20 0.--31. 1. "RANGE_HIGH,High threshold for range detect"
line.long 0x24 "PGA_GAIN_CTL,PGA Gain Control register"
bitfld.long 0x24 0.--2. "GAIN,PGA Gain setting of 1 2 4 8 16 32 are supported" "0: 1x,1: 2x,2: 4x,3: 8x,4: 16x,5: 32x,?,?"
line.long 0x28 "CAP_CFG0,Capacitor Configuration 0 register"
bitfld.long 0x28 28.--30. "RESCAP,N/A" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x28 20.--23. 1. "FCAP3,The third stage integrating capacitance"
newline
hexmask.long.byte 0x28 12.--15. 1. "FCAP2,The second state integrating capacitance"
newline
hexmask.long.byte 0x28 0.--6. 1. "FCAP1,binary weighted first stage integrating capacitance"
line.long 0x2C "CAP_CFG1,Capacitor Configuration 1 register"
bitfld.long 0x2C 24.--26. "IPCAP3,The third integrator's input sampling capacitance" "0: 50fF,1: 100fF,2: 150fF,3: 200fF,4: 250fF,5: 300fF,6: 350fF,7: 400fF"
newline
bitfld.long 0x2C 20.--22. "IPCAP2,The second integrators input sampling capacitance" "0: 50fF,1: 100fF,2: 150fF,3: 200fF,4: 250fF,5: 300fF,6: 350fF,7: 400fF"
newline
hexmask.long.byte 0x2C 8.--13. 1. "IPCAP1,Binary weighted first stage integrating capacitance"
newline
hexmask.long.byte 0x2C 0.--5. 1. "DACCAP,Binary weighted first stage DAC capacitance"
line.long 0x30 "CAP_CFG2,Capacitor Configuration 2 register"
hexmask.long.byte 0x30 20.--23. 1. "SUMCAPFB,The summer feedback capacitance"
newline
bitfld.long 0x30 16.--18. "SUMCAP3,The summer capacitance that lies on the feed-forward path from the third integrator output (0fF to 350fF in 50fF step)" "0: 50fF,1: 100fF,2: 150fF,3: 200fF,4: 250fF,5: 300fF,6: 350fF,7: 400fF"
newline
bitfld.long 0x30 12.--14. "SUMCAP2,The summer capacitance that lies on the feed-forward path from the second integrator output (0fF to 350 in 50fF steps)" "0: 50fF,1: 100fF,2: 150fF,3: 200fF,4: 250fF,5: 300fF,6: 350fF,7: 400fF"
newline
bitfld.long 0x30 8.--10. "SUMCAP1,The summer capacitance that lies on the feed-forward path from the first integrator output (0fF to 350f 50fF steps)" "0: 50fF,1: 100fF,2: 150fF,3: 200fF,4: 250fF,5: 300fF,6: 350fF,7: 400fF"
newline
hexmask.long.byte 0x30 0.--4. 1. "SUMCAPIN,The summer capacitance that lies on the path where the input signal is summed (50fF to 1.6pF in 50f steps)"
line.long 0x34 "ACC_THRESH,Accumulated Data Threshold"
hexmask.long 0x34 0.--31. 1. "ACC_THRESH,Accumulated Threshold"
rgroup.long ($2+0x40)++0x7
line.long 0x0 "RESULT,Channel result data register"
hexmask.long 0x0 0.--31. 1. "RESULT,Result Register (signed)"
line.long 0x4 "RESULT_TAG,Result Tag register"
hexmask.long.byte 0x4 20.--26. 1. "DATA_TYPE,Result Data Type"
newline
bitfld.long 0x4 16.--17. "DCH_ID,Digital Channel ID" "0,1,2,3"
newline
hexmask.long.byte 0x4 8.--13. 1. "SMP_COUNT,Sample Count"
newline
hexmask.long.byte 0x4 0.--6. 1. "RESULT_PARITY,Result Parity (ECC Parity)"
group.long ($2+0x48)++0x3
line.long 0x0 "ACC_RESULT,Channel Accumulated result data register"
hexmask.long 0x0 0.--31. 1. "ACC_RESULT,Accumulator Output result register. Write '0s' to clear. This register will only be updated if the post processor is enabled. This register must be manually cleared it is not cleared after ACC_THRESH_INTR."
group.long ($2+0x50)++0xB
line.long 0x0 "INTR,Interrupt request register"
bitfld.long 0x0 7. "RANGE_INTR,Range detect Interrupt: hardware sets this interrupt if the conversion result of that channel met the condition specified by the RANGE_LOW and RANGE_HIGH registers. Write with '1' to clear bit." "0,1"
newline
bitfld.long 0x0 6. "ACC_THRESH_INTR,Accumulated Threshold Interrupt: hardware sets this interrupt when the accumulated threshold value has been surpassed. Not implemented in Alpha TO" "0,1"
newline
bitfld.long 0x0 5. "SATURATE_INTR,Saturate Interrupt: hardware sets this interrupt if a conversion result is prevented from overflowing in either the decimator or the post processor when PP_CTL.SAT_EN=1. Write with '1' to clear bit. Not implemented in Alpha TO" "0,1"
newline
bitfld.long 0x0 4. "OVERLOAD_INTR,Overload Interrupt: hardware sets this interrupt for each channel if the modulator output is all zeros or all ones. This is an indication that the modulator is overloaded. Write with '1' to clear bit. Not implemented in Alpha TO" "0,1"
newline
bitfld.long 0x0 3. "HWT_COLLISION_INTR,Hardware Trigger Collision Interrupt 0: hardware sets this interrupt when the HW trigger signal is asserted while the DSM is BUSY. Raising this interrupt is delayed to when the scan caused by the HW trigger has been completed i.e. not.." "0: hardware sets this interrupt when the HW trigger..,?"
newline
bitfld.long 0x0 2. "FWT_COLLISION_INTR,Firmware Trigger Collision Interrupt 0: hardware sets this interrupt when FW_TRIGGER is asserted while the DSM is BUSY. Raising this interrupt is delayed to when the scan caused by the FW_TRIGGER has been completed i.e. not when the.." "0: hardware sets this interrupt when FW_TRIGGER is..,?"
newline
bitfld.long 0x0 1. "OVERFLOW_INTR,Overflow Interrupt: hardware sets this interrupt when it sets a new DATA_VAL_INTR while that bit was not yet cleared by the firmware. Write with '1' to clear bit. Not implemented in Alpha TO" "0,1"
newline
bitfld.long 0x0 0. "DATA_VAL_INTR,Data Valid Interrupt 0: hardware sets this interrupt after completing a scan of all the enabled channels. Write with '1' to clear bit." "0: hardware sets this interrupt after completing a..,?"
line.long 0x4 "INTR_SET,Interrupt set request register"
bitfld.long 0x4 7. "RANGE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "ACC_THRESH_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "OVERLOAD_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 3. "HWT_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "FWT_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "DATA_VAL_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_MASK,Interrupt mask register"
bitfld.long 0x8 7. "RANGE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "ACC_THRESH_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "SATURATE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "OVERLOAD_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "HWT_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "FWT_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "DATA_VAL_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long ($2+0x5C)++0x7
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
bitfld.long 0x0 7. "RANGE_MASKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "ACC_THRESH_MASKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "SATURATE_MASKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "OVERLOAD_MASKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "HWT_COLLISION_MASKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "FWT_COLLISION_MASKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "OVERFLOW_MASKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "DATA_VAL_MASKED,Logical and of corresponding request and mask bits." "0,1"
line.long 0x4 "STATUS,Status registesr"
bitfld.long 0x4 0. "OVERLOAD_CAUSE,To be read after OVERLOAD_INTR issues. If read returns 0 overload is due to all 0s. If read returns 1 overload is due to all 1s" "0,1"
tree "FCFG (FIR Configuration)"
base ad:0x40300100
group.long ($2)++0x3
line.long 0x0 "COEF,Coefficient Value"
hexmask.long.word 0x0 0.--15. 1. "COEF,FIR Coefficient Value"
group.long ($2+0x8)++0x3
line.long 0x0 "TAP,Tap Value"
hexmask.long 0x0 0.--31. 1. "TAP,Tap value Witten by hardware readable by software."
tree.end
tree.end
repeat.end
repeat 2. (list 0x0 0x1)(list ad:0x40340000 ad:0x40350000)
tree "ACHAN[$1]"
base $2
group.long ($2)++0x1B
line.long 0x0 "ACHAN_CTL,Analog Channel Control"
bitfld.long 0x0 31. "ENABLE,Analog Channel Enable" "0,1"
newline
bitfld.long 0x0 16.--17. "AAF_CUTOFF_FREQ,N/A" "0,1,2,3"
newline
bitfld.long 0x0 10. "VCM_BUF_EN,VCM Buffer Enable" "0,1"
newline
bitfld.long 0x0 9. "VDDA_RES_EN,VDDA Resistor Reference Enable" "0,1"
newline
bitfld.long 0x0 8. "VCCA_RES_EN,VCCA Resistor Reference Enable" "0,1"
newline
bitfld.long 0x0 3. "REF_EN,Reference Enable" "0,1"
newline
bitfld.long 0x0 2. "BUF_EN,Buffer Enable" "0,1"
newline
bitfld.long 0x0 1. "PGA_EN,Programmable Gain Amplifier Enable (also enables VNEG Pump)" "0,1"
newline
bitfld.long 0x0 0. "MOD_EN,Modulator Enable (also enables INMUX)" "0,1"
line.long 0x4 "TR_CTL,Trigger Control for Sequencer"
bitfld.long 0x4 7. "PEND_SEC_TR_EN,Secondary Trigger Enable (enables HW triggers)" "0,1"
newline
bitfld.long 0x4 6. "SYNC_SEC_TR,Synchronize Secondary Trigger" "0: bypass clock domain synchronization of the..,1: synchronize the trigger signal to the DSM clock.."
newline
bitfld.long 0x4 4.--5. "PEND_SEC_TR_SEL,Select for Trigger that pends secondary digital channels linked to this analog channel to convert on the next primary trigger." "0: select HW tr_start[0],1: select HW tr_start[1],2: select HW tr_start[2],3: select HW tr_start[3]"
newline
bitfld.long 0x4 3. "PRIM_TR_EN,Primary Trigger Enable (enables HW triggers)" "0,1"
newline
bitfld.long 0x4 2. "SYNC_PRIM_TR,Synchronize Primary Trigger" "0: bypass clock domain synchronization of the..,1: synchronize the trigger signal to the DSM clock.."
newline
bitfld.long 0x4 0.--1. "PRIM_TR_SEL,Select for Primary Trigger. Triggers starts conversion on all primary digital channels linked to this analog channel." "0: select HW tr_start[0],1: select HW tr_start[1],2: select HW tr_start[2],3: select HW tr_start[3]"
line.long 0x8 "CHOP_CTL,Chopping Control for Sequencer"
bitfld.long 0x8 31. "CHOP_RST_EN,N/A" "0,1"
newline
bitfld.long 0x8 30. "CIRCUIT_2ND_EN,2nd Stage Circuit Chopping Enable" "0,1"
newline
bitfld.long 0x8 28.--29. "CIRCUIT_CHOP,Circuit Chopping" "0: Off,1: Disconnect AAF,2: Disconnect AAF,3: Disconnect AAF"
newline
bitfld.long 0x8 24.--25. "CHOP_MODE,Chopping Mode" "0: OFF: Channel Chopping and Buffer Cross Chopping..,1: Channel Chopping Enabled,?,?"
newline
hexmask.long.byte 0x8 16.--23. 1. "DEC_BLANK_CNT,Decimator Blanking Count"
newline
hexmask.long.byte 0x8 8.--15. 1. "AAF_SHORT_R_CNT,Anti-Aliasing Filter Short Resistor Count"
newline
hexmask.long.byte 0x8 0.--3. 1. "SMP_CNT,Chopping Sample Count"
line.long 0xC "PGA_CTL,Programmable Gain Amplifier Control"
bitfld.long 0xC 10. "PGA_BW_BOOST_EN,TBD - Currently not used" "0,1"
newline
bitfld.long 0xC 9. "PGA_DYN_DIODE_BIAS,TBD - Currently not used" "0,1"
newline
bitfld.long 0xC 8. "PGA_OVERLAP_EN,PGA Overlap Enable" "0,1"
newline
bitfld.long 0xC 5. "PGA_IDAC_EN,IDAC Enable" "0,1"
newline
bitfld.long 0xC 4. "PGA_CHOP_EN,Chopping Enable" "0,1"
newline
bitfld.long 0xC 0.--1. "PGA_PWR_LEVELS,PGA Power Levels" "0,1,2,3"
line.long 0x10 "MOD_CTL,Modulator Control"
bitfld.long 0x10 27. "MOD_CHOP_EN,Modulator Chopping Enable" "0,1"
newline
bitfld.long 0x10 24.--26. "MOD_FCHOP,Modulator Chopping Clock Frequency Selection" "0: chopping frequency is Fclock/2,1: chopping frequency is Fclock/4,2: chopping frequency is Fclock/8,3: chopping frequency is Fclock/16,4: chopping frequency is Fclock/32,5: chopping frequency is Fclock/64,6: chopping frequency is Fclock/128,7: chopping frequency is Fclock/256"
newline
bitfld.long 0x10 12.--14. "POWER_SUM,The power control for the summer block" "0: 75 percent Power Mode,1: 81 percent Power Mode,2: 94 percent Power Mode,3: 100 percent Power Mode,4: 150 percent Power Mode,5: N/A,6: N/A,7: N/A"
newline
bitfld.long 0x10 8.--9. "POWER_COMP,The power control for the quantizer block" "0: 50 percent Power Mode,1: 75 percent Power Mode,2: 100 percent Power Mode,3: 200 percent Power Mode"
newline
bitfld.long 0x10 4.--6. "POWER2_3,The power control for the second and third integrator stages" "0: 75 percent Power Mode,1: 81 percent Power Mode,2: 94 percent Power Mode,3: 100 percent Power Mode,4: 150 percent Power Mode,5: 100 percent Power Mode,6: 100 percent Power Mode,7: 100 percent Power Mode"
newline
bitfld.long 0x10 0.--2. "POWER1,First stage Opamp power level control" "0: 10 percent Power Mode,1: 31 percent Power Mode,2: 44 percent Power Mode,3: 63 percent Power Mode,4: 75 percent Power Mode,5: 88 percent Power Mode,6: 100 percent Power Mode,7: 150 percent Power Mode"
line.long 0x14 "DPATH_CTL,Datapath Control"
bitfld.long 0x14 28. "FCLOCK_EN,Modulator Clock Enable (FCLOCK)" "0,1"
newline
bitfld.long 0x14 24.--25. "MX_DOUT,Select the DSM data routed to the dbg_io output:" "0: none,1: dbg_io[5:0] = {modrst,2: dbg_io[5:0] = {ovdcause,3: dbg_io[5:0] = {modrst"
newline
bitfld.long 0x14 22. "RESET3_EN,Allow third stage integrating capacitance to be reset. If enabled this reset is triggered by an overload detection" "0,1"
newline
bitfld.long 0x14 21. "RESET2_EN,Allow second stage integrating capacitance to be reset. If enabled this reset is triggered by an overload detection" "0,1"
newline
bitfld.long 0x14 20. "RESET1_EN,Allow first stage integrating capacitance to be reset. If enabled this reset is triggered by an overload detection" "0,1"
newline
bitfld.long 0x14 19. "BUF_PGA_CHOP_CLK_EN,Buffer and PGA Chopping Clock enable for Buffer and PGA" "0,1"
newline
bitfld.long 0x14 16.--18. "BUF_PGA_FCHOP,Chopping Clock Frequency selection for Buffer and PGA" "0: Fclock/2,1: Fclock/4,2: Fclock/8,3: Fclock/16,4: Fclock/32,5: Fclock/64,6: Fclock/128,7: Fclock/256"
newline
bitfld.long 0x14 14. "MX_DIN,Select the data source of the Decimcator intput :" "0: modulator data is selected as input to decimator,1: dbg_io[3:0] is selected as the input to the.."
newline
bitfld.long 0x14 13. "OD_EN,Overload Detect Enable" "0,1"
newline
hexmask.long.byte 0x14 8.--12. 1. "ODET_TH,Overload detection threshold. If the number of continuous 1s or 0s coming out of quantizer exceeds this number the overload detection flag is set"
newline
bitfld.long 0x14 2.--3. "NONOV,Non-Overlap delay of clock phases" "0: low,1: medium,2: high,3: very high"
newline
bitfld.long 0x14 0.--1. "QLEV,N/A" "0,1,2,3"
line.long 0x18 "BUF_CTL,Buffer Control"
bitfld.long 0x18 5. "BUF_IDAC_EN,Buffer IDAC enable" "0,1"
newline
bitfld.long 0x18 4. "BUF_CHOP_EN,Buffer chopping enable" "0,1"
newline
bitfld.long 0x18 0.--1. "BUF_PWR_LEVELS,Buffer Power Levels" "0,1,2,3"
group.long ($2+0x20)++0x1F
line.long 0x0 "PUMP_CTL,Pump Control"
bitfld.long 0x0 4.--5. "CLOCK_SEL,Negative Pump Clock selection" "0: pump clock sourced by clk_pump/2,1: pump clock sourced by clk_pump/1,?,?"
newline
bitfld.long 0x0 0.--1. "VNEG_PWR_MODE,Negative pump power mode (actually a trim for risk mitigation)" "0,1,2,3"
line.long 0x4 "REF_CTL,Reference Control"
bitfld.long 0x4 6. "VREF_QTZ_SEL,VREF_QTZ selection" "0: VREFH CDAC,1: VCCA_KELVIN"
newline
bitfld.long 0x4 4.--5. "VCM_SEL,N/A" "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "VCM_PWR,Power Control for the Voltage Common Mode Buffer for the Sigma Delta ADC" "0: VCM Buffer is operating in Low Power (18 uA) mode,1: VCM Buffer is operating in Medium Power (28 uA)..,2: VCM Buffer is operating in High Power (55 uA) mode,3: VCM Buffer is operating in Turbo Power (114 uA).."
newline
bitfld.long 0x4 0.--1. "VREF_PWR,Power control for the voltage reference buffer for the sigma delta ADC" "0: VREF Buffer is operating in Low Power (26 uA) mode,1: VREF Buffer is operating in Medium Power (32 uA)..,2: VREF Buffer is operating in High Power (118 uA)..,3: VREF Buffer is operating in Turbo Power (232 uA).."
line.long 0x8 "START,Start Conversion"
bitfld.long 0x8 8. "PEND_SEC,Pend Secondary Conversion (FW Trigger) A write of 1 to this bit pends a secondary conversion. This bit is cleared after the next primary conversion completes." "0,1"
newline
bitfld.long 0x8 0. "START_PRIM,Start Primary Conversion (FW Trigger) . A write of 1 to this bit starts a primary conversion. This bit is cleared once the conversion is started. A write of 1 while the sequencer is busy is ignored and the FWT_COLLISION interrupt is set for.." "0,1"
line.long 0xC "INMUX_CTL,INMUX Control"
bitfld.long 0xC 16. "DECODE_EN,Enables Decode Logic to close switches. This must be set to '1' allow usage of POS_PIN_SEL and NEG_PIN_SEL. If set to '0' all switches in the INMUX will be open. This register is only applicable when SWITCH_SQ_CTL.INMUX=0" "0,1"
newline
hexmask.long.byte 0xC 8.--12. 1. "NEG_PIN_SEL,Negative Pin Select"
newline
hexmask.long.byte 0xC 0.--6. 1. "POS_PIN_SEL,Positive Pin Select"
line.long 0x10 "DEM_CTL,Dynamic Element Matching Control"
bitfld.long 0x10 2. "DEM_EN,Enable DEM" "0,1"
newline
bitfld.long 0x10 1. "SCRAM1_EN,Enable Scrambler 1" "0,1"
newline
bitfld.long 0x10 0. "SCRAM0_EN,Enable Scrambler 0" "0,1"
line.long 0x14 "SWITCH,Firmware Switch Control"
bitfld.long 0x14 7. "AAF_SW4,Firmware control: 0=open 1=close AAF switch 4. Write with '1' to set bit. This switch can only be closed via this register if SWITCH_SQ_CTL.AAF=0" "0: open,1: close AAF switch 4"
newline
bitfld.long 0x14 6. "AAF_SW3,Firmware control: 0=open 1=close AAF switch 3. Write with '1' to set bit. This switch can only be closed via this register if SWITCH_SQ_CTL.AAF=0." "0: open,1: close AAF switch 3"
newline
bitfld.long 0x14 5. "AAF_SW2,Firmware control: 0=open 1=close AAF switch 2. Write with '1' to set bit. This switch can only be closed via this register if SWITCH_SQ_CTL.AAF=0" "0: open,1: close AAF switch 2"
newline
bitfld.long 0x14 4. "AAF_SW1,Firmware control: 0=open 1=close AAF switch 1. Write with '1' to set bit. This switch can only be closed via this register if SWITCH_SQ_CTL.AAF=0" "0: open,1: close AAF switch 1"
newline
bitfld.long 0x14 3. "INMUX_ABUSB_VMINUS,Firmware control: 0=open 1=close switch between VMINUS and AMUXBUSB. Write with '1' to set bit. This switch can be closed while the sequencer is controls the INMUX pin selection" "0: open,1: close switch between VMINUS and AMUXBUSB"
newline
bitfld.long 0x14 2. "INMUX_ABUSA_VMINUS,Firmware control: 0=open 1=close switch between VMINUS and AMUXBUSA output. Write with '1' to set bit. This switch can be closed while the sequencer is controls the INMUX pin selection" "0: open,1: close switch between VMINUS and AMUXBUSA output"
newline
bitfld.long 0x14 1. "INMUX_ABUSB_VPLUS,Firmware control: 0=open 1=close switch between VPLUS and AMUXBUSB. Write with '1' to set bit. This switch can be closed while the sequencer is controls the INMUX pin selection" "0: open,1: close switch between VPLUS and AMUXBUSB"
newline
bitfld.long 0x14 0. "INMUX_ABUSA_VPLUS,Firmware control: 0=open 1=close switch between VPLUS and AMUXBUSA output. Write with '1' to set bit. This switch can be closed while the sequencer is controls the INMUX pin selection" "0: open,1: close switch between VPLUS and AMUXBUSA output"
line.long 0x18 "SWITCH_CLEAR,Firmware Switch Control Clear"
bitfld.long 0x18 7. "AAF_SW4,Write '1' to clear corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x18 6. "AAF_SW3,Write '1' to clear corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x18 5. "AAF_SW2,Write '1' to clear corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x18 4. "AAF_SW1,Write '1' to clear corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x18 3. "INMUX_ABUSB_VMINUS,Write '1' to clear corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x18 2. "INMUX_ABUSA_VMINUS,Write '1' to clear corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x18 1. "INMUX_ABUSB_VPLUS,Write '1' to clear corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x18 0. "INMUX_ABUSA_VPLUS,Write '1' to clear corresponding bit in the SWITCH register" "0,1"
line.long 0x1C "SWITCH_SQ_CTL,Switch Sequencer Control"
bitfld.long 0x1C 4. "AAF,Allow sequencer control for the provided switches" "0,1"
newline
bitfld.long 0x1C 0. "INMUX,Allow sequencer control for the provided switches" "0,1"
rgroup.long ($2+0x40)++0x3
line.long 0x0 "SWITCH_STATUS,Switch Status"
bitfld.long 0x0 7. "AAF_SW4,switch status of corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x0 6. "AAF_SW3,switch status of corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x0 5. "AAF_SW2,switch status of corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x0 4. "AAF_SW1,switch status of corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x0 3. "INMUX_ABUSB_VMINUS,switch status of corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x0 2. "INMUX_ABUSA_VMINUS,switch status of corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x0 1. "INMUX_ABUSB_VPLUS,switch status of corresponding bit in the SWITCH register" "0,1"
newline
bitfld.long 0x0 0. "INMUX_ABUSA_VPLUS,switch status of corresponding bit in the SWITCH register" "0,1"
group.long ($2+0x44)++0x3
line.long 0x0 "DFT_CTL,DFT Control Register"
hexmask.long.byte 0x0 20.--24. 1. "SPARE_CTL,Spare MMIO Controls for analog"
newline
bitfld.long 0x0 19. "CHOP_PHASE_CTL,Circuit chopping phase control. Inverts circuit chopping phase" "0,1"
newline
bitfld.long 0x0 18. "RS1_PULLDOWN,RS1 Pull-down. Enables pull down on RSH1/RSL1 input pair for offset calibration." "0,1"
newline
bitfld.long 0x0 17. "RS0_PULLDOWN,RS0 Pull-down. Enables pull down on RSH0/RSL0 input pair for offset calibration." "0,1"
newline
bitfld.long 0x0 16. "FRC_ANA_EN_LOW,Force global analog enable low (enable_scanoff_hv) to test for any SA1 faults on the level-shifter enables." "0,1"
newline
bitfld.long 0x0 13. "VNEG_PMP_TEST_EN,Negative Pump Test Enable" "0,1"
newline
bitfld.long 0x0 12. "PGA_TEST_EN,PGA Test Mode" "0,1"
newline
bitfld.long 0x0 7. "MUX_EN,DFT MUX Enable" "0,1"
newline
bitfld.long 0x0 4.--6. "MUXB_SEL,DFT MUX Selection for AMUXBUSB" "0: dft_out = vcca_dsm_dft,1: dft_out = refout,2: dft_out = vref_qtz,3: dft_out = aaf_in_n,4: dft_out = iref_2p4u - current source of buffer..,5: dft_out = buffin_vminus,6: dft_out = buffin_vplus,7: dft_out = bufout_vminus"
newline
bitfld.long 0x0 0.--2. "MUXA_SEL,DFT MUX Selection for AMUXBUSA" "0: dft_out = vcca_dsm_dft_kelvin,1: dft_out = vcm,2: dft_out = vref_dac,3: dft_out = aaf_in_p,4: dft_out = iref_4p8u - current source of PGA top..,5: dft_out = buffin_vplus,6: dft_out = buffin_vminus,7: dft_out = bufout_vplus"
rgroup.long ($2+0x48)++0x3
line.long 0x0 "DFT_STATUS,DFT Status Register"
bitfld.long 0x0 0. "OBSVR_LS_OUT,Observation point of level-shifters output. Used for detection of SA1 faults on the level-shifter enables. The read back value of this register changes based on the configuration and trims of the ACHAN and PACSS_MMIO registers." "0,1"
group.long ($2+0xFF00)++0x23
line.long 0x0 "TRIM_PGA0_CTL,PGA Trim 0 (lock protected)"
hexmask.long.byte 0x0 0.--5. 1. "OFST_P,Offset Plus Trim"
line.long 0x4 "TRIM_PGA1_CTL,PGA Trim 1 (lock protected)"
hexmask.long.byte 0x4 0.--5. 1. "OFST_SLOPE_P,Offset Slope Plus Trim"
line.long 0x8 "TRIM_PGA2_CTL,PGA Trim 2 (lock protected)"
hexmask.long.byte 0x8 0.--5. 1. "OFST_M,Offset Minus Trim"
line.long 0xC "TRIM_PGA3_CTL,PGA Trim 3 (lock protected)"
hexmask.long.byte 0xC 0.--5. 1. "OFST_SLOPE_M,Offset Slope Minus Trim"
line.long 0x10 "TRIM_PGA4_CTL,PGA Trim 4 (lock protected)"
bitfld.long 0x10 0.--2. "CM,Common Mode (Output Range) Trim" "0,1,2,3,4,5,6,7"
line.long 0x14 "TRIM_BUF0_CTL,Buffer Trim 0 (lock protected)"
hexmask.long.byte 0x14 0.--5. 1. "OFST_P,Offset Plus Trim"
line.long 0x18 "TRIM_BUF1_CTL,Buffer Trim 1 (lock protected)"
hexmask.long.byte 0x18 0.--5. 1. "OFST_PTAT_P,Offset PTAT Plus Trim"
line.long 0x1C "TRIM_BUF2_CTL,Buffer Trim 2 (lock protected)"
hexmask.long.byte 0x1C 0.--5. 1. "OFST_M,Offset Minus Trim"
line.long 0x20 "TRIM_BUF3_CTL,Buffer Trim 3 (lock protected)"
hexmask.long.byte 0x20 0.--5. 1. "OFST_PTAT_M,Offset PTAT Minus Trim"
tree.end
repeat.end
tree "MMIO (PACSS Global MMIO)"
base ad:0x403F0000
group.long 0x0++0x13
line.long 0x0 "PACSS_CTL,Precision Analog Channel Control"
bitfld.long 0x0 31. "ENABLE,Global Enable" "0,1"
bitfld.long 0x0 8.--9. "HVDIVG_MUX_SEL,High Voltage Divider Ground Reference Mux Select" "0: Select VSSA,1: Select VSSA,2: Select RSH[0],3: Select RSL[0]"
newline
bitfld.long 0x0 7. "OCD1_EN,Over Current Detection 1 Enable" "0,1"
bitfld.long 0x0 6. "OCD0_EN,Over Current Detection 0 Enable" "0,1"
newline
bitfld.long 0x0 5. "VPOS_PMP_EN,Positive Pump Enable" "0,1"
bitfld.long 0x0 4. "HPBGR_EN,High Precision Bandgap Reference Enable" "0,1"
newline
bitfld.long 0x0 3. "AREF_EN,AREF Enable" "0,1"
bitfld.long 0x0 2. "TMPS_EN,Temperature Sensor Enable" "0,1"
newline
bitfld.long 0x0 1. "LDO_EN,Low Dropout Regulator Enable" "0,1"
bitfld.long 0x0 0. "AGC_EN,Auto-Gain Correction Enable" "0,1"
line.long 0x4 "AGC_CTL0,Auto-Gain Correction Control 0"
bitfld.long 0x4 28.--29. "FAST_DEC_SCLR,Fast Decimator Scaler" "0: FAST_DEC_RESULT = RESULT,1: FAST_DEC_RESULT = RESULT << 1,2: FAST_DEC_RESULT = RESULT << 2,3: FAST_DEC_RESULT = RESULT << 3"
hexmask.long.byte 0x4 24.--27. 1. "MAX_LVL,Maximum Gain level"
newline
hexmask.long.byte 0x4 20.--23. 1. "MIN_LVL,Minimum Gain Level"
hexmask.long.byte 0x4 16.--19. 1. "INIT_LVL,Initial Gain level"
newline
hexmask.long.byte 0x4 8.--15. 1. "HI_THRESH,High Threshold value"
hexmask.long.byte 0x4 0.--7. 1. "LO_THRESH,Low Threshold value"
line.long 0x8 "AGC_CTL1,Auto-Gain Correction Control 1"
hexmask.long.byte 0x8 24.--31. 1. "SCALER_BLANK_CNT,Scaler Blank Count"
hexmask.long.byte 0x8 16.--23. 1. "DEC_BLANK_CNT,Decimator Blank Count"
newline
hexmask.long.byte 0x8 8.--15. 1. "AAF_BLANK_CNT,AAF Blank Count"
bitfld.long 0x8 7. "AAF_BLANK_MODE,Anti-Aliasing Filter (AAF) Blanking Mode" "0: Short AAF resistor,1: Bypass AAF"
newline
hexmask.long.byte 0x8 0.--4. 1. "FAST_DR,Fast Decimator Decimation Ratio"
line.long 0xC "AGC_CTL2,Auto-Gain Correction Control 2"
hexmask.long.word 0xC 16.--31. 1. "LO_THRESH_CNT,Low Threshold Filter Counter"
bitfld.long 0xC 0. "LO_THRESH_FLT_MODE,Low Threshold Filter Mode" "0: counter mode,1: integrator mode"
line.long 0x10 "AGC_CTL3,Auto-Gain Correction Control 3"
hexmask.long.word 0x10 16.--31. 1. "HI_THRESH_CNT,High Threshold Filter Counter"
bitfld.long 0x10 0. "HI_THRESH_FLT_MODE,High Threshold Filter Mode" "0: counter mode,1: integrator mode"
group.long 0x20++0x7
line.long 0x0 "TMPS_CTL,Temperature Sensor Control"
bitfld.long 0x0 31. "VTEMP_RET_SEL,Connect VTEMP_RET pin to the vssa_kelvin of the BJTs and resistor." "0,1"
bitfld.long 0x0 30. "VTEMP_SEL,Connect VTEMP pin to vbe/vres output voltage." "0,1"
newline
bitfld.long 0x0 29. "VTEMP_SUP_SEL,Select external current source to bias the BJTs or Resistor." "0,1"
bitfld.long 0x0 28. "AMUXB_SEL,Select amuxbus_b to be connected to temp sensor vbe/vres output." "0,1"
newline
bitfld.long 0x0 27. "AMUXA_SEL,Select amuxbus_a as a current source for biasing BJTs or Resistor" "0,1"
bitfld.long 0x0 24.--25. "LOAD_MODE,N/A" "0,1,2,3"
newline
hexmask.long.word 0x0 12.--20. 1. "BIPOLAR_UNIT,Number of bipolar transistors between 0 (all switches open) and 9"
bitfld.long 0x0 11. "IREF_SEL,Temperature Sensor Current Reference Select" "0: selects AREF as current reference source,1: selects SRSS as current reference source"
newline
hexmask.long.word 0x0 0.--8. 1. "IREF_UNIT,Number of units between 0 (all switches open) and 9"
line.long 0x4 "VPOS_PUMP_CTL,Positive Pump Control"
bitfld.long 0x4 4.--5. "CLOCK_SEL,Positive Pump Clock selection" "0: pump clock sourced by clk_pump/2,1: pump clock sourced by clk_pump/1,?,?"
bitfld.long 0x4 3. "VPOS_BYPASS_EN,N/A" "0,1"
newline
bitfld.long 0x4 0.--2. "VPOS_PWR_MODE,N/A" "0,1,2,3,4,5,6,7"
group.long 0x30++0x3
line.long 0x0 "START,Start Conversion"
bitfld.long 0x0 8. "PEND_SEC,Pend Secondary Conversion (FW Trigger) A write of 1 to this bit pends a secondary conversion. This bit is cleared after the next primary conversion completes." "0,1"
bitfld.long 0x0 0. "START_PRIM,Start Primary Conversion (FW Trigger) . A write of 1 to this bit starts a primary conversion on both sequencers simultaneously. This bit is cleared once the conversion is started. A write of 1 while the sequencer(s) is busy is ignored and the.." "0,1"
group.long 0x40++0xB
line.long 0x0 "INTR,System Interrupt request register"
bitfld.long 0x0 9. "OCD1,Over Current Detection 1 Interrupt" "0,1"
bitfld.long 0x0 8. "OCD0,Over Current Detection 0 Interrupt" "0,1"
newline
bitfld.long 0x0 0. "AGC_GLVL_CHG,AGC Gain Level Change Interrupt" "0,1"
line.long 0x4 "INTR_SET,System Interrupt set request register"
bitfld.long 0x4 9. "OCD1_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
bitfld.long 0x4 8. "OCD0_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "AGC_GLVL_CHG_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_MASK,System Interrupt mask register"
bitfld.long 0x8 9. "OCD1_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
bitfld.long 0x8 8. "OCD0_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "AGC_GLVL_CHG_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0x4C++0x7
line.long 0x0 "INTR_MASKED,System Interrupt masked request register"
bitfld.long 0x0 9. "OCD1_MASKED,Logical and of corresponding request and mask bits." "0,1"
bitfld.long 0x0 8. "OCD0_MASKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "AGC_GLVL_CHG_MASKED,Logical and of corresponding request and mask bits." "0,1"
line.long 0x4 "INTR_CAUSE,Interrupt Cause Register"
bitfld.long 0x4 4. "PACSS_INT,System (PACSS_MMIO) Interrupt Pending" "0,1"
bitfld.long 0x4 3. "DCH3_INT,Digital Channel 3 Interrupt Pending" "0,1"
newline
bitfld.long 0x4 2. "DCH2_INT,Digital Channel 2 Interrupt Pending" "0,1"
bitfld.long 0x4 1. "DCH1_INT,Digital Channel 1 Interrupt Pending" "0,1"
newline
bitfld.long 0x4 0. "DCH0_INT,Digital Channel 0 Interrupt Pending" "0,1"
rgroup.long 0x60++0x7
line.long 0x0 "STATUS0,Status Register 0"
hexmask.long.word 0x0 8.--19. 1. "AGC_FAST_DEC_RESULT,AGC Fast Decimator Result"
hexmask.long.byte 0x0 4.--7. 1. "AGC_CURR_GLVL,AGC Current gain level"
newline
bitfld.long 0x0 0.--1. "SEQ_BUSY,Sequencer Busy bit per analog channel" "0,1,2,3"
line.long 0x4 "STATUS1,Status Register 1"
hexmask.long.word 0x4 16.--31. 1. "HI_THRESH_CNTR,Status of High threshold counter"
hexmask.long.word 0x4 0.--15. 1. "LO_THRESH_CNTR,Status of Low threshold counter"
repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9)(list ad:0x403F0100 ad:0x403F0110 ad:0x403F0120 ad:0x403F0130 ad:0x403F0140 ad:0x403F0150 ad:0x403F0160 ad:0x403F0170 ad:0x403F0180 ad:0x403F0190)
tree "GAINLVL_STRUCT[$1]"
base $2
group.long ($2)++0xF
line.long 0x0 "GAIN_CFG0,Gain configuration register 0"
hexmask.long.byte 0x0 24.--29. 1. "IPCAP1,Binary weighted first stage integrating capacitance"
hexmask.long.byte 0x0 16.--21. 1. "DACCAP,Binary weighted first stage DAC capacitance"
hexmask.long.byte 0x0 4.--7. 1. "SHIFT1,Value for left shift amount (see SHIFTL in DEC_CTL)"
bitfld.long 0x0 0.--2. "PGA_GAIN,Gain setting of 1 2 4 8 16 32 are supported" "0: 1x,1: 2x,2: 4x,3: 8x,4: 16x,5: 32x,?,?"
line.long 0x4 "GAIN_CFG1,Gain configuration register 1"
hexmask.long.byte 0x4 20.--23. 1. "SUMCAPFB,The summer feedback capacitance"
bitfld.long 0x4 16.--18. "SUMCAP3,The summer capacitance that lies on the feed-forward path from the third integrator output" "0: 50fF,1: 100fF,2: 150fF,3: 200fF,4: 250fF,5: 300fF,6: 350fF,7: 400fF"
bitfld.long 0x4 12.--14. "SUMCAP2,The summer capacitance that lies on the feed-forward path from the second integrator output" "0: 50fF,1: 100fF,2: 150fF,3: 200fF,4: 250fF,5: 300fF,6: 350fF,7: 400fF"
bitfld.long 0x4 8.--10. "SUMCAP1,The summer capacitance that lies on the feed-forward path from the first integrator output" "0: 50fF,1: 100fF,2: 150fF,3: 200fF,4: 250fF,5: 300fF,6: 350fF,7: 400fF"
hexmask.long.byte 0x4 0.--4. 1. "SUMCAPIN,The summer capacitance that lies on the path where the input signal is summed"
line.long 0x8 "OFST_COR,Offset Correction register"
hexmask.long.word 0x8 0.--15. 1. "OCOR,Decimator Offset Correction Coefficient"
line.long 0xC "GAIN_COR,Gain Correction register"
hexmask.long.word 0xC 0.--15. 1. "GCOR,Decimator Gain Correction Coefficient"
tree.end
repeat.end
base ad:0x403F0000
group.long 0x500++0x3
line.long 0x0 "HPBGR_CTL,High Precision Bandgap Reference Control"
bitfld.long 0x0 8.--10. "HPBGR_FCHOP,High Precision Bandgap Reference Chopping Clock Frequency selection" "0: Fclock/2,1: Fclock/4,2: Fclock/8,3: Fclock/16,4: Fclock/32,5: Fclock/64,6: Fclock/128,7: Fclock/256"
bitfld.long 0x0 4. "SEL_PHC,Buffer phase compensation option for external capacitor" "0: cap present,1: cap absent)"
newline
bitfld.long 0x0 2. "CHOP_POS,Chopping position select (0: normal phase 1: reverse phase. Applies to output buffer and BGR core; BGR core is also affected by CHOP_CLK_SEL). Only applies when CHOP_DIS=1." "0: normal phase,1: reverse phase"
bitfld.long 0x0 1. "CHOP_CLK_SEL,Bgr core chopping phase select input (0: normal phase 1: reverse phase)" "0: normal phase,1: reverse phase)"
newline
bitfld.long 0x0 0. "CHOP_EN,HPBGR Chopping Enable (1: enable 0: disable)" "0: disable),1: enable"
group.long 0x510++0x3
line.long 0x0 "HPBGR_DFT_CTL,High Precision Bandgap Reference DFT Control"
bitfld.long 0x0 0.--2. "ADFT_MODE,N/A" "0,1,2,3,4,5,6,7"
group.long 0x600++0x3
line.long 0x0 "AREF_CTL,Analog Reference Control"
bitfld.long 0x0 0. "LP_MODE,Low Power Mode" "0: Full power,1: No 2"
group.long 0x610++0x3
line.long 0x0 "AREF_DFT_CTL,Analog Reference DFT Control"
bitfld.long 0x0 20.--22. "AREF_SPARE,N/A" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 16. "DFT_OUT_SEL,ADFT output select (0: to amuxbusa 1: to amuxbusb)" "0: to amuxbusa,1: to amuxbusb)"
newline
bitfld.long 0x0 12.--13. "DFT_RSEL,DFT Resistor Select" "0: No resistor,?,?,?"
hexmask.long.byte 0x0 8.--11. 1. "DFT_CURR_SEL,Selects which single current from DFT_SOURCE type to send to ADFT. (0: first current 1: second current etc to max of available currents)"
newline
bitfld.long 0x0 4. "DFT_SUM,DFT outputs sum (0: Single currents to ADFT 1: Sum of all currents of type selected by DFT_SOURCE are sent to ADFT)" "0: Single currents to ADFT,1: Sum of all currents of type selected by.."
bitfld.long 0x0 0.--2. "DFT_SOURCE,N/A" "0,1,2,3,4,5,6,7"
repeat 2. (list 0x0 0x1)(list ad:0x403F0700 ad:0x403F0710)
tree "OCD_STRUCT[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "OCD_CTL,Over Current Detector Control"
bitfld.long 0x0 31. "OCD_EN,OCD Enable" "0,1"
bitfld.long 0x0 24.--25. "OCD_INPUT_SEL,OCD Input Selection" "0,1,2,3"
bitfld.long 0x0 16.--17. "OCD_CLOCK_SEL,OCD Clock Selection - TBD" "0,1,2,3"
hexmask.long.byte 0x0 8.--11. 1. "OCD_LEVEL,Differential voltage for overcurrent detection"
bitfld.long 0x0 4.--6. "OCD_FILT,Detection filter time elect" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0.--1. "OCD_POLARITY,Deglitch polarity select" "0,1,2,3"
group.long ($2+0x8)++0x7
line.long 0x0 "OCD_STATUS,Over Current Detector Status"
bitfld.long 0x0 5. "OCD_HELD,OCD comparator status latched until last clearing. Clear with write of '1'" "0,1"
rbitfld.long 0x0 4. "OCD_COMP,Status of OCD comparator" "0,1"
rbitfld.long 0x0 0. "OCD,Status of OCD" "0,1"
line.long 0x4 "OCD_DFT,Over Current Detector DFT Control"
hexmask.long.byte 0x4 8.--11. 1. "SPARE,OCD Spare controls"
bitfld.long 0x4 4.--5. "OCD_DDFT_SEL,OCD DDFT selection - details TBD" "0,1,2,3"
bitfld.long 0x4 0.--1. "OCD_ADFT_SEL,OCD ADFT selection - details TBD" "0,1,2,3"
tree.end
repeat.end
base ad:0x403F0000
group.long 0x800++0x3
line.long 0x0 "REG_PROT,Register Protection"
hexmask.long 0x0 0.--31. 1. "MAGIC,Setting this register to the value 0xf08169e7 unlocks access to Lock Protected Registers. These registers can not be written to unless this value has been written into this register. Writing a value OTHER than the magic key will disable access to.."
group.long 0x900++0x3
line.long 0x0 "PDFT_CTL,PACSS DFT Control"
bitfld.long 0x0 17. "VPOS_PMP_TEST_EN,Postive Pump Test Enable" "0,1"
bitfld.long 0x0 16. "LDO_BYPASS,N/A" "0,1"
newline
hexmask.long.byte 0x0 4.--7. 1. "DDFT1_MUX_SEL,N/A"
hexmask.long.byte 0x0 0.--3. 1. "DDFT0_MUX_SEL,N/A"
group.long 0xFF00++0x43
line.long 0x0 "TRIM_REGL0_CTL,Regulator (LDO) Trim 0 (lock protected)"
bitfld.long 0x0 4. "COARSE,Coarse Trim" "0,1"
bitfld.long 0x0 0.--2. "FINE,Fine Trim" "0,1,2,3,4,5,6,7"
line.long 0x4 "TRIM_HPBGR0_CTL,High Precision Bandgap Reference Trim Control 0 (lock protected)"
hexmask.long.byte 0x4 0.--7. 1. "VREF_OS,Offset trim for HPBGR 1.2V output"
line.long 0x8 "TRIM_HPBGR1_CTL,High Precision Bandgap Reference Trim Control 1 (lock protected)"
hexmask.long.byte 0x8 0.--6. 1. "VREF_TC,First order temp-co correction trim"
line.long 0xC "TRIM_HPBGR2_CTL,High Precision Bandgap Reference Trim Control 2 (lock protected)"
hexmask.long.byte 0xC 4.--7. 1. "VREF_NL2,High temperature second order temp-co correction trim"
hexmask.long.byte 0xC 0.--3. 1. "VREF_NL1,Low temperature second order temp-co correction trim"
line.long 0x10 "TRIM_HPBGR3_CTL,High Precision Bandgap Reference Trim Control 3 (lock protected)"
bitfld.long 0x10 7. "NL_COREC_DIS,Second order temp-co correction enable (0: correction 1: no correction)" "0: correction,1: no correction)"
hexmask.long.byte 0x10 0.--4. 1. "VREF_AMP,Chopping amplifier trim"
line.long 0x14 "TRIM_HPBGR4_CTL,High Precision Bandgap Reference Trim Control 4 (lock protected)"
bitfld.long 0x14 6.--7. "NL2GAIN,Non-linearity Gain Trim 2" "0,1,2,3"
bitfld.long 0x14 4.--5. "NL2TEMP,Non-linearity Temperature Trim 2" "0,1,2,3"
newline
bitfld.long 0x14 2.--3. "NL1GAIN,Non-linearity Gain Trim 1" "0,1,2,3"
bitfld.long 0x14 0.--1. "NL1TEMP,Non-linearity Temperature Trim 1" "0,1,2,3"
line.long 0x18 "TRIM_AREF0_CTL,Analog Reference Trim Control 0 (lock protected)"
hexmask.long.byte 0x18 0.--4. 1. "ICTAT,Trim for AREF CTAT currents"
line.long 0x1C "TRIM_AREF1_CTL,Analog Reference Trim Control 1 (lock protected)"
hexmask.long.byte 0x1C 0.--3. 1. "IPTAT_COARSE,Coarse Trim for AREF PTAT currents"
line.long 0x20 "TRIM_AREF2_CTL,Analog Reference Trim Control 2 (lock protected)"
hexmask.long.byte 0x20 0.--4. 1. "IPTAT_FINE,Fine Trim for AREF PTAT currents"
line.long 0x24 "TRIM_AREF3_CTL,Analog Reference Trim Control 3 (lock protected)"
bitfld.long 0x24 0.--2. "PTAT_DAC,Trim for AREF PTAT DAC" "0,1,2,3,4,5,6,7"
line.long 0x28 "TRIM_AREF4_CTL,Analog Reference Trim Control 4 (lock protected)"
hexmask.long.byte 0x28 0.--3. 1. "ZTAT_COARSE,Coarse Trim for AREF ZTAT"
line.long 0x2C "TRIM_AREF5_CTL,Analog Reference Trim Control 5 (lock protected)"
hexmask.long.byte 0x2C 0.--4. 1. "ZTAT_FINE,Fine Trim for AREF ZTAT"
line.long 0x30 "TRIM_AREF6_CTL,Analog Reference Trim Control 6 (lock protected)"
hexmask.long.byte 0x30 0.--3. 1. "CTAT_COARSE,Coarse Trim for AREF CTAT"
line.long 0x34 "TRIM_OCD00_CTL,Over Current Detector 0 Trim Control 0 (lock protected)"
hexmask.long.byte 0x34 0.--7. 1. "TRIM0,OCD Trim 0 (TBD) - TODO: Add to lock logic"
line.long 0x38 "TRIM_OCD01_CTL,Over Current Detector 0 Trim Control 1 (lock protected)"
hexmask.long.byte 0x38 0.--7. 1. "TRIM1,OCD Trim 1 (TBD) - TODO: Add to lock logic"
line.long 0x3C "TRIM_OCD10_CTL,Over Current Detector 1 Trim Control 0 (lock protected)"
hexmask.long.byte 0x3C 0.--7. 1. "TRIM0,OCD Trim 0 (TBD) - TODO: Add to lock logic"
line.long 0x40 "TRIM_OCD11_CTL,Over Current Detector 1 Trim Control 1 (lock protected)"
hexmask.long.byte 0x40 0.--7. 1. "TRIM1,OCD Trim 1 (TBD) - TODO: Add to lock logic"
tree.end
tree.end
tree "PERI (Peripheral Interconnect)"
base ad:0x40010000
group.long 0x0++0x3
line.long 0x0 "DIV_CMD,Divider command register"
bitfld.long 0x0 31. "ENABLE,Clock divider enable command (mutually exclusive with DISABLE). Typically SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled its integer and.." "0: Disable the divider using the DIV_CMD,1: Configure the divider's DIV_XXX_CTL register"
bitfld.long 0x0 30. "DISABLE,Clock divider disable command (mutually exlusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'." "0,1"
bitfld.long 0x0 14.--15. "PA_SEL_TYPE,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:" "0,1,2,3"
hexmask.long.byte 0x0 8.--13. 1. "PA_SEL_DIV,(PA_SEL_TYPE PA_SEL_DIV) pecifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other even when they are enabled.."
bitfld.long 0x0 6.--7. "SEL_TYPE,Specifies the divider type of the divider on which the command is performed:" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "SEL_DIV,(SEL_TYPE SEL_DIV) specifies the divider on which the command (DISABLE/ENABLE) is performed."
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x100)++0x3
line.long 0x0 "PCLK_CTL[$1],Programmable clock control register"
bitfld.long 0x0 6.--7. "SEL_TYPE,Specifies divider type:" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "SEL_DIV,Specifies one of the dividers of the divider type specified by SEL_TYPE."
repeat.end
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x200)++0x3
line.long 0x0 "DIV_8_CTL[$1],Divider control register (for 8.0 divider)"
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]. Note: this type of divider does NOT allow for a fractional division."
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
repeat.end
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x300)++0x3
line.long 0x0 "DIV_16_CTL[$1],Divider control register (for 16.0 divider)"
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: this type of divider does NOT allow for a fractional division."
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
repeat.end
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x400)++0x3
line.long 0x0 "DIV_16_5_CTL[$1],Divider control register (for 16.5 divider)"
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: combined with fractional division this divider type allows for a division in the range [1 65 536 31/32] in 1/32 increments."
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods."
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
repeat.end
repeat 63. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x500)++0x3
line.long 0x0 "DIV_24_5_CTL[$1],Divider control register (for 24.5 divider)"
hexmask.long.tbyte 0x0 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1 16 777 216]. Note: combined with fractional division this divider type allows for a division in the range [1 16 777 216 31/32] in 1/32 increments."
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods."
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
repeat.end
group.long 0x600++0x3
line.long 0x0 "TR_CTL,Trigger control register"
bitfld.long 0x0 31. "TR_ACT,SW sets this field to '1' by to activate (set to '1') a trigger as identified by TR_SEL and TR_OUT for TR_COUNT cycles. HW sets this field to '0' when the cycle counter is decremented to '0'. Note: a TR_COUNT value of 255 is a special case and.." "0,1"
bitfld.long 0x0 30. "TR_OUT,Specifies whether trigger activation is for a specific input or ouput trigger of the trigger multiplexer. Activation of a specific input trigger will result in activation of all output triggers that have the specific input trigger selected.." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "TR_COUNT,Amount of cycles a specific trigger is activated. During activation (TR_ACT is '1') HW decrements this field to '0' using a cycle counter. During activation SW should not modify this register field. A value of 255 is a special case: HW does.."
hexmask.long.byte 0x0 8.--11. 1. "TR_GROUP,Specifies the trigger group."
hexmask.long.byte 0x0 0.--6. 1. "TR_SEL,Specifies the activated trigger when TR_ACT is '1'. TR_OUT specifies whether the activated trigger is an input trigger or output trigger to the trigger multiplexer. During activation (TR_ACT is '1') SW should not modify this register field. If.."
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40012000 ad:0x40012200 ad:0x40012400 ad:0x40012600)
tree "TR_GROUP[$1]"
base $2
repeat 128. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "TR_OUT_CTL[$1],Trigger control register"
hexmask.long.byte 0x0 0.--6. 1. "SEL,Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default.."
repeat.end
tree.end
repeat.end
tree.end
tree "SCB (Serial Communication Block)"
base ad:0x40240000
group.long 0x0++0x3
line.long 0x0 "CTRL,Generic control register."
bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
newline
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
newline
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
newline
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
newline
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
newline
bitfld.long 0x0 11. "BYTE_MODE,Determines the number of bits per FIFO data element:" "0,1"
newline
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
newline
bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
newline
bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Generic status register."
bitfld.long 0x0 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states.." "0,1"
group.long 0x8++0x3
line.long 0x0 "CMD_RESP_CTRL,Command/response control register."
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
rgroup.long 0xC++0x3
line.long 0x0 "CMD_RESP_STATUS,Command/response status register."
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximim memory.."
group.long 0x20++0x3
line.long 0x0 "SPI_CTRL,SPI control register."
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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bitfld.long 0x0 26.--27. "SLAVE_SELECT,Selects one of the four outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconducturs submode. In master..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity. SSEL_POLARITY3 applies to the outgoing SPI slave select signal 3 (master mode)." "0,1"
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity. SSEL_POLARITY2 applies to the outgoing SPI slave select signal 2 (master mode)." "0,1"
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity. SSEL_POLARITY1 applies to the outgoing SPI slave select signal 1 (master mode)." "0,1"
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). only SPI_SELECT[0] is used in slave mode." "0,1"
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. Only used in SPI Motorola submode. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 2. "CPHA,Only applicable in SPI Motorola submode. Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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bitfld.long 0x0 0. "CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "SPI_STATUS,SPI status register."
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection (low active) is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
group.long 0x40++0xB
line.long 0x0 "UART_CTRL,UART control register."
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
line.long 0x4 "UART_TX_CTRL,UART transmitter control register."
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
line.long 0x8 "UART_RX_CTRL,UART receiver control register."
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame seperates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behaviour when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period. If STOP_BITS is '1' stop bits error detection is NOT performed. If.." "0,1,2,3,4,5,6,7"
rgroup.long 0x4C++0x3
line.long 0x0 "UART_RX_STATUS,UART receiver status register."
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
group.long 0x50++0x3
line.long 0x0 "UART_FLOW_CTRL,UART flow control register"
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
group.long 0x60++0x3
line.long 0x0 "I2C_CTRL,I2C control register."
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full. When '0' clock stretching is used instead (till the receiver FIFO is no longer full)." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
rgroup.long 0x64++0x3
line.long 0x0 "I2C_STATUS,I2C status register."
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
group.long 0x68++0xB
line.long 0x0 "I2C_M_CMD,I2C master command register."
bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
line.long 0x4 "I2C_S_CMD,I2C slave command register."
bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
line.long 0x8 "I2C_CFG,I2C configuration register."
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2. See s8i2cs BROS (001-59539) for more details on the trim bit values." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1. See s8i2cs BROS (001-59539) for more details on the trim bit values." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0. See s8i2cs BROS (001-59539) for more details on the trim bit values." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values. With s8iom0s8v1p2 I/Os trim bits should be programmed to 3 to suppress glitches below 50ns." "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter. See s8i2cs BROS (001-59539) for more details on the trim bit values." "0,1,2,3"
group.long 0x200++0x7
line.long 0x0 "TX_CTRL,Transmitter control register."
bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the amount of bits in a transmitted data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only valid.."
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control register."
bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
rgroup.long 0x208++0x3
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status register."
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
wgroup.long 0x240++0x3
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write register."
hexmask.long.word 0x0 0.--15. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
group.long 0x300++0x7
line.long 0x0 "RX_CTRL,Receiver control register."
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptability to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "DATA_WIDTH,Dataframe width. DATA_WIDTH + 1 is the expected amount of bits in received data frame. This number does not include start parity and stop bits. For UART mode the valid range is [3 8]. For SPI the valid range is [3 15]. For I2C the only.."
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control register."
bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
rgroup.long 0x308++0x3
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status register."
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
group.long 0x310++0x3
line.long 0x0 "RX_MATCH,Slave address and mask register."
hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
rgroup.long 0x340++0x7
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read register."
hexmask.long.word 0x0 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read register."
hexmask.long.word 0x4 0.--15. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.BYTE_MODE is '1' only DATA[7:0] are used."
rgroup.long 0xE00++0x3
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal register"
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
newline
bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
group.long 0xE80++0x3
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request register"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
group.long 0xE88++0x3
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask register"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xE8C++0x3
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked register"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xEC0++0x3
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request register"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
group.long 0xEC8++0x3
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask register"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xECC++0x3
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked register"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF00++0xB
line.long 0x0 "INTR_M,Master interrupt request register."
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent and the transmit FIFO and shift register are empty." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
line.long 0x4 "INTR_M_SET,Master interrupt set request register"
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_M_MASK,Master interrupt mask register."
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF0C++0x3
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request register"
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF40++0xB
line.long 0x0 "INTR_S,Slave interrupt request register."
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
newline
bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
newline
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
newline
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
newline
bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
newline
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
newline
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
line.long 0x4 "INTR_S_SET,Slave interrupt set request register."
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_S_MASK,Slave interrupt mask register."
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF4C++0x3
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request register"
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF80++0xB
line.long 0x0 "INTR_TX,Transmitter interrupt request register."
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is usefull when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set.." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO; i.e. EMPTY is '1'. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
newline
bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL." "0,1"
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request register"
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask register."
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF8C++0x3
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request register"
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
group.long 0xFC0++0xB
line.long 0x0 "INTR_RX,Receiver interrupt request register."
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
newline
bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.BYTE_MODE: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL." "0,1"
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request register."
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask register."
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xFCC++0x3
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request register"
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
tree.end
tree "SPCIF (System Performance Controller Interface)"
base ad:0x0
tree "SPCIF0"
base ad:0x40110000
group.long 0x0++0x3
line.long 0x0 "GEOMETRY,Flash/NVL geometry information"
bitfld.long 0x0 31. "DE_CPD_LP,0': SRAM busy wait loop has not been copied." "0,1"
hexmask.long.byte 0x0 24.--30. 1. "NVL,NVLatch size in Byte multiples (chip dependent):"
rbitfld.long 0x0 22.--23. "FLASH_ROW,Page size in 64 Byte multiples (chip dependent):" "0,1,2,3"
rbitfld.long 0x0 20.--21. "NUM_FLASH,Number of flash macros (chip dependent):" "0,1,2,3"
hexmask.long.byte 0x0 14.--19. 1. "SFLASH,Supervisory flash capacity in 256 Byte multiples (chip dependent). If multiple flash macros are present this field provides the supervisory flash capacity of all flash macros together:"
hexmask.long.word 0x0 0.--13. 1. "FLASH,Regular flash capacity in 256 Byte multiples (chip dependent). If multiple flash macros are present this field provides the flash capacity of all flash macros together:"
group.long 0x1C++0x3
line.long 0x0 "NVL_WR_DATA,NVL write data register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data to be written to NVLatch array"
wgroup.long 0x60++0x3
line.long 0x0 "FLASH_LOCK,Flash Lock Register"
hexmask.long 0x0 0.--31. 1. "KEY,Write Only register that locks/unlocks access to the FLASH MACRO_WE register by writing a key value to the register. The Key is the 32 bit value '0xF56B3A81'. When this specific bit pattern is written to the register write access to FLASH_MACRO_WE.."
group.long 0x64++0x3
line.long 0x0 "FLASH_MACRO_WE,Flash Macro Write Enable"
rbitfld.long 0x0 31. "LOCKED,When set indicates that write access to FLASH_MACRO_WE.MAC_WRITE_EN is blocked. The value of this bit toggles when the key value is written into FLASH_LOCK.KEY." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "MAC_WRITE_EN,Access control to Flash Macros Write Access. This is a bit mask where each bit controls Program/Erase Access to the corresponding Macro. When the bit is set to '1' then the Macro may be programmed/erased when the bit is set to '0' the.."
group.long 0x7F0++0xB
line.long 0x0 "INTR,SPCIF interrupt request register"
bitfld.long 0x0 0. "TIMER,Timer counter value reaches '0'. Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit." "0,1"
line.long 0x4 "INTR_SET,SPCIF interrupt set request register"
bitfld.long 0x4 0. "TIMER,Write INTR_SET field with '1' to set corresponding INTR field." "0,1"
line.long 0x8 "INTR_MASK,SPCIF interrupt mask register"
bitfld.long 0x8 0. "TIMER,Mask for corresponding field in INTR register." "0,1"
rgroup.long 0x7FC++0x3
line.long 0x0 "INTR_MASKED,SPCIF interrupt masked request register"
bitfld.long 0x0 0. "TIMER,Logical and of corresponding request and mask fields." "0,1"
tree.end
tree "SPCIF1"
base ad:0x40120000
group.long 0x0++0x3
line.long 0x0 "GEOMETRY,Flash/NVL geometry information"
bitfld.long 0x0 31. "DE_CPD_LP,0': SRAM busy wait loop has not been copied." "0,1"
hexmask.long.byte 0x0 24.--30. 1. "NVL,NVLatch size in Byte multiples (chip dependent):"
rbitfld.long 0x0 22.--23. "FLASH_ROW,Page size in 64 Byte multiples (chip dependent):" "0,1,2,3"
rbitfld.long 0x0 20.--21. "NUM_FLASH,Number of flash macros (chip dependent):" "0,1,2,3"
hexmask.long.byte 0x0 14.--19. 1. "SFLASH,Supervisory flash capacity in 256 Byte multiples (chip dependent). If multiple flash macros are present this field provides the supervisory flash capacity of all flash macros together:"
hexmask.long.word 0x0 0.--13. 1. "FLASH,Regular flash capacity in 256 Byte multiples (chip dependent). If multiple flash macros are present this field provides the flash capacity of all flash macros together:"
group.long 0x1C++0x3
line.long 0x0 "NVL_WR_DATA,NVL write data register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data to be written to NVLatch array"
wgroup.long 0x60++0x3
line.long 0x0 "FLASH_LOCK,Flash Lock Register"
hexmask.long 0x0 0.--31. 1. "KEY,Write Only register that locks/unlocks access to the FLASH MACRO_WE register by writing a key value to the register. The Key is the 32 bit value '0xF56B3A81'. When this specific bit pattern is written to the register write access to FLASH_MACRO_WE.."
group.long 0x64++0x3
line.long 0x0 "FLASH_MACRO_WE,Flash Macro Write Enable"
rbitfld.long 0x0 31. "LOCKED,When set indicates that write access to FLASH_MACRO_WE.MAC_WRITE_EN is blocked. The value of this bit toggles when the key value is written into FLASH_LOCK.KEY." "0,1"
hexmask.long.byte 0x0 0.--3. 1. "MAC_WRITE_EN,Access control to Flash Macros Write Access. This is a bit mask where each bit controls Program/Erase Access to the corresponding Macro. When the bit is set to '1' then the Macro may be programmed/erased when the bit is set to '0' the.."
group.long 0x7F0++0xB
line.long 0x0 "INTR,SPCIF interrupt request register"
bitfld.long 0x0 0. "TIMER,Timer counter value reaches '0'. Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit." "0,1"
line.long 0x4 "INTR_SET,SPCIF interrupt set request register"
bitfld.long 0x4 0. "TIMER,Write INTR_SET field with '1' to set corresponding INTR field." "0,1"
line.long 0x8 "INTR_MASK,SPCIF interrupt mask register"
bitfld.long 0x8 0. "TIMER,Mask for corresponding field in INTR register." "0,1"
rgroup.long 0x7FC++0x3
line.long 0x0 "INTR_MASKED,SPCIF interrupt masked request register"
bitfld.long 0x0 0. "TIMER,Logical and of corresponding request and mask fields." "0,1"
tree.end
tree.end
tree "SRSSHV (System Resources High Voltage Subsystem)"
base ad:0x40030000
group.long 0x0++0x7
line.long 0x0 "PWR_CONTROL,Power Mode Control (Lock Protected)"
bitfld.long 0x0 23. "EXT_VCCD,Always write 0 except as noted below." "0,1"
newline
rbitfld.long 0x0 18.--19. "SPARE,Spare AHB readback bits that are hooked to PWR_PWRSYS_TRIM1.SPARE_TRIM[1:0] through spare logic equivalent to bitwise inversion. Engineering only." "0,1,2,3"
newline
bitfld.long 0x0 17. "OVER_TEMP_THRESH,Over-temperature threshold." "0: TEMP_HIGH condition occurs between 120C and 125C,1: TEMP_HIGH condition occurs between 60C and 75C"
newline
bitfld.long 0x0 16. "OVER_TEMP_EN,Enables the die over temperature sensor. Must be enabled when using the TEMP_HIGH interrupt." "0,1"
newline
rbitfld.long 0x0 5. "LPM_READY,Indicates whether the low power mode regulator is ready to enter DEEPSLEEP mode." "0: If DEEPSLEEP mode is requested,1: Normal operation"
newline
rbitfld.long 0x0 4. "DEBUG_SESSION,Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)" "0: No debug session active,1: Debug session is active"
newline
hexmask.long.byte 0x0 0.--3. 1. "POWER_MODE,Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon."
line.long 0x4 "PWR_KEY_DELAY,Power System Key&Delay Register (Lock Protected)"
hexmask.long.word 0x4 0.--9. 1. "WAKEUP_HOLDOFF,Delay to wait for references to settle on wakeup from deepsleep. BOD is ignored and system does not resume until this delay expires. Note that the same delay on POR is hard-coded. The default assumes the output of the predivider is 48MHz.."
group.long 0x14++0x3
line.long 0x0 "TST_MODE,Test Mode Control Register"
bitfld.long 0x0 31. "TEST_MODE,0: Normal operation mode" "0: Normal operation mode,1: Test mode"
newline
rbitfld.long 0x0 30. "TEST_KEY_DFT_EN,This bit is set when a XRES test mode key is shifted in. It is the value of the test_key_dft_en signal. When this bit is set the BootROM will not yield execution to the FLASH image (same function as setting TEST_MODE bit below)." "0,1"
newline
bitfld.long 0x0 28. "BLOCK_ALT_XRES,Relevant only for parts that have the alternate XRES mechanism of overloading a GPIO pin temporarily as alternate XRES during test. When set this bit blocks the alternate XRES function such that the pin can be used for normal I/O or for.." "0,1"
newline
rbitfld.long 0x0 2. "SWD_CONNECTED,0: SWD not active" "0: SWD not active,1: SWD activated"
group.long 0x1C++0x3
line.long 0x0 "CLK_CAL_CNT1,Clock Calibration Counter 1"
rbitfld.long 0x0 31. "CAL_COUNTER_DONE,Status bit indicating that the internal counter #1 is finished counting and CLK_CAL_CNT2.COUNTER stopped counting up" "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "CAL_COUNTER1,Down-counter clocked on DFT output #0 (see CLK_DFT_SELECT). This register always reads as zero. Counting starts internally when this register is written with a nonzero value. CAL_COUNTER_DONE goes immediately low to indicate that the.."
rgroup.long 0x20++0x3
line.long 0x0 "CLK_CAL_CNT2,Clock Calibration Counter 2"
hexmask.long.word 0x0 0.--15. 1. "CAL_COUNTER2,Up-counter clocked on DFT output #1 (see CLK_DFT_SELECT). When CLK_CAL_CNT1.CAL_COUNTER_DONE==1 the counter is stopped and can be read by SW. Do not read this value unless CAL_COUNTER_DONE==1. The expected final value is related to the.."
group.long 0x28++0xF
line.long 0x0 "CLK_SELECT,Clock Select Register (Lock Protected)"
bitfld.long 0x0 8. "LFCLK_SEL,Low Frequency Clock Select. Selecting a clock source that is not enabled will result in undefined behavior. Writes to this field are ignored unless the WDT is unlocked using WDT_LOCK register. It takes about 3 cycles of the new selected.." "0: ILO - Internal Low Frequency Oscillator,1: PILO - Precision Internal Low Frequency Oscillator"
newline
bitfld.long 0x0 6.--7. "SYSCLK_DIV,Select clk_sys prescaler value." "0: clk_sys= clk_hf/1,1: clk_sys= clk_hf/2,2: clk_sys= clk_hf/4,3: clk_sys= clk_hf/8"
newline
bitfld.long 0x0 4.--5. "PUMP_SEL,Selects clock source for charge pump clock. This clock is not guaranteed to be glitch free when changing any of its sources or settings." "0: No clock connect to gnd,1: Use main IMO output,2: Use clk_hf (using selected source after..,?"
newline
bitfld.long 0x0 2.--3. "HFCLK_DIV,Selects clk_hf predivider value. It will take 3-4 clcok cycles to switch to the new predivder value" "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8"
newline
bitfld.long 0x0 0.--1. "HFCLK_SEL,Selects a source for clk_hf and dsi_in[0]. Note that not all products support all clock sources. Selecting a clock source that is not supported or enabled will result in undefined behavior. It takes about 3 cycles of the new selected clock.." "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator or PLL..,3: HPOSC - High Precision Oscillator"
line.long 0x4 "CLK_ILO_CONFIG,ILO Configuration (Lock Protected)"
bitfld.long 0x4 31. "ENABLE,Master enable for ILO oscillator. Clearing this bit will disable the ILO. Do not disable this clock if the CLK_LF uses it clock the source. Writes to this field are ignored when LFCLK_SEL is using this clock as the source and WDT is locked.." "0,1"
line.long 0x8 "CLK_IMO_CONFIG,IMO Configuration (Lock Protected)"
bitfld.long 0x8 31. "ENABLE,Master enable for IMO oscillator. Clearing this bit will disable the IMO. Don't do this if the system is running off it." "0,1"
line.long 0xC "CLK_DFT_SELECT,Clock DFT Mode Selection Register"
bitfld.long 0xC 14. "DFT_EDGE1,Edge sensitivity for in-line divider on output #1 (only relevant when DIV1>0)." "0: Use posedge for divider,1: Use negedge for divider"
newline
bitfld.long 0xC 12.--13. "DFT_DIV1,DFT Output Divide Down." "0: Direct Output,1: Divide by 2,2: Divide by 4,3: Divide by 8"
newline
hexmask.long.byte 0xC 8.--11. 1. "DFT_SEL1,Select signal for DFT output #1"
newline
bitfld.long 0xC 6. "DFT_EDGE0,Edge sensitivity for in-line divider on output #0 (only relevant when DIV0>0)." "0: Use posedge for divider,1: Use negedge for divider"
newline
bitfld.long 0xC 4.--5. "DFT_DIV0,DFT Output Divide Down." "0: Direct Output,1: Divide by 2,2: Divide by 4,3: Divide by 8"
newline
hexmask.long.byte 0xC 0.--3. 1. "DFT_SEL0,Select signal for DFT output #0"
rgroup.long 0x40++0x3
line.long 0x0 "SRSS_MASKED,SRSS Interrupt Masked Register"
bitfld.long 0x0 4. "CRWDT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "CLK_CAL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "LIFETIME_WAKEUP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "TEMP_HIGH,Logical and of corresponding request and mask bits." "0,1"
group.long 0x44++0xB
line.long 0x0 "SRSS_INTR,SRSS Interrupt Register"
bitfld.long 0x0 4. "CRWDT,Interrupt from CRWDT. This bit is set by the CRWDT when enabled by CRWDT_CONFIG." "0,1"
newline
bitfld.long 0x0 3. "CLK_CAL,Clock calibration counter is done. This field is reset during DEEPSLEEP mode." "0,1"
newline
bitfld.long 0x0 2. "LIFETIME_WAKEUP,Wakeup Interrupt from LIFETIME Counter. This bit is set when LIFETIME_COUNTER ==LIFETIME_WAKEUP. This is a DeepSleep Interrupt. The interupt souce will reset only with hard reset (power releated XRES WDT)." "0,1"
newline
bitfld.long 0x0 1. "TEMP_HIGH,Regulator over-temp interrupt. This interrupt can occur when a short circuit exists on the vccd pin or when extreme loads are applied on IO-cells causing the die to overheat. Firmware is encourage to shutdown all IO cells and then go to.." "0,1"
line.long 0x4 "SRSS_INTR_SET,SRSS Interrupt Set Register"
bitfld.long 0x4 4. "CRWDT,Set interrupt for Challgne/Response Interrupt. Reads back same as SRSS_INTR.CRWDT." "0,1"
newline
bitfld.long 0x4 3. "CLK_CAL,Set interrupt for clock calibration counter done. This field is reset during DEEPSLEEP mode. Reads back same as SRSS_INTR.CLK_CAL." "0,1"
newline
bitfld.long 0x4 2. "LIFETIME_WAKEUP,Writing 1 to this bit internally sets the LIFETIME_WAKEUP interrupt. Reads back same as SRSS_INTR.LIFETIME_WAKEUP. The interupt souce will reset only with hard reset (power releated XRES WDT)." "0,1"
newline
bitfld.long 0x4 1. "TEMP_HIGH,Writing 1 to this bit internally sets the overtemp interrupt. This can be observed by reading SRSS_INTR.TEMP_HIGH. This bit always reads back as zero." "0,1"
line.long 0x8 "SRSS_INTR_MASK,SRSS Interrupt Mask Register"
bitfld.long 0x8 4. "CRWDT,Mask for CRWDT interrupt" "0,1"
newline
bitfld.long 0x8 3. "CLK_CAL,Mask for clock calibration done" "0,1"
newline
bitfld.long 0x8 2. "LIFETIME_WAKEUP,Mask for lifetimecounter" "0,1"
newline
bitfld.long 0x8 1. "TEMP_HIGH,Masks REG_OVERTEMP interrupt" "0,1"
group.long 0x54++0x3
line.long 0x0 "RES_CAUSE,Reset Cause Observation Register"
bitfld.long 0x0 30. "RESET_PORVDDD,Indicator that a POR occurred. This is a high-voltage cause bit and hardware clears the other bits when this one is set. It does not block further recording of other high-voltage causes." "0,1"
newline
bitfld.long 0x0 24. "RESET_BODHVSS,External VDDD supply crossed brown-out limit. Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit. Below this limit it is not possible to reliably retain.." "0,1"
newline
bitfld.long 0x0 22. "RESET_OVDVCCD,Overvoltage detection on the internal core VCCD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD and RESET_XRES. Hardware clears this bit during POR." "0,1"
newline
bitfld.long 0x0 20. "RESET_OVDVDDD,Overvoltage detection on the external VDDD supply. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD and RESET_XRES. Hardware clears this bit during POR." "0,1"
newline
bitfld.long 0x0 19. "RESET_BODVCCD,Internal VCCD core supply crossed the brown-out limit. Note that this detector will detect gross issues with the internal core supply but may not catch all brown-out conditions. Functional and timing supervision (CSV WDT) is provided to.." "0,1"
newline
bitfld.long 0x0 17. "RESET_BODVDDD,External VDDD supply crossed brown-out limit. Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit. Below this limit it is not possible to reliably retain.." "0,1"
newline
bitfld.long 0x0 16. "RESET_XRES,External XRES pin was asserted. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits." "0,1"
newline
bitfld.long 0x0 9. "RESET_CRWDT,Challenge/Response Watchdog reset. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
newline
bitfld.long 0x0 4. "RESET_SOFT,Cortex-M0 requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware." "0,1"
newline
bitfld.long 0x0 3. "RESET_PROT_FAULT,A protection violation occurred that requires a RESET. This includes but is not limited to hitting a debug breakpoint while in Privileged Mode." "0,1"
newline
bitfld.long 0x0 1. "RESET_ACT_FAULT,Reset caused by the Fault Infrastructure. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above)." "0,1"
newline
bitfld.long 0x0 0. "RESET_WDT,A WatchDog Timer reset has occurred since last power cycle." "0,1"
group.long 0x80++0x3
line.long 0x0 "REG_PROT,Register Protection"
hexmask.long 0x0 0.--31. 1. "MAGIC,Setting this register to the value 0xf08169e7 unlocks access to Lock Protected Registers. These registers can not be written to unless this value has been written into this register. Writing a value OTHER than the magic key will disable access to.."
group.long 0x90++0x3
line.long 0x0 "CRWDT_CTL,Challenge Response WatchDog Control (Lock Protected)"
bitfld.long 0x0 31. "ENABLED,When set to '1' enables Challenge/Response WatchDog Timer to Count. Will require 2 clk_lf cycles to take effect." "0,1"
newline
rbitfld.long 0x0 30. "STATUS_ENABLED,Indicates actual state of CRWDT enable. May lag ENABLED by up to one clk_lf cycles." "0,1"
rgroup.long 0x94++0x3
line.long 0x0 "CRWDT_CHALLENGE,Challenge Response WatchDog Challenge Value"
hexmask.long.byte 0x0 0.--7. 1. "CHALLENGE,Challenge/Response WatchDog Challenge value. Implements the LFSR CCRC8-AutoSar usiing the polynomial x^8+x^5+x^3+x^2+x+1. The next value in the LFSR sequence is used to compare against the value subsequently written to the CRWDT_RESPONSE.."
group.long 0x98++0x3
line.long 0x0 "CRWDT_RESPONSE,Challenge Response WatchDog Response Value"
hexmask.long.byte 0x0 0.--7. 1. "RESPONSE,Challenge/Response WatchDog Response value. Value is compared against the expected next value in the LFSR sequence following the value obtained from CRWDT_CHALLENGE. If the values match the CRWDT_UPCNT resets. If the values miscompare the.."
rgroup.long 0x9C++0x3
line.long 0x0 "CRWDT_UPCNT,Challenge Response WatchDog Up Counter"
hexmask.long.tbyte 0x0 0.--23. 1. "UPCNT,Challenge/Response WatchDog Up Counter. The counter upcounts upon every clk_lf occurence when enabled. If a match occurs between CRWDT_CHALLENGE and CRWDT_RESPONSE the counter resets. If there is a mismatch the action is taken selected by.."
group.long 0xA0++0x1B
line.long 0x0 "CRWDT_EARLY,Challenge Response WatchDog Early Limit (Lock Protected)"
hexmask.long.tbyte 0x0 0.--23. 1. "EARLY,Challenge/Response Early Value will cause the action selected by CRWDT_CONFIG.EARLY_ACTION if CRWDT_UPCNT < CRWDT_EARLY and there is a CRWDT_CHALLENGE/CRWDT_RESPONSE match."
line.long 0x4 "CRWDT_WARN,Challenge Response WatchDog Warning Limit (Lock Protected)"
hexmask.long.tbyte 0x4 0.--23. 1. "WARNING,Challenge/Response Warning Value will cause the action selected by CRWDT_CONFIGWARN_ACTION if CRWDT_UPCNT>CRWDT_WARN and there is a CRWDT_CHALLENGE/CRWDT_RESPONSE match."
line.long 0x8 "CRWDT_LATE,Challenge Response WatchDog Late Limit (Lock Protected)"
hexmask.long.tbyte 0x8 0.--23. 1. "LATE,Challenge/Response Late Value will cause action selected by CRWDT_CONFIG.LATE_ACTION if CRWDT_UPCNT = CRWDT_LATE."
line.long 0xC "CRWDT_CONFIG,Challenge Response WatchDog Configuration"
bitfld.long 0xC 31. "DEBUG_RUN,Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging including service configuration updates and enable/disable. Note it may take up to two clk_lf cycles for the counter to pause and another.." "0: When debugger connected,1: When debugger connected"
newline
bitfld.long 0xC 11. "CHALLENGE_FAIL_ACTION,Action taken when a failed resonse occurs i.e. the expected LFSR value is different than the expected value." "0: Do nothing,1: Trigger a reset"
newline
bitfld.long 0xC 8. "WARN_ACTION,Action taken if this watchdog when the proper response is written to CRWDT_RESPONSE and CRWDT_UPCNT reaches CRWDT_WARN and CRWDT_UPCNT<CRWDT_LATE. WARN_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected." "0: Do nothing,1: Trigger a Fault and interrupt"
newline
bitfld.long 0xC 4. "LATE_ACTION,Action taken if this watchdog is not serviced before CRWDT_LATE s reached. The counter resets CRWDT_UPCNT when CRWDT_LATE is reached regardless of CRWDT_CONFIG.LATE_ACTION setting. LATE_ACTION is ignored (i.e. treated as NOTHING) when a.." "0: Do nothing,1: Trigger a fault. Further trigger a system-wide.."
newline
bitfld.long 0xC 0. "EARLY_ACTION,Action taken if this watchdog when the proper response is written to CRWDT_RESPONSE before CRWDT_UPCNT reaches CRWDT_EARLY. EARLY_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected." "0: Do nothing,1: Trigger a Fault and interrupt"
line.long 0x10 "LIFETIME_CTL,Liftetime Counter Control (Lock Protected)"
bitfld.long 0x10 31. "ENABLED,When set to '1' enables LIFETIME_COUNTER to increment. Due to internal synchronization may take up to one clk_lf cycles to take effect. The synchronization can be checked by waiting until ENABLED==STATUS_ENABLED whenever ENABLED is changed." "0,1"
newline
rbitfld.long 0x10 30. "STATUS_ENABLED,Indicates actual state of lifetime counter enable. May lag ENABLED by up to one clk_lf cycles." "0,1"
newline
bitfld.long 0x10 0.--2. "PRESEL,Select Divide ratio for Preselector. Legal values are 0-4. Values 5 6 and 7 yield the same result as PERSEL_DIV32. Do not change this setting when lifetime counter is enabled (LIFETIME_CTL.ENABLED=1). Due to internal synchronization it takes.." "0: Divide CLK_LF by 2,1: Divide CLK_LF by 4,2: Divide CLK_LF by 8,3: Divide CLK_LF by 16,4: Divide CLK_LF by 32,?,?,?"
line.long 0x14 "LIFETIME_WAKEUP,Lifetime Wakeup Value"
hexmask.long 0x14 0.--31. 1. "WAKEUP,Compare the WAKEUP value against LIFETIME_COUNTER. If they are equal interrupt_wakeup to set. Due to internal synchronization it may take up to 1 LFCLK cycles to update the counters after a write to this register. This register bit only resets.."
line.long 0x18 "LIFETIME_COUNTER,Lifetime Counter Current Value"
hexmask.long 0x18 0.--31. 1. "COUNT,Lifetime Counter which clocks on the output of the CLK_LF PreScalar output controlled by LIFETIME_CTL.PRESEL. The counter doesn't increment unless LIFETIME_CTL.STATUS_ENABLED =1. FW is responsible for initializing this value after reset and.."
group.long 0xE0++0x3
line.long 0x0 "PWR_SSV_CTL,Supply Supervisory Control Register (Lock Protected)"
bitfld.long 0x0 31. "BODHVSS_ENABLE,Enable for BOD on vddd from HVSS. This gives BOD robustness during DeepSleep. FW should enable during boot-up and keep it enabled." "0,1"
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bitfld.long 0x0 27. "OVDVCCD_ENABLE,Enable for OVD on vccd. FW should enable this after the OVD trims are set during boot-up and keep it enabled." "0,1"
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bitfld.long 0x0 19. "OVDVDDD_ENABLE,Enable for OVD on vddd. FW should enable this after the OVD trims are set during boot-up and keep it enabled." "0,1"
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bitfld.long 0x0 11. "BODVCCD_ENABLE,Enable for BOD on vccd. This cannot be disabled during normal operation." "0,1"
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bitfld.long 0x0 3. "BODVDDD_ENABLE,Enable for BOD on vddd. This cannot be disabled during normal operation." "0,1"
rgroup.long 0xE4++0x3
line.long 0x0 "PWR_SSV_STATUS,Supply Supervision Status Register"
bitfld.long 0x0 12. "BODHVSS_OK,BODHVSS indicates vddd is ok. This will always read 1 because a detected brownout will reset the chip." "0,1"
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bitfld.long 0x0 10. "OVDVCCD_OK,OVD indicates vccd is ok. After OVDVCCD is enabled it will always read 1 because a detected over-over-voltage condition will reset the chip." "0,1"
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bitfld.long 0x0 8. "OVDVDDD_OK,OVD indicates vddd is ok. After OVDVDDD is enabled it will always read 1 because a detected over-voltage condition will reset the chip." "0,1"
newline
bitfld.long 0x0 2. "BODVCCD_OK,BOD indicates vccd is ok. This will always read 1 because a detected brownout will reset the chip." "0,1"
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bitfld.long 0x0 0. "BODVDDD_OK,BOD indicates vddd is ok. This will always read 1 because a detected brownout will reset the chip." "0,1"
tree "WDT (Watchdog Timer)"
base ad:0x40030100
group.long 0x0++0x17
line.long 0x0 "CTL,WDT Control Register"
bitfld.long 0x0 31. "ENABLE,Enable watchdog. May take up to three clk_lf cycles to take effect. When ENABLE changes from 1->0 the counter is cleared. Do not enter DEEPSLEEP if ENABLE<>ENABLED. This can be done by waiting until ENABLE==ENABLED whenever ENABLE is changed." "0: Counter is disabled,1: Counter is enabled"
rbitfld.long 0x0 0. "ENABLED,Indicates actual state of watchdog. May lag ENABLE by up to three clk_lf cycles." "0,1"
line.long 0x4 "LOWER_LIMIT,WDT Lower Limit Register"
hexmask.long 0x4 0.--31. 1. "LOWER_LIMIT,Lower limit for watchdog. See LOWER_ACTION."
line.long 0x8 "UPPER_LIMIT,WDT Upper Limit Register"
hexmask.long 0x8 0.--31. 1. "UPPER_LIMIT,Upper limit for watchdog. See UPPER_ACTION."
line.long 0xC "WARN_LIMIT,WDT Warn Limit Register"
hexmask.long 0xC 0.--31. 1. "WARN_LIMIT,Warn limit for watchdog. See WARN_ACTION."
line.long 0x10 "CONFIG,WDT Configuration Register"
bitfld.long 0x10 31. "DEBUG_RUN,Pauses/runs this counter while a debugger is connected. Other behaviors are unchanged during debugging including service configuration updates and enable/disable. Note it may take up to two clk_lf cycles for the counter to pause and another.." "0: When debugger connected,1: When debugger connected"
bitfld.long 0x10 29. "DPSLP_PAUSE,Pauses/runs this counter when the system is in DEEPSLEEP. Note it may take up to two clk_lf cycles for the counter to pause due to internal synchronization. During DEEPSLEEP wakeup the pause request is removed when clk_hf starts clocking .." "0: Counter behaves normally during DEEPSLEEP,1: Counter pauses during DEEPSLEEP"
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bitfld.long 0x10 28. "DEBUG_TRIGGER_EN,Enables the trigger input for WDT to pause the counter during debug mode. To pause at a breakpoint while debugging configure the trigger matrix to connect the related CPU halted signal to the trigger input for this WDT and then set.." "0: Pauses the counter whenever a debug probe is..,1: Pauses the counter whenever a debug probe is.."
bitfld.long 0x10 12. "AUTO_SERVICE,Automatically service when the count value reaches WARN_LIMIT. This allows creation of a periodic interrupt if this counter is not needed as a watchdog. This field is ignored when LOWER_ACTION<>NOTHING or when UPPER_ACTION<>NOTHING." "0,1"
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bitfld.long 0x10 8. "WARN_ACTION,Action taken when the count value reaches WARN_LIMIT. The minimum setting to achieve a periodic interrupt is WARN_LIMIT==1. A setting of zero will trigger once but not periodically." "0: Do nothing,1: Trigger an interrupt."
bitfld.long 0x10 4. "UPPER_ACTION,Action taken if this watchdog is not serviced before UPPER_LIMIT is reached. The counter stops counting when UPPER_LIMIT is reached regardless of UPPER_ACTION setting. UPPER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is.." "0: Do nothing,1: Trigger a reset."
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bitfld.long 0x10 0. "LOWER_ACTION,Action taken if this watchdog is serviced before LOWER_LIMIT is reached. LOWER_ACTION is ignored (i.e. treated as NOTHING) when a debugger is connected and/or when the chip is in DEEPSLEEP modes." "0: No action is triggered,1: The action is triggered on same edge when it.."
line.long 0x14 "CNT,WDT Count Register"
hexmask.long 0x14 0.--31. 1. "CNT,Current value of subcounter for this WDT. This field may lag the actual count value by up to one clk_lf cycle due to internal synchronization. When this subcounter is disabled and unlocked the count value can be written for verification and.."
group.long 0x40++0x7
line.long 0x0 "LOCK,WDT Lock register"
bitfld.long 0x0 0.--1. "WDT_LOCK,Prohibits writing control and configuration registers related to this WDT when not equal 0 (as specified in the other register descriptions). Requires at least two different writes to unlock." "0: No effect,1: Clears bit 0,2: Clears bit 1,3: Sets both bits 0 and 1"
line.long 0x4 "SERVICE,WDT Service register"
bitfld.long 0x4 0. "SERVICE,Services the watchdog. This resets the count value to zero. This may take up to three clk_lf cycle to take effect. Hardware clears this bit after necessary synchronization. To ensure a pending SERVICE write is reflected firmware should wait.." "0,1"
group.long 0x50++0xB
line.long 0x0 "INTR,WDT Interrupt Register"
bitfld.long 0x0 0. "WDT,WDT Interrupt Request. This bit is set as configured by WDT action and limits. Due to internal synchronization it takes up to 8 SYSCLK cycles to update after a W1C or reading this register and during this time AHB bus is stalled." "0,1"
line.long 0x4 "INTR_SET,WDT Interrupt Set Register"
bitfld.long 0x4 0. "WDT,Set interrupt." "0,1"
line.long 0x8 "INTR_MASK,WDT Interrupt Mask Register"
bitfld.long 0x8 0. "WDT,Mask for watchdog timer. Clearing this bit will not forward the interrupt to the CPU." "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "INTR_MASKED,WDT Interrupt Masked Register"
bitfld.long 0x0 0. "WDT,Logical and of corresponding request and mask bits." "0,1"
tree.end
base ad:0x40030000
group.long 0x300++0x3
newline
line.long 0x0 "HPOSC_CTL,High Precision Oscillator Control (Lock Protected)"
bitfld.long 0x0 31. "IMO_EN,HPOSC enable. Setting this bit will enable the HPOSC and clearing this bit will disable the HPOSC. Don't disable this clokc if the system is using this clock as the source." "0,1"
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bitfld.long 0x0 4. "CTAT_SWB,Selection control for internal CTAT generator." "0: Auto Select,1: Generator selected by CTAT_SEL"
newline
bitfld.long 0x0 1. "CTAT_SEL,CTAT generator selection only valid when CTAT_SW = 1." "0: Low noise type CTAT generator,1: Fast start-up type CTAT generator"
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bitfld.long 0x0 0. "LEAKC_DIS,N/A" "0,1"
group.long 0x400++0x3
line.long 0x0 "PILO_CTL,Precision Low Power Oscillator Control (Lock Protected)"
bitfld.long 0x0 31. "ILO_EN,PILO enable. Setting this bit will enable the PILO and clearing this bit will disable it. Do not disable this clock if the CLK_LF uses it clock the source. Writes to this field are ignored when LFCLK_SEL is using this clock as the source and.." "0,1"
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hexmask.long.byte 0x0 8.--15. 1. "TR_CAP,PILO user temperature fine trim. This register field resets with hard reset (power releated XRES WDT).."
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bitfld.long 0x0 4. "CTAT_SWB,Selection control for internal CTAT generator." "0: Auto Select,1: Generator selected by CTAT_SEL"
newline
bitfld.long 0x0 1. "CTAT_SEL,CTAT generator selection only valid when CTAT_SW = 1." "0: Low noise type CTAT generator,1: Fast start-up type CTAT generator"
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bitfld.long 0x0 0. "LEAKC_DIS,N/A" "0,1"
group.long 0xFF00++0x57
line.long 0x0 "PWR_BG_TRIM1,Bandgap Trim Register (Lock Protected)"
hexmask.long.byte 0x0 0.--5. 1. "REF_VTRIM,Trims the bandgap reference voltage output. Used to trim the VBG to the voltage where its temperature curvature is minimal. Bit [5] is unused within the bandgap block."
line.long 0x4 "PWR_BG_TRIM2,Bandgap Trim Register (Lock Protected)"
hexmask.long.byte 0x4 0.--5. 1. "REF_ITRIM,Trims the bandgap reference current output. Used to trim the IBG to the voltage where its temperature curvature is minimal."
line.long 0x8 "CLK_IMO_SELECT,IMO Frequency Select Register (Lock Protected)"
bitfld.long 0x8 0.--2. "FREQ,Select operating frequency" "0: IMO runs at 24 MHz,1: IMO runs at 28 MHz,2: IMO runs at 32 MHz,3: IMO runs at 36 MHz,4: IMO runs at 40 MHz,5: IMO runs at 44 MHz,6: IMO runs at 48 MHz,?"
line.long 0xC "CLK_IMO_TRIM1,IMO Trim Register (Lock Protected)"
hexmask.long.byte 0xC 0.--7. 1. "OFFSET,Frequency trim bits. These bits are determined at manufacturing time for each FREQ setting (IMO_TRIM2) and stored in SFLASH. This field is hardware updated during USB osclock mode. This field is mapped to the most significant bits of the IMO.."
line.long 0x10 "CLK_IMO_TRIM2,IMO Trim Register (Lock Protected)"
hexmask.long.byte 0x10 4.--7. 1. "TCTRIM,IMO temperature compesation trim. These bits are determined at manufacturing time to adjust for temperature dependence. This bits are dependent on frequency and need to be changed using the Cypress provided frequency change algorithm."
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bitfld.long 0x10 0.--2. "FSOFFSET,Frequency trim bits. These bits are not trimmed during manufacturing and kept at 0 under normal operation. This field is hardware updated during USB osclock mode. This field is mapped to the least significant bits of the IMO trim.." "0,1,2,3,4,5,6,7"
line.long 0x14 "CLK_IMO_TRIM3,IMO Trim Register (Lock Protected)"
hexmask.long.byte 0x14 0.--4. 1. "STEPSIZE,IMO trim stepsize bits. These bits are determined at manufacturing time to adjust for process variation. They are used to tune the stepsize of the FSOFFSET and OFFSET trims."
line.long 0x18 "PWR_PWRSYS_TRIM1,Power System Trim Register (Lock Protected)"
hexmask.long.byte 0x18 4.--7. 1. "SPARE_TRIM,Active-Reference temperature compensation trim (repurposed from spare bits)."
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hexmask.long.byte 0x18 0.--3. 1. "DPSLP_REF_TRIM,Trims the DeepSleep reference that is used by the DeepSleep regulator and DeepSleep power comparator."
line.long 0x1C "TRIM_BODVCCD,Brown Out Detect Trim (VCCD) (Lock Protected)"
bitfld.long 0x1C 4. "BOD_RANGE_SELECT_VCCD,Range select between 1.6V Vs 1.69V nominal." "0,1"
newline
hexmask.long.byte 0x1C 0.--3. 1. "BOD_TRIPSEL_VCCD,BOD VCCD trim (production)"
line.long 0x20 "TRIM_OVDVCCD,Over Voltage Detect Trim (VCCD) (Lock Protected)"
hexmask.long.byte 0x20 0.--3. 1. "OVD_TRIPSEL_VCCD,OVD VCCD trim (options)"
line.long 0x24 "TRIM_HPOSC0_CTL,High Precision Oscillator Trim Control 0 (Lock Protected)"
bitfld.long 0x24 6.--7. "PTATEC,Coarse trim for HPOSC PTAT current" "0,1,2,3"
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bitfld.long 0x24 4.--5. "CTATEC,Coarse trim for HPOSC CTAT current" "0,1,2,3"
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bitfld.long 0x24 2.--3. "PTATEF,Fine trim for HPOSC PTAT current" "0,1,2,3"
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bitfld.long 0x24 0.--1. "CTATEF,HPOSC frequency CTAT extra-fine trim" "0,1,2,3"
line.long 0x28 "TRIM_HPOSC1_CTL,High Precision Oscillator Trim Control 1 (Lock Protected)"
hexmask.long.byte 0x28 0.--4. 1. "TCF,HPOSC temp-co fine trim"
line.long 0x2C "TRIM_HPOSC2_CTL,High Precision Oscillator Trim Control 2 (Lock Protected)"
hexmask.long.byte 0x2C 0.--7. 1. "PTAT,HPOSC PTAT trim"
line.long 0x30 "TRIM_HPOSC3_CTL,High Precision Oscillator Trim Control 3 (Lock Protected)"
hexmask.long.byte 0x30 0.--7. 1. "CTAT,HPOSC CTAT trim"
line.long 0x34 "TRIM_HPOSC4_CTL,High Precision Oscillator Trim Control 4 (Lock Protected)"
hexmask.long.byte 0x34 3.--7. 1. "HPOSC_LEAK,HPOSC leakage cancellation trim"
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bitfld.long 0x34 0.--2. "TOC,HPOSC temp-co coarse trim" "0,1,2,3,4,5,6,7"
line.long 0x38 "TRIM_PILO0_CTL,Low Frequency Oscillator Trim Control 0 (Lock Protected)"
bitfld.long 0x38 6.--7. "PTATEC,PILO temperature PTATextra-coarse trim" "0,1,2,3"
newline
bitfld.long 0x38 4.--5. "CTATEC,PILO temperature CTAT extra-coarse trim" "0,1,2,3"
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bitfld.long 0x38 2.--3. "PTATEF,PILO frequency PTATextra-fine trim" "0,1,2,3"
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bitfld.long 0x38 0.--1. "CTATEF,PILO frequency CTAT extra-fine trim" "0,1,2,3"
line.long 0x3C "TRIM_PILO1_CTL,Low Frequency Oscillator Trim Control 1 (Lock Protected)"
hexmask.long.byte 0x3C 0.--4. 1. "TCF,PILO temp-co fine trim"
line.long 0x40 "TRIM_PILO2_CTL,Low Frequency Oscillator Trim Control 2 (Lock Protected)"
hexmask.long.byte 0x40 0.--7. 1. "PTAT,PILO frequency PTAT coarse trim"
line.long 0x44 "TRIM_PILO3_CTL,Low Frequency Oscillator Trim Control 3 (Lock Protected)"
hexmask.long.byte 0x44 0.--7. 1. "CTAT,PILO frequency CTAT coarse trim"
line.long 0x48 "TRIM_PILO4_CTL,Low Frequency Oscillator Trim Control 4 (Lock Protected)"
hexmask.long.byte 0x48 0.--3. 1. "TCC,PILO temperature coarse trim"
line.long 0x4C "TRIM_PILO5_CTL,Low Frequency Oscillator Trim Control 5 (Lock Protected)"
hexmask.long.byte 0x4C 0.--4. 1. "PILO_TR_LEAK,PILO leakage cancellation trim"
line.long 0x50 "TRIM_BODVDDD,Brown Out Detect Trim (VDDD) (Lock Protected)"
hexmask.long.byte 0x50 0.--3. 1. "BOD_TRIPSEL_VDDD,BOD VDDD trim (options)"
line.long 0x54 "TRIM_OVDVDDD,Over Voltage Detect Trim (VDDD) (Lock Protected)"
bitfld.long 0x54 4. "OVD_RANGE_SELECT_VDDD,Range select between 3.8V Vs 5.77V nominal." "0,1"
newline
hexmask.long.byte 0x54 0.--3. 1. "OVD_TRIPSEL_VDDD,OVD VDDD trim (options)"
tree.end
tree "TCPWM (Timer/Counter/PWM)"
base ad:0x40200000
group.long 0x0++0x3
line.long 0x0 "CTRL,TCPWM control register 0."
hexmask.long.byte 0x0 0.--7. 1. "COUNTER_ENABLED,Counter enables for counters 0 up to CNT_NR-1."
group.long 0x8++0x3
line.long 0x0 "CMD,TCPWM command register."
hexmask.long.byte 0x0 24.--31. 1. "COUNTER_START,Counters SW start trigger. For HW behavior see COUNTER_CAPTURE field."
hexmask.long.byte 0x0 16.--23. 1. "COUNTER_STOP,Counters SW stop trigger. For HW behavior see COUNTER_CAPTURE field."
hexmask.long.byte 0x0 8.--15. 1. "COUNTER_RELOAD,Counters SW reload trigger. For HW behavior see COUNTER_CAPTURE field."
hexmask.long.byte 0x0 0.--7. 1. "COUNTER_CAPTURE,Counters SW capture trigger. When written with '1' a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is.."
rgroup.long 0xC++0x3
line.long 0x0 "INTR_CAUSE,TCPWM Counter interrupt cause register."
hexmask.long.byte 0x0 0.--7. 1. "COUNTER_INT,Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED the associated interrupt field is immediately set to '0'."
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40200100 ad:0x40200140 ad:0x40200180 ad:0x402001C0)
tree "CNT[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CTRL,Counter control register"
bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,?,2: Capture mode,3: Quadrature encoding mode,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,?"
bitfld.long 0x0 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4)." "0: X1 encoding (QUAD mode),1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),?"
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
newline
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit control field. In PWM_DT mode this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes the lower 3 bits of this field determine pre-scaling of the selected counter.."
bitfld.long 0x0 3. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 2. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
bitfld.long 0x0 1. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM PWM_DT and PWM_PR modes." "0,1"
newline
bitfld.long 0x0 0. "AUTO_RELOAD_CC,Specifies switching of the CC and buffered CC values. This field has a function in TIMER PWM PWM_DT and PWM_PR modes." "0: never switch,?"
rgroup.long ($2+0x4)++0x3
line.long 0x0 "STATUS,Counter status register"
bitfld.long 0x0 31. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion. In all other modes this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality."
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
group.long ($2+0x8)++0x13
line.long 0x0 "COUNTER,Counter count register"
hexmask.long.word 0x0 0.--15. 1. "COUNTER,16-bit counter value. It is advised to not write to this field when the counter is running."
line.long 0x4 "CC,Counter compare/capture register"
hexmask.long.word 0x4 0.--15. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
line.long 0x8 "CC_BUFF,Counter buffered compare/capture register"
hexmask.long.word 0x8 0.--15. 1. "CC,Additional buffer for counter CC register."
line.long 0xC "PERIOD,Counter period register"
hexmask.long.word 0xC 0.--15. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
line.long 0x10 "PERIOD_BUFF,Counter buffered period register"
hexmask.long.word 0x10 0.--15. 1. "PERIOD,Additional buffer for counter PERIOD register."
group.long ($2+0x20)++0xB
line.long 0x0 "TR_CTRL0,Counter trigger control register 0"
hexmask.long.byte 0x0 16.--19. 1. "START_SEL,Selects one of the 16 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
hexmask.long.byte 0x0 12.--15. 1. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger. In PWM PWM_DT and PWM_PR modes this is the kill trigger. In these modes the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the.."
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hexmask.long.byte 0x0 8.--11. 1. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger. In QUAD mode this is the index or revolution pulse. In this mode it will update the counter with the value in the TCPWM_CNTn_PERIOD register."
hexmask.long.byte 0x0 4.--7. 1. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger. In QUAD mode this is the first phase (phi A). Default setting selects input trigger 1 which is always '1'."
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hexmask.long.byte 0x0 0.--3. 1. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. Input trigger 2 is the first external trigger line (tcpwm.tr_in[0])."
line.long 0x4 "TR_CTRL1,Counter trigger control register 1"
bitfld.long 0x4 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
bitfld.long 0x4 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
newline
bitfld.long 0x4 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
bitfld.long 0x4 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
newline
bitfld.long 0x4 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
line.long 0x8 "TR_CTRL2,Counter trigger control register 2"
bitfld.long 0x8 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
bitfld.long 0x8 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
newline
bitfld.long 0x8 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
group.long ($2+0x30)++0xB
line.long 0x0 "INTR,Interrupt request register."
bitfld.long 0x0 1. "CC_MATCH,Counter matches CC register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
line.long 0x4 "INTR_SET,Interrupt set request register."
bitfld.long 0x4 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_MASK,Interrupt mask register."
bitfld.long 0x8 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long ($2+0x3C)++0x3
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
bitfld.long 0x0 1. "CC_MATCH,Logical and of corresponding request and mask bits." "0,1"
bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
tree.end
repeat.end
tree.end
AUTOINDENT.OFF
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