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Gen4_R-Car_Trace32/2_Trunk/perpsoc4200.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: PSoC 4200 On-Chip Peripherals
; @Props: Released
; @Author: KWI, DAB
; @Changelog: 2019-02-05 KWI
; 2022-01-21 DAB
; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
; @Doc: CY8C4xxx.svd
; @Core: Cortex-M0
; @Chip: CY8C4244AXI-443, CY8C4244AXQ-443, CY8C4244AZI-443, CY8C4244FNI-443,
; CY8C4244LQI-443, CY8C4244LQQ-443, CY8C4244PVI-432, CY8C4244PVI-442,
; CY8C4244PVQ-432, CY8C4244PVQ-442, CY8C4245AXI-473, CY8C4245AXI-483,
; CY8C4245AXQ-473, CY8C4245AXQ-483, CY8C4245AZI-473, CY8C4245AZI-483,
; CY8C4245FNI-483, CY8C4245LQI-483, CY8C4245LQQ-483, CY8C4245PVI-482,
; CY8C4245PVQ-482
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perpsoc4200.per 14191 2022-01-27 13:52:46Z kwisniewski $
config 16. 8.
tree.close "Core Registers (Cortex-M0)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
tree "CLK (Programmable clocks)"
base ad:0x40020000
repeat 3. (strings "00" "01" "02" )(list 0x0 0x4 0x8 )
group.long ($2+0x00)++0x03
line.long 0x00 "DIVIDER_A$1,Clock Divider Configuration"
bitfld.long 0x00 31. "ENABLE_A,Enable divider A" "0,1"
hexmask.long.word 0x00 0.--15. 1. "DIVIDER_A,Divider value for divider A in the row"
repeat.end
repeat 3. (strings "00" "01" "02" )(list 0x0 0x4 0x8 )
group.long ($2+0x40)++0x03
line.long 0x00 "DIVIDER_B$1,Clock Divider Configuration"
bitfld.long 0x00 31. "ENABLE_B,Enable divider B" "0,1"
bitfld.long 0x00 30. "CASCADE_A_B,Cascade divider A into divider B" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "DIVIDER_B,Divider value for divider B in the row"
repeat.end
repeat 3. (strings "00" "01" "02" )(list 0x0 0x4 0x8 )
group.long ($2+0x80)++0x03
line.long 0x00 "DIVIDER_C$1,Clock Divider Configuration"
bitfld.long 0x00 31. "ENABLE_C,Enable divider C" "0,1"
bitfld.long 0x00 30. "CASCADE_B_C,Cascade divider B into divider C" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "DIVIDER_C,Divider value for divider C in the row"
repeat.end
group.long 0x100++0x03
line.long 0x00 "DIVIDER_FRAC_A00,Frac Divider Configuration"
bitfld.long 0x00 31. "ENABLE_A,Enable divider A" "0,1"
bitfld.long 0x00 16.--20. "FRAC_A,Fractional divider value: 0/32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 0.--15. 1. "DIVIDER_A,Divider value for divider A in the row"
group.long 0x140++0x03
line.long 0x00 "DIVIDER_FRAC_B00,Frac Divider Configuration"
bitfld.long 0x00 31. "ENABLE_B,Enable divider B" "0,1"
bitfld.long 0x00 30. "CASCADE_A_B,Cascade divider A into divider B" "0,1"
newline
bitfld.long 0x00 16.--20. "FRAC_B,Fractional divider value: 0/32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "DIVIDER_B,Divider value for divider B in the row"
group.long 0x180++0x03
line.long 0x00 "DIVIDER_FRAC_C00,Frac Divider Configuration"
bitfld.long 0x00 31. "ENABLE_C,Enable divider C" "0,1"
bitfld.long 0x00 30. "CASCADE_B_C,Cascade divider B into divider C" "0,1"
newline
bitfld.long 0x00 16.--20. "FRAC_C,Fractional divider value: 0/32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "DIVIDER_C,Divider value for divider C in the row"
repeat 16. (strings "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "SELECT$1,Clock Routing Configuration"
bitfld.long 0x00 4.--5. "DIVIDER_ABC,Select which divider from row to use" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 0.--3. "DIVIDER_N,Select divider bank row to source clock from" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
tree.end
tree "CM0 (Cortex-M0 System Bus (ARM PPB Peripherals))"
base ad:0xE0000000
group.long 0x1FD0++0x03
line.long 0x00 "DWT_PID4,Watchpoint Unit CoreSight ROM Table Peripheral ID #4"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #4"
group.long 0x1FE0++0x03
line.long 0x00 "DWT_PID0,Watchpoint Unit CoreSight ROM Table Peripheral ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #0"
group.long 0x1FE4++0x03
line.long 0x00 "DWT_PID1,Watchpoint Unit CoreSight ROM Table Peripheral ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #1"
group.long 0x1FE8++0x03
line.long 0x00 "DWT_PID2,Watchpoint Unit CoreSight ROM Table Peripheral ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #2"
group.long 0x1FEC++0x03
line.long 0x00 "DWT_PID3,Watchpoint Unit CoreSight ROM Table Peripheral ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #3"
group.long 0x1FF0++0x03
line.long 0x00 "DWT_CID0,Watchpoint Unit CoreSight ROM Table Component ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #0"
group.long 0x1FF4++0x03
line.long 0x00 "DWT_CID1,Watchpoint Unit CoreSight ROM Table Component ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #1"
group.long 0x1FF8++0x03
line.long 0x00 "DWT_CID2,Watchpoint Unit CoreSight ROM Table Component ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #2"
group.long 0x1FFC++0x03
line.long 0x00 "DWT_CID3,Watchpoint Unit CoreSight ROM Table Component ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #3"
group.long 0x2FD0++0x03
line.long 0x00 "BP_PID4,Breakpoint Unit CoreSight ROM Table Peripheral ID #4"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #4"
group.long 0x2FE0++0x03
line.long 0x00 "BP_PID0,Breakpoint Unit CoreSight ROM Table Peripheral ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #0"
group.long 0x2FE4++0x03
line.long 0x00 "BP_PID1,Breakpoint Unit CoreSight ROM Table Peripheral ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #1"
group.long 0x2FE8++0x03
line.long 0x00 "BP_PID2,Breakpoint Unit CoreSight ROM Table Peripheral ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #2"
group.long 0x2FEC++0x03
line.long 0x00 "BP_PID3,Breakpoint Unit CoreSight ROM Table Peripheral ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #3"
group.long 0x2FF0++0x03
line.long 0x00 "BP_CID0,Breakpoint Unit CoreSight ROM Table Component ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #0"
group.long 0x2FF4++0x03
line.long 0x00 "BP_CID1,Breakpoint Unit CoreSight ROM Table Component ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #1"
group.long 0x2FF8++0x03
line.long 0x00 "BP_CID2,Breakpoint Unit CoreSight ROM Table Component ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #2"
group.long 0x2FFC++0x03
line.long 0x00 "BP_CID3,Breakpoint Unit CoreSight ROM Table Component ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #3"
group.long 0xE010++0x03
line.long 0x00 "SYST_CSR,Systick Control & Status"
rbitfld.long 0x00 16. "COUNTFLAG,Indicates whether the counter has counted to 0 since the last read of this register:?0 timer has not counted to 0.?1 timer has counted to 0.?COUNTFLAG is set to 1 by a count transition from 1 to 0.?COUNTFLAG is cleared to 0 by a read of this.." "0,1"
bitfld.long 0x00 2. "CLKSOURCE,Indicates the SysTick clock source:?0 SysTick uses the optional external reference clock.?1 SysTick uses the processor clock.?If no external clock is provided this bit reads as one and ignores writes" "0,1"
newline
bitfld.long 0x00 1. "TICKINT,Indicates whether counting to 0 causes the status of the SysTick exception to change to pending:?0 count to 0 does not affect the SysTick exception status.?1 count to 0 changes the SysTick exception status to pending.?Changing the value of the.." "0,1"
bitfld.long 0x00 0. "ENABLE,Indicates the enabled status of the SysTick counter:?0 counter is disabled.?1 counter is operating" "0,1"
group.long 0xE014++0x03
line.long 0x00 "SYST_RVR,Systick Reload Value"
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,The value to load into the SYST_CVR register when the counter reaches 0"
group.long 0xE018++0x03
line.long 0x00 "SYST_CVR,SysTick Current Value"
hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,Current counter value.?This is the value of the counter at the time it is sampled"
group.long 0xE01C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration Value"
rbitfld.long 0x00 31. "NOREF,Indicates whether the IMPLEMENTATION DEFINED reference clock is provided:?0 the reference clock is implemented.?1 the reference clock is not implemented.?When this bit is 1 the CLKSOURCE bit of the SYST_CSR register is forced to 1 and cannot be.." "0,1"
rbitfld.long 0x00 30. "SKEW,Indicates whether the 10ms calibration value is exact:?0 10ms calibration value is exact.?1 10ms calibration value is inexact because of the clock frequency" "0,1"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,Optionally holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
group.long 0xE100++0x03
line.long 0x00 "ISER,Interrupt Set-Enable Register"
hexmask.long 0x00 0.--31. 1. "SETENA,Enables or reads the enabled state of one or more interrupts"
group.long 0xE180++0x03
line.long 0x00 "ICER,Interrupt Clear Enable Register"
hexmask.long 0x00 0.--31. 1. "CLRENA,Disables or reads the enabled state of one or more interrupts"
group.long 0xE200++0x03
line.long 0x00 "ISPR,Interrupt Set-Pending Register"
hexmask.long 0x00 0.--31. 1. "SETPEND,Changes the state of one or more interrupts to pending"
group.long 0xE280++0x03
line.long 0x00 "ICPR,Interrupt Clear-Pending Register"
hexmask.long 0x00 0.--31. 1. "CLRPEND,Changes the state of one or more interrupts to not pending"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0xE400)++0x03
line.long 0x00 "IPR$1,Interrupt Priority Registers"
bitfld.long 0x00 30.--31. "PRI_N3,Priority of interrupt number N+3" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_N2,Priority of interrupt number N+2" "0,1,2,3"
newline
bitfld.long 0x00 14.--15. "PRI_N1,Priority of interrupt number N+1" "0,1,2,3"
bitfld.long 0x00 6.--7. "PRI_N0,Priority of interrupt number N" "0,1,2,3"
repeat.end
group.long 0xED00++0x03
line.long 0x00 "CPUID,CPUID Register"
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementer code for ARM"
rbitfld.long 0x00 20.--23. "VARIANT,Implementation defined" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 16.--19. "CONSTANT,Indicates the architecture ARMv6-M" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 4.--15. 1. "PARTNO,Indicates part number Cortex-M0"
newline
rbitfld.long 0x00 0.--3. "REVISION,Indicates revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xED04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. "NMIPENDSET,Activates an NMI exception or reads back the current state.?Because NMI is the highest priority exception it activates as soon as it is registered" "0,1"
bitfld.long 0x00 28. "PENDSVSET,Sets a pending PendSV interrupt or reads back the current state" "0,1"
newline
bitfld.long 0x00 27. "PENDSVCLR,Clears a pending PendSV interrupt" "0,1"
bitfld.long 0x00 26. "PENDSTSETb,Sets a pending SysTick or reads back the current state" "0,1"
newline
bitfld.long 0x00 25. "PENDSTCLR,Clears a pending SysTick whether set here or by the timer hardware" "0,1"
rbitfld.long 0x00 23. "ISRPREEMPT,Indicates whether a pending exception will be serviced on exit from debug halt state" "0,1"
newline
rbitfld.long 0x00 22. "ISRPENDING,Indicates if an external configurable NVIC generated interrupt is pending" "0,1"
hexmask.long.word 0x00 12.--20. 1. "VECTPENDING,The exception number for the highest priority pending exception"
newline
hexmask.long.word 0x00 0.--8. 1. "VECTACTIVE,The exception number for the current executing exception"
group.long 0xED0C++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. "VECTKEY,Vector Key"
rbitfld.long 0x00 15. "ENDIANNESS,Indicates the memory system data endianness:?0 little endian?1 big endian.?See Endian support on page A3-44 for more information" "0,1"
newline
bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request" "0,1"
bitfld.long 0x00 1. "VECTCLRACTIVE,Clears all active state information for fixed and configurable?exceptions" "0,1"
group.long 0xED10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. "SEVONPEND,Determines whether an interrupt transition from inactive state to pending state is a wakeup event:?0: transitions from inactive to pending are not wakeup events.?1: transitions from inactive to pending are wakeup events.?See WFE on page A6-197.." "0,1"
bitfld.long 0x00 2. "SLEEPDEEP,An implementation can use this bit to select DeepSleep/Hibernate power modes upon execution of WFI/WFE:?0: Select Sleep mode?1: Select DeepSleep/Hibernate (depends on PWR_CONTROL.HIBERNATE)" "0,1"
newline
bitfld.long 0x00 1. "SLEEPONEXIT,Determines whether on an exit from an ISR that returns to the base level of execution priority the processor enters a sleep state:?0 do not enter sleep state.?1 enter sleep state.?See Power management on page B1-240 for more information" "0,1"
group.long 0xED14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
rbitfld.long 0x00 9. "STKALIGN," "0,1"
rbitfld.long 0x00 3. "UNALIGN_TRP," "0,1"
group.long 0xED1C++0x03
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. "PRI_11,Priority of system handler 11 SVCall" "0,1,2,3"
group.long 0xED20++0x03
line.long 0x00 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x00 30.--31. "PRI_15,Priority of system handler 15 SysTick" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_14,Priority of system handler 14 PendSV" "0,1,2,3"
group.long 0xED24++0x03
line.long 0x00 "SHCSR,System Handler Control and State Register"
bitfld.long 0x00 15. "SVCALLPENDED,0 SVCall is not pending.?1 SVCall is pending.?This bit reflects the pending state on a read and updates the pending state to the value written on a" "0,1"
group.long 0xEFD0++0x03
line.long 0x00 "SCS_PID4,System Control Space ROM Table Peripheral ID #4"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #4"
group.long 0xEFE0++0x03
line.long 0x00 "SCS_PID0,System Control Space ROM Table Peripheral ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #0"
group.long 0xEFE4++0x03
line.long 0x00 "SCS_PID1,System Control Space ROM Table Peripheral ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #1"
group.long 0xEFE8++0x03
line.long 0x00 "SCS_PID2,System Control Space ROM Table Peripheral ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #2"
group.long 0xEFEC++0x03
line.long 0x00 "SCS_PID3,System Control Space ROM Table Peripheral ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #3"
group.long 0xEFF0++0x03
line.long 0x00 "SCS_CID0,System Control Space ROM Table Component ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #0"
group.long 0xEFF4++0x03
line.long 0x00 "SCS_CID1,System Control Space ROM Table Component ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #1"
group.long 0xEFF8++0x03
line.long 0x00 "SCS_CID2,System Control Space ROM Table Component ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #2"
group.long 0xEFFC++0x03
line.long 0x00 "SCS_CID3,System Control Space ROM Table Component ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #3"
group.long 0xFF000++0x03
line.long 0x00 "ROM_SCS,CM0 CoreSight ROM Table Peripheral #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Offset to SCS ROM Table"
group.long 0xFF004++0x03
line.long 0x00 "ROM_DWT,CM0 CoreSight ROM Table Peripheral #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Offset to DWT ROM Table"
group.long 0xFF008++0x03
line.long 0x00 "ROM_BPU,CM0 CoreSight ROM Table Peripheral #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Offset to BPU ROM Table"
group.long 0xFF00C++0x03
line.long 0x00 "ROM_END,CM0 CoreSight ROM Table End Marker"
hexmask.long 0x00 0.--31. 1. "VALUE,End marker in peripheral list"
group.long 0xFFFCC++0x03
line.long 0x00 "ROM_CSMT,CM0 CoreSight ROM Table Memory Type"
hexmask.long 0x00 0.--31. 1. "VALUE,Memory Type"
group.long 0xFFFD0++0x03
line.long 0x00 "ROM_PID4,CM0 CoreSight ROM Table Peripheral ID #4"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #4"
group.long 0xFFFE0++0x03
line.long 0x00 "ROM_PID0,CM0 CoreSight ROM Table Peripheral ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #0"
group.long 0xFFFE4++0x03
line.long 0x00 "ROM_PID1,CM0 CoreSight ROM Table Peripheral ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #1"
group.long 0xFFFE8++0x03
line.long 0x00 "ROM_PID2,CM0 CoreSight ROM Table Peripheral ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #2"
group.long 0xFFFEC++0x03
line.long 0x00 "ROM_PID3,CM0 CoreSight ROM Table Peripheral ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Peripheral ID #3"
group.long 0xFFFF0++0x03
line.long 0x00 "ROM_CID0,CM0 CoreSight ROM Table Component ID #0"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #0"
group.long 0xFFFF4++0x03
line.long 0x00 "ROM_CID1,CM0 CoreSight ROM Table Component ID #1"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #1"
group.long 0xFFFF8++0x03
line.long 0x00 "ROM_CID2,CM0 CoreSight ROM Table Component ID #2"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #2"
group.long 0xFFFFC++0x03
line.long 0x00 "ROM_CID3,CM0 CoreSight ROM Table Component ID #3"
hexmask.long 0x00 0.--31. 1. "VALUE,Component ID #3"
tree.end
tree "CORESIGHTTABLE_DATA (No description available)"
base ad:0xF0000000
tree.end
tree "CPUSS (CPU Subsystem)"
base ad:0x40000000
group.long 0x00++0x03
line.long 0x00 "CONFIG,CPU Subsystem Configuration"
bitfld.long 0x00 1. "FLSH_ACC_BYPASS," "0,1"
bitfld.long 0x00 0. "VECS_IN_RAM," "0,1"
group.long 0x04++0x03
line.long 0x00 "SYSREQ,System Request Register"
bitfld.long 0x00 31. "SYSREQ,Firmware/ATE writes 1 to request a system call" "0,1"
rbitfld.long 0x00 30. "HMASTER," "0,1"
newline
rbitfld.long 0x00 29. "ROM_ACCESS_EN,Indicates that access to ROM is currently enabled" "0,1"
bitfld.long 0x00 28. "PRIVILEGED,Indicates whether the system is in privileged or user mode" "0,1"
newline
bitfld.long 0x00 27. "NO_RST_OVR,Disable Reset Vector fetch relocation:?0: CPU requests to locations" "0,1"
hexmask.long.word 0x00 0.--15. 1. "COMMAND,Opcode of the system call being requested"
group.long 0x08++0x03
line.long 0x00 "SYSARG,System Request Argument Register"
hexmask.long 0x00 0.--31. 1. "ARG32,Argument to System Call specified in SYSREQ"
group.long 0x0C++0x03
line.long 0x00 "PROTECTION,Protection Register"
bitfld.long 0x00 31. "PROT_LOCK,Setting this field will block (ignore) any further writes to the PROT field in this register" "0,1"
bitfld.long 0x00 0.--3. "PROT,Current protection mode - this field is available as a global signal everywhere in the system" "0: No description available,1: No description available,2: No description available,?,4: No description available,?,?,?,8: No description available,?..."
group.long 0x10++0x03
line.long 0x00 "PRIV_ROM,Privileged Limit Register"
hexmask.long.byte 0x00 0.--7. 1. "ROM_LIMIT,Indicates the limit where the privileged area of ROM starts in increments of 256B.?0: Entire ROM is Privileged?1: First 256B are UserMode accessiable?...?Any number larger than the size of the ROM indicates that the entire ROM is user mode.."
group.long 0x14++0x03
line.long 0x00 "PRIV_RAM,Privileged Limit Register"
hexmask.long.word 0x00 0.--8. 1. "RAM_LIMIT,Indicates the limit where the privileged area of SRAM starts in increments of 256B.?0: Entire SRAM is Privileged?1: First 256B are UserMode accessiable?...?Any number larger than the size of the RAM indicates that the entire ROM is user mode.."
group.long 0x18++0x03
line.long 0x00 "PRIV_FLASH,Privileged Limit Register"
hexmask.long.word 0x00 0.--10. 1. "FLASH_LIMIT,Indicates the limit where the privileged area of FLASH starts in increments of 256B.?0: Entire FLASH is Privileged?1: First 256B are UserMode accessiable?...?Any number larger than the size of the FLASH indicates that the entire Flash is.."
group.long 0x1C++0x03
line.long 0x00 "WOUNDING,Wounding Control Register"
bitfld.long 0x00 20.--22. "FLASH_WOUND,Indicates the amount of accessible Flash in this part" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
bitfld.long 0x00 16.--18. "RAM_WOUND,Indicates the amount of accessible RAM in this part" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
newline
abitfld.long 0x00 0.--8. "RAM_SIZE,Indicates size of RAM in this device in units of 256B (0: 0B 1: 256B 2: 512B ...)" "0x001=1: 256B,0x002=2: 512B ...)"
group.long 0x20++0x03
line.long 0x00 "INTR_SELECT,Interrupt Multiplexer Select Register"
hexmask.long 0x00 0.--31. 1. "SELECT32,When bit<N> is set NVIC IRQ<N> is connected to DSI"
tree.end
tree "CSD (Capsense Controller)"
base ad:0x40080000
group.long 0x00++0x03
line.long 0x00 "ID,ID & Revision Number"
hexmask.long.word 0x00 16.--31. 1. "REVISION,the version number is 0x0001"
hexmask.long.word 0x00 0.--15. 1. "ID,the ID of CSD peripheral is 0xE0E1"
group.long 0x04++0x03
line.long 0x00 "CONFIG,Configuration and Control"
bitfld.long 0x00 31. "ENABLE,Master enable of the CSD IP" "0,1"
bitfld.long 0x00 30. "DDFTCOMP,Changes comp_out signal for DFT purpose only" "0: No description available,1: No description available"
newline
bitfld.long 0x00 29. "ADFTEN,When selected convert IDAC1/2 outputs from current to voltage before sending to AMUXBUS-A/B" "0,1"
bitfld.long 0x00 26.--28. "DDFTSEL,Changes the dsi_sample_out signal from its normal function (sample_out) to a selection of other DDFT signals" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,?..."
newline
bitfld.long 0x00 23.--24. "REFBUF_DRV,Current drive strength for reference buffer" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 22. "SENSE_INSEL,Selects how to connect the sensing comparator to the Cmod capacitor" "0: No description available,1: No description available"
newline
bitfld.long 0x00 21. "REBUF_OUTSEL,Selects which AMUXBUS the reference buffer connects to" "0: No description available,1: No description available"
bitfld.long 0x00 19. "SENSE_COMP_EN,Turns on the sense comparator circuit" "0,1"
newline
bitfld.long 0x00 18. "MUTUAL_CAP,Enables mutual cap sensing mode" "0: No description available,1: No description available"
bitfld.long 0x00 17. "POLARITY2,For normal CSD operations this field is not used" "0: No description available,1: No description available"
newline
bitfld.long 0x00 16. "POLARITY,Selects the polarity of the sensing operation" "0: No description available,1: No description available"
bitfld.long 0x00 15. "COMP_PIN,Connects either the Cmod or Csh_tank sense return line to the reference buffer comparator" "0: No description available,1: No description available"
newline
bitfld.long 0x00 14. "COMP_MODE,Selects between charging of the Cmod/Csh_tank capacitor using the GPIO digital output buffer or the CSD reference buffer" "0: No description available,1: No description available"
bitfld.long 0x00 13. "REFBUF_EN,Enables the reference buffer/comparator circuits for charging Cmod/Csh_tank using the mode selected in COMP_MODE" "0,1"
newline
bitfld.long 0x00 12. "SENSE_EN,Enables the sense modulator output" "0,1"
bitfld.long 0x00 11. "SENSE_COMP_BW,Selects bandwidth for sensing comparator" "0: No description available,1: No description available"
newline
bitfld.long 0x00 9.--10. "SHIELD_DELAY,Indicates the number of clk_hf clock cycles that csd_shield is delayed relative to csd_sense" "0,1,2,3"
bitfld.long 0x00 8. "DSI_SENSE_EN,Enables the use of the dsi_sense_in input instead of the internally generated modulation signal to drive csd_sense and csd_shield signals" "0,1"
newline
bitfld.long 0x00 7. "PRS_12_8,Selects between 8 or 12b PRS sequence" "0: No description available,1: No description available"
bitfld.long 0x00 6. "PRS_SELECT,Selects between PRS or simple divide by 2 sense modulation" "0: No description available,1: No description available"
newline
bitfld.long 0x00 5. "PRS_CLEAR,When set forces the pseudo-random generator to it's initial state" "0,1"
bitfld.long 0x00 1. "SAMPLE_SYNC,Enables double synchronizing of sample input from DSI (only relevant when DSI_SAMPLE_EN=1)" "0,1"
newline
bitfld.long 0x00 0. "DSI_SAMPLE_EN,Enables the use of the dsi_sample_in input instead of the comparator output to strobe COUNTER" "0,1"
group.long 0x08++0x03
line.long 0x00 "IDAC,IDAC Configuration"
bitfld.long 0x00 30. "FEEDBACK_MODE,This bit controls whether during CSD operation the IDAC is controlled from the sampling flip-flop or directly from the comparator" "0: No description available,1: No description available"
bitfld.long 0x00 26. "IDAC2_RANGE,Current multiplier setting for IDAC2" "0: No description available,1: No description available"
newline
bitfld.long 0x00 24.--25. "IDAC2_MODE,Controls the usage mode of IDAC2" "0: No description available,1: No description available,2: No description available,3: No description available"
hexmask.long.byte 0x00 16.--22. 1. "IDAC2,Current setting for IDAC2 (7 bits)"
newline
bitfld.long 0x00 10. "IDAC1_RANGE,Current multiplier setting for IDAC1" "0: No description available,1: No description available"
bitfld.long 0x00 8.--9. "IDAC1_MODE,Controls the usage mode of IDAC1" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
hexmask.long.byte 0x00 0.--7. 1. "IDAC1,Current setting for IDAC1 (8 bits)"
group.long 0x0C++0x03
line.long 0x00 "COUNTER,CSD Counter Register"
hexmask.long.word 0x00 16.--31. 1. "PERIOD,The remaining period (in clk_csd1 cycles) during which COUNTER will count the comparator output count.?Firmware will write this field to the desired period after which it will start counting down to 0"
hexmask.long.word 0x00 0.--15. 1. "COUNTER,This field increments whenever the comparator is sampled and the sample is 1"
group.long 0x10++0x03
line.long 0x00 "STATUS,Status Register"
rbitfld.long 0x00 3. "SAMPLE,Output of main sensing comparator" "0,1"
rbitfld.long 0x00 2. "COMP_OUT,Output of reference buffer comparator used to charge up Cmod or Csh_tank" "0: No description available,1: No description available"
newline
rbitfld.long 0x00 1. "CSD_SENSE,Signal used to drive the Cs switches" "0,1"
rbitfld.long 0x00 0. "CSD_CHARGE,Qualified and possible inverted value of COMP_OUT that is used to drive GPIO's charging Cmod or Csh_tank" "0,1"
group.long 0x14++0x03
line.long 0x00 "INTR,CSD Interrupt Request Register"
bitfld.long 0x00 0. "CSD,The CSD IRQ bit is set" "0,1"
group.long 0x18++0x03
line.long 0x00 "INTR_SET,CSD Interrupt set register"
bitfld.long 0x00 0. "CSD,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xFF00++0x03
line.long 0x00 "TRIM1,CSD Trim Register"
bitfld.long 0x00 4.--7. "IDAC2_SRC_TRIM,IDAC2 trim bits for gain control in current source mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "IDAC1_SRC_TRIM,IDAC1 trim bits for gain control in current source mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFF04++0x03
line.long 0x00 "TRIM2,CSD Trim Register"
bitfld.long 0x00 4.--7. "IDAC2_SNK_TRIM,IDAC2 trim bits for gain control in current sink mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "IDAC1_SNK_TRIM,IDAC1 trim bits for gain control in current sink mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "CTBM (Continuous Time Block Mini)"
base ad:0x40100000
group.long 0x00++0x03
line.long 0x00 "CTB_CTRL,global CTB and power control"
bitfld.long 0x00 31. "ENABLED," "0: CTB IP disabled (put analog in power,1: CTB IP enabled"
group.long 0x04++0x03
line.long 0x00 "OA_RES0_CTRL,Opamp0 and resistor0 control"
bitfld.long 0x00 11. "OA0_PUMP_EN,Opamp0 pump enable" "0,1"
bitfld.long 0x00 8.--9. "OA0_COMPINT,Opamp0 comparator edge detect" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.long 0x00 6. "OA0_BYPASS_DSI_SYNC,Opamp0 bypass comparator output synchronization for DSI output" "0: synchronize,1: bypass"
bitfld.long 0x00 5. "OA0_HYST_EN,Opamp0 hysteresis enable (10mV)" "0,1"
newline
bitfld.long 0x00 4. "OA0_COMP_EN,Opamp0 comparator enable" "0,1"
bitfld.long 0x00 2. "OA0_DRIVE_STR_SEL,Opamp0 output strenght select" "0,1"
newline
bitfld.long 0x00 0.--1. "OA0_PWR_MODE,Opamp0 power level" "0,1,2,3"
group.long 0x08++0x03
line.long 0x00 "OA_RES1_CTRL,Opamp1 and resistor1 control"
bitfld.long 0x00 11. "OA1_PUMP_EN,Opamp1 pump enable" "0,1"
bitfld.long 0x00 8.--9. "OA1_COMPINT,Opamp0 comparator edge detect" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.long 0x00 6. "OA1_BYPASS_DSI_SYNC,Opamp1 bypass comparator output synchronization for DSI output" "0: synchronize,1: bypass"
bitfld.long 0x00 5. "OA1_HYST_EN,Opamp1 hysteresis enable (10mV)" "0,1"
newline
bitfld.long 0x00 4. "OA1_COMP_EN,Opamp1 comparator enable" "0,1"
bitfld.long 0x00 2. "OA1_DRIVE_STR_SEL,Opamp1 output strenght select" "0,1"
newline
bitfld.long 0x00 0.--1. "OA1_PWR_MODE,Opamp1 power level" "0,1,2,3"
group.long 0x0C++0x03
line.long 0x00 "COMP_STAT,Comparator status"
rbitfld.long 0x00 16. "OA1_COMP,Opamp1 current comparator status" "0,1"
rbitfld.long 0x00 0. "OA0_COMP,Opamp0 current comparator status" "0,1"
group.long 0x20++0x03
line.long 0x00 "INTR,Interrupt request register"
bitfld.long 0x00 1. "COMP1,Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers" "0,1"
bitfld.long 0x00 0. "COMP0,Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers" "0,1"
group.long 0x24++0x03
line.long 0x00 "INTR_SET,Interrupt request set register"
bitfld.long 0x00 1. "COMP1_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "COMP0_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0x28++0x03
line.long 0x00 "INTR_MASK,Interrupt request mask"
bitfld.long 0x00 1. "COMP1_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "COMP0_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0x2C++0x03
line.long 0x00 "INTR_MASKED,Interrupt request masked"
rbitfld.long 0x00 1. "COMP1_MASKED,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 0. "COMP0_MASKED,Logical and of corresponding request and mask bits" "0,1"
group.long 0x30++0x03
line.long 0x00 "DFT_CTRL,Analog DfT controls"
bitfld.long 0x00 31. "DFT_EN,Analog DfT enable" "0,1"
bitfld.long 0x00 0.--2. "DFT_MODE,Analog DfT mode" "0,1,2,3,4,5,6,7"
group.long 0x80++0x03
line.long 0x00 "OA0_SW,Opamp0 switch control"
bitfld.long 0x00 21. "OA0O_D81,Opamp0 output switch to short 1x with 1L0xdrive" "0,1"
bitfld.long 0x00 18. "OA0O_D51,Opamp0 output sarbus0 (ctbbus2 in CTB)" "0,1"
newline
bitfld.long 0x00 14. "OA0M_A81,Opamp0 negative terminal Opamp0 bottom" "0,1"
bitfld.long 0x00 8. "OA0M_A11,Opamp0 negative terminal P1" "0,1"
newline
bitfld.long 0x00 3. "OA0P_A30,Opamp0 positive terminal ctbbus0" "0,1"
bitfld.long 0x00 2. "OA0P_A20,Opamp0 positive terminal P0" "0,1"
newline
bitfld.long 0x00 0. "OA0P_A00,Opamp0 positive terminal amuxbusa" "0,1"
group.long 0x84++0x03
line.long 0x00 "OA0_SW_CLEAR,Opamp0 switch control clear"
bitfld.long 0x00 21. "OA0O_D81,see corresponding bit in OA0_SW" "0,1"
bitfld.long 0x00 18. "OA0O_D51,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x00 14. "OA0M_A81,see corresponding bit in OA0_SW" "0,1"
bitfld.long 0x00 8. "OA0M_A11,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x00 3. "OA0P_A30,see corresponding bit in OA0_SW" "0,1"
bitfld.long 0x00 2. "OA0P_A20,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x00 0. "OA0P_A00,see corresponding bit in OA0_SW" "0,1"
group.long 0x88++0x03
line.long 0x00 "OA1_SW,Opamp1 switch control"
bitfld.long 0x00 21. "OA1O_D82,Opamp1 output switch to short 1x with 1L0xdrive" "0,1"
bitfld.long 0x00 19. "OA1O_D62,Opamp1 output sarbus1 (ctbbus3 in CTB)" "0,1"
newline
bitfld.long 0x00 18. "OA1O_D52,Opamp1 output sarbus0 (ctbbus2 in CTB)" "0,1"
bitfld.long 0x00 14. "OA1M_A82,Opamp1 negative terminal Opamp1 bottom" "0,1"
newline
bitfld.long 0x00 8. "OA1M_A22,Opamp1 negative terminal P4" "0,1"
bitfld.long 0x00 4. "OA1P_A43,Opamp1 positive terminal ctbbus1" "0,1"
newline
bitfld.long 0x00 1. "OA1P_A13,Opamp1 positive terminal P5" "0,1"
bitfld.long 0x00 0. "OA1P_A03,Opamp1 positive terminal amuxbusb" "0,1"
group.long 0x8C++0x03
line.long 0x00 "OA1_SW_CLEAR,Opamp1 switch control clear"
bitfld.long 0x00 21. "OA1O_D82,see corresponding bit in OA1_SW" "0,1"
bitfld.long 0x00 19. "OA1O_D62,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0x00 18. "OA1O_D52,see corresponding bit in OA1_SW" "0,1"
bitfld.long 0x00 14. "OA1M_A82,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0x00 8. "OA1M_A22,see corresponding bit in OA1_SW" "0,1"
bitfld.long 0x00 4. "OA1P_A43,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0x00 1. "OA1P_A13,see corresponding bit in OA1_SW" "0,1"
bitfld.long 0x00 0. "OA1P_A03,see corresponding bit in OA1_SW" "0,1"
group.long 0xC0++0x03
line.long 0x00 "CTB_SW_HW_CTRL,CTB bus switch control status"
bitfld.long 0x00 3. "P3_HW_CTRL,Pin P3 switches" "0,1"
bitfld.long 0x00 2. "P2_HW_CTRL,Pin P2 switches" "0,1"
group.long 0xC4++0x03
line.long 0x00 "CTB_SW_STATUS,CTB bus switch control status"
rbitfld.long 0x00 30. "OA1O_D62_STAT,see OA1O_D62 bit in OA1_SW" "0,1"
rbitfld.long 0x00 29. "OA1O_D52_STAT,see OA1O_D52 bit in OA1_SW" "0,1"
newline
rbitfld.long 0x00 28. "OA0O_D51_STAT,see OA0O_D51 bit in OA0_SW" "0,1"
group.long 0xF00++0x03
line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 trim control"
bitfld.long 0x00 0.--5. "OA0_OFFSET_TRIM,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF04++0x03
line.long 0x00 "OA0_SLOPE_OFFSET_TRIM,Opamp0 trim control"
bitfld.long 0x00 0.--5. "OA0_SLOPE_OFFSET_TRIM,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF08++0x03
line.long 0x00 "OA0_COMP_TRIM,Opamp0 trim control"
bitfld.long 0x00 0.--1. "OA0_COMP_TRIM,Opamp0 Compenation Capacitor Trim" "0,1,2,3"
group.long 0xF0C++0x03
line.long 0x00 "OA1_OFFSET_TRIM,Opamp1 trim control"
bitfld.long 0x00 0.--5. "OA1_OFFSET_TRIM,Opamp1 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF10++0x03
line.long 0x00 "OA1_SLOPE_OFFSET_TRIM,Opamp1 trim control"
bitfld.long 0x00 0.--5. "OA1_SLOPE_OFFSET_TRIM,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF14++0x03
line.long 0x00 "OA1_COMP_TRIM,Opamp1 trim control"
bitfld.long 0x00 0.--1. "OA1_COMP_TRIM,Opamp1 Compenation Capacitor Trim" "0,1,2,3"
tree.end
tree "HSIOM (High-Speed IO-Matrix for PSOC4A)"
base ad:0x40010000
group.long 0x00++0x03
line.long 0x00 "PORT_SEL0,Port 0 control register"
bitfld.long 0x00 28.--31. "SEL7,Selects pin 7 source" "?,?,?,?,?,?,?,?,?,?,?,?,?,?,14: No description available,15: No description available"
bitfld.long 0x00 24.--27. "SEL6,Selects pin 6 source" "?,?,?,?,?,?,?,?,8: No description available,?,?,?,?,?,?,15: No description available"
newline
bitfld.long 0x00 20.--23. "SEL5,Selects pin 5 source" "?,?,?,?,?,?,?,?,?,9: No description available,?,?,?,?,14: No description available,15: No description available"
bitfld.long 0x00 16.--19. "SEL4,Selects pin 4 source" "?,?,?,?,?,?,?,?,?,9: No description available,?,?,?,?,14: No description available,15: No description available"
newline
bitfld.long 0x00 12.--15. "SEL3,Selects pin 3 source" "0: No description available,?..."
bitfld.long 0x00 8.--11. "SEL2,Selects pin 2 source" "0: No description available,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: No description available"
newline
bitfld.long 0x00 4.--7. "SEL1,Selects pin 1 source" "0: No description available,?,?,?,?,?,?,?,?,?,?,?,?,?,?,15: No description available"
bitfld.long 0x00 0.--3. "SEL0,Selects pin 0 source" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
group.long 0x04++0x03
line.long 0x00 "PORT_SEL1,Port 1 control register"
bitfld.long 0x00 28.--31. "SEL7,Selects pin 7 source" "0: No description available,?..."
bitfld.long 0x00 24.--27. "SEL6,Selects pin 6 source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "SEL5,Selects pin 5 source" "0: No description available,?..."
bitfld.long 0x00 16.--19. "SEL4,Selects pin 4 source" "0: No description available,?..."
newline
bitfld.long 0x00 12.--15. "SEL3,Selects pin 3 source" "0: No description available,?,?,?,?,?,?,?,8: No description available,?..."
bitfld.long 0x00 8.--11. "SEL2,Selects pin 2 source" "0: No description available,?,?,?,?,?,?,?,8: No description available,?..."
newline
bitfld.long 0x00 4.--7. "SEL1,Selects pin 1 source" "0: No description available,?,?,?,?,?,?,?,8: No description available,?..."
bitfld.long 0x00 0.--3. "SEL0,Selects pin 0 source" "0: No description available,?,?,?,?,?,?,?,8: No description available,?..."
group.long 0x08++0x03
line.long 0x00 "PORT_SEL2,Port 2 control register"
bitfld.long 0x00 28.--31. "SEL7,Selects pin 7 source" "0: No description available,?,?,?,?,?,?,?,8: No description available,?..."
bitfld.long 0x00 24.--27. "SEL6,Selects pin 6 source" "0: No description available,?,?,?,?,?,?,?,8: No description available,?..."
newline
bitfld.long 0x00 20.--23. "SEL5,Selects pin 5 source" "0: No description available,?,?,?,?,?,?,?,8: No description available,?..."
bitfld.long 0x00 16.--19. "SEL4,Selects pin 4 source" "0: No description available,?,?,?,?,?,?,?,8: No description available,?..."
newline
bitfld.long 0x00 12.--15. "SEL3,Selects pin 3 source" "0: No description available,?..."
bitfld.long 0x00 8.--11. "SEL2,Selects pin 2 source" "0: No description available,?..."
newline
bitfld.long 0x00 4.--7. "SEL1,Selects pin 1 source" "0: No description available,?..."
bitfld.long 0x00 0.--3. "SEL0,Selects pin 0 source" "0: No description available,?..."
group.long 0x0C++0x03
line.long 0x00 "PORT_SEL3,Port 3 control register"
bitfld.long 0x00 28.--31. "SEL7,Selects pin 7 source" "?,?,?,?,?,?,?,?,8: No description available,?,?,?,?,?,14: No description available,?..."
bitfld.long 0x00 24.--27. "SEL6,Selects pin 6 source" "?,?,?,?,?,?,?,?,8: No description available,?,?,?,?,?,14: No description available,15: No description available"
newline
bitfld.long 0x00 20.--23. "SEL5,Selects pin 5 source" "?,?,?,?,?,?,?,?,8: No description available,?,?,?,?,?,?,15: No description available"
bitfld.long 0x00 16.--19. "SEL4,Selects pin 4 source" "?,?,?,?,?,?,?,?,8: No description available,?,?,?,?,?,?,15: No description available"
newline
bitfld.long 0x00 12.--15. "SEL3,Selects pin 3 source" "?,?,?,?,?,?,?,?,8: No description available,?,?,?,?,?,14: No description available,15: No description available"
bitfld.long 0x00 8.--11. "SEL2,Selects pin 2 source" "?,?,?,?,?,?,?,?,8: No description available,?,?,?,?,?,14: No description available,15: No description available"
newline
bitfld.long 0x00 4.--7. "SEL1,Selects pin 1 source" "?,?,?,?,?,?,?,?,8: No description available,9: No description available,?,?,?,?,14: No description available,15: No description available"
bitfld.long 0x00 0.--3. "SEL0,Selects pin 0 source" "?,?,?,?,?,?,?,?,8: No description available,9: No description available,?,?,?,?,14: No description available,15: No description available"
group.long 0x10++0x03
line.long 0x00 "PORT_SEL4,Port 4 control register"
bitfld.long 0x00 12.--15. "SEL3,Selects pin 3 source" "?,?,?,?,?,?,?,7: CSD_CSHTANK/CSD_CSHTANK_CHRG,?,?,?,?,?,?,?,15: No description available"
bitfld.long 0x00 8.--11. "SEL2,Selects pin 2 source" "?,?,?,?,?,?,6: No description available,7: No description available,?,?,?,?,?,?,?,15: No description available"
newline
bitfld.long 0x00 4.--7. "SEL1,Selects pin 1 source" "?,?,?,?,?,?,?,?,?,9: No description available,?,?,?,?,14: No description available,15: No description available"
bitfld.long 0x00 0.--3. "SEL0,Selects pin 0 source" "?,?,?,?,?,?,?,?,?,9: No description available,?,?,?,?,14: No description available,15: No description available"
tree.end
tree "LCD (LCD Controller Block)"
base ad:0x40090000
group.long 0x00++0x03
line.long 0x00 "ID,ID & Revision"
hexmask.long.word 0x00 16.--31. 1. "REVISION,the version number is 0x0001"
hexmask.long.word 0x00 0.--15. 1. "ID,the ID of LCD controller peripheral is 0xF0F0"
group.long 0x04++0x03
line.long 0x00 "DIVIDER,LCD Divider Register"
hexmask.long.word 0x00 16.--31. 1. "DEAD_DIV,Length of the dead time period in cycles"
hexmask.long.word 0x00 0.--15. 1. "SUBFR_DIV,Input clock frequency divide value to generate the 1/4 sub-frame period"
group.long 0x08++0x03
line.long 0x00 "CONTROL,LCD Configuration Register"
rbitfld.long 0x00 31. "LS_EN_STAT,LS enable status bit" "0,1"
bitfld.long 0x00 8.--11. "COM_NUM,The number of COM connections minus 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--6. "BIAS,PWM bias selection" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 4. "OP_MODE,Driving mode configuration" "0: No description available,1: No description available"
newline
bitfld.long 0x00 3. "TYPE,LCD driving waveform type configuration" "0: No description available,1: No description available"
bitfld.long 0x00 2. "LCD_MODE,HS/LS Mode selection" "0: No description available,1: No description available"
newline
bitfld.long 0x00 1. "HS_EN,high speed (LS) generator enable?1: enable?0: disable" "0,1"
bitfld.long 0x00 0. "LS_EN,Low speed (HS) generator enable?1: enable?0: disable" "0,1"
repeat 5. (strings "00" "01" "02" "03" "04" )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x100)++0x03
line.long 0x00 "DATA$1,LCD Pin Data Registers"
hexmask.long 0x00 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb)"
repeat.end
tree.end
tree "LPCOMP (Low-power Comparator)"
base ad:0x400A0000
group.long 0x00++0x03
line.long 0x00 "ID,ID & Revision"
hexmask.long.word 0x00 16.--31. 1. "REVISION,the version number is 0x0001"
hexmask.long.word 0x00 0.--15. 1. "ID,the ID of LPCOMP peripheral is 0xE0E0"
group.long 0x04++0x03
line.long 0x00 "CONFIG,LPCOMP Configuration Register"
bitfld.long 0x00 15. "ENABLE2,Enable comparator #2" "0,1"
rbitfld.long 0x00 14. "OUT2,Current output value of the comparator" "0,1"
newline
bitfld.long 0x00 12.--13. "INTTYPE2,Sets which edge will trigger an IRQ" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 11. "FILTER2,Enable the inline digital filter for the comparator" "0,1"
newline
bitfld.long 0x00 10. "HYST2,Add 10mV hysteresis to the comparator" "0,1"
bitfld.long 0x00 8.--9. "MODE2,Operating mode for the comparator" "0: No description available,1: No description available,2: No description available,?..."
newline
bitfld.long 0x00 7. "ENABLE1,Enable comparator #1" "0,1"
rbitfld.long 0x00 6. "OUT1,Current output value of the comparator" "0,1"
newline
bitfld.long 0x00 4.--5. "INTTYPE1,Sets which edge will trigger an IRQ" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 3. "FILTER1,Enable the inline digital filter for the comparator" "0,1"
newline
bitfld.long 0x00 2. "HYST1,Add 10mV hysteresis to the comparator" "0,1"
bitfld.long 0x00 0.--1. "MODE1,Operating mode for the comparator" "0: No description available,1: No description available,2: No description available,?..."
group.long 0x08++0x03
line.long 0x00 "DFT,LPCOMP DFT register"
bitfld.long 0x00 1. "BYPASS,Enables bypass of inp input straight to output" "0,1"
bitfld.long 0x00 0. "CAL_EN,Calibration enable" "0,1"
group.long 0x0C++0x03
line.long 0x00 "INTR,LPCOMP Interrupt request register"
bitfld.long 0x00 1. "COMP2,Comparator #2 generated an interrupt" "0,1"
bitfld.long 0x00 0. "COMP1,Comparator #1 generated an interrupt" "0,1"
group.long 0x10++0x03
line.long 0x00 "INTR_SET,LPCOMP Interrupt set register"
bitfld.long 0x00 1. "COMP2,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "COMP1,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xFF00++0x03
line.long 0x00 "TRIM1,LPCOMP Trim Register"
bitfld.long 0x00 0.--4. "COMP1_TRIMA,Trim A for Comparator #1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xFF04++0x03
line.long 0x00 "TRIM2,LPCOMP Trim Register"
bitfld.long 0x00 0.--4. "COMP1_TRIMB,Trim B for Comparator #1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xFF08++0x03
line.long 0x00 "TRIM3,LPCOMP Trim Register"
bitfld.long 0x00 0.--4. "COMP2_TRIMA,Trim A for Comparator #2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xFF0C++0x03
line.long 0x00 "TRIM4,LPCOMP Trim Register"
bitfld.long 0x00 0.--4. "COMP2_TRIMB,Trim B for Comparator #2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "PRT (GPIO Port Registers)"
repeat 5. (list 0. 1. 2. 3. 4.) (list ad:0x40040000 ad:0x40040100 ad:0x40040200 ad:0x40040300 ad:0x40040400)
tree "PRT$1"
base $2
group.long 0x00++0x03
line.long 0x00 "DR,Port Output Data Register"
hexmask.long.byte 0x00 0.--7. 1. "DATAREG,The data written to this register specifies the high ('1') or low ('0') state for a specific pin"
group.long 0x04++0x03
line.long 0x00 "PS,Port Pin State Register"
rbitfld.long 0x00 8. "PINSTATE_FLT,Reads of this register return the logical state of the filtered pin" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "PINSTATE,Reads of this register return the logical state of the corresponding I/O pin"
group.long 0x08++0x03
line.long 0x00 "PC,Port Configuration Register"
bitfld.long 0x00 25. "SLOW,This bit controls the output edge rate of all pins on the port:?0: fast.?1: slow" "0,1"
bitfld.long 0x00 24. "VTRIP_SEL,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "0,1"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "DM,The GPIO drive mode for a specific pin"
group.long 0x0C++0x03
line.long 0x00 "INTCFG,Port IRQ Configuration Register"
bitfld.long 0x00 18.--20. "FLT_SELECT,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--17. "INTTYPE_FLT,Same for the glitch filtered pin (selected by FLT_SELECT)" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
hexmask.long.word 0x00 0.--15. 1. "INTTYPE,Sets which edge will trigger an IRQ for a specific pin"
group.long 0x10++0x03
line.long 0x00 "INTSTAT,Port IRQ Status Register"
rbitfld.long 0x00 24. "PS_FLT,This is a duplicate of the contents of the PS register provided here to allow reading of both pin state and interrupt state of the port in a single read operation" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "PS,This is a duplicate of the contents of the PS register provided here to allow reading of both pin state and interrupt state of the port in a single read operation"
newline
bitfld.long 0x00 8. "INTSTAT_FLT,Deglitched interrupt pending (selected by FLT_SELECT)" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "INTSTAT,Bit n indicates interrupt pending on pin #n"
group.long 0x18++0x03
line.long 0x00 "PC2,Port Secondary Configuration Register"
hexmask.long.byte 0x00 0.--7. 1. "INP_DIS,Disables the input buffer indepent of the port control drive mode (PC.DM)"
tree.end
repeat.end
tree.end
tree "SAR (SAR ADC with Sequencer)"
base ad:0x401A0000
group.long 0x00++0x03
line.long 0x00 "CTRL,Analog control register"
bitfld.long 0x00 31. "ENABLED," "0: SAR IP disabled (put analog in power,1: SAR IP enabled"
bitfld.long 0x00 30. "SWITCH_DISABLE,Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control)?" "0: Normal mode ,1: Switches disabled"
newline
bitfld.long 0x00 29. "DSI_MODE,SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1)?" "0: Normal mode SAR sequencer operates according to,1: CHAN_EN INJ_START_EN and channel configurations"
bitfld.long 0x00 28. "DSI_SYNC_CONFIG," "0: bypass cd synchronisation of the DSI,1: synchronize the DSI config signals "
newline
bitfld.long 0x00 24.--25. "ICONT_LV,SARADC low power mode" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 16.--19. "SPARE,Spare controls not yet designated for late changes done with an ECO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "PWR_CTRL_VREF,VREF buffer low power mode" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 13. "SAR_HW_CTRL_NEGVREF,Hardware control" "0: only firmware control,1: hardware control masked by setting"
newline
bitfld.long 0x00 9.--11. "NEG_SEL,SARADC internal NEG selection for Single ended conversion" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
bitfld.long 0x00 7. "VREF_BYP_CAP_EN,VREF bypass cap enable for when VREF buffer is on" "0,1"
newline
bitfld.long 0x00 4.--6. "VREF_SEL,SARADC internal VREF selection" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.long 0x04++0x03
line.long 0x00 "SAMPLE_CTRL,Sample control register"
bitfld.long 0x00 31. "EOS_DSI_OUT_EN,Enable to output EOS_INTR to DSI" "0,1"
bitfld.long 0x00 19. "DSI_SYNC_TRIGGER," "0: bypass cd synchronisation of the DSI,1: synchronize the DSI trigger signal"
newline
bitfld.long 0x00 18. "DSI_TRIGGER_LEVEL," "0: DSI trigger signal is a pulse input a positive,1: DSI trigger signal is a level input as long as"
bitfld.long 0x00 17. "DSI_TRIGGER_EN," "0: firmware trigger only,1: enable hardware (DSI) trigger"
newline
bitfld.long 0x00 16. "CONTINUOUS," "0: Wait for next FW_TRIGGER (one shot) or hardware,1: Continuously scan enabled channels ignore.."
bitfld.long 0x00 7. "AVG_SHIFT,Averaging shifting: after averaging the result is shifted right to fit in the sample resolution i.e" "0,1"
newline
bitfld.long 0x00 4.--6. "AVG_CNT,Averaging Count for channels that have over sampling enabled (AVG_EN)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "DIFFERENTIAL_SIGNED,Output data from a differential conversion as a signed value" "0: No description available,1: No description available"
newline
bitfld.long 0x00 2. "SINGLE_ENDED_SIGNED,Output data from a single ended conversion as a signed value" "0: No description available,1: No description available"
bitfld.long 0x00 1. "LEFT_ALIGN,Left align data in data[15:0] default data is right aligned in data[11:0] with sign extension to 16 bits if the channel is differential" "0,1"
newline
bitfld.long 0x00 0. "SUB_RESOLUTION,Conversion resolution for channels that have sub-resolution enabled (RESOLUTION=1) (otherwise resolution is 12-bit)" "0: No description available,1: No description available"
group.long 0x10++0x03
line.long 0x00 "SAMPLE_TIME01,Sample time specification ST0 and ST1"
hexmask.long.word 0x00 16.--25. 1. "SAMPLE_TIME1,Sample time1"
hexmask.long.word 0x00 0.--9. 1. "SAMPLE_TIME0,Sample time0 (aperture) in ADC clock cycles.?Minimum sample time is 222ns which is 4 cycles with an 18MHz clock"
group.long 0x14++0x03
line.long 0x00 "SAMPLE_TIME23,Sample time specification ST2 and ST3"
hexmask.long.word 0x00 16.--25. 1. "SAMPLE_TIME3,Sample time3"
hexmask.long.word 0x00 0.--9. 1. "SAMPLE_TIME2,Sample time2"
group.long 0x18++0x03
line.long 0x00 "RANGE_THRES,Global range detect threshold register"
hexmask.long.word 0x00 16.--31. 1. "RANGE_HIGH,high threshold for range detect"
hexmask.long.word 0x00 0.--15. 1. "RANGE_LOW,low threshold for range detect"
group.long 0x1C++0x03
line.long 0x00 "RANGE_COND,Global range detect mode register"
bitfld.long 0x00 30.--31. "RANGE_COND,Range condition select" "0: No description available,1: No description available,2: No description available,3: No description available"
group.long 0x20++0x03
line.long 0x00 "CHAN_EN,Enable bits for the channels"
abitfld.long 0x00 0.--15. "CHAN_EN,Channel enable" "0x0000=0: the corresponding channel is disabled.?,0x0001=1: the corresponding channel is enabled.."
group.long 0x24++0x03
line.long 0x00 "START_CTRL,Start control register (firmware trigger)"
bitfld.long 0x00 0. "FW_TRIGGER,When firmware writes a 1 here it will trigger the next scan of enabled channels hardware clears this bit when the scan started with this trigger is completed" "0,1"
group.long 0x30++0x03
line.long 0x00 "DFT_CTRL,DFT control register"
bitfld.long 0x00 31. "ADFT_OVERRIDE,During deepsleep/ hibernate mode keep SARMUX active i.e" "0,1"
bitfld.long 0x00 29. "DCEN,Delay Control Enable for latch.?" "0: doubles the latch enable time.?,1: normal latch enable time (default)"
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bitfld.long 0x00 28. "EN_CSEL_DFT,Mux select signal for DAC control" "0,1"
bitfld.long 0x00 24.--27. "SEL_CSEL_DFT,Usage" "?,1: DFT bits for DAC array?Usage,2: For [0]=1 (when dcen=0),?..."
newline
bitfld.long 0x00 20.--22. "DFT_OUTC,DFT control for preamp outputs" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. "DFT_INC,DFT control for preamp inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "HIZ,DFT control for getting higher input impedance" "0,1"
bitfld.long 0x00 0. "DLY_INC,DFT control: Control for delay circuits on sampling phase =1 doubes the non-overlap delay" "0,1"
repeat 8. (strings "00" "01" "02" "03" "04" "05" "06" "07" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x80)++0x03
line.long 0x00 "CHAN_CONFIG$1,Channel configuration register"
bitfld.long 0x00 31. "DSI_OUT_EN,DSI data output enable for this channel.?" "0: the conversion result for this channel is only,1: the conversion result for this channel is.."
bitfld.long 0x00 12.--13. "SAMPLE_TIME_SEL,Sample time select: select which of the 4 global sample times to use for this channel" "0,1,2,3"
newline
bitfld.long 0x00 10. "AVG_EN,Averaging enable for this channel" "0,1"
bitfld.long 0x00 9. "RESOLUTION,Resolution for this channel" "0: No description available,1: No description available"
newline
bitfld.long 0x00 8. "DIFFERENTIAL_EN,Differential enable for this channel.?" "0: Single-ended voltage is measured,1: The differential voltage is measured"
bitfld.long 0x00 4.--6. "PORT_ADDR,Address of the port that contains the pin to be sampled by this channel" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,?,6: No description available,7: No description available"
newline
bitfld.long 0x00 0.--2. "PIN_ADDR,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
repeat.end
repeat 8. (strings "00" "01" "02" "03" "04" "05" "06" "07" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x100)++0x03
line.long 0x00 "CHAN_WORK$1,Channel working data register"
rbitfld.long 0x00 31. "CHAN_WORK_VALID_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register" "0,1"
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
repeat.end
repeat 8. (strings "00" "01" "02" "03" "04" "05" "06" "07" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x180)++0x03
line.long 0x00 "CHAN_RESULT$1,Channel result data register"
rbitfld.long 0x00 31. "CHAN_RESULT_VALID_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_VALID register" "0,1"
rbitfld.long 0x00 30. "RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_RANGE_INTR register" "0,1"
newline
rbitfld.long 0x00 29. "SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_SATURATE_INTR register" "0,1"
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
repeat.end
group.long 0x200++0x03
line.long 0x00 "CHAN_WORK_VALID,Channel working data register valid bits"
hexmask.long.word 0x00 0.--15. 1. "CHAN_WORK_VALID,If set the corresponding WORK data is valid i.e"
group.long 0x204++0x03
line.long 0x00 "CHAN_RESULT_VALID,Channel result data register valid bits"
hexmask.long.word 0x00 0.--15. 1. "CHAN_RESULT_VALID,If set the corresponding RESULT data is valid i.e"
group.long 0x208++0x03
line.long 0x00 "STATUS,Current status of internal SAR registers (mostly for debug)"
rbitfld.long 0x00 31. "BUSY,If high then the SAR is busy with a conversion" "0,1"
rbitfld.long 0x00 30. "SW_VREF_NEG,the current switch status including DSI and sequencer controls of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL)" "0,1"
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rbitfld.long 0x00 0.--4. "CUR_CHAN,current channel being sampled (channel 16 indicates the injection channel) only valid if BUSY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x20C++0x03
line.long 0x00 "AVG_STAT,Current averaging status (for debug)"
hexmask.long.byte 0x00 24.--31. 1. "CUR_AVG_CNT,the current value of the averaging counter"
hexmask.long.tbyte 0x00 0.--19. 1. "CUR_AVG_ACCU,the current value of the averaging accumulator"
group.long 0x210++0x03
line.long 0x00 "INTR,Interrupt request register"
bitfld.long 0x00 7. "INJ_COLLISION_INTR,Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 && INJ_TAILGATING==0) while the SAR is BUSY" "0,1"
bitfld.long 0x00 6. "INJ_RANGE_INTR,Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers" "0,1"
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bitfld.long 0x00 5. "INJ_SATURATE_INTR,Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF (for 12-bit resolution) this is an indication that the ADC likely saturated" "0,1"
bitfld.long 0x00 4. "INJ_EOC_INTR,Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used)" "0,1"
newline
bitfld.long 0x00 3. "DSI_COLLISION_INTR,DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY" "0,1"
bitfld.long 0x00 2. "FW_COLLISION_INTR,Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY" "0,1"
newline
bitfld.long 0x00 1. "OVERFLOW_INTR,Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware" "0,1"
bitfld.long 0x00 0. "EOS_INTR,End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels" "0,1"
group.long 0x214++0x03
line.long 0x00 "INTR_SET,Interrupt set request register"
bitfld.long 0x00 7. "INJ_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "INJ_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "INJ_SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "INJ_EOC_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
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bitfld.long 0x00 3. "DSI_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "FW_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "EOS_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0x218++0x03
line.long 0x00 "INTR_MASK,Interrupt mask register"
bitfld.long 0x00 7. "INJ_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "INJ_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "INJ_SATURATE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "INJ_EOC_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 3. "DSI_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "FW_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "EOS_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0x21C++0x03
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
rbitfld.long 0x00 7. "INJ_COLLISION_MASKED,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 6. "INJ_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 5. "INJ_SATURATE_MASKED,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 4. "INJ_EOC_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 3. "DSI_COLLISION_MASKED,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 2. "FW_COLLISION_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 1. "OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 0. "EOS_MASKED,Logical and of corresponding request and mask bits" "0,1"
group.long 0x220++0x03
line.long 0x00 "SATURATE_INTR,Saturate interrupt request register"
hexmask.long.word 0x00 0.--15. 1. "SATURATE_INTR,Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF (for 12-bit resolution) this is an indication that the ADC likely saturated"
group.long 0x224++0x03
line.long 0x00 "SATURATE_INTR_SET,Saturate interrupt set request register"
hexmask.long.word 0x00 0.--15. 1. "SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register"
group.long 0x228++0x03
line.long 0x00 "SATURATE_INTR_MASK,Saturate interrupt mask register"
hexmask.long.word 0x00 0.--15. 1. "SATURATE_MASK,Mask bit for corresponding bit in interrupt request register"
group.long 0x22C++0x03
line.long 0x00 "SATURATE_INTR_MASKED,Saturate interrupt masked request register"
hexmask.long.word 0x00 0.--15. 1. "SATURATE_MASKED,Logical and of corresponding request and mask bits"
group.long 0x230++0x03
line.long 0x00 "RANGE_INTR,Range detect interrupt request register"
hexmask.long.word 0x00 0.--15. 1. "RANGE_INTR,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers"
group.long 0x234++0x03
line.long 0x00 "RANGE_INTR_SET,Range detect interrupt set request register"
hexmask.long.word 0x00 0.--15. 1. "RANGE_SET,Write with '1' to set corresponding bit in interrupt request register"
group.long 0x238++0x03
line.long 0x00 "RANGE_INTR_MASK,Range detect interrupt mask register"
hexmask.long.word 0x00 0.--15. 1. "RANGE_MASK,Mask bit for corresponding bit in interrupt request register"
group.long 0x23C++0x03
line.long 0x00 "RANGE_INTR_MASKED,Range interrupt masked request register"
hexmask.long.word 0x00 0.--15. 1. "RANGE_MASKED,Logical and of corresponding request and mask bits"
group.long 0x240++0x03
line.long 0x00 "INTR_CAUSE,Interrupt cause register"
rbitfld.long 0x00 31. "RANGE_MASKED_RED,Reduction OR of all SAR_RANGE_INTR_MASKED bits" "0,1"
rbitfld.long 0x00 30. "SATURATE_MASKED_RED,Reduction OR of all SAR_SATURATION_INTR_MASKED bits" "0,1"
newline
rbitfld.long 0x00 7. "INJ_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
rbitfld.long 0x00 6. "INJ_RANGE_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
rbitfld.long 0x00 5. "INJ_SATURATE_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
rbitfld.long 0x00 4. "INJ_EOC_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
rbitfld.long 0x00 3. "DSI_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
rbitfld.long 0x00 2. "FW_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
rbitfld.long 0x00 1. "OVERFLOW_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
rbitfld.long 0x00 0. "EOS_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
group.long 0x280++0x03
line.long 0x00 "INJ_CHAN_CONFIG,Injection channel configuration register"
bitfld.long 0x00 31. "INJ_START_EN,Set by firmware to enable the injection channel" "0,1"
bitfld.long 0x00 30. "INJ_TAILGATING,Injection channel tailgating.?" "0: no tailgating for this channel SAR is,1: injection channel tailgating"
newline
bitfld.long 0x00 12.--13. "INJ_SAMPLE_TIME_SEL,Injection sample time select: select which of the 4 global sample times to use for this channel" "0,1,2,3"
bitfld.long 0x00 10. "INJ_AVG_EN,Averaging enable for this channel" "0,1"
newline
bitfld.long 0x00 9. "INJ_RESOLUTION,Resolution for this channel" "0: No description available,1: No description available"
bitfld.long 0x00 8. "INJ_DIFFERENTIAL_EN,Differential enable for this channel.?" "0: Single-ended voltage is measured,1: The differential voltage is measured"
newline
bitfld.long 0x00 4.--6. "INJ_PORT_ADDR,Address of the port that contains the pin to be sampled by this channel" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,?,6: No description available,7: No description available"
bitfld.long 0x00 0.--2. "INJ_PIN_ADDR,Address of the pin to be sampled by this injection channel" "0,1,2,3,4,5,6,7"
group.long 0x290++0x03
line.long 0x00 "INJ_RESULT,Injection channel result register"
rbitfld.long 0x00 31. "INJ_EOC_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
rbitfld.long 0x00 30. "INJ_RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
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rbitfld.long 0x00 29. "INJ_SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
rbitfld.long 0x00 28. "INJ_COLLISION_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "INJ_RESULT,SAR conversion result of the channel"
group.long 0x300++0x03
line.long 0x00 "MUX_SWITCH0,SARMUX Firmware switch controls"
bitfld.long 0x00 29. "MUX_FW_P7_COREIO3,Firmware control" "0: open,1: close"
bitfld.long 0x00 28. "MUX_FW_P6_COREIO2,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 27. "MUX_FW_P5_COREIO1,Firmware control" "0: open,1: close"
bitfld.long 0x00 26. "MUX_FW_P4_COREIO0,Firmware control" "0: open,1: close"
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bitfld.long 0x00 25. "MUX_FW_SARBUS1_VMINUS,Firmware control" "0: open,1: close"
bitfld.long 0x00 24. "MUX_FW_SARBUS0_VMINUS,Firmware control" "0: open,1: close"
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bitfld.long 0x00 23. "MUX_FW_SARBUS1_VPLUS,Firmware control" "0: open,1: close"
bitfld.long 0x00 22. "MUX_FW_SARBUS0_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 21. "MUX_FW_AMUXBUSB_VMINUS,Firmware control" "0: open,1: close"
bitfld.long 0x00 20. "MUX_FW_AMUXBUSA_VMINUS,Firmware control" "0: open,1: close"
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bitfld.long 0x00 19. "MUX_FW_AMUXBUSB_VPLUS,Firmware control" "0: open,1: close"
bitfld.long 0x00 18. "MUX_FW_AMUXBUSA_VPLUS,Firmware control" "0: open,1: close"
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bitfld.long 0x00 17. "MUX_FW_TEMP_VPLUS,Firmware control" "0: open,1: close"
bitfld.long 0x00 16. "MUX_FW_VSSA_VMINUS,Firmware control" "0: open,1: close"
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bitfld.long 0x00 15. "MUX_FW_P7_VMINUS,Firmware control" "0: open,1: close"
bitfld.long 0x00 14. "MUX_FW_P6_VMINUS,Firmware control" "0: open,1: close"
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bitfld.long 0x00 13. "MUX_FW_P5_VMINUS,Firmware control" "0: open,1: close"
bitfld.long 0x00 12. "MUX_FW_P4_VMINUS,Firmware control" "0: open,1: close"
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bitfld.long 0x00 11. "MUX_FW_P3_VMINUS,Firmware control" "0: open,1: close"
bitfld.long 0x00 10. "MUX_FW_P2_VMINUS,Firmware control" "0: open,1: close"
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bitfld.long 0x00 9. "MUX_FW_P1_VMINUS,Firmware control" "0: open,1: close"
bitfld.long 0x00 8. "MUX_FW_P0_VMINUS,Firmware control" "0: open,1: close"
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bitfld.long 0x00 7. "MUX_FW_P7_VPLUS,Firmware control" "0: open,1: close"
bitfld.long 0x00 6. "MUX_FW_P6_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 5. "MUX_FW_P5_VPLUS,Firmware control" "0: open,1: close"
bitfld.long 0x00 4. "MUX_FW_P4_VPLUS,Firmware control" "0: open,1: close"
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bitfld.long 0x00 3. "MUX_FW_P3_VPLUS,Firmware control" "0: open,1: close"
bitfld.long 0x00 2. "MUX_FW_P2_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 1. "MUX_FW_P1_VPLUS,Firmware control" "0: open,1: close"
bitfld.long 0x00 0. "MUX_FW_P0_VPLUS,Firmware control" "0: open,1: close"
group.long 0x304++0x03
line.long 0x00 "MUX_SWITCH_CLEAR0,SARMUX Firmware switch control clear"
bitfld.long 0x00 29. "MUX_FW_P7_COREIO3,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 28. "MUX_FW_P6_COREIO2,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 27. "MUX_FW_P5_COREIO1,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 26. "MUX_FW_P4_COREIO0,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 25. "MUX_FW_SARBUS1_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 24. "MUX_FW_SARBUS0_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 23. "MUX_FW_SARBUS1_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 22. "MUX_FW_SARBUS0_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 21. "MUX_FW_AMUXBUSB_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 20. "MUX_FW_AMUXBUSA_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 19. "MUX_FW_AMUXBUSB_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 18. "MUX_FW_AMUXBUSA_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 17. "MUX_FW_TEMP_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 16. "MUX_FW_VSSA_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 15. "MUX_FW_P7_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 14. "MUX_FW_P6_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 13. "MUX_FW_P5_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 12. "MUX_FW_P4_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 11. "MUX_FW_P3_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 10. "MUX_FW_P2_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 9. "MUX_FW_P1_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 8. "MUX_FW_P0_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 7. "MUX_FW_P7_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 6. "MUX_FW_P6_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 5. "MUX_FW_P5_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 4. "MUX_FW_P4_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 3. "MUX_FW_P3_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 2. "MUX_FW_P2_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 1. "MUX_FW_P1_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
bitfld.long 0x00 0. "MUX_FW_P0_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
group.long 0x308++0x03
line.long 0x00 "MUX_SWITCH1,SARMUX Firmware switch controls"
bitfld.long 0x00 3. "MUX_FW_ADFT1_SARBUS1,Firmware control" "0: open,1: close"
bitfld.long 0x00 2. "MUX_FW_ADFT0_SARBUS0,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 1. "MUX_FW_P5_DFT_INM,Firmware control" "0: open,1: close"
bitfld.long 0x00 0. "MUX_FW_P4_DFT_INP,Firmware control" "0: open,1: close"
group.long 0x30C++0x03
line.long 0x00 "MUX_SWITCH_CLEAR1,SARMUX Firmware switch control clear"
bitfld.long 0x00 3. "MUX_FW_ADFT1_SARBUS1,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
bitfld.long 0x00 2. "MUX_FW_ADFT0_SARBUS0,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
newline
bitfld.long 0x00 1. "MUX_FW_P5_DFT_INM,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
bitfld.long 0x00 0. "MUX_FW_P4_DFT_INP,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
group.long 0x340++0x03
line.long 0x00 "MUX_SWITCH_HW_CTRL,SARMUX switch hardware control"
bitfld.long 0x00 23. "MUX_HW_CTRL_SARBUS1,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
bitfld.long 0x00 22. "MUX_HW_CTRL_SARBUS0,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
newline
bitfld.long 0x00 19. "MUX_HW_CTRL_AMUXBUSB,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
bitfld.long 0x00 18. "MUX_HW_CTRL_AMUXBUSA,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
newline
bitfld.long 0x00 17. "MUX_HW_CTRL_TEMP,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
bitfld.long 0x00 16. "MUX_HW_CTRL_VSSA,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
newline
bitfld.long 0x00 7. "MUX_HW_CTRL_P7,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
bitfld.long 0x00 6. "MUX_HW_CTRL_P6,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
newline
bitfld.long 0x00 5. "MUX_HW_CTRL_P5,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
bitfld.long 0x00 4. "MUX_HW_CTRL_P4,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
newline
bitfld.long 0x00 3. "MUX_HW_CTRL_P3,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
bitfld.long 0x00 2. "MUX_HW_CTRL_P2,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
newline
bitfld.long 0x00 1. "MUX_HW_CTRL_P1,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
bitfld.long 0x00 0. "MUX_HW_CTRL_P0,Hardware control" "0: only firmware control,1: hardware control masked by firmware"
group.long 0x348++0x03
line.long 0x00 "MUX_SWITCH_STATUS,SARMUX switch status"
rbitfld.long 0x00 25. "MUX_FW_SARBUS1_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
rbitfld.long 0x00 24. "MUX_FW_SARBUS0_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
rbitfld.long 0x00 23. "MUX_FW_SARBUS1_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
rbitfld.long 0x00 22. "MUX_FW_SARBUS0_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
rbitfld.long 0x00 21. "MUX_FW_AMUXBUSB_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
rbitfld.long 0x00 20. "MUX_FW_AMUXBUSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
rbitfld.long 0x00 19. "MUX_FW_AMUXBUSB_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
rbitfld.long 0x00 18. "MUX_FW_AMUXBUSA_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
rbitfld.long 0x00 17. "MUX_FW_TEMP_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
rbitfld.long 0x00 16. "MUX_FW_VSSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
rbitfld.long 0x00 15. "MUX_FW_P7_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
rbitfld.long 0x00 14. "MUX_FW_P6_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
rbitfld.long 0x00 13. "MUX_FW_P5_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
rbitfld.long 0x00 12. "MUX_FW_P4_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
rbitfld.long 0x00 11. "MUX_FW_P3_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
rbitfld.long 0x00 10. "MUX_FW_P2_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
rbitfld.long 0x00 9. "MUX_FW_P1_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
rbitfld.long 0x00 8. "MUX_FW_P0_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
rbitfld.long 0x00 7. "MUX_FW_P7_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
rbitfld.long 0x00 6. "MUX_FW_P6_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
rbitfld.long 0x00 5. "MUX_FW_P5_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
rbitfld.long 0x00 4. "MUX_FW_P4_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
rbitfld.long 0x00 3. "MUX_FW_P3_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
rbitfld.long 0x00 2. "MUX_FW_P2_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
rbitfld.long 0x00 1. "MUX_FW_P1_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
rbitfld.long 0x00 0. "MUX_FW_P0_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
group.long 0x380++0x03
line.long 0x00 "PUMP_CTRL,Switch pump control"
bitfld.long 0x00 31. "ENABLED," "0,1"
bitfld.long 0x00 0. "CLOCK_SEL,Clock select" "0: external clock,1: internal clock (deprecated)"
group.long 0xF00++0x03
line.long 0x00 "ANA_TRIM,Analog trim register"
bitfld.long 0x00 3. "TRIMUNIT,Attenuation cap trimming" "0,1"
bitfld.long 0x00 0.--2. "CAP_TRIM,Attenuation cap trimming" "0,1,2,3,4,5,6,7"
group.long 0xF04++0x03
line.long 0x00 "WOUNDING,SAR wounding register"
bitfld.long 0x00 0.--1. "WOUND_RESOLUTION,Maximum SAR resolution allowed" "0: No description available,1: No description available,2: No description available,3: No description available"
tree.end
tree "SCB (Serial Communications Block (SPI/UART/I2C))"
repeat 2. (list 0. 1.) (list ad:0x40060000 ad:0x40070000)
tree "SCB$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CTRL,Generic control register"
bitfld.long 0x00 31. "ENABLED,IP enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 24.--25. "MODE,Mode of operation (3: Reserved)" "0: No description available,1: No description available,2: No description available,?..."
newline
bitfld.long 0x00 17. "BLOCK,Only used in externally clocked mode" "0,1"
bitfld.long 0x00 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')" "0,1"
bitfld.long 0x00 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation" "0,1"
newline
bitfld.long 0x00 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI)" "0,1"
bitfld.long 0x00 0.--3. "OVS,Serial interface bit period oversampling factor expressed in lP clock cycles" "0: 16 times oversampling ,1: 32 times oversampling ,2: 48 times oversampling.,3: 96 times oversampling,4: 192 times oversampling,5: 768 times oversampling,6: 1536 times oversampling,?..."
group.long 0x04++0x03
line.long 0x00 "STATUS,Generic status register"
rbitfld.long 0x00 0. "EC_BUSY,Inidicates whether the externaly clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode)" "0,1"
group.long 0x20++0x03
line.long 0x00 "SPI_CTRL,SPI control register"
bitfld.long 0x00 31. "MASTER_MODE,Master ('1') or slave ('0') mode" "0,1"
bitfld.long 0x00 26.--27. "SLAVE_SELECT,Selects one of the four SPI slave select signals:?" "0: Slave 0 SPI_SELECT[0],1: Slave 1 SPI_SELECT[1],2: Slave 2 SPI_SELECT[2],3: Slave 3 SPI_SELECT[3]Only master mode"
newline
bitfld.long 0x00 24.--25. "MODE,Submode of SPI operation (3: Reserved)" "0: No description available,1: No description available,2: No description available,?..."
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
newline
bitfld.long 0x00 4. "LATE_MISO_SAMPLE,Only applicable in master mode" "0,1"
bitfld.long 0x00 3. "CPOL,Only applicable in SPI Motorola submode" "0,1"
newline
bitfld.long 0x00 2. "CPHA,Only applicable in SPI Motorola submode" "0,1"
bitfld.long 0x00 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode" "0,1"
newline
bitfld.long 0x00 0. "CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0')" "0,1"
group.long 0x24++0x03
line.long 0x00 "SPI_STATUS,SPI status register"
hexmask.long.byte 0x00 8.--15. 1. "EZ_ADDR,SPI slave EZ address"
rbitfld.long 0x00 0. "BUS_BUSY,SPI bus is busy" "0,1"
group.long 0x40++0x03
line.long 0x00 "UART_CTRL,UART control register"
bitfld.long 0x00 24.--25. "MODE,Submode of UART operation (3: Reserved)" "0: No description available,1: No description available,2: No description available,?..."
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
group.long 0x44++0x03
line.long 0x00 "UART_TX_CTRL,UART transmitter control register"
bitfld.long 0x00 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received" "0,1"
bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7"
group.long 0x48++0x03
line.long 0x00 "UART_RX_CTRL,UART receiver control register"
bitfld.long 0x00 16.--19. "BREAK_WIDTH,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 13. "SKIP_START,Only applicable in standard UART submode" "0,1"
newline
bitfld.long 0x00 12. "LIN_MODE,Only applicable in standard UART submode" "0,1"
bitfld.long 0x00 10. "MP_MODE,Multi-processor mode" "0,1"
newline
bitfld.long 0x00 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period" "0,1"
bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behaviour when a parity check fails" "0,1"
newline
bitfld.long 0x00 6. "POLARITY,Inverts incoming RX line signal" "0,1"
bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7"
group.long 0x4C++0x03
line.long 0x00 "UART_RX_STATUS,UART receiver status register"
hexmask.long.word 0x00 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver"
group.long 0x60++0x03
line.long 0x00 "I2C_CTRL,I2C control register"
bitfld.long 0x00 31. "MASTER_MODE,Master mode enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
bitfld.long 0x00 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only" "0: clock stretching is performed (till the..,1: a received data element byte the slave is"
newline
bitfld.long 0x00 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0')" "0: clock stretching is performed (till the,1: a received (matching or general) slave address"
bitfld.long 0x00 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full" "0,1"
newline
bitfld.long 0x00 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full" "0,1"
bitfld.long 0x00 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address" "0,1"
newline
bitfld.long 0x00 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full" "0,1"
bitfld.long 0x00 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full" "0,1"
newline
bitfld.long 0x00 4.--7. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x64++0x03
line.long 0x00 "I2C_STATUS,I2C status register"
hexmask.long.byte 0x00 8.--15. 1. "EZ_ADDR,I2C slave EZ address"
rbitfld.long 0x00 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0')" "0,1"
newline
rbitfld.long 0x00 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0')" "0,1"
rbitfld.long 0x00 0. "BUS_BUSY,I2C bus is busy" "0,1"
group.long 0x68++0x03
line.long 0x00 "I2C_M_CMD,I2C master command register"
bitfld.long 0x00 4. "M_STOP,When '1' attempt to transmit a STOP" "0,1"
bitfld.long 0x00 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1"
newline
bitfld.long 0x00 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
bitfld.long 0x00 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle" "0,1"
newline
bitfld.long 0x00 0. "M_START,When '1' transmit a START or REPEATED START" "0,1"
group.long 0x6C++0x03
line.long 0x00 "I2C_S_CMD,I2C slave command register"
bitfld.long 0x00 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1"
bitfld.long 0x00 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
group.long 0x70++0x03
line.long 0x00 "I2C_CFG,I2C configuration register"
bitfld.long 0x00 27. "SDA_FILT_OUT_ENABLED,I2C SDA output delay filter enabled" "0,1"
bitfld.long 0x00 26. "SDA_FILT_OUT_HS,When '0': 50 ns filter" "0,1"
newline
bitfld.long 0x00 25. "SCL_FILT_ENABLED,I2C SCL filter enabled" "0,1"
bitfld.long 0x00 24. "SCL_FILT_HS,When '0': 50 ns filter" "0,1"
newline
bitfld.long 0x00 17. "SDA_FILT_ENABLED,I2C SDA filter enabled" "0,1"
bitfld.long 0x00 16. "SDA_FILT_HS,When '0': 50 ns filter" "0,1"
newline
bitfld.long 0x00 10.--11. "SDA_FILT_OUT_TRIM,Trim bits for the I2C SDA filter in the SDA output path (for SCL to SDA hold delay)" "0,1,2,3"
bitfld.long 0x00 8.--9. "SDA_FILT_OUT_HYS,Trim bits for the I2C SDA filter in the SDA output path (for SCL to SDA hold delay)" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "SCL_FILT_TRIM,Trim bits for the I2C SCL filter" "0,1,2,3"
bitfld.long 0x00 4.--5. "SCL_FILT_HYS,Trim bits for the I2C SCL filter" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "SDA_FILT_TRIM,Trim bits for the I2C SDA filter" "0,1,2,3"
bitfld.long 0x00 0.--1. "SDA_FILT_HYS,Trim bits for the I2C SDA filter" "0,1,2,3"
group.long 0x100++0x03
line.long 0x00 "BIST_CONTROL,BIST control register"
bitfld.long 0x00 29. "RAM_GO,Firmare/Probe sets this field to start a SRAM BIST access sequence to a single SRAM location" "0,1"
rbitfld.long 0x00 28. "RAM_FAIL,Indicates pass/fail of the SRAM operation sequence" "0,1"
newline
bitfld.long 0x00 27. "RAM_WORD," "0,1"
bitfld.long 0x00 26. "RAM_PREADR," "0,1"
newline
bitfld.long 0x00 24.--25. "RAM_OPCNT,Number of SRAM operations to execute when fired using RAM_GO.?0: only execute RAM_OP1 (opt plus PREADDR)?1: execute RAM_OP1 RAM_OP2 (opt plus PREADDR)?2: execute RAM_OP1 RAM_OP2 RAM_OP3 (opt plus PREADDR)?3: execute RAM_OP1 RAM_OP2 RAM_OP3.." "0,1,2,3"
bitfld.long 0x00 22.--23. "RAM_OP4,Fourth SRAM BIST operation:?0: Write BIST_DATA?1: Write ~BIST_DATA?2: Read and compare against BIST_DATA?3: Read and compare against ~BIST_DATA" "0,1,2,3"
newline
bitfld.long 0x00 20.--21. "RAM_OP3,Third SRAM BIST operation:?0: Write BIST_DATA?1: Write ~BIST_DATA?2: Read and compare against BIST_DATA?3: Read and compare against ~BIST_DATA" "0,1,2,3"
bitfld.long 0x00 18.--19. "RAM_OP2,Second SRAM BIST operation:?0: Write BIST_DATA?1: Write ~BIST_DATA?2: Read and compare against BIST_DATA?3: Read and compare against ~BIST_DATA" "0,1,2,3"
newline
bitfld.long 0x00 16.--17. "RAM_OP1,First SRAM BIST operation:?0: Write BIST_DATA?1: Write ~BIST_DATA?2: Read and compare against BIST_DATA?3: Read and compare against ~BIST_DATA" "0,1,2,3"
bitfld.long 0x00 0.--4. "RAM_ADDR,Address for SRAM BIST sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x104++0x03
line.long 0x00 "BIST_DATA,BIST data register"
hexmask.long.word 0x00 0.--15. 1. "RAM_DATA,Data pattern for BIST sequence"
group.long 0x200++0x03
line.long 0x00 "TX_CTRL,Transmitter control register"
bitfld.long 0x00 31. "ENABLED,Transmitter enabled" "0,1"
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
newline
bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x204++0x03
line.long 0x00 "TX_FIFO_CTRL,Transmitter FIFO control register"
bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated" "0,1"
newline
bitfld.long 0x00 0.--2. "TRIGGER_LEVEL,Trigger level" "0,1,2,3,4,5,6,7"
group.long 0x208++0x03
line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO status register"
rbitfld.long 0x00 24.--26. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 16.--18. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0')" "0,1"
rbitfld.long 0x00 0.--3. "USED,Amount of enties in the transmitter FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x03
line.long 0x00 "TX_FIFO_WR,Transmitter FIFO write register"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data frame written into the transmitter FIFO"
group.long 0x300++0x03
line.long 0x00 "RX_CTRL,Receiver control register"
bitfld.long 0x00 31. "ENABLED,Receiver enabled" "0,1"
bitfld.long 0x00 9. "MEDIAN,Median filter" "0,1"
newline
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x304++0x03
line.long 0x00 "RX_FIFO_CTRL,Receiver FIFO control register"
bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated" "0,1"
newline
bitfld.long 0x00 0.--2. "TRIGGER_LEVEL,Trigger level" "0,1,2,3,4,5,6,7"
group.long 0x308++0x03
line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO status register"
rbitfld.long 0x00 24.--26. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 16.--18. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0')" "0,1"
rbitfld.long 0x00 0.--3. "USED,Amount of enties in the receiver FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x310++0x03
line.long 0x00 "RX_MATCH,Slave address and mask register"
hexmask.long.byte 0x00 16.--23. 1. "MASK,Slave device address mask"
hexmask.long.byte 0x00 0.--7. 1. "ADDR,Slave device address"
group.long 0x340++0x03
line.long 0x00 "RX_FIFO_RD,Receiver FIFO read register"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO"
group.long 0x344++0x03
line.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO read register"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO"
repeat 16. (strings "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x400)++0x03
line.long 0x00 "EZ_DATA$1,EZ memory location registers"
hexmask.long.byte 0x00 0.--7. 1. "EZ_DATA,Data in EZ memory location"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x440)++0x03
line.long 0x00 "EZ_DATA$1,EZ memory location registers"
hexmask.long.byte 0x00 0.--7. 1. "EZ_DATA,Data in EZ memory location"
repeat.end
group.long 0xE00++0x03
line.long 0x00 "INTR_CAUSE,Active clocked interrupt signal register"
rbitfld.long 0x00 5. "SPI_EC,Externally clocked SPI interrupt active ( interrupt_spi_ec ): INTR_SPI_EC_MASKED != 0" "0,1"
rbitfld.long 0x00 4. "I2C_EC,Externally clock I2C interrupt active ( interrupt_i2c_ec ): INTR_I2C_EC_MASKED != 0" "0,1"
newline
rbitfld.long 0x00 3. "RX,Receiver interrupt active ( interrupt_rx ): INTR_RX_MASKED != 0" "0,1"
rbitfld.long 0x00 2. "TX,Transmitter interrupt active ( interrupt_tx ): INTR_TX_MASKED != 0" "0,1"
newline
rbitfld.long 0x00 1. "S,Slave interrupt active ( interrupt_slave ): INTR_S_MASKED != 0" "0,1"
rbitfld.long 0x00 0. "M,Master interrupt active ( interrupt_master ): INTR_M_MASKED != 0" "0,1"
group.long 0xE80++0x03
line.long 0x00 "INTR_I2C_EC,Externally clocked I2C interrupt request register"
bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred (only available in EZ mode)" "0,1"
bitfld.long 0x00 1. "EZ_STOP,STOP detection (only available in EZ mode)" "0,1"
newline
bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1"
group.long 0xE88++0x03
line.long 0x00 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask register"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0xE8C++0x03
line.long 0x00 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked register"
rbitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1"
group.long 0xEC0++0x03
line.long 0x00 "INTR_SPI_EC,Externally clocked SPI interrupt request register"
bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1"
bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1"
newline
bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1"
group.long 0xEC8++0x03
line.long 0x00 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask register"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0xECC++0x03
line.long 0x00 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked register"
rbitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1"
group.long 0xF00++0x03
line.long 0x00 "INTR_M,Master interrupt request register"
bitfld.long 0x00 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent and the transmit FIFO is empty" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,I2C master STOP" "0,1"
bitfld.long 0x00 2. "I2C_ACK,I2C master acknowledgement" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,I2C master negative acknowledgement" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line" "0,1"
group.long 0xF04++0x03
line.long 0x00 "INTR_M_SET,Master interrupt set request register"
bitfld.long 0x00 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xF08++0x03
line.long 0x00 "INTR_M_MASK,Master interrupt mask register"
bitfld.long 0x00 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0xF0C++0x03
line.long 0x00 "INTR_M_MASKED,Master interrupt masked request register"
rbitfld.long 0x00 9. "SPI_DONE,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
group.long 0xF40++0x03
line.long 0x00 "INTR_S,Slave interrupt request register"
bitfld.long 0x00 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer" "0,1"
bitfld.long 0x00 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occured" "0,1"
newline
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition)" "0,1"
newline
bitfld.long 0x00 7. "I2C_GENERAL,I2C slave general call address received" "0,1"
bitfld.long 0x00 6. "I2C_ADDR_MATCH,I2C slave matching address received" "0,1"
newline
bitfld.long 0x00 5. "I2C_START,I2C slave START received" "0,1"
bitfld.long 0x00 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed)" "0,1"
newline
bitfld.long 0x00 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed)" "0,1"
bitfld.long 0x00 2. "I2C_ACK,I2C slave acknowledgement received" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,I2C slave negative acknowledgement received" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1')" "0,1"
group.long 0xF44++0x03
line.long 0x00 "INTR_S_SET,Slave interrupt set request register"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xF48++0x03
line.long 0x00 "INTR_S_MASK,Slave interrupt mask register"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "I2C_START,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0xF4C++0x03
line.long 0x00 "INTR_S_MASKED,Slave interrupt masked request register"
rbitfld.long 0x00 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 7. "I2C_GENERAL,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 5. "I2C_START,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
group.long 0xF80++0x03
line.long 0x00 "INTR_TX,Transmitter interrupt request register"
bitfld.long 0x00 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line" "0,1"
bitfld.long 0x00 9. "UART_DONE,UART transmitter done event" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode" "0,1"
bitfld.long 0x00 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full TX FIFO" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,TX FIFO is empty i.e" "0,1"
bitfld.long 0x00 1. "NOT_FULL,TX FIFO is not full" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in SCB_TX_FIFO_CTL" "0,1"
group.long 0xF84++0x03
line.long 0x00 "INTR_TX_SET,Transmitter interrupt set request register"
bitfld.long 0x00 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xF88++0x03
line.long 0x00 "INTR_TX_MASK,Transmitter interrupt mask register"
bitfld.long 0x00 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0xF8C++0x03
line.long 0x00 "INTR_TX_MASKED,Transmitter interrupt masked request register"
rbitfld.long 0x00 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 9. "UART_DONE,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 8. "UART_NACK,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 4. "EMPTY,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 1. "NOT_FULL,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
group.long 0xFC0++0x03
line.long 0x00 "INTR_RX,Receiver interrupt request register"
bitfld.long 0x00 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,LIN baudrate detection is completed" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Parity error in received data frame" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Frame error in received data frame" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full RX FIFO" "0,1"
bitfld.long 0x00 3. "FULL,RX FIFO is full" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,RX FIFO is not empty" "0,1"
bitfld.long 0x00 0. "TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL" "0,1"
group.long 0xFC4++0x03
line.long 0x00 "INTR_RX_SET,Receiver interrupt set request register"
bitfld.long 0x00 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 3. "FULL,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xFC8++0x03
line.long 0x00 "INTR_RX_MASK,Receiver interrupt mask register"
bitfld.long 0x00 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 3. "FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0xFCC++0x03
line.long 0x00 "INTR_RX_MASKED,Receiver interrupt masked request register"
rbitfld.long 0x00 11. "BREAK_DETECT,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 10. "BAUD_DETECT,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 9. "PARITY_ERROR,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 8. "FRAME_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 3. "FULL,Logical and of corresponding request and mask bits" "0,1"
newline
rbitfld.long 0x00 2. "NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
tree.end
repeat.end
tree.end
tree "SFLASH (Supervisory Flash Area (Cypress Trim & Wounding Info))"
base ad:0xFFFF000
repeat 16. (strings "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x00)++0x00
line.byte 0x00 "PROT_ROW$1,Per Page Write Protection"
hexmask.byte 0x00 0.--7. 1. "DATA8,Protection Data (1b per page)"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x10)++0x00
line.byte 0x00 "PROT_ROW$1,Per Page Write Protection"
hexmask.byte 0x00 0.--7. 1. "DATA8,Protection Data (1b per page)"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x20)++0x00
line.byte 0x00 "PROT_ROW$1,Per Page Write Protection"
hexmask.byte 0x00 0.--7. 1. "DATA8,Protection Data (1b per page)"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x30)++0x00
line.byte 0x00 "PROT_ROW$1,Per Page Write Protection"
hexmask.byte 0x00 0.--7. 1. "DATA8,Protection Data (1b per page)"
repeat.end
group.byte 0x7F++0x00
line.byte 0x00 "PROT_PROTECTION,Protection Level"
bitfld.byte 0x00 0.--1. "PROT_LEVEL,Current Protection Mode - note that encoding is different from CPUSS_PROTECTION !!" "0: No description available,1: No description available,2: No description available,3: No description available"
repeat 16. (strings "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x100)++0x03
line.long 0x00 "AV_PAIRS_32B$1,32b Addr/Value pair Section"
hexmask.long 0x00 0.--31. 1. "DATA32,Address or Value Word"
repeat.end
group.long 0x140++0x03
line.long 0x00 "CPUSS_WOUNDING,CPUSS Wounding Register"
hexmask.long 0x00 0.--31. 1. "DATA32,Data to use for register"
group.long 0x144++0x03
line.long 0x00 "SILICON_ID,Silicon ID"
hexmask.long.word 0x00 0.--15. 1. "ID,Silicon ID"
group.long 0x148++0x03
line.long 0x00 "CPUSS_PRIV_RAM,RAM Privileged Limit"
hexmask.long 0x00 0.--31. 1. "DATA32,Data to use for register"
group.long 0x14C++0x03
line.long 0x00 "CPUSS_PRIV_FLASH,Flash Privileged Limit"
hexmask.long 0x00 0.--31. 1. "DATA32,Data to use for register"
group.word 0x150++0x01
line.word 0x00 "HIB_KEY_DELAY,Hibernate wakeup value for PWR_KEY_DELAY"
hexmask.word 0x00 0.--9. 1. "WAKEUP_HOLDOFF,Delay (in 12MHz IMO clock cycles) to wait for references to settle on wakeup from hibernate/deepsleep"
group.word 0x152++0x01
line.word 0x00 "DPSLP_KEY_DELAY,DeepSleep wakeup value for PWR_KEY_DELAY"
hexmask.word 0x00 0.--9. 1. "WAKEUP_HOLDOFF,Delay (in 12MHz IMO clock cycles) to wait for references to settle on wakeup from hibernate/deepsleep"
group.byte 0x154++0x00
line.byte 0x00 "SWD_CONFIG,SWD pinout selector (not present in TSG4/TSG5-M)"
bitfld.byte 0x00 0. "SWD_SELECT," "0,1"
group.long 0x158++0x03
line.long 0x00 "SWD_LISTEN,Listen Window Length"
hexmask.long 0x00 0.--31. 1. "CYCLES,Number of clock cycles"
group.long 0x15C++0x03
line.long 0x00 "FLASH_START,Flash Image Start Address"
hexmask.long 0x00 0.--31. 1. "ADDRESS,Start Address"
group.byte 0x160++0x00
line.byte 0x00 "CSD_TRIM1_HVIDAC,CSD Trim Data for HVIDAC operation"
hexmask.byte 0x00 0.--7. 1. "TRIM8,Trim data"
group.byte 0x161++0x00
line.byte 0x00 "CSD_TRIM2_HVIDAC,CSD Trim Data for HVIDAC operation"
hexmask.byte 0x00 0.--7. 1. "TRIM8,Trim data"
group.byte 0x162++0x00
line.byte 0x00 "CSD_TRIM1_CSD,CSD Trim Data for (normal) CSD operation"
hexmask.byte 0x00 0.--7. 1. "TRIM8,Trim data"
group.byte 0x163++0x00
line.byte 0x00 "CSD_TRIM2_CSD,CSD Trim Data for (normal) CSD operation"
hexmask.byte 0x00 0.--7. 1. "TRIM8,Trim data"
group.word 0x164++0x01
line.word 0x00 "SAR_TEMP_MULTIPLIER,SAR Temperature Sensor Multiplication Factor"
hexmask.word 0x00 0.--15. 1. "TEMP_MULTIPLIER,Multiplier value for SAR temperature sensor in fixed point 0.16 format"
group.word 0x166++0x01
line.word 0x00 "SAR_TEMP_OFFSET,SAR Temperature Sensor Offset"
hexmask.word 0x00 0.--15. 1. "TEMP_OFFSET,Offset value for SAR temperature sensor in fixed point 10.6 format"
group.byte 0x169++0x00
line.byte 0x00 "SKIP_CHECKSUM,Checksum Skip Option Register"
hexmask.byte 0x00 0.--7. 1. "SKIP,"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 )
group.byte ($2+0x170)++0x00
line.byte 0x00 "PROT_VIRGINKEY$1,Virgin Protection Mode Key"
hexmask.byte 0x00 0.--7. 1. "KEY8,Key Byte"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x00 0x01 0x02 )
group.byte ($2+0x178)++0x00
line.byte 0x00 "DIE_LOT$1,Lot Number (3 bytes)"
hexmask.byte 0x00 0.--7. 1. "LOT,Lot Number Byte"
repeat.end
group.byte 0x17B++0x00
line.byte 0x00 "DIE_WAFER,Wafer Number"
hexmask.byte 0x00 0.--7. 1. "WAFER,Wafer Number"
group.byte 0x17C++0x00
line.byte 0x00 "DIE_X,X Position on Wafer CRI Pass/Fail Bin"
bitfld.byte 0x00 6.--7. "CRI_PASS,CRI Pass Bin (1-3) or 0 (Fail Bin)" "0,1,2,3"
bitfld.byte 0x00 0.--5. "X,X Position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x17D++0x00
line.byte 0x00 "DIE_Y,Y Position on Wafer CHI Pass/Fail Bin"
bitfld.byte 0x00 6.--7. "CHI_PASS,CHI Pass Bin (1-3) or 0 (Fail Bin)" "0,1,2,3"
bitfld.byte 0x00 0.--5. "Y,Y Position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x17E++0x00
line.byte 0x00 "DIE_SORT,Sort1/2/3 Pass/Fail Bin"
bitfld.byte 0x00 4.--5. "S3_PASS,SORT3 Pass Bin (1-3) or 0 (Fail Bin)" "0,1,2,3"
bitfld.byte 0x00 2.--3. "S2_PASS,SORT2 Pass Bin (1-3) or 0 (Fail Bin)" "0,1,2,3"
newline
bitfld.byte 0x00 0.--1. "S1_PASS,SORT1 Pass Bin (1-3) or 0 (Fail Bin)" "0,1,2,3"
group.byte 0x17F++0x00
line.byte 0x00 "DIE_MINOR,Minor Revision Number"
hexmask.byte 0x00 0.--7. 1. "MINOR,Minor revision number"
repeat 16. (strings "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "10" "11" "12" "13" "14" "15" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
group.byte ($2+0x180)++0x00
line.byte 0x00 "PE_TE_DATA$1,PE/TE Data"
hexmask.byte 0x00 0.--7. 1. "DATA8,PE/TE Data"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
group.byte ($2+0x190)++0x00
line.byte 0x00 "PE_TE_DATA$1,PE/TE Data"
hexmask.byte 0x00 0.--7. 1. "DATA8,PE/TE Data"
repeat.end
group.long 0x1A0++0x03
line.long 0x00 "PP,Preprogram Settings"
bitfld.long 0x00 28.--31. "NDAC,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PDAC,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "PERIOD,Period of timer (in units of 36 MHz IMO clock periods)"
group.long 0x1A4++0x03
line.long 0x00 "E,Erase Settings"
bitfld.long 0x00 28.--31. "NDAC,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PDAC,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "PERIOD,Period of timer (in units of 36 MHz IMO clock periods)"
group.long 0x1A8++0x03
line.long 0x00 "P,Program Settings"
bitfld.long 0x00 28.--31. "NDAC,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PDAC,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "PERIOD,Period of timer (in units of 36 MHz IMO clock periods)"
group.long 0x1AC++0x03
line.long 0x00 "EA_E,Erase All - Erase Settings"
bitfld.long 0x00 28.--31. "NDAC,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PDAC,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "PERIOD,Period of timer (in units of 36 MHz IMO clock periods)"
group.long 0x1B0++0x03
line.long 0x00 "EA_P,Erase All - Program Settings"
bitfld.long 0x00 28.--31. "NDAC,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PDAC,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "PERIOD,Period of timer (in units of 36 MHz IMO clock periods)"
group.long 0x1B4++0x03
line.long 0x00 "ES_E,Erase Sector - Erase Settings"
bitfld.long 0x00 28.--31. "NDAC,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PDAC,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "PERIOD,Period of timer (in units of 36 MHz IMO clock periods)"
group.long 0x1B8++0x03
line.long 0x00 "ES_P_EO,Erase Sector - Program EO Settings"
bitfld.long 0x00 28.--31. "NDAC,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "PDAC,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.tbyte 0x00 0.--23. 1. "PERIOD,Period of timer (in units of 36 MHz IMO clock periods)"
group.byte 0x1BC++0x00
line.byte 0x00 "E_VCTAT,Bandgap Trim Register"
bitfld.byte 0x00 6. "VCTAT_ENABLE,Enable VCTAT block" "0,1"
bitfld.byte 0x00 4.--5. "VCTAT_VOLTAGE,Output voltage absolute trim" "0,1,2,3"
newline
bitfld.byte 0x00 0.--3. "VCTAT_SLOPE,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x1BD++0x00
line.byte 0x00 "P_VCTAT,Bandgap Trim Register"
bitfld.byte 0x00 6. "VCTAT_ENABLE,Enable VCTAT block" "0,1"
bitfld.byte 0x00 4.--5. "VCTAT_VOLTAGE,Output voltage absolute trim" "0,1,2,3"
newline
bitfld.byte 0x00 0.--3. "VCTAT_SLOPE,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x1BE++0x00
line.byte 0x00 "MARGIN,Margin DAC Control Register"
hexmask.byte 0x00 0.--7. 1. "MDAC,Margin DAC input"
group.byte 0x1BF++0x00
line.byte 0x00 "SPCIF_TRIM1,BDAC control register"
bitfld.byte 0x00 0.--3. "BDAC,BDAC flash input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x1C0++0x00
line.byte 0x00 "IMO_MAXF0,Max frequency for trim pair"
bitfld.byte 0x00 0.--5. "MAXFREQ,Max frequency (3..48) at which IMO_ABS/TMPCO3 is valid (range is IMO_MAXF2+1 .. IMO_MAXF3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1C1++0x00
line.byte 0x00 "IMO_ABS0,Value for PWR_BG_TRIM4 (ICTAT trim for IMO current reference)"
bitfld.byte 0x00 0.--5. "ABS_TRIM_IMO,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1C2++0x00
line.byte 0x00 "IMO_TMPCO0,Value for PWR_BG_TRIM5 (ICTAT tempco for IMO current reference)"
bitfld.byte 0x00 0.--5. "TMPCO_TRIM_IMO,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1C3++0x00
line.byte 0x00 "IMO_MAXF1,Max frequency for trim pair"
bitfld.byte 0x00 0.--5. "MAXFREQ,Max frequency (3..48) at which IMO_ABS/TMPCO3 is valid (range is IMO_MAXF2+1 .. IMO_MAXF3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1C4++0x00
line.byte 0x00 "IMO_ABS1,Value for PWR_BG_TRIM4 (ICTAT trim for IMO current reference)"
bitfld.byte 0x00 0.--5. "ABS_TRIM_IMO,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1C5++0x00
line.byte 0x00 "IMO_TMPCO1,Value for PWR_BG_TRIM5 (ICTAT tempco for IMO current reference)"
bitfld.byte 0x00 0.--5. "TMPCO_TRIM_IMO,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1C6++0x00
line.byte 0x00 "IMO_MAXF2,Max frequency for trim pair"
bitfld.byte 0x00 0.--5. "MAXFREQ,Max frequency (3..48) at which IMO_ABS/TMPCO3 is valid (range is IMO_MAXF2+1 .. IMO_MAXF3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1C7++0x00
line.byte 0x00 "IMO_ABS2,Value for PWR_BG_TRIM4 (ICTAT trim for IMO current reference)"
bitfld.byte 0x00 0.--5. "ABS_TRIM_IMO,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1C8++0x00
line.byte 0x00 "IMO_TMPCO2,Value for PWR_BG_TRIM5 (ICTAT tempco for IMO current reference)"
bitfld.byte 0x00 0.--5. "TMPCO_TRIM_IMO,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1C9++0x00
line.byte 0x00 "IMO_MAXF3,Max frequency for trim pair"
bitfld.byte 0x00 0.--5. "MAXFREQ,Max frequency (3..48) at which IMO_ABS/TMPCO3 is valid (range is IMO_MAXF2+1 .. IMO_MAXF3)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1CA++0x00
line.byte 0x00 "IMO_ABS3,Value for PWR_BG_TRIM4 (ICTAT trim for IMO current reference)"
bitfld.byte 0x00 0.--5. "ABS_TRIM_IMO,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1CB++0x00
line.byte 0x00 "IMO_TMPCO3,Value for PWR_BG_TRIM5 (ICTAT tempco for IMO current reference)"
bitfld.byte 0x00 0.--5. "TMPCO_TRIM_IMO,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1CC++0x00
line.byte 0x00 "IMO_ABS4,Value for PWR_BG_TRIM4 (ICTAT trim for IMO current reference)"
bitfld.byte 0x00 0.--5. "ABS_TRIM_IMO,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.byte 0x1CD++0x00
line.byte 0x00 "IMO_TMPCO4,Value for PWR_BG_TRIM5 (ICTAT tempco for IMO current reference)"
bitfld.byte 0x00 0.--5. "TMPCO_TRIM_IMO,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 16. (strings "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "10" "11" "12" "13" "14" "15" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
group.byte ($2+0x1D0)++0x00
line.byte 0x00 "IMO_TRIM$1,IMO Trim Register"
hexmask.byte 0x00 0.--7. 1. "OFFSET,Frequency trim bits"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
group.byte ($2+0x1E0)++0x00
line.byte 0x00 "IMO_TRIM$1,IMO Trim Register"
hexmask.byte 0x00 0.--7. 1. "OFFSET,Frequency trim bits"
repeat.end
repeat 14. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D )
group.byte ($2+0x1F0)++0x00
line.byte 0x00 "IMO_TRIM$1,IMO Trim Register"
hexmask.byte 0x00 0.--7. 1. "OFFSET,Frequency trim bits"
repeat.end
group.word 0x1FE++0x01
line.word 0x00 "CHECKSUM,Boot Checksum"
hexmask.word 0x00 0.--15. 1. "CHECKSUM,Checksum of fixed data checked during boot"
tree.end
tree "SPCIF (Flash Control Interface)"
base ad:0x400E0000
group.long 0x00++0x03
line.long 0x00 "GEOMETRY,Flash/NVL geometry information"
bitfld.long 0x00 31. "DE_CPD_LP," "0,1"
hexmask.long.byte 0x00 24.--30. 1. "NVL,NVL Size in bytes"
newline
rbitfld.long 0x00 22.--23. "FLASH_ROW,Flash row size in 128B units" "0,1,2,3"
rbitfld.long 0x00 20.--21. "NUM_FLASH,Number of flash arrays" "0,1,2,3"
newline
rbitfld.long 0x00 16.--19. "SFLASH,Supervisory Flash Size in 256B segments" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "FLASH,Flash size in 256B segments"
group.long 0x1C++0x03
line.long 0x00 "NVL_WR_DATA,NVL Write Data Register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,Data to be written to NVL array"
tree.end
tree "SROM_DATA (No description available)"
base ad:0x10000000
tree.end
tree "SRSS (SRSSv2 Registers (Power Clock Reset))"
base ad:0x400B0000
group.long 0x00++0x03
line.long 0x00 "PWR_CONTROL,Power Mode Control"
bitfld.long 0x00 31. "HIBERNATE,Selects between HIBERNATE/DEEPSLEEP modes when Cortex-M0 enters low power mode (SleepDeep)" "0: No description available,1: No description available"
bitfld.long 0x00 29. "LFCLK_SHORT,Short Vcclfclk and Vccdpslp power rails in DeepSleep power mode" "0,1"
newline
bitfld.long 0x00 28. "HIBERNATE_DISABLE," "0,1"
bitfld.long 0x00 27. "FIMO_DISABLE,This bit is asserted during the boot process?0: Forces IMO to operate at 12MHz ignore its frequency and trim settings and operate independent on its external references.?1: Turns IMO into normal operational mode" "0,1"
newline
bitfld.long 0x00 25. "HVMON_RELOAD,Firmware writes 1 to reload HV State in hibernate shadow copy" "0,1"
bitfld.long 0x00 24. "HVMON_ENABLE," "0,1"
newline
bitfld.long 0x00 23. "EXT_VCCD,Indicates that Vccd is provided externally (on Vccd pin)" "0,1"
rbitfld.long 0x00 5. "LPM_READY,Indicates whether the low power mode regulators are ready to enter DEEPSLEEP or HIBERNATE mode" "0,1"
newline
rbitfld.long 0x00 4. "DEBUG_SESSION,Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)" "0: No description available,1: No description available"
rbitfld.long 0x00 0.--3. "POWER_MODE,Current power mode of the device" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,?..."
group.long 0x04++0x03
line.long 0x00 "PWR_INTR,Power System Interrupt Register"
bitfld.long 0x00 1. "LVD,Indicates an Low Voltage Detect interrupt" "0,1"
group.long 0x08++0x03
line.long 0x00 "PWR_INTR_MASK,Power System Interrupt Mask Register"
bitfld.long 0x00 1. "LVD," "0,1"
group.long 0x0C++0x03
line.long 0x00 "PWR_KEY_DELAY,Power System Key&Delay Register"
hexmask.long.word 0x00 0.--9. 1. "WAKEUP_HOLDOFF,Delay (in 12MHz IMO clock cycles) to wait for references to settle on wakeup from hibernate/deepsleep"
group.long 0x10++0x03
line.long 0x00 "PWR_PWRSYS_CONFIG,Power System Trim and Configuration"
bitfld.long 0x00 9. "HIB_TEST_REP,When set the enhanced replica load regulation circuit is enabled" "0,1"
bitfld.long 0x00 8. "HIB_TEST_EN,Bias control for the DSBOD/HBOD" "0,1"
group.long 0x14++0x03
line.long 0x00 "PWR_BG_CONFIG,Bandgap Trim and Configuration"
bitfld.long 0x00 16.--18. "VREF_EN,Reference voltage enable" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8. "BG_DFT_VCORE_SEL,ADFT mux select for Bandgap characterization (engineering only)" "0,1"
newline
bitfld.long 0x00 6.--7. "BG_DFT_ICORE_SEL,ADFT mux select for Bandgap characterization (engineering only)" "0,1,2,3"
bitfld.long 0x00 5. "BG_DFT_CORE_SEL,ADFT mux select for Bandgap characterization (engineering only)" "0,1"
newline
bitfld.long 0x00 1.--4. "BG_DFT_VREF_SEL,ADFT mux select for Reference System characterization (engineering only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "BG_DFT_EN,Enables DFT capability for Bandgap" "0,1"
group.long 0x18++0x03
line.long 0x00 "PWR_VMON_CONFIG,Voltage Monitoring Trim and Configuration"
bitfld.long 0x00 8.--9. "VMON_ADFT_SEL,ADFT mux select for HVPOR PBOD and LVD circuits (engineering only)" "0,1,2,3"
bitfld.long 0x00 5.--7. "VMON_DDFT_SEL,DDFT mux select for HVPOR PBOD and LVD circuits (engineering only)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 1.--4. "LVD_SEL,Threshold selection for Low Voltage Detect circuit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "LVD_EN,Enable Low Voltage Detect circuit" "0,1"
group.long 0x1C++0x03
line.long 0x00 "PWR_DFT_SELECT,Power DFT Mode Selection Register"
bitfld.long 0x00 31. "POWER_UP_HIBDPSLP,When set forces pwrg_actdig=1 for hibernate/deepsleep circuits" "0,1"
bitfld.long 0x00 30. "POWER_UP_ACTIVE,When set forces pwrgood=1 for active regulator" "0,1"
newline
bitfld.long 0x00 29. "IMO_REFGEN_DIS,Disables the IMO reference generator to allow testing the current references" "0,1"
bitfld.long 0x00 28. "HVMON_DFT_OVR,Overrides the trim values coming from NVLatches to the values stored in the HV Monitor" "0,1"
newline
bitfld.long 0x00 27. "NWELL_DIS,Controls the vnwell level during deep sleep and hibernate" "0,1"
bitfld.long 0x00 26. "BREF_TESTMODE,Puts the bootref in testmode" "0,1"
newline
bitfld.long 0x00 25. "BREF_REFSW,Controls the power system reference source?0: boot reference?1: Low voltage bandgap (LVBG)?Using the LVBG reference improves PSRR" "0,1"
bitfld.long 0x00 24. "BREF_OUTEN,Enables the output stage of the LDO reference selector" "0,1"
newline
bitfld.long 0x00 23. "BREF_EN,Enables the boot reference currents" "0,1"
bitfld.long 0x00 22. "QUIET_EN,Force Vccq regulator on/off" "0,1"
newline
bitfld.long 0x00 20. "LFCLK_OPEN,Force switch between Vcclfclk and Vccdpslp open" "0,1"
bitfld.long 0x00 19. "QUIET_OPEN,Force switch between Vccq and Vccdpslp open" "0,1"
newline
bitfld.long 0x00 18. "DEEPSLEEP_OPEN,Force switch between Vccdpslp and Vccd open" "0,1"
bitfld.long 0x00 17. "HIBERNATE_OPEN,Force switch between Vcchib and Vccdpslp open" "0,1"
newline
bitfld.long 0x00 16. "NWELL_OPEN,Force switch between Vnwell and Vcchib open" "0,1"
bitfld.long 0x00 15. "RSVD_BYPASS,Reserved unused register" "0,1"
newline
bitfld.long 0x00 14. "DEEPSLEEP_EN,Force DeepSleep Regulator on" "0,1"
bitfld.long 0x00 13. "POWER_UP_RAW_CTL,Value to force onto power_up_raw_hv" "0,1"
newline
bitfld.long 0x00 12. "POWER_UP_RAW_BYP,When set the LPCOMP output is controllable by POWER_UP_RAW_CTL" "0,1"
bitfld.long 0x00 11. "IPOR_EN,Force IPOR_EN signal high" "0,1"
newline
bitfld.long 0x00 10. "BLEED_EN,When set enables bleeder cells on various switched power nets to accelerate discharge during retention testing" "0,1"
bitfld.long 0x00 9. "LPCOMP_DIS,When set disables the LPCOMP" "0,1"
newline
bitfld.long 0x00 8. "ACTIVE_INRUSH_DIS,Force disable of active regulator inrush current limiter" "0,1"
bitfld.long 0x00 7. "ACTIVE_EN,Force active regulator on" "0,1"
newline
bitfld.long 0x00 6. "BYPASS,Forces regulator into bypass mode" "0,1"
bitfld.long 0x00 3.--5. "TVMON2_SEL,Select source for PWRSYS ADFT output #2:?0: not connected (default)?1: not connected?2: Boot Reference biasn?3: Boot Reference nprot?4: DO NOT USE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "TVMON1_SEL,Select source for PWRSYS ADFT output #1:?0: not connected (default)?1: vnwell?2: vccq?3: vccd_sw?4: vcclfclk?5: vcchib?6: vccdpslp?7: vccqr" "0,1,2,3,4,5,6,7"
group.long 0x20++0x03
line.long 0x00 "PWR_DDFT_SELECT,Digital DFT Select"
bitfld.long 0x00 4.--7. "DDFT2_SEL,Signal select for ddft2 output:?0: act_power_en_a?1: power_up_raw?2: act_power_good_a?3: fastrefs_valid?4: vmon?5: bootref_outen?6: bootref_refsw?7: active_inrush_dis?8: awake?9: hvpor_reset_n?10: lpcomp_dis?11: wakeup_a?12: vmon_valid?13:.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DDFT1_SEL,Signal select for ddft1 output:?0: wakeup_a?1: ipor_reset?2: hbod_reset_raw_n?3: lpcomp_dis?4: power_up_delayed?5: awake?6: hvmon_out_of_sync?7: pbod_reset?8: hvbod_reset?9: lpm_ready?10: io_disable_req_lv (excluding por_force_in_hv)?11:.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x03
line.long 0x00 "PWR_DFT_KEY,DFT Safety Override"
bitfld.long 0x00 20. "VMON_PD,Disables the VMON block which includes PBOD HVBOD and LVD circuits" "0,1"
bitfld.long 0x00 19. "IO_DISABLE_BYPASS,Bypasses the IO disable logic for testing the delay-line that is part of the glitch-free IO reset circuitry" "0,1"
newline
bitfld.long 0x00 18. "DFT_MODE,Enable DfT modes other than the above" "0,1"
bitfld.long 0x00 17. "BODS_OFF,Forces all outputs of BOD detectors to be ignored effectively disabling all brown-out detection" "0,1"
newline
bitfld.long 0x00 16. "HBOD_OFF_AWAKE,Forces the output of the HBOD to be blocked (ignored) while in Active or Sleep mode (i.e. when under the umbrella of PBOD)" "0,1"
hexmask.long.word 0x00 0.--15. 1. "KEY16,This field must be set to 0xE4C5 for any of the other fields in this register to have effect and for scan_mode to be allowed"
group.long 0x28++0x03
line.long 0x00 "PWR_BOD_KEY,BOD Detection Key"
hexmask.long.word 0x00 0.--15. 1. "KEY16,To detect brown-outs firmware should do this on boot:?1"
group.long 0x2C++0x03
line.long 0x00 "PWR_STOP,STOP Mode Register"
bitfld.long 0x00 31. "STOP,Firmware sets this bit to enter STOP mode" "0,1"
bitfld.long 0x00 17. "FREEZE,Firmware sets this bit to freeze the configuration mode and state of all GPIOs and SIOs in the system" "0,1"
newline
bitfld.long 0x00 16. "POLARITY," "0,1"
hexmask.long.byte 0x00 8.--15. 1. "UNLOCK,This byte must be set to 0x3A for FREEZE or STOP fields to operate"
newline
hexmask.long.byte 0x00 0.--7. 1. "TOKEN,Contains a 8-bit token that is retained through a STOP/WAKEUP sequence that can be used by firmware to differentiate WAKEUP from a general RESET event"
group.long 0x100++0x03
line.long 0x00 "CLK_SELECT,Clock Select Register"
bitfld.long 0x00 19.--21. "SYSCLK_DIV,SYSCLK Pre-Scaler Value" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
bitfld.long 0x00 18. "HALF_EN,This bit impact products using CPUSSv1 only" "0,1"
newline
bitfld.long 0x00 16.--17. "HFCLK_SEL,Selects the source for HFCLK" "0: No description available,1: No description available,2: No description available,?..."
bitfld.long 0x00 14.--15. "WDT_LOCK,Prohibits writing to WDT_* registers and CLK_ILO/WCO_CONFIG registerst when not equal 0" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.long 0x00 12.--13. "DPLLREF_SEL,Selects a source for the reference (tracking) input of DPLL:?0: DSI_OUT[0]?1: DSI_OUT[1]?2: DSI_OUT[2]?3: DSI_OUT[3]" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 9.--11. "DPLLIN_SEL,Selects a source for the input of DPLL.?Note that not all products support all clock sources" "0: No description available,1: No description available,2: No description available,?,4: No description available,5: No description available,6: No description available,7: No description available"
newline
bitfld.long 0x00 6.--8. "PLL_SEL,Selects a source for the input of the PLL.?Note that not all products support all clock sources" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
bitfld.long 0x00 3.--5. "DBL_SEL,Selects a source for the input of DBL.?Note that not all products support all clock sources" "0: No description available,1: No description available,2: No description available,?,4: No description available,5: No description available,6: No description available,7: No description available"
newline
bitfld.long 0x00 0.--2. "DIRECT_SEL,Selects a source for HFCLK (when HFCLK_SEL=0) and DSI_IN[0].?Note that not all products support all clock sources" "0: No description available,1: No description available,2: No description available,?,4: No description available,5: No description available,6: No description available,7: No description available"
group.long 0x104++0x03
line.long 0x00 "CLK_ILO_CONFIG,ILO Configuration"
bitfld.long 0x00 31. "ENABLE,Master enable for ILO oscillator" "0,1"
bitfld.long 0x00 2. "SATBIAS,PFET bias" "0: No description available,1: No description available"
newline
bitfld.long 0x00 1. "TURBO,Turbo mode for faster startup from coma power down?0: turbo disabled?1: turbo enabled" "0,1"
bitfld.long 0x00 0. "PD_MODE,Power down mode" "0: No description available,1: No description available"
group.long 0x108++0x03
line.long 0x00 "CLK_IMO_CONFIG,IMO Configuration"
bitfld.long 0x00 31. "ENABLE,Master enable for IMO oscillator" "0,1"
bitfld.long 0x00 30. "EN_CLK2X,Enables main oscillator doubler circuit that can be used for TSS Charge Pumps" "0,1"
newline
bitfld.long 0x00 29. "EN_CLK36,Enables 36MHz secondary oscillator that can be used for Pump or Flash Pump" "0,1"
bitfld.long 0x00 28. "TEST_USB_MODE,Forces IMO into USB mode" "0,1"
newline
bitfld.long 0x00 25.--27. "PUMP_SEL,Selects operating source for Pump clock" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,?..."
bitfld.long 0x00 24. "TEST_FASTBIAS,Forces the IMO into FIMO mode (engineering only)" "0,1"
newline
bitfld.long 0x00 23. "EN_FASTBIAS,Forces the FIMO's fast bias circuits to remain powered (engineering only)" "0,1"
bitfld.long 0x00 22. "FLASHPUMP_SEL,Selects operating source for SPCIF Timer/Flash Pump clock" "0: No description available,1: No description available"
group.long 0x10C++0x03
line.long 0x00 "CLK_IMO_SPREAD,IMO Spread Spectrum Configuration"
bitfld.long 0x00 30.--31. "SS_MODE,Spread Spectrum Mode" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 28.--29. "SS_RANGE,Spread spectrum range (downspread when SS_VALUE=16).?3: reserved do not use" "0: No description available,1: No description available,2: No description available,?..."
newline
bitfld.long 0x00 8.--12. "SS_MAX,Maximum counter value for spread spectrum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. "SS_VALUE,Current offset value for spread spectrum modulation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x110++0x03
line.long 0x00 "CLK_DFT_SELECT,Clock DFT Mode Selection Register"
bitfld.long 0x00 12.--13. "DFT_DIV2,DFT Output Divide Down" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 8.--11. "DFT_SEL2,Select signal for DFT output #2" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
newline
bitfld.long 0x00 4.--5. "DFT_DIV1,DFT Output Divide Down" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 0.--3. "DFT_SEL1,Select signal for DFT output #1" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
group.long 0x200++0x03
line.long 0x00 "WDT_CTRLOW,Watchdog Counters 0/1"
hexmask.long.word 0x00 16.--31. 1. "WDT_CTR1,Current value of WDT Counter 1"
hexmask.long.word 0x00 0.--15. 1. "WDT_CTR0,Current value of WDT Counter 0"
group.long 0x204++0x03
line.long 0x00 "WDT_CTRHIGH,Watchdog Counter 2"
hexmask.long 0x00 0.--31. 1. "WDT_CTR2,Current value of WDT Counter 2"
group.long 0x208++0x03
line.long 0x00 "WDT_MATCH,Watchdog counter match values"
hexmask.long.word 0x00 16.--31. 1. "WDT_MATCH1,Match value for Watchdog Counter 1"
hexmask.long.word 0x00 0.--15. 1. "WDT_MATCH0,Match value for Watchdog Counter 0"
group.long 0x20C++0x03
line.long 0x00 "WDT_CONFIG,Watchdog Counters Configuration"
bitfld.long 0x00 30.--31. "LFCLK_SEL,Select source for LFCLK:?0: ILO - Internal R/C Oscillator?1: WCO - Internal Crystal Oscillator?2-3: Reserved - do not use?Note that not all products support all clock sources" "0,1,2,3"
bitfld.long 0x00 24.--28. "WDT_BITS2,Bit to observe for WDT_INT2:?0: Assert when bit0 of WDT_CTR2 toggles (one int every tick)?..?31: Assert when bit31 of WDT_CTR2 toggles (one int every 2^31 ticks)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16. "WDT_MODE2,Watchdog Counter 2 Mode" "0: No description available,1: No description available"
bitfld.long 0x00 11. "WDT_CASCADE1_2,Cascade Watchdog Counters 1 2" "0,1"
newline
bitfld.long 0x00 10. "WDT_CLEAR1,Clear Watchdog Counter when WDT_CTR1=WDT_MATCH1" "0,1"
bitfld.long 0x00 8.--9. "WDT_MODE1,Watchdog Counter Action on Match (WDT_CTR1=WDT_MATCH1)" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.long 0x00 3. "WDT_CASCADE0_1,Cascade Watchdog Counters 0 1" "0,1"
bitfld.long 0x00 2. "WDT_CLEAR0,Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0" "0,1"
newline
bitfld.long 0x00 0.--1. "WDT_MODE0,Watchdog Counter Action on Match (WDT_CTR0=WDT_MATCH0)" "0: No description available,1: No description available,2: No description available,3: No description available"
group.long 0x210++0x03
line.long 0x00 "WDT_CONTROL,Watchdog Counters Control"
bitfld.long 0x00 19. "WDT_RESET2,Resets counter 2 back to 0000_0000" "0,1"
bitfld.long 0x00 18. "WDT_INT2,WDT Interrupt Request" "0,1"
newline
rbitfld.long 0x00 17. "WDT_ENABLED2,Indicates actual state of counter" "0,1"
bitfld.long 0x00 16. "WDT_ENABLE2,Enable Counter 2?0: Counter is disabled (not clocked)?1: Counter is enabled (counting up)?Note: This field takes considerable time (up to 3 LFCLK cycles) to take effect" "0,1"
newline
bitfld.long 0x00 11. "WDT_RESET1,Resets counter 1 back to 0000" "0,1"
bitfld.long 0x00 10. "WDT_INT1,WDT Interrupt Request" "0,1"
newline
rbitfld.long 0x00 9. "WDT_ENABLED1,Indicates actual state of counter" "0,1"
bitfld.long 0x00 8. "WDT_ENABLE1,Enable Counter 1?0: Counter is disabled (not clocked)?1: Counter is enabled (counting up)?Note: This field takes considerable time (up to 3 LFCLK cycles) to take effect" "0,1"
newline
bitfld.long 0x00 3. "WDT_RESET0,Resets counter 0 back to 0000" "0,1"
bitfld.long 0x00 2. "WDT_INT0,WDT Interrupt Request" "0,1"
newline
rbitfld.long 0x00 1. "WDT_ENABLED0,Indicates actual state of counter" "0,1"
bitfld.long 0x00 0. "WDT_ENABLE0,Enable Counter 0?0: Counter is disabled (not clocked)?1: Counter is enabled (counting up)?Note: This field takes considerable time (up to 3 LFCLK cycles) to take effect" "0,1"
group.long 0x300++0x03
line.long 0x00 "RES_CAUSE,Reset Cause Observation Register"
bitfld.long 0x00 7. "RESET_XRES,This field is deprecated and will always read 0" "0,1"
bitfld.long 0x00 6. "RESET_PBOD,This field is deprecated and will always read 0" "0,1"
newline
bitfld.long 0x00 5. "RESET_HVBOD,This field is deprecated and will always read 0" "0,1"
bitfld.long 0x00 4. "RESET_SOFT,Cortex-M0 requested a system reset through it's SYSRESETREQ" "0,1"
newline
bitfld.long 0x00 3. "RESET_PROT_FAULT,A protection violation occurred that requires a RESET" "0,1"
bitfld.long 0x00 2. "RESET_LOCKUP,This field is deprecated and will always read 0" "0,1"
newline
bitfld.long 0x00 1. "RESET_DSBOD,This field is deprecated and will always read 0" "0,1"
bitfld.long 0x00 0. "RESET_WDT,A WatchDog Timer reset has occurred since last power cycle" "0,1"
group.long 0xFF00++0x03
line.long 0x00 "PWR_PWRSYS_TRIM1,Power System Trim Register"
bitfld.long 0x00 4.--7. "BOD_TRIM_TRIP,BOD trip point trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "BOD_TURBO_THRESH,BOD Turbo Threshold Control?0 Turbo Threshold is set to 100mV above BOD trip point?1 Turbo Threshold is set to 50mV above BOD trip point" "0,1"
newline
bitfld.long 0x00 0.--2. "HIB_BIAS_TRIM,Current reference trim" "0,1,2,3,4,5,6,7"
group.long 0xFF04++0x03
line.long 0x00 "PWR_PWRSYS_TRIM2,Power System Trim Register"
bitfld.long 0x00 7. "DPSLP_TRIM_VOLTAGE,Raise output voltage?1= regulator hibernate 200mV higher?0= nominal 1.4-1.6V range" "0,1"
bitfld.long 0x00 6. "DPSLP_TRIM_LEAKAGE,Enable Vcchib pass gate leakage control" "0,1"
newline
bitfld.long 0x00 4.--5. "DPSLP_TRIM_LOAD,Current load trim capability?00= Min current load capability?11= Max current load capability" "0,1,2,3"
bitfld.long 0x00 2.--3. "LFCLK_TRIM_VOLTAGE,Output voltage trim?00= default ?01= Trim lfclk by -50mV?10= Trim lfclk by +50mV?11= illegal" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "LFCLK_TRIM_LOAD,Current load trim capability?00= Min current load capability?11= Max current load capability" "0,1,2,3"
group.long 0xFF08++0x03
line.long 0x00 "PWR_PWRSYS_TRIM3,Power System Trim Register"
bitfld.long 0x00 3.--7. "QUIET_TRIM,Vccq (quiet regulator) trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--2. "NWELL_TRIM,Vnwell (nwell regulator) trim?[0]: Vcchib + nhv(0.6V -1V)?[1]: Vcchib + nlowvt(0.4 -0.8V)?[2]: Vcchib + nhvnat(0.1-0.3)" "0,1,2,3,4,5,6,7"
group.long 0xFF0C++0x03
line.long 0x00 "PWR_PWRSYS_TRIM4,Power System Trim Register"
bitfld.long 0x00 4.--5. "HIB_TRIM_REFERENCE,Hibernate Reference trim?10=Trim reference by -27mV?01=Trim reference by +27mV?00= no trim" "0,1,2,3"
bitfld.long 0x00 3. "HIB_TRIM_VOLTAGE,Elevate output voltage?1= regulator hibernate 200mV higher ?0= nominal 1.4-1.6V range" "0,1"
newline
bitfld.long 0x00 2. "HIB_TRIM_LEAKAGE,Enable Vcchib pass gate leakage control" "0,1"
bitfld.long 0x00 0.--1. "HIB_TRIM_NWELL,Vnwell Leakage control?00= smart nwell regulation?01= regulate nwell to constant voltage" "0,1,2,3"
group.long 0xFF10++0x03
line.long 0x00 "PWR_BG_TRIM1,Bandgap Trim Register"
bitfld.long 0x00 3.--6. "INL_CROSS_MAIN,Bandgap INL cross-over point control for centering curve at 30C (main current reference)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "INL_TRIM_MAIN,Bandgap nonlinear current trim for curvature correction (main current reference)" "0,1,2,3,4,5,6,7"
group.long 0xFF14++0x03
line.long 0x00 "PWR_BG_TRIM2,Bandgap Trim Register"
bitfld.long 0x00 7. "VCTAT_VOLTAGE_MSB,Output voltage absolute trim (MSB)" "0,1"
bitfld.long 0x00 6. "VCTAT_ENABLE,Enable VCTAT block" "0,1"
newline
bitfld.long 0x00 4.--5. "VCTAT_VOLTAGE,Output voltage absolute trim (LSBs)" "0,1,2,3"
bitfld.long 0x00 0.--3. "VCTAT_SLOPE,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFF18++0x03
line.long 0x00 "PWR_BG_TRIM3,Bandgap Trim Register"
bitfld.long 0x00 3.--6. "INL_CROSS_IMO,IMO Irefgen INL cross-over point control for centering curve at 30C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "INL_TRIM_IMO,IMO Irefgen nonlinear current trim for curvature correction" "0,1,2,3,4,5,6,7"
group.long 0xFF1C++0x03
line.long 0x00 "PWR_BG_TRIM4,Bandgap Trim Register"
bitfld.long 0x00 0.--5. "ABS_TRIM_IMO,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xFF20++0x03
line.long 0x00 "PWR_BG_TRIM5,Bandgap Trim Register"
bitfld.long 0x00 0.--5. "TMPCO_TRIM_IMO,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xFF24++0x03
line.long 0x00 "CLK_ILO_TRIM,ILO Trim Register"
bitfld.long 0x00 4.--7. "COARSE_TRIM,Adjusts the bias in the event of high current after fab:?Bias trim:?bit3=0: Normal Mode?bit3=1:Low Current Mode??Resistor Trim (Short R to gnd):?bit2=0: Normal Mode?bit2=1: Short R/4?bit1=0: Unshort R/2?bit1=1: Normal Mode (Short.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "TRIM,Trim bits to control frequency?0: Minimum frequency?15: Maximum frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFF28++0x03
line.long 0x00 "CLK_IMO_TRIM1,IMO Trim Register"
hexmask.long.byte 0x00 0.--7. 1. "OFFSET,Frequency trim bits"
group.long 0xFF2C++0x03
line.long 0x00 "CLK_IMO_TRIM2,IMO Trim Register"
bitfld.long 0x00 0.--5. "FREQ,Frequency to be selected (default 24MHz)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xFF30++0x03
line.long 0x00 "CLK_IMO_TRIM3,IMO Trim Register"
bitfld.long 0x00 0.--3. "TRIM_CLK36,Trim bits for 36MHz oscillator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xFF34++0x03
line.long 0x00 "CLK_IMO_TRIM4,IMO Trim Register"
bitfld.long 0x00 5.--7. "FSOFFSET,Full-speed USB offset" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "GAIN,Gain for IMO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xFF38++0x03
line.long 0x00 "PWR_RSVD_TRIM,Reserved unused registers"
bitfld.long 0x00 0.--3. "RSVD_TRIM,Reserved unused registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree "TCPWM (Quad Timer/Counter/PWM)"
base ad:0x40050000
group.long 0x00++0x03
line.long 0x00 "CTRL,TCPWM control register 0"
hexmask.long.byte 0x00 0.--7. 1. "COUNTER_ENABLED,Counter enables for counters 0 up to CNT_NR-1"
group.long 0x08++0x03
line.long 0x00 "CMD,TCPWM command register"
hexmask.long.byte 0x00 24.--31. 1. "COUNTER_START,Counters SW start trigger"
hexmask.long.byte 0x00 16.--23. 1. "COUNTER_STOP,Counters SW stop trigger"
newline
hexmask.long.byte 0x00 8.--15. 1. "COUNTER_RELOAD,Counters SW reload trigger"
hexmask.long.byte 0x00 0.--7. 1. "COUNTER_CAPTURE,Counters SW capture trigger"
group.long 0x0C++0x03
line.long 0x00 "INTR_CAUSE,TCPWM Counter interrupt cause register"
hexmask.long.byte 0x00 0.--7. 1. "COUNTER_INT,Counters interrupt signal active"
tree.end
tree "TCPWM_CNT (Timer/Counter/PWM Counter Module)"
repeat 4. (list 0. 1. 2. 3.) (list ad:0x40050100 ad:0x40050140 ad:0x40050180 ad:0x400501C0)
tree "TCPWM_CNT$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CTRL,Counter control register"
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: No description available,?,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,?..."
bitfld.long 0x00 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4).?In PWM PWM_DT and PWM_PR modes these two bits can be used to invert dt_line_out and dt_line_compl_out" "0: No description available,1: No description available,2: No description available,?..."
newline
bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
hexmask.long.byte 0x00 8.--15. 1. "GENERIC,Generic 8-bit control field"
bitfld.long 0x00 3. "PWM_STOP_ON_KILL,When '1' the kill/stop event stops the counter" "0,1"
newline
bitfld.long 0x00 2. "PWM_SYNC_KILL,When '1' the kill event disables the dt_line_out and dt_line_compl_out signals till the next terminal count event (synchronous kill)" "0,1"
bitfld.long 0x00 1. "AUTO_RELOAD_PERIOD,When '1' the hardware automatically updates the PERIOD register during a terminal count with an active switch event" "0,1"
newline
bitfld.long 0x00 0. "AUTO_RELOAD_CC,When '1' the hardware automatically updates the CC register during a terminal count with an active switch event" "0,1"
group.long 0x04++0x03
line.long 0x00 "STATUS,Counter status register"
rbitfld.long 0x00 31. "RUNNING,When '0' the counter is NOT running" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "GENERIC,Generic 8-bit counter field"
newline
rbitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
group.long 0x08++0x03
line.long 0x00 "COUNTER,Counter count register"
hexmask.long.word 0x00 0.--15. 1. "COUNTER,16-bit counter value"
group.long 0x0C++0x03
line.long 0x00 "CC,Counter compare/capture register"
hexmask.long.word 0x00 0.--15. 1. "CC,In CAPTURE mode captures the counter value"
group.long 0x10++0x03
line.long 0x00 "CC_BUFF,Counter buffered compare/capture register"
hexmask.long.word 0x00 0.--15. 1. "CC,Additional buffer for counter CC register"
group.long 0x14++0x03
line.long 0x00 "PERIOD,Counter period register"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,Period value: upper value of the counter"
group.long 0x18++0x03
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,Additional buffer for counter PERIOD register"
group.long 0x20++0x03
line.long 0x00 "TR_CTRL0,Counter trigger control register 0"
bitfld.long 0x00 16.--19. "START_SEL,Selects one of the 16 input triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x24++0x03
line.long 0x00 "TR_CTRL1,Counter trigger control register 1"
bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.long 0x00 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register" "0: No description available,1: No description available,2: No description available,3: No description available"
group.long 0x28++0x03
line.long 0x00 "TR_CTRL2,Counter trigger control register 2"
bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches 0 ) on the line_out output signals" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the line_out output signals" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.long 0x00 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the line_out output signals" "0: No description available,1: No description available,2: No description available,3: No description available"
group.long 0x30++0x03
line.long 0x00 "INTR,Interrupt request register"
bitfld.long 0x00 1. "CC_MATCH,Counter matches CC register event" "0,1"
bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
group.long 0x34++0x03
line.long 0x00 "INTR_SET,Interrupt set request register"
bitfld.long 0x00 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0x38++0x03
line.long 0x00 "INTR_MASK,Interrupt mask register"
bitfld.long 0x00 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
group.long 0x3C++0x03
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
rbitfld.long 0x00 1. "CC_MATCH,Logical and of corresponding request and mask bits" "0,1"
rbitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
tree.end
repeat.end
tree.end
tree "TST (Test Subsystem)"
base ad:0x40030000
group.long 0x00++0x03
line.long 0x00 "CTRL,Main Test Control Register"
bitfld.long 0x00 30. "PTM_MODE_EN," "0,1"
bitfld.long 0x00 29. "SCAN_MODE," "0,1"
newline
bitfld.long 0x00 28. "SCAN_COMPRESS," "0,1"
bitfld.long 0x00 27. "SCAN_IDDQ," "0,1"
newline
bitfld.long 0x00 26. "SCAN_TRF," "0,1"
bitfld.long 0x00 25. "SCAN_TRF1," "0,1"
newline
bitfld.long 0x00 24. "SCAN_OCC_OBSERVE," "0,1"
bitfld.long 0x00 18. "TEST_SPARE2_EN,Enable bit for spare signal in scan control chain" "0,1"
newline
bitfld.long 0x00 17. "TEST_SPARE1_EN,Enable bit for spare signal in scan control chain" "0,1"
bitfld.long 0x00 16. "TEST_SYSRETAIN_EN,Enable sleepb test points for retention registers in Active domain" "0,1"
newline
bitfld.long 0x00 15. "TEST_SLPRETAIN_EN,Enable sleepb test points for retention registers in DeepSleep domain" "0,1"
bitfld.long 0x00 14. "TEST_SYSISOLATE_EN,Enable sleep test points in Active domain" "0,1"
newline
bitfld.long 0x00 13. "TEST_SLPISOLATE_EN,Enable sleep test points in DeepSleep domain" "0,1"
bitfld.long 0x00 12. "TEST_OCC0_2_EN_N,Enable the OCC test point of Bit 2 in TRF mode" "0,1"
newline
bitfld.long 0x00 11. "TEST_OCC0_1_EN_N,Enable the OCC test point of Bit 1 in TRF mode" "0,1"
bitfld.long 0x00 10. "TEST_ICG_EN_N,Enable clock gater test points during scan" "0,1"
newline
bitfld.long 0x00 9. "TEST_SET_EN_N,Enable async set test points during scan" "0,1"
bitfld.long 0x00 8. "TEST_RESET_EN_N,Enable async reset test points during scan" "0,1"
newline
rbitfld.long 0x00 2. "SWD_CONNECTED," "0,1"
bitfld.long 0x00 1. "DAP_NO_DEBUG," "0,1"
newline
bitfld.long 0x00 0. "DAP_NO_ACCESS," "0,1"
group.long 0x04++0x03
line.long 0x00 "ADFT_CTRL,Analog DFT Control Register"
bitfld.long 0x00 31. "ENABLE,Enables ADFT functionality" "0,1"
group.long 0x08++0x03
line.long 0x00 "DDFT_CTRL,Digital DFT Control Register"
bitfld.long 0x00 31. "ENABLE," "0,1"
bitfld.long 0x00 29.--30. "DIVIDE,Controls in-line divider for DDFT output #1 (used for high-speed clock measurements)" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.long 0x00 28. "EDGE,Edge sensitivity for in-line divider on DDFT output #1 (only relevant when DIVIDE>0)" "0: No description available,1: No description available"
bitfld.long 0x00 8.--13. "DFT_SEL2,Select signal for DDFT output #2" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,?..."
newline
bitfld.long 0x00 0.--5. "DFT_SEL1,Select signal for DDFT output #1" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,?..."
group.long 0x14++0x03
line.long 0x00 "MODE,Test Mode Control Register"
bitfld.long 0x00 31. "TEST_MODE," "0,1"
rbitfld.long 0x00 2. "SWD_CONNECTED," "0,1"
group.long 0x18++0x03
line.long 0x00 "TRIM_CNTR1,IMO trim down-counter and status (clk_sys)"
rbitfld.long 0x00 31. "COUNTER_DONE,Status bit indicating that TRIM_CNTR1.COUNTER==0 and TRIM_CNT2.COUNTER stopped counting up" "0,1"
hexmask.long.word 0x00 0.--15. 1. "COUNTER,Down-counter clocked on clk_sys"
group.long 0x1C++0x03
line.long 0x00 "TRIM_CNTR2,IMO trim up-counter (ddft)"
hexmask.long.word 0x00 0.--15. 1. "COUNTER,Up-counter clocked on DDFT output #2"
tree.end
tree "UDB (Programmable Digital Subsystem)"
base ad:0x400F0000
group.long 0x8000++0x03
line.long 0x00 "INT_CFG,UDB Subsystem Interrupt Configuration"
hexmask.long 0x00 0.--31. 1. "INT_MODE_CFG,Interrupt Mode bit position corresponds to interrupt"
tree.end
tree "UDB_BCTL0 (UDB Array Bank Control)"
base ad:0x400F6000
group.byte 0x00++0x00
line.byte 0x00 "DRV,Master Digital Clock Drive Register"
hexmask.byte 0x00 0.--7. 1. "DRV,Master digital clock drive enable for the digital clock that matches the index"
group.byte 0x01++0x00
line.byte 0x00 "MDCLK_EN,Master Digital Clock Enable Register"
hexmask.byte 0x00 0.--7. 1. "DCEN,Master digital clock enable for the digital clock that matches the index"
group.byte 0x02++0x00
line.byte 0x00 "MBCLK_EN,Master Digital Clock Enable Register"
bitfld.byte 0x00 0. "BCEN,Bank Clock Enable Control" "0: No description available,1: No description available"
group.byte 0x08++0x00
line.byte 0x00 "BOTSEL_L,Lower Nibble Bottom Digital Clock Select Register"
bitfld.byte 0x00 6.--7. "CLK_SEL3,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "CLK_SEL2,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "CLK_SEL1,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "CLK_SEL0,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x09++0x00
line.byte 0x00 "BOTSEL_U,Upper Nibble Bottom Digital Clock Select Register"
bitfld.byte 0x00 6.--7. "CLK_SEL7,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "CLK_SEL6,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "CLK_SEL5,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "CLK_SEL4,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x0A++0x00
line.byte 0x00 "TOPSEL_L,Lower Nibble Top Digital Clock Select Register"
bitfld.byte 0x00 6.--7. "CLK_SEL3,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "CLK_SEL2,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "CLK_SEL1,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "CLK_SEL0,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x0B++0x00
line.byte 0x00 "TOPSEL_U,Upper Nibble Top Digital Clock Select Register"
bitfld.byte 0x00 6.--7. "CLK_SEL7,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "CLK_SEL6,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "CLK_SEL5,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "CLK_SEL4,Clock selection control for digital clock" "0: No description available,1: No description available,2: No description available,3: No description available"
repeat 2. (strings "0" "1" )(list 0x0 0x2 )
group.word ($2+0x10)++0x01
line.word 0x00 "QCLK_EN$1,Quadrant Digital Clock Enable Registers"
bitfld.word 0x00 15. "SLEEP_TEST,Assertion of this bit drives sleep into the s8udb array for internal s8udb test purposes" "0: No description available,1: No description available"
bitfld.word 0x00 14. "NC0,Spare register bit" "0,1"
newline
bitfld.word 0x00 13. "WR_CFG_OPT,Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe used in generating write strobes for latches within the UDB" "0: No description available,1: No description available"
bitfld.word 0x00 12. "GLB_DSI_WR,Enable global write operation for the DSI routing channels" "0: No description available,1: No description available"
newline
bitfld.word 0x00 11. "DISABLE_ROUTE,By default when this bit is set to '0' the quadrant routing (for 2 channels in the quadrant) are enabled when the global route enable for the bank is set" "0: No description available,1: No description available"
bitfld.word 0x00 10. "GCH_WR_HI,Enable global write operation for the routing channel with the higher address in the associated quadrant" "0: No description available,1: No description available"
newline
bitfld.word 0x00 9. "GCH_WR_LO,Enable global write operation for the routing channel with the lower address in the associated quadrant" "0: No description available,1: No description available"
bitfld.word 0x00 8. "BCEN_Q,Bank Clock Enable Control" "0: No description available,1: No description available"
newline
hexmask.word.byte 0x00 0.--7. 1. "DCEN_Q,Digital clock enable for indexed digital clock for the associated quadrant"
repeat.end
tree.end
tree "UDB_DSI (DSI Configuration (16 DSI))"
repeat 4. (list 0. 1. 2. 3.) (list ad:0x400F4000 ad:0x400F4100 ad:0x400F4200 ad:0x400F4300)
tree "UDB_DSI$1"
base $2
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x00)++0x00
line.byte 0x00 "HC$1,DSI HC Tile Configuration"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration for DSI channel bytes"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x10)++0x00
line.byte 0x00 "HC$1,DSI HC Tile Configuration"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration for DSI channel bytes"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x20)++0x00
line.byte 0x00 "HC$1,DSI HC Tile Configuration"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration for DSI channel bytes"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x30)++0x00
line.byte 0x00 "HC$1,DSI HC Tile Configuration"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration for DSI channel bytes"
repeat.end
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x40)++0x00
line.byte 0x00 "HC$1,DSI HC Tile Configuration"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration for DSI channel bytes"
repeat.end
repeat 16. (strings "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" "90" "91" "92" "93" "94" "95" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x50)++0x00
line.byte 0x00 "HC$1,DSI HC Tile Configuration"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration for DSI channel bytes"
repeat.end
repeat 16. (strings "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" "106" "107" "108" "109" "110" "111" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x60)++0x00
line.byte 0x00 "HC$1,DSI HC Tile Configuration"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration for DSI channel bytes"
repeat.end
repeat 16. (strings "112" "113" "114" "115" "116" "117" "118" "119" "120" "121" "122" "123" "124" "125" "126" "127" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x70)++0x00
line.byte 0x00 "HC$1,DSI HC Tile Configuration"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration for DSI channel bytes"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x80)++0x00
line.byte 0x00 "HV_L$1,DSI HV Tile Configuration Left"
hexmask.byte 0x00 0.--7. 1. "HV_BYTE,RAM configuration for DSI channel bytes"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x90)++0x00
line.byte 0x00 "HS$1,DSI HS Tile Configuration Horizontal Segmentation"
hexmask.byte 0x00 0.--7. 1. "HS_BYTE,RAM configuration for DSI channel bytes"
repeat.end
repeat 8. (strings "16" "17" "18" "19" "20" "21" "22" "23" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )
group.byte ($2+0xA0)++0x00
line.byte 0x00 "HS$1,DSI HS Tile Configuration Horizontal Segmentation"
hexmask.byte 0x00 0.--7. 1. "HS_BYTE,RAM configuration for DSI channel bytes"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0xA8)++0x00
line.byte 0x00 "HV_R$1,DSI HV Tile Configuration Right"
hexmask.byte 0x00 0.--7. 1. "HV_BYTE,RAM configuration for DSI channel bytes"
repeat.end
repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x2 0x4 0x6 0x8 0xA )
group.word ($2+0xC0)++0x01
line.word 0x00 "DSIINP$1,DSI PI Tile Configuration for DSI I/O Input"
bitfld.word 0x00 4.--7. "PI_BOT,RAM configuration for BOTTOM DSI port interface not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "PI_TOP,RAM configuration for TOP DSI port interface not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x2 0x4 0x6 )
group.word ($2+0xCC)++0x01
line.word 0x00 "DSIOUTP$1,DSI PI Tile Configuration for DSI I/O Output pair"
bitfld.word 0x00 4.--7. "PI_BOT,RAM configuration for BOTTOM DSI port interface not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "PI_TOP,RAM configuration for TOP DSI port interface not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x2 0x4 0x6 0x8 0xA )
group.word ($2+0xD4)++0x01
line.word 0x00 "DSIOUTT$1,DSI PI Tile Configuration for DSI I/O Output triplet"
bitfld.word 0x00 4.--7. "PI_BOT,RAM configuration for BOTTOM DSI port interface not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "PI_TOP,RAM configuration for TOP DSI port interface not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x2 0x4 0x6 0x8 0xA 0xC 0xE )
group.word ($2+0xE0)++0x01
line.word 0x00 "VS$1,DSI VS Tile Configuration Vertical Segmentation"
bitfld.word 0x00 4.--7. "VS_BOT,RAM configuration for BOTTOM DSI vertical segmentation not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "VS_TOP,RAM configuration for TOP DSI vertical segmentation not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
tree.end
repeat.end
tree.end
tree "UDB_P0_ROUTE (Routing Configuration for one UDB Pair)"
base ad:0x400F3100
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x00)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x10)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x20)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x30)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x40)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" "90" "91" "92" "93" "94" "95" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x50)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" "106" "107" "108" "109" "110" "111" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x60)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "112" "113" "114" "115" "116" "117" "118" "119" "120" "121" "122" "123" "124" "125" "126" "127" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x70)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x80)++0x00
line.byte 0x00 "HV_L$1,UDB Channel HV Tile Configuration Left"
hexmask.byte 0x00 0.--7. 1. "HV_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x90)++0x00
line.byte 0x00 "HS$1,UDB Channel HS Tile Configuration Horizontal Segmentation"
hexmask.byte 0x00 0.--7. 1. "HS_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 8. (strings "16" "17" "18" "19" "20" "21" "22" "23" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )
group.byte ($2+0xA0)++0x00
line.byte 0x00 "HS$1,UDB Channel HS Tile Configuration Horizontal Segmentation"
hexmask.byte 0x00 0.--7. 1. "HS_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0xA8)++0x00
line.byte 0x00 "HV_R$1,UDB Channel HV Tile Configuration Right"
hexmask.byte 0x00 0.--7. 1. "HV_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x0 0x2 0x4 )
group.word ($2+0xC0)++0x01
line.word 0x00 "PLD0IN$1,UDB Channel PI Tile Configuration PLD Input"
bitfld.word 0x00 4.--7. "PI_BOT,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "PI_TOP,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x0 0x2 0x4 )
group.word ($2+0xCA)++0x01
line.word 0x00 "PLD1IN$1,UDB Channel PI Tile Configuration PLD Input"
bitfld.word 0x00 4.--7. "PI_BOT,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "PI_TOP,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
group.byte 0xD0++0x00
line.byte 0x00 "DPIN0,UDB Channel PI Tile Configuration Datapath Input"
bitfld.byte 0x00 4.--7. "PI_BOT,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PI_TOP,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xD2++0x00
line.byte 0x00 "DPIN1,UDB Channel PI Tile Configuration Datapath Input"
bitfld.byte 0x00 4.--5. "PI_BOT2,RAM configuration bits (2) for BOTTOM UDB port interface configuration" "0,1,2,3"
bitfld.byte 0x00 2.--3. "PI_TOP2,RAM configuration bits (2) for TOP UDB port interface configuration" "0,1,2,3"
group.byte 0xD6++0x00
line.byte 0x00 "SCIN,UDB Channel PI Tile Configuration Status / Control Blocks Input Control"
bitfld.byte 0x00 4.--7. "PI_BOT,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PI_TOP,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xD8++0x00
line.byte 0x00 "SCIOIN,UDB Channel PI Tile Configuration Status / Control Blocks Input / Output Control"
bitfld.byte 0x00 4.--7. "PI_BOT,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PI_TOP,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xDE++0x00
line.byte 0x00 "RCIN,UDB Channel PI Tile Configuration Reset and Clock Blocks Input Control"
bitfld.byte 0x00 4.--7. "PI_BOT,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PI_TOP,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x2 0x4 0x6 0x8 0xA 0xC 0xE )
group.word ($2+0xE0)++0x01
line.word 0x00 "VS$1,UDB Channel VS Tile Configuration Vertical Segmentation"
bitfld.word 0x00 4.--7. "VS_BOT,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "VS_TOP,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
tree.end
tree "UDB_P0_U (Single UDB Configuration)"
repeat 2. (list 0. 1.) (list ad:0x400F3000 ad:0x400F3080)
tree "UDB_P0_U$1"
base $2
repeat 12. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x00)++0x03
line.long 0x00 "PLD_IT$1,PLD Input Terms"
bitfld.long 0x00 31. "PLD1_ITxT_7,True input term" "0,1"
bitfld.long 0x00 30. "PLD1_ITxT_6,True input term" "0,1"
newline
bitfld.long 0x00 29. "PLD1_ITxT_5,True input term" "0,1"
bitfld.long 0x00 28. "PLD1_ITxT_4,True input term" "0,1"
newline
bitfld.long 0x00 27. "PLD1_ITxT_3,True input term" "0,1"
bitfld.long 0x00 26. "PLD1_ITxT_2,True input term" "0,1"
newline
bitfld.long 0x00 25. "PLD1_ITxT_1,True input term" "0,1"
bitfld.long 0x00 24. "PLD1_ITxT_0,True input term" "0,1"
newline
bitfld.long 0x00 23. "PLD0_ITxT_7,True input term" "0,1"
bitfld.long 0x00 22. "PLD0_ITxT_6,True input term" "0,1"
newline
bitfld.long 0x00 21. "PLD0_ITxT_5,True input term" "0,1"
bitfld.long 0x00 20. "PLD0_ITxT_4,True input term" "0,1"
newline
bitfld.long 0x00 19. "PLD0_ITxT_3,True input term" "0,1"
bitfld.long 0x00 18. "PLD0_ITxT_2,True input term" "0,1"
newline
bitfld.long 0x00 17. "PLD0_ITxT_1,True input term" "0,1"
bitfld.long 0x00 16. "PLD0_ITxT_0,True input term" "0,1"
newline
bitfld.long 0x00 15. "PLD1_ITxC_7,Complement input term" "0,1"
bitfld.long 0x00 14. "PLD1_ITxC_6,Complement input term" "0,1"
newline
bitfld.long 0x00 13. "PLD1_ITxC_5,Complement input term" "0,1"
bitfld.long 0x00 12. "PLD1_ITxC_4,Complement input term" "0,1"
newline
bitfld.long 0x00 11. "PLD1_ITxC_3,Complement input term" "0,1"
bitfld.long 0x00 10. "PLD1_ITxC_2,Complement input term" "0,1"
newline
bitfld.long 0x00 9. "PLD1_ITxC_1,Complement input term" "0,1"
bitfld.long 0x00 8. "PLD1_ITxC_0,Complement input term" "0,1"
newline
bitfld.long 0x00 7. "PLD0_ITxC_7,Complement input term" "0,1"
bitfld.long 0x00 6. "PLD0_ITxC_6,Complement input term" "0,1"
newline
bitfld.long 0x00 5. "PLD0_ITxC_5,Complement input term" "0,1"
bitfld.long 0x00 4. "PLD0_ITxC_4,Complement input term" "0,1"
newline
bitfld.long 0x00 3. "PLD0_ITxC_3,Complement input term" "0,1"
bitfld.long 0x00 2. "PLD0_ITxC_2,Complement input term" "0,1"
newline
bitfld.long 0x00 1. "PLD0_ITxC_1,Complement input term" "0,1"
bitfld.long 0x00 0. "PLD0_ITxC_0,Complement input term" "0,1"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x2 0x4 0x6 )
group.word ($2+0x30)++0x01
line.word 0x00 "PLD_ORT$1,PLD OR Terms"
bitfld.word 0x00 15. "PLD1_ORT_PTx_7,OR term" "0,1"
bitfld.word 0x00 14. "PLD1_ORT_PTx_6,OR term" "0,1"
newline
bitfld.word 0x00 13. "PLD1_ORT_PTx_5,OR term" "0,1"
bitfld.word 0x00 12. "PLD1_ORT_PTx_4,OR term" "0,1"
newline
bitfld.word 0x00 11. "PLD1_ORT_PTx_3,OR term" "0,1"
bitfld.word 0x00 10. "PLD1_ORT_PTx_2,OR term" "0,1"
newline
bitfld.word 0x00 9. "PLD1_ORT_PTx_1,OR term" "0,1"
bitfld.word 0x00 8. "PLD1_ORT_PTx_0,OR term" "0,1"
newline
bitfld.word 0x00 7. "PLD0_ORT_PTx_7,OR term" "0,1"
bitfld.word 0x00 6. "PLD0_ORT_PTx_6,OR term" "0,1"
newline
bitfld.word 0x00 5. "PLD0_ORT_PTx_5,OR term" "0,1"
bitfld.word 0x00 4. "PLD0_ORT_PTx_4,OR term" "0,1"
newline
bitfld.word 0x00 3. "PLD0_ORT_PTx_3,OR term" "0,1"
bitfld.word 0x00 2. "PLD0_ORT_PTx_2,OR term" "0,1"
newline
bitfld.word 0x00 1. "PLD0_ORT_PTx_1,OR term" "0,1"
bitfld.word 0x00 0. "PLD0_ORT_PTx_0,OR term" "0,1"
repeat.end
group.word 0x38++0x01
line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell configuration for Carry Enable and Constant"
bitfld.word 0x00 15. "PLD1_MC3_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 14. "PLD1_MC3_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 13. "PLD1_MC2_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 12. "PLD1_MC2_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 11. "PLD1_MC1_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 10. "PLD1_MC1_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 9. "PLD1_MC0_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 8. "PLD1_MC0_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 7. "PLD0_MC3_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 6. "PLD0_MC3_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 5. "PLD0_MC2_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 4. "PLD0_MC2_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 3. "PLD0_MC1_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 2. "PLD0_MC1_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 1. "PLD0_MC0_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 0. "PLD0_MC0_CEN,Carry enable" "0: No description available,1: No description available"
group.word 0x3A++0x01
line.word 0x00 "PLD_MC_CFG_XORFB,PLD Macro cell XOR feedback"
bitfld.word 0x00 14.--15. "PLD1_MC3_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.word 0x00 12.--13. "PLD1_MC2_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.word 0x00 10.--11. "PLD1_MC1_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.word 0x00 8.--9. "PLD1_MC0_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.word 0x00 6.--7. "PLD0_MC3_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.word 0x00 4.--5. "PLD0_MC2_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.word 0x00 2.--3. "PLD0_MC1_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.word 0x00 0.--1. "PLD0_MC0_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
group.word 0x3C++0x01
line.word 0x00 "PLD_MC_SET_RESET,PLD Macro cell Set Reset Selection"
bitfld.word 0x00 15. "PLD1_MC3_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 14. "PLD1_MC3_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 13. "PLD1_MC2_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 12. "PLD1_MC2_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 11. "PLD1_MC1_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 10. "PLD1_MC1_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 9. "PLD1_MC0_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 8. "PLD1_MC0_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 7. "PLD0_MC3_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 6. "PLD0_MC3_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 5. "PLD0_MC2_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 4. "PLD0_MC2_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 3. "PLD0_MC1_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 2. "PLD0_MC1_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 1. "PLD0_MC0_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 0. "PLD0_MC0_SET_SEL,Set select enable" "0: No description available,1: No description available"
group.word 0x3E++0x01
line.word 0x00 "PLD_MC_CFG_BYPASS,PLD Macro cell Bypass control"
bitfld.word 0x00 15. "NC15,Spare register bit" "0,1"
bitfld.word 0x00 14. "PLD1_MC3_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 13. "NC13,Spare register bit" "0,1"
bitfld.word 0x00 12. "PLD1_MC2_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 11. "NC11,Spare register bit" "0,1"
bitfld.word 0x00 10. "PLD1_MC1_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 9. "NC9,Spare register bit" "0,1"
bitfld.word 0x00 8. "PLD1_MC0_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 7. "NC7,Spare register bit" "0,1"
bitfld.word 0x00 6. "PLD0_MC3_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 5. "NC5,Spare register bit" "0,1"
bitfld.word 0x00 4. "PLD0_MC2_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 3. "NC3,Spare register bit" "0,1"
bitfld.word 0x00 2. "PLD0_MC1_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 1. "NC1,Spare register bit" "0,1"
bitfld.word 0x00 0. "PLD0_MC0_BYPASS,Bypass selection" "0: No description available,1: No description available"
group.byte 0x40++0x00
line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0"
bitfld.byte 0x00 4.--6. "RAD1,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
bitfld.byte 0x00 0.--2. "RAD0,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.byte 0x41++0x00
line.byte 0x00 "CFG1,Datapath Input Selection - RAD2"
bitfld.byte 0x00 7. "DP_RTE_BYPASS4,DP_In bypass ctl" "0: No description available,1: No description available"
bitfld.byte 0x00 6. "DP_RTE_BYPASS3,DP_In bypass ctl" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 5. "DP_RTE_BYPASS2,DP_In bypass ctl" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "DP_RTE_BYPASS1,DP_In bypass ctl" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 3. "DP_RTE_BYPASS0,DP_In bypass ctl" "0: No description available,1: No description available"
bitfld.byte 0x00 0.--2. "RAD2,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.byte 0x42++0x00
line.byte 0x00 "CFG2,Datapath Input Selection - F1_LD F0_LD"
bitfld.byte 0x00 7. "NC7,Spare register bit" "0,1"
bitfld.byte 0x00 4.--6. "F1_LD,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
newline
bitfld.byte 0x00 3. "DP_RTE_BYPASS5,DP_In bypass ctl" "0: No description available,1: No description available"
bitfld.byte 0x00 0.--2. "F0_LD,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.byte 0x43++0x00
line.byte 0x00 "CFG3,Datapath Input Selection - D1_LD D0_LD"
bitfld.byte 0x00 4.--6. "D1_LD,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
bitfld.byte 0x00 0.--2. "D0_LD,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.byte 0x44++0x00
line.byte 0x00 "CFG4,Datapath Input Selection - CI_MUX SI_MUX"
bitfld.byte 0x00 4.--6. "CI_MUX,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
bitfld.byte 0x00 0.--2. "SI_MUX,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.byte 0x45++0x00
line.byte 0x00 "CFG5,Datapath Output Selection for OUT1 OUT0"
bitfld.byte 0x00 4.--7. "OUT1,Datapath Permutable Output Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
bitfld.byte 0x00 0.--3. "OUT0,Datapath Permutable Output Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
group.byte 0x46++0x00
line.byte 0x00 "CFG6,Datapath Output Selection for OUT3 OUT2"
bitfld.byte 0x00 4.--7. "OUT3,Datapath Permutable Output Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
bitfld.byte 0x00 0.--3. "OUT2,Datapath Permutable Output Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
group.byte 0x47++0x00
line.byte 0x00 "CFG7,Datapath Output Selection for OUT5 OUT4"
bitfld.byte 0x00 4.--7. "OUT5,Datapath Permutable Output Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
bitfld.byte 0x00 0.--3. "OUT4,Datapath Permutable Output Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
group.byte 0x48++0x00
line.byte 0x00 "CFG8,Datapath Output Synchronization Option"
bitfld.byte 0x00 7. "NC7,Spare register bit" "0,1"
bitfld.byte 0x00 6. "NC6,Spare register bit" "0,1"
newline
bitfld.byte 0x00 0.--5. "OUT_SYNC,Datapath Output Synchronization" "0: No description available,1: No description available,?..."
group.byte 0x49++0x00
line.byte 0x00 "CFG9,Datapath ALU Mask"
hexmask.byte 0x00 0.--7. 1. "AMASK,Datapath ALU Mask"
group.byte 0x4A++0x00
line.byte 0x00 "CFG10,Datapath Compare 0 Mask"
hexmask.byte 0x00 0.--7. 1. "CMASK0,Datapath Compare 0 Mask"
group.byte 0x4B++0x00
line.byte 0x00 "CFG11,Datapath Compare 1 Mask"
hexmask.byte 0x00 0.--7. 1. "CMASK0,Datapath Compare 1 Mask"
group.byte 0x4C++0x00
line.byte 0x00 "CFG12,Datapath mask enables and shift in configuration"
bitfld.byte 0x00 7. "CMASK1_EN,Datapath mask enable" "0: No description available,1: No description available"
bitfld.byte 0x00 6. "CMASK0_EN,Datapath mask enable" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 5. "AMASK_EN,Datapath mask enable" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "DEF_SI,Datapath default shift value" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2.--3. "SI_SELB,Datapath shift in source select" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "SI_SELA,Datapath shift in source select" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x4D++0x00
line.byte 0x00 "CFG13,Datapath carry in and compare configuration"
bitfld.byte 0x00 6.--7. "CMP_SELB,Datapath compare select" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "CMP_SELA,Datapath compare select" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "CI_SELB,Datapath carry in source select" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "CI_SELA,Datapath carry in source select" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x4E++0x00
line.byte 0x00 "CFG14,Datapath chaining and MSB configuration"
bitfld.byte 0x00 7. "MSB_EN,Datapath MSB selection enable" "0: No description available,1: No description available"
bitfld.byte 0x00 4.--6. "MSB_SEL,Datapath MSB Selection" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
newline
bitfld.byte 0x00 3. "CHAIN_CMSB,Datapath CRC MSB chaining enable" "0: No description available,1: No description available"
bitfld.byte 0x00 2. "CHAIN_FB,Datapath CRC feedback chaining enable" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 1. "CHAIN1,Datapath condition chaining enable" "0: No description available,1: No description available"
bitfld.byte 0x00 0. "CHAIN0,Datapath condition chaining enable" "0: No description available,1: No description available"
group.byte 0x4F++0x00
line.byte 0x00 "CFG15,Datapath FIFO shift and parallel input control"
bitfld.byte 0x00 7. "PI_SEL,Datapath parallel input selection" "0: No description available,1: No description available"
bitfld.byte 0x00 6. "SHIFT_SEL,Datapath shift out selection" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 5. "PI_DYN,Enable for dynamic control of parallel data input (PI) mux" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "MSB_SI,Arithmetic shift right operation shift in selection" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2.--3. "F1_INSEL,Datapath FIFO Configuration" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "F0_INSEL,Datapath FIFO Configuration" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x50++0x00
line.byte 0x00 "CFG16,Datapath FIFO and register access configuration control"
bitfld.byte 0x00 7. "F1_CK_INV,FIFO Clock Invert" "0: No description available,1: No description available"
bitfld.byte 0x00 6. "F0_CK_INV,FIFO Clock Invert" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 5. "FIFO_FAST,FIFO Fast Mode" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "FIFO_CAP,FIFO Software Capture Mode" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 3. "FIFO_EDGE,Edge/level sensitive FIFO write control (Fx_LD)" "0: No description available,1: No description available"
bitfld.byte 0x00 2. "FIFO_ASYNC,Asynchronous FIFO clocking support" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 1. "EXT_CRCPRS,External CRC/PRS mode" "0: No description available,1: No description available"
bitfld.byte 0x00 0. "WRK16_CONCAT,Datapath register access mode" "0: No description available,1: No description available"
group.byte 0x51++0x00
line.byte 0x00 "CFG17,Datapath FIFO control"
bitfld.byte 0x00 4. "FIFO_ADD_SYNC,Adds an additional sync flip-flop to FIFO block status" "0: No description available,1: No description available"
bitfld.byte 0x00 3. "NC3,Spare register bit" "0,1"
newline
bitfld.byte 0x00 2. "NC2,Spare register bit" "0,1"
bitfld.byte 0x00 1. "F1_DYN,No description available" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 0. "F0_DYN,When this bit is set the associated FIFO configuration may be dynamically controlled" "0: No description available,1: No description available"
group.byte 0x52++0x00
line.byte 0x00 "CFG18,Control Register Mode 0 (used in conjunction with Control Register Mode 1)"
hexmask.byte 0x00 0.--7. 1. "CTL_MD0,CTL_MD1 and CTL_MD0 are concatenated to form an encoding for the mode of each control bit in the control register"
group.byte 0x53++0x00
line.byte 0x00 "CFG19,Control Register Mode 1 (used in conjunction with Control Register Mode 0)"
hexmask.byte 0x00 0.--7. 1. "CTL_MD1,CTL_MD1 and CTL_MD0 are concatenated to form an encoding for the mode of each control bit in the control register"
group.byte 0x54++0x00
line.byte 0x00 "CFG20,Status Register input mode selection"
hexmask.byte 0x00 0.--7. 1. "STAT_MD,Mode selection for each bit of the status register"
group.byte 0x55++0x00
line.byte 0x00 "CFG21,Spare register bits"
bitfld.byte 0x00 1. "NC1,Spare register bit" "0,1"
bitfld.byte 0x00 0. "NC0,Spare register bit" "0,1"
group.byte 0x56++0x00
line.byte 0x00 "CFG22,SC block configuration control"
bitfld.byte 0x00 4. "SC_EXT_RES,Control register external reset operation" "0: No description available,1: No description available"
bitfld.byte 0x00 3. "SC_SYNC_MD,SC Sync Mode - controls when the status register operates as a 4-bit double synchronizer module" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2. "SC_INT_MD,SC Interrupt Mode - controls when the UDB driving an interrupt generated from the masked OR reduction of status bits 6 to 0" "0: No description available,1: No description available"
bitfld.byte 0x00 0.--1. "SC_OUT_CTL,Selects the output source for the Status and Control routing connections" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x57++0x00
line.byte 0x00 "CFG23,Counter Control"
bitfld.byte 0x00 6. "ALT_CNT,Configure the alternate operating mode of the counter" "0: No description available,1: No description available"
bitfld.byte 0x00 5. "ROUTE_EN,Configure the counter enable signal for routing input" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 4. "ROUTE_LD,Configure the counter load signal for routing input" "0: No description available,1: No description available"
bitfld.byte 0x00 2.--3. "CNT_EN_SEL,Selects the routing inputs for the counter enable signal" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 0.--1. "CNT_LD_SEL,Selects the routing inputs for the counter load signal" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x58++0x00
line.byte 0x00 "CFG24,PLD0 Clock and Reset control"
bitfld.byte 0x00 7. "RC_RES_SEL1,Configures the routed reset for the associated UDB component block" "0,1"
bitfld.byte 0x00 6. "RC_RES_SEL0_OR_FRES,Configures the routed or firmware reset for the associated UDB component block" "0,1"
newline
bitfld.byte 0x00 5. "RC_INV,Optionally inverts the clock selection for the associated UDB component block" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "RC_EN_INV,Optionally inverts the clock enable selection for the associated UDB component blocks" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2.--3. "RC_EN_MODE,Selects the operating mode for the clock to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "RC_EN_SEL,Selects channel route for enable control to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x59++0x00
line.byte 0x00 "CFG25,PLD1 Clock and Reset control"
bitfld.byte 0x00 7. "RC_RES_SEL1,Configures the routed reset for the associated UDB component block" "0,1"
bitfld.byte 0x00 6. "RC_RES_SEL0_OR_FRES,Configures the routed or firmware reset for the associated UDB component block" "0,1"
newline
bitfld.byte 0x00 5. "RC_INV,Optionally inverts the clock selection for the associated UDB component block" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "RC_EN_INV,Optionally inverts the clock enable selection for the associated UDB component blocks" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2.--3. "RC_EN_MODE,Selects the operating mode for the clock to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "RC_EN_SEL,Selects channel route for enable control to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x5A++0x00
line.byte 0x00 "CFG26,Datapath Clock and Reset control"
bitfld.byte 0x00 7. "RC_RES_SEL1,Configures the routed reset for the associated UDB component block" "0,1"
bitfld.byte 0x00 6. "RC_RES_SEL0_OR_FRES,Configures the routed or firmware reset for the associated UDB component block" "0,1"
newline
bitfld.byte 0x00 5. "RC_INV,Optionally inverts the clock selection for the associated UDB component block" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "RC_EN_INV,Optionally inverts the clock enable selection for the associated UDB component blocks" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2.--3. "RC_EN_MODE,Selects the operating mode for the clock to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "RC_EN_SEL,Selects channel route for enable control to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x5B++0x00
line.byte 0x00 "CFG27,Status/Control Clock and Reset control"
bitfld.byte 0x00 7. "RC_RES_SEL1,Configures the routed reset for the associated UDB component block" "0,1"
bitfld.byte 0x00 6. "RC_RES_SEL0_OR_FRES,Configures the routed or firmware reset for the associated UDB component block" "0,1"
newline
bitfld.byte 0x00 5. "RC_INV,Optionally inverts the clock selection for the associated UDB component block" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "RC_EN_INV,Optionally inverts the clock enable selection for the associated UDB component blocks" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2.--3. "RC_EN_MODE,Selects the operating mode for the clock to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "RC_EN_SEL,Selects channel route for enable control to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x5C++0x00
line.byte 0x00 "CFG28,Clock Selection for PLD1 and PLD0"
bitfld.byte 0x00 4.--7. "PLD1_CK_SEL,Clock selection registers" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,?..."
bitfld.byte 0x00 0.--3. "PLD0_CK_SEL,Clock selection registers" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,?..."
group.byte 0x5D++0x00
line.byte 0x00 "CFG29,Clock Selection for Datapath Status and Control"
bitfld.byte 0x00 4.--7. "SC_CK_SEL,Clock selection registers" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,?..."
bitfld.byte 0x00 0.--3. "DP_CK_SEL,Clock selection registers" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,?..."
group.byte 0x5E++0x00
line.byte 0x00 "CFG30,Reset control"
bitfld.byte 0x00 7. "SC_RES_POL,Only valid when ALT RES (CFG31) is '1'" "0: No description available,1: No description available"
bitfld.byte 0x00 6. "DP_RES_POL,Only valid when ALT RES (CFG31) is '1'" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 4. "GUDB_WR,Enable global write operation for the configuration and working registers in this UDB" "0: No description available,1: No description available"
bitfld.byte 0x00 3. "EN_RES_CNTCTL,This bit gates the routed reset to the counter/control register" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2. "RES_POL,The meaning of this bit depends on the value of the ALT RES bit in CFG31" "0: No description available,1: No description available"
bitfld.byte 0x00 0.--1. "RES_SEL,The meaning of this bit depends on the value of ALT RES (CFG31)" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x5F++0x00
line.byte 0x00 "CFG31,Reset control"
bitfld.byte 0x00 7. "PLD1_RES_POL,Not connected" "0: No description available,1: No description available"
bitfld.byte 0x00 6. "PLD0_RES_POL,The meaning of this bit depends on the value of ALT RES" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 4.--5. "EXT_CK_SEL,External clock selection" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 3. "EN_RES_DP,Only valid when ALT RES (CFG31) is '1'" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2. "EN_RES_STAT,Only valid when ALT RES (CFG31) is '1'" "0: No description available,1: No description available"
bitfld.byte 0x00 1. "EXT_SYNC,Enable synchronization of selected external clock" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 0. "ALT_RES,This bit toggles between two reset configurations" "0: No description available,1: No description available"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x2 0x4 0x6 0x8 0xA 0xC 0xE )
group.word ($2+0x60)++0x01
line.word 0x00 "DCFG$1,Dynamic Configuration RAM"
bitfld.word 0x00 13.--15. "FUNC,Dynamic ALU function selection" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
bitfld.word 0x00 12. "SRC_A,Dynamic ALU source A selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 10.--11. "SRC_B,Dynamic ALU source B selection" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.word 0x00 8.--9. "SHIFT,Dynamic shift selection" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.word 0x00 6.--7. "A0_WR_SRC,Dynamic A0 write source selection" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.word 0x00 4.--5. "A1_WR_SRC,Dynamic A1 write source selection" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.word 0x00 3. "CFB_EN,Dynamic CRC feedback selection" "0: No description available,1: No description available"
bitfld.word 0x00 2. "CI_SEL,Dynamic carry in selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 1. "SI_SEL,Dynamic shift in selection" "0: No description available,1: No description available"
bitfld.word 0x00 0. "CMP_SEL,Dynamic compare selection" "0: No description available,1: No description available"
repeat.end
tree.end
repeat.end
tree.end
tree "UDB_P1_ROUTE (Routing Configuration for one UDB Pair)"
base ad:0x400F3300
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x00)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x10)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x20)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x30)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x40)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" "90" "91" "92" "93" "94" "95" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x50)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" "106" "107" "108" "109" "110" "111" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x60)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "112" "113" "114" "115" "116" "117" "118" "119" "120" "121" "122" "123" "124" "125" "126" "127" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x70)++0x00
line.byte 0x00 "HC$1,UDB Channel HC Tile Configuration Horizontal Channel"
hexmask.byte 0x00 0.--7. 1. "HC_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x80)++0x00
line.byte 0x00 "HV_L$1,UDB Channel HV Tile Configuration Left"
hexmask.byte 0x00 0.--7. 1. "HV_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0x90)++0x00
line.byte 0x00 "HS$1,UDB Channel HS Tile Configuration Horizontal Segmentation"
hexmask.byte 0x00 0.--7. 1. "HS_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 8. (strings "16" "17" "18" "19" "20" "21" "22" "23" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )
group.byte ($2+0xA0)++0x00
line.byte 0x00 "HS$1,UDB Channel HS Tile Configuration Horizontal Segmentation"
hexmask.byte 0x00 0.--7. 1. "HS_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
group.byte ($2+0xA8)++0x00
line.byte 0x00 "HV_R$1,UDB Channel HV Tile Configuration Right"
hexmask.byte 0x00 0.--7. 1. "HV_BYTE,RAM configuration bytes for channel"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x0 0x2 0x4 )
group.word ($2+0xC0)++0x01
line.word 0x00 "PLD0IN$1,UDB Channel PI Tile Configuration PLD Input"
bitfld.word 0x00 4.--7. "PI_BOT,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "PI_TOP,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
repeat 3. (strings "0" "1" "2" )(list 0x0 0x2 0x4 )
group.word ($2+0xCA)++0x01
line.word 0x00 "PLD1IN$1,UDB Channel PI Tile Configuration PLD Input"
bitfld.word 0x00 4.--7. "PI_BOT,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "PI_TOP,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
group.byte 0xD0++0x00
line.byte 0x00 "DPIN0,UDB Channel PI Tile Configuration Datapath Input"
bitfld.byte 0x00 4.--7. "PI_BOT,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PI_TOP,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xD2++0x00
line.byte 0x00 "DPIN1,UDB Channel PI Tile Configuration Datapath Input"
bitfld.byte 0x00 4.--5. "PI_BOT2,RAM configuration bits (2) for BOTTOM UDB port interface configuration" "0,1,2,3"
bitfld.byte 0x00 2.--3. "PI_TOP2,RAM configuration bits (2) for TOP UDB port interface configuration" "0,1,2,3"
group.byte 0xD6++0x00
line.byte 0x00 "SCIN,UDB Channel PI Tile Configuration Status / Control Blocks Input Control"
bitfld.byte 0x00 4.--7. "PI_BOT,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PI_TOP,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xD8++0x00
line.byte 0x00 "SCIOIN,UDB Channel PI Tile Configuration Status / Control Blocks Input / Output Control"
bitfld.byte 0x00 4.--7. "PI_BOT,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PI_TOP,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0xDE++0x00
line.byte 0x00 "RCIN,UDB Channel PI Tile Configuration Reset and Clock Blocks Input Control"
bitfld.byte 0x00 4.--7. "PI_BOT,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.byte 0x00 0.--3. "PI_TOP,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x2 0x4 0x6 0x8 0xA 0xC 0xE )
group.word ($2+0xE0)++0x01
line.word 0x00 "VS$1,UDB Channel VS Tile Configuration Vertical Segmentation"
bitfld.word 0x00 4.--7. "VS_BOT,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.word 0x00 0.--3. "VS_TOP,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
tree.end
tree "UDB_P1_U (Single UDB Configuration)"
repeat 2. (list 0. 1.) (list ad:0x400F3200 ad:0x400F3280)
tree "UDB_P1_U$1"
base $2
repeat 12. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x00)++0x03
line.long 0x00 "PLD_IT$1,PLD Input Terms"
bitfld.long 0x00 31. "PLD1_ITxT_7,True input term" "0,1"
bitfld.long 0x00 30. "PLD1_ITxT_6,True input term" "0,1"
newline
bitfld.long 0x00 29. "PLD1_ITxT_5,True input term" "0,1"
bitfld.long 0x00 28. "PLD1_ITxT_4,True input term" "0,1"
newline
bitfld.long 0x00 27. "PLD1_ITxT_3,True input term" "0,1"
bitfld.long 0x00 26. "PLD1_ITxT_2,True input term" "0,1"
newline
bitfld.long 0x00 25. "PLD1_ITxT_1,True input term" "0,1"
bitfld.long 0x00 24. "PLD1_ITxT_0,True input term" "0,1"
newline
bitfld.long 0x00 23. "PLD0_ITxT_7,True input term" "0,1"
bitfld.long 0x00 22. "PLD0_ITxT_6,True input term" "0,1"
newline
bitfld.long 0x00 21. "PLD0_ITxT_5,True input term" "0,1"
bitfld.long 0x00 20. "PLD0_ITxT_4,True input term" "0,1"
newline
bitfld.long 0x00 19. "PLD0_ITxT_3,True input term" "0,1"
bitfld.long 0x00 18. "PLD0_ITxT_2,True input term" "0,1"
newline
bitfld.long 0x00 17. "PLD0_ITxT_1,True input term" "0,1"
bitfld.long 0x00 16. "PLD0_ITxT_0,True input term" "0,1"
newline
bitfld.long 0x00 15. "PLD1_ITxC_7,Complement input term" "0,1"
bitfld.long 0x00 14. "PLD1_ITxC_6,Complement input term" "0,1"
newline
bitfld.long 0x00 13. "PLD1_ITxC_5,Complement input term" "0,1"
bitfld.long 0x00 12. "PLD1_ITxC_4,Complement input term" "0,1"
newline
bitfld.long 0x00 11. "PLD1_ITxC_3,Complement input term" "0,1"
bitfld.long 0x00 10. "PLD1_ITxC_2,Complement input term" "0,1"
newline
bitfld.long 0x00 9. "PLD1_ITxC_1,Complement input term" "0,1"
bitfld.long 0x00 8. "PLD1_ITxC_0,Complement input term" "0,1"
newline
bitfld.long 0x00 7. "PLD0_ITxC_7,Complement input term" "0,1"
bitfld.long 0x00 6. "PLD0_ITxC_6,Complement input term" "0,1"
newline
bitfld.long 0x00 5. "PLD0_ITxC_5,Complement input term" "0,1"
bitfld.long 0x00 4. "PLD0_ITxC_4,Complement input term" "0,1"
newline
bitfld.long 0x00 3. "PLD0_ITxC_3,Complement input term" "0,1"
bitfld.long 0x00 2. "PLD0_ITxC_2,Complement input term" "0,1"
newline
bitfld.long 0x00 1. "PLD0_ITxC_1,Complement input term" "0,1"
bitfld.long 0x00 0. "PLD0_ITxC_0,Complement input term" "0,1"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x2 0x4 0x6 )
group.word ($2+0x30)++0x01
line.word 0x00 "PLD_ORT$1,PLD OR Terms"
bitfld.word 0x00 15. "PLD1_ORT_PTx_7,OR term" "0,1"
bitfld.word 0x00 14. "PLD1_ORT_PTx_6,OR term" "0,1"
newline
bitfld.word 0x00 13. "PLD1_ORT_PTx_5,OR term" "0,1"
bitfld.word 0x00 12. "PLD1_ORT_PTx_4,OR term" "0,1"
newline
bitfld.word 0x00 11. "PLD1_ORT_PTx_3,OR term" "0,1"
bitfld.word 0x00 10. "PLD1_ORT_PTx_2,OR term" "0,1"
newline
bitfld.word 0x00 9. "PLD1_ORT_PTx_1,OR term" "0,1"
bitfld.word 0x00 8. "PLD1_ORT_PTx_0,OR term" "0,1"
newline
bitfld.word 0x00 7. "PLD0_ORT_PTx_7,OR term" "0,1"
bitfld.word 0x00 6. "PLD0_ORT_PTx_6,OR term" "0,1"
newline
bitfld.word 0x00 5. "PLD0_ORT_PTx_5,OR term" "0,1"
bitfld.word 0x00 4. "PLD0_ORT_PTx_4,OR term" "0,1"
newline
bitfld.word 0x00 3. "PLD0_ORT_PTx_3,OR term" "0,1"
bitfld.word 0x00 2. "PLD0_ORT_PTx_2,OR term" "0,1"
newline
bitfld.word 0x00 1. "PLD0_ORT_PTx_1,OR term" "0,1"
bitfld.word 0x00 0. "PLD0_ORT_PTx_0,OR term" "0,1"
repeat.end
group.word 0x38++0x01
line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell configuration for Carry Enable and Constant"
bitfld.word 0x00 15. "PLD1_MC3_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 14. "PLD1_MC3_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 13. "PLD1_MC2_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 12. "PLD1_MC2_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 11. "PLD1_MC1_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 10. "PLD1_MC1_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 9. "PLD1_MC0_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 8. "PLD1_MC0_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 7. "PLD0_MC3_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 6. "PLD0_MC3_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 5. "PLD0_MC2_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 4. "PLD0_MC2_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 3. "PLD0_MC1_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 2. "PLD0_MC1_CEN,Carry enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 1. "PLD0_MC0_DFF_C,DFF Constant" "0: No description available,1: No description available"
bitfld.word 0x00 0. "PLD0_MC0_CEN,Carry enable" "0: No description available,1: No description available"
group.word 0x3A++0x01
line.word 0x00 "PLD_MC_CFG_XORFB,PLD Macro cell XOR feedback"
bitfld.word 0x00 14.--15. "PLD1_MC3_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.word 0x00 12.--13. "PLD1_MC2_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.word 0x00 10.--11. "PLD1_MC1_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.word 0x00 8.--9. "PLD1_MC0_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.word 0x00 6.--7. "PLD0_MC3_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.word 0x00 4.--5. "PLD0_MC2_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.word 0x00 2.--3. "PLD0_MC1_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.word 0x00 0.--1. "PLD0_MC0_XORFB,XOR feedback" "0: No description available,1: No description available,2: No description available,3: No description available"
group.word 0x3C++0x01
line.word 0x00 "PLD_MC_SET_RESET,PLD Macro cell Set Reset Selection"
bitfld.word 0x00 15. "PLD1_MC3_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 14. "PLD1_MC3_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 13. "PLD1_MC2_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 12. "PLD1_MC2_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 11. "PLD1_MC1_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 10. "PLD1_MC1_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 9. "PLD1_MC0_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 8. "PLD1_MC0_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 7. "PLD0_MC3_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 6. "PLD0_MC3_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 5. "PLD0_MC2_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 4. "PLD0_MC2_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 3. "PLD0_MC1_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 2. "PLD0_MC1_SET_SEL,Set select enable" "0: No description available,1: No description available"
newline
bitfld.word 0x00 1. "PLD0_MC0_RESET_SEL,Reset select enable" "0: No description available,1: No description available"
bitfld.word 0x00 0. "PLD0_MC0_SET_SEL,Set select enable" "0: No description available,1: No description available"
group.word 0x3E++0x01
line.word 0x00 "PLD_MC_CFG_BYPASS,PLD Macro cell Bypass control"
bitfld.word 0x00 15. "NC15,Spare register bit" "0,1"
bitfld.word 0x00 14. "PLD1_MC3_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 13. "NC13,Spare register bit" "0,1"
bitfld.word 0x00 12. "PLD1_MC2_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 11. "NC11,Spare register bit" "0,1"
bitfld.word 0x00 10. "PLD1_MC1_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 9. "NC9,Spare register bit" "0,1"
bitfld.word 0x00 8. "PLD1_MC0_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 7. "NC7,Spare register bit" "0,1"
bitfld.word 0x00 6. "PLD0_MC3_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 5. "NC5,Spare register bit" "0,1"
bitfld.word 0x00 4. "PLD0_MC2_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 3. "NC3,Spare register bit" "0,1"
bitfld.word 0x00 2. "PLD0_MC1_BYPASS,Bypass selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 1. "NC1,Spare register bit" "0,1"
bitfld.word 0x00 0. "PLD0_MC0_BYPASS,Bypass selection" "0: No description available,1: No description available"
group.byte 0x40++0x00
line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0"
bitfld.byte 0x00 4.--6. "RAD1,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
bitfld.byte 0x00 0.--2. "RAD0,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.byte 0x41++0x00
line.byte 0x00 "CFG1,Datapath Input Selection - RAD2"
bitfld.byte 0x00 7. "DP_RTE_BYPASS4,DP_In bypass ctl" "0: No description available,1: No description available"
bitfld.byte 0x00 6. "DP_RTE_BYPASS3,DP_In bypass ctl" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 5. "DP_RTE_BYPASS2,DP_In bypass ctl" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "DP_RTE_BYPASS1,DP_In bypass ctl" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 3. "DP_RTE_BYPASS0,DP_In bypass ctl" "0: No description available,1: No description available"
bitfld.byte 0x00 0.--2. "RAD2,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.byte 0x42++0x00
line.byte 0x00 "CFG2,Datapath Input Selection - F1_LD F0_LD"
bitfld.byte 0x00 7. "NC7,Spare register bit" "0,1"
bitfld.byte 0x00 4.--6. "F1_LD,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
newline
bitfld.byte 0x00 3. "DP_RTE_BYPASS5,DP_In bypass ctl" "0: No description available,1: No description available"
bitfld.byte 0x00 0.--2. "F0_LD,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.byte 0x43++0x00
line.byte 0x00 "CFG3,Datapath Input Selection - D1_LD D0_LD"
bitfld.byte 0x00 4.--6. "D1_LD,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
bitfld.byte 0x00 0.--2. "D0_LD,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.byte 0x44++0x00
line.byte 0x00 "CFG4,Datapath Input Selection - CI_MUX SI_MUX"
bitfld.byte 0x00 4.--6. "CI_MUX,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
bitfld.byte 0x00 0.--2. "SI_MUX,Datapath Permutable Input Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
group.byte 0x45++0x00
line.byte 0x00 "CFG5,Datapath Output Selection for OUT1 OUT0"
bitfld.byte 0x00 4.--7. "OUT1,Datapath Permutable Output Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
bitfld.byte 0x00 0.--3. "OUT0,Datapath Permutable Output Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
group.byte 0x46++0x00
line.byte 0x00 "CFG6,Datapath Output Selection for OUT3 OUT2"
bitfld.byte 0x00 4.--7. "OUT3,Datapath Permutable Output Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
bitfld.byte 0x00 0.--3. "OUT2,Datapath Permutable Output Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
group.byte 0x47++0x00
line.byte 0x00 "CFG7,Datapath Output Selection for OUT5 OUT4"
bitfld.byte 0x00 4.--7. "OUT5,Datapath Permutable Output Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
bitfld.byte 0x00 0.--3. "OUT4,Datapath Permutable Output Mux" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,10: No description available,11: No description available,12: No description available,13: No description available,14: No description available,15: No description available"
group.byte 0x48++0x00
line.byte 0x00 "CFG8,Datapath Output Synchronization Option"
bitfld.byte 0x00 7. "NC7,Spare register bit" "0,1"
bitfld.byte 0x00 6. "NC6,Spare register bit" "0,1"
newline
bitfld.byte 0x00 0.--5. "OUT_SYNC,Datapath Output Synchronization" "0: No description available,1: No description available,?..."
group.byte 0x49++0x00
line.byte 0x00 "CFG9,Datapath ALU Mask"
hexmask.byte 0x00 0.--7. 1. "AMASK,Datapath ALU Mask"
group.byte 0x4A++0x00
line.byte 0x00 "CFG10,Datapath Compare 0 Mask"
hexmask.byte 0x00 0.--7. 1. "CMASK0,Datapath Compare 0 Mask"
group.byte 0x4B++0x00
line.byte 0x00 "CFG11,Datapath Compare 1 Mask"
hexmask.byte 0x00 0.--7. 1. "CMASK0,Datapath Compare 1 Mask"
group.byte 0x4C++0x00
line.byte 0x00 "CFG12,Datapath mask enables and shift in configuration"
bitfld.byte 0x00 7. "CMASK1_EN,Datapath mask enable" "0: No description available,1: No description available"
bitfld.byte 0x00 6. "CMASK0_EN,Datapath mask enable" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 5. "AMASK_EN,Datapath mask enable" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "DEF_SI,Datapath default shift value" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2.--3. "SI_SELB,Datapath shift in source select" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "SI_SELA,Datapath shift in source select" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x4D++0x00
line.byte 0x00 "CFG13,Datapath carry in and compare configuration"
bitfld.byte 0x00 6.--7. "CMP_SELB,Datapath compare select" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "CMP_SELA,Datapath compare select" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "CI_SELB,Datapath carry in source select" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "CI_SELA,Datapath carry in source select" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x4E++0x00
line.byte 0x00 "CFG14,Datapath chaining and MSB configuration"
bitfld.byte 0x00 7. "MSB_EN,Datapath MSB selection enable" "0: No description available,1: No description available"
bitfld.byte 0x00 4.--6. "MSB_SEL,Datapath MSB Selection" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
newline
bitfld.byte 0x00 3. "CHAIN_CMSB,Datapath CRC MSB chaining enable" "0: No description available,1: No description available"
bitfld.byte 0x00 2. "CHAIN_FB,Datapath CRC feedback chaining enable" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 1. "CHAIN1,Datapath condition chaining enable" "0: No description available,1: No description available"
bitfld.byte 0x00 0. "CHAIN0,Datapath condition chaining enable" "0: No description available,1: No description available"
group.byte 0x4F++0x00
line.byte 0x00 "CFG15,Datapath FIFO shift and parallel input control"
bitfld.byte 0x00 7. "PI_SEL,Datapath parallel input selection" "0: No description available,1: No description available"
bitfld.byte 0x00 6. "SHIFT_SEL,Datapath shift out selection" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 5. "PI_DYN,Enable for dynamic control of parallel data input (PI) mux" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "MSB_SI,Arithmetic shift right operation shift in selection" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2.--3. "F1_INSEL,Datapath FIFO Configuration" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "F0_INSEL,Datapath FIFO Configuration" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x50++0x00
line.byte 0x00 "CFG16,Datapath FIFO and register access configuration control"
bitfld.byte 0x00 7. "F1_CK_INV,FIFO Clock Invert" "0: No description available,1: No description available"
bitfld.byte 0x00 6. "F0_CK_INV,FIFO Clock Invert" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 5. "FIFO_FAST,FIFO Fast Mode" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "FIFO_CAP,FIFO Software Capture Mode" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 3. "FIFO_EDGE,Edge/level sensitive FIFO write control (Fx_LD)" "0: No description available,1: No description available"
bitfld.byte 0x00 2. "FIFO_ASYNC,Asynchronous FIFO clocking support" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 1. "EXT_CRCPRS,External CRC/PRS mode" "0: No description available,1: No description available"
bitfld.byte 0x00 0. "WRK16_CONCAT,Datapath register access mode" "0: No description available,1: No description available"
group.byte 0x51++0x00
line.byte 0x00 "CFG17,Datapath FIFO control"
bitfld.byte 0x00 4. "FIFO_ADD_SYNC,Adds an additional sync flip-flop to FIFO block status" "0: No description available,1: No description available"
bitfld.byte 0x00 3. "NC3,Spare register bit" "0,1"
newline
bitfld.byte 0x00 2. "NC2,Spare register bit" "0,1"
bitfld.byte 0x00 1. "F1_DYN,No description available" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 0. "F0_DYN,When this bit is set the associated FIFO configuration may be dynamically controlled" "0: No description available,1: No description available"
group.byte 0x52++0x00
line.byte 0x00 "CFG18,Control Register Mode 0 (used in conjunction with Control Register Mode 1)"
hexmask.byte 0x00 0.--7. 1. "CTL_MD0,CTL_MD1 and CTL_MD0 are concatenated to form an encoding for the mode of each control bit in the control register"
group.byte 0x53++0x00
line.byte 0x00 "CFG19,Control Register Mode 1 (used in conjunction with Control Register Mode 0)"
hexmask.byte 0x00 0.--7. 1. "CTL_MD1,CTL_MD1 and CTL_MD0 are concatenated to form an encoding for the mode of each control bit in the control register"
group.byte 0x54++0x00
line.byte 0x00 "CFG20,Status Register input mode selection"
hexmask.byte 0x00 0.--7. 1. "STAT_MD,Mode selection for each bit of the status register"
group.byte 0x55++0x00
line.byte 0x00 "CFG21,Spare register bits"
bitfld.byte 0x00 1. "NC1,Spare register bit" "0,1"
bitfld.byte 0x00 0. "NC0,Spare register bit" "0,1"
group.byte 0x56++0x00
line.byte 0x00 "CFG22,SC block configuration control"
bitfld.byte 0x00 4. "SC_EXT_RES,Control register external reset operation" "0: No description available,1: No description available"
bitfld.byte 0x00 3. "SC_SYNC_MD,SC Sync Mode - controls when the status register operates as a 4-bit double synchronizer module" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2. "SC_INT_MD,SC Interrupt Mode - controls when the UDB driving an interrupt generated from the masked OR reduction of status bits 6 to 0" "0: No description available,1: No description available"
bitfld.byte 0x00 0.--1. "SC_OUT_CTL,Selects the output source for the Status and Control routing connections" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x57++0x00
line.byte 0x00 "CFG23,Counter Control"
bitfld.byte 0x00 6. "ALT_CNT,Configure the alternate operating mode of the counter" "0: No description available,1: No description available"
bitfld.byte 0x00 5. "ROUTE_EN,Configure the counter enable signal for routing input" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 4. "ROUTE_LD,Configure the counter load signal for routing input" "0: No description available,1: No description available"
bitfld.byte 0x00 2.--3. "CNT_EN_SEL,Selects the routing inputs for the counter enable signal" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 0.--1. "CNT_LD_SEL,Selects the routing inputs for the counter load signal" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x58++0x00
line.byte 0x00 "CFG24,PLD0 Clock and Reset control"
bitfld.byte 0x00 7. "RC_RES_SEL1,Configures the routed reset for the associated UDB component block" "0,1"
bitfld.byte 0x00 6. "RC_RES_SEL0_OR_FRES,Configures the routed or firmware reset for the associated UDB component block" "0,1"
newline
bitfld.byte 0x00 5. "RC_INV,Optionally inverts the clock selection for the associated UDB component block" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "RC_EN_INV,Optionally inverts the clock enable selection for the associated UDB component blocks" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2.--3. "RC_EN_MODE,Selects the operating mode for the clock to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "RC_EN_SEL,Selects channel route for enable control to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x59++0x00
line.byte 0x00 "CFG25,PLD1 Clock and Reset control"
bitfld.byte 0x00 7. "RC_RES_SEL1,Configures the routed reset for the associated UDB component block" "0,1"
bitfld.byte 0x00 6. "RC_RES_SEL0_OR_FRES,Configures the routed or firmware reset for the associated UDB component block" "0,1"
newline
bitfld.byte 0x00 5. "RC_INV,Optionally inverts the clock selection for the associated UDB component block" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "RC_EN_INV,Optionally inverts the clock enable selection for the associated UDB component blocks" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2.--3. "RC_EN_MODE,Selects the operating mode for the clock to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "RC_EN_SEL,Selects channel route for enable control to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x5A++0x00
line.byte 0x00 "CFG26,Datapath Clock and Reset control"
bitfld.byte 0x00 7. "RC_RES_SEL1,Configures the routed reset for the associated UDB component block" "0,1"
bitfld.byte 0x00 6. "RC_RES_SEL0_OR_FRES,Configures the routed or firmware reset for the associated UDB component block" "0,1"
newline
bitfld.byte 0x00 5. "RC_INV,Optionally inverts the clock selection for the associated UDB component block" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "RC_EN_INV,Optionally inverts the clock enable selection for the associated UDB component blocks" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2.--3. "RC_EN_MODE,Selects the operating mode for the clock to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "RC_EN_SEL,Selects channel route for enable control to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x5B++0x00
line.byte 0x00 "CFG27,Status/Control Clock and Reset control"
bitfld.byte 0x00 7. "RC_RES_SEL1,Configures the routed reset for the associated UDB component block" "0,1"
bitfld.byte 0x00 6. "RC_RES_SEL0_OR_FRES,Configures the routed or firmware reset for the associated UDB component block" "0,1"
newline
bitfld.byte 0x00 5. "RC_INV,Optionally inverts the clock selection for the associated UDB component block" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "RC_EN_INV,Optionally inverts the clock enable selection for the associated UDB component blocks" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2.--3. "RC_EN_MODE,Selects the operating mode for the clock to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "RC_EN_SEL,Selects channel route for enable control to the associated UDB component block" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x5C++0x00
line.byte 0x00 "CFG28,Clock Selection for PLD1 and PLD0"
bitfld.byte 0x00 4.--7. "PLD1_CK_SEL,Clock selection registers" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,?..."
bitfld.byte 0x00 0.--3. "PLD0_CK_SEL,Clock selection registers" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,?..."
group.byte 0x5D++0x00
line.byte 0x00 "CFG29,Clock Selection for Datapath Status and Control"
bitfld.byte 0x00 4.--7. "SC_CK_SEL,Clock selection registers" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,?..."
bitfld.byte 0x00 0.--3. "DP_CK_SEL,Clock selection registers" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,8: No description available,9: No description available,?..."
group.byte 0x5E++0x00
line.byte 0x00 "CFG30,Reset control"
bitfld.byte 0x00 7. "SC_RES_POL,Only valid when ALT RES (CFG31) is '1'" "0: No description available,1: No description available"
bitfld.byte 0x00 6. "DP_RES_POL,Only valid when ALT RES (CFG31) is '1'" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 4. "GUDB_WR,Enable global write operation for the configuration and working registers in this UDB" "0: No description available,1: No description available"
bitfld.byte 0x00 3. "EN_RES_CNTCTL,This bit gates the routed reset to the counter/control register" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2. "RES_POL,The meaning of this bit depends on the value of the ALT RES bit in CFG31" "0: No description available,1: No description available"
bitfld.byte 0x00 0.--1. "RES_SEL,The meaning of this bit depends on the value of ALT RES (CFG31)" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x5F++0x00
line.byte 0x00 "CFG31,Reset control"
bitfld.byte 0x00 7. "PLD1_RES_POL,Not connected" "0: No description available,1: No description available"
bitfld.byte 0x00 6. "PLD0_RES_POL,The meaning of this bit depends on the value of ALT RES" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 4.--5. "EXT_CK_SEL,External clock selection" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 3. "EN_RES_DP,Only valid when ALT RES (CFG31) is '1'" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 2. "EN_RES_STAT,Only valid when ALT RES (CFG31) is '1'" "0: No description available,1: No description available"
bitfld.byte 0x00 1. "EXT_SYNC,Enable synchronization of selected external clock" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 0. "ALT_RES,This bit toggles between two reset configurations" "0: No description available,1: No description available"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x2 0x4 0x6 0x8 0xA 0xC 0xE )
group.word ($2+0x60)++0x01
line.word 0x00 "DCFG$1,Dynamic Configuration RAM"
bitfld.word 0x00 13.--15. "FUNC,Dynamic ALU function selection" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available"
bitfld.word 0x00 12. "SRC_A,Dynamic ALU source A selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 10.--11. "SRC_B,Dynamic ALU source B selection" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.word 0x00 8.--9. "SHIFT,Dynamic shift selection" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.word 0x00 6.--7. "A0_WR_SRC,Dynamic A0 write source selection" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.word 0x00 4.--5. "A1_WR_SRC,Dynamic A1 write source selection" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.word 0x00 3. "CFB_EN,Dynamic CRC feedback selection" "0: No description available,1: No description available"
bitfld.word 0x00 2. "CI_SEL,Dynamic carry in selection" "0: No description available,1: No description available"
newline
bitfld.word 0x00 1. "SI_SEL,Dynamic shift in selection" "0: No description available,1: No description available"
bitfld.word 0x00 0. "CMP_SEL,Dynamic compare selection" "0: No description available,1: No description available"
repeat.end
tree.end
repeat.end
tree.end
tree "UDB_PA (Port Adapter Configuration)"
repeat 4. (list 0. 1. 2. 3.) (list ad:0x400F5000 ad:0x400F5010 ad:0x400F5020 ad:0x400F5030)
tree "UDB_PA$1"
base $2
group.byte 0x00++0x00
line.byte 0x00 "CFG0,PA Data In Clock Control Register"
bitfld.byte 0x00 6.--7. "NC,Spare register bits" "0,1,2,3"
bitfld.byte 0x00 5. "CLKIN_INV,Determines whether the selected clock is inverted or not" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 4. "CLKIN_EN_INV,Determines whether the selected enable is inverted or not" "0: No description available,1: No description available"
bitfld.byte 0x00 2.--3. "CLKIN_EN_MODE,Select one of four operating modes" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 0.--1. "CLKIN_EN_SEL,Select one of four choices for clock enable" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x01++0x00
line.byte 0x00 "CFG1,PA Data Out Clock Control Register"
bitfld.byte 0x00 6.--7. "NC,Spare register bits" "0,1,2,3"
bitfld.byte 0x00 5. "CLKOUT_INV,Determines whether the selected clock is inverted or not" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 4. "CLKOUT_EN_INV,Determines whether the selected enable is inverted or not" "0: No description available,1: No description available"
bitfld.byte 0x00 2.--3. "CLKOUT_EN_MODE,Select one of four operating modes" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 0.--1. "CLKOUT_EN_SEL,Select one of four choices for clock enable" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x02++0x00
line.byte 0x00 "CFG2,PA Clock Select Register"
bitfld.byte 0x00 4.--7. "CLKOUT_SEL,Select one of four choices for clock enable" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,?,9: No description available,?,?,12: No description available,13: No description available,14: No description available,15: No description available"
bitfld.byte 0x00 0.--3. "CLKIN_SEL,Select one of four choices for clock enable" "0: No description available,1: No description available,2: No description available,3: No description available,4: No description available,5: No description available,6: No description available,7: No description available,?,9: No description available,?,?,12: No description available,13: No description available,14: No description available,15: No description available"
group.byte 0x03++0x00
line.byte 0x00 "CFG3,PA Reset Select Register"
bitfld.byte 0x00 7. "NC7,Spare register bit" "0,1"
bitfld.byte 0x00 6. "RES_OUT_INV,Select the polarity of the reset control" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 4.--5. "RES_OUT_SEL,Select one of four inputs to serve as the reset control to the block" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 3. "NC0,Spare register bit" "0,1"
newline
bitfld.byte 0x00 2. "RES_IN_INV,Select the polarity of the reset control" "0: No description available,1: No description available"
bitfld.byte 0x00 0.--1. "RES_IN_SEL,Select one of four inputs to serve as the reset control to the block" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x04++0x00
line.byte 0x00 "CFG4,PA Reset Enable Register"
bitfld.byte 0x00 3.--7. "NC7654,Spare register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 2. "RES_OE_EN,Enable the selected reset" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 1. "RES_OUT_EN,Enable the selected reset" "0: No description available,1: No description available"
bitfld.byte 0x00 0. "RES_IN_EN,Enable the selected reset" "0: No description available,1: No description available"
group.byte 0x05++0x00
line.byte 0x00 "CFG5,PA Reset Pin Select Register"
bitfld.byte 0x00 3.--7. "NC7654,Spare register bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.byte 0x00 0. "PIN_SEL,Select port input to route to reset multiplexer (dsi_xx_input_p[7:0])" "0: No description available,1: No description available"
group.byte 0x06++0x00
line.byte 0x00 "CFG6,PA Input Data Sync Control Register - Low"
bitfld.byte 0x00 6.--7. "IN_SYNC3,Synchronization selection for PA input 3" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "IN_SYNC2,Synchronization selection for PA input 2" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "IN_SYNC1,Synchronization selection for PA input 1" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "IN_SYNC0,Synchronization selection for PA input 0" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x07++0x00
line.byte 0x00 "CFG7,PA Input Data Sync Control Register - High"
bitfld.byte 0x00 6.--7. "IN_SYNC7,Synchronization selection for PA input 7" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "IN_SYNC6,Synchronization selection for PA input 6" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "IN_SYNC5,Synchronization selection for PA input 5" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "IN_SYNC4,Synchronization selection for PA input 4" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x08++0x00
line.byte 0x00 "CFG8,PA Output Data Sync Control Register - Low"
bitfld.byte 0x00 6.--7. "OUT_SYNC3,Synchronization selection for PA output 3" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "OUT_SYNC2,Synchronization selection for PA output 2" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "OUT_SYNC1,Synchronization selection for PA output 1" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "OUT_SYNC0,Synchronization selection for PA output 0" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x09++0x00
line.byte 0x00 "CFG9,PA Output Data Sync Control Register - High"
bitfld.byte 0x00 6.--7. "OUT_SYNC7,Synchronization selection for PA output 7" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "OUT_SYNC6,Synchronization selection for PA output 6" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "OUT_SYNC5,Synchronization selection for PA output 5" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "OUT_SYNC4,Synchronization selection for PA output 4" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x0A++0x00
line.byte 0x00 "CFG10,PA Output Data Select Register - Low"
bitfld.byte 0x00 6.--7. "DATA_SEL3,Data selection for PA output 3" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "DATA_SEL2,Data selection for PA output 2" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "DATA_SEL1,Data selection for PA output 1" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "DATA_SEL0,Data selection for PA output 0" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x0B++0x00
line.byte 0x00 "CFG11,PA Output Data Select Register - High"
bitfld.byte 0x00 6.--7. "DATA_SEL7,Data selection for PA output 7" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "DATA_SEL6,Data selection for PA output 6" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "DATA_SEL5,Data selection for PA output 5" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "DATA_SEL4,Data selection for PA output 4" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x0C++0x00
line.byte 0x00 "CFG12,PA OE Select Register - Low"
bitfld.byte 0x00 6.--7. "OE_SEL3,Data selection for PA oe 3" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "OE_SEL2,Data selection for PA oe 2" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "OE_SEL1,Data selection for PA oe 1" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "OE_SEL0,Data selection for PA oe 0" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x0D++0x00
line.byte 0x00 "CFG13,PA OE Select Register - High"
bitfld.byte 0x00 6.--7. "OE_SEL7,Data selection for PA oe 7" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "OE_SEL6,Data selection for PA oe 6" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "OE_SEL5,Data selection for PA oe 5" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "OE_SEL4,Data selection for PA oe 4" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x0E++0x00
line.byte 0x00 "CFG14,PA OE Sync Register"
bitfld.byte 0x00 6.--7. "OE_SYNC3,Synchronization options for dsi_to_oe[3]" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "OE_SYNC2,Synchronization options for dsi_to_oe[2]" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "OE_SYNC1,Synchronization options for dsi_to_oe[1]" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "OE_SYNC0,Synchronization options for dsi_to_oe[0]" "0: No description available,1: No description available,2: No description available,3: No description available"
tree.end
repeat.end
tree.end
tree "UDB_UDBIF (UDB Subsystem Interface Configuration)"
base ad:0x400F7000
group.byte 0x00++0x00
line.byte 0x00 "BANK_CTL,Bank Control"
bitfld.byte 0x00 7. "GLBL_WR,UDB Array Global Writing Option" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "PIPE,Pipelining Control" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 3. "LOCK,UDB Array Configuration Locking" "0: No description available,1: No description available"
bitfld.byte 0x00 2. "BANK_EN,Enable Bank" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 1. "ROUTE_EN,Enable Routing" "0: No description available,1: No description available"
bitfld.byte 0x00 0. "DIS_COR,Selection of Clear-On-Read" "0: No description available,1: No description available"
group.byte 0x01++0x00
line.byte 0x00 "WAIT_CFG,Wait States Configuration"
bitfld.byte 0x00 6.--7. "WR_WRK_WAIT,Write Work Wait States" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 4.--5. "RD_WRK_WAIT,Read Work Wait States" "0: No description available,1: No description available,2: No description available,3: No description available"
newline
bitfld.byte 0x00 2.--3. "WR_CFG_WAIT,Write Configuration Wait States" "0: No description available,1: No description available,2: No description available,3: No description available"
bitfld.byte 0x00 0.--1. "RD_CFG_WAIT,Read Configuration Wait States" "0: No description available,1: No description available,2: No description available,3: No description available"
group.byte 0x1C++0x00
line.byte 0x00 "INT_CLK_CTL,Interrupt Synchronizer Clock Control"
rbitfld.byte 0x00 0. "EN_HFCLK,This bit enables the interrupt synchronizer in the UDB interface" "0,1"
tree.end
tree "UDB_W (UDB Working Registers 8-bit mode (1 UDB at a time))"
tree "UDB_W8"
base ad:0x400F0000
repeat 4. (strings "00" "01" "02" "03" )(list 0x0 0x1 0x2 0x3 )
group.byte ($2+0x00)++0x00
line.byte 0x00 "A0_$1,Accumulator 0"
hexmask.byte 0x00 0.--7. 1. "A0,Accumulator 0"
repeat.end
repeat 4. (strings "00" "01" "02" "03" )(list 0x0 0x1 0x2 0x3 )
group.byte ($2+0x10)++0x00
line.byte 0x00 "A1_$1,Accumulator 1"
hexmask.byte 0x00 0.--7. 1. "A1,Accumulator 1"
repeat.end
repeat 4. (strings "00" "01" "02" "03" )(list 0x0 0x1 0x2 0x3 )
group.byte ($2+0x20)++0x00
line.byte 0x00 "D0_$1,Data 0"
hexmask.byte 0x00 0.--7. 1. "D0,Data 0"
repeat.end
repeat 4. (strings "00" "01" "02" "03" )(list 0x0 0x1 0x2 0x3 )
group.byte ($2+0x30)++0x00
line.byte 0x00 "D1_$1,Data 1"
hexmask.byte 0x00 0.--7. 1. "D1,Data 1"
repeat.end
repeat 4. (strings "00" "01" "02" "03" )(list 0x0 0x1 0x2 0x3 )
group.byte ($2+0x40)++0x00
line.byte 0x00 "F0_$1,FIFO 0"
hexmask.byte 0x00 0.--7. 1. "F0,Fifo 0"
repeat.end
repeat 4. (strings "00" "01" "02" "03" )(list 0x0 0x1 0x2 0x3 )
group.byte ($2+0x50)++0x00
line.byte 0x00 "F1_$1,FIFO 1"
hexmask.byte 0x00 0.--7. 1. "F1,Fifo 1"
repeat.end
repeat 4. (strings "00" "01" "02" "03" )(list 0x0 0x1 0x2 0x3 )
group.byte ($2+0x60)++0x00
line.byte 0x00 "ST_$1,Status Register"
hexmask.byte 0x00 0.--7. 1. "ST,Status register"
repeat.end
repeat 4. (strings "00" "01" "02" "03" )(list 0x0 0x1 0x2 0x3 )
group.byte ($2+0x70)++0x00
line.byte 0x00 "CTL_$1,Control Register"
hexmask.byte 0x00 0.--7. 1. "CTL,Control register"
repeat.end
repeat 4. (strings "00" "01" "02" "03" )(list 0x0 0x1 0x2 0x3 )
group.byte ($2+0x80)++0x00
line.byte 0x00 "MSK_$1,Interrupt Mask"
hexmask.byte 0x00 0.--6. 1. "MSK,Interrupt Mask Register"
repeat.end
repeat 4. (strings "00" "01" "02" "03" )(list 0x0 0x1 0x2 0x3 )
group.byte ($2+0x90)++0x00
line.byte 0x00 "ACTL_$1,Auxiliary Control"
bitfld.byte 0x00 5. "CNT_START,Control Register Counter Enable" "0: No description available,1: No description available"
bitfld.byte 0x00 4. "INT_EN,enable interrupt" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 3. "FIFO1_LVL,FIFO fill status level control" "0: No description available,1: No description available"
bitfld.byte 0x00 2. "FIFO0_LVL,FIFO fill status level control" "0: No description available,1: No description available"
newline
bitfld.byte 0x00 1. "FIFO1_CLR,FIFO clear" "0: No description available,1: No description available"
bitfld.byte 0x00 0. "FIFO0_CLR,FIFO clear" "0: No description available,1: No description available"
repeat.end
repeat 4. (strings "00" "01" "02" "03" )(list 0x0 0x1 0x2 0x3 )
group.byte ($2+0xA0)++0x00
line.byte 0x00 "MC_$1,PLD Macrocell reading"
rbitfld.byte 0x00 4.--7. "PLD1_MC,Read Macrocell 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.byte 0x00 0.--3. "PLD0_MC,Read Macrocell 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
tree.end
tree "UDB_W16"
base ad:0x400F1000
repeat 3. (strings "00" "01" "02" )(list 0x0 0x2 0x4 )
group.word ($2+0x00)++0x01
line.word 0x00 "A0_$1,Accumulator 0"
hexmask.word.byte 0x00 8.--15. 1. "A0_MS,Accumulator 0 for UDB[n+1]"
hexmask.word.byte 0x00 0.--7. 1. "A0_LS,Accumulator 0 for UDB[n]"
repeat.end
repeat 3. (strings "00" "01" "02" )(list 0x0 0x2 0x4 )
group.word ($2+0x20)++0x01
line.word 0x00 "A1_$1,Accumulator 1"
hexmask.word.byte 0x00 8.--15. 1. "A1_MS,Accumulator 1 for UDB[n+1]"
hexmask.word.byte 0x00 0.--7. 1. "A1_LS,Accumulator 1 for UDB[n]"
repeat.end
repeat 3. (strings "00" "01" "02" )(list 0x0 0x2 0x4 )
group.word ($2+0x40)++0x01
line.word 0x00 "D0_$1,Data 0"
hexmask.word.byte 0x00 8.--15. 1. "D0_MS,Data 0 for UDB[n+1]"
hexmask.word.byte 0x00 0.--7. 1. "D0_LS,Data 0 for UDB[n]"
repeat.end
repeat 3. (strings "00" "01" "02" )(list 0x0 0x2 0x4 )
group.word ($2+0x60)++0x01
line.word 0x00 "D1_$1,Data 1"
hexmask.word.byte 0x00 8.--15. 1. "D1_MS,Data 1 for UDB[n+1]"
hexmask.word.byte 0x00 0.--7. 1. "D1_LS,Data 1 for UDB[n]"
repeat.end
repeat 3. (strings "00" "01" "02" )(list 0x0 0x2 0x4 )
group.word ($2+0x80)++0x01
line.word 0x00 "F0_$1,FIFO 0"
hexmask.word.byte 0x00 8.--15. 1. "F0_MS,Fifo 0 for UDB[n+1]"
hexmask.word.byte 0x00 0.--7. 1. "F0_LS,Fifo 0 for UDB[n]"
repeat.end
repeat 3. (strings "00" "01" "02" )(list 0x0 0x2 0x4 )
group.word ($2+0xA0)++0x01
line.word 0x00 "F1_$1,FIFO 1"
hexmask.word.byte 0x00 8.--15. 1. "F1_MS,Fifo 1 for UDB[n+1]"
hexmask.word.byte 0x00 0.--7. 1. "F1_LS,Fifo 1 for UDB[n]"
repeat.end
repeat 3. (strings "00" "01" "02" )(list 0x0 0x2 0x4 )
group.word ($2+0xC0)++0x01
line.word 0x00 "ST_$1,Status Register"
hexmask.word.byte 0x00 8.--15. 1. "ST_MS,Status register for UDB[n+1]"
hexmask.word.byte 0x00 0.--7. 1. "ST_LS,Status register for UDB[n]"
repeat.end
repeat 3. (strings "00" "01" "02" )(list 0x0 0x2 0x4 )
group.word ($2+0xE0)++0x01
line.word 0x00 "CTL_$1,Control Register"
hexmask.word.byte 0x00 8.--15. 1. "CTL_MS,Control register for UDB[n+1]"
hexmask.word.byte 0x00 0.--7. 1. "CTL_LS,Control register for UDB[n]"
repeat.end
repeat 3. (strings "00" "01" "02" )(list 0x00 0x02 0x04 )
group.word ($2+0x100)++0x01
line.word 0x00 "MSK_$1,Interrupt Mask"
hexmask.word.byte 0x00 8.--14. 1. "MSK_MS,Interrupt Mask Register"
hexmask.word.byte 0x00 0.--6. 1. "MSK_LS,Interrupt Mask Register"
repeat.end
repeat 3. (strings "00" "01" "02" )(list 0x00 0x02 0x04 )
group.word ($2+0x120)++0x01
line.word 0x00 "ACTL_$1,Auxiliary Control"
bitfld.word 0x00 13. "CNT_START_MS,Control Register Counter Enable" "0: No description available,1: No description available"
bitfld.word 0x00 12. "INT_EN_MS,enable interrupt" "0: No description available,1: No description available"
newline
bitfld.word 0x00 11. "FIFO1_LVL_MS,FIFO fill status level control" "0: No description available,1: No description available"
bitfld.word 0x00 10. "FIFO0_LVL_MS,FIFO fill status level control" "0: No description available,1: No description available"
newline
bitfld.word 0x00 9. "FIFO1_CLR_MS,FIFO clear" "0: No description available,1: No description available"
bitfld.word 0x00 8. "FIFO0_CLR_MS,FIFO clear" "0: No description available,1: No description available"
newline
bitfld.word 0x00 5. "CNT_START_LS,Control Register Counter Enable" "0: No description available,1: No description available"
bitfld.word 0x00 4. "INT_EN_LS,enable interrupt" "0: No description available,1: No description available"
newline
bitfld.word 0x00 3. "FIFO1_LVL_LS,FIFO fill status level control" "0: No description available,1: No description available"
bitfld.word 0x00 2. "FIFO0_LVL_LS,FIFO fill status level control" "0: No description available,1: No description available"
newline
bitfld.word 0x00 1. "FIFO1_CLR_LS,FIFO clear" "0: No description available,1: No description available"
bitfld.word 0x00 0. "FIFO0_CLR_LS,FIFO clear" "0: No description available,1: No description available"
repeat.end
repeat 3. (strings "00" "01" "02" )(list 0x00 0x02 0x04 )
group.word ($2+0x140)++0x01
line.word 0x00 "MC_$1,PLD Macrocell reading"
rbitfld.word 0x00 12.--15. "PLD1_MC_MS,Read Macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.word 0x00 8.--11. "PLD0_MC_MS,Read Macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.word 0x00 4.--7. "PLD1_MC_LS,Read Macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.word 0x00 0.--3. "PLD0_MC_LS,Read Macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat.end
tree.end
tree "UDB_W32"
base ad:0x400F2000
group.long 0x00++0x03
line.long 0x00 "A0_00,Accumulator 0"
hexmask.long.byte 0x00 24.--31. 1. "A0_3,Accumulator 0 for UDB[n+3]"
hexmask.long.byte 0x00 16.--23. 1. "A0_2,Accumulator 0 for UDB[n+2]"
newline
hexmask.long.byte 0x00 8.--15. 1. "A0_1,Accumulator 0 for UDB[n+1]"
hexmask.long.byte 0x00 0.--7. 1. "A0_0,Accumulator 0 for UDB[n]"
group.long 0x40++0x03
line.long 0x00 "A1_00,Accumulator 1"
hexmask.long.byte 0x00 24.--31. 1. "A1_3,Accumulator 1 for UDB[n+3]"
hexmask.long.byte 0x00 16.--23. 1. "A1_2,Accumulator 1 for UDB[n+2]"
newline
hexmask.long.byte 0x00 8.--15. 1. "A1_1,Accumulator 1 for UDB[n+1]"
hexmask.long.byte 0x00 0.--7. 1. "A1_0,Accumulator 1 for UDB[n]"
group.long 0x80++0x03
line.long 0x00 "D0_00,Data 0"
hexmask.long.byte 0x00 24.--31. 1. "D0_3,Data 0 for UDB[n+3]"
hexmask.long.byte 0x00 16.--23. 1. "D0_2,Data 0 for UDB[n+2]"
newline
hexmask.long.byte 0x00 8.--15. 1. "D0_1,Data 0 for UDB[n+1]"
hexmask.long.byte 0x00 0.--7. 1. "D0_0,Data 0 for UDB[n]"
group.long 0xC0++0x03
line.long 0x00 "D1_00,Data 1"
hexmask.long.byte 0x00 24.--31. 1. "D1_3,Data 1 for UDB[n+3]"
hexmask.long.byte 0x00 16.--23. 1. "D1_2,Data 1 for UDB[n+2]"
newline
hexmask.long.byte 0x00 8.--15. 1. "D1_1,Data 1 for UDB[n+1]"
hexmask.long.byte 0x00 0.--7. 1. "D1_0,Data 1 for UDB[n]"
group.long 0x100++0x03
line.long 0x00 "F0_00,FIFO 0"
hexmask.long.byte 0x00 24.--31. 1. "F0_3,Fifo 0 for UDB[n+3]"
hexmask.long.byte 0x00 16.--23. 1. "F0_2,Fifo 0 for UDB[n+2]"
newline
hexmask.long.byte 0x00 8.--15. 1. "F0_1,Fifo 0 for UDB[n+1]"
hexmask.long.byte 0x00 0.--7. 1. "F0_0,Fifo 0 for UDB[n]"
group.long 0x140++0x03
line.long 0x00 "F1_00,FIFO 1"
hexmask.long.byte 0x00 24.--31. 1. "F1_3,Fifo 1 for UDB[n+3]"
hexmask.long.byte 0x00 16.--23. 1. "F1_2,Fifo 1 for UDB[n+2]"
newline
hexmask.long.byte 0x00 8.--15. 1. "F1_1,Fifo 1 for UDB[n+1]"
hexmask.long.byte 0x00 0.--7. 1. "F1_0,Fifo 1 for UDB[n]"
group.long 0x180++0x03
line.long 0x00 "ST_00,Status Register"
hexmask.long.byte 0x00 24.--31. 1. "ST_3,Status register for UDB[n+3]"
hexmask.long.byte 0x00 16.--23. 1. "ST_2,Status register for UDB[n+2]"
newline
hexmask.long.byte 0x00 8.--15. 1. "ST_1,Status register for UDB[n+1]"
hexmask.long.byte 0x00 0.--7. 1. "ST_0,Status register for UDB[n]"
group.long 0x1C0++0x03
line.long 0x00 "CTL_00,Control Register"
hexmask.long.byte 0x00 24.--31. 1. "CTL_3,Control register for UDB[n+3]"
hexmask.long.byte 0x00 16.--23. 1. "CTL_2,Control register for UDB[n+2]"
newline
hexmask.long.byte 0x00 8.--15. 1. "CTL_1,Control register for UDB[n+1]"
hexmask.long.byte 0x00 0.--7. 1. "CTL_0,Control register for UDB[n]"
group.long 0x200++0x03
line.long 0x00 "MSK_00,Interrupt Mask"
hexmask.long.byte 0x00 24.--30. 1. "MSK_3,Interrupt Mask Register"
hexmask.long.byte 0x00 16.--22. 1. "MSK_2,Interrupt Mask Register"
newline
hexmask.long.byte 0x00 8.--14. 1. "MSK_1,Interrupt Mask Register"
hexmask.long.byte 0x00 0.--6. 1. "MSK_0,Interrupt Mask Register"
group.long 0x240++0x03
line.long 0x00 "ACTL_00,Auxiliary Control"
bitfld.long 0x00 29. "CNT_START_3,Control Register Counter Enable" "0: No description available,1: No description available"
bitfld.long 0x00 28. "INT_EN_3,enable interrupt" "0: No description available,1: No description available"
newline
bitfld.long 0x00 27. "FIFO1_LVL_3,FIFO fill status level control" "0: No description available,1: No description available"
bitfld.long 0x00 26. "FIFO0_LVL_3,FIFO fill status level control" "0: No description available,1: No description available"
newline
bitfld.long 0x00 25. "FIFO1_CLR_3,FIFO clear" "0: No description available,1: No description available"
bitfld.long 0x00 24. "FIFO0_CLR_3,FIFO clear" "0: No description available,1: No description available"
newline
bitfld.long 0x00 21. "CNT_START_2,Control Register Counter Enable" "0: No description available,1: No description available"
bitfld.long 0x00 20. "INT_EN_2,enable interrupt" "0: No description available,1: No description available"
newline
bitfld.long 0x00 19. "FIFO1_LVL_2,FIFO fill status level control" "0: No description available,1: No description available"
bitfld.long 0x00 18. "FIFO0_LVL_2,FIFO fill status level control" "0: No description available,1: No description available"
newline
bitfld.long 0x00 17. "FIFO1_CLR_2,FIFO clear" "0: No description available,1: No description available"
bitfld.long 0x00 16. "FIFO0_CLR_2,FIFO clear" "0: No description available,1: No description available"
newline
bitfld.long 0x00 13. "CNT_START_1,Control Register Counter Enable" "0: No description available,1: No description available"
bitfld.long 0x00 12. "INT_EN_1,enable interrupt" "0: No description available,1: No description available"
newline
bitfld.long 0x00 11. "FIFO1_LVL_1,FIFO fill status level control" "0: No description available,1: No description available"
bitfld.long 0x00 10. "FIFO0_LVL_1,FIFO fill status level control" "0: No description available,1: No description available"
newline
bitfld.long 0x00 9. "FIFO1_CLR_1,FIFO clear" "0: No description available,1: No description available"
bitfld.long 0x00 8. "FIFO0_CLR_1,FIFO clear" "0: No description available,1: No description available"
newline
bitfld.long 0x00 5. "CNT_START_0,Control Register Counter Enable" "0: No description available,1: No description available"
bitfld.long 0x00 4. "INT_EN_0,enable interrupt" "0: No description available,1: No description available"
newline
bitfld.long 0x00 3. "FIFO1_LVL_0,FIFO fill status level control" "0: No description available,1: No description available"
bitfld.long 0x00 2. "FIFO0_LVL_0,FIFO fill status level control" "0: No description available,1: No description available"
newline
bitfld.long 0x00 1. "FIFO1_CLR_0,FIFO clear" "0: No description available,1: No description available"
bitfld.long 0x00 0. "FIFO0_CLR_0,FIFO clear" "0: No description available,1: No description available"
group.long 0x280++0x03
line.long 0x00 "MC_00,PLD Macrocell reading"
rbitfld.long 0x00 28.--31. "PLD1_MC_3,Read Macrocell 1 for UDB[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 24.--27. "PLD0_MC_3,Read Macrocell 0 for UDB[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20.--23. "PLD1_MC_2,Read Macrocell 1 for UDB[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 16.--19. "PLD0_MC_2,Read Macrocell 0 for UDB[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 12.--15. "PLD1_MC_1,Read Macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 8.--11. "PLD0_MC_1,Read Macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 4.--7. "PLD1_MC_0,Read Macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 0.--3. "PLD0_MC_0,Read Macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
tree.end
autoindent.off
newline
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