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woody d411edd9b4 add Trace32 File
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; --------------------------------------------------------------------------------
; @Title: PSOC4100SMAX On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2023-10-30 NEJ
; @Manufacturer: INFINEON - Infineon Technologies AG
; @Doc: Generated (TRACE32, build: 164352.), based on:
; psoc4100smax.svd (Ver. 1.0)
; @Core: Cortex-M0+
; @Chip: CY8C4147AZE-S598, CY8C4147AZE-S578, CY8C4148AZE-S598, CY8C4148LDE-S573,
; CY8C4148LDE-S593, CY8C4147AZA-S548, CY8C4147AZE-S548, CY8C4147AZS-S548,
; CY8C4147AZA-S555, CY8C4147AZS-S555, CY8C4147AZE-S555, CY8C4147AZA-S558,
; CY8C4147AZS-S558, CY8C4147AZE-S558, CY8C4147AZA-S565, CY8C4147AZS-S565,
; CY8C4147AZE-S565, CY8C4147AZA-S568, CY8C4147AZS-S568, CY8C4147AZE-S568,
; CY8C4147AZA-S575, CY8C4147AZS-S575, CY8C4147AZE-S575, CY8C4147AZA-S578,
; CY8C4147AZS-S578, CY8C4147AZA-S585, CY8C4147AZS-S585, CY8C4147AZE-S585,
; CY8C4147AZA-S588, CY8C4147AZS-S588, CY8C4147AZE-S588, CY8C4147AZA-S595,
; CY8C4147AZS-S595, CY8C4147AZE-S595, CY8C4147AZA-S598, CY8C4147AZS-S598,
; CY8C4148AZA-S545, CY8C4148AZS-S545, CY8C4148AZE-S545, CY8C4148AZA-S548,
; CY8C4148AZS-S548, CY8C4148AZE-S548, CY8C4148AZA-S555, CY8C4148AZS-S555,
; CY8C4148AZE-S555, CY8C4148AZA-S558, CY8C4148AZS-S558, CY8C4148AZE-S558,
; CY8C4148AZA-S565, CY8C4148AZS-S565, CY8C4148AZE-S565, CY8C4148AZA-S568,
; CY8C4148AZS-S568, CY8C4148AZE-S568, CY8C4148AZA-S575, CY8C4148AZS-S575,
; CY8C4148AZE-S575, CY8C4148AZA-S578, CY8C4148AZS-S578, CY8C4148AZE-S578,
; CY8C4148AZA-S585, CY8C4148AZS-S585, CY8C4148AZE-S585, CY8C4148AZA-S588,
; CY8C4148AZS-S588, CY8C4148AZE-S588, CY8C4148AZA-S595, CY8C4148AZS-S595,
; CY8C4148AZE-S595, CY8C4148AZA-S598, CY8C4148AZS-S598, CY8C4149AZA-S545,
; CY8C4149AZS-S545, CY8C4149AZE-S545, CY8C4149AZA-S548, CY8C4149AZS-S548,
; CY8C4149AZE-S548, CY8C4149AZA-S555, CY8C4149AZS-S555, CY8C4149AZE-S555,
; CY8C4149AZA-S558, CY8C4149AZS-S558, CY8C4149AZE-S558, CY8C4149AZA-S565,
; CY8C4149AZS-S565, CY8C4149AZE-S565, CY8C4149AZA-S568, CY8C4149AZS-S568,
; CY8C4149AZE-S568, CY8C4149AZA-S575, CY8C4149AZS-S575, CY8C4149AZE-S575,
; CY8C4149AZA-S578, CY8C4149AZS-S578, CY8C4149AZE-S578, CY8C4149AZA-S585,
; CY8C4149AZS-S585, CY8C4149AZE-S585, CY8C4149AZA-S588, CY8C4149AZS-S588,
; CY8C4149AZE-S588, CY8C4149AZA-S595, CY8C4149AZS-S595, CY8C4149AZE-S595,
; CY8C4149AZA-S598, CY8C4149AZS-S598, CY8C4149AZE-S598, CY8C4147LDA-S543,
; CY8C4147LDE-S543, CY8C4147LDS-S543, CY8C4147LDA-S553, CY8C4147LDS-S553,
; CY8C4147LDE-S553, CY8C4147LDA-S563, CY8C4147LDS-S563, CY8C4147LDE-S563,
; CY8C4147LDA-S573, CY8C4147LDS-S573, CY8C4147LDE-S573, CY8C4147LDA-S583,
; CY8C4147LDS-S583, CY8C4147LDE-S583, CY8C4147LDA-S593, CY8C4147LDS-S593,
; CY8C4147LDE-S593, CY8C4148LDA-S543, CY8C4148LDS-S543, CY8C4148LDE-S543,
; CY8C4148LDA-S553, CY8C4148LDS-S553, CY8C4148LDE-S553, CY8C4148LDA-S563,
; CY8C4148LDS-S563, CY8C4148LDE-S563, CY8C4148LDA-S573, CY8C4148LDS-S573,
; CY8C4148LDA-S583, CY8C4148LDS-S583, CY8C4148LDE-S583, CY8C4148LDA-S593,
; CY8C4148LDS-S593, CY8C4149LDA-S543, CY8C4149LDS-S543, CY8C4149LDE-S543,
; CY8C4149LDA-S553, CY8C4149LDS-S553, CY8C4149LDE-S553, CY8C4149LDA-S563,
; CY8C4149LDS-S563, CY8C4149LDE-S563, CY8C4149LDA-S573, CY8C4149LDS-S573,
; CY8C4149LDE-S573, CY8C4149LDA-S583, CY8C4149LDS-S583, CY8C4149LDE-S583,
; CY8C4149LDA-S593, CY8C4149LDS-S593, CY8C4149LDE-S593
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perpsoc4100smax.per 16952 2023-11-08 13:36:10Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
sif (CORENAME()=="CORTEXM0+")
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
endif
tree "CANFD (Control Area Network Controller)"
base ad:0x40400000
tree "CH0"
tree "M_TTCAN"
rgroup.long 0x0++0x7
line.long 0x0 "CREL,Core Release Register"
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
newline
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release"
hexmask.long.byte 0x0 16.--19. 1. "YEAR,Time Stamp Year"
newline
hexmask.long.byte 0x0 8.--15. 1. "MON,Time Stamp Month"
hexmask.long.byte 0x0 0.--7. 1. "DAY,Time Stamp Day"
line.long 0x4 "ENDN,Endian Register"
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
group.long 0xC++0x23
line.long 0x0 "DBTP,Data Bit Timing & Prescaler Register"
bitfld.long 0x0 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data Bit Rate Prescaler"
newline
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
newline
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width"
line.long 0x4 "TEST,Test Register"
rbitfld.long 0x4 7. "RX,Receive Pin" "0: The CAN bus is dominant,1: The CAN bus is recessive"
bitfld.long 0x4 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
newline
bitfld.long 0x4 4. "LBCK,Loop Back Mode" "0: Reset value,1: Loop Back Mode is enabled"
bitfld.long 0x4 3. "CAT,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_asct = '0',?"
newline
bitfld.long 0x4 2. "CAM,ASC is not supported by M_TTCAN" "0: Output pin m_ttcan_ascm = '0',1: Output pin m_ttcan_ascm = '1'"
bitfld.long 0x4 1. "TAT,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_asct controlled by FSE,1: Level at pin m_ttcan_asct = '1'"
newline
bitfld.long 0x4 0. "TAM,ASC is not supported by M_TTCAN" "0: Level at pin m_ttcan_ascm controlled by FSE,1: Level at pin m_ttcan_ascm = '1'"
line.long 0x8 "RWD,RAM Watchdog"
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog Value"
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog Configuration"
line.long 0xC "CCCR,CC Control Register"
bitfld.long 0xC 15. "NISO,Non ISO Operation" "0: CAN FD frame format according to ISO 11898-1:2015,1: CAN FD frame format according to Bosch CAN FD.."
bitfld.long 0xC 14. "TXP,Transmit Pause" "0: Transmit pause disabled,1: Transmit pause enabled"
newline
bitfld.long 0xC 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
bitfld.long 0xC 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
newline
bitfld.long 0xC 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
bitfld.long 0xC 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
newline
bitfld.long 0xC 7. "TEST,Test Mode Enable" "0: Normal operation,1: Test Mode"
bitfld.long 0xC 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
newline
bitfld.long 0xC 5. "MON_,Bus Monitoring Mode" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
bitfld.long 0xC 4. "CSR,Clock Stop Request not supported by M_TTCAN use CTL.STOP_REQ at the group level instead." "0: No clock stop is requested,1: Clock stop requested"
newline
bitfld.long 0xC 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_TTCAN may be set in power down by stopping.."
bitfld.long 0xC 2. "ASM,Restricted Operation Mode" "0: Normal CAN operation,1: Restricted Operation Mode active"
newline
bitfld.long 0xC 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started"
line.long 0x10 "NBTP,Nominal Bit Timing & Prescaler Register"
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width"
hexmask.long.word 0x10 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler"
newline
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
line.long 0x14 "TSCC,Timestamp Counter Configuration"
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp Counter Prescaler (still used for TOCC)"
bitfld.long 0x14 0.--1. "TSS,Timestamp Select should always be set to external timestamp counter" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,?,?"
line.long 0x18 "TSCV,Timestamp Counter Value"
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp Counter not used for M_TTCAN"
line.long 0x1C "TOCC,Timeout Counter Configuration"
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout Period"
bitfld.long 0x1C 1.--2. "TOS,Timeout Select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,?,?"
newline
bitfld.long 0x1C 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled"
line.long 0x20 "TOCV,Timeout Counter Value"
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout Counter"
rgroup.long 0x40++0x7
line.long 0x0 "ECR,Error Counter Register"
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
bitfld.long 0x0 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the error.."
newline
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
line.long 0x4 "PSR,Protocol Status Register"
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
newline
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0: Since this bit was reset by the CPU,1: Message in CAN FD format with FDF flag set has.."
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its BRS flag set"
newline
bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0: Last received CAN FD message did not have its..,1: Last received CAN FD message had its ESI flag set"
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state"
bitfld.long 0x4 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
newline
bitfld.long 0x4 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state,1: The M_CAN is in the Error_Passive state"
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing,1: Idle,?,?"
newline
bitfld.long 0x4 0.--2. "LEC,Last Error Code " "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the M_TTCAN..,4: Bit1Error: During the transmission of a message,5: Bit0Error: During the transmission of a message,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol Status.."
group.long 0x48++0x3
line.long 0x0 "TDCR,Transmitter Delay Compensation Register"
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
group.long 0x50++0xF
line.long 0x0 "IR,Interrupt Register"
bitfld.long 0x0 29. "ARA,N/A" "0,1"
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected"
newline
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected"
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
newline
bitfld.long 0x0 25. "BO_,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
bitfld.long 0x0 24. "EW_,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
newline
bitfld.long 0x0 23. "EP_,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred"
newline
bitfld.long 0x0 21. "BEU,Bit Error Uncorrected" "0: No bit error detected when reading from Message..,1: Bit error detected"
bitfld.long 0x0 20. "BEC,M_TTCAN reports correctable ECC fault to the generic fault structure this bit always reads as 0." "0: No bit error detected when reading from Message..,1: Bit error detected and corrected"
newline
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx.."
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
newline
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
newline
bitfld.long 0x0 15. "TEFL_,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost"
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
newline
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark"
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
newline
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
newline
bitfld.long 0x0 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
bitfld.long 0x0 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
newline
bitfld.long 0x0 7. "RF1L_,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
newline
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark"
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
newline
bitfld.long 0x0 3. "RF0L_,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
newline
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark"
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
line.long 0x4 "IE,Interrupt Enable"
bitfld.long 0x4 29. "ARAE,N/A" "0,1"
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
newline
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Enable" "0,1"
newline
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
newline
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
newline
bitfld.long 0x4 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
bitfld.long 0x4 20. "BECE,Bit Error Corrected Interrupt Enable (not used in M_TTCAN)" "0,1"
newline
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
newline
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
newline
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
newline
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x4 12. "TEFNE,Tx Event FIDO New Entry Interrupt Enable" "0,1"
newline
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
newline
bitfld.long 0x4 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
newline
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
newline
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
line.long 0x8 "ILS,Interrupt Line Select"
bitfld.long 0x8 29. "ARAL,N/A" "0,1"
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
newline
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Line" "0,1"
newline
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
newline
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
newline
bitfld.long 0x8 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
bitfld.long 0x8 20. "BECL,Bit Error Corrected Interrupt Line (not used in M_TTCAN)" "0,1"
newline
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
newline
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
newline
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
newline
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
newline
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
newline
bitfld.long 0x8 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
newline
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
newline
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
newline
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
newline
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
line.long 0xC "ILE,Interrupt Line Enable"
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_ttcan_int1 disabled,1: Interrupt line m_ttcan_int1 enabled"
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_ttcan_int0 disabled,1: Interrupt line m_ttcan_int0 enabled"
group.long 0x80++0xB
line.long 0x0 "GFC,Global Filter Configuration"
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,?,?"
newline
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended IDs"
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
hexmask.long.word 0x4 2.--15. 1. "FLSSA,Filter List Standard Start Address"
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
hexmask.long.word 0x8 2.--15. 1. "FLESA,Filter List Extended Start Address"
group.long 0x90++0x3
line.long 0x0 "XIDAM,Extended ID AND Mask"
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
rgroup.long 0x94++0x3
line.long 0x0 "HPMS,High Priority Message Status"
bitfld.long 0x0 15. "FLST,Filter List" "0: Standard Filter List,1: Extended Filter List"
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
newline
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,?,?"
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
group.long 0x98++0xB
line.long 0x0 "NDAT1,New Data 1"
hexmask.long 0x0 0.--31. 1. "ND,New Data"
line.long 0x4 "NDAT2,New Data 2"
hexmask.long 0x4 0.--31. 1. "ND,New Data"
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
newline
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
hexmask.long.word 0x8 2.--15. 1. "F0SA,Rx FIFO 0 Start Address"
rgroup.long 0xA4++0x3
line.long 0x0 "RXF0S,Rx FIFO 0 Status"
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
newline
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
newline
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
group.long 0xA8++0xB
line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
line.long 0x4 "RXBC,Rx Buffer Configuration"
hexmask.long.word 0x4 2.--15. 1. "RBSA,Rx Buffer Start Address"
line.long 0x8 "RXF1C,Rx FIFO 1 Configuration"
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
newline
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size"
hexmask.long.word 0x8 2.--15. 1. "F1SA,Rx FIFO 1 Start Address"
rgroup.long 0xB4++0x3
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state,1: Debug message A received,?,?"
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
newline
bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index"
newline
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index"
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
group.long 0xB8++0xB
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index"
line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration"
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x8 "TXBC,Tx Buffer Configuration"
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
newline
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
hexmask.long.word 0x8 2.--15. 1. "TBSA,Tx Buffers Start Address"
rgroup.long 0xC4++0x3
line.long 0x0 "TXFQS,Tx FIFO/Queue Status"
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full"
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
newline
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
group.long 0xC8++0x3
line.long 0x0 "TXESC,Tx Buffer Element Size Configuration"
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
rgroup.long 0xCC++0x3
line.long 0x0 "TXBRP,Tx Buffer Request Pending"
hexmask.long 0x0 0.--31. 1. "TRP,Transmission Request Pending"
group.long 0xD0++0x7
line.long 0x0 "TXBAR,Tx Buffer Add Request"
hexmask.long 0x0 0.--31. 1. "AR,Add Request"
line.long 0x4 "TXBCR,Tx Buffer Cancellation Request"
hexmask.long 0x4 0.--31. 1. "CR,Cancellation Request"
rgroup.long 0xD8++0x7
line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred"
hexmask.long 0x0 0.--31. 1. "TO,Transmission Occurred"
line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished"
hexmask.long 0x4 0.--31. 1. "CF,Cancellation Finished"
group.long 0xE0++0x7
line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
hexmask.long 0x0 0.--31. 1. "TIE,Transmission Interrupt Enable"
line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
hexmask.long 0x4 0.--31. 1. "CFIE,Cancellation Finished Interrupt Enable"
group.long 0xF0++0x3
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
newline
hexmask.long.word 0x0 2.--15. 1. "EFSA,Event FIFO Start Address"
rgroup.long 0xF4++0x3
line.long 0x0 "TXEFS,Tx Event FIFO Status"
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost"
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
newline
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
newline
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
group.long 0xF8++0x3
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
group.long 0x100++0x2B
line.long 0x0 "TTTMC,TT Trigger Memory Configuration"
hexmask.long.byte 0x0 16.--22. 1. "TME,Trigger Memory Elements"
hexmask.long.word 0x0 2.--15. 1. "TMSA,Trigger Memory Start Address"
line.long 0x4 "TTRMC,TT Reference Message Configuration"
bitfld.long 0x4 31. "RMPS,Reference Message Payload Select" "0: Message Marker MM,1: bytes 2-8"
bitfld.long 0x4 30. "XTD,Extended Identifier" "0,1"
newline
hexmask.long 0x4 0.--28. 1. "RID,Reference Identifier"
line.long 0x8 "TTOCF,TT Operation Configuration"
bitfld.long 0x8 26. "EVTP,Event Trigger Polarity" "0: Rising edge trigger,1: Falling edge trigger"
bitfld.long 0x8 25. "ECC,Enable Clock Calibration" "0: Automatic clock calibration in TTCAN Level 0,1: Automatic clock calibration in TTCAN Level 0"
newline
bitfld.long 0x8 24. "EGTF,Enable Global Time Filtering" "0: Global time filtering in TTCAN Level 0,1: Global time filtering in TTCAN Level 0"
hexmask.long.byte 0x8 16.--23. 1. "AWL,Application Watchdog Limit"
newline
bitfld.long 0x8 15. "EECS,Enable External Clock Synchronization" "0: External clock synchronization in TTCAN Level 0,1: External clock synchronization in TTCAN Level 0"
hexmask.long.byte 0x8 8.--14. 1. "IRTO,Initial Reference Trigger Offset"
newline
bitfld.long 0x8 5.--7. "LDSDL,LD of Synchronization Deviation Limit" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 4. "TM,Time Master" "0: Time Master function disabled,1: Potential Time Master"
newline
bitfld.long 0x8 3. "GEN,Gap Enable" "0: Strictly time-triggered operation,1: External event-synchronized time-triggered.."
bitfld.long 0x8 0.--1. "OM,Operation Mode" "0: Event-driven CAN communication,1: TTCAN level 1,?,?"
line.long 0xC "TTMLM,TT Matrix Limits"
hexmask.long.word 0xC 16.--27. 1. "ENTT,Expected Number of Tx Triggers"
hexmask.long.byte 0xC 8.--11. 1. "TXEW,Tx Enable Window"
newline
bitfld.long 0xC 6.--7. "CSS,N/A" "0,1,2,3"
hexmask.long.byte 0xC 0.--5. 1. "CCM,N/A"
line.long 0x10 "TURCF,TUR Configuration"
bitfld.long 0x10 31. "ELT,Enable Local Time" "0: Local time is stopped,1: Local time is enabled"
hexmask.long.word 0x10 16.--29. 1. "DC,Denominator Configuration"
newline
hexmask.long.word 0x10 0.--15. 1. "NCL,Numerator Configuration Low"
line.long 0x14 "TTOCN,TT Operation Control"
rbitfld.long 0x14 15. "LCKC,TT Operation Control Register Locked" "0: Write access to TTOCN enabled,1: Write access to TTOCN locked"
bitfld.long 0x14 13. "ESCN,External Synchronization Control" "0: External synchronization disabled,1: External synchronization enabled"
newline
bitfld.long 0x14 12. "NIG,Next is Gap" "0: No action,1: Transmit next reference message with Next_is_Gap.."
bitfld.long 0x14 11. "TMG,Time Mark Gap" "0: Reset by each reference message,1: Next reference message started when Register.."
newline
bitfld.long 0x14 10. "FGP,Finish Gap" "0: No reference message requested,1: Application requested start of reference message"
bitfld.long 0x14 9. "GCS,Gap Control Select" "0: Gap control independent from m_ttcan_evt,1: Gap control by input pin m_ttcan_evt"
newline
bitfld.long 0x14 8. "TTIE,Trigger Time Mark Interrupt Pulse Enable" "0: Trigger Time Mark Interrupt output m_ttcan_tmp..,1: Trigger Time Mark Interrupt output m_ttcan_tmp.."
bitfld.long 0x14 6.--7. "TMC,Register Time Mark Compare" "0: No Register Time Mark Interrupt generated,1: Register Time Mark Interrupt if Time Mark =..,?,?"
newline
bitfld.long 0x14 5. "RTIE,Register Time Mark Interrupt Pulse Enable" "0: Register Time Mark Interrupt output m_ttcan_rtp..,1: Register Time Mark Interrupt output m_ttcan_rtp.."
bitfld.long 0x14 3.--4. "SWS,Stop Watch Source" "0: Stop Watch disabled,1: Actual value of cycle time is copied to TTCPT,?,?"
newline
bitfld.long 0x14 2. "SWP,Stop Watch Polarity" "0: Rising edge trigger,1: Falling edge trigger"
bitfld.long 0x14 1. "ECS,External Clock Synchronization" "0,1"
newline
bitfld.long 0x14 0. "SGT,Set Global time" "0,1"
line.long 0x18 "TTGTP,TT Global Time Preset"
hexmask.long.word 0x18 16.--31. 1. "CTP,Cycle Time Target Phase"
hexmask.long.word 0x18 0.--15. 1. "TP,N/A"
line.long 0x1C "TTTMK,TT Time Mark"
rbitfld.long 0x1C 31. "LCKM,TT Time Mark Register Locked" "0: Write access to TTTMK enabled,1: Write access to TTTMK locked"
hexmask.long.byte 0x1C 16.--22. 1. "TICC,Time Mark Cycle Code"
newline
hexmask.long.word 0x1C 0.--15. 1. "TM_,Time Mark"
line.long 0x20 "TTIR,TT Interrupt Register"
bitfld.long 0x20 18. "CER,Configuration Error" "0: No error found in trigger list,1: Error found in trigger list"
bitfld.long 0x20 17. "AW,Application Watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time"
newline
bitfld.long 0x20 16. "WT,Watch Trigger" "0: cycle time 0xFF00),1: Missing reference message"
bitfld.long 0x20 15. "IWT,Initialization Watch Trigger" "0: No missing reference message during system startup,1: No system startup due to missing reference message"
newline
bitfld.long 0x20 14. "ELC,Error Level Changed" "0: No change in error level,1: Error level changed"
bitfld.long 0x20 13. "SE2,Scheduling Error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred"
newline
bitfld.long 0x20 12. "SE1,Scheduling Error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred"
bitfld.long 0x20 11. "TXO,Tx Count Overflow" "0: Number of Tx Trigger as expected,1: More Tx trigger than expected in one matrix cycle"
newline
bitfld.long 0x20 10. "TXU,Tx Count Underflow" "0: Number of Tx Trigger as expected,1: Less Tx trigger than expected in one matrix cycle"
bitfld.long 0x20 9. "GTE,Global Time Error" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit"
newline
bitfld.long 0x20 8. "GTD,Global Time Discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time"
bitfld.long 0x20 7. "GTW,Global Time Wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred"
newline
bitfld.long 0x20 6. "SWE,Stop Watch Event" "0: No rising/falling edge at stop watch trigger pin..,1: Rising/falling edge at stop watch trigger pin.."
bitfld.long 0x20 5. "TTMI,Trigger Time Mark Event Internal" "0: cycle time TTOCF,1: Time mark reached"
newline
bitfld.long 0x20 4. "RTMI,Register Time Mark Interrupt" "0: Time mark not reached,1: Time mark reached"
bitfld.long 0x20 3. "SOG,Start of Gap" "0: No reference message seen with Next_is_Gap bit set,1: Reference message with Next_is_Gap bit set.."
newline
bitfld.long 0x20 2. "CSM_,Change of Synchronization Mode" "0: No change in master to slave relation or..,1: Master to slave relation or schedule.."
bitfld.long 0x20 1. "SMC,Start of Matrix Cycle" "0: No Matrix Cycle started since bit has been reset,1: Matrix Cycle started"
newline
bitfld.long 0x20 0. "SBC,Start of Basic Cycle" "0: No Basic Cycle started since bit has been reset,1: Basic Cycle started"
line.long 0x24 "TTIE,TT Interrupt Enable"
bitfld.long 0x24 18. "CERE,Configuration Error Interrupt Enable" "0,1"
bitfld.long 0x24 17. "AWE_,Application Watchdog Interrupt Enable" "0,1"
newline
bitfld.long 0x24 16. "WTE,Watch Trigger Interrupt Enable" "0,1"
bitfld.long 0x24 15. "IWTE,Initialization Watch Trigger Interrupt Enable" "0,1"
newline
bitfld.long 0x24 14. "ELCE,Change Error Level Interrupt Enable" "0,1"
bitfld.long 0x24 13. "SE2E,Scheduling Error 2 Interrupt Enable" "0,1"
newline
bitfld.long 0x24 12. "SE1E,Scheduling Error 1 Interrupt Enable" "0,1"
bitfld.long 0x24 11. "TXOE,Tx Count Overflow Interrupt Enable" "0,1"
newline
bitfld.long 0x24 10. "TXUE,Tx Count Underflow Interrupt Enable" "0,1"
bitfld.long 0x24 9. "GTEE,Global Time Error Interrupt Enable" "0,1"
newline
bitfld.long 0x24 8. "GTDE,Global Time Discontinuity Interrupt Enable" "0,1"
bitfld.long 0x24 7. "GTWE,Global Time Wrap Interrupt Enable" "0,1"
newline
bitfld.long 0x24 6. "SWEE,Stop Watch Event Interrupt Enable" "0,1"
bitfld.long 0x24 5. "TTMIE,Trigger Time Mark Event Internal Enable" "0,1"
newline
bitfld.long 0x24 4. "RTMIE,Register Time Mark Interrupt Enable" "0,1"
bitfld.long 0x24 3. "SOGE,Start of Gap Interrupt Enable" "0,1"
newline
bitfld.long 0x24 2. "CSME,Change of Synchronization Mode Interrupt Enable" "0,1"
bitfld.long 0x24 1. "SMCE,Start of Matrix Cycle Interrupt Enable" "0,1"
newline
bitfld.long 0x24 0. "SBCE,Start of Basic Cycle Interrupt Enable" "0,1"
line.long 0x28 "TTILS,TT Interrupt Line Select"
bitfld.long 0x28 18. "CERL,Configuration Error Interrupt Line" "0,1"
bitfld.long 0x28 17. "AWL_,Application Watchdog Interrupt Line" "0,1"
newline
bitfld.long 0x28 16. "WTL,Watch Trigger Interrupt Line" "0,1"
bitfld.long 0x28 15. "IWTL,Initialization Watch Trigger Interrupt Line" "0,1"
newline
bitfld.long 0x28 14. "ELCL,Change Error Level Interrupt Line" "0,1"
bitfld.long 0x28 13. "SE2L,Scheduling Error 2 Interrupt Line" "0,1"
newline
bitfld.long 0x28 12. "SE1L,Scheduling Error 1 Interrupt Line" "0,1"
bitfld.long 0x28 11. "TXOL,Tx Count Overflow Interrupt Line" "0,1"
newline
bitfld.long 0x28 10. "TXUL,Tx Count Underflow Interrupt Line" "0,1"
bitfld.long 0x28 9. "GTEL,Global Time Error Interrupt Line" "0,1"
newline
bitfld.long 0x28 8. "GTDL,Global Time Discontinuity Interrupt Line" "0,1"
bitfld.long 0x28 7. "GTWL,Global Time Wrap Interrupt Line" "0,1"
newline
bitfld.long 0x28 6. "SWEL,Stop Watch Event Interrupt Line" "0,1"
bitfld.long 0x28 5. "TTMIL,Trigger Time Mark Event Internal Line" "0,1"
newline
bitfld.long 0x28 4. "RTMIL,Register Time Mark Interrupt Line" "0,1"
bitfld.long 0x28 3. "SOGL,Start of Gap Interrupt Line" "0,1"
newline
bitfld.long 0x28 2. "CSML,Change of Synchronization Mode Interrupt Line" "0,1"
bitfld.long 0x28 1. "SMCL,Start of Matrix Cycle Interrupt Line" "0,1"
newline
bitfld.long 0x28 0. "SBCL,Start of Basic Cycle Interrupt Line" "0,1"
rgroup.long 0x12C++0x17
line.long 0x0 "TTOST,TT Operation Status"
bitfld.long 0x0 31. "SPL,Schedule Phase Lock" "0: Phase outside range,1: Phase inside range"
bitfld.long 0x0 30. "WECS,Wait for External Clock Synchronization" "0: No external clock synchronization pending,1: Node waits for external clock synchronization to.."
newline
bitfld.long 0x0 29. "AWE,Application Watchdog Event" "0: Application Watchdog served in time,1: Failed to serve Application Watchdog in time"
bitfld.long 0x0 28. "WFE,Wait for Event" "0: No Gap announced,1: Reference message with Next_is_Gap = '1' received"
newline
bitfld.long 0x0 27. "GSI,Gap Started Indicator" "0: No Gap in schedule,1: Gap time after Basic Cycle has started"
bitfld.long 0x0 24.--26. "TMP,Time Master Priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 23. "GFI,Gap Finished Indicator" "0: Reset at the end of each reference message,1: Gap finished by M_TTCAN"
bitfld.long 0x0 22. "WGTD,Wait for Global Time Discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take.."
newline
hexmask.long.byte 0x0 8.--15. 1. "RTO,Reference Trigger Offset"
bitfld.long 0x0 7. "QCS,Quality of Clock Speed" "0: Local clock speed not synchronized to Time..,1: Synchronization Deviation <= SDL"
newline
bitfld.long 0x0 6. "QGTP,Quality of Global Time Phase" "0: Global time not valid,1: Global time in phase with Time Master"
bitfld.long 0x0 4.--5. "SYS,Synchronization State" "0: Out of Synchronization,1: Synchronizing to TTCAN communication,?,?"
newline
bitfld.long 0x0 2.--3. "MS,Master State" "0: Master_Off,1: Operating as Time Slave,?,?"
bitfld.long 0x0 0.--1. "EL,Error Level" "0: Severity 0,1: Severity 1,?,?"
line.long 0x4 "TURNA,TUR Numerator Actual"
hexmask.long.tbyte 0x4 0.--17. 1. "NAV,N/A"
line.long 0x8 "TTLGT,TT Local & Global Time"
hexmask.long.word 0x8 16.--31. 1. "GT,Global Time"
hexmask.long.word 0x8 0.--15. 1. "LT,Local Time"
line.long 0xC "TTCTC,TT Cycle Time & Count"
hexmask.long.byte 0xC 16.--21. 1. "CC,Cycle Count"
hexmask.long.word 0xC 0.--15. 1. "CT,Cycle Time"
line.long 0x10 "TTCPT,TT Capture Time"
hexmask.long.word 0x10 16.--31. 1. "SWV,Stop Watch Value"
hexmask.long.byte 0x10 0.--5. 1. "CCV,Cycle Count Value"
line.long 0x14 "TTCSM,TT Cycle Sync Mark"
hexmask.long.word 0x14 0.--15. 1. "CSM,Cycle Sync Mark"
tree.end
group.long 0x180++0x3
newline
line.long 0x0 "RXFTOP_CTL,Receive FIFO Top control"
bitfld.long 0x0 1. "F1TPE,FIFO 1 Top Pointer Enable." "0,1"
bitfld.long 0x0 0. "F0TPE,FIFO 0 Top Pointer Enable." "0,1"
rgroup.long 0x1A0++0x3
line.long 0x0 "RXFTOP0_STAT,Receive FIFO 0 Top Status"
hexmask.long.word 0x0 0.--15. 1. "F0TA,Current FIFO 0 Top Address."
rgroup.long 0x1A8++0x3
line.long 0x0 "RXFTOP0_DATA,Receive FIFO 0 Top Data"
hexmask.long 0x0 0.--31. 1. "F0TD,When enabled (F0TPE=1) read data from MRAM at location FnTA. This register can have a read side effect if the following conditions are met:"
rgroup.long 0x1B0++0x3
line.long 0x0 "RXFTOP1_STAT,Receive FIFO 1 Top Status"
hexmask.long.word 0x0 0.--15. 1. "F1TA,See F0TA description"
rgroup.long 0x1B8++0x3
line.long 0x0 "RXFTOP1_DATA,Receive FIFO 1 Top Data"
hexmask.long 0x0 0.--31. 1. "F1TD,See F0TD description"
tree.end
group.long 0x1000++0x3
newline
line.long 0x0 "CTL,Global CAN control register"
bitfld.long 0x0 31. "MRAM_OFF,MRAM off" "0: Default MRAM on,1: Switch MRAM off"
hexmask.long.byte 0x0 0.--7. 1. "STOP_REQ,Clock Stop Request for each TTCAN IP ."
rgroup.long 0x1004++0x3
line.long 0x0 "STATUS,Global CAN status register"
hexmask.long.byte 0x0 0.--7. 1. "STOP_ACK,Clock Stop Acknowledge for each TTCAN IP."
rgroup.long 0x1010++0x7
line.long 0x0 "INTR0_CAUSE,Consolidated interrupt0 cause register"
hexmask.long.byte 0x0 0.--7. 1. "INT0,Show pending m_ttcan_int0 of each channel"
line.long 0x4 "INTR1_CAUSE,Consolidated interrupt1 cause register"
hexmask.long.byte 0x4 0.--7. 1. "INT1,Show pending m_ttcan_int1 of each channel"
group.long 0x1020++0x7
line.long 0x0 "TS_CTL,Time Stamp control register"
bitfld.long 0x0 31. "ENABLED,Counter enable bit" "0: Count disabled,1: Count enabled"
hexmask.long.word 0x0 0.--15. 1. "PRESCALE,Time Stamp counter prescale value."
line.long 0x4 "TS_CNT,Time Stamp counter value"
hexmask.long.word 0x4 0.--15. 1. "VALUE,The counter value of the Time Stamp Counter."
group.long 0x1080++0x7
line.long 0x0 "ECC_CTL,ECC control"
bitfld.long 0x0 16. "ECC_EN,Enable ECC for CANFD SRAM" "0,1"
line.long 0x4 "ECC_ERR_INJ,ECC error injection"
hexmask.long.byte 0x4 24.--30. 1. "ERR_PAR,ECC Parity bits to use for ECC error injection at address ERR_ADDR."
bitfld.long 0x4 20. "ERR_EN,Enable error injection (ECC_EN must be 1)." "0,1"
hexmask.long.word 0x4 2.--15. 1. "ERR_ADDR,Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed."
tree.end
tree "CPUSS (CPU Subsystem)"
base ad:0x40100000
group.long 0x0++0x2B
line.long 0x0 "CONFIG,Configuration register"
bitfld.long 0x0 0. "VECT_IN_RAM,0': Vector Table is located at 0x0000:0000 in flash" "0,1"
line.long 0x4 "SYSREQ,SYSCALL control register"
bitfld.long 0x4 31. "SYSCALL_REQ,CPU/DAP writes a '1' to this field to request a SystemCall. The HMASTER_0 field indicates the source of the write access. Setting this field to '1' immediate results in a NMI. The SystemCall NMI interrupt handler sets this field to '0' after.." "0,1"
rbitfld.long 0x4 30. "HMASTER_0,Indicates the source of the write access to the SYSREQ register." "0: the current source of write access is captured,1: the previous value"
rbitfld.long 0x4 29. "ROM_ACCESS_EN,Indicates that executing from Boot ROM is enabled. HW sets this field to '1' on reset or when the SystemCall NMI vector is fetched from Boot ROM. HW sets this field to '0' when the CPU is NOT executing from either Boot or System ROM. This.." "0,1"
newline
bitfld.long 0x4 28. "PRIVILEGED,Indicates whether the system is in privileged ('1') or user mode ('0'). Only CPU SW executing from ROM can set this field to '1' when ROM_ACCESS_EN is '1' (the CPU is executing a SystemCall NMI interrupt handler). Any other write to this field.." "0,1"
bitfld.long 0x4 27. "DIS_RESET_VECT_REL,Disable Reset Vector fetch relocation:" "0,1"
hexmask.long.word 0x4 0.--15. 1. "SYSCALL_COMMAND,Opcode of the system call being requested."
line.long 0x8 "SYSARG,SYSARG control register"
hexmask.long 0x8 0.--31. 1. "SYSCALL_ARG,Argument to System Call specified in SYSREQ. Semantics of argument depends on system call made. Typically a pointer to a parameter block."
line.long 0xC "PROTECTION,Protection control register"
bitfld.long 0xC 31. "PROTECTION_LOCK,Setting this field will block (ignore) any further writes to the PROTECTION_MODE field in this register. Once '1' this field cannot be cleared." "0,1"
bitfld.long 0xC 30. "FLASH_LOCK,Setting this bit will force SPCIF.ADDRESS.AXA to be ignored which prevents SM Flash from being erased or overwritten. It is used to indicate the DEAD protection mode. Writes to this field are ignored when PROTECTION_LOCK is '1'" "0,1"
hexmask.long.byte 0xC 0.--3. 1. "PROTECTION_MODE,Current protection mode; this field is available as a global signal everywhere in the system. Writes to this field are ignored when PROTECTION_LOCK is '1':"
line.long 0x10 "PRIV_ROM,ROM privilege register"
hexmask.long.word 0x10 16.--25. 1. "SROM_PROT_LIMIT,Indicates the limit where the privileged area of System ROM partition starts in increments of 256 Bytes. The limit is wrt. the start of the ROM memory (start of the Boot ROM partition)."
hexmask.long.byte 0x10 0.--7. 1. "BROM_PROT_LIMIT,Indicates the limit where the privileged area of the Boot ROM partition starts in increments of 256 Bytes."
line.long 0x14 "PRIV_RAM,RAM privilege register"
hexmask.long.word 0x14 0.--8. 1. "RAM_PROT_LIMIT,Indicates the limit where the privileged area of SRAM starts in increments of 256 Bytes."
line.long 0x18 "PRIV_FLASH,Flash privilege register"
hexmask.long.word 0x18 0.--11. 1. "FLASH_PROT_LIMIT,Indicates the limit where the privileged area of flash starts in increments of 256 Bytes."
line.long 0x1C "WOUNDING,Wounding register"
bitfld.long 0x1C 24.--26. "RAM1_WOUND,Wounding of RAM 1 (see description of RAM_WOUND)." "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 20.--22. "FLASH_WOUND,Indicates the amount of accessible flash in this part. The value in this field is effectively write-once (it is only possible to set bits not clear them). The remainder portion of flash is not accessible and will return an AHB-Lite bus error." "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 16.--18. "RAM_WOUND,Indicates the amount of accessible RAM 0 memory capacity in this part. The value in this field is effectively write-once (it is only possible to set bits not clear them). The remainder portion of SRAM is not accessible and will return an.." "0,1,2,3,4,5,6,7"
line.long 0x20 "INT_SEL,Interrupt multiplexer select register"
hexmask.long 0x20 0.--31. 1. "DSI,Specifies interrupt source:"
line.long 0x24 "INT_MODE,DSI interrupt pulse mode register"
hexmask.long 0x24 0.--31. 1. "DSI_INT_PULSE,Specifies DSI interrupt format:"
line.long 0x28 "NMI_MODE,DSI NMI pulse mode register"
bitfld.long 0x28 0. "DSI_NMI_PULSE,Specifies DSI NMI format:" "0,1"
group.long 0x30++0xF
line.long 0x0 "FLASH_CTL,FLASH control register"
bitfld.long 0x0 16.--17. "ARB,Arbitration policy:" "0,1,2,3"
bitfld.long 0x0 8. "FLASH_INVALIDATE,1': Invalidates the content of the flash controller's buffers." "0,1"
bitfld.long 0x0 4. "PREF_EN,Prefetch enable:" "0,1"
newline
bitfld.long 0x0 0.--1. "FLASH_WS,Amount of ROM wait states:" "0,1,2,3"
line.long 0x4 "ROM_CTL,ROM control register"
bitfld.long 0x4 16.--17. "ARB,Arbitration policy:" "0,1,2,3"
bitfld.long 0x4 0. "ROM_WS,Amount of ROM wait states:" "0,1"
line.long 0x8 "RAM_CTL,RAM control register"
bitfld.long 0x8 16.--17. "ARB,Arbitration policy:" "0,1,2,3"
line.long 0xC "DMAC_CTL,DMA controller register"
bitfld.long 0xC 16.--17. "ARB,Arbitration policy:" "0,1,2,3"
group.long 0xA0++0x7
line.long 0x0 "PRIV_RAM1,RAM 1 privilege register"
hexmask.long.word 0x0 0.--8. 1. "RAM_PROT_LIMIT,See description of PRIV_RAM.RAM_PROT_LIMIT. Note that the reset value is 0x1ff indicating that the complete RAM 1 memory capacity is User accessible."
line.long 0x4 "RAM1_CTL,RAM 1 control register"
bitfld.long 0x4 16.--17. "ARB,Arbitration policy (for RAM controller 1):" "0,1,2,3"
group.long 0xB0++0x3
line.long 0x0 "MTB_CTL,MTB control register"
bitfld.long 0x0 0. "CPU_HALT_TSTOP_EN,1': Enable CPU Halt to stop MTB trace. ('HALTED' output of CM0+ can stop the trace when high/'1')" "0,1"
repeat 24. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x100)++0x3
line.long 0x0 "SL_CTL[$1],Slave control register"
bitfld.long 0x0 16.--17. "ARB,Arbitration policy:" "0,1,2,3"
repeat.end
tree.end
tree "CTBM (Continuous Time Block Mini)"
base ad:0x40300000
group.long 0x0++0xB
line.long 0x0 "CTB_CTRL,global CTB and power control"
bitfld.long 0x0 31. "ENABLED,- 0: CTB IP disabled (put analog in power down open all switches)" "0: CTB IP disabled,1: CTB IP enabled"
newline
bitfld.long 0x0 30. "DEEPSLEEP_ON,- 0: CTB IP disabled off during DeepSleep power mode" "0: CTB IP disabled off during DeepSleep power mode,1: CTB IP remains enabled during DeepSleep power.."
line.long 0x4 "OA_RES0_CTRL,Opamp0 and resistor0 control"
bitfld.long 0x4 11. "OA0_PUMP_EN,Opamp0 pump enable" "0,1"
newline
bitfld.long 0x4 8.--9. "OA0_COMPINT,Opamp0 comparator edge detect for interrupt and pulse mode of DSI (trigger)" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
newline
bitfld.long 0x4 7. "OA0_DSI_LEVEL,Opamp0 comparator DSI (trigger) out level :" "0: pulse,1: level"
newline
bitfld.long 0x4 6. "OA0_BYPASS_DSI_SYNC,Opamp0 bypass comparator output synchronization for DSI (trigger) output: 0=synchronize (level or pulse) 1=bypass (output async)" "0: synchronize,1: bypass"
newline
bitfld.long 0x4 5. "OA0_HYST_EN,Opamp0 hysteresis enable (10mV)" "0,1"
newline
bitfld.long 0x4 4. "OA0_COMP_EN,Opamp0 comparator enable" "0,1"
newline
bitfld.long 0x4 2. "OA0_DRIVE_STR_SEL,Opamp0 output strenght select 0=1x 1=10x" "0,1"
newline
bitfld.long 0x4 0.--1. "OA0_PWR_MODE,Opamp0 power level" "0: Off,1: Low compensation setting (smallest cap highest..,2: Medium compensation setting. For gain=4:..,3: Highest compensation (largest cap lowest GBW)."
line.long 0x8 "OA_RES1_CTRL,Opamp1 and resistor1 control"
bitfld.long 0x8 11. "OA1_PUMP_EN,Opamp1 pump enable" "0,1"
newline
bitfld.long 0x8 8.--9. "OA1_COMPINT,Opamp1 comparator edge detect for interrupt and pulse mode of DSI (trigger)" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
newline
bitfld.long 0x8 7. "OA1_DSI_LEVEL,Opamp1 comparator DSI (trigger) out level :" "0: pulse,1: level"
newline
bitfld.long 0x8 6. "OA1_BYPASS_DSI_SYNC,Opamp1 bypass comparator output synchronization for DSI output: 0=synchronize 1=bypass" "0: synchronize,1: bypass"
newline
bitfld.long 0x8 5. "OA1_HYST_EN,Opamp1 hysteresis enable (10mV)" "0,1"
newline
bitfld.long 0x8 4. "OA1_COMP_EN,Opamp1 comparator enable" "0,1"
newline
bitfld.long 0x8 2. "OA1_DRIVE_STR_SEL,Opamp1 output strenght select 0=1x 1=10x" "0,1"
newline
bitfld.long 0x8 0.--1. "OA1_PWR_MODE,Opamp1 power level: see description of OA0_PWR_MODE" "0,1,2,3"
rgroup.long 0xC++0x3
line.long 0x0 "COMP_STAT,Comparator status"
bitfld.long 0x0 16. "OA1_COMP,Opamp1 current comparator status" "0,1"
newline
bitfld.long 0x0 0. "OA0_COMP,Opamp0 current comparator status" "0,1"
group.long 0x20++0xB
line.long 0x0 "INTR,Interrupt request register"
bitfld.long 0x0 1. "COMP1,Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers. Write with '1' to clear bit." "0,1"
newline
bitfld.long 0x0 0. "COMP0,Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit." "0,1"
line.long 0x4 "INTR_SET,Interrupt request set register"
bitfld.long 0x4 1. "COMP1_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "COMP0_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_MASK,Interrupt request mask"
bitfld.long 0x8 1. "COMP1_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "COMP0_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0x2C++0x3
line.long 0x0 "INTR_MASKED,Interrupt request masked"
bitfld.long 0x0 1. "COMP1_MASKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "COMP0_MASKED,Logical and of corresponding request and mask bits." "0,1"
group.long 0x30++0x3
line.long 0x0 "DFT_CTRL,Was 'Analog DfT controls'. now used as Risk Mitigation bits (RMP)"
bitfld.long 0x0 31. "DFT_EN,this bit is combined with the 3 bits 2:0 to form RMP[3:0]" "0,1"
newline
bitfld.long 0x0 0.--2. "DFT_MODE,this bit is combined with bit 31 to form RMP[3:0] it must always be written with '3' for correct operation." "0,1,2,3,4,5,6,7"
group.long 0x80++0xF
line.long 0x0 "OA0_SW,Opamp0 switch control"
bitfld.long 0x0 21. "OA0O_D81,Opamp0 output switch to short 1x with 10x drive" "0,1"
newline
bitfld.long 0x0 18. "OA0O_D51,Opamp0 output sarbus0 (ctbbus2 in CTB)" "0,1"
newline
bitfld.long 0x0 14. "OA0M_A81,Opamp0 negative terminal Opamp0 output" "0,1"
newline
bitfld.long 0x0 8. "OA0M_A11,Opamp0 negative terminal P1" "0,1"
newline
bitfld.long 0x0 3. "OA0P_A30,Opamp0 positive terminal ctbbus0" "0,1"
newline
bitfld.long 0x0 2. "OA0P_A20,Opamp0 positive terminal P0" "0,1"
newline
bitfld.long 0x0 0. "OA0P_A00,Opamp0 positive terminal amuxbusa" "0,1"
line.long 0x4 "OA0_SW_CLEAR,Opamp0 switch control clear"
bitfld.long 0x4 21. "OA0O_D81,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x4 18. "OA0O_D51,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x4 14. "OA0M_A81,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x4 8. "OA0M_A11,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x4 3. "OA0P_A30,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x4 2. "OA0P_A20,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x4 0. "OA0P_A00,see corresponding bit in OA0_SW" "0,1"
line.long 0x8 "OA1_SW,Opamp1 switch control"
bitfld.long 0x8 21. "OA1O_D82,Opamp1 output switch to short 1x with 10x drive" "0,1"
newline
bitfld.long 0x8 19. "OA1O_D62,Opamp1 output sarbus1 (ctbbus3 in CTB)" "0,1"
newline
bitfld.long 0x8 18. "OA1O_D52,Opamp1 output sarbus0 (ctbbus2 in CTB)" "0,1"
newline
bitfld.long 0x8 14. "OA1M_A82,Opamp1 negative terminal Opamp1 output" "0,1"
newline
bitfld.long 0x8 8. "OA1M_A22,Opamp1 negative terminal P4" "0,1"
newline
bitfld.long 0x8 4. "OA1P_A43,Opamp1 positive terminal ctbbus1" "0,1"
newline
bitfld.long 0x8 1. "OA1P_A13,Opamp1 positive terminal P5" "0,1"
newline
bitfld.long 0x8 0. "OA1P_A03,Opamp1 positive terminal amuxbusb" "0,1"
line.long 0xC "OA1_SW_CLEAR,Opamp1 switch control clear"
bitfld.long 0xC 21. "OA1O_D82,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0xC 19. "OA1O_D62,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0xC 18. "OA1O_D52,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0xC 14. "OA1M_A82,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0xC 8. "OA1M_A22,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0xC 4. "OA1P_A43,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0xC 1. "OA1P_A13,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0xC 0. "OA1P_A03,see corresponding bit in OA1_SW" "0,1"
group.long 0xC0++0x3
line.long 0x0 "CTB_SW_HW_CTRL,CTB bus switch control"
bitfld.long 0x0 3. "P3_HW_CTRL,for P33 D52 D62 (dsi_out[3])" "0,1"
newline
bitfld.long 0x0 2. "P2_HW_CTRL,for P22 D51 (dsi_out[2])" "0,1"
rgroup.long 0xC4++0x3
line.long 0x0 "CTB_SW_STATUS,CTB bus switch control status"
bitfld.long 0x0 30. "OA1O_D62_STAT,see OA1O_D62 bit in OA1_SW" "0,1"
newline
bitfld.long 0x0 29. "OA1O_D52_STAT,see OA1O_D52 bit in OA1_SW" "0,1"
newline
bitfld.long 0x0 28. "OA0O_D51_STAT,see OA0O_D51 bit in OA0_SW" "0,1"
group.long 0xF00++0x17
line.long 0x0 "OA0_OFFSET_TRIM,Opamp0 trim control"
hexmask.long.byte 0x0 0.--5. 1. "OA0_OFFSET_TRIM,Opamp0 offset trim"
line.long 0x4 "OA0_SLOPE_OFFSET_TRIM,Opamp0 trim control"
hexmask.long.byte 0x4 0.--5. 1. "OA0_SLOPE_OFFSET_TRIM,Opamp0 slope offset drift trim"
line.long 0x8 "OA0_COMP_TRIM,Opamp0 trim control"
bitfld.long 0x8 0.--1. "OA0_COMP_TRIM,Opamp 0 Compensation Capacitor Trim" "0,1,2,3"
line.long 0xC "OA1_OFFSET_TRIM,Opamp1 trim control"
hexmask.long.byte 0xC 0.--5. 1. "OA1_OFFSET_TRIM,Opamp1 offset trim"
line.long 0x10 "OA1_SLOPE_OFFSET_TRIM,Opamp1 trim control"
hexmask.long.byte 0x10 0.--5. 1. "OA1_SLOPE_OFFSET_TRIM,Opamp1 slope offset drift trim"
line.long 0x14 "OA1_COMP_TRIM,Opamp1 trim control"
bitfld.long 0x14 0.--1. "OA1_COMP_TRIM,Opamp 1 Compensation Capacitor Trim" "0,1,2,3"
tree.end
tree "DMAC (Direct Memory Access)"
base ad:0x40101000
group.long 0x0++0x3
line.long 0x0 "CTL,Control register"
bitfld.long 0x0 31. "ENABLED,0': IP is disabled. Non-retainable MMIO registers and logic functionality are reset (retainable MMIO registers are NOT reset):" "0,1"
rgroup.long 0x10++0xF
line.long 0x0 "STATUS,Status register"
bitfld.long 0x0 31. "ACTIVE,Specifies if there is a currently active (pending) channel in the data transfer engine:" "0,1"
bitfld.long 0x0 30. "PING_PONG,Specifies the descriptor of the channel is currently in use." "0,1"
bitfld.long 0x0 28.--29. "PRIO,Specifies the priority of the currently active channel." "0,1,2,3"
bitfld.long 0x0 24.--26. "STATE,State of the data transfer engine." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 16.--20. 1. "CH_ADDR,Specifies the channel number of the currently active channel. E.g. if we have 32 channels the channel number address with CH_ADDR_WIDTH is LOG2 (32) = 5 and this field is a 5-bit field. If channel 7 is active STATUS.ACTIVE is '1' and.."
hexmask.long.word 0x0 0.--15. 1. "DATA_NR,Specifies the index of the currently active data transfer. This value increases from '0' to CONTROL.DATA_NR."
line.long 0x4 "STATUS_SRC_ADDR,Source address status register"
hexmask.long 0x4 0.--31. 1. "ADDR,Base address or current address of source location of currently active channel. The specific address information is cycle dependent. This field is provided for debug purposes. Functionally no assumption should be made on whether the base or current.."
line.long 0x8 "STATUS_DST_ADDR,Destination address register"
hexmask.long 0x8 0.--31. 1. "ADDR,Base address or current address of destination location of currently active channel. The specific address information is cycle dependent. This field is provided for debug purposes. Functionally no assumption should be made on whether the base or.."
line.long 0xC "STATUS_CH_ACT,Channel activation status register"
hexmask.long 0xC 0.--31. 1. "CH,Channel activation status. Bit i is associated to channel i with i = 0 ... CH_NR-1."
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x80)++0x3
line.long 0x0 "CH_CTL[$1],Channel control register"
bitfld.long 0x0 31. "ENABLED,'0': channel disabled. The channel's trigger is ignored and the channel cannot be activated. If the activated channel is disabled the data transfer(s) are aborted." "0,1"
bitfld.long 0x0 30. "PING_PONG,Each channel has two descriptor structures for double buffering purposes. As the controller operates on one structure the main CPU can operate on the other structure. The descriptor structures are identified as PING ('0') and PONG ('1'). This.." "0,1"
bitfld.long 0x0 28.--29. "PRIO,Channel priority with '0' representing the highest priority and '3' representing the lowest priority. Priority decoding uses the channel priority to determine the highest priority activated channel. If multiple activated channels have the same.." "0,1,2,3"
repeat.end
group.long 0x7F0++0xB
line.long 0x0 "INTR,Interrupt register"
hexmask.long 0x0 0.--31. 1. "CH,Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit."
line.long 0x4 "INTR_SET,Interrupt set register"
hexmask.long 0x4 0.--31. 1. "CH,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)."
line.long 0x8 "INTR_MASK,Interrupt mask register"
hexmask.long 0x8 0.--31. 1. "CH,Mask for corresponding field in INTR register."
rgroup.long 0x7FC++0x3
line.long 0x0 "INTR_MASKED,Interrupt masked register"
hexmask.long 0x0 0.--31. 1. "CH,Logical BITWISE AND of corresponding request and mask fields."
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40101800 ad:0x40101820 ad:0x40101840 ad:0x40101860 ad:0x40101880 ad:0x401018A0 ad:0x401018C0 ad:0x401018E0 ad:0x40101900 ad:0x40101920 ad:0x40101940 ad:0x40101960 ad:0x40101980 ad:0x401019A0 ad:0x401019C0 ad:0x401019E0)
tree "DESCR[$1]"
base $2
group.long ($2)++0x1F
line.long 0x0 "PING_SRC,Ping source address"
hexmask.long 0x0 0.--31. 1. "ADDR,Base address of source location. The effective source location is calculated by adding on offset (derived from PING.STATUS.CURR_DATA_NR) to this base address."
line.long 0x4 "PING_DST,Ping destination address"
hexmask.long 0x4 0.--31. 1. "ADDR,Base address of destination location. The effective destination location is calculated by adding on offset (derived from PING.STATUS.CURR_DATA_NR) to this base address."
line.long 0x8 "PING_CTL,Ping control word"
bitfld.long 0x8 30.--31. "OPCODE,Specifies the specific data transfer (only when the VALID bit of the descriptor's STATUS word is '1'):" "0,1,2,3"
bitfld.long 0x8 29. "FLIPPING,'1': On completion of the current descriptor structure the current descriptor identifier CH_CTLi.PING_PONG is flipped/inverted. In DMA mode descriptor list transfer flipping of the current descriptor identifier can be used to construct a.." "0,1"
bitfld.long 0x8 28. "PREEMPTABLE,'1': Transfer is preemptable. In DMA mode (OPCODE is '1' or '2') multi data element transfers are constructed out of multiple single data element load (from the source location) and store (to the destination location) sequences. This field.." "0,1"
bitfld.long 0x8 27. "SET_CAUSE,'1': On completion of the current descriptor structure the interrupt cause field of the channel is set to '1' (INTR.CH[i])." "0,1"
bitfld.long 0x8 26. "INV_DESCR,'1': On completion of the current descriptor structure the VALID bit of the descriptor's STATUS word is set to '0'." "0,1"
bitfld.long 0x8 24.--25. "WAIT_FOR_DEACT,Specifies whether the data transfer engine should wait for the channel to be deactivated; i.e. the selected system trigger is not active. This field is used to synchronize the controller's data transfer(s) with the agent that generated the.." "0,1,2,3"
newline
bitfld.long 0x8 23. "SRC_ADDR_INCR,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not." "0,1"
bitfld.long 0x8 22. "SRC_TRANSFER_SIZE,Specifies the bus transfer size to the source location:" "0,1"
bitfld.long 0x8 21. "DST_ADDR_INCR,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not." "0,1"
bitfld.long 0x8 20. "DST_TRANSFER_SIZE,Specifies the bus transfer size to the destination location:" "0,1"
bitfld.long 0x8 16.--17. "DATA_SIZE,Specifies the data element size:" "0,1,2,3"
hexmask.long.word 0x8 0.--15. 1. "DATA_NR,Number of data elements that are transferred by a single descriptor."
line.long 0xC "PING_STATUS,Ping status word"
bitfld.long 0xC 31. "VALID,'0': Invalid cannot be used for a data transfer. An attempt to use this descriptor for a data transfer will result in an INVALID_DESCR response code (and the interrupt cause bit is set to '1')." "0,1"
bitfld.long 0xC 16.--18. "RESPONSE,Response code (the first two codes NO_ERROR and DONE are the result of normal behavior the other codes are the result of erroneous behavior)." "0,1,2,3,4,5,6,7"
hexmask.long.word 0xC 0.--15. 1. "CURR_DATA_NR,Specifies the index of the current data transfer. This value increases from 0 to CONTROL.DATA_NR. HW sets this field:"
line.long 0x10 "PONG_SRC,Pong source address"
hexmask.long 0x10 0.--31. 1. "ADDR,See description of PING_SRC."
line.long 0x14 "PONG_DST,Pong destination address"
hexmask.long 0x14 0.--31. 1. "ADDR,See description of PING_DST."
line.long 0x18 "PONG_CTL,Pong control word"
bitfld.long 0x18 30.--31. "OPCODE,See description of PING_CTL." "0,1,2,3"
bitfld.long 0x18 29. "FLIPPING,See description of PING_CTL." "0,1"
bitfld.long 0x18 28. "PREEMPTABLE,See description of PING_CTL." "0,1"
bitfld.long 0x18 27. "SET_CAUSE,See description of PING_CTL." "0,1"
bitfld.long 0x18 26. "INV_DESCR,See description of PING_CTL." "0,1"
bitfld.long 0x18 24.--25. "WAIT_FOR_DEACT,See description of PING_CTL." "0,1,2,3"
newline
bitfld.long 0x18 23. "SRC_ADDR_INCR,See description of PING_CTL." "0,1"
bitfld.long 0x18 22. "SRC_TRANSFER_SIZE,See description of PING_CTL." "0,1"
bitfld.long 0x18 21. "DST_ADDR_INCR,See description of PING_CTL." "0,1"
bitfld.long 0x18 20. "DST_TRANSFER_SIZE,See description of PING_CTL." "0,1"
bitfld.long 0x18 16.--17. "DATA_SIZE,See description of PING_CTL." "0,1,2,3"
hexmask.long.word 0x18 0.--15. 1. "DATA_NR,See description of PING_CTL."
line.long 0x1C "PONG_STATUS,Pong status word"
bitfld.long 0x1C 31. "VALID,See description of PING_STATUS." "0,1"
bitfld.long 0x1C 16.--18. "RESPONSE,See description of PING_STATUS." "0,1,2,3,4,5,6,7"
hexmask.long.word 0x1C 0.--15. 1. "CURR_DATA_NR,See description of PING_STATUS."
tree.end
repeat.end
tree.end
tree "EXCO (External Clock)"
base ad:0x402F0000
group.long 0x0++0x3
line.long 0x0 "CLK_SELECT,Clock Select Register"
bitfld.long 0x0 1.--2. "REF_SEL,Select source for PLL reference" "0: from ECO,1: from external reference,2: from clk_imo,3: from clk_imo"
newline
bitfld.long 0x0 0. "CLK_SELECT,When PLL_CONFIG.ENABLE=0 then clk_eco=clk_osc." "0: clk_eco=clk_osc,1: PLL_CONFIG"
group.long 0x8++0x3
line.long 0x0 "ECO_CONFIG,ECO Configuration Register"
bitfld.long 0x0 31. "ENABLE,Master enable for ECO oscillator. Refer to CLK_EN for sequencing." "0,1"
newline
bitfld.long 0x0 1. "AGC_EN,Automatic Gain Control (AGC) enable. When set the oscillation amplitude is controlled to the level selected by ECO_TRIM0.ATRIM. When low the amplitude is not explicitly controlled and will grow until it saturates to the supply rail (1.8V nom)." "0,1"
newline
bitfld.long 0x0 0. "CLK_EN,Clock Enable. When enabling the clock first write ENABLE=1 wait at least 10us and then write CLK_EN=1. When disabling clearing both CLK_EN=0 and ENABLE=0 can be done in the same AHB write" "0,1"
rgroup.long 0xC++0x3
line.long 0x0 "ECO_STATUS,ECO Status Register"
bitfld.long 0x0 0. "WATCHDOG_ERROR,This bit is set to 1 if the oscillator is stuck. The ECO clock is gated off during a watchdog error condition. Due to internal synchonization the clock is stopped two cycles after an error condition is observed and ungated two cycles.." "0,1"
group.long 0x14++0x3
line.long 0x0 "PLL_CONFIG,PLL Configuration Register"
bitfld.long 0x0 31. "ENABLE,Master enable for PLL power gate. Refer to ISOLATE_N field for required sequencing." "0: Block is powered off,1: Block is powered on"
newline
bitfld.long 0x0 30. "ISOLATE_N,Isolation control of PLL outputs. This also internally resets the PLL. De-assert >= 5us after ENABLE=1. Assertion can happen in same write as ENABLE=0. Do not change while PLL output is selected." "0: Isolate outputs; Precharge PLL control voltage..,1: Do not isolate outputs"
newline
bitfld.long 0x0 20.--21. "BYPASS_SEL,Selects the source of the system PLL0 clock. See also CLK_SELECT.CLK_SELECT for effect on clk_eco selection." "0: Automatic using lock indicator. When unlocked..,1: Same as AUTO,2: Select PLL reference input (bypass mode).,3: Select PLL output. Ignores lock indicator."
newline
bitfld.long 0x0 16.--18. "ICP_SEL,Programmable charge pump current between 0uA and 7uA. Do not change while the PLL output is selected. For functional operation the value must be set according to the PLL output frequency Fout (measured before the output divider):" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 14.--15. "OUTPUT_DIV,Control bits for Output divider. Do not change while PLL output is selected." "0: Pass Through,1: Divide by 2,2: Divide by 4,3: Divide by 8"
newline
hexmask.long.byte 0x0 8.--13. 1. "REFERENCE_DIV,Control bits for reference divider: Divide by 2=0001 ... divide by 64=111111. Do not change while PLL output is selected."
newline
hexmask.long.byte 0x0 0.--7. 1. "FEEDBACK_DIV,Control bits for feedback divider: Valid divide is 8-255. Do not change while PLL output is selected."
rgroup.long 0x18++0x3
line.long 0x0 "PLL_STATUS,PLL Status Register"
bitfld.long 0x0 0. "LOCKED,PLL Lock Indicator - See CLK_SELECT.CLK_SELECT description for interaction with clk_eco selection." "0,1"
group.long 0x1C++0x7
line.long 0x0 "PLL_TEST,PLL Test Register"
bitfld.long 0x0 4. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware. This is a diagnostic bit used for char and validation." "0,1"
newline
bitfld.long 0x0 3. "FAST_LOCK_EN,Fast Lock Enable - Speeds up the lock time when set to 1. When ISOLATE_N is high the PLL control voltage will be precharged to reduce time spent acquiring frequency lock." "0,1"
newline
bitfld.long 0x0 0.--2. "TEST_MODE,Test Mode" "0: Normal Operation,1: Vcontrol Leakage Test Mode Measure frequency..,2: Charge Pump Down Current Test Mode With ICPSEL>0..,3: Charge Pump Up Current Test Mode With ICPSEL>0..,4: User Mode with Extended Fast Lock Precharge,5: Reference and Feedback Counter Test Mode,6: Lock Detector Delay Line Test Mode,7: Lock Detector Wait and Extended Fast Lock.."
line.long 0x4 "EXCO_PGM_CLK,EXCO Program Clock"
bitfld.long 0x4 31. "ENABLE,Enable bit-banging test capability in this register." "0,1"
newline
bitfld.long 0x4 4. "EN_CLK_PLL0,Bit bang en_clk_pll0" "0,1"
newline
bitfld.long 0x4 3. "CLK_PLL0_OUT,Bit bang clk_pll0_out" "0,1"
newline
rbitfld.long 0x4 2. "CLK_PLL0_IN,Observation point for clk_pll0_in not retained." "0,1"
newline
bitfld.long 0x4 1. "CLK_ECO,Bit bang clk_eco" "0,1"
group.long 0x30++0xB
line.long 0x0 "REF_CTL,Clock Supervision Reference Contol"
bitfld.long 0x0 31. "CSV_EN,Enables clock supervision both frequency and loss." "0,1"
newline
bitfld.long 0x0 18. "CSV_CLK_SW_EN,Enable CSV to cause Clock Switch to IMO when set." "0,1"
newline
bitfld.long 0x0 17. "CSV_TRIG_EN,Enable CSV to cause trigger if a clock switch occurs to IMO." "0,1"
newline
bitfld.long 0x0 16. "CSV_INT_EN,Enable CSV setting INT.CSV_CLK_SW if a clock switch occurs to IMO." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable or DeepSleep wakeup from reference clock start to monitored clock start."
line.long 0x4 "REF_LIMIT,Clock Supervision Reference Limits"
hexmask.long.word 0x4 16.--31. 1. "UPPER,Cycle time upper limit. Set the upper limit -1 in reference clock cycles before (or same time) the next monitored clock event must happen. If a monitored clock event does not happen before this limit is reached or does not happen at all (clock.."
newline
hexmask.long.word 0x4 0.--15. 1. "LOWER,Cycle time lower limit. Set the lower limit -1 in reference clock cycles before the next monitored clock event is allowed to happen. If a monitored clock event happens before this limit is reached a CSV error is detected."
line.long 0x8 "MON_CTL,Clock Supervision Monitor Control"
hexmask.long.word 0x8 0.--15. 1. "PERIOD,Period time. Set the Period -1 in monitored clock cycles before the next monitored clock event happens."
group.long 0x40++0xB
line.long 0x0 "INTR,Interrupt Request Register"
bitfld.long 0x0 2. "CSV_CLK_SW,Clock Supervisor Switched Clock Source to IMO" "0,1"
newline
bitfld.long 0x0 1. "WD_ERR,EXCO Watch Dog Error detected - Oscillator stopped oscillating" "0,1"
newline
bitfld.long 0x0 0. "PLL_LOCK,HW will set this bit when PLL loses lock (PLL 'locked' output goes low)." "0,1"
line.long 0x4 "INTR_SET,Interrupt Set Register"
bitfld.long 0x4 2. "CSV_CLK_SW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "WD_ERR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "PLL_LOCK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_MASK,Interrupt Mask Register"
bitfld.long 0x8 2. "CSV_CLK_SW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "WD_ERR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "PLL_LOCK,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0x4C++0x3
line.long 0x0 "INTR_MASKED,Interrrupt Masked Register"
bitfld.long 0x0 2. "CSV_CLK_SW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "WD_ERR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "PLL_LOCK,Logical and of corresponding request and mask bits." "0,1"
group.long 0x50++0x7
line.long 0x0 "RSTDLY_CTL,Programmable Delay Counter Control"
bitfld.long 0x0 31. "EN,Programmable Delay Counter Enable" "0,1"
newline
bitfld.long 0x0 0. "LOAD,Programmable Delay Counter Load - Reloads the DLYCOUNT into the COUNT_VAL register" "0: No Action,1: Generate a 1 clock pulse that loads the Initial.."
line.long 0x4 "RSTDLY,Programmable Delay Counter Initial Amount"
hexmask.long.word 0x4 0.--15. 1. "DLYCOUNT,Delay Count Value"
rgroup.long 0x58++0x3
line.long 0x0 "RSTDLY_COUNT_VAL,Programmable Delay Counter Value"
hexmask.long.word 0x0 0.--15. 1. "COUNT_VAL,Current Programmable Delay Counter value"
group.long 0xFF00++0xF
line.long 0x0 "ECO_TRIM0,ECO Trim0 Register"
bitfld.long 0x0 2.--4. "ATRIM,Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1. WARNING: use care when setting this field because driving a crystal beyond its rated limit can permanently damage the crystal." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--1. "WDTRIM,Watch Dog Trim - Delta voltage below stead state level" "0,1,2,3"
line.long 0x4 "ECO_TRIM1,ECO Trim1 Register"
bitfld.long 0x4 4.--5. "GTRIM,Gain Trim - Startup time" "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "RTRIM,Feedback resistor Trim" "0,1,2,3"
newline
bitfld.long 0x4 0.--1. "FTRIM,Filter Trim - 3rd harmonic oscillation" "0,1,2,3"
line.long 0x8 "ECO_TRIM2,ECO Trim2 Register"
hexmask.long.byte 0x8 0.--5. 1. "ITRIM,Current Trim"
line.long 0xC "PLL_TRIM,PLL Trim Register"
bitfld.long 0xC 4.--5. "LOCK_DELAY,Selects the number of PLL phase frequency detector cycles that the phase error must be in range before declaring lock. (PFD clock cycle = Clock Reference Period/REFERENCE_DIV)" "0: 16 PFD clock cycles,1: 32 PFD clock cycles,2: 48 PFD clock cycles,3: 64 PFD clock cycles"
newline
bitfld.long 0xC 2.--3. "LOCK_WINDOW,Selects the allowed phase error before declaring the PLL Unlocked" "0: Delay 25 ns,1: Delay 50 ns,2: Delay 75 ns,3: Delay 100 ns"
newline
bitfld.long 0xC 0.--1. "VCO_GAIN,Programmable VCO frequency characteristic at high freq - set to <10>" "0,1,2,3"
tree.end
tree "GPIO (General Purpose IO)"
base ad:0x40040000
repeat 13. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC)(list ad:0x40040000 ad:0x40040100 ad:0x40040200 ad:0x40040300 ad:0x40040400 ad:0x40040500 ad:0x40040600 ad:0x40040700 ad:0x40040800 ad:0x40040900 ad:0x40040A00 ad:0x40040B00 ad:0x40040C00)
tree "PRT[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "DR,Port output data register"
bitfld.long 0x0 7. "DATA7,IO pad 7 output data." "0,1"
newline
bitfld.long 0x0 6. "DATA6,IO pad 6 output data." "0,1"
newline
bitfld.long 0x0 5. "DATA5,IO pad 5 output data." "0,1"
newline
bitfld.long 0x0 4. "DATA4,IO pad 4 output data." "0,1"
newline
bitfld.long 0x0 3. "DATA3,IO pad 3 output data." "0,1"
newline
bitfld.long 0x0 2. "DATA2,IO pad 2 output data." "0,1"
newline
bitfld.long 0x0 1. "DATA1,IO pad 1 output data." "0,1"
newline
bitfld.long 0x0 0. "DATA0,IO pad 0 output data." "0,1"
rgroup.long ($2+0x4)++0x3
line.long 0x0 "PS,Port IO pad state register"
bitfld.long 0x0 8. "FLT_DATA,Reads of this register return the logical state of the filtered pin." "0,1"
newline
bitfld.long 0x0 7. "DATA7,IO pad 7 state." "0,1"
newline
bitfld.long 0x0 6. "DATA6,IO pad 6 state." "0,1"
newline
bitfld.long 0x0 5. "DATA5,IO pad 5 state." "0,1"
newline
bitfld.long 0x0 4. "DATA4,IO pad 4 state." "0,1"
newline
bitfld.long 0x0 3. "DATA3,IO pad 3 state." "0,1"
newline
bitfld.long 0x0 2. "DATA2,IO pad 2 state." "0,1"
newline
bitfld.long 0x0 1. "DATA1,IO pad 1 state." "0,1"
newline
bitfld.long 0x0 0. "DATA0,IO pad 0 state:" "0: Logic low,1: Logic high"
group.long ($2+0x8)++0x13
line.long 0x0 "PC,Port configuration register"
bitfld.long 0x0 30.--31. "PORT_IB_MODE_SEL,This field selects the input buffer reference. The size (1 or 2 bits) and functionality is dependent on the IO cell." "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "PORT_SLEW_CTL,Slew control. Only used in the O_Z drive mode (mode 4: strong pull down open drain): This field is intended for I2C functionality. See BROS 001-70428 for more details." "0: HS mode (100pf < Cb < 400pF 1.71<VDDD<5.5..,1: HS mode (Cb<100pf 1.71<VDDD<5.5 Vext>2.8..,2: HS mode (100pf<Cb<400pf 1.71<VDDD<5.5 Vext<3.3)..,3: HS mode (Cb<100pf 1.71<VDDD<5.5 Vext<=2.8.."
newline
bitfld.long 0x0 27. "PORT_HYST_TRIM,This field is used to improve the hysteresis (to 10 percent of vddio) of the selectable trip point input buffer. The voltage reference comes from the VREFGEN block and is only available when using the VREFGEN block:" "0,1"
newline
bitfld.long 0x0 25. "PORT_SLOW,This field controls the output edge rate of all pins on the port:" "0,1"
newline
bitfld.long 0x0 24. "PORT_VTRIP_SEL,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage. Note: this bit is ignored for SIO ports the VTRIP_SEL settings in the SIO register are used instead (a separate VTRIP_SEL is provided for each pin pair)." "0: input buffer functions as a CMOS input buffer,1: input buffer functions as a LVTTL input buffer"
newline
bitfld.long 0x0 21.--23. "DM7,The GPIO drive mode for IO pad 7." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DM6,The GPIO drive mode for IO pad 6." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15.--17. "DM5,The GPIO drive mode for IO pad 5." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12.--14. "DM4,The GPIO drive mode for IO pad 4." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 9.--11. "DM3,The GPIO drive mode for IO pad 3." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--8. "DM2,The GPIO drive mode for IO pad 2." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3.--5. "DM1,The GPIO drive mode for IO pad 1." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "DM0,The GPIO drive mode for IO pad 0." "0: Mode 0 (analog mode): Output buffer off (high..,1: Mode 1: Output buffer off (high Z). Input buffer..,2: Mode 2: Strong pull down ('0') weak/resistive..,3: Mode 3: Weak/resistive pull down (PD) strong..,4: Mode 4: Strong pull down ('0') open drain (pull..,5: Mode 5: Open drain (pull down off) strong pull..,6: Mode 6: Strong pull down ('0') strong pull up..,7: Mode 7: Weak/resistive pull down (PD).."
line.long 0x4 "INTR_CFG,Port interrupt configuration register"
bitfld.long 0x4 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 16.--17. "FLT_EDGE_SEL,Same for the glitch filtered pin (selected by FLT_SEL)." "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
newline
bitfld.long 0x4 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pad 7." "0,1,2,3"
newline
bitfld.long 0x4 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pad 6." "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pad 5." "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pad 4." "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pad 3." "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pad 2." "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pad 1." "0,1,2,3"
newline
bitfld.long 0x4 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pad 0." "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
line.long 0x8 "INTR,Port interrupt status register"
rbitfld.long 0x8 24. "PS_FLT_DATA,This is a duplicate of the contents of the PS register provided here to allow reading of both pin state and interrupt state of the port in a single read operation." "0,1"
newline
rbitfld.long 0x8 23. "PS_DATA7,N/A" "0,1"
newline
rbitfld.long 0x8 22. "PS_DATA6,N/A" "0,1"
newline
rbitfld.long 0x8 21. "PS_DATA5,N/A" "0,1"
newline
rbitfld.long 0x8 20. "PS_DATA4,N/A" "0,1"
newline
rbitfld.long 0x8 19. "PS_DATA3,N/A" "0,1"
newline
rbitfld.long 0x8 18. "PS_DATA2,N/A" "0,1"
newline
rbitfld.long 0x8 17. "PS_DATA1,N/A" "0,1"
newline
rbitfld.long 0x8 16. "PS_DATA0,`" "0,1"
newline
bitfld.long 0x8 8. "FLT_DATA,Deglitched interrupt pending (selected by FLT_SEL)." "0,1"
newline
bitfld.long 0x8 7. "DATA7,Interrupt pending on IO pad 7. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 6. "DATA6,Interrupt pending on IO pad 6. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 5. "DATA5,Interrupt pending on IO pad 5. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 4. "DATA4,Interrupt pending on IO pad 4. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 3. "DATA3,Interrupt pending on IO pad 3. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 2. "DATA2,Interrupt pending on IO pad 2. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 1. "DATA1,Interrupt pending on IO pad 1. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 0. "DATA0,Interrupt pending on IO pad 0. Firmware writes 1 to clear the interrupt." "0,1"
line.long 0xC "SIO,Port SIO configuration register"
bitfld.long 0xC 29.--31. "PAIR_VOH67_SEL,See corresponding definition for IO pads 0 and 1." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 27.--28. "PAIR_VREF67_SEL,See corresponding definition for IO pads 0 and 1." "0,1,2,3"
newline
bitfld.long 0xC 26. "PAIR_VTRIP67_SEL,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 25. "PAIR_IBUF67_SEL,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 24. "PAIR_VREG67_EN,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 21.--23. "PAIR_VOH45_SEL,See corresponding definition for IO pads 0 and 1." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 19.--20. "PAIR_VREF45_SEL,See corresponding definition for IO pads 0 and 1." "0,1,2,3"
newline
bitfld.long 0xC 18. "PAIR_VTRIP45_SEL,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 17. "PAIR_IBUF45_SEL,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 16. "PAIR_VREG45_EN,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 13.--15. "PAIR_VOH23_SEL,See corresponding definition for IO pads 0 and 1." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 11.--12. "PAIR_VREF23_SEL,See corresponding definition for IO pads 0 and 1." "0,1,2,3"
newline
bitfld.long 0xC 10. "PAIR_VTRIP23_SEL,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 9. "PAIR_IBUF23_SEL,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 8. "PAIR_VREG23_EN,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 5.--7. "PAIR_VOH01_SEL,Selects regulated Voh output level and trip point of input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL)." "0: Voh = 1*reference; e,1: Voh = 1,2: Voh = 1,3: Voh = 1,4: Voh = 2,5: Voh = 2,6: Voh = 2,7: Voh = 4"
newline
bitfld.long 0xC 3.--4. "PAIR_VREF01_SEL,Selects reference voltage Vref for trip-point of input buffer:" "0: trip-point reference of SRSS internal reference..,1: trip-point reference of SRSS internal reference..,2: trip-point reference of AMUXBUS_A,3: trip-point reference of AMUXBUS_B"
newline
bitfld.long 0xC 2. "PAIR_VTRIP01_SEL,Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'):" "0: input buffer functions as a CMOS input buffer,1: input buffer functions as a LVTTL input buffer"
newline
bitfld.long 0xC 1. "PAIR_IBUF01_SEL,Selects input buffer mode:" "0: singled ended input buffer,1: differential input buffer"
newline
bitfld.long 0xC 0. "PAIR_VREG01_EN,Selects output buffer mode:" "0: unregulated output buffer,1: regulated output buffer"
line.long 0x10 "PC2,Port configuration register 2"
bitfld.long 0x10 7. "INP_DIS7,Disables the input buffer for IO pad 7." "0,1"
newline
bitfld.long 0x10 6. "INP_DIS6,Disables the input buffer for IO pad 6." "0,1"
newline
bitfld.long 0x10 5. "INP_DIS5,Disables the input buffer for IO pad 5." "0,1"
newline
bitfld.long 0x10 4. "INP_DIS4,Disables the input buffer for IO pad 4." "0,1"
newline
bitfld.long 0x10 3. "INP_DIS3,Disables the input buffer for IO pad 3." "0,1"
newline
bitfld.long 0x10 2. "INP_DIS2,Disables the input buffer for IO pad 2." "0,1"
newline
bitfld.long 0x10 1. "INP_DIS1,Disables the input buffer for IO pad 1." "0,1"
newline
bitfld.long 0x10 0. "INP_DIS0,Disables the input buffer for IO pad 0 independent of the port control drive mode (PC.DM). This bit should be set when analog signals are present on the pin and PC.DM != 0 is required to use the output driver." "0,1"
group.long ($2+0x40)++0x13
line.long 0x0 "DR_SET,Port output data set register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,IO pad i:"
line.long 0x4 "DR_CLR,Port output data clear register"
hexmask.long.byte 0x4 0.--7. 1. "DATA,IO pad i:"
line.long 0x8 "DR_INV,Port output data invert register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,IO pad i:"
line.long 0xC "DS,Port drive strength register"
bitfld.long 0xC 17. "PORT_V1P2_IB_MODE_SEL,For GPIOV1P2 cell " "0: vtrip_sel register controls the vtrip_sel of the..,1: vddio detect cell output controls the vtrip_sel.."
newline
bitfld.long 0xC 16. "PORT_V1P2_VTRIP_SEL,For GPIOV1P2:" "0: VDDIO 1,1: VDDIO 1"
newline
bitfld.long 0xC 14.--15. "DS7,The GPIO drive strength for IO pad 7." "0,1,2,3"
newline
bitfld.long 0xC 12.--13. "DS6,The GPIO drive strength for IO pad 6." "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "DS5,The GPIO drive strength for IO pad 5." "0,1,2,3"
newline
bitfld.long 0xC 8.--9. "DS4,The GPIO drive strength for IO pad 4." "0,1,2,3"
newline
bitfld.long 0xC 6.--7. "DS3,The GPIO drive strength for IO pad 3." "0,1,2,3"
newline
bitfld.long 0xC 4.--5. "DS2,The GPIO drive strength for IO pad 2." "0,1,2,3"
newline
bitfld.long 0xC 2.--3. "DS1,The GPIO drive strength for IO pad 1." "0,1,2,3"
newline
bitfld.long 0xC 0.--1. "DS0,The GPIO drive strength for IO pad 0." "0: 1 ma drive nominal - changes with external R/C..,1: 2 ma drive nominal - changes with external R/C..,2: 4 ma drive nominal - changes with external R/C..,3: 8 ma drive nominal - changes with external R/C.."
line.long 0x10 "FILT_CONFIG,IO filter config register"
bitfld.long 0x10 23. "FILT7_EN,Filter selection for IO pad 7" "0,1"
newline
bitfld.long 0x10 22. "FILT6_EN,Filter selection for IO pad 6" "0,1"
newline
bitfld.long 0x10 21. "FILT5_EN,Filter selection for IO pad 5" "0,1"
newline
bitfld.long 0x10 20. "FILT4_EN,Filter selection for IO pad 4" "0,1"
newline
bitfld.long 0x10 19. "FILT3_EN,Filter selection for IO pad 3" "0,1"
newline
bitfld.long 0x10 18. "FILT2_EN,Filter selection for IO pad 2" "0,1"
newline
bitfld.long 0x10 17. "FILT1_EN,Filter selection for IO pad 1" "0,1"
newline
bitfld.long 0x10 16. "FILT0_EN,Filter selection for IO pad 0" "0,1"
newline
bitfld.long 0x10 14.--15. "TRIM7,trim bits for 50ns filter on IO pad 7" "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "TRIM6,trim bits for 50ns filter on IO pad 6" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "TRIM5,trim bits for 50ns filter on IO pad 5" "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "TRIM4,trim bits for 50ns filter on IO pad 4" "0,1,2,3"
newline
bitfld.long 0x10 6.--7. "TRIM3,trim bits for 50ns filter on IO pad 3" "0,1,2,3"
newline
bitfld.long 0x10 4.--5. "TRIM2,trim bits for 50ns filter on IO pad 2" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "TRIM1,trim bits for 50ns filter on IO pad 1" "0,1,2,3"
newline
bitfld.long 0x10 0.--1. "TRIM0,trim bits for 50ns filter on IO pad 0" "0,1,2,3"
group.long ($2+0x80)++0x3
line.long 0x0 "VREFGEN,Reference generator configuration register"
bitfld.long 0x0 8. "VREFGEN_EN,Reference generator enable:" "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "REF_SEL,Reference selection. A reference Voltage vinref is created using a Voltage vddio:"
tree.end
repeat.end
base ad:0x40040000
rgroup.long 0x1000++0x3
line.long 0x0 "INTR_CAUSE,Interrupt port cause register"
hexmask.long 0x0 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'interrupts_gpio[i]' for IO port i). The register is used when the system uses a shared/combined interrupt line.."
rgroup.long 0x1020++0x3
line.long 0x0 "GPIOV1P2_DET,GPIOV1P2 Detect output"
bitfld.long 0x0 0. "DET,Indicates HI when VDDIO is in 1.8V range and LOW when VDDIO is in 1.2V range." "0,1"
tree.end
tree "HSIOM (High Speed IO Matrix)"
base ad:0x40020000
repeat 13. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC)(list ad:0x40020000 ad:0x40020100 ad:0x40020200 ad:0x40020300 ad:0x40020400 ad:0x40020500 ad:0x40020600 ad:0x40020700 ad:0x40020800 ad:0x40020900 ad:0x40020A00 ad:0x40020B00 ad:0x40020C00)
tree "PRT[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "PORT_SEL,Port selection register"
hexmask.long.byte 0x0 28.--31. 1. "IO7_SEL,Selects connection for IO pad 7 route."
hexmask.long.byte 0x0 24.--27. 1. "IO6_SEL,Selects connection for IO pad 6 route."
hexmask.long.byte 0x0 20.--23. 1. "IO5_SEL,Selects connection for IO pad 5 route."
hexmask.long.byte 0x0 16.--19. 1. "IO4_SEL,Selects connection for IO pad 4 route."
hexmask.long.byte 0x0 12.--15. 1. "IO3_SEL,Selects connection for IO pad 3 route."
hexmask.long.byte 0x0 8.--11. 1. "IO2_SEL,Selects connection for IO pad 2 route."
hexmask.long.byte 0x0 4.--7. 1. "IO1_SEL,Selects connection for IO pad 1 route."
hexmask.long.byte 0x0 0.--3. 1. "IO0_SEL,Selects connection for IO pad 0 route."
tree.end
repeat.end
base ad:0x40020000
group.long 0x2000++0x3
line.long 0x0 "PUMP_CTL,Pump control"
bitfld.long 0x0 31. "ENABLED,Pump enabled:" "0,1"
bitfld.long 0x0 0. "CLOCK_SEL,Clock select:" "0,1"
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "AMUX_SPLIT_CTL[$1],AMUX splitter cell control"
bitfld.long 0x0 6. "SWITCH_BB_S0,T-switch control for AMUXBUSB vssa/ground switch." "0,1"
bitfld.long 0x0 5. "SWITCH_BB_SR,T-switch control for Right AMUXBUSB switch." "0,1"
bitfld.long 0x0 4. "SWITCH_BB_SL,T-switch control for Left AMUXBUSB switch." "0,1"
bitfld.long 0x0 2. "SWITCH_AA_S0,T-switch control for AMUXBUSA vssa/ground switch:" "0,1"
bitfld.long 0x0 1. "SWITCH_AA_SR,T-switch control for Right AMUXBUSA switch:" "0,1"
bitfld.long 0x0 0. "SWITCH_AA_SL,T-switch control for Left AMUXBUSA switch:" "0,1"
repeat.end
tree.end
tree "I2S (Inter-IC Sound Bus)"
base ad:0x404F0000
group.long 0x0++0x3
line.long 0x0 "CTL,Control"
bitfld.long 0x0 31. "RX_ENABLED,Enables the I2S RX component:" "0,1"
bitfld.long 0x0 30. "TX_ENABLED,Enables the I2S TX component:" "0,1"
group.long 0x10++0x3
line.long 0x0 "CLOCK_CTL,Clock control"
bitfld.long 0x0 8. "CLOCK_SEL,Selects clock to be used by I2S:" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "CLOCK_DIV,Frequency divisor for generating I2S clock frequency."
group.long 0x20++0x3
line.long 0x0 "CMD,Command"
bitfld.long 0x0 16. "RX_START,Receiver enable:" "0,1"
bitfld.long 0x0 8. "TX_PAUSE,Pause enable:" "0,1"
newline
bitfld.long 0x0 0. "TX_START,Transmitter enable:" "0,1"
group.long 0x40++0x3
line.long 0x0 "TR_CTL,Trigger control"
bitfld.long 0x0 16. "RX_REQ_EN,Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception" "0,1"
bitfld.long 0x0 0. "TX_REQ_EN,Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission" "0,1"
group.long 0x80++0x7
line.long 0x0 "TX_CTL,Transmitter control"
bitfld.long 0x0 25. "SCKI_POL,TX slave bit clock polarity." "0,1"
bitfld.long 0x0 24. "SCKO_POL,TX master bit clock polarity." "0,1"
newline
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
newline
bitfld.long 0x0 13. "WD_EN,Set watchdog for 'tx_ws_in':" "0,1"
bitfld.long 0x0 12. "OVHDATA,Set overhead value:" "0,1"
newline
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
newline
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
newline
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data transmission is advanced by 0.5 SCK cycles. This bit is valid only in TX slave mode." "0: Serial data will be transmitted off the SCK..,1: Serial data will be transmitted off the SCK.."
line.long 0x4 "TX_WATCHDOG,Transmitter watchdog"
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the TX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
group.long 0xA0++0x7
line.long 0x0 "RX_CTL,Receiver control"
bitfld.long 0x0 25. "SCKI_POL,RX slave bit clock polarity." "0,1"
bitfld.long 0x0 24. "SCKO_POL,RX master bit clock polarity." "0,1"
newline
bitfld.long 0x0 23. "BIT_EXTENSION,When reception word length is shorter than the word length of RX_FIFO_RD extension mode of upper bit should be set." "0,1"
bitfld.long 0x0 20.--22. "WORD_LEN,Word length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
newline
bitfld.long 0x0 16.--18. "CH_LEN,Channel length in number of bits:" "0: 8-bit,1: 16-bit,2: 18-bit,3: 20-bit,4: 24-bit,5: 32-bit,?,?"
bitfld.long 0x0 13. "WD_EN,Set watchdog for 'rx_ws_in'" "0,1"
newline
bitfld.long 0x0 10. "WS_PULSE,Set WS pulse width in TDM mode:" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
bitfld.long 0x0 8.--9. "I2S_MODE,Select I2S left-justified or TDM:" "0: Left Justified,1: I2S mode,2: TDM mode A the 1st Channel align to WSO Rising..,3: TDM mode B the 1st Channel align to WSO Rising.."
newline
bitfld.long 0x0 7. "MS,Set interface in master or slave mode:" "0: Slave,1: Master"
bitfld.long 0x0 4.--6. "CH_NR,Specifies number of channels per frame:" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
newline
bitfld.long 0x0 3. "B_CLOCK_INV,Serial data capture is delayed by 0.5 SCK cycles. This bit is valid only in RX master mode." "0: Serial data will be captured by the SCK falling..,1: Serial data will be captured by the SCK rising.."
line.long 0x4 "RX_WATCHDOG,Receiver watchdog"
hexmask.long 0x4 0.--31. 1. "WD_COUNTER,Start value of the RX watchdog. With the reset value of 0x0000:0000 the counter is disabled. This is clocked by the AHB-Lite system clock 'clk_sys'."
group.long 0x200++0x3
line.long 0x0 "TX_FIFO_CTL,TX FIFO control"
bitfld.long 0x0 17. "FREEZE,When '1' hardware reads from the TX FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer. This field is used only for debugging purposes." "0,1"
bitfld.long 0x0 16. "CLEAR,When '1' the TX FIFO and TX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the TX FIFO has less entries than the number of this field a transmitter trigger event is generated."
rgroup.long 0x204++0x3
line.long 0x0 "TX_FIFO_STATUS,TX FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,TX FIFO write pointer: FIFO location at which a new data frame is written by the host. This field is used only for debugging purposes."
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes."
newline
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the TX FIFO. The field value is in the range [0 256]."
wgroup.long 0x208++0x3
line.long 0x0 "TX_FIFO_WR,TX FIFO write"
hexmask.long 0x0 0.--31. 1. "DATA,Data written into the TX FIFO. Behavior is similar to that of a PUSH operation."
group.long 0x300++0x3
line.long 0x0 "RX_FIFO_CTL,RX FIFO control"
bitfld.long 0x0 17. "FREEZE,When '1' hardware writes to the RX FIFO have no effect. Freeze will not advance the RX FIFO write pointer. This field is used only for debugging purposee." "0,1"
bitfld.long 0x0 16. "CLEAR,When '1' the RX FIFO and RX_BUF are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If a clear/invalidation is.." "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the RX FIFO has more entries than the number of this field a receiver trigger event is generated."
rgroup.long 0x304++0xB
line.long 0x0 "RX_FIFO_STATUS,RX FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware. This field is used only for debugging purposes."
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,RX FIFO read pointer: FIFO location from which a data frame is read by the host. This field is used only for debugging purposes."
newline
hexmask.long.word 0x0 0.--8. 1. "USED,Number of entries in the RX FIFO. The field value is in the range [0 256]."
line.long 0x4 "RX_FIFO_RD,RX FIFO read"
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will remove the data frame from the RX FIFO; i.e. behavior is similar to that of a POP operation."
line.long 0x8 "RX_FIFO_RD_SILENT,RX FIFO silent read"
hexmask.long 0x8 0.--31. 1. "DATA,Data read from the RX FIFO. Reading a data frame will NOT remove the data frame from the RX FIFO; i.e. behavior is similar to that of a PEEK operation. This field is used only for debugging purposes."
group.long 0xF00++0xB
line.long 0x0 "INTR,Interrupt register"
bitfld.long 0x0 24. "RX_WD,Triggers (sets to '1') when the Rx watchdog event occurs." "0,1"
bitfld.long 0x0 22. "RX_UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
newline
bitfld.long 0x0 21. "RX_OVERFLOW,Attempt to write to a full RX FIFO." "0,1"
bitfld.long 0x0 19. "RX_FULL,RX FIFO is full." "0,1"
newline
bitfld.long 0x0 18. "RX_NOT_EMPTY,RX FIFO is not empty." "0,1"
bitfld.long 0x0 16. "RX_TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL." "0,1"
newline
bitfld.long 0x0 8. "TX_WD,Triggers (sets to '1') when the Tx watchdog event occurs." "0,1"
bitfld.long 0x0 6. "TX_UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and TX_EMPTY is '1'." "0,1"
newline
bitfld.long 0x0 5. "TX_OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
bitfld.long 0x0 4. "TX_EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
newline
bitfld.long 0x0 1. "TX_NOT_FULL,TX FIFO is not full." "0,1"
bitfld.long 0x0 0. "TX_TRIGGER,Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL." "0,1"
line.long 0x4 "INTR_SET,Interrupt set register"
bitfld.long 0x4 24. "RX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
bitfld.long 0x4 22. "RX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 21. "RX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
bitfld.long 0x4 19. "RX_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 18. "RX_NOT_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
bitfld.long 0x4 16. "RX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "TX_WD,Write with '1' to set corresponding bit in interrupt request register." "0,1"
bitfld.long 0x4 6. "TX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "TX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
bitfld.long 0x4 4. "TX_EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "TX_NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
bitfld.long 0x4 0. "TX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_MASK,Interrupt mask register"
bitfld.long 0x8 24. "RX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
bitfld.long 0x8 22. "RX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 21. "RX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
bitfld.long 0x8 19. "RX_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 18. "RX_NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
bitfld.long 0x8 16. "RX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "TX_WD,Mask bit for corresponding bit in interrupt request register." "0,1"
bitfld.long 0x8 6. "TX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "TX_OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
bitfld.long 0x8 4. "TX_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "TX_NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
bitfld.long 0x8 0. "TX_TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF0C++0x3
line.long 0x0 "INTR_MASKED,Interrupt masked register"
bitfld.long 0x0 24. "RX_WD,Logical and of corresponding request and mask bits." "0,1"
bitfld.long 0x0 22. "RX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 21. "RX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
bitfld.long 0x0 19. "RX_FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 18. "RX_NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
bitfld.long 0x0 16. "RX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "TX_WD,Logical and of corresponding request and mask bits." "0,1"
bitfld.long 0x0 6. "TX_UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "TX_OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
bitfld.long 0x0 4. "TX_EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "TX_NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
bitfld.long 0x0 0. "TX_TRIGGER,Logical and of corresponding request and mask bits." "0,1"
tree.end
tree "LCD (LCD Direct)"
base ad:0x40210000
rgroup.long 0x0++0x3
line.long 0x0 "ID,ID & Revision"
hexmask.long.word 0x0 16.--31. 1. "REVISION,The version number is 0x0001"
hexmask.long.word 0x0 0.--15. 1. "ID,The ID of LCD controller peripheral is 0xF0F0"
group.long 0x4++0x7
line.long 0x0 "DIVIDER,LCD Divider Register"
hexmask.long.word 0x0 16.--31. 1. "DEAD_DIV,Length of the dead time period in cycles. When set to zero no dead time period exists."
hexmask.long.word 0x0 0.--15. 1. "SUBFR_DIV,Input clock frequency divide value to generate the 1/4 sub-frame period. The sub-frame period is 4*(SUBFR_DIV+1) cycles long."
line.long 0x4 "CONTROL,LCD Configuration Register"
rbitfld.long 0x4 31. "LS_EN_STAT,LS enable status bit. This bit is a copy of LS_EN that is synchronized to the low speed clock domain and back to the system clock domain. Firmware can use this bit to observe whether LS_EN has taken effect in the low speed clock domain." "0,1"
hexmask.long.byte 0x4 8.--11. 1. "COM_NUM,The number of COM connections minus 2. So:"
newline
bitfld.long 0x4 5.--6. "BIAS,PWM bias selection" "0: 1/2 Bias,1: 1/3 Bias,2: 1/4 Bias (not supported by LS generator),3: 1/5 Bias (not supported by LS generator)"
bitfld.long 0x4 4. "OP_MODE,Driving mode configuration" "0: PWM Mode,1: Digital Correlation Mode"
newline
bitfld.long 0x4 3. "TYPE,LCD driving waveform type configuration." "0: Type A - Each frame addresses each COM pin only..,1: Type B - Each frame addresses each COM pin twice.."
bitfld.long 0x4 2. "LCD_MODE,HS/LS Mode selection" "0: Select Low Speed (32kHz) Generator (Works in..,1: Select High Speed (system clock) Generator.."
newline
bitfld.long 0x4 1. "HS_EN,High speed (HS) generator enable" "0: disable,1: enable"
bitfld.long 0x4 0. "LS_EN,Low speed (LS) generator enable" "0: disable,1: enable"
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x100)++0x3
line.long 0x0 "DATA0[$1],LCD Pin Data Registers"
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb)."
repeat.end
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x200)++0x3
line.long 0x0 "DATA1[$1],LCD Pin Data Registers"
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb)."
repeat.end
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x300)++0x3
line.long 0x0 "DATA2[$1],LCD Pin Data Registers"
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb)."
repeat.end
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x400)++0x3
line.long 0x0 "DATA3[$1],LCD Pin Data Registers"
hexmask.long 0x0 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb)."
repeat.end
tree.end
tree "LPCOMP (Low-Power Comparator)"
base ad:0x402B0000
rgroup.long 0x0++0x3
line.long 0x0 "ID,ID & Revision"
hexmask.long.word 0x0 16.--31. 1. "REVISION,the version number is 0x0001"
hexmask.long.word 0x0 0.--15. 1. "ID,the ID of LPCOMP peripheral is 0xE0E0"
group.long 0x4++0x3
line.long 0x0 "CONFIG,LPCOMP Configuration Register"
bitfld.long 0x0 21. "DSI_LEVEL2,Opamp2 comparator DSI (trigger) out level : 0=pulse 1=level" "0: pulse,1: level"
bitfld.long 0x0 20. "DSI_BYPASS2,Opamp2 bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse) 1=bypass (output async)" "0: synchronize,1: bypass"
newline
bitfld.long 0x0 17. "DSI_LEVEL1,Opamp1 comparator DSI (trigger) out level : 0=pulse 1=level" "0: pulse,1: level"
bitfld.long 0x0 16. "DSI_BYPASS1,Opamp1 bypass comparator output synchronization for DSI output: 0=synchronize (level or pulse) 1=bypass (output async)" "0: synchronize,1: bypass"
newline
bitfld.long 0x0 15. "ENABLE2,Enable comparator #2" "0,1"
rbitfld.long 0x0 14. "OUT2,Current output value of the comparator." "0,1"
newline
bitfld.long 0x0 12.--13. "INTTYPE2,Sets which edge will trigger an IRQ" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
bitfld.long 0x0 11. "FILTER2,N/A" "0,1"
newline
bitfld.long 0x0 10. "HYST2,Add 10mV hysteresis to the comparator" "0: Enable Hysteresis,1: Disable Hysteresis"
bitfld.long 0x0 8.--9. "MODE2,Operating mode for the comparator" "0: Slow operating mode (uses less power <50uA),1: Fast operating mode (uses more power <400uA),2: Ultra low power operting mode (uses ~2-4uA),?"
newline
bitfld.long 0x0 7. "ENABLE1,Enable comparator #1" "0,1"
rbitfld.long 0x0 6. "OUT1,Current output value of the comparator." "0,1"
newline
bitfld.long 0x0 4.--5. "INTTYPE1,Sets which edge will trigger an IRQ" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
bitfld.long 0x0 3. "FILTER1,N/A" "0,1"
newline
bitfld.long 0x0 2. "HYST1,Add 10mV hysteresis to the comparator" "0: Enable Hysteresis,1: Disable Hysteresis"
bitfld.long 0x0 0.--1. "MODE1,Operating mode for the comparator" "0: Slow operating mode (uses less power <50uA),1: Fast operating mode (uses more power <400uA),2: Ultra low power operting mode (uses ~2-4uA),?"
group.long 0x10++0xB
line.long 0x0 "INTR,LPCOMP Interrupt request register"
bitfld.long 0x0 1. "COMP2,Comparator 2 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit." "0,1"
bitfld.long 0x0 0. "COMP1,Comparator 1 Interrupt: hardware sets this interrupt when comparator 0 triggers. Write with '1' to clear bit." "0,1"
line.long 0x4 "INTR_SET,LPCOMP Interrupt set register"
bitfld.long 0x4 1. "COMP2,Write with '1' to set corresponding bit in interrupt request register." "0,1"
bitfld.long 0x4 0. "COMP1,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_MASK,LPCOMP Interrupt request mask"
bitfld.long 0x8 1. "COMP2_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
bitfld.long 0x8 0. "COMP1_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0x1C++0x3
line.long 0x0 "INTR_MASKED,LPCOMP Interrupt request masked"
bitfld.long 0x0 1. "COMP2_MASKED,Logical and of corresponding request and mask bits." "0,1"
bitfld.long 0x0 0. "COMP1_MASKED,Logical and of corresponding request and mask bits." "0,1"
group.long 0xFF00++0xF
line.long 0x0 "TRIM1,LPCOMP Trim Register"
hexmask.long.byte 0x0 0.--4. 1. "COMP1_TRIMA,Trim A for Comparator #1"
line.long 0x4 "TRIM2,LPCOMP Trim Register"
hexmask.long.byte 0x4 0.--4. 1. "COMP1_TRIMB,Trim B for Comparator #1"
line.long 0x8 "TRIM3,LPCOMP Trim Register"
hexmask.long.byte 0x8 0.--4. 1. "COMP2_TRIMA,Trim A for Comparator #2"
line.long 0xC "TRIM4,LPCOMP Trim Register"
hexmask.long.byte 0xC 0.--4. 1. "COMP2_TRIMB,Trim B for Comparator #2"
tree.end
tree "MSC (MultiSense Controller)"
base ad:0x0
tree "MSC0"
base ad:0x40290000
group.long 0x0++0x2B
line.long 0x0 "CTL,Configuration and Control"
bitfld.long 0x0 31. "ENABLED,Master enable of the MSCv3 IP. Must be set to '1' for any operation to function." "0: N/A,1: N/A"
newline
bitfld.long 0x0 24. "CLK_MSC_RATIO,Control bit for logic that creates clk_msc from clk_hf." "0: N/A,1: N/A"
newline
bitfld.long 0x0 20. "BUF_MODE,Shield buffer operating mode select." "0: N/A,1: N/A"
newline
bitfld.long 0x0 16.--17. "OPERATING_MODE,Sequencer FSM Operating Mode" "0: Frame scan configurations are stored in system..,1: Frame scan configurations are stored in system..,2: Frame scan configurations are stored in IP RAM.,3: Frame scan configurations are stored in IP RAM."
newline
bitfld.long 0x0 12. "EXT_FRAME_START_EN,Control bit to enable external frame start of Sequencer FSM via GPIO." "0: N/A,1: N/A"
newline
bitfld.long 0x0 8. "CLK_SYNC_EN,Control bit to create external channel sync clock." "0: N/A,1: N/A"
newline
bitfld.long 0x0 4. "MSCCMP_EN,MSC Comparator Enable." "0: N/A,1: N/A"
newline
bitfld.long 0x0 0. "SENSE_EN,Enables the sense modulator output." "0: N/A,1: N/A"
line.long 0x4 "SPARE,Spare MMIO"
hexmask.long.byte 0x4 0.--5. 1. "SPARE,Spare MMIO (Hard IP)."
line.long 0x8 "SCAN_CTL1,Scan Control 1"
hexmask.long.byte 0x8 16.--23. 1. "FRAME_START_PTR,Pointer to first sensor configuration of a frame. Hardware increments a local pointer from this start point. In LP-AoC mode hardware returns to this pointer after the frame is complete prior to starting the next frame (after a timeout)."
newline
bitfld.long 0x8 12.--14. "DEBUG_CONV_PH_SEL,Debug counter conversion chop phase select for DEBUG_CONV_COUNT. Must be between 0 and NUM_CONV." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 8. "RAW_COUNT_MODE,Control bit to handle behaviour when RAW_COUNT exceeds 0xFFFF." "0: N/A,1: N/A"
newline
bitfld.long 0x8 4.--5. "NUM_SAMPLES,Number of samples (minus 1) to be scanned. NUM_SAMPLES > 1 results in autonomous scan same sensor (AS-SS) behaviour." "0,1,2,3"
newline
bitfld.long 0x8 3. "RESCAN_DEBUG_MODE,If this bit is set all results (good and bad) generated by NUM_AUTO_RESAMPLE are stored. Debug feature." "0: N/A,1: N/A"
newline
bitfld.long 0x8 0.--2. "NUM_AUTO_RESAMPLE,If Sequencer detects a bad conversion and NUM_AUTO_RESAMPLE != 0 it will not store the bad result. Instead it will automatically re-sample using current configuration without firmware intervention. This process repeats until a good.." "0,1,2,3,4,5,6,7"
line.long 0xC "SCAN_CTL2,Scan Control 2"
bitfld.long 0xC 24. "CHOP_EVEN_HOLD_EN,Use this bit to hold the chop value at the end of every even chop phase of NUM_CONV." "0: N/A,1: N/A"
newline
bitfld.long 0xC 16. "CHOP_POL,Polarity of first chop phase. Hardware updates chop control locally from this point (via inversion and following CHOP_EVEN_HOLD_EN programming also)." "0,1"
newline
hexmask.long.word 0xC 0.--9. 1. "NUM_EPI_CYCLES,Number of clk_mod cycles to be run during EPILOGUE. Note that setting this register to 0 is an illegal configuration. This guarantees at least 1 clk_mod cycle during EPILOGUE (required to help timing closure in Sequencer FSM)."
line.long 0x10 "INIT_CTL1,Initialisation Control 1"
bitfld.long 0x10 28. "PER_SAMPLE,Decides if coarse initialisation is done per sample when NUM_SAMPLES > 0 (i.e. more than one sample per scan). Applies to CMOD_SEL selected Cmod." "0: N/A,1: N/A"
newline
hexmask.long.word 0x10 16.--27. 1. "NUM_INIT_CMOD_12_SHORT_CYCLES,Duration of the coarse short phase (shorting Cmod1 and Cmod2 in full-wave mode). Programmed in terms of clk_mod cycles. Should be set to zero in the case of half-wave mode."
newline
hexmask.long.word 0x10 0.--11. 1. "NUM_INIT_CMOD_12_RAIL_CYCLES,Duration of the coarse initialisation phase (e.g. connecting Cmod1 to vdda and Cmod2 to vssa in full-wave mode). Programmed in terms of clk_mod cycles."
line.long 0x14 "INIT_CTL2,Initialisation Control 2"
hexmask.long.word 0x14 16.--27. 1. "NUM_INIT_CMOD_34_SHORT_CYCLES,Duration of the coarse short phase (shorting Cmod3 and Cmod4 in full-wave mode). Programmed in terms of clk_mod cycles. Should be set to zero in the case of half-wave mode."
newline
hexmask.long.word 0x14 0.--11. 1. "NUM_INIT_CMOD_34_RAIL_CYCLES,Duration of the coarse initialisation phase (e.g. connecting Cmod3 to vdda and Cmod4 to vssa in full-wave mode). Programmed in terms of clk_mod cycles."
line.long 0x18 "INIT_CTL3,Initialisation Control 3"
bitfld.long 0x18 15. "INIT_MODE,Determines autonomous initialisation behaviour during INIT_CMOD." "0: Decode CMOD_SEL,1: C1CB = 1"
newline
bitfld.long 0x18 10.--11. "CMOD_SEL,Select which Cmod are used and the cycle thresholds to be used for coarse initialisation. Note this field affects which Cmod switches are autonomously initialised by hardware as well as influencing the cycle counters as per INIT_MODE." "0: Used for full-wave,1: Used for full-wave,2: Used for half-wave,3: Used for half-wave"
newline
bitfld.long 0x18 8.--9. "NUM_PRO_OFFSET_TRIPS,Number of comparator trips required to be observed in PRO_OFFSET before proceeding to dummy cycles." "0,1,2,3"
newline
hexmask.long.byte 0x18 0.--7. 1. "NUM_PRO_OFFSET_CYCLES,Maximum number of clk_mod cycles to be assigned for the PRO_OFFSET state. If NUM_PRO_OFFSET_TRIPS are observed before this timeout exit at that point."
line.long 0x1C "INIT_CTL4,Initialisation Control 4"
hexmask.long.word 0x1C 16.--25. 1. "NUM_PRO_WAIT_CYCLES,Number of clk_mod cycles to be run during PRO_WAIT."
newline
hexmask.long.byte 0x1C 0.--7. 1. "NUM_PRO_DUMMY_SUB_CONVS,Number of sub-conversions (dummy cycles) to be run during PRO_DUMMY."
line.long 0x20 "SENSE_DUTY_CTL,Sense Clock Duty Cycle Control"
bitfld.long 0x20 27. "PHASE_WIDTH_SEL,Select which phases the PHASE_WIDTH applies to:" "0: N/A,1: N/A"
newline
hexmask.long.word 0x20 16.--25. 1. "PHASE_SHIFT_CYCLES,Phase shift cycle control for ph0X and ph1X."
newline
hexmask.long.word 0x20 0.--11. 1. "PHASE_WIDTH,Control width (clk_mod cycles) of ph0 and ph2 OR ph1 and ph3. If set to zero Fs is divided equally between all phases. This field is only applicable when LFSR_MODE = DIRECT_CLOCK."
line.long 0x24 "SENSE_PERIOD_CTL,Sense Clock Period Control"
hexmask.long.byte 0x24 16.--19. 1. "LFSR_SCALE,Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This scaling is only applicable in spread spectrum mode."
newline
hexmask.long.word 0x24 0.--11. 1. "LFSR_POLY,Programmable polynomial to be used for the sense LFSR. For example (default):"
line.long 0x28 "FILTER_CTL,Filter Control"
bitfld.long 0x28 24. "FILTER_MODE,N/A" "0: Use the standard first order counter low pass..,1: Use CIC2 Filter. Advantage of CIC2 over CIC1 is.."
newline
bitfld.long 0x28 16. "BIT_FORMAT,Determines how the synchronised comparator output is interpreted by the filter pipeline." "0: Input values [0 +1],1: Input values [-1 +1]. In this scenario a value.."
group.long 0x30++0x7
line.long 0x0 "CCOMP_CDAC_CTL,Compensation CAPDAC Control"
bitfld.long 0x0 31. "EPILOGUE_EN,Control on whether Ccomp is active during EPILOGUE for final balancing in a conversion." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x0 8.--15. 1. "SEL_CO_PRO_OFFSET,Select value for Compensation CAPDAC size during PRO_OFFSET until the first comparator trip is observed. Otherwise SEL_CO applies."
line.long 0x4 "DITHER_CDAC_CTL,Flatspot/Dither CAPDAC Switch Control"
hexmask.long.byte 0x4 16.--23. 1. "LFSR_POLY_FL,Dither/Flatspot CAPDAC LFSR polynomial. Uses same encoding as the spread spectrum polynomial LFSR_POLY. For example (default):"
newline
hexmask.long.byte 0x4 0.--7. 1. "SEL_FL,Select value for Dither/Flatspot CAPDAC size."
group.long 0x40++0x23
line.long 0x0 "CSW_CTL,Control Mux Switch Control"
hexmask.long 0x0 0.--31. 1. "CSW_FUNC_MODE,Select between SW_SEL_CSW[x] and SW_SEL_CSW_FUNC."
line.long 0x4 "SW_SEL_GPIO,GPIO Switch Control"
bitfld.long 0x4 24.--26. "SW_DSI_CSH_TANK,MUX select for dsi_csh_tank waveform." "0: N/A,1: N/A,2: chop == 1 ? ph0 : ph1,3: chop == 1 ? ph1 : ph3,4: N/A,?,?,?"
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bitfld.long 0x4 20.--22. "SW_DSI_CMOD,MUX select for dsi_cmod waveform." "0: N/A,1: N/A,2: chop == 1 ? ph1 : ph0,3: chop == 1 ? ph3 : ph1,4: N/A,?,?,?"
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bitfld.long 0x4 16. "SW_CSD_CHARGE,MUX select for csd_charge waveform." "0: N/A,1: N/A"
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bitfld.long 0x4 12.--13. "SW_CSD_POLARITY,MUX select for csd_polarity waveform." "0: N/A,1: N/A,2: N/A,?"
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bitfld.long 0x4 8. "SW_CSD_MUTUAL,MUX select for csd_mutual waveform." "0: N/A,1: N/A"
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bitfld.long 0x4 4.--6. "SW_CSD_SHIELD,MUX select for csd_shield waveform." "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,5: ph0 || [Fs2_ph1 && (ph1 || ph3)],6: N/A,?"
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bitfld.long 0x4 0.--2. "SW_CSD_SENSE,MUX select for csd_sense waveform." "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,5: N/A,6: N/A,?"
line.long 0x8 "SW_SEL_CDAC_RE,Reference CAPDAC Switch Control"
bitfld.long 0x8 20.--21. "SW_REBG,Reference CAPDAC bottom plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb)"
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bitfld.long 0x8 16.--17. "SW_REBV,Reference CAPDAC bottom plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb)"
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bitfld.long 0x8 12.--14. "SW_RETG,Reference CAPDAC top plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode,5: DFT mode,?,?"
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bitfld.long 0x8 8.--10. "SW_RETV,Reference CAPDAC top plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode,5: DFT mode,?,?"
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bitfld.long 0x8 4.--6. "SW_RECB,Reference CAPDAC to CSD Bus B Switch" "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_reffb) : sel = 11..,3: chop == 1 ? sel = 10 (clk_reffb) : sel = 11..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x8 0.--2. "SW_RETCA,Reference CAPDAC top plate to CSD Bus A Switch" "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_reffb) : sel = 11..,3: chop == 1 ? sel = 10 (clk_reffb) : sel = 11..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
line.long 0xC "SW_SEL_CDAC_CO,Compensation CAPDAC Switch Control"
bitfld.long 0xC 20.--21. "SW_COBG,Compensation CAPDAC bottom plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_comp),3: sel = 11 (!clk_comp)"
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bitfld.long 0xC 16.--17. "SW_COBV,Compensation CAPDAC bottom plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_comp),3: sel = 11 (!clk_comp)"
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bitfld.long 0xC 12.--14. "SW_COTG,Compensation CAPDAC top plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode,5: DFT mode,?,?"
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bitfld.long 0xC 8.--10. "SW_COTV,Compensation CAPDAC top plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode,5: DFT mode,?,?"
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bitfld.long 0xC 4.--6. "SW_COCB,Compensation CAPDAC to CSD Bus B Switch." "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_comp) : sel = 11..,3: chop == 1 ? sel = 10 (clk_comp) : sel = 11..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0xC 0.--2. "SW_COTCA,Compensation CAPDAC top plate to CSD Bus A Switch." "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_comp) : sel = 11..,3: chop == 1 ? sel = 10 (clk_comp) : sel = 11..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
line.long 0x10 "SW_SEL_CDAC_CF,Fine CAPDAC Switch Control"
bitfld.long 0x10 20.--21. "SW_CFBG,Fine CAPDAC bottom plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: FINE_MODE == REFERENCE ? sel = 10 (clk_reffb) :..,3: FINE_MODE == REFERENCE ? sel = 11 (!clk_reffb) :.."
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bitfld.long 0x10 16.--17. "SW_CFBV,Fine CAPDAC bottom plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: FINE_MODE == REFERENCE ? sel = 10 (clk_reffb) :..,3: FINE_MODE == REFERENCE ? sel = 11 (!clk_reffb) :.."
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bitfld.long 0x10 12.--14. "SW_CFTG,Fine CAPDAC top plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 [(FINE_MODE == REFERENCE) ? clk_reffb :..,3: sel = 11 [(FINE_MODE == REFERENCE) ? !clk_reffb..,4: DFT mode (ph0 ? sel = 01 : sel = 00),5: DFT mode (ph2 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x10 8.--10. "SW_CFTV,Fine CAPDAC top plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 [(FINE_MODE == REFERENCE) ? clk_reffb :..,3: sel = 11 [(FINE_MODE == REFERENCE) ? !clk_reffb..,4: DFT mode (ph0 ? sel = 01 : sel = 00),5: DFT mode (ph2 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x10 4.--6. "SW_CFTCB,Fine CAPDAC top plate to CSD Bus B Switch." "0: sel = 00,1: sel = 01,2: case({chop FINE_MODE}) {1 REFERENCE} : sel = 11..,3: case({chop FINE_MODE}) {1 REFERENCE} : sel = 10..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x10 0.--2. "SW_CFTCA,Fine CAPDAC top plate to CSD Bus A Switch." "0: sel = 00,1: sel = 01,2: case({chop FINE_MODE}) {1 REFERENCE} : sel = 11..,3: case({chop FINE_MODE}) {1 REFERENCE} : sel = 10..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
line.long 0x14 "SW_SEL_CMOD1,CMOD Switch Control 1"
bitfld.long 0x14 31. "ENABLED,CMOD1 enable." "0: N/A,1: N/A"
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bitfld.long 0x14 30. "REF_MODE,CMOD1 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD." "0: N/A,1: N/A"
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hexmask.long.byte 0x14 24.--27. 1. "SW_C1CG,CMOD1 to vssa_q Switch."
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hexmask.long.byte 0x14 16.--19. 1. "SW_C1CV,CMOD1 to vdda_q Switch."
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bitfld.long 0x14 12.--13. "SW_C1CC,CMOD1 to CSD Bus C Switch." "0: N/A,1: N/A,2: N/A,?"
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hexmask.long.byte 0x14 8.--11. 1. "SW_C1CB,CMOD1 to CSD Bus B Switch."
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hexmask.long.byte 0x14 0.--3. 1. "SW_C1CA,CMOD1 to CSD Bus A Switch."
line.long 0x18 "SW_SEL_CMOD2,CMOD Switch Control 2"
bitfld.long 0x18 31. "ENABLED,CMOD2 enable." "0: N/A,1: N/A"
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bitfld.long 0x18 30. "REF_MODE,CMOD2 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD." "0: N/A,1: N/A"
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hexmask.long.byte 0x18 24.--27. 1. "SW_C2CG,CMOD2 to vssa_q Switch."
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hexmask.long.byte 0x18 16.--19. 1. "SW_C2CV,CMOD2 to vdda_q Switch."
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bitfld.long 0x18 12.--13. "SW_C2CC,CMOD2 to CSD Bus C Switch." "0: N/A,1: N/A,2: N/A,?"
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hexmask.long.byte 0x18 8.--11. 1. "SW_C2CB,CMOD2 to CSD Bus B Switch."
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hexmask.long.byte 0x18 0.--3. 1. "SW_C2CA,CMOD2 to CSD Bus A Switch."
line.long 0x1C "SW_SEL_CMOD3,CMOD Switch Control 3"
bitfld.long 0x1C 31. "ENABLED,CMOD3 enable." "0: N/A,1: N/A"
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bitfld.long 0x1C 30. "REF_MODE,CMOD3 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD." "0: N/A,1: N/A"
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hexmask.long.byte 0x1C 24.--27. 1. "SW_C3CG,CMOD3 to vssa_q Switch."
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hexmask.long.byte 0x1C 16.--19. 1. "SW_C3CV,CMOD3 to vdda_q Switch."
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bitfld.long 0x1C 12.--13. "SW_C3CC,CMOD3 to CSD Bus C Switch." "0: N/A,1: N/A,2: N/A,?"
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hexmask.long.byte 0x1C 8.--11. 1. "SW_C3CB,CMOD3 to CSD Bus B Switch."
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hexmask.long.byte 0x1C 0.--3. 1. "SW_C3CA,CMOD3 to CSD Bus A Switch."
line.long 0x20 "SW_SEL_CMOD4,CMOD Switch Control 4"
bitfld.long 0x20 31. "ENABLED,CMOD4 enable." "0: N/A,1: N/A"
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bitfld.long 0x20 30. "REF_MODE,CMOD4 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD." "0: N/A,1: N/A"
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hexmask.long.byte 0x20 24.--27. 1. "SW_C4CG,CMOD4 to vssa_q Switch."
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hexmask.long.byte 0x20 16.--19. 1. "SW_C4CV,CMOD4 to vdda_q Switch."
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bitfld.long 0x20 12.--13. "SW_C4CC,CMOD4 to CSD Bus C Switch." "0: N/A,1: N/A,2: N/A,?"
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hexmask.long.byte 0x20 8.--11. 1. "SW_C4CB,CMOD4 to CSD Bus B Switch."
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hexmask.long.byte 0x20 0.--3. 1. "SW_C4CA,CMOD4 to CSD Bus A Switch."
group.long 0x70++0x3
line.long 0x0 "OBS_CTL,Observability Control"
hexmask.long.byte 0x0 24.--27. 1. "OBSERVE3,Selects the source for observe output signal 3:"
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hexmask.long.byte 0x0 16.--19. 1. "OBSERVE2,Selects the source for observe output signal 2:"
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hexmask.long.byte 0x0 8.--11. 1. "OBSERVE1,Selects the source for observe output signal 1:"
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hexmask.long.byte 0x0 0.--3. 1. "OBSERVE0,Selects the source for observe output signal 0:"
group.long 0x80++0x7
line.long 0x0 "WAKEUP_CTL,Wakeup Control"
bitfld.long 0x0 31. "ENABLED,If set then LP AoC FSM will operate when in DEEP_SLEEP. This also switches clk_hf -> clk_lf." "0: N/A,1: N/A"
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hexmask.long.word 0x0 0.--15. 1. "WAKEUP_TIMER,Timer interval between wakeup scans in LP-AoC mode. Assumes a 32kHz operating clock (clk_lf). Desired range is 1->2000ms."
line.long 0x4 "LP_AOC_CTL,LP-AoC Control"
hexmask.long.byte 0x4 24.--27. 1. "DEBOUNCE_THRESHOLD,Global threshold for successive TOUCH_THRESHOLD exceeds to warrant a full system wakeup."
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hexmask.long.byte 0x4 16.--23. 1. "BUCKET_STEP_SIZE,Global step size for SENSOR_BASELINE adjustment."
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hexmask.long.word 0x4 0.--15. 1. "BUCKET_THRESHOLD,Global threshold to control the per sensor SENSOR_BASELINE updates."
rgroup.long 0x100++0x13
line.long 0x0 "STATUS1,General Status Register 1"
hexmask.long.word 0x0 16.--31. 1. "RAW_COUNT_POS,Useful for determining component counts for positive and negative charge by subtracting from RAW_COUNT."
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hexmask.long.word 0x0 0.--15. 1. "RAW_COUNT,Live current raw counter. For debug/test purposes. In normal operation Firmware/DMA will typically read results from RESULT_FIFO_RD."
line.long 0x4 "STATUS2,General Status Register 2"
hexmask.long.word 0x4 0.--15. 1. "DEBUG_CONV_COUNT,Debug raw count for a particular conversion. Enabled only during a specified conversion of a sample (a specific chop phase)."
line.long 0x8 "STATUS3,General Status Register 3"
bitfld.long 0x8 28. "MSC_CMP_OUT,Output of main sensing comparator (synchronized). For debug/test purposes." "0,1"
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bitfld.long 0x8 24. "FS_CLOCK,Sense clock Fs control waveform. For debug/test purposes." "0,1"
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hexmask.long.byte 0x8 16.--19. 1. "SEQ_STATE,MSC Sequencer FSM state."
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hexmask.long.word 0x8 0.--15. 1. "NUM_SUB_CONVS,Number of sub-conversions remaining while in PRO_DUMMY and SUB_CONV."
line.long 0xC "RESULT_FIFO_STATUS,Result FIFO Status"
bitfld.long 0xC 31. "FIFO_OVERFLOW,Set if hardware attempts to write a RAW_COUNT (and associated metrics) to an already full result FIFO." "0,1"
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bitfld.long 0xC 30. "FIFO_UNDERFLOW,Hardware sets this field to '1' when reading from an empty FIFO (RESULT_FIFO_STATUS.USED is '0')." "0,1"
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hexmask.long.word 0xC 20.--29. 1. "RD_PTR,Result FIFO read pointer: FIFO location from which data is read via AHB."
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hexmask.long.word 0xC 10.--19. 1. "WR_PTR,Result FIFO write pointer: FIFO location at which a new data is written by the hardware."
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hexmask.long.word 0xC 0.--9. 1. "USED,Number of used/occupied entries in the result FIFO. When '0' the FIFO is empty."
line.long 0x10 "RESULT_FIFO_RD,Result FIFO Pointer"
hexmask.long.byte 0x10 24.--27. 1. "BAD_CONV_COUNT,Counter to indicate whether conversion of a sample is bad at the end of each chop phase. This is true if the comparator has not tripped by the end of EPILOGUE in a chop phase."
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bitfld.long 0x10 20.--22. "RESAMPLE_COUNT,Counter indicating number of attempted re-samples (via NUM_AUTO_RESAMPLE) for this raw count." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 16. "OVERFLOW,RAW_COUNT overflow." "0,1"
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hexmask.long.word 0x10 0.--15. 1. "RAW_COUNT,FILTER_MODE = CIC1: Accumulated raw count for a sample."
group.long 0x170++0xB
line.long 0x0 "INTR,MSCv3 Interrupt Cause Register"
bitfld.long 0x0 31. "FIFO_OVERFLOW,Result FIFO overflow condition." "0,1"
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bitfld.long 0x0 30. "FIFO_UNDERFLOW,Result FIFO underflow condition." "0,1"
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bitfld.long 0x0 24. "CONFIG_REQ,Request for scan configuration and scan start. The Sequencer FSM is entering WAIT_SCAN_START when this interrupt is raised. This interrupt can be used in CPU mode in a multi-channel scenario with external frame start to indicate to firmware.." "0,1"
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bitfld.long 0x0 20. "CIC2_ERROR,CIC2 error detected. This bit is set at the end of a sample if the number of valid CIC2 sub-samples is not one of [1 2 4 8 16]. At the end of a CIC2 sample RESULT_FIFO_RD.RAW_COUNT contains the average of the valid sub-samples observed during.." "?,1: no division"
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bitfld.long 0x0 16. "FRAME,A single frame is complete." "0,1"
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bitfld.long 0x0 12. "INIT,Coarse initialisation complete. For debug purposes." "0,1"
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bitfld.long 0x0 8. "SCAN,A single scan is complete." "0,1"
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bitfld.long 0x0 4. "SAMPLE,A single sample is complete. For debug purposes." "0,1"
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bitfld.long 0x0 0. "SUB_SAMPLE,A valid CIC2 sub-sample is complete. To facilitate firmware averaging of sub-samples. For debug purposes." "0,1"
line.long 0x4 "INTR_SET,MSCv3 Interrupt Set Register"
bitfld.long 0x4 31. "FIFO_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 30. "FIFO_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 24. "CONFIG_REQ,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 20. "CIC2_ERROR,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 16. "FRAME,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 12. "INIT,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 8. "SCAN,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 4. "SAMPLE,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 0. "SUB_SAMPLE,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
line.long 0x8 "INTR_MASK,MSCv3 Interrupt Mask Register"
bitfld.long 0x8 31. "FIFO_OVERFLOW,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 30. "FIFO_UNDERFLOW,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 24. "CONFIG_REQ,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 20. "CIC2_ERROR,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 16. "FRAME,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 12. "INIT,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 8. "SCAN,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 4. "SAMPLE,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 0. "SUB_SAMPLE,Mask bit for corresponding bit in interrupt cause register." "0,1"
rgroup.long 0x17C++0x3
line.long 0x0 "INTR_MASKED,MSCv3 Interrupt Masked Register"
bitfld.long 0x0 31. "FIFO_OVERFLOW,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 30. "FIFO_UNDERFLOW,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 24. "CONFIG_REQ,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 20. "CIC2_ERROR,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 16. "FRAME,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 12. "INIT,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 8. "SCAN,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 4. "SAMPLE,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 0. "SUB_SAMPLE,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
group.long 0x180++0xB
line.long 0x0 "INTR_LP,Low Power Interrupt Cause Register"
bitfld.long 0x0 0. "WAKEUP,LP-AoC has detected wakeup." "0,1"
line.long 0x4 "INTR_LP_SET,Low Power Interrupt Set Register"
bitfld.long 0x4 0. "WAKEUP,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
line.long 0x8 "INTR_LP_MASK,Low Power Interrupt Mask Register"
bitfld.long 0x8 0. "WAKEUP,Mask bit for corresponding bit in interrupt cause register." "0,1"
rgroup.long 0x18C++0x3
line.long 0x0 "INTR_LP_MASKED,Low Power Interrupt Masked Register"
bitfld.long 0x0 0. "WAKEUP,Logical AND of corresponding INTR_LP and INTR_LP_MASK bits." "0,1"
group.long 0x190++0x3
line.long 0x0 "FRAME_CMD,Frame Command Register"
bitfld.long 0x0 0. "START_FRAME,Start the MSCv3 sequencer frame process. Note that a rising edge on this bit also creates a 2x cycle clk_msc pulse on the msc_ext_frm_start_out signal. The corresponding msc_ext_frm_start_out_en is controlled by CTL.ENABLED." "0,1"
group.long 0x198++0x3
line.long 0x0 "WAKEUP_CMD,Wakeup Command Register"
bitfld.long 0x0 16. "ABORT,Abort the LP-AoC when in WAIT_FOR_DS state." "0,1"
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bitfld.long 0x0 0. "WAIT_FOR_DS,Set by firmware to prime the LP-AoC FSM to be ready to detect entry to DEEP_SLEEP. When detected hardware clears the bit down and the LP-AoC FSM periodically scans all valid sensor configurations programmed in the sensor configuration.." "0,1"
group.long 0x200++0x23
line.long 0x0 "SNS_STRUCT_CTL,Sensor Struct Control"
hexmask.long.byte 0x0 8.--11. 1. "LENGTH,Number of SNS_* registers from OFFSET for current sensor configuration in local IP storage. Used by LOAD_CONFIG state in Sequencer FSM. Applicable only when CONFIG_NR > 0."
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hexmask.long.byte 0x0 0.--3. 1. "OFFSET,Starting offset into SNS_* registers of current sensor configuration in local IP storage. Used by LOAD_CONFIG state in Sequencer FSM. Applicable only when CONFIG_NR > 0."
line.long 0x4 "SNS_LP_AOC_SENSOR_CTL1,LP-AoC Sensor Control 1"
hexmask.long.word 0x4 16.--31. 1. "N_BUCKET,Per sensor bucket for baseline <= raw count adjustments."
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hexmask.long.word 0x4 0.--15. 1. "P_BUCKET,Per sensor bucket for baseline greater than raw count adjustments."
line.long 0x8 "SNS_LP_AOC_SENSOR_CTL2,LP-AoC Sensor Control 2"
hexmask.long.word 0x8 16.--27. 1. "TOUCH_THRESHOLD,Per sensor threshold for |baseline - rawCount| to warrant a single touch detect."
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hexmask.long.word 0x8 0.--15. 1. "SENSOR_BASELINE,Per sensor baseline value."
line.long 0xC "SNS_SW_SEL_CSW_MASK2,Control MUX Function Select Mask 2"
hexmask.long 0xC 0.--31. 1. "FUNC_MASK,{SNS_SW_SEL_CSW_MASK2.FUNC_MASK[x] "
line.long 0x10 "SNS_SW_SEL_CSW_MASK1,Control MUX Function Select Mask 1"
hexmask.long 0x10 0.--31. 1. "FUNC_MASK,{SNS_SW_SEL_CSW_MASK2.FUNC_MASK[x] "
line.long 0x14 "SNS_SW_SEL_CSW_MASK0,Control MUX Function Select Mask 0"
hexmask.long 0x14 0.--31. 1. "FUNC_MASK,{SNS_SW_SEL_CSW_MASK2.FUNC_MASK[x] "
line.long 0x18 "SNS_SCAN_CTL,Sensor Scan Control"
bitfld.long 0x18 31. "INIT_BYPASS,Coarse initialisation bypass control. Applies to CMOD_SEL selected Cmod." "0: N/A,1: N/A"
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bitfld.long 0x18 28.--30. "NUM_CONV,Number of conversions (minus 1) per scanned sample. This is required for chopping (chop polarity is updated per conversion)." "0: N/A,1: N/A,?,3: N/A,?,?,?,7: N/A"
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hexmask.long.word 0x18 16.--27. 1. "COMP_DIV,The ratio (minus 1) of clk_comp::clk_mod."
newline
hexmask.long.word 0x18 0.--15. 1. "NUM_SUB_CONVS,Number of sub-conversions (minus 1) in a conversion."
line.long 0x1C "SNS_CDAC_CTL,Sensor CAPDAC Control"
bitfld.long 0x1C 28. "LFSR_SCALE_TYPE_FL,Flatspot/Dither CAPDAC shift direction." "0: N/A,1: N/A"
newline
bitfld.long 0x1C 24.--26. "LFSR_SCALE_FL,Shift the magnitude portion of the Flatspot/Dither CAPDAC LFSR output code left or right by LSFR_SCALE_FL bits. Direction of shift controlled by LFSR_SCALE_TYPE_FL." "?,?,?,?,?,?,6: bit polynomial,7: bit magnitude"
newline
bitfld.long 0x1C 23. "FL_EN,Dither/Flatspot LFSR enable control." "0: N/A,1: N/A"
newline
bitfld.long 0x1C 22. "CLOCK_REF_RATE,Used to select clk_mod or clk_mod/2 to as clk_ref. This clock is gated depending on the synchronised comparator to generate the gated feedback clock (clk_reffb) to the Reference CAPDAC." "0: N/A,1: N/A"
newline
bitfld.long 0x1C 21. "FINE_MODE,Operational mode for Fine CAPDAC" "0: N/A,1: N/A"
newline
hexmask.long.byte 0x1C 16.--20. 1. "SEL_CF,Select value for Fine CAPDAC size."
newline
hexmask.long.byte 0x1C 8.--15. 1. "SEL_CO,Select value for Compensation CAPDAC size."
newline
hexmask.long.byte 0x1C 0.--7. 1. "SEL_RE,Select value for Reference CAPDAC size."
line.long 0x20 "SNS_CTL,Sense Control and Command Register"
bitfld.long 0x20 30.--31. "LFSR_BITS,Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period (spread spectrum mode)." "0: Use 2 bits: range = [-2 1],1: Use 3 bits: range = [-4 3],2: Use 4 bits: range = [-8 7],3: Use 5 bits: range = [-16 15] (default)"
newline
bitfld.long 0x20 28.--29. "LFSR_MODE,Mode for generating the sense clock." "0: N/A,1: N/A,2: N/A,?"
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hexmask.long.word 0x20 16.--27. 1. "SENSE_DIV,The length (minus 1) of the sense modulation 'clock' period in clk_mod cycles (frequency = Fs). SENSE_DIV + 1 = sense_ratio."
newline
hexmask.long.byte 0x20 8.--15. 1. "DECIM_RATE,Sets the decimation rate for the sinc^2 filter (CIC2). Typically referred to as N. Note N = DECIM_RATE + 1. Only applies when FILTER_CTL.FILTER_MODE = CIC2 and irrelevant for CIC1 mode (no effect in this mode)."
newline
bitfld.long 0x20 6.--7. "SENSE_MODE_SEL,Sense mode register structure selection. This field allows quick change between registers that influence sense mode. This register selects which structure is currently 'live' and used by the IP." "0: Use MODE_STRUCT[0].,1: Use MODE_STRUCT[1].,2: Use MODE_STRUCT[2].,3: Use MODE_STRUCT[3]."
newline
bitfld.long 0x20 4.--5. "MULTI_CH_MODE,Multi channel mode configuration. Determines whether consensus mechanism is engaged to ensure channels scan in lockstep." "0: N/A,1: N/A,2: N/A,?"
newline
bitfld.long 0x20 2. "LAST,Indicator that current sensor configuration is the last sensor in the frame." "0,1"
newline
bitfld.long 0x20 1. "VALID,Indicator of sensor configuration validity." "0,1"
newline
bitfld.long 0x20 0. "START_SCAN,Start the MSCv3 sequencer scan process. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when all NUM_SAMPLES for this scan have been accumulated or if the sequencer is reset." "0,1"
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x300)++0x3
line.long 0x0 "SW_SEL_CSW[$1],Control Switch MUX Switch Control"
bitfld.long 0x0 31. "ENABLED,Control MUX Sensor N enable." "0: N/A,1: N/A"
newline
bitfld.long 0x0 30. "REF_MODE,Control MUX Sensor N is used as a reference." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x0 24.--27. 1. "SW_SNCG,Control MUX Sensor N to vssa_q Switch."
newline
hexmask.long.byte 0x0 16.--19. 1. "SW_SNCV,Control MUX Sensor N to vdda_q Switch."
newline
bitfld.long 0x0 12.--13. "SW_SNCC,Control MUX Sensor N to CSD Bus C Switch." "0: N/A,1: N/A,2: N/A,?"
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hexmask.long.byte 0x0 8.--11. 1. "SW_SNCB,Control MUX Sensor N to CSD Bus B Switch."
newline
hexmask.long.byte 0x0 0.--3. 1. "SW_SNCA,Control MUX Sensor N to CSD Bus A Switch."
repeat.end
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x400)++0x3
line.long 0x0 "SW_SEL_CSW_FUNC[$1],Control Switch MUX Switch Control Global Functions"
bitfld.long 0x0 31. "ENABLED,Control MUX Sensor enable." "0: N/A,1: N/A"
newline
bitfld.long 0x0 30. "REF_MODE,Control MUX Sensor is used as a reference." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x0 24.--27. 1. "SW_SNCG,Control MUX Sensor to vssa_q Switch."
newline
hexmask.long.byte 0x0 16.--19. 1. "SW_SNCV,Control MUX Sensor to vdda_q Switch."
newline
bitfld.long 0x0 12.--13. "SW_SNCC,Control MUX Sensor to CSD Bus C Switch." "0: N/A,1: N/A,2: N/A,?"
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hexmask.long.byte 0x0 8.--11. 1. "SW_SNCB,Control MUX Sensor to CSD Bus B Switch."
newline
hexmask.long.byte 0x0 0.--3. 1. "SW_SNCA,Control MUX Sensor to CSD Bus A Switch."
repeat.end
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40290500 ad:0x40290520 ad:0x40290540)
tree "MODE[$1]"
base $2
group.long ($2)++0x13
line.long 0x0 "SENSE_DUTY_CTL,Sense Clock Duty Cycle Control"
bitfld.long 0x0 28. "PHASE_MODE_SEL,Select 4-phase or 2-phase mode." "0: N/A,1: N/A"
newline
bitfld.long 0x0 24. "PHASE_SHIFT_EN,Enable phase shift logic that generates the Ph0X and Ph1X waveforms. Used for inductive and impedance sensing." "0: N/A,1: N/A"
newline
bitfld.long 0x0 10. "PHX_GAP_2CYCLE_EN,If set applies a two cycle gap on ph0X/ph1X if the corresponding PHASE_GAP_*_EN is set." "0: N/A,1: N/A"
newline
bitfld.long 0x0 9. "PHASE_GAP_PH1X_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph1x." "0: No gap,1: N/A"
newline
bitfld.long 0x0 8. "PHASE_GAP_PH0X_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph0x." "0: No gap,1: N/A"
newline
bitfld.long 0x0 6. "PH_GAP_2CYCLE_EN,If set applies a two cycle gap on ph0/ph1/ph2/ph3/Fs2_ph0/Fs2_ph1 if the corresponding PHASE_GAP_*_EN is set." "0: N/A,1: N/A"
newline
bitfld.long 0x0 5. "PHASE_GAP_FS2_PH1_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of Fs2_ph0." "0: No gap,1: N/A"
newline
bitfld.long 0x0 4. "PHASE_GAP_FS2_PH0_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of Fs2_ph0." "0: No gap,1: N/A"
newline
bitfld.long 0x0 3. "PHASE_GAP_PH3_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph3." "0: No gap,1: N/A"
newline
bitfld.long 0x0 2. "PHASE_GAP_PH2_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph2." "0: No gap,1: N/A"
newline
bitfld.long 0x0 1. "PHASE_GAP_PH1_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph1." "0: No gap,1: N/A"
newline
bitfld.long 0x0 0. "PHASE_GAP_PH0_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph0." "0: No gap,1: N/A"
line.long 0x4 "SW_SEL_CDAC_FL,Flatspot/Dither CAPDAC Switch Control"
bitfld.long 0x4 31. "ACTIVATION_MODE,Activation event for Dither/Flatspot LFSR." "0: N/A,1: N/A"
newline
bitfld.long 0x4 20.--22. "SW_FLBG,Flatspot/Dither CAPDAC bottom plate to vssa_q Switch." "0: N/A,1: N/A,2: N/A,3: N/A,4: [(msb^ph1)^(ph0||ph1)] & [ph0||ph1],5: (![(msb^ph1)^(ph0||ph1)]) & [ph0||ph1],6: [(msb^(ph2||ph3))^(ph0||ph2)] &..,7: (![(msb^(ph2||ph3))^(ph0||ph2)]) &.."
newline
bitfld.long 0x4 16.--18. "SW_FLBV,Flatspot/Dither CAPDAC bottom plate to vdda_q Switch." "0: N/A,1: N/A,2: N/A,3: N/A,4: [(msb^ph1)^(ph0||ph1)] & [ph0||ph1],5: (![(msb^ph1)^(ph0||ph1)]) & [ph0||ph1],6: [(msb^(ph2||ph3))^(ph0||ph2)] &..,7: (![(msb^(ph2||ph3))^(ph0||ph2)]) &.."
newline
bitfld.long 0x4 12.--14. "SW_FLTG,Flatspot/Dither CAPDAC top plate to vssa_q Switch." "0: N/A,1: N/A,2: N/A,3: N/A,4: DFT mode,5: DFT mode,?,?"
newline
bitfld.long 0x4 8.--9. "SW_FLTV,Flatspot/Dither CAPDAC top plate to vdda_q Switch." "0: N/A,1: N/A,2: DFT mode,3: DFT mode"
newline
bitfld.long 0x4 4.--6. "SW_FLCB,Flatspot/Dither CAPDAC to CSD Bus B Switch" "0: N/A,1: N/A,2: chop == 1 ? ph1 : ph3,3: chop == 1 ? ph3 : ph1,4: chop == 1 ? ph0 : ph1,5: chop == 1 ? ph1 : ph0,?,?"
newline
bitfld.long 0x4 0.--2. "SW_FLTCA,Flatspot/Dither CAPDAC top plate to CSD Bus A Switch" "0: N/A,1: N/A,2: chop == 1 ? ph1 : ph3,3: chop == 1 ? ph3 : ph1,4: chop == 1 ? ph0 : ph1,5: chop == 1 ? ph1 : ph0,?,?"
line.long 0x8 "SW_SEL_TOP,Top Level Switch Control"
bitfld.long 0x8 31. "MBF,AMUXBUSB to Filter Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x8 30. "RMF,Ratiometric Reference to Filter Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x8 29. "BGRF,Bandgap Reference to Filter Switch" "0: N/A,1: N/A"
newline
hexmask.long.byte 0x8 24.--27. 1. "SHG,COAX Shield to vssa_q Switch"
newline
hexmask.long.byte 0x8 20.--23. 1. "SHV,COAX Shield to vdda_q Switch"
newline
bitfld.long 0x8 18.--19. "SOSH,COAX Shield to Shield Buffer Output Switch" "0: N/A,1: N/A,2: N/A,?"
newline
bitfld.long 0x8 16.--17. "BYB,AMUXBUS B to CSD Bus B Switch." "0: sel = 00,1: sel = 01,2: sel = 10,3: sel = 11"
newline
bitfld.long 0x8 15. "AYB_EN,AMUXBUS A to CSD Bus B Switch. Controls first part of AYB switch (AYB_EN<0> on the hardIP)." "0: on the hardIP),1: Closes first part of AYB switch and disables.."
newline
bitfld.long 0x8 12.--14. "AYB_CTL,AMUXBUS A to CSD Bus B Switch. Controls second part of AYB switch (AYB_EN<1> on hardIP)." "0: Opens second part of AYB switch. Enables..,1: on hardIP),2: chop == 0 ? ph1 : ph0,3: chop == 0 ? ph3 : ph1,4: chop == 0 ? ph1 : ph3,5: chop == 0 ? ph0 : ph1,6: N/A,7: N/A"
newline
bitfld.long 0x8 11. "AYA_EN,AMUXBUS A to CSD Bus A Switch. Controls the first part of AYA switch (AYA_EN<0> on the hardIP)." "0: on the hardIP),1: Closes first part of AYA switch and disables.."
newline
bitfld.long 0x8 8.--10. "AYA_CTL,AMUXBUS A to CSD Bus A Switch. Controls second part of AYA switch (AYA_EN<1> on hardIP)." "0: Opens second part of AYA switch. Enables..,1: on hardIP),2: chop == 0 ? ph0 : ph1,3: chop == 0 ? ph1 : ph3,4: chop == 0 ? ph3 : ph1,5: chop == 0 ? ph1 : ph0,6: N/A,7: N/A"
newline
bitfld.long 0x8 6. "MBCC,AMUXBUSB to CSD Bus C Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x8 4. "CBCC,CSD Bus B to CSD Bus C Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x8 2. "CACC,CSD Bus A to CSD Bus C Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x8 0. "CACB,CSD Bus A to CSD Bus B Switch." "0: N/A,1: N/A"
line.long 0xC "SW_SEL_COMP,MSC Comparator Switch Control"
bitfld.long 0xC 31. "HALF_WAVE_EN,Enables halfwave mode in the comparator where reference is vdda_q." "0: N/A,1: N/A"
newline
bitfld.long 0xC 22. "CMF,Comparator Minus Terminal to Reference Filter Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 20. "CMG,Comparator Minus Terminal to vssa_q Switch." "0: N/A,1: N/A"
newline
bitfld.long 0xC 18. "CMV,Comparator Minus Terminal to vdda_q Switch." "0: N/A,1: N/A"
newline
bitfld.long 0xC 16. "CMCS4,Comparator Minus Terminal to CMOD4 Sense Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 14. "CMCS2,Comparator Minus Terminal to CMOD2 Sense Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 12. "CPF,Comparator Plus Terminal to Reference Filter Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 10. "CMCB,Comparator Minus Terminal to CSD Bus B Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 8. "CPCB,Comparator Plus Terminal to CSD Bus B Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 6. "CPCA,Comparator Plus Terminal to CSD Bus A Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 4. "CPMA,Comparator Plus Terminal to AMUXBUSA Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 2. "CPCS3,Comparator Plus Terminal to CMOD3 Sense Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 0. "CPCS1,Comparator Plus Terminal to CMOD1 Sense Switch" "0: N/A,1: N/A"
line.long 0x10 "SW_SEL_SH,Shielding Switch Control"
bitfld.long 0x10 31. "BUF_EN,Enable the shield buffer." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x10 24.--27. 1. "BUF_SEL,Selects value of compensation capacitance in shield buffer."
newline
bitfld.long 0x10 18. "CCSO,CSD Bus C to Shield OpAmp Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 16. "FSP,Reference Filter to Shield Positive Terminal Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 14. "SPCS3,Shield Positive Terminal to CMOD3 Sense Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 12. "SPCS1,Shield Positive Terminal to CMOD1 Sense Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 10. "CBSO,CSD Bus B to Shield OpAmp Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 8. "SOMB,Shield OpAmp to AMUXBUSB Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 6. "C3SH,cmod3_4_sh to sh Switch (Drives cmod3_4_sh with shield signal)" "0: N/A,1: N/A"
newline
bitfld.long 0x10 4. "C3SHG,cmod3_4_sh to vssa Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 2. "C1SH,cmod1_2_sh to sh Switch (Drives cmod1_2_sh with shield signal)" "0: N/A,1: N/A"
newline
bitfld.long 0x10 0. "C1SHG,cmod1_2_sh to vssa Switch" "0: N/A,1: N/A"
tree.end
repeat.end
base ad:0x40290000
repeat 4096. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x1000)++0x3
line.long 0x0 "SENSOR_DATA[$1],Sensor Configuration Storage"
hexmask.long 0x0 0.--31. 1. "DATA,Local IP storage to support per-sensor configuration for AS-MS mode. Storage requirement in bytes is CONFIG_NR * (number of per sensor registers) * 4. The per sensor registers all have the prefix SNS_*."
repeat.end
group.long 0xFF00++0x3
line.long 0x0 "TRIM_CTL,Trim Control"
bitfld.long 0x0 5. "TRIM_POLARITY,Controls polarity of comparator offset trim." "0,1"
newline
bitfld.long 0x0 4. "TRIM_EN,Enables comparator offset trim." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x0 0.--3. 1. "TRIM_IN,Controls magnitude of comparator offset trim."
tree.end
tree "MSC1"
base ad:0x402A0000
group.long 0x0++0x2B
line.long 0x0 "CTL,Configuration and Control"
bitfld.long 0x0 31. "ENABLED,Master enable of the MSCv3 IP. Must be set to '1' for any operation to function." "0: N/A,1: N/A"
newline
bitfld.long 0x0 24. "CLK_MSC_RATIO,Control bit for logic that creates clk_msc from clk_hf." "0: N/A,1: N/A"
newline
bitfld.long 0x0 20. "BUF_MODE,Shield buffer operating mode select." "0: N/A,1: N/A"
newline
bitfld.long 0x0 16.--17. "OPERATING_MODE,Sequencer FSM Operating Mode" "0: Frame scan configurations are stored in system..,1: Frame scan configurations are stored in system..,2: Frame scan configurations are stored in IP RAM.,3: Frame scan configurations are stored in IP RAM."
newline
bitfld.long 0x0 12. "EXT_FRAME_START_EN,Control bit to enable external frame start of Sequencer FSM via GPIO." "0: N/A,1: N/A"
newline
bitfld.long 0x0 8. "CLK_SYNC_EN,Control bit to create external channel sync clock." "0: N/A,1: N/A"
newline
bitfld.long 0x0 4. "MSCCMP_EN,MSC Comparator Enable." "0: N/A,1: N/A"
newline
bitfld.long 0x0 0. "SENSE_EN,Enables the sense modulator output." "0: N/A,1: N/A"
line.long 0x4 "SPARE,Spare MMIO"
hexmask.long.byte 0x4 0.--5. 1. "SPARE,Spare MMIO (Hard IP)."
line.long 0x8 "SCAN_CTL1,Scan Control 1"
hexmask.long.byte 0x8 16.--23. 1. "FRAME_START_PTR,Pointer to first sensor configuration of a frame. Hardware increments a local pointer from this start point. In LP-AoC mode hardware returns to this pointer after the frame is complete prior to starting the next frame (after a timeout)."
newline
bitfld.long 0x8 12.--14. "DEBUG_CONV_PH_SEL,Debug counter conversion chop phase select for DEBUG_CONV_COUNT. Must be between 0 and NUM_CONV." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 8. "RAW_COUNT_MODE,Control bit to handle behaviour when RAW_COUNT exceeds 0xFFFF." "0: N/A,1: N/A"
newline
bitfld.long 0x8 4.--5. "NUM_SAMPLES,Number of samples (minus 1) to be scanned. NUM_SAMPLES > 1 results in autonomous scan same sensor (AS-SS) behaviour." "0,1,2,3"
newline
bitfld.long 0x8 3. "RESCAN_DEBUG_MODE,If this bit is set all results (good and bad) generated by NUM_AUTO_RESAMPLE are stored. Debug feature." "0: N/A,1: N/A"
newline
bitfld.long 0x8 0.--2. "NUM_AUTO_RESAMPLE,If Sequencer detects a bad conversion and NUM_AUTO_RESAMPLE != 0 it will not store the bad result. Instead it will automatically re-sample using current configuration without firmware intervention. This process repeats until a good.." "0,1,2,3,4,5,6,7"
line.long 0xC "SCAN_CTL2,Scan Control 2"
bitfld.long 0xC 24. "CHOP_EVEN_HOLD_EN,Use this bit to hold the chop value at the end of every even chop phase of NUM_CONV." "0: N/A,1: N/A"
newline
bitfld.long 0xC 16. "CHOP_POL,Polarity of first chop phase. Hardware updates chop control locally from this point (via inversion and following CHOP_EVEN_HOLD_EN programming also)." "0,1"
newline
hexmask.long.word 0xC 0.--9. 1. "NUM_EPI_CYCLES,Number of clk_mod cycles to be run during EPILOGUE. Note that setting this register to 0 is an illegal configuration. This guarantees at least 1 clk_mod cycle during EPILOGUE (required to help timing closure in Sequencer FSM)."
line.long 0x10 "INIT_CTL1,Initialisation Control 1"
bitfld.long 0x10 28. "PER_SAMPLE,Decides if coarse initialisation is done per sample when NUM_SAMPLES > 0 (i.e. more than one sample per scan). Applies to CMOD_SEL selected Cmod." "0: N/A,1: N/A"
newline
hexmask.long.word 0x10 16.--27. 1. "NUM_INIT_CMOD_12_SHORT_CYCLES,Duration of the coarse short phase (shorting Cmod1 and Cmod2 in full-wave mode). Programmed in terms of clk_mod cycles. Should be set to zero in the case of half-wave mode."
newline
hexmask.long.word 0x10 0.--11. 1. "NUM_INIT_CMOD_12_RAIL_CYCLES,Duration of the coarse initialisation phase (e.g. connecting Cmod1 to vdda and Cmod2 to vssa in full-wave mode). Programmed in terms of clk_mod cycles."
line.long 0x14 "INIT_CTL2,Initialisation Control 2"
hexmask.long.word 0x14 16.--27. 1. "NUM_INIT_CMOD_34_SHORT_CYCLES,Duration of the coarse short phase (shorting Cmod3 and Cmod4 in full-wave mode). Programmed in terms of clk_mod cycles. Should be set to zero in the case of half-wave mode."
newline
hexmask.long.word 0x14 0.--11. 1. "NUM_INIT_CMOD_34_RAIL_CYCLES,Duration of the coarse initialisation phase (e.g. connecting Cmod3 to vdda and Cmod4 to vssa in full-wave mode). Programmed in terms of clk_mod cycles."
line.long 0x18 "INIT_CTL3,Initialisation Control 3"
bitfld.long 0x18 15. "INIT_MODE,Determines autonomous initialisation behaviour during INIT_CMOD." "0: Decode CMOD_SEL,1: C1CB = 1"
newline
bitfld.long 0x18 10.--11. "CMOD_SEL,Select which Cmod are used and the cycle thresholds to be used for coarse initialisation. Note this field affects which Cmod switches are autonomously initialised by hardware as well as influencing the cycle counters as per INIT_MODE." "0: Used for full-wave,1: Used for full-wave,2: Used for half-wave,3: Used for half-wave"
newline
bitfld.long 0x18 8.--9. "NUM_PRO_OFFSET_TRIPS,Number of comparator trips required to be observed in PRO_OFFSET before proceeding to dummy cycles." "0,1,2,3"
newline
hexmask.long.byte 0x18 0.--7. 1. "NUM_PRO_OFFSET_CYCLES,Maximum number of clk_mod cycles to be assigned for the PRO_OFFSET state. If NUM_PRO_OFFSET_TRIPS are observed before this timeout exit at that point."
line.long 0x1C "INIT_CTL4,Initialisation Control 4"
hexmask.long.word 0x1C 16.--25. 1. "NUM_PRO_WAIT_CYCLES,Number of clk_mod cycles to be run during PRO_WAIT."
newline
hexmask.long.byte 0x1C 0.--7. 1. "NUM_PRO_DUMMY_SUB_CONVS,Number of sub-conversions (dummy cycles) to be run during PRO_DUMMY."
line.long 0x20 "SENSE_DUTY_CTL,Sense Clock Duty Cycle Control"
bitfld.long 0x20 27. "PHASE_WIDTH_SEL,Select which phases the PHASE_WIDTH applies to:" "0: N/A,1: N/A"
newline
hexmask.long.word 0x20 16.--25. 1. "PHASE_SHIFT_CYCLES,Phase shift cycle control for ph0X and ph1X."
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hexmask.long.word 0x20 0.--11. 1. "PHASE_WIDTH,Control width (clk_mod cycles) of ph0 and ph2 OR ph1 and ph3. If set to zero Fs is divided equally between all phases. This field is only applicable when LFSR_MODE = DIRECT_CLOCK."
line.long 0x24 "SENSE_PERIOD_CTL,Sense Clock Period Control"
hexmask.long.byte 0x24 16.--19. 1. "LFSR_SCALE,Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This scaling is only applicable in spread spectrum mode."
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hexmask.long.word 0x24 0.--11. 1. "LFSR_POLY,Programmable polynomial to be used for the sense LFSR. For example (default):"
line.long 0x28 "FILTER_CTL,Filter Control"
bitfld.long 0x28 24. "FILTER_MODE,N/A" "0: Use the standard first order counter low pass..,1: Use CIC2 Filter. Advantage of CIC2 over CIC1 is.."
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bitfld.long 0x28 16. "BIT_FORMAT,Determines how the synchronised comparator output is interpreted by the filter pipeline." "0: Input values [0 +1],1: Input values [-1 +1]. In this scenario a value.."
group.long 0x30++0x7
line.long 0x0 "CCOMP_CDAC_CTL,Compensation CAPDAC Control"
bitfld.long 0x0 31. "EPILOGUE_EN,Control on whether Ccomp is active during EPILOGUE for final balancing in a conversion." "0: N/A,1: N/A"
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hexmask.long.byte 0x0 8.--15. 1. "SEL_CO_PRO_OFFSET,Select value for Compensation CAPDAC size during PRO_OFFSET until the first comparator trip is observed. Otherwise SEL_CO applies."
line.long 0x4 "DITHER_CDAC_CTL,Flatspot/Dither CAPDAC Switch Control"
hexmask.long.byte 0x4 16.--23. 1. "LFSR_POLY_FL,Dither/Flatspot CAPDAC LFSR polynomial. Uses same encoding as the spread spectrum polynomial LFSR_POLY. For example (default):"
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hexmask.long.byte 0x4 0.--7. 1. "SEL_FL,Select value for Dither/Flatspot CAPDAC size."
group.long 0x40++0x23
line.long 0x0 "CSW_CTL,Control Mux Switch Control"
hexmask.long 0x0 0.--31. 1. "CSW_FUNC_MODE,Select between SW_SEL_CSW[x] and SW_SEL_CSW_FUNC."
line.long 0x4 "SW_SEL_GPIO,GPIO Switch Control"
bitfld.long 0x4 24.--26. "SW_DSI_CSH_TANK,MUX select for dsi_csh_tank waveform." "0: N/A,1: N/A,2: chop == 1 ? ph0 : ph1,3: chop == 1 ? ph1 : ph3,4: N/A,?,?,?"
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bitfld.long 0x4 20.--22. "SW_DSI_CMOD,MUX select for dsi_cmod waveform." "0: N/A,1: N/A,2: chop == 1 ? ph1 : ph0,3: chop == 1 ? ph3 : ph1,4: N/A,?,?,?"
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bitfld.long 0x4 16. "SW_CSD_CHARGE,MUX select for csd_charge waveform." "0: N/A,1: N/A"
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bitfld.long 0x4 12.--13. "SW_CSD_POLARITY,MUX select for csd_polarity waveform." "0: N/A,1: N/A,2: N/A,?"
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bitfld.long 0x4 8. "SW_CSD_MUTUAL,MUX select for csd_mutual waveform." "0: N/A,1: N/A"
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bitfld.long 0x4 4.--6. "SW_CSD_SHIELD,MUX select for csd_shield waveform." "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,5: ph0 || [Fs2_ph1 && (ph1 || ph3)],6: N/A,?"
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bitfld.long 0x4 0.--2. "SW_CSD_SENSE,MUX select for csd_sense waveform." "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,5: N/A,6: N/A,?"
line.long 0x8 "SW_SEL_CDAC_RE,Reference CAPDAC Switch Control"
bitfld.long 0x8 20.--21. "SW_REBG,Reference CAPDAC bottom plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb)"
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bitfld.long 0x8 16.--17. "SW_REBV,Reference CAPDAC bottom plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb)"
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bitfld.long 0x8 12.--14. "SW_RETG,Reference CAPDAC top plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode,5: DFT mode,?,?"
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bitfld.long 0x8 8.--10. "SW_RETV,Reference CAPDAC top plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode,5: DFT mode,?,?"
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bitfld.long 0x8 4.--6. "SW_RECB,Reference CAPDAC to CSD Bus B Switch" "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_reffb) : sel = 11..,3: chop == 1 ? sel = 10 (clk_reffb) : sel = 11..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x8 0.--2. "SW_RETCA,Reference CAPDAC top plate to CSD Bus A Switch" "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_reffb) : sel = 11..,3: chop == 1 ? sel = 10 (clk_reffb) : sel = 11..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
line.long 0xC "SW_SEL_CDAC_CO,Compensation CAPDAC Switch Control"
bitfld.long 0xC 20.--21. "SW_COBG,Compensation CAPDAC bottom plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_comp),3: sel = 11 (!clk_comp)"
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bitfld.long 0xC 16.--17. "SW_COBV,Compensation CAPDAC bottom plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_comp),3: sel = 11 (!clk_comp)"
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bitfld.long 0xC 12.--14. "SW_COTG,Compensation CAPDAC top plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode,5: DFT mode,?,?"
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bitfld.long 0xC 8.--10. "SW_COTV,Compensation CAPDAC top plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode,5: DFT mode,?,?"
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bitfld.long 0xC 4.--6. "SW_COCB,Compensation CAPDAC to CSD Bus B Switch." "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_comp) : sel = 11..,3: chop == 1 ? sel = 10 (clk_comp) : sel = 11..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0xC 0.--2. "SW_COTCA,Compensation CAPDAC top plate to CSD Bus A Switch." "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_comp) : sel = 11..,3: chop == 1 ? sel = 10 (clk_comp) : sel = 11..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
line.long 0x10 "SW_SEL_CDAC_CF,Fine CAPDAC Switch Control"
bitfld.long 0x10 20.--21. "SW_CFBG,Fine CAPDAC bottom plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: FINE_MODE == REFERENCE ? sel = 10 (clk_reffb) :..,3: FINE_MODE == REFERENCE ? sel = 11 (!clk_reffb) :.."
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bitfld.long 0x10 16.--17. "SW_CFBV,Fine CAPDAC bottom plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: FINE_MODE == REFERENCE ? sel = 10 (clk_reffb) :..,3: FINE_MODE == REFERENCE ? sel = 11 (!clk_reffb) :.."
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bitfld.long 0x10 12.--14. "SW_CFTG,Fine CAPDAC top plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 [(FINE_MODE == REFERENCE) ? clk_reffb :..,3: sel = 11 [(FINE_MODE == REFERENCE) ? !clk_reffb..,4: DFT mode (ph0 ? sel = 01 : sel = 00),5: DFT mode (ph2 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x10 8.--10. "SW_CFTV,Fine CAPDAC top plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 [(FINE_MODE == REFERENCE) ? clk_reffb :..,3: sel = 11 [(FINE_MODE == REFERENCE) ? !clk_reffb..,4: DFT mode (ph0 ? sel = 01 : sel = 00),5: DFT mode (ph2 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x10 4.--6. "SW_CFTCB,Fine CAPDAC top plate to CSD Bus B Switch." "0: sel = 00,1: sel = 01,2: case({chop FINE_MODE}) {1 REFERENCE} : sel = 11..,3: case({chop FINE_MODE}) {1 REFERENCE} : sel = 10..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x10 0.--2. "SW_CFTCA,Fine CAPDAC top plate to CSD Bus A Switch." "0: sel = 00,1: sel = 01,2: case({chop FINE_MODE}) {1 REFERENCE} : sel = 11..,3: case({chop FINE_MODE}) {1 REFERENCE} : sel = 10..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
line.long 0x14 "SW_SEL_CMOD1,CMOD Switch Control 1"
bitfld.long 0x14 31. "ENABLED,CMOD1 enable." "0: N/A,1: N/A"
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bitfld.long 0x14 30. "REF_MODE,CMOD1 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD." "0: N/A,1: N/A"
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hexmask.long.byte 0x14 24.--27. 1. "SW_C1CG,CMOD1 to vssa_q Switch."
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hexmask.long.byte 0x14 16.--19. 1. "SW_C1CV,CMOD1 to vdda_q Switch."
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bitfld.long 0x14 12.--13. "SW_C1CC,CMOD1 to CSD Bus C Switch." "0: N/A,1: N/A,2: N/A,?"
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hexmask.long.byte 0x14 8.--11. 1. "SW_C1CB,CMOD1 to CSD Bus B Switch."
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hexmask.long.byte 0x14 0.--3. 1. "SW_C1CA,CMOD1 to CSD Bus A Switch."
line.long 0x18 "SW_SEL_CMOD2,CMOD Switch Control 2"
bitfld.long 0x18 31. "ENABLED,CMOD2 enable." "0: N/A,1: N/A"
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bitfld.long 0x18 30. "REF_MODE,CMOD2 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD." "0: N/A,1: N/A"
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hexmask.long.byte 0x18 24.--27. 1. "SW_C2CG,CMOD2 to vssa_q Switch."
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hexmask.long.byte 0x18 16.--19. 1. "SW_C2CV,CMOD2 to vdda_q Switch."
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bitfld.long 0x18 12.--13. "SW_C2CC,CMOD2 to CSD Bus C Switch." "0: N/A,1: N/A,2: N/A,?"
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hexmask.long.byte 0x18 8.--11. 1. "SW_C2CB,CMOD2 to CSD Bus B Switch."
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hexmask.long.byte 0x18 0.--3. 1. "SW_C2CA,CMOD2 to CSD Bus A Switch."
line.long 0x1C "SW_SEL_CMOD3,CMOD Switch Control 3"
bitfld.long 0x1C 31. "ENABLED,CMOD3 enable." "0: N/A,1: N/A"
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bitfld.long 0x1C 30. "REF_MODE,CMOD3 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD." "0: N/A,1: N/A"
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hexmask.long.byte 0x1C 24.--27. 1. "SW_C3CG,CMOD3 to vssa_q Switch."
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hexmask.long.byte 0x1C 16.--19. 1. "SW_C3CV,CMOD3 to vdda_q Switch."
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bitfld.long 0x1C 12.--13. "SW_C3CC,CMOD3 to CSD Bus C Switch." "0: N/A,1: N/A,2: N/A,?"
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hexmask.long.byte 0x1C 8.--11. 1. "SW_C3CB,CMOD3 to CSD Bus B Switch."
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hexmask.long.byte 0x1C 0.--3. 1. "SW_C3CA,CMOD3 to CSD Bus A Switch."
line.long 0x20 "SW_SEL_CMOD4,CMOD Switch Control 4"
bitfld.long 0x20 31. "ENABLED,CMOD4 enable." "0: N/A,1: N/A"
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bitfld.long 0x20 30. "REF_MODE,CMOD4 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD." "0: N/A,1: N/A"
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hexmask.long.byte 0x20 24.--27. 1. "SW_C4CG,CMOD4 to vssa_q Switch."
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hexmask.long.byte 0x20 16.--19. 1. "SW_C4CV,CMOD4 to vdda_q Switch."
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bitfld.long 0x20 12.--13. "SW_C4CC,CMOD4 to CSD Bus C Switch." "0: N/A,1: N/A,2: N/A,?"
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hexmask.long.byte 0x20 8.--11. 1. "SW_C4CB,CMOD4 to CSD Bus B Switch."
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hexmask.long.byte 0x20 0.--3. 1. "SW_C4CA,CMOD4 to CSD Bus A Switch."
group.long 0x70++0x3
line.long 0x0 "OBS_CTL,Observability Control"
hexmask.long.byte 0x0 24.--27. 1. "OBSERVE3,Selects the source for observe output signal 3:"
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hexmask.long.byte 0x0 16.--19. 1. "OBSERVE2,Selects the source for observe output signal 2:"
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hexmask.long.byte 0x0 8.--11. 1. "OBSERVE1,Selects the source for observe output signal 1:"
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hexmask.long.byte 0x0 0.--3. 1. "OBSERVE0,Selects the source for observe output signal 0:"
group.long 0x80++0x7
line.long 0x0 "WAKEUP_CTL,Wakeup Control"
bitfld.long 0x0 31. "ENABLED,If set then LP AoC FSM will operate when in DEEP_SLEEP. This also switches clk_hf -> clk_lf." "0: N/A,1: N/A"
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hexmask.long.word 0x0 0.--15. 1. "WAKEUP_TIMER,Timer interval between wakeup scans in LP-AoC mode. Assumes a 32kHz operating clock (clk_lf). Desired range is 1->2000ms."
line.long 0x4 "LP_AOC_CTL,LP-AoC Control"
hexmask.long.byte 0x4 24.--27. 1. "DEBOUNCE_THRESHOLD,Global threshold for successive TOUCH_THRESHOLD exceeds to warrant a full system wakeup."
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hexmask.long.byte 0x4 16.--23. 1. "BUCKET_STEP_SIZE,Global step size for SENSOR_BASELINE adjustment."
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hexmask.long.word 0x4 0.--15. 1. "BUCKET_THRESHOLD,Global threshold to control the per sensor SENSOR_BASELINE updates."
rgroup.long 0x100++0x13
line.long 0x0 "STATUS1,General Status Register 1"
hexmask.long.word 0x0 16.--31. 1. "RAW_COUNT_POS,Useful for determining component counts for positive and negative charge by subtracting from RAW_COUNT."
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hexmask.long.word 0x0 0.--15. 1. "RAW_COUNT,Live current raw counter. For debug/test purposes. In normal operation Firmware/DMA will typically read results from RESULT_FIFO_RD."
line.long 0x4 "STATUS2,General Status Register 2"
hexmask.long.word 0x4 0.--15. 1. "DEBUG_CONV_COUNT,Debug raw count for a particular conversion. Enabled only during a specified conversion of a sample (a specific chop phase)."
line.long 0x8 "STATUS3,General Status Register 3"
bitfld.long 0x8 28. "MSC_CMP_OUT,Output of main sensing comparator (synchronized). For debug/test purposes." "0,1"
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bitfld.long 0x8 24. "FS_CLOCK,Sense clock Fs control waveform. For debug/test purposes." "0,1"
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hexmask.long.byte 0x8 16.--19. 1. "SEQ_STATE,MSC Sequencer FSM state."
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hexmask.long.word 0x8 0.--15. 1. "NUM_SUB_CONVS,Number of sub-conversions remaining while in PRO_DUMMY and SUB_CONV."
line.long 0xC "RESULT_FIFO_STATUS,Result FIFO Status"
bitfld.long 0xC 31. "FIFO_OVERFLOW,Set if hardware attempts to write a RAW_COUNT (and associated metrics) to an already full result FIFO." "0,1"
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bitfld.long 0xC 30. "FIFO_UNDERFLOW,Hardware sets this field to '1' when reading from an empty FIFO (RESULT_FIFO_STATUS.USED is '0')." "0,1"
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hexmask.long.word 0xC 20.--29. 1. "RD_PTR,Result FIFO read pointer: FIFO location from which data is read via AHB."
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hexmask.long.word 0xC 10.--19. 1. "WR_PTR,Result FIFO write pointer: FIFO location at which a new data is written by the hardware."
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hexmask.long.word 0xC 0.--9. 1. "USED,Number of used/occupied entries in the result FIFO. When '0' the FIFO is empty."
line.long 0x10 "RESULT_FIFO_RD,Result FIFO Pointer"
hexmask.long.byte 0x10 24.--27. 1. "BAD_CONV_COUNT,Counter to indicate whether conversion of a sample is bad at the end of each chop phase. This is true if the comparator has not tripped by the end of EPILOGUE in a chop phase."
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bitfld.long 0x10 20.--22. "RESAMPLE_COUNT,Counter indicating number of attempted re-samples (via NUM_AUTO_RESAMPLE) for this raw count." "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 16. "OVERFLOW,RAW_COUNT overflow." "0,1"
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hexmask.long.word 0x10 0.--15. 1. "RAW_COUNT,FILTER_MODE = CIC1: Accumulated raw count for a sample."
group.long 0x170++0xB
line.long 0x0 "INTR,MSCv3 Interrupt Cause Register"
bitfld.long 0x0 31. "FIFO_OVERFLOW,Result FIFO overflow condition." "0,1"
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bitfld.long 0x0 30. "FIFO_UNDERFLOW,Result FIFO underflow condition." "0,1"
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bitfld.long 0x0 24. "CONFIG_REQ,Request for scan configuration and scan start. The Sequencer FSM is entering WAIT_SCAN_START when this interrupt is raised. This interrupt can be used in CPU mode in a multi-channel scenario with external frame start to indicate to firmware.." "0,1"
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bitfld.long 0x0 20. "CIC2_ERROR,CIC2 error detected. This bit is set at the end of a sample if the number of valid CIC2 sub-samples is not one of [1 2 4 8 16]. At the end of a CIC2 sample RESULT_FIFO_RD.RAW_COUNT contains the average of the valid sub-samples observed during.." "?,1: no division"
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bitfld.long 0x0 16. "FRAME,A single frame is complete." "0,1"
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bitfld.long 0x0 12. "INIT,Coarse initialisation complete. For debug purposes." "0,1"
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bitfld.long 0x0 8. "SCAN,A single scan is complete." "0,1"
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bitfld.long 0x0 4. "SAMPLE,A single sample is complete. For debug purposes." "0,1"
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bitfld.long 0x0 0. "SUB_SAMPLE,A valid CIC2 sub-sample is complete. To facilitate firmware averaging of sub-samples. For debug purposes." "0,1"
line.long 0x4 "INTR_SET,MSCv3 Interrupt Set Register"
bitfld.long 0x4 31. "FIFO_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 30. "FIFO_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 24. "CONFIG_REQ,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 20. "CIC2_ERROR,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 16. "FRAME,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 12. "INIT,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 8. "SCAN,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 4. "SAMPLE,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 0. "SUB_SAMPLE,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
line.long 0x8 "INTR_MASK,MSCv3 Interrupt Mask Register"
bitfld.long 0x8 31. "FIFO_OVERFLOW,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 30. "FIFO_UNDERFLOW,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 24. "CONFIG_REQ,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 20. "CIC2_ERROR,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 16. "FRAME,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 12. "INIT,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 8. "SCAN,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 4. "SAMPLE,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 0. "SUB_SAMPLE,Mask bit for corresponding bit in interrupt cause register." "0,1"
rgroup.long 0x17C++0x3
line.long 0x0 "INTR_MASKED,MSCv3 Interrupt Masked Register"
bitfld.long 0x0 31. "FIFO_OVERFLOW,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 30. "FIFO_UNDERFLOW,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 24. "CONFIG_REQ,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 20. "CIC2_ERROR,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 16. "FRAME,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 12. "INIT,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 8. "SCAN,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 4. "SAMPLE,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 0. "SUB_SAMPLE,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
group.long 0x180++0xB
line.long 0x0 "INTR_LP,Low Power Interrupt Cause Register"
bitfld.long 0x0 0. "WAKEUP,LP-AoC has detected wakeup." "0,1"
line.long 0x4 "INTR_LP_SET,Low Power Interrupt Set Register"
bitfld.long 0x4 0. "WAKEUP,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
line.long 0x8 "INTR_LP_MASK,Low Power Interrupt Mask Register"
bitfld.long 0x8 0. "WAKEUP,Mask bit for corresponding bit in interrupt cause register." "0,1"
rgroup.long 0x18C++0x3
line.long 0x0 "INTR_LP_MASKED,Low Power Interrupt Masked Register"
bitfld.long 0x0 0. "WAKEUP,Logical AND of corresponding INTR_LP and INTR_LP_MASK bits." "0,1"
group.long 0x190++0x3
line.long 0x0 "FRAME_CMD,Frame Command Register"
bitfld.long 0x0 0. "START_FRAME,Start the MSCv3 sequencer frame process. Note that a rising edge on this bit also creates a 2x cycle clk_msc pulse on the msc_ext_frm_start_out signal. The corresponding msc_ext_frm_start_out_en is controlled by CTL.ENABLED." "0,1"
group.long 0x198++0x3
line.long 0x0 "WAKEUP_CMD,Wakeup Command Register"
bitfld.long 0x0 16. "ABORT,Abort the LP-AoC when in WAIT_FOR_DS state." "0,1"
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bitfld.long 0x0 0. "WAIT_FOR_DS,Set by firmware to prime the LP-AoC FSM to be ready to detect entry to DEEP_SLEEP. When detected hardware clears the bit down and the LP-AoC FSM periodically scans all valid sensor configurations programmed in the sensor configuration.." "0,1"
group.long 0x200++0x23
line.long 0x0 "SNS_STRUCT_CTL,Sensor Struct Control"
hexmask.long.byte 0x0 8.--11. 1. "LENGTH,Number of SNS_* registers from OFFSET for current sensor configuration in local IP storage. Used by LOAD_CONFIG state in Sequencer FSM. Applicable only when CONFIG_NR > 0."
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hexmask.long.byte 0x0 0.--3. 1. "OFFSET,Starting offset into SNS_* registers of current sensor configuration in local IP storage. Used by LOAD_CONFIG state in Sequencer FSM. Applicable only when CONFIG_NR > 0."
line.long 0x4 "SNS_LP_AOC_SENSOR_CTL1,LP-AoC Sensor Control 1"
hexmask.long.word 0x4 16.--31. 1. "N_BUCKET,Per sensor bucket for baseline <= raw count adjustments."
newline
hexmask.long.word 0x4 0.--15. 1. "P_BUCKET,Per sensor bucket for baseline greater than raw count adjustments."
line.long 0x8 "SNS_LP_AOC_SENSOR_CTL2,LP-AoC Sensor Control 2"
hexmask.long.word 0x8 16.--27. 1. "TOUCH_THRESHOLD,Per sensor threshold for |baseline - rawCount| to warrant a single touch detect."
newline
hexmask.long.word 0x8 0.--15. 1. "SENSOR_BASELINE,Per sensor baseline value."
line.long 0xC "SNS_SW_SEL_CSW_MASK2,Control MUX Function Select Mask 2"
hexmask.long 0xC 0.--31. 1. "FUNC_MASK,{SNS_SW_SEL_CSW_MASK2.FUNC_MASK[x] "
line.long 0x10 "SNS_SW_SEL_CSW_MASK1,Control MUX Function Select Mask 1"
hexmask.long 0x10 0.--31. 1. "FUNC_MASK,{SNS_SW_SEL_CSW_MASK2.FUNC_MASK[x] "
line.long 0x14 "SNS_SW_SEL_CSW_MASK0,Control MUX Function Select Mask 0"
hexmask.long 0x14 0.--31. 1. "FUNC_MASK,{SNS_SW_SEL_CSW_MASK2.FUNC_MASK[x] "
line.long 0x18 "SNS_SCAN_CTL,Sensor Scan Control"
bitfld.long 0x18 31. "INIT_BYPASS,Coarse initialisation bypass control. Applies to CMOD_SEL selected Cmod." "0: N/A,1: N/A"
newline
bitfld.long 0x18 28.--30. "NUM_CONV,Number of conversions (minus 1) per scanned sample. This is required for chopping (chop polarity is updated per conversion)." "0: N/A,1: N/A,?,3: N/A,?,?,?,7: N/A"
newline
hexmask.long.word 0x18 16.--27. 1. "COMP_DIV,The ratio (minus 1) of clk_comp::clk_mod."
newline
hexmask.long.word 0x18 0.--15. 1. "NUM_SUB_CONVS,Number of sub-conversions (minus 1) in a conversion."
line.long 0x1C "SNS_CDAC_CTL,Sensor CAPDAC Control"
bitfld.long 0x1C 28. "LFSR_SCALE_TYPE_FL,Flatspot/Dither CAPDAC shift direction." "0: N/A,1: N/A"
newline
bitfld.long 0x1C 24.--26. "LFSR_SCALE_FL,Shift the magnitude portion of the Flatspot/Dither CAPDAC LFSR output code left or right by LSFR_SCALE_FL bits. Direction of shift controlled by LFSR_SCALE_TYPE_FL." "?,?,?,?,?,?,6: bit polynomial,7: bit magnitude"
newline
bitfld.long 0x1C 23. "FL_EN,Dither/Flatspot LFSR enable control." "0: N/A,1: N/A"
newline
bitfld.long 0x1C 22. "CLOCK_REF_RATE,Used to select clk_mod or clk_mod/2 to as clk_ref. This clock is gated depending on the synchronised comparator to generate the gated feedback clock (clk_reffb) to the Reference CAPDAC." "0: N/A,1: N/A"
newline
bitfld.long 0x1C 21. "FINE_MODE,Operational mode for Fine CAPDAC" "0: N/A,1: N/A"
newline
hexmask.long.byte 0x1C 16.--20. 1. "SEL_CF,Select value for Fine CAPDAC size."
newline
hexmask.long.byte 0x1C 8.--15. 1. "SEL_CO,Select value for Compensation CAPDAC size."
newline
hexmask.long.byte 0x1C 0.--7. 1. "SEL_RE,Select value for Reference CAPDAC size."
line.long 0x20 "SNS_CTL,Sense Control and Command Register"
bitfld.long 0x20 30.--31. "LFSR_BITS,Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period (spread spectrum mode)." "0: Use 2 bits: range = [-2 1],1: Use 3 bits: range = [-4 3],2: Use 4 bits: range = [-8 7],3: Use 5 bits: range = [-16 15] (default)"
newline
bitfld.long 0x20 28.--29. "LFSR_MODE,Mode for generating the sense clock." "0: N/A,1: N/A,2: N/A,?"
newline
hexmask.long.word 0x20 16.--27. 1. "SENSE_DIV,The length (minus 1) of the sense modulation 'clock' period in clk_mod cycles (frequency = Fs). SENSE_DIV + 1 = sense_ratio."
newline
hexmask.long.byte 0x20 8.--15. 1. "DECIM_RATE,Sets the decimation rate for the sinc^2 filter (CIC2). Typically referred to as N. Note N = DECIM_RATE + 1. Only applies when FILTER_CTL.FILTER_MODE = CIC2 and irrelevant for CIC1 mode (no effect in this mode)."
newline
bitfld.long 0x20 6.--7. "SENSE_MODE_SEL,Sense mode register structure selection. This field allows quick change between registers that influence sense mode. This register selects which structure is currently 'live' and used by the IP." "0: Use MODE_STRUCT[0].,1: Use MODE_STRUCT[1].,2: Use MODE_STRUCT[2].,3: Use MODE_STRUCT[3]."
newline
bitfld.long 0x20 4.--5. "MULTI_CH_MODE,Multi channel mode configuration. Determines whether consensus mechanism is engaged to ensure channels scan in lockstep." "0: N/A,1: N/A,2: N/A,?"
newline
bitfld.long 0x20 2. "LAST,Indicator that current sensor configuration is the last sensor in the frame." "0,1"
newline
bitfld.long 0x20 1. "VALID,Indicator of sensor configuration validity." "0,1"
newline
bitfld.long 0x20 0. "START_SCAN,Start the MSCv3 sequencer scan process. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when all NUM_SAMPLES for this scan have been accumulated or if the sequencer is reset." "0,1"
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x300)++0x3
line.long 0x0 "SW_SEL_CSW[$1],Control Switch MUX Switch Control"
bitfld.long 0x0 31. "ENABLED,Control MUX Sensor N enable." "0: N/A,1: N/A"
newline
bitfld.long 0x0 30. "REF_MODE,Control MUX Sensor N is used as a reference." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x0 24.--27. 1. "SW_SNCG,Control MUX Sensor N to vssa_q Switch."
newline
hexmask.long.byte 0x0 16.--19. 1. "SW_SNCV,Control MUX Sensor N to vdda_q Switch."
newline
bitfld.long 0x0 12.--13. "SW_SNCC,Control MUX Sensor N to CSD Bus C Switch." "0: N/A,1: N/A,2: N/A,?"
newline
hexmask.long.byte 0x0 8.--11. 1. "SW_SNCB,Control MUX Sensor N to CSD Bus B Switch."
newline
hexmask.long.byte 0x0 0.--3. 1. "SW_SNCA,Control MUX Sensor N to CSD Bus A Switch."
repeat.end
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x400)++0x3
line.long 0x0 "SW_SEL_CSW_FUNC[$1],Control Switch MUX Switch Control Global Functions"
bitfld.long 0x0 31. "ENABLED,Control MUX Sensor enable." "0: N/A,1: N/A"
newline
bitfld.long 0x0 30. "REF_MODE,Control MUX Sensor is used as a reference." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x0 24.--27. 1. "SW_SNCG,Control MUX Sensor to vssa_q Switch."
newline
hexmask.long.byte 0x0 16.--19. 1. "SW_SNCV,Control MUX Sensor to vdda_q Switch."
newline
bitfld.long 0x0 12.--13. "SW_SNCC,Control MUX Sensor to CSD Bus C Switch." "0: N/A,1: N/A,2: N/A,?"
newline
hexmask.long.byte 0x0 8.--11. 1. "SW_SNCB,Control MUX Sensor to CSD Bus B Switch."
newline
hexmask.long.byte 0x0 0.--3. 1. "SW_SNCA,Control MUX Sensor to CSD Bus A Switch."
repeat.end
repeat 3. (list 0x0 0x1 0x2)(list ad:0x402A0500 ad:0x402A0520 ad:0x402A0540)
tree "MODE[$1]"
base $2
group.long ($2)++0x13
line.long 0x0 "SENSE_DUTY_CTL,Sense Clock Duty Cycle Control"
bitfld.long 0x0 28. "PHASE_MODE_SEL,Select 4-phase or 2-phase mode." "0: N/A,1: N/A"
newline
bitfld.long 0x0 24. "PHASE_SHIFT_EN,Enable phase shift logic that generates the Ph0X and Ph1X waveforms. Used for inductive and impedance sensing." "0: N/A,1: N/A"
newline
bitfld.long 0x0 10. "PHX_GAP_2CYCLE_EN,If set applies a two cycle gap on ph0X/ph1X if the corresponding PHASE_GAP_*_EN is set." "0: N/A,1: N/A"
newline
bitfld.long 0x0 9. "PHASE_GAP_PH1X_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph1x." "0: No gap,1: N/A"
newline
bitfld.long 0x0 8. "PHASE_GAP_PH0X_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph0x." "0: No gap,1: N/A"
newline
bitfld.long 0x0 6. "PH_GAP_2CYCLE_EN,If set applies a two cycle gap on ph0/ph1/ph2/ph3/Fs2_ph0/Fs2_ph1 if the corresponding PHASE_GAP_*_EN is set." "0: N/A,1: N/A"
newline
bitfld.long 0x0 5. "PHASE_GAP_FS2_PH1_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of Fs2_ph0." "0: No gap,1: N/A"
newline
bitfld.long 0x0 4. "PHASE_GAP_FS2_PH0_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of Fs2_ph0." "0: No gap,1: N/A"
newline
bitfld.long 0x0 3. "PHASE_GAP_PH3_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph3." "0: No gap,1: N/A"
newline
bitfld.long 0x0 2. "PHASE_GAP_PH2_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph2." "0: No gap,1: N/A"
newline
bitfld.long 0x0 1. "PHASE_GAP_PH1_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph1." "0: No gap,1: N/A"
newline
bitfld.long 0x0 0. "PHASE_GAP_PH0_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph0." "0: No gap,1: N/A"
line.long 0x4 "SW_SEL_CDAC_FL,Flatspot/Dither CAPDAC Switch Control"
bitfld.long 0x4 31. "ACTIVATION_MODE,Activation event for Dither/Flatspot LFSR." "0: N/A,1: N/A"
newline
bitfld.long 0x4 20.--22. "SW_FLBG,Flatspot/Dither CAPDAC bottom plate to vssa_q Switch." "0: N/A,1: N/A,2: N/A,3: N/A,4: [(msb^ph1)^(ph0||ph1)] & [ph0||ph1],5: (![(msb^ph1)^(ph0||ph1)]) & [ph0||ph1],6: [(msb^(ph2||ph3))^(ph0||ph2)] &..,7: (![(msb^(ph2||ph3))^(ph0||ph2)]) &.."
newline
bitfld.long 0x4 16.--18. "SW_FLBV,Flatspot/Dither CAPDAC bottom plate to vdda_q Switch." "0: N/A,1: N/A,2: N/A,3: N/A,4: [(msb^ph1)^(ph0||ph1)] & [ph0||ph1],5: (![(msb^ph1)^(ph0||ph1)]) & [ph0||ph1],6: [(msb^(ph2||ph3))^(ph0||ph2)] &..,7: (![(msb^(ph2||ph3))^(ph0||ph2)]) &.."
newline
bitfld.long 0x4 12.--14. "SW_FLTG,Flatspot/Dither CAPDAC top plate to vssa_q Switch." "0: N/A,1: N/A,2: N/A,3: N/A,4: DFT mode,5: DFT mode,?,?"
newline
bitfld.long 0x4 8.--9. "SW_FLTV,Flatspot/Dither CAPDAC top plate to vdda_q Switch." "0: N/A,1: N/A,2: DFT mode,3: DFT mode"
newline
bitfld.long 0x4 4.--6. "SW_FLCB,Flatspot/Dither CAPDAC to CSD Bus B Switch" "0: N/A,1: N/A,2: chop == 1 ? ph1 : ph3,3: chop == 1 ? ph3 : ph1,4: chop == 1 ? ph0 : ph1,5: chop == 1 ? ph1 : ph0,?,?"
newline
bitfld.long 0x4 0.--2. "SW_FLTCA,Flatspot/Dither CAPDAC top plate to CSD Bus A Switch" "0: N/A,1: N/A,2: chop == 1 ? ph1 : ph3,3: chop == 1 ? ph3 : ph1,4: chop == 1 ? ph0 : ph1,5: chop == 1 ? ph1 : ph0,?,?"
line.long 0x8 "SW_SEL_TOP,Top Level Switch Control"
bitfld.long 0x8 31. "MBF,AMUXBUSB to Filter Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x8 30. "RMF,Ratiometric Reference to Filter Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x8 29. "BGRF,Bandgap Reference to Filter Switch" "0: N/A,1: N/A"
newline
hexmask.long.byte 0x8 24.--27. 1. "SHG,COAX Shield to vssa_q Switch"
newline
hexmask.long.byte 0x8 20.--23. 1. "SHV,COAX Shield to vdda_q Switch"
newline
bitfld.long 0x8 18.--19. "SOSH,COAX Shield to Shield Buffer Output Switch" "0: N/A,1: N/A,2: N/A,?"
newline
bitfld.long 0x8 16.--17. "BYB,AMUXBUS B to CSD Bus B Switch." "0: sel = 00,1: sel = 01,2: sel = 10,3: sel = 11"
newline
bitfld.long 0x8 15. "AYB_EN,AMUXBUS A to CSD Bus B Switch. Controls first part of AYB switch (AYB_EN<0> on the hardIP)." "0: on the hardIP),1: Closes first part of AYB switch and disables.."
newline
bitfld.long 0x8 12.--14. "AYB_CTL,AMUXBUS A to CSD Bus B Switch. Controls second part of AYB switch (AYB_EN<1> on hardIP)." "0: Opens second part of AYB switch. Enables..,1: on hardIP),2: chop == 0 ? ph1 : ph0,3: chop == 0 ? ph3 : ph1,4: chop == 0 ? ph1 : ph3,5: chop == 0 ? ph0 : ph1,6: N/A,7: N/A"
newline
bitfld.long 0x8 11. "AYA_EN,AMUXBUS A to CSD Bus A Switch. Controls the first part of AYA switch (AYA_EN<0> on the hardIP)." "0: on the hardIP),1: Closes first part of AYA switch and disables.."
newline
bitfld.long 0x8 8.--10. "AYA_CTL,AMUXBUS A to CSD Bus A Switch. Controls second part of AYA switch (AYA_EN<1> on hardIP)." "0: Opens second part of AYA switch. Enables..,1: on hardIP),2: chop == 0 ? ph0 : ph1,3: chop == 0 ? ph1 : ph3,4: chop == 0 ? ph3 : ph1,5: chop == 0 ? ph1 : ph0,6: N/A,7: N/A"
newline
bitfld.long 0x8 6. "MBCC,AMUXBUSB to CSD Bus C Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x8 4. "CBCC,CSD Bus B to CSD Bus C Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x8 2. "CACC,CSD Bus A to CSD Bus C Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x8 0. "CACB,CSD Bus A to CSD Bus B Switch." "0: N/A,1: N/A"
line.long 0xC "SW_SEL_COMP,MSC Comparator Switch Control"
bitfld.long 0xC 31. "HALF_WAVE_EN,Enables halfwave mode in the comparator where reference is vdda_q." "0: N/A,1: N/A"
newline
bitfld.long 0xC 22. "CMF,Comparator Minus Terminal to Reference Filter Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 20. "CMG,Comparator Minus Terminal to vssa_q Switch." "0: N/A,1: N/A"
newline
bitfld.long 0xC 18. "CMV,Comparator Minus Terminal to vdda_q Switch." "0: N/A,1: N/A"
newline
bitfld.long 0xC 16. "CMCS4,Comparator Minus Terminal to CMOD4 Sense Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 14. "CMCS2,Comparator Minus Terminal to CMOD2 Sense Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 12. "CPF,Comparator Plus Terminal to Reference Filter Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 10. "CMCB,Comparator Minus Terminal to CSD Bus B Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 8. "CPCB,Comparator Plus Terminal to CSD Bus B Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 6. "CPCA,Comparator Plus Terminal to CSD Bus A Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 4. "CPMA,Comparator Plus Terminal to AMUXBUSA Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 2. "CPCS3,Comparator Plus Terminal to CMOD3 Sense Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 0. "CPCS1,Comparator Plus Terminal to CMOD1 Sense Switch" "0: N/A,1: N/A"
line.long 0x10 "SW_SEL_SH,Shielding Switch Control"
bitfld.long 0x10 31. "BUF_EN,Enable the shield buffer." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x10 24.--27. 1. "BUF_SEL,Selects value of compensation capacitance in shield buffer."
newline
bitfld.long 0x10 18. "CCSO,CSD Bus C to Shield OpAmp Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 16. "FSP,Reference Filter to Shield Positive Terminal Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 14. "SPCS3,Shield Positive Terminal to CMOD3 Sense Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 12. "SPCS1,Shield Positive Terminal to CMOD1 Sense Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 10. "CBSO,CSD Bus B to Shield OpAmp Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 8. "SOMB,Shield OpAmp to AMUXBUSB Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 6. "C3SH,cmod3_4_sh to sh Switch (Drives cmod3_4_sh with shield signal)" "0: N/A,1: N/A"
newline
bitfld.long 0x10 4. "C3SHG,cmod3_4_sh to vssa Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 2. "C1SH,cmod1_2_sh to sh Switch (Drives cmod1_2_sh with shield signal)" "0: N/A,1: N/A"
newline
bitfld.long 0x10 0. "C1SHG,cmod1_2_sh to vssa Switch" "0: N/A,1: N/A"
tree.end
repeat.end
base ad:0x402A0000
repeat 4096. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x1000)++0x3
line.long 0x0 "SENSOR_DATA[$1],Sensor Configuration Storage"
hexmask.long 0x0 0.--31. 1. "DATA,Local IP storage to support per-sensor configuration for AS-MS mode. Storage requirement in bytes is CONFIG_NR * (number of per sensor registers) * 4. The per sensor registers all have the prefix SNS_*."
repeat.end
group.long 0xFF00++0x3
line.long 0x0 "TRIM_CTL,Trim Control"
bitfld.long 0x0 5. "TRIM_POLARITY,Controls polarity of comparator offset trim." "0,1"
newline
bitfld.long 0x0 4. "TRIM_EN,Enables comparator offset trim." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x0 0.--3. 1. "TRIM_IN,Controls magnitude of comparator offset trim."
tree.end
tree.end
tree "PASS (Programmable Analog Sub System Memory Mapped IO)"
base ad:0x403F0000
rgroup.long 0x0++0x3
line.long 0x0 "INTR_CAUSE,Interrupt cause register"
bitfld.long 0x0 3. "CTB3_INT,CTB3 interrupt pending" "0,1"
bitfld.long 0x0 2. "CTB2_INT,CTB2 interrupt pending" "0,1"
bitfld.long 0x0 1. "CTB1_INT,CTB1 interrupt pending" "0,1"
newline
bitfld.long 0x0 0. "CTB0_INT,CTB0 interrupt pending" "0,1"
group.long 0x30++0x3
line.long 0x0 "DFT_CTRL,DFT control register"
bitfld.long 0x0 0. "DSAB_ADFT_RES_EN,Close the switch to connect the DSAB ADFT resistor to the AMUXBUS" "0,1"
group.long 0x108++0x3
line.long 0x0 "PASS_CTRL,PASS Control"
hexmask.long.byte 0x0 8.--15. 1. "RMB_BITS,Risk mitigation bits"
bitfld.long 0x0 1. "PMPCLK_SRC,- 0: Pump clk is clk_hf" "0: Pump clk is clk_hf,1: Pump clk is direct from SRSS"
bitfld.long 0x0 0. "PMPCLK_BYP,- 0: Pump clk is clk_hf/2" "0: Pump clk is clk_hf/2,1: Pump clk is selected from PMPCLK_SRC"
tree "DSAB (DSAB configuration)"
base ad:0x403F0E00
group.long 0x0++0x7
line.long 0x0 "DSAB_CTRL,global DSAB control"
bitfld.long 0x0 31. "ENABLED,This field (along with SEL_OUT and REF_SWAP_EN) provides bitwise selection of the current sources that drive the DSAB ZTC and PTAT outputs." "0,1"
bitfld.long 0x0 28. "STARTUP_RM,Risk mitigation control" "?,1: Force start the startup circuit"
bitfld.long 0x0 24. "BYPASS_MODE_EN,0 - DSAB PTAT generator is powered from DSAB regulator: VDDA must be at least 2.4V" "0: DSAB PTAT generator is powered from DSAB..,1: DSAB PTAT generator is pwoered directly from.."
newline
hexmask.long.byte 0x0 16.--19. 1. "REF_SWAP_EN,This field (along with SEL_OUT and ENABLED) provides bitwise selection of the current sources that drive the DSAB ZTC and PTAT outputs."
hexmask.long.byte 0x0 8.--11. 1. "SEL_OUT,N/A"
hexmask.long.byte 0x0 0.--5. 1. "CURRENT_SEL,DSAB DAC control field"
line.long 0x4 "DSAB_DFT,DFT bits"
hexmask.long.byte 0x4 0.--3. 1. "EN_DFT,- 0: DSAB DFT disabled"
tree.end
base ad:0x403F0000
group.long 0xF00++0x3
newline
line.long 0x0 "DSAB_TRIM,DSAB Trim bits"
bitfld.long 0x0 4.--5. "DSAB_RMB_BITS,Risk mitigation bits" "0,1,2,3"
hexmask.long.byte 0x0 0.--3. 1. "IBIAS_TRIM,1111=lowest 0000=highest"
tree.end
tree "PERI (Peripheral Interconnect)"
base ad:0x40010000
group.long 0x0++0x3
line.long 0x0 "DIV_CMD,Divider command register"
bitfld.long 0x0 31. "ENABLE,Clock divider enable command (mutually exclusive with DISABLE). Typically SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled its integer and.." "0: Disable the divider using the DIV_CMD,1: Configure the divider's DIV_XXX_CTL register"
bitfld.long 0x0 30. "DISABLE,Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'." "0,1"
bitfld.long 0x0 14.--15. "PA_SEL_TYPE,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:" "0,1,2,3"
hexmask.long.byte 0x0 8.--13. 1. "PA_SEL_DIV,(PA_SEL_TYPE PA_SEL_DIV) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other even when they are.."
bitfld.long 0x0 6.--7. "SEL_TYPE,Specifies the divider type of the divider on which the command is performed:" "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--5. 1. "SEL_DIV,(SEL_TYPE SEL_DIV) specifies the divider on which the command (DISABLE/ENABLE) is performed."
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x100)++0x3
line.long 0x0 "PCLK_CTL[$1],Programmable clock control register"
bitfld.long 0x0 6.--7. "SEL_TYPE,Specifies divider type:" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "SEL_DIV,Specifies one of the dividers of the divider type specified by SEL_TYPE."
repeat.end
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x200)++0x3
line.long 0x0 "DIV_8_CTL[$1],Divider control register (for 8.0 divider)"
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]. Note: this type of divider does NOT allow for a fractional division."
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
repeat.end
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x300)++0x3
line.long 0x0 "DIV_16_CTL[$1],Divider control register (for 16.0 divider)"
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: this type of divider does NOT allow for a fractional division."
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
repeat.end
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x400)++0x3
line.long 0x0 "DIV_16_5_CTL[$1],Divider control register (for 16.5 divider)"
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: combined with fractional division this divider type allows for a division in the range [1 65 536 31/32] in 1/32 increments."
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods."
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
repeat.end
repeat 63. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x500)++0x3
line.long 0x0 "DIV_24_5_CTL[$1],Divider control register (for 24.5 divider)"
hexmask.long.tbyte 0x0 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1 16 777 216]. Note: combined with fractional division this divider type allows for a division in the range [1 16 777 216 31/32] in 1/32 increments."
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods."
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
repeat.end
group.long 0x600++0x3
line.long 0x0 "TR_CTL,Trigger control register"
bitfld.long 0x0 31. "TR_ACT,SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL and TR_OUT for TR_COUNT cycles. HW sets this field to '0' when the cycle counter is decremented to '0'. Note: a TR_COUNT value of 255 is a special case and.." "0,1"
bitfld.long 0x0 30. "TR_OUT,Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger will result in activation of all output triggers that have the specific input trigger selected.." "0,1"
hexmask.long.byte 0x0 16.--23. 1. "TR_COUNT,Amount of cycles a specific trigger is activated. During activation (TR_ACT is '1') HW decrements this field to '0' using a cycle counter. During activation SW should not modify this register field. A value of 255 is a special case: HW does.."
hexmask.long.byte 0x0 8.--11. 1. "TR_GROUP,Specifies the trigger group."
hexmask.long.byte 0x0 0.--6. 1. "TR_SEL,Specifies the activated trigger when TR_ACT is '1'. TR_OUT specifies whether the activated trigger is an input trigger or output trigger to the trigger multiplexer. During activation (TR_ACT is '1') SW should not modify this register field. If.."
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x40012000 ad:0x40012200 ad:0x40012400 ad:0x40012600)
tree "TR_GROUP[$1]"
base $2
repeat 128. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "TR_OUT_CTL[$1],Trigger control register"
hexmask.long.byte 0x0 0.--6. 1. "SEL,Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default.."
repeat.end
tree.end
repeat.end
tree.end
tree "PRGIO (Programmable IO)"
base ad:0x40050000
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40050000 ad:0x40050100 ad:0x40050200)
tree "PRT[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CTL,Control register"
bitfld.long 0x0 31. "ENABLED,Enable for programmable IO. Should only be set to '1' when the programmable IO is completely configured:" "0,1"
bitfld.long 0x0 25. "PIPELINE_EN,Enable for pipeline register:" "0,1"
bitfld.long 0x0 24. "HLD_OVR,IO cell hold override functionality. In DeepSleep and Hibernate power modes the HSIOM holds the IO cell output and output enable signals if Active functionality is connected to the IO pads. This is undesirable if the PRGIO is supposed to deliver.." "0,1"
hexmask.long.byte 0x0 8.--12. 1. "CLOCK_SRC,Clock ('clk_fabric') and reset ('rst_fabric_n') source selection:"
hexmask.long.byte 0x0 0.--7. 1. "BYPASS,Bypass of the programmable IO one bit for each IO pin: BYPASS[i] is for IO pin i. When ENABLED is '1' this field is used. When ENABLED is '0' this field is NOT used and PRGIO is always bypassed."
group.long ($2+0x10)++0x3
line.long 0x0 "SYNC_CTL,Synchronization control register"
hexmask.long.byte 0x0 8.--15. 1. "CHIP_SYNC_EN,Synchronization of the chip input signals to 'clk_fabric' one bit for each input: CHIP_SYNC_EN[i] is for input i."
hexmask.long.byte 0x0 0.--7. 1. "IO_SYNC_EN,Synchronization of the IO pin input signals to 'clk_fabric' one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i."
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x20)++0x3
line.long 0x0 "LUT_SEL[$1],LUT component input selection"
hexmask.long.byte 0x0 16.--19. 1. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection. Encoding is the same as for LUT_TR1_SEL."
hexmask.long.byte 0x0 8.--11. 1. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection:"
hexmask.long.byte 0x0 0.--3. 1. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection:"
repeat.end
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x40)++0x3
line.long 0x0 "LUT_CTL[$1],LUT component control register"
bitfld.long 0x0 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation:" "0,1,2,3"
hexmask.long.byte 0x0 0.--7. 1. "LUT,LUT configuration. Depending on the LUT opcode LUT_OPC the internal state lut_reg (captured in a flip-flop) and the LUT input signals tr0_in tr1_in tr2_in the LUT configuration is used to determine the LUT output signal and the next sequential.."
repeat.end
group.long ($2+0xC0)++0x7
line.long 0x0 "DU_SEL,Data unit component input selection"
bitfld.long 0x0 28.--29. "DU_DATA1_SEL,Data unit input data 'data1_in' source selection. Encoding is the same as for DU_DATA0_SEL." "0,1,2,3"
bitfld.long 0x0 24.--25. "DU_DATA0_SEL,Data unit input data 'data0_in' source selection:" "0,1,2,3"
hexmask.long.byte 0x0 16.--19. 1. "DU_TR2_SEL,Data unit input signal 'tr2_in' source selection. Encoding is the same as for DU_TR0_SEL."
hexmask.long.byte 0x0 8.--11. 1. "DU_TR1_SEL,Data unit input signal 'tr1_in' source selection. Encoding is the same as for DU_TR0_SEL."
hexmask.long.byte 0x0 0.--3. 1. "DU_TR0_SEL,Data unit input signal 'tr0_in' source selection:"
line.long 0x4 "DU_CTL,Data unit component control register"
hexmask.long.byte 0x4 8.--11. 1. "DU_OPC,Data unit opcode specifies the data unit operation:"
bitfld.long 0x4 0.--2. "DU_SIZE,Size/width of the data unit data operands (in bits) is DU_SIZE+1. E.g. if DU_SIZE is 7 the width is 8 bits." "0,1,2,3,4,5,6,7"
group.long ($2+0xF0)++0x3
line.long 0x0 "DATA,Data register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data unit input data source."
tree.end
repeat.end
tree.end
tree "SAR (SAR ADC)"
base ad:0x403A0000
group.long 0x0++0x7
line.long 0x0 "CTRL,Analog control register."
bitfld.long 0x0 31. "ENABLED,Before enabling always make sure the SAR is idle (STATUS.BUSY==0)" "0: SAR IP disabled,1: SAR IP enabled"
newline
bitfld.long 0x0 30. "SWITCH_DISABLE,Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control)" "0: Normal mode,1: Switches disabled"
newline
bitfld.long 0x0 29. "DSI_MODE,SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1)" "0: Normal mode,1: CHAN_EN"
newline
bitfld.long 0x0 28. "DSI_SYNC_CONFIG,- 0: bypass clock domain synchronisation of the DSI config signals." "0: bypass clock domain synchronisation of the DSI..,1: synchronize the DSI config signals to peripheral.."
newline
bitfld.long 0x0 27. "DEEPSLEEP_ON,- 0: SARMUX IP disabled off during DeepSleep power mode" "0: SARMUX IP disabled off during DeepSleep power mode,1: SARMUX IP remains enabled during DeepSleep power.."
newline
bitfld.long 0x0 24.--25. "ICONT_LV,SARADC low power mode." "0: normal power (default) max clk_sar is 18MHz.,1: 1/2 power mode max clk_sar is 9MHz.,2: 1.333 power mode max clk_sar is 18MHz.,3: 1/4 power mode max clk_sar is 4.5MHz."
newline
bitfld.long 0x0 20. "BOOSTPUMP_EN,SARADC internal pump: 0=disabled: pump output is VDDA 1=enabled: pump output is boosted." "0: disabled: pump output is VDDA,1: enabled: pump output is boosted"
newline
hexmask.long.byte 0x0 16.--19. 1. "SPARE,Spare controls not yet designated for late changes done with an ECO"
newline
bitfld.long 0x0 14.--15. "PWR_CTRL_VREF,VREF buffer low power mode." "0: normal power (default) bypass cap max clk_sar is..,1: deprecated,2: Invalid for PSoC4A otherwise 2X power no bypass..,3: deprecated"
newline
bitfld.long 0x0 13. "SAR_HW_CTRL_NEGVREF,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for VREF to NEG switch." "0: only firmware control,1: hardware control masked by firmware setting for.."
newline
bitfld.long 0x0 9.--11. "NEG_SEL,SARADC internal NEG selection for Single ended conversion" "0: NEG input of SARADC is connected to..,1: NEG input of SARADC is connected to VSSA in..,2: NEG input of SARADC is connected to P1 pin of..,3: NEG input of SARADC is connected to P3 pin of..,4: NEG input of SARADC is connected to P5 pin of..,5: NEG input of SARADC is connected to P7 pin of..,6: NEG input of SARADC is connected to an ACORE in..,7: NEG input of SARADC is shorted with VREF input.."
newline
bitfld.long 0x0 7. "VREF_BYP_CAP_EN,VREF bypass cap enable for when VREF buffer is on" "0,1"
newline
bitfld.long 0x0 4.--6. "VREF_SEL,SARADC internal VREF selection." "0: VREF0 from PRB (VREF buffer on),1: VREF1 from PRB (VREF buffer on),2: VREF2 from PRB (VREF buffer on),3: VREF from AROUTE (VREF buffer on),4: 1.024V from BandGap (VREF buffer on),5: External precision Vref direct from a pin (low..,6: Vdda/2 (VREF buffer on),7: Vdda."
line.long 0x4 "SAMPLE_CTRL,Sample control register."
bitfld.long 0x4 31. "EOS_DSI_OUT_EN,Enable to output EOS_INTR to DSI. When enabled each time EOS_INTR is set by the hardware also a pulse is send on the dsi_eos signal." "0,1"
newline
bitfld.long 0x4 19. "DSI_SYNC_TRIGGER,- 0: bypass clock domain synchronisation of the DSI trigger signal." "0: bypass clock domain synchronisation of the DSI..,1: synchronize the DSI trigger signal to the SAR.."
newline
bitfld.long 0x4 18. "DSI_TRIGGER_LEVEL,- 0: DSI trigger signal is a pulse input a positive edge detected on the DSI trigger signal triggers a new scan." "0: DSI trigger signal is a pulse input,1: DSI trigger signal is a level input"
newline
bitfld.long 0x4 17. "DSI_TRIGGER_EN,- 0: firmware trigger only: disable hardware (DSI) trigger." "0: firmware trigger only: disable hardware,1: enable hardware"
newline
bitfld.long 0x4 16. "CONTINUOUS,- 0: Wait for next FW_TRIGGER (one shot) or hardware (DSI) trigger (e.g. from TPWM for periodic triggering) before scanning enabled channels." "0: Wait for next FW_TRIGGER,1: Continuously scan enabled channels"
newline
bitfld.long 0x4 7. "AVG_SHIFT,Averaging shifting: after averaging the result is shifted right to fit in the sample resolution. For averaging the sample resolution is the highest resolution allowed by wounding." "0,1"
newline
bitfld.long 0x4 4.--6. "AVG_CNT,Averaging Count for channels that have over sampling enabled (AVG_EN). A channel will be sampled back to back (1<<(AVG_CNT+1)) = [2..256] times before the result is stored and the next enabled channel is sampled (1st order accumulate and dump.." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 3. "DIFFERENTIAL_SIGNED,Output data from a differential conversion as a signed value" "0: result data is unsigned (zero extended if needed),1: Default: result data is signed (sign extended if.."
newline
bitfld.long 0x4 2. "SINGLE_ENDED_SIGNED,Output data from a single ended conversion as a signed value" "0: Default: result data is unsigned (zero extended..,1: result data is signed (sign extended if needed)"
newline
bitfld.long 0x4 1. "LEFT_ALIGN,Left align data in data[15:0] default data is right aligned in data[11:0] with sign extension to 16 bits if the channel is differential." "0,1"
newline
bitfld.long 0x4 0. "SUB_RESOLUTION,Conversion resolution for channels that have sub-resolution enabled (RESOLUTION=1) (otherwise resolution is 12-bit)." "0: 8-bit.,1: 10-bit."
group.long 0x10++0x17
line.long 0x0 "SAMPLE_TIME01,Sample time specification ST0 and ST1"
hexmask.long.word 0x0 16.--25. 1. "SAMPLE_TIME1,Sample time1"
newline
hexmask.long.word 0x0 0.--9. 1. "SAMPLE_TIME0,Sample time0 (aperture) in ADC clock cycles. Note that actual sample time is half a clock less than specified here. The minimum sample time is 194ns which is 3.5 cycles (4 in this field) with an 18MHz clock. Minimum legal value in this.."
line.long 0x4 "SAMPLE_TIME23,Sample time specification ST2 and ST3"
hexmask.long.word 0x4 16.--25. 1. "SAMPLE_TIME3,Sample time3"
newline
hexmask.long.word 0x4 0.--9. 1. "SAMPLE_TIME2,Sample time2"
line.long 0x8 "RANGE_THRES,Global range detect threshold register."
hexmask.long.word 0x8 16.--31. 1. "RANGE_HIGH,High threshold for range detect."
newline
hexmask.long.word 0x8 0.--15. 1. "RANGE_LOW,Low threshold for range detect."
line.long 0xC "RANGE_COND,Global range detect mode register."
bitfld.long 0xC 30.--31. "RANGE_COND,Range condition select." "0: result < RANGE_LOW,1: RANGE_LOW <= result < RANGE_HIGH,2: RANGE_HIGH <= result,3: result < RANGE_LOW || RANGE_HIGH <= result"
line.long 0x10 "CHAN_EN,Enable bits for the channels"
hexmask.long.word 0x10 0.--15. 1. "CHAN_EN,Channel enable."
line.long 0x14 "START_CTRL,Start control register (firmware trigger)."
bitfld.long 0x14 0. "FW_TRIGGER,When firmware writes a 1 here it will trigger the next scan of enabled channels hardware clears this bit when the scan started with this trigger is completed. If scanning continuously the trigger is ignored and hardware clears this bit after.." "0,1"
group.long 0x30++0x3
line.long 0x0 "DFT_CTRL,DFT control register."
bitfld.long 0x0 31. "ADFT_OVERRIDE,During deepsleep/ hibernate mode keep SARMUX active i.e. do not open all switches (disconnect) to be used for ADFT" "0,1"
newline
bitfld.long 0x0 29. "DCEN,Delay Control Enable for latch." "0: doubles the latch enable time,1: normal latch enable time"
newline
bitfld.long 0x0 28. "EN_CSEL_DFT,Mux select signal for DAC control" "0,1"
newline
hexmask.long.byte 0x0 24.--27. 1. "SEL_CSEL_DFT,Usage 1: DFT bits for DAC array"
newline
bitfld.long 0x0 20.--22. "DFT_OUTC,DFT control for preamp outputs" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 16.--19. 1. "DFT_INC,DFT control for preamp inputs"
newline
bitfld.long 0x0 1. "HIZ,DFT control for getting higher input impedance must be 1 (0 is deprecated)" "0,1"
newline
bitfld.long 0x0 0. "DLY_INC,DFT control: Control for delay circuits on sampling phase =1 doubes the non-overlap delay" "0,1"
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x80)++0x3
line.long 0x0 "CHAN_CONFIG[$1],Channel configuration register."
bitfld.long 0x0 31. "DSI_OUT_EN,DSI data output enable for this channel." "0: the conversion result for this channel is only..,1: the conversion result for this channel is stored.."
newline
bitfld.long 0x0 12.--13. "SAMPLE_TIME_SEL,Sample time select: select which of the 4 global sample times to use for this channel" "0,1,2,3"
newline
bitfld.long 0x0 10. "AVG_EN,Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)" "0,1"
newline
bitfld.long 0x0 9. "RESOLUTION,Resolution for this channel. When AVG_EN is set this bit is ignored and always a 12-bit resolution (or highest resolution allowed by wounding) is used for this channel." "0: The maximum resolution is used for this channel..,1: The resolution specified by SUB_RESOLUTION in.."
newline
bitfld.long 0x0 8. "DIFFERENTIAL_EN,Differential enable for this channel." "0: The voltage on the addressed pin is measured,1: The differential voltage on the addressed pin.."
newline
bitfld.long 0x0 4.--6. "PORT_ADDR,Address of the port that contains the pin to be sampled by this channel." "0: SARMUX pins.,1: CTB0,2: CTB1,3: CTB2,4: CTB3,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)"
newline
bitfld.long 0x0 0.--2. "PIN_ADDR,Address of the pin to be sampled by this channel. If differential is enabled then PIN_ADDR[0] is ignored and considered to be 0 i.e. PIN_ADDR points to the even pin of a pin pair. For differential the even pin of the pair is connected to Vplus.." "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x100)++0x3
line.long 0x0 "CHAN_WORK[$1],Channel working data register"
bitfld.long 0x0 31. "CHAN_WORK_VALID_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register" "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "WORK,SAR conversion working data of the channel. The data is written here right after sampling this channel."
repeat.end
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
rgroup.long ($2+0x180)++0x3
line.long 0x0 "CHAN_RESULT[$1],Channel result data register"
bitfld.long 0x0 31. "CHAN_RESULT_VALID_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_VALID register" "0,1"
newline
bitfld.long 0x0 30. "RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_RANGE_INTR register" "0,1"
newline
bitfld.long 0x0 29. "SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_SATURATE_INTR register" "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "RESULT,SAR conversion result of the channel. The data is copied here from the WORK field after all enabled channels in this scan have been sampled."
repeat.end
rgroup.long 0x200++0xF
line.long 0x0 "CHAN_WORK_VALID,Channel working data register valid bits"
hexmask.long.word 0x0 0.--15. 1. "CHAN_WORK_VALID,If set the corresponding WORK data is valid i.e. was already sampled during the current scan."
line.long 0x4 "CHAN_RESULT_VALID,Channel result data register valid bits"
hexmask.long.word 0x4 0.--15. 1. "CHAN_RESULT_VALID,If set the corresponding RESULT data is valid i.e. was sampled during the last scan."
line.long 0x8 "STATUS,Current status of internal SAR registers (mostly for debug)"
bitfld.long 0x8 31. "BUSY,If high then the SAR is busy with a conversion. This bit is always high when CONTINUOUS is set. Firmware should wait for this bit to be low before putting the SAR in power down." "0,1"
newline
bitfld.long 0x8 30. "SW_VREF_NEG,the current switch status including DSI and sequencer controls of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL)." "0,1"
newline
hexmask.long.byte 0x8 0.--4. 1. "CUR_CHAN,current channel being sampled (channel 16 indicates the injection channel) only valid if BUSY."
line.long 0xC "AVG_STAT,Current averaging status (for debug)"
hexmask.long.byte 0xC 24.--31. 1. "CUR_AVG_CNT,the current value of the averaging counter. Note that the value shown is updated after the sampling time and therefore runs ahead of the accumulator update."
newline
hexmask.long.tbyte 0xC 0.--19. 1. "CUR_AVG_ACCU,the current value of the averaging accumulator"
group.long 0x210++0xB
line.long 0x0 "INTR,Interrupt request register."
bitfld.long 0x0 7. "INJ_COLLISION_INTR,Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 && INJ_TAILGATING==0) while the SAR is BUSY. Raising this interrupt is delayed to when the sampling of the.." "0,1"
newline
bitfld.long 0x0 6. "INJ_RANGE_INTR,Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit." "0,1"
newline
bitfld.long 0x0 5. "INJ_SATURATE_INTR,Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF (for 12-bit resolution) this is an indication that the ADC likely saturated. Write with '1' to.." "0,1"
newline
bitfld.long 0x0 4. "INJ_EOC_INTR,Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used). Write with '1' to clear bit." "0,1"
newline
bitfld.long 0x0 3. "DSI_COLLISION_INTR,DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the DSI trigger has been completed i.e. not when the.." "0,1"
newline
bitfld.long 0x0 2. "FW_COLLISION_INTR,Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY. Raising this interrupt is delayed to when the scan caused by the FW_TRIGGER has been completed i.e. not when the preceeding.." "0,1"
newline
bitfld.long 0x0 1. "OVERFLOW_INTR,Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware. Write with '1' to clear bit." "0,1"
newline
bitfld.long 0x0 0. "EOS_INTR,End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels. Write with '1' to clear bit." "0,1"
line.long 0x4 "INTR_SET,Interrupt set request register"
bitfld.long 0x4 7. "INJ_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "INJ_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "INJ_SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "INJ_EOC_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 3. "DSI_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "FW_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "EOS_SET,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_MASK,Interrupt mask register."
bitfld.long 0x8 7. "INJ_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 6. "INJ_RANGE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 5. "INJ_SATURATE_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 4. "INJ_EOC_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 3. "DSI_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 2. "FW_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "EOS_MASK,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0x21C++0x3
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
bitfld.long 0x0 7. "INJ_COLLISION_MASKED,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 6. "INJ_RANGE_MASKED,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 5. "INJ_SATURATE_MASKED,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 4. "INJ_EOC_MASKED,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 3. "DSI_COLLISION_MASKED,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "FW_COLLISION_MASKED,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "OVERFLOW_MASKED,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "EOS_MASKED,Logical and of corresponding request and mask bits." "0,1"
group.long 0x220++0xB
line.long 0x0 "SATURATE_INTR,Saturate interrupt request register."
hexmask.long.word 0x0 0.--15. 1. "SATURATE_INTR,Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF (for 12-bit resolution) this is an indication that the ADC likely saturated. Write with.."
line.long 0x4 "SATURATE_INTR_SET,Saturate interrupt set request register"
hexmask.long.word 0x4 0.--15. 1. "SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register."
line.long 0x8 "SATURATE_INTR_MASK,Saturate interrupt mask register."
hexmask.long.word 0x8 0.--15. 1. "SATURATE_MASK,Mask bit for corresponding bit in interrupt request register."
rgroup.long 0x22C++0x3
line.long 0x0 "SATURATE_INTR_MASKED,Saturate interrupt masked request register"
hexmask.long.word 0x0 0.--15. 1. "SATURATE_MASKED,Logical and of corresponding request and mask bits."
group.long 0x230++0xB
line.long 0x0 "RANGE_INTR,Range detect interrupt request register."
hexmask.long.word 0x0 0.--15. 1. "RANGE_INTR,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers. Write with '1' to clear bit."
line.long 0x4 "RANGE_INTR_SET,Range detect interrupt set request register"
hexmask.long.word 0x4 0.--15. 1. "RANGE_SET,Write with '1' to set corresponding bit in interrupt request register."
line.long 0x8 "RANGE_INTR_MASK,Range detect interrupt mask register."
hexmask.long.word 0x8 0.--15. 1. "RANGE_MASK,Mask bit for corresponding bit in interrupt request register."
rgroup.long 0x23C++0x7
line.long 0x0 "RANGE_INTR_MASKED,Range interrupt masked request register"
hexmask.long.word 0x0 0.--15. 1. "RANGE_MASKED,Logical and of corresponding request and mask bits."
line.long 0x4 "INTR_CAUSE,Interrupt cause register"
bitfld.long 0x4 31. "RANGE_MASKED_RED,Reduction OR of all SAR_RANGE_INTR_MASKED bits" "0,1"
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bitfld.long 0x4 30. "SATURATE_MASKED_RED,Reduction OR of all SAR_SATURATION_INTR_MASKED bits" "0,1"
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bitfld.long 0x4 7. "INJ_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
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bitfld.long 0x4 6. "INJ_RANGE_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
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bitfld.long 0x4 5. "INJ_SATURATE_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
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bitfld.long 0x4 4. "INJ_EOC_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
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bitfld.long 0x4 3. "DSI_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
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bitfld.long 0x4 2. "FW_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
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bitfld.long 0x4 1. "OVERFLOW_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
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bitfld.long 0x4 0. "EOS_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
group.long 0x280++0x3
line.long 0x0 "INJ_CHAN_CONFIG,Injection channel configuration register."
bitfld.long 0x0 31. "INJ_START_EN,Set by firmware to enable the injection channel. If INJ_TAILGATING is not set this bit also functions as trigger for this channel. Cleared by hardware after this channel has been sampled (i.e. this channel is always one shot even if.." "0,1"
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bitfld.long 0x0 30. "INJ_TAILGATING,Injection channel tailgating." "0: no tailgating for this channel,1: injection channel tailgating"
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bitfld.long 0x0 12.--13. "INJ_SAMPLE_TIME_SEL,Injection sample time select: select which of the 4 global sample times to use for this channel" "0,1,2,3"
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bitfld.long 0x0 10. "INJ_AVG_EN,Averaging enable for this channel. If set the AVG_CNT and AVG_SHIFT settings are used for sampling the addressed pin(s)" "0,1"
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bitfld.long 0x0 9. "INJ_RESOLUTION,Resolution for this channel." "0: 12-bit resolution is used for this channel.,1: The resolution specified by SUB_RESOLUTION in.."
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bitfld.long 0x0 8. "INJ_DIFFERENTIAL_EN,Differential enable for this channel." "0: The voltage on the addressed pin is measured,1: The differential voltage on the addressed pin.."
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bitfld.long 0x0 4.--6. "INJ_PORT_ADDR,Address of the port that contains the pin to be sampled by this channel." "0: SARMUX pins.,1: CTB0,2: CTB1,3: CTB2,4: CTB3,?,6: AROUTE virtual port,7: SARMUX virtual port"
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bitfld.long 0x0 0.--2. "INJ_PIN_ADDR,Address of the pin to be sampled by this injection channel. If differential is enabled then PIN_ADDR[0] is ignored and considered to be 0 i.e. PIN_ADDR points to the even pin of a pin pair." "0,1,2,3,4,5,6,7"
rgroup.long 0x290++0x3
line.long 0x0 "INJ_RESULT,Injection channel result register"
bitfld.long 0x0 31. "INJ_EOC_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
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bitfld.long 0x0 30. "INJ_RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
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bitfld.long 0x0 29. "INJ_SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
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bitfld.long 0x0 28. "INJ_COLLISION_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
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hexmask.long.word 0x0 0.--15. 1. "INJ_RESULT,SAR conversion result of the channel."
group.long 0x300++0xF
line.long 0x0 "MUX_SWITCH0,SARMUX Firmware switch controls"
bitfld.long 0x0 29. "MUX_FW_P7_COREIO3,Firmware control: 0=open 1=close switch between P7 and coreio3 signal. Write with '1' to set bit." "0: open,1: close switch between P7 and coreio3 signal"
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bitfld.long 0x0 28. "MUX_FW_P6_COREIO2,Firmware control: 0=open 1=close switch between P6 and coreio2 signal. Write with '1' to set bit." "0: open,1: close switch between P6 and coreio2 signal"
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bitfld.long 0x0 27. "MUX_FW_P5_COREIO1,Firmware control: 0=open 1=close switch between P5 and coreio1 signal. Write with '1' to set bit." "0: open,1: close switch between P5 and coreio1 signal"
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bitfld.long 0x0 26. "MUX_FW_P4_COREIO0,Firmware control: 0=open 1=close switch between P4 and coreio0 signal. Write with '1' to set bit." "0: open,1: close switch between P4 and coreio0 signal"
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bitfld.long 0x0 25. "MUX_FW_SARBUS1_VMINUS,Firmware control: 0=open 1=close switch between sarbus1 and vminus signal. Write with '1' to set bit." "0: open,1: close switch between sarbus1 and vminus signal"
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bitfld.long 0x0 24. "MUX_FW_SARBUS0_VMINUS,Firmware control: 0=open 1=close switch between sarbus0 and vminus signal. Write with '1' to set bit." "0: open,1: close switch between sarbus0 and vminus signal"
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bitfld.long 0x0 23. "MUX_FW_SARBUS1_VPLUS,Firmware control: 0=open 1=close switch between sarbus1 and vplus signal. Write with '1' to set bit." "0: open,1: close switch between sarbus1 and vplus signal"
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bitfld.long 0x0 22. "MUX_FW_SARBUS0_VPLUS,Firmware control: 0=open 1=close switch between sarbus0 and vplus signal. Write with '1' to set bit." "0: open,1: close switch between sarbus0 and vplus signal"
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bitfld.long 0x0 21. "MUX_FW_AMUXBUSB_VMINUS,Firmware control: 0=open 1=close switch between amuxbusb and vminus signal. Write with '1' to set bit." "0: open,1: close switch between amuxbusb and vminus signal"
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bitfld.long 0x0 20. "MUX_FW_AMUXBUSA_VMINUS,Firmware control: 0=open 1=close switch between amuxbusa and vminus signal. Write with '1' to set bit." "0: open,1: close switch between amuxbusa and vminus signal"
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bitfld.long 0x0 19. "MUX_FW_AMUXBUSB_VPLUS,Firmware control: 0=open 1=close switch between amuxbusb and vplus signal. Write with '1' to set bit." "0: open,1: close switch between amuxbusb and vplus signal"
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bitfld.long 0x0 18. "MUX_FW_AMUXBUSA_VPLUS,Firmware control: 0=open 1=close switch between amuxbusa and vplus signal. Write with '1' to set bit." "0: open,1: close switch between amuxbusa and vplus signal"
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bitfld.long 0x0 17. "MUX_FW_TEMP_VPLUS,Firmware control: 0=open 1=close switch between temperature sensor and vplus signal also powers on the temperature sensor. Write with '1' to set bit." "0: open,1: close switch between temperature sensor and.."
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bitfld.long 0x0 16. "MUX_FW_VSSA_VMINUS,Firmware control: 0=open 1=close switch between vssa_kelvin and vminus signal. Write with '1' to set bit." "0: open,1: close switch between vssa_kelvin and vminus signal"
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bitfld.long 0x0 15. "MUX_FW_P7_VMINUS,Firmware control: 0=open 1=close switch between pin P7 and vminus signal. Write with '1' to set bit." "0: open,1: close switch between pin P7 and vminus signal"
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bitfld.long 0x0 14. "MUX_FW_P6_VMINUS,Firmware control: 0=open 1=close switch between pin P6 and vminus signal. Write with '1' to set bit." "0: open,1: close switch between pin P6 and vminus signal"
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bitfld.long 0x0 13. "MUX_FW_P5_VMINUS,Firmware control: 0=open 1=close switch between pin P5 and vminus signal. Write with '1' to set bit." "0: open,1: close switch between pin P5 and vminus signal"
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bitfld.long 0x0 12. "MUX_FW_P4_VMINUS,Firmware control: 0=open 1=close switch between pin P4 and vminus signal. Write with '1' to set bit." "0: open,1: close switch between pin P4 and vminus signal"
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bitfld.long 0x0 11. "MUX_FW_P3_VMINUS,Firmware control: 0=open 1=close switch between pin P3 and vminus signal. Write with '1' to set bit." "0: open,1: close switch between pin P3 and vminus signal"
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bitfld.long 0x0 10. "MUX_FW_P2_VMINUS,Firmware control: 0=open 1=close switch between pin P2 and vminus signal. Write with '1' to set bit." "0: open,1: close switch between pin P2 and vminus signal"
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bitfld.long 0x0 9. "MUX_FW_P1_VMINUS,Firmware control: 0=open 1=close switch between pin P1 and vminus signal. Write with '1' to set bit." "0: open,1: close switch between pin P1 and vminus signal"
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bitfld.long 0x0 8. "MUX_FW_P0_VMINUS,Firmware control: 0=open 1=close switch between pin P0 and vminus signal. Write with '1' to set bit." "0: open,1: close switch between pin P0 and vminus signal"
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bitfld.long 0x0 7. "MUX_FW_P7_VPLUS,Firmware control: 0=open 1=close switch between pin P7 and vplus signal. Write with '1' to set bit." "0: open,1: close switch between pin P7 and vplus signal"
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bitfld.long 0x0 6. "MUX_FW_P6_VPLUS,Firmware control: 0=open 1=close switch between pin P6 and vplus signal. Write with '1' to set bit." "0: open,1: close switch between pin P6 and vplus signal"
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bitfld.long 0x0 5. "MUX_FW_P5_VPLUS,Firmware control: 0=open 1=close switch between pin P5 and vplus signal. Write with '1' to set bit." "0: open,1: close switch between pin P5 and vplus signal"
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bitfld.long 0x0 4. "MUX_FW_P4_VPLUS,Firmware control: 0=open 1=close switch between pin P4 and vplus signal. Write with '1' to set bit." "0: open,1: close switch between pin P4 and vplus signal"
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bitfld.long 0x0 3. "MUX_FW_P3_VPLUS,Firmware control: 0=open 1=close switch between pin P3 and vplus signal. Write with '1' to set bit." "0: open,1: close switch between pin P3 and vplus signal"
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bitfld.long 0x0 2. "MUX_FW_P2_VPLUS,Firmware control: 0=open 1=close switch between pin P2 and vplus signal. Write with '1' to set bit." "0: open,1: close switch between pin P2 and vplus signal"
newline
bitfld.long 0x0 1. "MUX_FW_P1_VPLUS,Firmware control: 0=open 1=close switch between pin P1 and vplus signal. Write with '1' to set bit." "0: open,1: close switch between pin P1 and vplus signal"
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bitfld.long 0x0 0. "MUX_FW_P0_VPLUS,Firmware control: 0=open 1=close switch between pin P0 and vplus signal. Write with '1' to set bit." "0: open,1: close switch between pin P0 and vplus signal"
line.long 0x4 "MUX_SWITCH_CLEAR0,SARMUX Firmware switch control clear"
bitfld.long 0x4 29. "MUX_FW_P7_COREIO3,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 28. "MUX_FW_P6_COREIO2,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 27. "MUX_FW_P5_COREIO1,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 26. "MUX_FW_P4_COREIO0,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 25. "MUX_FW_SARBUS1_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 24. "MUX_FW_SARBUS0_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 23. "MUX_FW_SARBUS1_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 22. "MUX_FW_SARBUS0_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 21. "MUX_FW_AMUXBUSB_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 20. "MUX_FW_AMUXBUSA_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 19. "MUX_FW_AMUXBUSB_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 18. "MUX_FW_AMUXBUSA_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 17. "MUX_FW_TEMP_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 16. "MUX_FW_VSSA_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 15. "MUX_FW_P7_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 14. "MUX_FW_P6_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 13. "MUX_FW_P5_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 12. "MUX_FW_P4_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 11. "MUX_FW_P3_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 10. "MUX_FW_P2_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 9. "MUX_FW_P1_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 8. "MUX_FW_P0_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 7. "MUX_FW_P7_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 6. "MUX_FW_P6_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 5. "MUX_FW_P5_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 4. "MUX_FW_P4_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 3. "MUX_FW_P3_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 2. "MUX_FW_P2_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 1. "MUX_FW_P1_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x4 0. "MUX_FW_P0_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
line.long 0x8 "MUX_SWITCH1,SARMUX Firmware switch controls"
bitfld.long 0x8 3. "MUX_FW_ADFT1_SARBUS1,Firmware control: 0=open 1=close switch between adft1 signal and sarbus1 signal. Write with '1' to set bit." "0: open,1: close switch between adft1 signal and sarbus1.."
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bitfld.long 0x8 2. "MUX_FW_ADFT0_SARBUS0,Firmware control: 0=open 1=close switch between adft0 signal and sarbus0 signal. Write with '1' to set bit." "0: open,1: close switch between adft0 signal and sarbus0.."
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bitfld.long 0x8 1. "MUX_FW_P5_DFT_INM,Firmware control: 0=open 1=close switch between P5 pin and dft_inm signal. Write with '1' to set bit." "0: open,1: close switch between P5 pin and dft_inm signal"
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bitfld.long 0x8 0. "MUX_FW_P4_DFT_INP,Firmware control: 0=open 1=close switch between P4 pin and dft_inp signal. Write with '1' to set bit." "0: open,1: close switch between P4 pin and dft_inp signal"
line.long 0xC "MUX_SWITCH_CLEAR1,SARMUX Firmware switch control clear"
bitfld.long 0xC 3. "MUX_FW_ADFT1_SARBUS1,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
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bitfld.long 0xC 2. "MUX_FW_ADFT0_SARBUS0,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
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bitfld.long 0xC 1. "MUX_FW_P5_DFT_INM,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
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bitfld.long 0xC 0. "MUX_FW_P4_DFT_INP,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
group.long 0x340++0x3
line.long 0x0 "MUX_SWITCH_HW_CTRL,SARMUX switch hardware control"
bitfld.long 0x0 23. "MUX_HW_CTRL_SARBUS1,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for sarbus1 switches." "0: only firmware control,1: hardware control masked by firmware setting for.."
newline
bitfld.long 0x0 22. "MUX_HW_CTRL_SARBUS0,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for sarbus0 switches." "0: only firmware control,1: hardware control masked by firmware setting for.."
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bitfld.long 0x0 19. "MUX_HW_CTRL_AMUXBUSB,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for amuxbusb switches." "0: only firmware control,1: hardware control masked by firmware setting for.."
newline
bitfld.long 0x0 18. "MUX_HW_CTRL_AMUXBUSA,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for amuxbusa switches." "0: only firmware control,1: hardware control masked by firmware setting for.."
newline
bitfld.long 0x0 17. "MUX_HW_CTRL_TEMP,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for temp switch." "0: only firmware control,1: hardware control masked by firmware setting for.."
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bitfld.long 0x0 16. "MUX_HW_CTRL_VSSA,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for vssa switch." "0: only firmware control,1: hardware control masked by firmware setting for.."
newline
bitfld.long 0x0 7. "MUX_HW_CTRL_P7,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for pin P7 switches." "0: only firmware control,1: hardware control masked by firmware setting for.."
newline
bitfld.long 0x0 6. "MUX_HW_CTRL_P6,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for pin P6 switches." "0: only firmware control,1: hardware control masked by firmware setting for.."
newline
bitfld.long 0x0 5. "MUX_HW_CTRL_P5,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for pin P5 switches." "0: only firmware control,1: hardware control masked by firmware setting for.."
newline
bitfld.long 0x0 4. "MUX_HW_CTRL_P4,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for pin P4 switches." "0: only firmware control,1: hardware control masked by firmware setting for.."
newline
bitfld.long 0x0 3. "MUX_HW_CTRL_P3,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for pin P3 switches." "0: only firmware control,1: hardware control masked by firmware setting for.."
newline
bitfld.long 0x0 2. "MUX_HW_CTRL_P2,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for pin P2 switches." "0: only firmware control,1: hardware control masked by firmware setting for.."
newline
bitfld.long 0x0 1. "MUX_HW_CTRL_P1,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for pin P1 switches." "0: only firmware control,1: hardware control masked by firmware setting for.."
newline
bitfld.long 0x0 0. "MUX_HW_CTRL_P0,Hardware control: 0=only firmware control 1=hardware control masked by firmware setting for pin P0 switches." "0: only firmware control,1: hardware control masked by firmware setting for.."
rgroup.long 0x348++0x3
line.long 0x0 "MUX_SWITCH_STATUS,SARMUX switch status"
bitfld.long 0x0 25. "MUX_FW_SARBUS1_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 24. "MUX_FW_SARBUS0_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 23. "MUX_FW_SARBUS1_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 22. "MUX_FW_SARBUS0_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 21. "MUX_FW_AMUXBUSB_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 20. "MUX_FW_AMUXBUSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 19. "MUX_FW_AMUXBUSB_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 18. "MUX_FW_AMUXBUSA_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 17. "MUX_FW_TEMP_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 16. "MUX_FW_VSSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 15. "MUX_FW_P7_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 14. "MUX_FW_P6_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 13. "MUX_FW_P5_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 12. "MUX_FW_P4_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 11. "MUX_FW_P3_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 10. "MUX_FW_P2_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 9. "MUX_FW_P1_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 8. "MUX_FW_P0_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 7. "MUX_FW_P7_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 6. "MUX_FW_P6_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 5. "MUX_FW_P5_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 4. "MUX_FW_P4_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 3. "MUX_FW_P3_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 2. "MUX_FW_P2_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 1. "MUX_FW_P1_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
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bitfld.long 0x0 0. "MUX_FW_P0_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
group.long 0x380++0x3
line.long 0x0 "PUMP_CTRL,Switch pump control"
bitfld.long 0x0 31. "ENABLED,0=disabled: pump output is VDDA_PUMP 1=enabled: pump output is boosted." "0: disabled: pump output is VDDA_PUMP,1: enabled: pump output is boosted"
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bitfld.long 0x0 0. "CLOCK_SEL,Clock select: 0=external clock 1=internal clock (deprecated)." "0: external clock,1: internal clock"
group.long 0xF00++0x7
line.long 0x0 "ANA_TRIM,Analog trim register."
bitfld.long 0x0 3. "TRIMUNIT,Attenuation cap trimming" "0,1"
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bitfld.long 0x0 0.--2. "CAP_TRIM,Attenuation cap trimming" "0,1,2,3,4,5,6,7"
line.long 0x4 "WOUNDING,SAR wounding register"
bitfld.long 0x4 0.--1. "WOUND_RESOLUTION,Maximum SAR resolution allowed" "0: unwounded: up to full 12-bit SAR resolution..,1: wounded: max resolution upto 10-bit SAR..,2: wounded: only 8-bit SAR resolution allowed,3: wounded: only 8-bit SAR resolution allowed"
tree.end
tree "SCB (Serial Communication Block)"
base ad:0x0
tree "SCB0"
base ad:0x40240000
group.long 0x0++0x3
line.long 0x0 "CTRL,Generic control"
bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
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bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element depending on physical SRAM cell data width." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
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bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
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bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
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bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Generic status"
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
group.long 0x8++0x3
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
rgroup.long 0xC++0x3
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
group.long 0x20++0x3
line.long 0x0 "SPI_CTRL,SPI control"
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "SPI_STATUS,SPI status"
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
group.long 0x28++0x7
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
bitfld.long 0x0 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive " "0: retain the level of last data bit,1: change to high"
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
group.long 0x40++0xB
line.long 0x0 "UART_CTRL,UART control"
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
line.long 0x8 "UART_RX_CTRL,UART receiver control"
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
rgroup.long 0x4C++0x3
line.long 0x0 "UART_RX_STATUS,UART receiver status"
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
group.long 0x50++0x3
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
group.long 0x60++0x3
line.long 0x0 "I2C_CTRL,I2C control"
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
rgroup.long 0x64++0x3
line.long 0x0 "I2C_STATUS,I2C status"
bitfld.long 0x0 24. "HS_MODE,this is to indicate I2C Hs-mode transfer " "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
group.long 0x68++0xF
line.long 0x0 "I2C_M_CMD,I2C master command"
bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
line.long 0x4 "I2C_S_CMD,I2C slave command"
bitfld.long 0x4 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected." "0,1"
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bitfld.long 0x4 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty." "0,1"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
line.long 0x8 "I2C_CFG,I2C configuration"
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
line.long 0xC "I2C_STRETCH_CTRL,I2C stretch control"
hexmask.long.byte 0xC 0.--3. 1. "STRETCH_THRESHOLD,stretch threthold."
rgroup.long 0x78++0x3
line.long 0x0 "I2C_STRETCH_STATUS,I2C stretch status"
bitfld.long 0x0 8. "STRETCHING,I2C SCL is stretched by this block (DUT) " "0,1"
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bitfld.long 0x0 5. "SYNC_DETECTED,synchronization detected." "0,1"
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bitfld.long 0x0 4. "STRETCH_DETECTED,stretch detected." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "STRETCH_COUNT,stretch count."
group.long 0x80++0x3
line.long 0x0 "I2C_CTRL_HS,I2C control for High-Speed mode"
bitfld.long 0x0 31. "HS_ENABLED,0': I2C Hs-mode is disabled " "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOVS_HS,Serial I2C interface low phase oversampling factor for I2C Hs-mode. LOVS_HS + 1 peripheral clock periods constitute the low phase of a bit period."
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hexmask.long.byte 0x0 0.--3. 1. "HOVS_HS,Serial I2C interface high phase oversampling factor for I2C Hs-mode. HOVS_HS + 1 peripheral clock periods constitute the high phase of a bit period."
group.long 0x200++0x7
line.long 0x0 "TX_CTRL,Transmitter control"
bitfld.long 0x0 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
rgroup.long 0x208++0x3
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
wgroup.long 0x240++0x3
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
group.long 0x300++0x7
line.long 0x0 "RX_CTRL,Receiver control"
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
rgroup.long 0x308++0x3
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
group.long 0x310++0x3
line.long 0x0 "RX_MATCH,Slave address and mask"
hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
rgroup.long 0x340++0x7
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
rgroup.long 0xE00++0x3
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
group.long 0xE80++0x3
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
group.long 0xE88++0x3
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xE8C++0x3
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xEC0++0x3
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
group.long 0xEC8++0x3
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xECC++0x3
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF00++0xB
line.long 0x0 "INTR_M,Master interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
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bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
line.long 0x4 "INTR_M_SET,Master interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF0C++0x3
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF40++0xB
line.long 0x0 "INTR_S,Slave interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
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bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
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bitfld.long 0x0 16. "I2C_RESTART,I2C slave RESTART received." "0,1"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF4C++0x3
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 16. "I2C_RESTART,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF80++0xB
line.long 0x0 "INTR_TX,Transmitter interrupt request"
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF8C++0x3
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
group.long 0xFC0++0xB
line.long 0x0 "INTR_RX,Receiver interrupt request"
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
newline
bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xFCC++0x3
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
tree.end
tree "SCB1"
base ad:0x40250000
group.long 0x0++0x3
line.long 0x0 "CTRL,Generic control"
bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
newline
bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
newline
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
newline
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
newline
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
newline
bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element depending on physical SRAM cell data width." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
newline
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
newline
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
newline
bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
newline
bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Generic status"
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
group.long 0x8++0x3
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
newline
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
rgroup.long 0xC++0x3
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
newline
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
newline
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
newline
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
group.long 0x20++0x3
line.long 0x0 "SPI_CTRL,SPI control"
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
newline
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
newline
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
newline
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
newline
bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
newline
bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
newline
bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
newline
bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
newline
bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
newline
bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
newline
bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
newline
bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
newline
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
newline
bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
newline
bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
newline
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
newline
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "SPI_STATUS,SPI status"
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
newline
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
newline
bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
newline
bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
group.long 0x28++0x7
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
bitfld.long 0x0 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive " "0: retain the level of last data bit,1: change to high"
newline
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
newline
bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
newline
bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
newline
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
group.long 0x40++0xB
line.long 0x0 "UART_CTRL,UART control"
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
newline
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
newline
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
newline
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
line.long 0x8 "UART_RX_CTRL,UART receiver control"
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
rgroup.long 0x4C++0x3
line.long 0x0 "UART_RX_STATUS,UART receiver status"
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
group.long 0x50++0x3
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
group.long 0x60++0x3
line.long 0x0 "I2C_CTRL,I2C control"
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
rgroup.long 0x64++0x3
line.long 0x0 "I2C_STATUS,I2C status"
bitfld.long 0x0 24. "HS_MODE,this is to indicate I2C Hs-mode transfer " "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
group.long 0x68++0xF
line.long 0x0 "I2C_M_CMD,I2C master command"
bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
line.long 0x4 "I2C_S_CMD,I2C slave command"
bitfld.long 0x4 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected." "0,1"
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bitfld.long 0x4 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty." "0,1"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
line.long 0x8 "I2C_CFG,I2C configuration"
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
line.long 0xC "I2C_STRETCH_CTRL,I2C stretch control"
hexmask.long.byte 0xC 0.--3. 1. "STRETCH_THRESHOLD,stretch threthold."
rgroup.long 0x78++0x3
line.long 0x0 "I2C_STRETCH_STATUS,I2C stretch status"
bitfld.long 0x0 8. "STRETCHING,I2C SCL is stretched by this block (DUT) " "0,1"
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bitfld.long 0x0 5. "SYNC_DETECTED,synchronization detected." "0,1"
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bitfld.long 0x0 4. "STRETCH_DETECTED,stretch detected." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "STRETCH_COUNT,stretch count."
group.long 0x80++0x3
line.long 0x0 "I2C_CTRL_HS,I2C control for High-Speed mode"
bitfld.long 0x0 31. "HS_ENABLED,0': I2C Hs-mode is disabled " "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOVS_HS,Serial I2C interface low phase oversampling factor for I2C Hs-mode. LOVS_HS + 1 peripheral clock periods constitute the low phase of a bit period."
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hexmask.long.byte 0x0 0.--3. 1. "HOVS_HS,Serial I2C interface high phase oversampling factor for I2C Hs-mode. HOVS_HS + 1 peripheral clock periods constitute the high phase of a bit period."
group.long 0x200++0x7
line.long 0x0 "TX_CTRL,Transmitter control"
bitfld.long 0x0 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
rgroup.long 0x208++0x3
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
wgroup.long 0x240++0x3
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
group.long 0x300++0x7
line.long 0x0 "RX_CTRL,Receiver control"
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
rgroup.long 0x308++0x3
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
group.long 0x310++0x3
line.long 0x0 "RX_MATCH,Slave address and mask"
hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
rgroup.long 0x340++0x7
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
rgroup.long 0xE00++0x3
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
group.long 0xE80++0x3
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
group.long 0xE88++0x3
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xE8C++0x3
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xEC0++0x3
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
group.long 0xEC8++0x3
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xECC++0x3
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF00++0xB
line.long 0x0 "INTR_M,Master interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
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bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
line.long 0x4 "INTR_M_SET,Master interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF0C++0x3
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF40++0xB
line.long 0x0 "INTR_S,Slave interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
newline
bitfld.long 0x0 16. "I2C_RESTART,I2C slave RESTART received." "0,1"
newline
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
newline
bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
newline
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
newline
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
newline
bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
newline
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
newline
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF4C++0x3
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 16. "I2C_RESTART,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF80++0xB
line.long 0x0 "INTR_TX,Transmitter interrupt request"
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
newline
bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF8C++0x3
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
group.long 0xFC0++0xB
line.long 0x0 "INTR_RX,Receiver interrupt request"
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
newline
bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xFCC++0x3
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
tree.end
tree "SCB2"
base ad:0x40260000
group.long 0x0++0x3
line.long 0x0 "CTRL,Generic control"
bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
newline
bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
newline
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
newline
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
newline
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element depending on physical SRAM cell data width." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
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bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
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bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
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bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Generic status"
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
group.long 0x8++0x3
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
rgroup.long 0xC++0x3
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
group.long 0x20++0x3
line.long 0x0 "SPI_CTRL,SPI control"
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "SPI_STATUS,SPI status"
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
group.long 0x28++0x7
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
bitfld.long 0x0 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive " "0: retain the level of last data bit,1: change to high"
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
group.long 0x40++0xB
line.long 0x0 "UART_CTRL,UART control"
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
line.long 0x8 "UART_RX_CTRL,UART receiver control"
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
rgroup.long 0x4C++0x3
line.long 0x0 "UART_RX_STATUS,UART receiver status"
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
group.long 0x50++0x3
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
group.long 0x60++0x3
line.long 0x0 "I2C_CTRL,I2C control"
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
rgroup.long 0x64++0x3
line.long 0x0 "I2C_STATUS,I2C status"
bitfld.long 0x0 24. "HS_MODE,this is to indicate I2C Hs-mode transfer " "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
group.long 0x68++0xF
line.long 0x0 "I2C_M_CMD,I2C master command"
bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
line.long 0x4 "I2C_S_CMD,I2C slave command"
bitfld.long 0x4 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected." "0,1"
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bitfld.long 0x4 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty." "0,1"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
line.long 0x8 "I2C_CFG,I2C configuration"
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
line.long 0xC "I2C_STRETCH_CTRL,I2C stretch control"
hexmask.long.byte 0xC 0.--3. 1. "STRETCH_THRESHOLD,stretch threthold."
rgroup.long 0x78++0x3
line.long 0x0 "I2C_STRETCH_STATUS,I2C stretch status"
bitfld.long 0x0 8. "STRETCHING,I2C SCL is stretched by this block (DUT) " "0,1"
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bitfld.long 0x0 5. "SYNC_DETECTED,synchronization detected." "0,1"
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bitfld.long 0x0 4. "STRETCH_DETECTED,stretch detected." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "STRETCH_COUNT,stretch count."
group.long 0x80++0x3
line.long 0x0 "I2C_CTRL_HS,I2C control for High-Speed mode"
bitfld.long 0x0 31. "HS_ENABLED,0': I2C Hs-mode is disabled " "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOVS_HS,Serial I2C interface low phase oversampling factor for I2C Hs-mode. LOVS_HS + 1 peripheral clock periods constitute the low phase of a bit period."
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hexmask.long.byte 0x0 0.--3. 1. "HOVS_HS,Serial I2C interface high phase oversampling factor for I2C Hs-mode. HOVS_HS + 1 peripheral clock periods constitute the high phase of a bit period."
group.long 0x200++0x7
line.long 0x0 "TX_CTRL,Transmitter control"
bitfld.long 0x0 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
rgroup.long 0x208++0x3
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
wgroup.long 0x240++0x3
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
group.long 0x300++0x7
line.long 0x0 "RX_CTRL,Receiver control"
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
rgroup.long 0x308++0x3
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
newline
hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
newline
bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
group.long 0x310++0x3
line.long 0x0 "RX_MATCH,Slave address and mask"
hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
rgroup.long 0x340++0x7
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
rgroup.long 0xE00++0x3
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
newline
bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
newline
bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
newline
bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
newline
bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
group.long 0xE80++0x3
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
group.long 0xE88++0x3
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xE8C++0x3
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xEC0++0x3
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
group.long 0xEC8++0x3
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xECC++0x3
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF00++0xB
line.long 0x0 "INTR_M,Master interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
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bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
line.long 0x4 "INTR_M_SET,Master interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF0C++0x3
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF40++0xB
line.long 0x0 "INTR_S,Slave interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
newline
bitfld.long 0x0 16. "I2C_RESTART,I2C slave RESTART received." "0,1"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
newline
bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
newline
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
newline
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF4C++0x3
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 16. "I2C_RESTART,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF80++0xB
line.long 0x0 "INTR_TX,Transmitter interrupt request"
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
newline
bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF8C++0x3
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
group.long 0xFC0++0xB
line.long 0x0 "INTR_RX,Receiver interrupt request"
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
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bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
newline
bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xFCC++0x3
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
tree.end
tree "SCB3"
base ad:0x40270000
group.long 0x0++0x3
line.long 0x0 "CTRL,Generic control"
bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
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bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element depending on physical SRAM cell data width." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
newline
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
newline
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
newline
bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
newline
bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Generic status"
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
group.long 0x8++0x3
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
newline
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
rgroup.long 0xC++0x3
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
newline
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
newline
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
newline
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
group.long 0x20++0x3
line.long 0x0 "SPI_CTRL,SPI control"
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
newline
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
newline
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
newline
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
newline
bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
newline
bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
newline
bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
newline
bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
newline
bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
newline
bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
newline
bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
newline
bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
newline
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
newline
bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
newline
bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
newline
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
newline
bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "SPI_STATUS,SPI status"
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
newline
hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
newline
bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
newline
bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
group.long 0x28++0x7
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
bitfld.long 0x0 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive " "0: retain the level of last data bit,1: change to high"
newline
bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
newline
bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
newline
bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
newline
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
group.long 0x40++0xB
line.long 0x0 "UART_CTRL,UART control"
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
newline
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
newline
bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
newline
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
newline
bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
line.long 0x8 "UART_RX_CTRL,UART receiver control"
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
newline
hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
newline
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
newline
bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
newline
bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
newline
bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
newline
bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
newline
bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
newline
bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
newline
bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
newline
bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
rgroup.long 0x4C++0x3
line.long 0x0 "UART_RX_STATUS,UART receiver status"
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
group.long 0x50++0x3
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
newline
bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
newline
bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
newline
hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
group.long 0x60++0x3
line.long 0x0 "I2C_CTRL,I2C control"
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
newline
bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
newline
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
newline
bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
newline
bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
newline
bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
newline
bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
newline
bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
newline
bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
newline
bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
rgroup.long 0x64++0x3
line.long 0x0 "I2C_STATUS,I2C status"
bitfld.long 0x0 24. "HS_MODE,this is to indicate I2C Hs-mode transfer " "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
group.long 0x68++0xF
line.long 0x0 "I2C_M_CMD,I2C master command"
bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
line.long 0x4 "I2C_S_CMD,I2C slave command"
bitfld.long 0x4 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected." "0,1"
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bitfld.long 0x4 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty." "0,1"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
line.long 0x8 "I2C_CFG,I2C configuration"
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
line.long 0xC "I2C_STRETCH_CTRL,I2C stretch control"
hexmask.long.byte 0xC 0.--3. 1. "STRETCH_THRESHOLD,stretch threthold."
rgroup.long 0x78++0x3
line.long 0x0 "I2C_STRETCH_STATUS,I2C stretch status"
bitfld.long 0x0 8. "STRETCHING,I2C SCL is stretched by this block (DUT) " "0,1"
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bitfld.long 0x0 5. "SYNC_DETECTED,synchronization detected." "0,1"
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bitfld.long 0x0 4. "STRETCH_DETECTED,stretch detected." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "STRETCH_COUNT,stretch count."
group.long 0x80++0x3
line.long 0x0 "I2C_CTRL_HS,I2C control for High-Speed mode"
bitfld.long 0x0 31. "HS_ENABLED,0': I2C Hs-mode is disabled " "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOVS_HS,Serial I2C interface low phase oversampling factor for I2C Hs-mode. LOVS_HS + 1 peripheral clock periods constitute the low phase of a bit period."
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hexmask.long.byte 0x0 0.--3. 1. "HOVS_HS,Serial I2C interface high phase oversampling factor for I2C Hs-mode. HOVS_HS + 1 peripheral clock periods constitute the high phase of a bit period."
group.long 0x200++0x7
line.long 0x0 "TX_CTRL,Transmitter control"
bitfld.long 0x0 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
rgroup.long 0x208++0x3
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
wgroup.long 0x240++0x3
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
group.long 0x300++0x7
line.long 0x0 "RX_CTRL,Receiver control"
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
rgroup.long 0x308++0x3
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
group.long 0x310++0x3
line.long 0x0 "RX_MATCH,Slave address and mask"
hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
rgroup.long 0x340++0x7
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
rgroup.long 0xE00++0x3
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
group.long 0xE80++0x3
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
group.long 0xE88++0x3
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xE8C++0x3
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xEC0++0x3
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
group.long 0xEC8++0x3
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xECC++0x3
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF00++0xB
line.long 0x0 "INTR_M,Master interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
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bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
line.long 0x4 "INTR_M_SET,Master interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF0C++0x3
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF40++0xB
line.long 0x0 "INTR_S,Slave interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
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bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
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bitfld.long 0x0 16. "I2C_RESTART,I2C slave RESTART received." "0,1"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF4C++0x3
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 16. "I2C_RESTART,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF80++0xB
line.long 0x0 "INTR_TX,Transmitter interrupt request"
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
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bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
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bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF8C++0x3
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
group.long 0xFC0++0xB
line.long 0x0 "INTR_RX,Receiver interrupt request"
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
newline
bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xFCC++0x3
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
tree.end
tree "SCB4"
base ad:0x40280000
group.long 0x0++0x3
line.long 0x0 "CTRL,Generic control"
bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
newline
bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
newline
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
newline
bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "0,1"
newline
bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
newline
bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element depending on physical SRAM cell data width." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
newline
bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0,1"
newline
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
newline
bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
newline
bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Generic status"
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
group.long 0x8++0x3
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
newline
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
rgroup.long 0xC++0x3
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
newline
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0,1"
newline
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
newline
hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
group.long 0x20++0x3
line.long 0x0 "SPI_CTRL,SPI control"
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
newline
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
newline
bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
newline
bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0,1"
newline
bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0,1"
newline
bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0,1"
newline
bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0,1"
newline
bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
newline
bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
newline
bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
newline
bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0,1"
newline
bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0,1"
newline
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
newline
bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0,1"
newline
bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0,1"
newline
bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "SPI_STATUS,SPI status"
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
group.long 0x28++0x7
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
bitfld.long 0x0 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive " "0: retain the level of last data bit,1: change to high"
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
group.long 0x40++0xB
line.long 0x0 "UART_CTRL,UART control"
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
line.long 0x8 "UART_RX_CTRL,UART receiver control"
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
newline
bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
rgroup.long 0x4C++0x3
line.long 0x0 "UART_RX_STATUS,UART receiver status"
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
group.long 0x50++0x3
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0,1"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0,1"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
group.long 0x60++0x3
line.long 0x0 "I2C_CTRL,I2C control"
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
rgroup.long 0x64++0x3
line.long 0x0 "I2C_STATUS,I2C status"
bitfld.long 0x0 24. "HS_MODE,this is to indicate I2C Hs-mode transfer " "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
group.long 0x68++0xF
line.long 0x0 "I2C_M_CMD,I2C master command"
bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
line.long 0x4 "I2C_S_CMD,I2C slave command"
bitfld.long 0x4 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected." "0,1"
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bitfld.long 0x4 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty." "0,1"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
line.long 0x8 "I2C_CFG,I2C configuration"
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0,1,2,3"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0,1"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0,1"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
line.long 0xC "I2C_STRETCH_CTRL,I2C stretch control"
hexmask.long.byte 0xC 0.--3. 1. "STRETCH_THRESHOLD,stretch threthold."
rgroup.long 0x78++0x3
line.long 0x0 "I2C_STRETCH_STATUS,I2C stretch status"
bitfld.long 0x0 8. "STRETCHING,I2C SCL is stretched by this block (DUT) " "0,1"
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bitfld.long 0x0 5. "SYNC_DETECTED,synchronization detected." "0,1"
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bitfld.long 0x0 4. "STRETCH_DETECTED,stretch detected." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "STRETCH_COUNT,stretch count."
group.long 0x80++0x3
line.long 0x0 "I2C_CTRL_HS,I2C control for High-Speed mode"
bitfld.long 0x0 31. "HS_ENABLED,0': I2C Hs-mode is disabled " "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOVS_HS,Serial I2C interface low phase oversampling factor for I2C Hs-mode. LOVS_HS + 1 peripheral clock periods constitute the low phase of a bit period."
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hexmask.long.byte 0x0 0.--3. 1. "HOVS_HS,Serial I2C interface high phase oversampling factor for I2C Hs-mode. HOVS_HS + 1 peripheral clock periods constitute the high phase of a bit period."
group.long 0x200++0x7
line.long 0x0 "TX_CTRL,Transmitter control"
bitfld.long 0x0 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
rgroup.long 0x208++0x3
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
wgroup.long 0x240++0x3
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
group.long 0x300++0x7
line.long 0x0 "RX_CTRL,Receiver control"
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
rgroup.long 0x308++0x3
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
group.long 0x310++0x3
line.long 0x0 "RX_MATCH,Slave address and mask"
hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
rgroup.long 0x340++0x7
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
rgroup.long 0xE00++0x3
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
group.long 0xE80++0x3
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
group.long 0xE88++0x3
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xE8C++0x3
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xEC0++0x3
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
group.long 0xEC8++0x3
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xECC++0x3
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF00++0xB
line.long 0x0 "INTR_M,Master interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
newline
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
line.long 0x4 "INTR_M_SET,Master interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF0C++0x3
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF40++0xB
line.long 0x0 "INTR_S,Slave interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
newline
bitfld.long 0x0 16. "I2C_RESTART,I2C slave RESTART received." "0,1"
newline
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
newline
bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
newline
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
newline
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
newline
bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
newline
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
newline
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF4C++0x3
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 16. "I2C_RESTART,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF80++0xB
line.long 0x0 "INTR_TX,Transmitter interrupt request"
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
newline
bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF8C++0x3
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
group.long 0xFC0++0xB
line.long 0x0 "INTR_RX,Receiver interrupt request"
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
newline
bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xFCC++0x3
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
tree.end
tree.end
tree "SPCIF (System Performance Controller Interface)"
base ad:0x40110000
group.long 0x0++0x3
line.long 0x0 "GEOMETRY,Flash/NVL geometry information"
bitfld.long 0x0 31. "DE_CPD_LP,0': SRAM busy wait loop has not been copied." "0,1"
hexmask.long.byte 0x0 24.--30. 1. "NVL,NVLatch size in Byte multiples (chip dependent):"
rbitfld.long 0x0 22.--23. "FLASH_ROW,Page size in 64 Byte multiples (chip dependent):" "0,1,2,3"
rbitfld.long 0x0 20.--21. "NUM_FLASH,Number of flash macros (chip dependent):" "0,1,2,3"
hexmask.long.byte 0x0 14.--19. 1. "SFLASH,Supervisory flash capacity in 256 Byte multiples (chip dependent). If multiple flash macros are present this field provides the supervisory flash capacity of all flash macros together:"
hexmask.long.word 0x0 0.--13. 1. "FLASH,Regular flash capacity in 256 Byte multiples (chip dependent). If multiple flash macros are present this field provides the flash capacity of all flash macros together:"
group.long 0x1C++0x3
line.long 0x0 "NVL_WR_DATA,NVL write data register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data to be written to NVLatch array"
group.long 0x7F0++0xB
line.long 0x0 "INTR,SPCIF interrupt request register"
bitfld.long 0x0 0. "TIMER,Timer counter value reaches '0'. Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit." "0,1"
line.long 0x4 "INTR_SET,SPCIF interrupt set request register"
bitfld.long 0x4 0. "TIMER,Write INTR_SET field with '1' to set corresponding INTR field." "0,1"
line.long 0x8 "INTR_MASK,SPCIF interrupt mask register"
bitfld.long 0x8 0. "TIMER,Mask for corresponding field in INTR register." "0,1"
rgroup.long 0x7FC++0x3
line.long 0x0 "INTR_MASKED,SPCIF interrupt masked request register"
bitfld.long 0x0 0. "TIMER,Logical and of corresponding request and mask fields." "0,1"
tree.end
tree "SRSSLT (System Resources Lite Subsystem)"
base ad:0x40030000
group.long 0x0++0x7
line.long 0x0 "PWR_CONTROL,Power Mode Control"
bitfld.long 0x0 23. "EXT_VCCD,Always write 0 except as noted below." "0,1"
rbitfld.long 0x0 18.--19. "SPARE,Spare AHB readback bits that are hooked to PWR_PWRSYS_TRIM1.SPARE_TRIM[1:0] through spare logic equivalent to bitwise inversion. Engineering only." "0,1,2,3"
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bitfld.long 0x0 17. "OVER_TEMP_THRESH,Over-temperature threshold." "0: TEMP_HIGH condition occurs between 120C and 125C,1: TEMP_HIGH condition occurs between 60C and 75C"
bitfld.long 0x0 16. "OVER_TEMP_EN,Enables the die over temperature sensor. Must be enabled when using the TEMP_HIGH interrupt." "0,1"
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rbitfld.long 0x0 5. "LPM_READY,Indicates whether the low power mode regulator is ready to enter DEEPSLEEP mode." "0: If DEEPSLEEP mode is requested,1: Normal operation"
rbitfld.long 0x0 4. "DEBUG_SESSION,Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)" "0: No debug session active,1: Debug session is active"
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hexmask.long.byte 0x0 0.--3. 1. "POWER_MODE,Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon."
line.long 0x4 "PWR_KEY_DELAY,Power System Key&Delay Register"
hexmask.long.word 0x4 0.--9. 1. "WAKEUP_HOLDOFF,Delay to wait for references to settle on wakeup from deepsleep. BOD is ignored and system does not resume until this delay expires. Note that the same delay on POR is hard-coded. The default assumes the output of the predivider is 48MHz.."
group.long 0xC++0x3
line.long 0x0 "PWR_DDFT_SELECT,Power DDFT Mode Selection Register"
hexmask.long.byte 0x0 4.--7. 1. "DDFT1_SEL,Select signal for power DDFT output #1"
hexmask.long.byte 0x0 0.--3. 1. "DDFT0_SEL,Select signal for power DDFT output #0"
group.long 0x14++0x3
line.long 0x0 "TST_MODE,Test Mode Control Register"
bitfld.long 0x0 31. "TEST_MODE,Setting this bit will prevent BootROM from yielding execution to Flash image." "0: Normal operation mode,1: Test mode"
rbitfld.long 0x0 30. "TEST_KEY_DFT_EN,This bit is set when a XRES test mode key is shifted in. It is the value of the test_key_dft_en signal. When this bit is set the BootROM will not yield execution to the FLASH image (same function as setting TEST_MODE bit below)." "0,1"
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bitfld.long 0x0 28. "BLOCK_ALT_XRES,Relevant only for parts that have the alternate XRES mechanism of overloading a GPIO pin temporarily as alternate XRES during test. When set this bit blocks the alternate XRES function such that the pin can be used for normal I/O or for.." "0,1"
rbitfld.long 0x0 2. "SWD_CONNECTED,0: SWD not active" "0: SWD not active,1: SWD activated"
group.long 0x28++0x13
line.long 0x0 "CLK_SELECT,Clock Select Register"
bitfld.long 0x0 6.--7. "SYSCLK_DIV,Select clk_sys prescaler value." "0: clk_sys= clk_hf/1,1: clk_sys= clk_hf/2,2: clk_sys= clk_hf/4,3: clk_sys= clk_hf/8"
bitfld.long 0x0 4.--5. "PUMP_SEL,Selects clock source for charge pump clock. This clock is not guaranteed to be glitch free when changing any of its sources or settings." "0: No clock connect to gnd,1: Use main IMO output,2: Use clk_hf (using selected source after..,?"
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bitfld.long 0x0 2.--3. "HFCLK_DIV,Selects clk_hf predivider value." "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8"
bitfld.long 0x0 0.--1. "HFCLK_SEL,Selects a source for clk_hf and dsi_in[0]. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior." "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator or PLL..,?"
line.long 0x4 "CLK_ILO_CONFIG,ILO Configuration"
bitfld.long 0x4 31. "ENABLE,Master enable for ILO oscillator. This bit is hardware set whenever the WDT_DISABLE_KEY is not set to the magic value." "0,1"
line.long 0x8 "CLK_IMO_CONFIG,IMO Configuration"
bitfld.long 0x8 31. "ENABLE,Master enable for IMO oscillator. Clearing this bit will disable the IMO. Don't do this if the system is running off it." "0,1"
line.long 0xC "CLK_DFT_SELECT,Clock DFT Mode Selection Register"
bitfld.long 0xC 14. "DFT_EDGE1,Edge sensitivity for in-line divider on output #1 (only relevant when DIV1>0)." "0: Use posedge for divider,1: Use negedge for divider"
bitfld.long 0xC 12.--13. "DFT_DIV1,DFT Output Divide Down." "0: Direct Output,1: Divide by 2,2: Divide by 4,3: Divide by 8"
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hexmask.long.byte 0xC 8.--11. 1. "DFT_SEL1,Select signal for DFT output #1"
bitfld.long 0xC 6. "DFT_EDGE0,Edge sensitivity for in-line divider on output #0 (only relevant when DIV0>0)." "0: Use posedge for divider,1: Use negedge for divider"
newline
bitfld.long 0xC 4.--5. "DFT_DIV0,DFT Output Divide Down." "0: Direct Output,1: Divide by 2,2: Divide by 4,3: Divide by 8"
hexmask.long.byte 0xC 0.--3. 1. "DFT_SEL0,Select signal for DFT output #0"
line.long 0x10 "WDT_DISABLE_KEY,Watchdog Disable Key Register"
hexmask.long 0x10 0.--31. 1. "KEY,Disables WDT reset when equal to 0xACED8865. The WDT reset functions normally for any other setting."
rgroup.long 0x3C++0x3
line.long 0x0 "WDT_COUNTER,Watchdog Counter Register"
hexmask.long.word 0x0 0.--15. 1. "COUNTER,Current value of WDT Counter"
group.long 0x40++0xF
line.long 0x0 "WDT_MATCH,Watchdog Match Register"
hexmask.long.byte 0x0 16.--19. 1. "IGNORE_BITS,The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Note that certain products may enforce a minimum.."
hexmask.long.word 0x0 0.--15. 1. "MATCH,Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match)."
line.long 0x4 "SRSS_INTR,SRSS Interrupt Register"
bitfld.long 0x4 1. "TEMP_HIGH,Regulator over-temp interrupt. This interrupt can occur when a short circuit exists on the vccd pin or when extreme loads are applied on IO-cells causing the die to overheat. Firmware is encourage to shutdown all IO cells and then go to.." "0,1"
bitfld.long 0x4 0. "WDT_MATCH,WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. Clearing this bit also feeds the watch dog. Missing 2 interrupts in a row will generate brown-out reset. Due to internal synchronization it takes 2 SYSCLK cycles to.." "0,1"
line.long 0x8 "SRSS_INTR_SET,SRSS Interrupt Set Register"
bitfld.long 0x8 1. "TEMP_HIGH,Writing 1 to this bit internally sets the overtemp interrupt. This can be observed by reading SRSS_INTR.TEMP_HIGH. This bit always reads back as zero." "0,1"
line.long 0xC "SRSS_INTR_MASK,SRSS Interrupt Mask Register"
bitfld.long 0xC 1. "TEMP_HIGH,Masks REG_OVERTEMP interrupt" "0,1"
bitfld.long 0xC 0. "WDT_MATCH,Clearing this bit will not forward the interrupt to the CPU. It will not however disable the WDT reset generation on 2 missed interrupts." "0,1"
group.long 0x54++0x3
line.long 0x0 "RES_CAUSE,Reset Cause Observation Register"
bitfld.long 0x0 4. "RESET_SOFT,Cortex-M0 requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware." "0,1"
bitfld.long 0x0 3. "RESET_PROT_FAULT,A protection violation occurred that requires a RESET. This includes but is not limited to hitting a debug breakpoint while in Privileged Mode." "0,1"
newline
bitfld.long 0x0 0. "RESET_WDT,A WatchDog Timer reset has occurred since last power cycle." "0,1"
group.long 0xF08++0x13
line.long 0x0 "CLK_IMO_SELECT,IMO Frequency Select Register"
bitfld.long 0x0 0.--2. "FREQ,Select operating frequency" "0: IMO runs at 24 MHz,1: IMO runs at 28 MHz,2: IMO runs at 32 MHz,3: IMO runs at 36 MHz,4: IMO runs at 40 MHz,5: IMO runs at 44 MHz,6: IMO runs at 48 MHz,?"
line.long 0x4 "CLK_IMO_TRIM1,IMO Trim Register"
hexmask.long.byte 0x4 0.--7. 1. "OFFSET,Frequency trim bits. These bits are determined at manufacturing time for each FREQ setting in CLK_IMO_SELECT and stored in SFLASH. This field is hardware updated during USB osclock mode or when a WCO uses this mechanism for PLL locking the WCO."
line.long 0x8 "CLK_IMO_TRIM2,IMO Trim Register"
bitfld.long 0x8 0.--2. "FSOFFSET,Frequency trim bits. These bits are not trimmed during manufacturing and kept at 0 under normal operation. This field is hardware updated during USB osclock mode or when a WCO uses this mechanism for PLL locking the WCO. This is only.." "0,1,2,3,4,5,6,7"
line.long 0xC "PWR_PWRSYS_TRIM1,Power System Trim Register"
hexmask.long.byte 0xC 4.--7. 1. "SPARE_TRIM,Active-Reference temperature compensation trim (repurposed from spare bits)."
hexmask.long.byte 0xC 0.--3. 1. "DPSLP_REF_TRIM,Trims the DeepSleep reference that is used by the DeepSleep regulator and DeepSleep power comparator."
line.long 0x10 "CLK_IMO_TRIM3,IMO Trim Register"
bitfld.long 0x10 5.--6. "TCTRIM,IMO temperature compesation trim. These bits are determined at manufacturing time to adjust for temperature dependence. This bits are dependent on frequency and need to be changed using the Cypress provided frequency change algorithm." "0,1,2,3"
hexmask.long.byte 0x10 0.--4. 1. "STEPSIZE,IMO trim stepsize bits. These bits are determined at manufacturing time to adjust for process variation. They are used to tune the stepsize of the FSOFFSET and OFFSET trims."
tree.end
tree "TCPWM (Timer/Counter/PWM)"
base ad:0x40200000
group.long 0x0++0x3
line.long 0x0 "CTRL,TCPWM control register 0."
hexmask.long.byte 0x0 0.--7. 1. "COUNTER_ENABLED,Counter enables for counters 0 up to CNT_NR-1."
group.long 0x8++0x3
line.long 0x0 "CMD,TCPWM command register."
hexmask.long.byte 0x0 24.--31. 1. "COUNTER_START,Counters SW start trigger. For HW behavior see COUNTER_CAPTURE field."
hexmask.long.byte 0x0 16.--23. 1. "COUNTER_STOP,Counters SW stop trigger. For HW behavior see COUNTER_CAPTURE field."
hexmask.long.byte 0x0 8.--15. 1. "COUNTER_RELOAD,Counters SW reload trigger. For HW behavior see COUNTER_CAPTURE field."
hexmask.long.byte 0x0 0.--7. 1. "COUNTER_CAPTURE,Counters SW capture trigger. When written with '1' a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is.."
rgroup.long 0xC++0x3
line.long 0x0 "INTR_CAUSE,TCPWM Counter interrupt cause register."
hexmask.long.byte 0x0 0.--7. 1. "COUNTER_INT,Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED the associated interrupt field is immediately set to '0'."
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x40200100 ad:0x40200140 ad:0x40200180 ad:0x402001C0 ad:0x40200200 ad:0x40200240 ad:0x40200280 ad:0x402002C0)
tree "CNT[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CTRL,Counter control register"
bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,?,2: Capture mode,3: Quadrature encoding mode,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,?"
bitfld.long 0x0 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4)." "0: X1 encoding (QUAD mode),1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),?"
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit control field. In PWM_DT mode this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes the lower 3 bits of this field determine pre-scaling of the selected counter.."
bitfld.long 0x0 3. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0,1"
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bitfld.long 0x0 2. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0,1"
bitfld.long 0x0 1. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM PWM_DT and PWM_PR modes." "0,1"
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bitfld.long 0x0 0. "AUTO_RELOAD_CC,Specifies switching of the CC and buffered CC values. This field has a function in TIMER PWM PWM_DT and PWM_PR modes." "0: never switch,?"
rgroup.long ($2+0x4)++0x3
line.long 0x0 "STATUS,Counter status register"
bitfld.long 0x0 31. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion. In all other modes this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality."
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
group.long ($2+0x8)++0x13
line.long 0x0 "COUNTER,Counter count register"
hexmask.long.word 0x0 0.--15. 1. "COUNTER,16-bit counter value. It is advised to not write to this field when the counter is running."
line.long 0x4 "CC,Counter compare/capture register"
hexmask.long.word 0x4 0.--15. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
line.long 0x8 "CC_BUFF,Counter buffered compare/capture register"
hexmask.long.word 0x8 0.--15. 1. "CC,Additional buffer for counter CC register."
line.long 0xC "PERIOD,Counter period register"
hexmask.long.word 0xC 0.--15. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
line.long 0x10 "PERIOD_BUFF,Counter buffered period register"
hexmask.long.word 0x10 0.--15. 1. "PERIOD,Additional buffer for counter PERIOD register."
group.long ($2+0x20)++0xB
line.long 0x0 "TR_CTRL0,Counter trigger control register 0"
hexmask.long.byte 0x0 16.--19. 1. "START_SEL,Selects one of the 16 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
hexmask.long.byte 0x0 12.--15. 1. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger. In PWM PWM_DT and PWM_PR modes this is the kill trigger. In these modes the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the.."
newline
hexmask.long.byte 0x0 8.--11. 1. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger. In QUAD mode this is the index or revolution pulse. In this mode it will update the counter with the value in the TCPWM_CNTn_PERIOD register."
hexmask.long.byte 0x0 4.--7. 1. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger. In QUAD mode this is the first phase (phi A). Default setting selects input trigger 1 which is always '1'."
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hexmask.long.byte 0x0 0.--3. 1. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. Input trigger 2 is the first external trigger line (tcpwm.tr_in[0])."
line.long 0x4 "TR_CTRL1,Counter trigger control register 1"
bitfld.long 0x4 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
bitfld.long 0x4 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0x4 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
bitfld.long 0x4 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
newline
bitfld.long 0x4 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
line.long 0x8 "TR_CTRL2,Counter trigger control register 2"
bitfld.long 0x8 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
bitfld.long 0x8 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x8 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
group.long ($2+0x30)++0xB
line.long 0x0 "INTR,Interrupt request register."
bitfld.long 0x0 1. "CC_MATCH,Counter matches CC register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
line.long 0x4 "INTR_SET,Interrupt set request register."
bitfld.long 0x4 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_MASK,Interrupt mask register."
bitfld.long 0x8 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long ($2+0x3C)++0x3
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
bitfld.long 0x0 1. "CC_MATCH,Logical and of corresponding request and mask bits." "0,1"
bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
tree.end
repeat.end
tree.end
tree "WCO (Watch Crystal Oscillator)"
base ad:0x40220000
group.long 0x0++0x3
line.long 0x0 "CONFIG,WCO Configuration Register"
bitfld.long 0x0 31. "IP_ENABLE,Master enable for IP - disables both WCO and DPLL" "0,1"
bitfld.long 0x0 30. "DPLL_ENABLE,Enable DPLL operation. The Oscillator is specified to be stable after 500 ms thus the DPLL should be asserted no sooner than that after IP_ENABLE is set." "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "ENBUS,Test Mode Control bits"
bitfld.long 0x0 2. "EXT_INPUT_EN,Disables the load resistor and allows external clock input for pad_xin" "0,1"
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bitfld.long 0x0 1. "LPM_AUTO,Automatically control low power mode (only relevant when LPM_EN=0):" "0: Do not enter low power mode,1: Enter low power mode"
bitfld.long 0x0 0. "LPM_EN,Force block into Low Power Mode:" "0: Do not force low power mode,1: Force low power mode"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,WCO Status Register"
bitfld.long 0x0 0. "OUT_BLNK_A,Indicates that output has transitioned - This bit is intended for Test Mode Only and is not a reliable indicator." "0,1"
group.long 0x8++0x3
line.long 0x0 "DPLL,WCO DPLL Register"
hexmask.long.byte 0x0 22.--29. 1. "DPLL_LF_LIMIT,Maximum IMO offset allowed (used to prevent DPLL dynamics from selecting an IMO frequency that the logic cannot support)"
bitfld.long 0x0 19.--21. "DPLL_LF_PGAIN,DPLL Loop Filter Proportionial Gain Setting" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 16.--18. "DPLL_LF_IGAIN,DPLL Loop Filter Integral Gain Setting" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x0 0.--10. 1. "DPLL_MULT,Multiplier to determine IMO frequency in multiples of the WCO frequency"
rgroup.long 0x200++0x7
line.long 0x0 "WDT_CTRLOW,Watchdog Counters 0/1"
hexmask.long.word 0x0 16.--31. 1. "WDT_CTR1,Current value of WDT Counter 1"
hexmask.long.word 0x0 0.--15. 1. "WDT_CTR0,Current value of WDT Counter 0"
line.long 0x4 "WDT_CTRHIGH,Watchdog Counter 2"
hexmask.long 0x4 0.--31. 1. "WDT_CTR2,Current value of WDT Counter 2"
group.long 0x208++0xF
line.long 0x0 "WDT_MATCH,Watchdog counter match values"
hexmask.long.word 0x0 16.--31. 1. "WDT_MATCH1,Match value for Watchdog Counter 1"
hexmask.long.word 0x0 0.--15. 1. "WDT_MATCH0,Match value for Watchdog Counter 0"
line.long 0x4 "WDT_CONFIG,Watchdog Counters Configuration"
bitfld.long 0x4 30.--31. "LFCLK_SEL,N/A" "0,1,2,3"
hexmask.long.byte 0x4 24.--28. 1. "WDT_BITS2,Bit to observe for WDT_INT2:"
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bitfld.long 0x4 16. "WDT_MODE2,Watchdog Counter 2 Mode." "0: Free running counter with no interrupt requests,1: Free running counter with interrupt request when.."
bitfld.long 0x4 11. "WDT_CASCADE1_2,Cascade Watchdog Counters 1 2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters." "0: Independent counters,1: Cascaded counters"
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bitfld.long 0x4 10. "WDT_CLEAR1,Clear Watchdog Counter when WDT_CTR1=WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1)." "0: Free running counter,1: Clear on match"
bitfld.long 0x4 8.--9. "WDT_MODE1,Watchdog Counter Action on Match (WDT_CTR1=WDT_MATCH1)." "0: Do nothing,1: WDT_MATCH1),2: Assert WDT Reset - Not Supported - here for..,3: Assert WDT_INTx assert WDT Reset after 3rd.."
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bitfld.long 0x4 3. "WDT_CASCADE0_1,Cascade Watchdog Counters 0 1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0." "0: Independent counters,1: Cascaded counters"
bitfld.long 0x4 2. "WDT_CLEAR0,Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1)." "0: Free running counter,1: Clear on match"
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bitfld.long 0x4 0.--1. "WDT_MODE0,Watchdog Counter Action on Match (WDT_CTR0=WDT_MATCH0)." "0: WDT_MATCH0),1: Assert WDT_INTx,2: Assert WDT Reset - Not Supported - here for..,3: Assert WDT_INTx assert WDT Reset after 3rd.."
line.long 0x8 "WDT_CONTROL,Watchdog Counters Control"
bitfld.long 0x8 19. "WDT_RESET2,Resets counter 2 back to 0000_0000. Hardware will reset this bit after counter was reset. This will take several LFCLK cycles to take effect. Wait until the reset completes before enabling the WDT." "0,1"
bitfld.long 0x8 18. "WDT_INT2,WDT Interrupt Request. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. After W1C WDT_CONTROL must be read for the hardware to internally remove the clear flag. Failure to do this may result.." "0,1"
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rbitfld.long 0x8 17. "WDT_ENABLED2,Indicates actual state of counter. May lag WDT_ENABLE2 by up to 3 LFCLK cycles. After changing WDT_ENABLE2 do not enter DEEPSLEEP mode until this field acknowledges the change." "0,1"
bitfld.long 0x8 16. "WDT_ENABLE2,Enable Counter 2" "0: Counter is disabled,1: Counter is enabled"
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bitfld.long 0x8 11. "WDT_RESET1,Resets counter 1 back to 0000. Hardware will reset this bit after counter was reset. This will take several LFCLK cycles to take effect. Wait until the reset completes before enabling the WDT." "0,1"
bitfld.long 0x8 10. "WDT_INT1,WDT Interrupt Request. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. After W1C WDT_CONTROL must be read for the hardware to internally remove the clear flag. Failure to do this may.." "0,1"
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rbitfld.long 0x8 9. "WDT_ENABLED1,Indicates actual state of counter. May lag WDT_ENABLE1 by up to 3 LFCLK cycles. After changing WDT_ENABLE1 do not enter DEEPSLEEP mode until this field acknowledges the change." "0,1"
bitfld.long 0x8 8. "WDT_ENABLE1,Enable Counter 1" "0: Counter is disabled,1: Counter is enabled"
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bitfld.long 0x8 3. "WDT_RESET0,Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take several LFCLK cycles to take effect. Wait until the reset completes before enabling the WDT." "0,1"
bitfld.long 0x8 2. "WDT_INT0,WDT Interrupt Request. This bit is set by hardware as configured by this registers. This bit must be cleared by firmware. Clearing this bit also prevents Reset from happening when WDT_MODEx=3. After W1C WDT_CONTROL must be read for the.." "0,1"
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rbitfld.long 0x8 1. "WDT_ENABLED0,Indicates actual state of counter. May lag WDT_ENABLE0 by up to 3 LFCLK cycles. After changing WDT_ENABLE0 do not enter DEEPSLEEP mode until this field acknowledges the change." "0,1"
bitfld.long 0x8 0. "WDT_ENABLE0,Enable Counter 0" "0: Counter is disabled,1: Counter is enabled"
line.long 0xC "WDT_CLKEN,Watchdog Counters Clock Enable"
bitfld.long 0xC 1. "CLK_ILO_EN_FOR_WDT,Enables the ILO clock for use by the WDT logic. Wait at least 4 ILO clock cycles for a change to take effect. Must be 0 when switching WDT_CONFIG.LFCLK_SEL. Should be 0 if CLK_WCO_EN_FOR_WDT=1." "0,1"
bitfld.long 0xC 0. "CLK_WCO_EN_FOR_WDT,Enables the WCO clock for use by the WDT logic. Wait at least 4 WCO clock cycles for a change to take effect. Must be 0 when switching WDT_CONFIG.LFCLK_SEL. Should be 0 if CLK_ILO_EN_FOR_WDT=1" "0,1"
group.long 0xF00++0x3
line.long 0x0 "TRIM,WCO Trim Register"
bitfld.long 0x0 4.--5. "LPM_GM,GM setting for LPM (bandwidth = DC/ms) - Used when WCO.LPM_AUTO=0 or when LPM_AUTO=1 and not in DeepSleep mode." "0,1,2,3"
bitfld.long 0x0 0.--2. "XGM,Amplifier GM setting - Used when WCO.LPM_AUTO=0 or when LPM_AUTO=1 and not in DeepSleep mode." "0,1,2,3,4,5,6,7"
tree.end
AUTOINDENT.OFF
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