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Gen4_R-Car_Trace32/2_Trunk/perpsoc4100.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: PSoC 4100 On-Chip Peripherals
; @Props: Released
; @Author: KMB, DAB
; @Changelog: 2021-08-31 KMB
; 2022-01-20 DAB
; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
; @Doc: psoc4100s.svd, psoc4100smax.svd, psoc4100sp.svd, psoc4100sp256kb.svd
; @Core: Cortex-M0+
; @Chip: CY8C414*
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perpsoc4100.per 14191 2022-01-27 13:52:46Z kwisniewski $
config 16. 8.
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
sif cpuis("CY8C4147*")||cpuis("CY8C4146A*")
tree "CAN (CAN Controller)"
base ad:0x402E0000
group.long 0x00++0x03
line.long 0x00 "INT_STATUS,Interrupt Status"
bitfld.long 0x00 15. "SST_FAILURE,Single shot transmission failure" "0: Normal operation,1: A buffer set for single shot transmission"
bitfld.long 0x00 14. "STUCK_AT_0,Stuck at dominant error" "0: Normal Operation,1: Indicates if the rx input remains stuack at 0"
newline
bitfld.long 0x00 13. "RTR_MSG,RTR auto-reply message sent" "0: Normal operation,1: Indicates that a RTR auto-reply message was.."
bitfld.long 0x00 12. "RX_MSG,Indicates that a message was received" "0: Normal operation,1: A new message was successfully received and"
newline
bitfld.long 0x00 11. "TX_MSG,Indicates that a message was sent" "0: Normal operation,1: A message was successfully sent from a"
bitfld.long 0x00 10. "RX_MSG_LOSS,when a new message arrives but the RxMessage flag MSG_AV is set and LINK_FLAG is not set RX_MSG_LOSS is set and the new message is discarded" "0,1"
newline
bitfld.long 0x00 9. "BUS_OFF,The CAN has reached the bus off state" "0,1"
bitfld.long 0x00 8. "CRC_ERR,A CAN CRC error was detected" "0,1"
newline
bitfld.long 0x00 7. "FORM_ERR,A CAN message format error was detected please ignore this interrupt when ERROR_STATUS.ERROR_STATE=2'B1x" "0,1"
bitfld.long 0x00 6. "ACK_ERR,An CAN message acknowledge error was detected" "0,1"
newline
bitfld.long 0x00 5. "STUFF_ERR,A bit stuffing error was detected" "0,1"
bitfld.long 0x00 4. "BIT_ERR,A bit error was detected" "0,1"
newline
bitfld.long 0x00 3. "OVR_LOAD,An overload frame was received or reactive overload frame condition is detected (ISO-11898-1 section 10.11)" "0,1"
bitfld.long 0x00 2. "ARB_LOSS,The arbitration was lost while sending a message" "0,1"
group.long 0x04++0x03
line.long 0x00 "INT_EBL,Interrupt Enable"
bitfld.long 0x00 15. "SST_FAILURE_ENBL,See description in INT_STATUS" "0,1"
bitfld.long 0x00 14. "STUCK_AT_0_ENBL,See description in INT_STATUS" "0,1"
newline
bitfld.long 0x00 13. "RTR_MSG_ENBL,See description in INT_STATUS" "0,1"
bitfld.long 0x00 12. "RX_MSG_ENBL,See description in INT_STATUS" "0,1"
newline
bitfld.long 0x00 11. "TX_MSG_ENBL,See description in INT_STATUS" "0,1"
bitfld.long 0x00 10. "RX_MSG_LOSS,See description in INT_STATUS" "0,1"
newline
bitfld.long 0x00 9. "BUS_OFF_ENBL,See description in INT_STATUS" "0,1"
bitfld.long 0x00 8. "CRC_ERR_ENBL,See description in INT_STATUS" "0,1"
newline
bitfld.long 0x00 7. "FORM_ERR_ENBL,See description in INT_STATUS" "0,1"
bitfld.long 0x00 6. "ACK_ERR_ENBL,See description in INT_STATUS" "0,1"
newline
bitfld.long 0x00 5. "STUFF_ERR_ENBL,See description in INT_STATUS" "0,1"
bitfld.long 0x00 4. "BIT_ERR_ENBL,See description in INT_STATUS" "0,1"
newline
bitfld.long 0x00 3. "OVR_LOAD_ENBL,See description in INT_STATUS" "0,1"
bitfld.long 0x00 2. "ARB_LOSS_ENBL,See description in INT_STATUS" "0,1"
newline
bitfld.long 0x00 0. "GLOBAL_INT_ENBL,global interrupt enable flag '0': All interrupts are disabled '1': Enabled interrupt sources are available" "0,1"
rgroup.long 0x08++0x03
line.long 0x00 "BUFFER_STATUS,RxMessage and TxMessage Buffer Status"
bitfld.long 0x00 23. "TX7_REQ_PEND,TxMessage Buffer Status" "0,1"
bitfld.long 0x00 22. "TX6_REQ_PEND,TxMessage Buffer Status" "0,1"
newline
bitfld.long 0x00 21. "TX5_REQ_PEND,TxMessage Buffer Status" "0,1"
bitfld.long 0x00 20. "TX4_REQ_PEND,TxMessage Buffer Status" "0,1"
newline
bitfld.long 0x00 19. "TX3_REQ_PEND,TxMessage Buffer Status" "0,1"
bitfld.long 0x00 18. "TX2_REQ_PEND,TxMessage Buffer Status" "0,1"
newline
bitfld.long 0x00 17. "TX1_REQ_PEND,TxMessage Buffer Status" "0,1"
bitfld.long 0x00 16. "TX0_REQ_PEND,TxMessage Buffer Status" "0,1"
newline
bitfld.long 0x00 15. "RX15_MSG_AV,RxMessage Buffer Status" "0,1"
bitfld.long 0x00 14. "RX14_MSG_AV,RxMessage Buffer Status" "0,1"
newline
bitfld.long 0x00 13. "RX13_MSG_AV,RxMessage Buffer Status" "0,1"
bitfld.long 0x00 12. "RX12_MSG_AV,RxMessage Buffer Status" "0,1"
newline
bitfld.long 0x00 11. "RX11_MSG_AV,RxMessage Buffer Status" "0,1"
bitfld.long 0x00 10. "RX10_MSG_AV,RxMessage Buffer Status" "0,1"
newline
bitfld.long 0x00 9. "RX9_MSG_AV,RxMessage Buffer Status" "0,1"
bitfld.long 0x00 8. "RX8_MSG_AV,RxMessage Buffer Status" "0,1"
newline
bitfld.long 0x00 7. "RX7_MSG_AV,RxMessage Buffer Status" "0,1"
bitfld.long 0x00 6. "RX6_MSG_AV,RxMessage Buffer Status" "0,1"
newline
bitfld.long 0x00 5. "RX5_MSG_AV,RxMessage Buffer Status" "0,1"
bitfld.long 0x00 4. "RX4_MSG_AV,RxMessage Buffer Status" "0,1"
newline
bitfld.long 0x00 3. "RX3_MSG_AV,RxMessage Buffer Status" "0,1"
bitfld.long 0x00 2. "RX2_MSG_AV,RxMessage Buffer Status" "0,1"
newline
bitfld.long 0x00 1. "RX1_MSG_AV,RxMessage Buffer Status" "0,1"
bitfld.long 0x00 0. "RX0_MSG_AV,RxMessage Buffer Status" "0,1"
rgroup.long 0x0C++0x03
line.long 0x00 "ERROR_STATUS,CAN Error Status"
bitfld.long 0x00 19. "RXGTE96,The Rx error counter is greater or equal 96" "0,1"
bitfld.long 0x00 18. "TXGTE96,The Tx error counter is greater or equal 96" "0,1"
newline
bitfld.long 0x00 16.--17. "ERROR_STATE,The error state of the CAN node: '00': error active (normal operation) '01': error passive '1x': bus off" "0,1,2,3"
hexmask.long.byte 0x00 8.--15. 1. "RX_ERR_CNT,The receive error counter according to the CAN 2.0 specification"
newline
hexmask.long.byte 0x00 0.--7. 1. "TX_ERR_CNT,The transmitter error counter according to the CAN standard"
group.long 0x10++0x03
line.long 0x00 "COMMAND,CAN Command Register"
rbitfld.long 0x00 28.--31. "IP_MAJOR_VERSION,IP Major Version Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 24.--27. "IP_MINOR_VERSION,IP Minor Version Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 16.--23. 1. "IP_REV_NUMBER,IP Revision Number"
bitfld.long 0x00 3. "SRAM_TEST,SRAM test mode '0': Normal operation '1': Enable SRAM test mode it can be set only when the IP is stopped (COMMAND.RUN=0 and really finished transition from run mode) this mode will not be used so it should never be set" "0,1"
newline
bitfld.long 0x00 2. "LOOPBACK_TEST,TEST_MODE[2]" "0: normal operation,1: Listen-only mode The output is held at 'R'.."
bitfld.long 0x00 1. "LISTEN,TEST_MODE[1]" "0,1"
newline
bitfld.long 0x00 0. "RUN,Run/Stop mode: '0': Sets the CAN controller into stop mode" "0,1"
group.long 0x14++0x03
line.long 0x00 "CONFIG,CAN Configuration"
abitfld.long 0x00 16.--30. "CFG_BITRATE,Prescaler for generating the time quantum which defines the TQ" "0x0000=0: One time quantum equals 1 clock cycle,0x0001=1: One time quantum equals 2 clock cycles,0x7FFF=32767: One time quantum equals 32768.."
bitfld.long 0x00 14. "ECR_MODE,Error Capture mode" "0: Free running,1: Capture mode"
newline
bitfld.long 0x00 13. "SWAP_ENDIAN,Swap Endian - the byte position of the CAN receive and transmit data fields can be modified to match the endian setting of the processor or the used CAN protocol" "0: CAN data byte position is not swapped (big..,1: CAN data byte position is swapped (little.."
bitfld.long 0x00 12. "CFG_ARBITER,Transmit buffer arbiter '0': Round robin arbitration '1': Fixed priority arbitration" "0,1"
newline
bitfld.long 0x00 8.--11. "CFG_TSEG1,Time segment 1 Length of the first time segment: tseg1 = cfg_tseg1 + 1 Time segment 1 includes the propagation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--7. "CFG_TSEG2,Time segment 2 Length of the second time segment: tseg2 = cfg_tseg2 + 1 cfg_tseg2=0 is not allowed cfg_tseg2=1 is only allowed in direct sampling mode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "AUTO_RESTART,'0': After bus-off the CAN core must be restarted by setting COMMAND.RUN register" "0,1"
bitfld.long 0x00 2.--3. "CFG_SJW,Synchronization jump width - 1 sjw <= tseg1 and sjw <= tseg2" "0,1,2,3"
newline
bitfld.long 0x00 1. "SAMPLING_MODE,CAN bus bit sampling '0': One sampling point is used in the receiver path '1': 3 sampling points with majority decision are used" "0,1"
bitfld.long 0x00 0. "EDGE_MODE,CAN bus synchronization logic '0': Edge from 'R' to 'D' is used for synchronization '1': Both edges are used Note only 'R' to 'D' edge shall be used for synchronization per ISO-11898-1 spec so this bit should always be set 0 (by default)" "0,1"
group.long 0x18++0x03
line.long 0x00 "ECR,Error Capture Register"
rbitfld.long 0x00 12.--16. "FIELD,Field" "0: Stopped,1: Synchronize,?,?,?,5: Interframe,6: Bus Idle,7: Start of Frame,8: Arbitration,9: Control,10: Data,11: CRC,12: ACK,13: End of frame,?,?,16: Error flag,17: Error echo,18: Error delimiter,?,?,?,?,?,24: Overload flag,25: Overload echo,26: Overload delimiter Others,?..."
rbitfld.long 0x00 6.--11. "BIT,Bit number inside of Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 5. "TX_MODE,TX Mode" "0: No status,1: CAN Controller is"
rbitfld.long 0x00 4. "RX_MODE,RX Mode" "0: No status,1: CAN Controller is receiver"
newline
rbitfld.long 0x00 1.--3. "ERROR_TYPE,Error type" "0: Arbitration loss,1: Bit Error,2: Bit Stuffing Error,3: Acknowledge Error,4: Form Error,5: CRC Error Others,?..."
bitfld.long 0x00 0. "ECR_STATUS,ECR STATUS" "0: ECR register captured an error or it is in free,1: ECR register is armed"
group.long 0x400++0x03
line.long 0x00 "CNTL,Control"
bitfld.long 0x00 31. "IP_ENABLE,IP Enable/Disable" "0: IP is disabled/reset,1: IP is enabled/running"
bitfld.long 0x00 0. "TT_ENABLE,TTCAN enable/disable" "0: TTCAN is disabled Interrupt_can is sourced from,1: TTCAN is enabled Interrupt_can is sourced from"
group.long 0x404++0x03
line.long 0x00 "TTCAN_COUNTER,TTCAN Level1 16-Bit local time counter"
hexmask.long.word 0x00 16.--31. 1. "LOCAL_TIME,Bit time counter in TTCAN level 1"
group.long 0x408++0x03
line.long 0x00 "TTCAN_COMPARE,TTCAN Level1 compare configuration"
hexmask.long.word 0x00 16.--31. 1. "TIME_MARK,compare target when TTCAN_COUNTER.LOCAL_TIME counts to TT_COMPARE INTR_CAN.TT_COMPARE will be set"
rgroup.long 0x40C++0x03
line.long 0x00 "TTCAN_CAPTURE,TTCAN Level1 capture configuration"
hexmask.long.word 0x00 16.--31. 1. "SYNC_MARK,copy TTCAN_COUNTER.LOCAL_TIME to TTCAN_CAPTURE.SYNC_MARK when SOF detected"
group.long 0x410++0x03
line.long 0x00 "TTCAN_TIMING,TTCAN Level1 timing configuration duplicate of CONFIG fields"
abitfld.long 0x00 16.--30. "CFG_BITRATE,Prescaler for generating the time quantum which defines the TQ" "0x0000=0: One time quantum equals 1 clock cycle,0x0001=1: One time quantum equals 2 clock cycles,0x7FFF=32767: One time quantum equals 32768.."
bitfld.long 0x00 8.--11. "CFG_TSEG1,Time segment 1 Length of the first time segment: tseg1 = cfg_tseg1 + 1 Time segment 1 includes the propagation time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--7. "CFG_TSEG2,Time segment 2 Length of the second time segment: tseg2 = cfg_tseg2 + 1 cfg_tseg2=0 is not allowed cfg_tseg2=1 is only allowed in direct sampling mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. "SAMPLING_MODE,CAN bus bit sampling '0': One sampling point is used in the receiver path '1': 3 sampling points with majority decision are used" "0,1"
group.long 0x414++0x03
line.long 0x00 "INTR_CAN,CAN Interrupt Cause (TTCAN + INT_STATUS Or)"
bitfld.long 0x00 2. "TT_CAPTURE,Triggers when LOCAL_TIME is saved to TT_CAPTURE on SOF detection" "0,1"
bitfld.long 0x00 1. "TT_COMPARE,Triggers when LOCAL_TIME is equal to TT_COMPARE" "0,1"
newline
bitfld.long 0x00 0. "INT_STATUS,Triggers when any enabled (INT_EBL) interrupt are set in INT_STATUS" "0,1"
group.long 0x418++0x03
line.long 0x00 "INTR_CAN_SET,CAN Interrupt Set (TTCAN + INT_STATUS Or)"
bitfld.long 0x00 2. "TT_CAPTURE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "TT_COMPARE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "INT_STATUS,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0x41C++0x03
line.long 0x00 "INTR_CAN_MASK,CAN Interrupt Mask (TTCAN + INT_STATUS Or)"
bitfld.long 0x00 2. "TT_CAPTURE,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "TT_COMPARE,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "INT_STATUS,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0x420++0x03
line.long 0x00 "INTR_CAN_MASKED,Can Interrupt Masked (TTCAN + INT_STATUS Or)"
bitfld.long 0x00 2. "TT_CAPTURE,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 1. "TT_COMPARE,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 0. "INT_STATUS,Logical and of corresponding request and mask bits" "0,1"
repeat 8. (increment 0 1)(increment 0 0x10)
tree "TX[$1]"
group.long ($2+0x20)++0x03
line.long 0x00 "CONTROL,TxMessage Buffer control/command"
bitfld.long 0x00 23. "WPNH,N/A" "0,1"
bitfld.long 0x00 21. "RTR,Remote Bit '0': This is a standard message '1': This is an RTR message" "0,1"
newline
bitfld.long 0x00 20. "IDE,Extended Identifier Bit '0': This is a standard format message '1': This is an extended format message" "0,1"
bitfld.long 0x00 16.--19. "DLC,DLC Data Length Code Invalid values are transmitted as they are but the number of data bytes is limited to eight" "0: Message has 0 data byte data[63:0] is not used,1: Message has 1 data byte data[63:56] is used,?,?,?,?,?,?,8: Message has 8 data bytes data[63:0] is used..,?..."
newline
bitfld.long 0x00 3. "WPNL,N/A" "0,1"
bitfld.long 0x00 2. "TX_INT_EBL,Tx Interrupt Enable '0': Interrupt disabled '1': Interrupt enabled successful message transmission sets the TxMsg" "0,1"
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bitfld.long 0x00 1. "TX_ABORT,Transmit Abort Request '0': idle '1': Requests removal of a pending message" "0,1"
bitfld.long 0x00 0. "TX_REQ,TxReq Transmit Request Write: '0': idle '1': Message Transmit Request5 Read: '0': TxReq completed '1': TxReq pending" "0,1"
group.long ($2+0x24)++0x03
line.long 0x00 "ID,TxMessage Buffer Identifier"
hexmask.long 0x00 3.--31. 1. "ID,Message identifier"
group.long ($2+0x28)++0x03
line.long 0x00 "DATA_HIGH,TxMessage Buffer Data high"
hexmask.long 0x00 0.--31. 1. "DATA,Data[63:32] when CONFIG.SWAP_ENDIAN=0(Big Endian by default) the sequence of DATA transmission is {DATA_HIGH[31:0] DATA_LOW[31:0]} if only byte is defined in CONTROL.DLC DATA_HIGH[7:0] will be transmitted when CONFIG.SWAP_ENDIAN=1(Little Endian).."
group.long ($2+0x2C)++0x03
line.long 0x00 "DATA_LOW,TxMessageBuffer Data low"
hexmask.long 0x00 0.--31. 1. "DATA,Data[31:0]"
tree.end
repeat.end
repeat 16. (increment 0 1)(increment 0 0xA0)
tree "RX[$1]"
group.long ($2+0xA0)++0x03
line.long 0x00 "CONTROL,RxMessage Buffer control/command"
bitfld.long 0x00 23. "WPNH,N/A" "0,1"
bitfld.long 0x00 21. "RTR_MSG,Remote Bit '1': This is an RTR message '0': This is a regular message depending on RTR_REPLY setting 0 this field will be updated by received data/remote frame 1 this field should be set to 0 (data frame type) by user in advance will not be.." "0,1"
newline
bitfld.long 0x00 20. "IDE_FMT,Extended Identifier Bit '1': This is an extended format message '0': This is a standard format message depending on RTR_REPLY setting 0 this field will be updated by received data/remote frame 1 this field should be aligned offline and set by.." "0,1"
bitfld.long 0x00 16.--19. "DLC,DLC Data Length Code" "0: Message has 0 data bytes data[63:0] is notvalid,1: Message has 1 data byte data[63:56] is valid,?,?,?,?,?,?,8: Message has 8 data bytes data[63:0] is valid..,?..."
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bitfld.long 0x00 7. "WPNL,N/A" "0,1"
bitfld.long 0x00 6. "LINK_FLAG,Link Flag '0': This buffer is not linked to the next '1': This buffer is linked with next buffer" "0,1"
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bitfld.long 0x00 5. "RX_INT_EBL,RxIntEbl Receive Interrupt Enable '0': Interrupt generation is disabled '1': Interrupt generation is enabled" "0,1"
bitfld.long 0x00 4. "RTR_REPLY,automatic message reply upon receipt of an RTR message '0': Automatic RTR message handling disabled '1': Automatic RTR message handling enabled when this bit is set only RTR message can be received by setting AMR.RTR=0 AMR.RTR=1" "0,1"
newline
bitfld.long 0x00 3. "BUFFER_EN,Buffer Enable '0': Buffer is disabled '1': Buffer is enabled" "0,1"
bitfld.long 0x00 2. "RTR_ABORT,RTR Abort Request '0': Idle '1': Requests removal of a pending RTR message reply" "0,1"
newline
rbitfld.long 0x00 1. "RTR_REPLY_PEND,RTReply_pending status '0': No RTR reply request pending '1': RTR reply request pending" "0,1"
bitfld.long 0x00 0. "MSG_AV_RTRSENT,Msg Available/RTR Sent If RTReply flag is set this bit shows if an RTR auto-reply message has been sent otherwise it indicates if the buffer contains a valid message" "0,1"
group.long ($2+0xA4)++0x03
line.long 0x00 "ID,Identifier"
hexmask.long 0x00 3.--31. 1. "ID,RxMessage: Identifier"
group.long ($2+0xA8)++0x03
line.long 0x00 "DATA_HIGH,RxMessage Data high"
hexmask.long 0x00 0.--31. 1. "DATA,Data[63:32]"
group.long ($2+0xAC)++0x03
line.long 0x00 "DATA_LOW,RxMessage Data low"
hexmask.long 0x00 0.--31. 1. "DATA,Data[31:0]"
group.long ($2+0xB0)++0x03
line.long 0x00 "AMR,Acceptance Mask Register"
hexmask.long 0x00 3.--31. 1. "ID,Identifier it cannot be used to match both 11bit and 29bit identifiers in case of 11bit identifiers lower 18bits should be all ones (don't care)"
bitfld.long 0x00 2. "IDE,N/A" "0,1"
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bitfld.long 0x00 1. "RTR,N/A" "0,1"
group.long ($2+0xB4)++0x03
line.long 0x00 "ACR,Acceptance Code Register"
hexmask.long 0x00 3.--31. 1. "ID,Identifier"
bitfld.long 0x00 2. "IDE,N/A" "0,1"
newline
bitfld.long 0x00 1. "RTR,N/A" "0,1"
group.long ($2+0xB8)++0x03
line.long 0x00 "AMR_DATA,Acceptance Mask Register - Data"
hexmask.long.word 0x00 0.--15. 1. "DATAL,Data[63:48] when DUT is NOT configured to receive only DATA frame this register should be configured with all ones (don't care)"
group.long ($2+0xBC)++0x03
line.long 0x00 "ACR_DATA,Acceptance Code Register - Data"
hexmask.long.word 0x00 0.--15. 1. "DATAL,Data[63:48]"
tree.end
repeat.end
tree.end
endif
sif cpuis("CY8C4149*")
tree "CANFD0 (CAN Controller)"
base ad:0x40400000
group.long 0x1000++0x03
line.long 0x00 "CTL,Global CAN control register"
bitfld.long 0x00 31. "MRAM_OFF,MRAM off" "0: Default MRAM on (with MRAM retained in..,1: Switch MRAM off (not retained) to save power"
hexmask.long.byte 0x00 0.--7. 1. "STOP_REQ,Clock Stop Request for each TTCAN IP"
rgroup.long 0x1004++0x03
line.long 0x00 "STATUS,Global CAN status register"
hexmask.long.byte 0x00 0.--7. 1. "STOP_ACK,Clock Stop Acknowledge for each TTCAN IP"
rgroup.long 0x1010++0x03
line.long 0x00 "INTR0_CAUSE,Consolidated interrupt0 cause register"
hexmask.long.byte 0x00 0.--7. 1. "INT0,Show pending m_ttcan_int0 of each channel"
rgroup.long 0x1014++0x03
line.long 0x00 "INTR1_CAUSE,Consolidated interrupt1 cause register"
hexmask.long.byte 0x00 0.--7. 1. "INT1,Show pending m_ttcan_int1 of each channel"
group.long 0x1020++0x03
line.long 0x00 "TS_CTL,Time Stamp control register"
bitfld.long 0x00 31. "ENABLED,Counter enable bit" "0: Count disabled,1: Count enabled"
hexmask.long.word 0x00 0.--15. 1. "PRESCALE,Time Stamp counter prescale value"
group.long 0x1024++0x03
line.long 0x00 "TS_CNT,Time Stamp counter value"
hexmask.long.word 0x00 0.--15. 1. "VALUE,The counter value of the Time Stamp Counter"
group.long 0x1080++0x03
line.long 0x00 "ECC_CTL,ECC control"
bitfld.long 0x00 16. "ECC_EN,Enable ECC for CANFD SRAM When disabled also all error injection functionality is disabled" "0,1"
group.long 0x1084++0x03
line.long 0x00 "ECC_ERR_INJ,ECC error injection"
hexmask.long.byte 0x00 24.--30. 1. "ERR_PAR,ECC Parity bits to use for ECC error injection at address ERR_ADDR"
bitfld.long 0x00 20. "ERR_EN,Enable error injection (ECC_EN must be 1)" "0,1"
newline
hexmask.long.word 0x00 2.--15. 1. "ERR_ADDR,Specifies the address of the word where an error will be injected on write or an non-correctable error will be suppressed"
tree "CH"
group.long 0x180++0x03
line.long 0x00 "RXFTOP_CTL,Receive FIFO Top control"
bitfld.long 0x00 1. "F1TPE,FIFO 1 Top Pointer Enable" "0,1"
bitfld.long 0x00 0. "F0TPE,FIFO 0 Top Pointer Enable" "0,1"
rgroup.long 0x1A0++0x03
line.long 0x00 "RXFTOP0_STAT,Receive FIFO 0 Top Status"
hexmask.long.word 0x00 0.--15. 1. "F0TA,Current FIFO 0 Top Address"
rgroup.long 0x1A8++0x03
line.long 0x00 "RXFTOP0_DATA,Receive FIFO 0 Top Data"
hexmask.long 0x00 0.--31. 1. "F0TD,When enabled (F0TPE=1) read data from MRAM at location FnTA"
rgroup.long 0x1B0++0x03
line.long 0x00 "RXFTOP1_STAT,Receive FIFO 1 Top Status"
hexmask.long.word 0x00 0.--15. 1. "F1TA,See F0TA description"
rgroup.long 0x1B8++0x03
line.long 0x00 "RXFTOP1_DATA,Receive FIFO 1 Top Data"
hexmask.long 0x00 0.--31. 1. "F1TD,See F0TD description"
tree "M_TTCAN"
rgroup.long 0x00++0x03
line.long 0x00 "CREL,Core Release Register"
bitfld.long 0x00 28.--31. "REL,Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-step of Core Release One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year One digit BCD-coded" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month Two digits BCD-coded"
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day Two digits BCD-coded"
rgroup.long 0x04++0x03
line.long 0x00 "ENDN,Endian Register"
hexmask.long 0x00 0.--31. 1. "ETV,Endianness Test Value The endianness test value is 0x87654321"
group.long 0x0C++0x03
line.long 0x00 "DBTP,Data Bit Timing & Prescaler Register"
bitfld.long 0x00 23. "TDC,Transmitter Delay Compensation" "0: Transmitter Delay Compensation disabled,1: Transmitter Delay Compensation enabled"
bitfld.long 0x00 16.--20. "DBRP,Data Bit Rate Prescaler 0x00-0x1F The value by which the oscillator frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "DTSEG1,Data time segment before sample point 0x00-0x1F Valid values are 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "DTSEG2,Data time segment after sample point 0x0-0xF Valid values are 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "DSJW,Data (Re)Synchronization Jump Width 0x0-0xF Valid values are 0 to 15" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "TEST,Test Register"
rbitfld.long 0x00 7. "RX,Receive Pin Monitors the actual value of pin m_ttcan_rx" "0: The CAN bus is dominant (m_ttcan_rx = '0'),1: The CAN bus is recessive (m_ttcan_rx = '1')"
bitfld.long 0x00 5.--6. "TX,Control of Transmit Pin 00 Reset value m_ttcan_tx controlled by the CAN Core updated at the end of the CAN bit time 01 Sample Point can be monitored at pin m_ttcan_tx 10 Dominant ('0') level at pin m_ttcan_tx 11 Recessive ('1') at pin m_ttcan_tx" "0,1,2,3"
newline
bitfld.long 0x00 4. "LBCK,Loop Back Mode" "0: Reset value Loop Back Mode is disabled,1: Loop Back Mode is enabled (see Section 3.1.9"
bitfld.long 0x00 3. "CAT,ASC is not supported by M_TTCAN Check ASC Transmit Control Monitors level at output pin m_ttcan_asct" "0,1"
newline
bitfld.long 0x00 2. "CAM,ASC is not supported by M_TTCAN Check ASC Multiplexer Control Monitors level at output pin m_ttcan_ascm" "0: Output pin m_ttcan_ascm = '0',1: Output pin m_ttcan_ascm = '1'"
bitfld.long 0x00 1. "TAT,ASC is not supported by M_TTCAN Test ASC Transmit Control Controls output pin m_ttcan_asct in test mode ORed with the signal from the FSE" "0: Level at pin m_ttcan_asct controlled by FSE,1: Level at pin m_ttcan_asct = '1'"
newline
bitfld.long 0x00 0. "TAM,ASC is not supported by M_TTCAN Test ASC Multiplexer Control Controls output pin m_ttcan_ascm in test mode ORed with the signal from the FSE" "0: Level at pin m_ttcan_ascm controlled by FSE,1: Level at pin m_ttcan_ascm = '1'"
group.long 0x14++0x03
line.long 0x00 "RWD,RAM Watchdog"
hexmask.long.byte 0x00 8.--15. 1. "WDV,Watchdog Value Actual Message RAM Watchdog Counter Value"
hexmask.long.byte 0x00 0.--7. 1. "WDC,Watchdog Configuration Start value of the Message RAM Watchdog Counter"
group.long 0x18++0x03
line.long 0x00 "CCCR,CC Control Register"
bitfld.long 0x00 15. "NISO,Non ISO Operation If this bit is set the M_TTCAN uses the CAN FD frame format as specified by the Bosch CAN FD Specification V1.0" "0: CAN FD frame format according to ISO..,1: CAN FD frame format according to Bosch CAN FD"
bitfld.long 0x00 14. "TXP,Transmit Pause If this bit is set the M_TTCAN pauses for two CAN bit times before starting the next transmission after itself has successfully transmitted a frame (see Section 3.5)" "0: Transmit pause disabled,1: Transmit pause enabled"
newline
bitfld.long 0x00 13. "EFBI,Edge Filtering during Bus Integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect"
bitfld.long 0x00 12. "PXHD,Protocol Exception Handling Disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
newline
bitfld.long 0x00 9. "BRSE,Bit Rate Switch Enable" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
bitfld.long 0x00 8. "FDOE,FD Operation Enable" "0: FD operation disabled,1: FD operation enabled"
newline
bitfld.long 0x00 7. "TEST,Test Mode Enable" "0: Normal operation register TEST holds reset..,1: Test Mode write access to register TEST enabled"
bitfld.long 0x00 6. "DAR,Disable Automatic Retransmission" "0: Automatic retransmission of messages not,1: Automatic retransmission disabled"
newline
bitfld.long 0x00 5. "MON_,Bus Monitoring Mode Bit MON can only be set by the Host when both CCE and INIT are set to '1'" "0: Bus Monitoring Mode is disabled,1: Bus Monitoring Mode is enabled"
bitfld.long 0x00 4. "CSR,Clock Stop Request not supported by M_TTCAN use CTL.STOP_REQ at the group level instead" "0: No clock stop is requested,1: Clock stop requested"
newline
bitfld.long 0x00 3. "CSA,Clock Stop Acknowledge" "0: No clock stop acknowledged,1: M_TTCAN may be set in power down by stopping"
bitfld.long 0x00 2. "ASM,Restricted Operation Mode Bit ASM can only be set by the Host when both CCE and INIT are set to '1'" "0: Normal CAN operation,1: Restricted Operation Mode active"
newline
bitfld.long 0x00 1. "CCE,Configuration Change Enable" "0: The CPU has no write access to the protected,1: The CPU has write access to the protected"
bitfld.long 0x00 0. "INIT,Initialization" "0: Normal Operation,1: Initialization is started"
group.long 0x1C++0x03
line.long 0x00 "NBTP,Nominal Bit Timing & Prescaler Register"
hexmask.long.byte 0x00 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width 0x00-0x7F Valid values are 0 to 127"
hexmask.long.word 0x00 16.--24. 1. "NBRP,Nominal Bit Rate Prescaler 0x000-0x1FFThe value by which the oscillator frequency is divided for generating the bit time quanta"
newline
hexmask.long.byte 0x00 8.--15. 1. "NTSEG1,Nominal Time segment before sample point 0x01-0xFF Valid values are 1 to 255"
hexmask.long.byte 0x00 0.--6. 1. "NTSEG2,Nominal Time segment after sample point 0x01-0x7F Valid values are 1 to 127"
group.long 0x20++0x03
line.long 0x00 "TSCC,Timestamp Counter Configuration"
bitfld.long 0x00 16.--19. "TCP,Timestamp Counter Prescaler (still used for TOCC) 0x0-0xF Configures the timestamp and timeout counters time unit in multiples of CAN bit times [1...16]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. "TSS,Timestamp Select should always be set to external timestamp counter" "0: Timestamp counter value always,1: Timestamp counter value incremented according..,2: External timestamp counter value used,3: Same as '00'"
group.long 0x24++0x03
line.long 0x00 "TSCV,Timestamp Counter Value"
hexmask.long.word 0x00 0.--15. 1. "TSC,Timestamp Counter not used for M_TTCAN The internal/external Timestamp Counter value is captured on start of frame (both Rx and Tx)"
group.long 0x28++0x03
line.long 0x00 "TOCC,Timeout Counter Configuration"
hexmask.long.word 0x00 16.--31. 1. "TOP,Timeout Period Start value of the Timeout Counter (down-counter)"
bitfld.long 0x00 1.--2. "TOS,Timeout Select When operating in Continuous mode a write to TOCV presets the counter to the value configured by TOCC.TOP and continues down-counting" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
newline
bitfld.long 0x00 0. "ETOC,Enable Timeout Counter" "0: Timeout Counter disabled,1: Timeout Counter enabled"
group.long 0x2C++0x03
line.long 0x00 "TOCV,Timeout Counter Value"
hexmask.long.word 0x00 0.--15. 1. "TOC,Timeout Counter The Timeout Counter is decremented in multiples of CAN bit times [1...16] depending on the configuration of TSCC.TCP"
rgroup.long 0x40++0x03
line.long 0x00 "ECR,Error Counter Register"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging The counter is incremented each time when a CAN protocol error causes the Transmit Error Counter or the Receive Error Counter to be incremented"
bitfld.long 0x00 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error,1: The Receive Error Counter has reached the error"
newline
hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter Actual state of the Receive Error Counter values between 0 and 127"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter Actual state of the Transmit Error Counter values between 0 and 255"
rgroup.long 0x44++0x03
line.long 0x00 "PSR,Protocol Status Register"
hexmask.long.byte 0x00 16.--22. 1. "TDCV,Transmitter Delay Compensation Value 0x00-0x7F Position of the secondary sample point defined by the sum of the measured delay from m_can_tx to m_can_rx and TDCR.TDCO"
bitfld.long 0x00 14. "PXE,Protocol Exception Event Reset on Read" "0: No protocol exception event occurred since last,1: Protocol exception event occurred"
newline
bitfld.long 0x00 13. "RFDF,Received a CAN FD Message Reset on Read This bit is set independent of acceptance filtering" "0: Since this bit was reset by the CPU no CAN FD,1: Message in CAN FD format with FDF flag set has"
bitfld.long 0x00 12. "RBRS,BRS flag of last received CAN FD Message Reset on Read This bit is set together with RFDF independent of acceptance filtering" "0: Last received CAN FD message did not have its,1: Last received CAN FD message had its BRS flag.."
newline
bitfld.long 0x00 11. "RESI,ESI flag of last received CAN FD Message Reset on Read This bit is set together with RFDF independent of acceptance filtering" "0: Last received CAN FD message did not have its,1: Last received CAN FD message had its ESI flag.."
bitfld.long 0x00 8.--10. "DLEC,Data Phase Last Error Code Set on Read Type of last error that occurred in the data phase of a CAN FD format frame with its BRS flag set" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 7. "BO,Bus_Off Status" "0: The M_CAN is not Bus_Off,1: The M_CAN is in Bus_Off state"
bitfld.long 0x00 6. "EW,Warning Status" "0: Both error counters are below the Error_Warning,1: At least one of error counter has reached the"
newline
bitfld.long 0x00 5. "EP,Error Passive" "0: The M_CAN is in the Error_Active state,1: The M_CAN is in the Error_Passive state"
bitfld.long 0x00 3.--4. "ACT,Activity Monitors the module's CAN communication state" "0: Synchronizing - node is synchronizing on CAN,1: Idle - node is neither receiver nor transmitter,2: Receiver - node is operating as receiver,3: Transmitter - node is operating as transmitter"
newline
bitfld.long 0x00 0.--2. "LEC,Last Error Code Set on Read0 The LEC indicates the type of the last error to occur on the CAN bus" "0: No Error,1: Stuff Error,2: Form Error,3: AckError,4: Bit1Error,5: Bit0Error,6: CRCError,7: NoChange"
group.long 0x48++0x03
line.long 0x00 "TDCR,Transmitter Delay Compensation Register"
hexmask.long.byte 0x00 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset 0x00-0x7F Offset value defining the distance between the measured delay from m_ttcan_tx to m_ttcan_rx and the secondary sample point"
hexmask.long.byte 0x00 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length 0x00-0x7F Defines the minimum value for the SSP position dominant edges on m_ttcan_rx that would result in an earlier SSP position are ignored for transmitter delay measurement"
group.long 0x50++0x03
line.long 0x00 "IR,Interrupt Register"
bitfld.long 0x00 29. "ARA,N/A" "0,1"
bitfld.long 0x00 28. "PED,Protocol Error in Data Phase (Data Bit Time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC"
newline
bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase (Nominal Bit Time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected"
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0: No Message RAM Watchdog event occurred,1: Message RAM Watchdog event due to missing READY"
newline
bitfld.long 0x00 25. "BO_,Bus_Off Status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
bitfld.long 0x00 24. "EW_,Warning Status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
newline
bitfld.long 0x00 23. "EP_,Error Passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0: CAN Error Logging Counter did not overflow,1: Overflow of CAN Error Logging Counter occurred"
newline
bitfld.long 0x00 21. "BEU,Bit Error Uncorrected Message RAM bit error detected uncorrected" "0: No bit error detected when reading from Message,1: Bit error detected uncorrected (e.g. parity.."
bitfld.long 0x00 20. "BEC,M_TTCAN reports correctable ECC fault to the generic fault structure this bit always reads as 0" "0: No bit error detected when reading from Message,1: Bit error detected and corrected (e.g. ECC)"
newline
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer The flag is set whenever a received message has been stored into a dedicated Rx Buffer" "0: No Rx Buffer updated,1: At least one received message stored into a Rx"
bitfld.long 0x00 18. "TOO,Timeout Occurred" "0: No timeout,1: Timeout reached"
newline
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure The flag is set when the Rx Handler - has not completed acceptance filtering or storage of an accepted message until the arbitration field of the following message has been received" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
newline
bitfld.long 0x00 15. "TEFL_,Tx Event FIFO Element Lost" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write"
bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
newline
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0: Tx Event FIFO fill level below watermark,1: Tx Event FIFO fill level reached watermark"
bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0: Tx Event FIFO unchanged,1: Tx Handler wrote Tx Event FIFO element"
newline
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
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bitfld.long 0x00 9. "TC,Transmission Completed" "0: No transmission completed,1: Transmission completed"
bitfld.long 0x00 8. "HPM,High Priority Message" "0: No high priority message received,1: High priority message received"
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bitfld.long 0x00 7. "RF1L_,Rx FIFO 1 Message Lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write"
bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
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bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0: Rx FIFO 1 fill level below watermark,1: Rx FIFO 1 fill level reached watermark"
bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
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bitfld.long 0x00 3. "RF0L_,Rx FIFO 0 Message Lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write"
bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0: Rx FIFO 0 fill level below watermark,1: Rx FIFO 0 fill level reached watermark"
bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
group.long 0x54++0x03
line.long 0x00 "IE,Interrupt Enable"
bitfld.long 0x00 29. "ARAE,N/A" "0,1"
bitfld.long 0x00 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
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bitfld.long 0x00 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
bitfld.long 0x00 26. "WDIE,Watchdog Interrupt Enable" "0,1"
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bitfld.long 0x00 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0x00 24. "EWE,Warning Status Interrupt Enable" "0,1"
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bitfld.long 0x00 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0x00 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
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bitfld.long 0x00 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
bitfld.long 0x00 20. "BECE,Bit Error Corrected Interrupt Enable (not used in M_TTCAN)" "0,1"
newline
bitfld.long 0x00 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x00 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
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bitfld.long 0x00 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0x00 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
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bitfld.long 0x00 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
bitfld.long 0x00 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
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bitfld.long 0x00 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x00 12. "TEFNE,Tx Event FIDO New Entry Interrupt Enable" "0,1"
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bitfld.long 0x00 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
bitfld.long 0x00 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
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bitfld.long 0x00 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
bitfld.long 0x00 8. "HPME,High Priority Message Interrupt Enable" "0,1"
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bitfld.long 0x00 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x00 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
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bitfld.long 0x00 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x00 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
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bitfld.long 0x00 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x00 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
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bitfld.long 0x00 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x00 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
group.long 0x58++0x03
line.long 0x00 "ILS,Interrupt Line Select"
bitfld.long 0x00 29. "ARAL,N/A" "0,1"
bitfld.long 0x00 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
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bitfld.long 0x00 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
bitfld.long 0x00 26. "WDIL,Watchdog Interrupt Line" "0,1"
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bitfld.long 0x00 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x00 24. "EWL,Warning Status Interrupt Line" "0,1"
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bitfld.long 0x00 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x00 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
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bitfld.long 0x00 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
bitfld.long 0x00 20. "BECL,Bit Error Corrected Interrupt Line (not used in M_TTCAN)" "0,1"
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bitfld.long 0x00 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x00 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
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bitfld.long 0x00 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x00 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
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bitfld.long 0x00 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x00 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
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bitfld.long 0x00 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x00 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
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bitfld.long 0x00 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
bitfld.long 0x00 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
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bitfld.long 0x00 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x00 8. "HPML,High Priority Message Interrupt Line" "0,1"
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bitfld.long 0x00 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x00 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
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bitfld.long 0x00 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x00 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
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bitfld.long 0x00 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x00 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
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bitfld.long 0x00 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x00 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
group.long 0x5C++0x03
line.long 0x00 "ILE,Interrupt Line Enable"
bitfld.long 0x00 1. "EINT1,Enable Interrupt Line 1" "0: Interrupt line m_ttcan_int1 disabled,1: Interrupt line m_ttcan_int1 enabled"
bitfld.long 0x00 0. "EINT0,Enable Interrupt Line 0" "0: Interrupt line m_ttcan_int0 disabled,1: Interrupt line m_ttcan_int0 enabled"
group.long 0x80++0x03
line.long 0x00 "GFC,Global Filter Configuration"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated" "0: Accept in Rx,1: Accept in Rx,2: Reject,3: Reject"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated" "0: Accept in Rx,1: Accept in Rx,2: Reject,3: Reject"
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bitfld.long 0x00 1. "RRFS,Reject Remote Frames Standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard.."
bitfld.long 0x00 0. "RRFE,Reject Remote Frames Extended" "0: Filter remote frames with 29-bit extended IDs,1: Reject all remote frames with 29-bit extended.."
group.long 0x84++0x03
line.long 0x00 "SIDFC,Standard ID Filter Configuration"
abitfld.long 0x00 16.--23. "LSS,List Size Standard" "0x00=0: No standard Message ID filter 1-128=..,0x80=128: Values greater than 128 are.."
hexmask.long.word 0x00 2.--15. 1. "FLSSA,Filter List Standard Start Address Start address of standard Message ID filter list (32-bit word address see Figure 2)"
group.long 0x88++0x03
line.long 0x00 "XIDFC,Extended ID Filter Configuration"
abitfld.long 0x00 16.--22. "LSE,List Size Extended" "0x00=0: No extended Message ID filter 1-64=..,0x40=64: Values greater than 64 are interpreted.."
hexmask.long.word 0x00 2.--15. 1. "FLESA,Filter List Extended Start Address Start address of extended Message ID filter list (32-bit word address see Figure 2)"
group.long 0x90++0x03
line.long 0x00 "XIDAM,Extended ID AND Mask"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask For acceptance filtering of extended frames the Extended ID AND Mask is ANDed with the Message ID of a received frame"
rgroup.long 0x94++0x03
line.long 0x00 "HPMS,High Priority Message Status"
bitfld.long 0x00 15. "FLST,Filter List Indicates the filter list of the matching filter element" "0: Standard Filter List,1: Extended Filter List"
hexmask.long.byte 0x00 8.--14. 1. "FIDX,Filter Index Index of matching filter element"
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bitfld.long 0x00 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
bitfld.long 0x00 0.--5. "BIDX,Buffer Index Index of Rx FIFO element to which the message was stored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x98++0x03
line.long 0x00 "NDAT1,New Data 1"
abitfld.long 0x00 0.--31. "ND,New Data The register holds the New Data flags of Rx Buffers 0 to 31" "0x00000000=0: Rx Buffer not updated,0x00000001=1: Rx Buffer updated from new message"
group.long 0x9C++0x03
line.long 0x00 "NDAT2,New Data 2"
abitfld.long 0x00 0.--31. "ND,New Data The register holds the New Data flags of Rx Buffers 32 to 63" "0x00000000=0: Rx Buffer not updated,0x00000001=1: Rx Buffer updated from new message"
group.long 0xA0++0x03
line.long 0x00 "RXF0C,Rx FIFO 0 Configuration"
bitfld.long 0x00 31. "F0OM,FIFO 0 Operation Mode FIFO 0 can be operated in blocking or in overwrite mode (see Section 3.4.2)" "0: FIFO 0 blocking mode,1: FIFO 0 overwrite mode"
abitfld.long 0x00 24.--30. "F0WM,Rx FIFO 0 Watermark" "0x00=0: Watermark interrupt disabled 1-64= Level..,0x40=64: Watermark interrupt disabled"
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abitfld.long 0x00 16.--22. "F0S,Rx FIFO 0 Size" "0x00=0: No Rx FIFO 0 1-64= Number of Rx FIFO 0..,0x40=64: Values greater than 64 are interpreted.."
hexmask.long.word 0x00 2.--15. 1. "F0SA,Rx FIFO 0 Start Address Start address of Rx FIFO 0 in Message RAM (32-bit word address see Figure 2)"
rgroup.long 0xA4++0x03
line.long 0x00 "RXF0S,Rx FIFO 0 Status"
bitfld.long 0x00 25. "RF0L,Rx FIFO 0 Message Lost This bit is a copy of interrupt flag IR.RF0L" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write"
bitfld.long 0x00 24. "F0F,Rx FIFO 0 Full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
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bitfld.long 0x00 16.--21. "F0PI,Rx FIFO 0 Put Index Rx FIFO 0 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--13. "F0GI,Rx FIFO 0 Get Index Rx FIFO 0 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.byte 0x00 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level Number of elements stored in Rx FIFO 0 range 0 to 64"
group.long 0xA8++0x03
line.long 0x00 "RXF0A,Rx FIFO 0 Acknowledge"
bitfld.long 0x00 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 0 it has to write the buffer index of the last element read from Rx FIFO 0 to F0AI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xAC++0x03
line.long 0x00 "RXBC,Rx Buffer Configuration"
hexmask.long.word 0x00 2.--15. 1. "RBSA,Rx Buffer Start Address Configures the start address of the Rx Buffers section in the Message RAM (32-bit word address)"
group.long 0xB0++0x03
line.long 0x00 "RXF1C,Rx FIFO 1 Configuration"
bitfld.long 0x00 31. "F1OM,FIFO 1 Operation Mode FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2)" "0: FIFO 1 blocking mode,1: FIFO 1 overwrite mode"
abitfld.long 0x00 24.--30. "F1WM,Rx FIFO 1 Watermark" "0x00=0: Watermark interrupt disabled 1-64= Level..,0x40=64: Watermark interrupt disabled"
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abitfld.long 0x00 16.--22. "F1S,Rx FIFO 1 Size" "0x00=0: No Rx FIFO 1 1-64= Number of Rx FIFO 1..,0x40=64: Values greater than 64 are interpreted.."
hexmask.long.word 0x00 2.--15. 1. "F1SA,Rx FIFO 1 Start Address Start address of Rx FIFO 1 in Message RAM (32-bit word address see Figure 2)"
rgroup.long 0xB4++0x03
line.long 0x00 "RXF1S,Rx FIFO 1 Status"
bitfld.long 0x00 30.--31. "DMS,Debug Message Status" "0: Idle state wait for reception of debug messages,1: Debug message A received,2: Debug messages A B received,3: Debug messages A B C received DMA request is.."
bitfld.long 0x00 25. "RF1L,Rx FIFO 1 Message Lost This bit is a copy of interrupt flag IR.RF1L" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write"
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bitfld.long 0x00 24. "F1F,Rx FIFO 1 Full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
bitfld.long 0x00 16.--21. "F1PI,Rx FIFO 1 Put Index Rx FIFO 1 write index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--13. "F1GI,Rx FIFO 1 Get Index Rx FIFO 1 read index pointer range 0 to 63" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.byte 0x00 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level Number of elements stored in Rx FIFO 1 range 0 to 64"
group.long 0xB8++0x03
line.long 0x00 "RXF1A,Rx FIFO 1 Acknowledge"
bitfld.long 0x00 0.--5. "F1AI,Rx FIFO 1 Acknowledge Index After the Host has read a message or a sequence of messages from Rx FIFO 1 it has to write the buffer index of the last element read from Rx FIFO 1 to F1AI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xBC++0x03
line.long 0x00 "RXESC,Rx Buffer / FIFO Element Size Configuration"
bitfld.long 0x00 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
bitfld.long 0x00 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
newline
bitfld.long 0x00 0.--2. "F0DS,N/A" "0,1,2,3,4,5,6,7"
group.long 0xC0++0x03
line.long 0x00 "TXBC,Tx Buffer Configuration"
bitfld.long 0x00 30. "TFQM,Tx FIFO/Queue Mode" "0: Tx FIFO operation,1: Tx Queue operation"
bitfld.long 0x00 24.--29. "TFQS,Transmit FIFO/Queue Size" "0: No Tx FIFO/Queue 1-32= Number of Tx Buffers..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Values greater than 32 are interpreted as 32,?..."
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bitfld.long 0x00 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0: No Dedicated Tx Buffers 1-32= Number of,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Values greater than 32 are interpreted as 32,?..."
hexmask.long.word 0x00 2.--15. 1. "TBSA,Tx Buffers Start Address Start address of Tx Buffers section in Message RAM (32-bit word address see Figure 2)"
rgroup.long 0xC4++0x03
line.long 0x00 "TXFQS,Tx FIFO/Queue Status"
bitfld.long 0x00 21. "TFQF,Tx FIFO/Queue Full" "0: Tx FIFO/Queue not full,1: Tx FIFO/Queue full"
bitfld.long 0x00 16.--20. "TFQPI,Tx FIFO/Queue Put Index Tx FIFO/Queue write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "TFGI,Tx FIFO Get Index Tx FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--5. "TFFL,Tx FIFO Free Level Number of consecutive free Tx FIFO elements starting from TFGI range 0 to 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xC8++0x03
line.long 0x00 "TXESC,Tx Buffer Element Size Configuration"
bitfld.long 0x00 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
rgroup.long 0xCC++0x03
line.long 0x00 "TXBRP,Tx Buffer Request Pending"
abitfld.long 0x00 0.--31. "TRP,Transmission Request Pending Each Tx Buffer has its own Transmission Request Pending bit" "0x00000000=0: No transmission request pending,0x00000001=1: Transmission request pending"
group.long 0xD0++0x03
line.long 0x00 "TXBAR,Tx Buffer Add Request"
abitfld.long 0x00 0.--31. "AR,Add Request Each Tx Buffer has its own Add Request bit" "0x00000000=0: No transmission request added,0x00000001=1: Transmission requested added"
group.long 0xD4++0x03
line.long 0x00 "TXBCR,Tx Buffer Cancellation Request"
abitfld.long 0x00 0.--31. "CR,Cancellation Request Each Tx Buffer has its own Cancellation Request bit" "0x00000000=0: No cancellation pending,0x00000001=1: Cancellation pending"
rgroup.long 0xD8++0x03
line.long 0x00 "TXBTO,Tx Buffer Transmission Occurred"
abitfld.long 0x00 0.--31. "TO,Transmission Occurred Each Tx Buffer has its own Transmission Occurred bit" "0x00000000=0: No transmission occurred,0x00000001=1: Transmission occurred"
rgroup.long 0xDC++0x03
line.long 0x00 "TXBCF,Tx Buffer Cancellation Finished"
abitfld.long 0x00 0.--31. "CF,Cancellation Finished Each Tx Buffer has its own Cancellation Finished bit" "0x00000000=0: No transmit buffer cancellation,0x00000001=1: Transmit buffer cancellation.."
group.long 0xE0++0x03
line.long 0x00 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
abitfld.long 0x00 0.--31. "TIE,Transmission Interrupt Enable Each Tx Buffer has its own Transmission Interrupt Enable bit" "0x00000000=0: Transmission interrupt disabled,0x00000001=1: Transmission interrupt enable"
group.long 0xE4++0x03
line.long 0x00 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
abitfld.long 0x00 0.--31. "CFIE,Cancellation Finished Interrupt Enable Each Tx Buffer has its own Cancellation Finished Interrupt Enable bit" "0x00000000=0: Cancellation finished interrupt..,0x00000001=1: Cancellation finished interrupt.."
group.long 0xF0++0x03
line.long 0x00 "TXEFC,Tx Event FIFO Configuration"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0: Watermark interrupt disabled 1-32= Level for Tx,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Watermark interrupt disabled,?..."
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0: Tx Event FIFO disabled 1-32= Number of Tx Event,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,32: Values greater than 32 are interpreted as 32..,?..."
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hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address Start address of Tx Event FIFO in Message RAM (32-bit word address see Figure 2)"
rgroup.long 0xF4++0x03
line.long 0x00 "TXEFS,Tx Event FIFO Status"
bitfld.long 0x00 25. "TEFL,Tx Event FIFO Element Lost This bit is a copy of interrupt flag IR.TEFL" "0: No Tx Event FIFO element lost,1: Tx Event FIFO element lost also set after write"
bitfld.long 0x00 24. "EFF,Event FIFO Full" "0: Tx Event FIFO not full,1: Tx Event FIFO full"
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bitfld.long 0x00 16.--20. "EFPI,Event FIFO Put Index Tx Event FIFO write index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--12. "EFGI,Event FIFO Get Index Tx Event FIFO read index pointer range 0 to 31" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--5. "EFFL,Event FIFO Fill Level Number of elements stored in Tx Event FIFO range 0 to 32" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF8++0x03
line.long 0x00 "TXEFA,Tx Event FIFO Acknowledge"
bitfld.long 0x00 0.--4. "EFAI,Event FIFO Acknowledge Index After the Host has read an element or a sequence of elements from the Tx Event FIFO it has to write the index of the last element read from Tx Event FIFO to EFAI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x100++0x03
line.long 0x00 "TTTMC,TT Trigger Memory Configuration"
abitfld.long 0x00 16.--22. "TME,Trigger Memory Elements" "0x00=0: No Trigger Memory 1-64= Number of..,0x40=64: Values greater than 64 are interpreted.."
hexmask.long.word 0x00 2.--15. 1. "TMSA,Trigger Memory Start Address Start address of Trigger Memory in Message RAM (32-bit word address see Figure 2)"
group.long 0x104++0x03
line.long 0x00 "TTRMC,TT Reference Message Configuration"
bitfld.long 0x00 31. "RMPS,Reference Message Payload Select Ignored in case of time slaves" "0: Message Marker MM Event FIFO Control EFC Data,1: bytes 2-8 Level 0"
bitfld.long 0x00 30. "XTD,Extended Identifier" "0: 11-bit standard identifier,1: 29-bit extended identifier"
newline
hexmask.long 0x00 0.--28. 1. "RID,Reference Identifier Identifier transmitted with reference message and used for reference message filtering"
group.long 0x108++0x03
line.long 0x00 "TTOCF,TT Operation Configuration"
bitfld.long 0x00 26. "EVTP,Event Trigger Polarity" "0: Rising edge trigger,1: Falling edge trigger"
bitfld.long 0x00 25. "ECC,Enable Clock Calibration" "0: Automatic clock calibration in TTCAN Level 0 2,1: Automatic clock calibration in TTCAN Level 0 2"
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bitfld.long 0x00 24. "EGTF,Enable Global Time Filtering" "0: Global time filtering in TTCAN Level 0 2 is,1: Global time filtering in TTCAN Level 0 2 is"
hexmask.long.byte 0x00 16.--23. 1. "AWL,Application Watchdog Limit The application watchdog can be disabled by programming AWL to 0x00"
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bitfld.long 0x00 15. "EECS,Enable External Clock Synchronization If enabled TUR configuration (TURCF.NCL only) may be updated during TTCAN operation" "0: External clock synchronization in TTCAN Level 0,1: External clock synchronization in TTCAN Level 0"
hexmask.long.byte 0x00 8.--14. 1. "IRTO,Initial Reference Trigger Offset 0x00-7F Positive offset range from 0 to 127"
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bitfld.long 0x00 5.--7. "LDSDL,LD of Synchronization Deviation Limit The Synchronization Deviation Limit SDL is configured by its dual logarithm LDSDL with SDL = 2(LDSDL + 5)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "TM,Time Master" "0: Time Master function disabled,1: Potential Time Master"
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bitfld.long 0x00 3. "GEN,Gap Enable" "0: Strictly time-triggered operation,1: External event-synchronized time-triggered"
bitfld.long 0x00 0.--1. "OM,Operation Mode" "0: Event-driven CAN communication default,1: TTCAN level 1,2: TTCAN level 2,3: TTCAN level 0"
group.long 0x10C++0x03
line.long 0x00 "TTMLM,TT Matrix Limits"
hexmask.long.word 0x00 16.--27. 1. "ENTT,Expected Number of Tx Triggers 0x000-FFF Expected number of Tx Triggers in one Matrix Cycle"
bitfld.long 0x00 8.--11. "TXEW,Tx Enable Window 0x0-F Length of Tx enable window 1-16 NTU cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6.--7. "CSS,N/A" "0,1,2,3"
bitfld.long 0x00 0.--5. "CCM,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x110++0x03
line.long 0x00 "TURCF,TUR Configuration"
bitfld.long 0x00 31. "ELT,Enable Local Time" "0: Local time is stopped default,1: Local time is enabled"
hexmask.long.word 0x00 16.--29. 1. "DC,Denominator Configuration 0x0000 Illegal value 0x0001-3FFF Denominator Configuration"
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hexmask.long.word 0x00 0.--15. 1. "NCL,Numerator Configuration Low Write access to the TUR Numerator Configuration Low is only possible during configuration with TURCF.ELT = '0' or if TTOCF.EECS (external clock synchronization enabled) is set"
group.long 0x114++0x03
line.long 0x00 "TTOCN,TT Operation Control"
rbitfld.long 0x00 15. "LCKC,TT Operation Control Register Locked Set by a write access to register TTOCN" "0: Write access to TTOCN enabled,1: Write access to TTOCN locked"
bitfld.long 0x00 13. "ESCN,External Synchronization Control If enabled the M_TTCAN synchronizes its cycle time phase to an external event signaled by a rising edge at pin m_ttcan_evt (see Section 4.11)" "0: External synchronization disabled,1: External synchronization enabled"
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bitfld.long 0x00 12. "NIG,Next is Gap This bit can only be set when the M_TTCAN is the actual Time Master and when it is configured for external event-synchronized time-triggered operation (TTOCF.GEN = '1')" "0: No action reset by reception of any reference,1: Transmit next reference message with.."
bitfld.long 0x00 11. "TMG,Time Mark Gap" "0: Reset by each reference message,1: Next reference message started when Register"
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bitfld.long 0x00 10. "FGP,Finish Gap Set by the CPU reset by each reference message" "0: No reference message requested,1: Application requested start of reference.."
bitfld.long 0x00 9. "GCS,Gap Control Select" "0: Gap control independent from m_ttcan_evt,1: Gap control by input pin m_ttcan_evt"
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bitfld.long 0x00 8. "TTIE,Trigger Time Mark Interrupt Pulse Enable External time mark events are configured by trigger memory element TMEX (see Section 2.4.7)" "0: Trigger Time Mark Interrupt output m_ttcan_tmp,1: Trigger Time Mark Interrupt output m_ttcan_tmp"
bitfld.long 0x00 6.--7. "TMC,Register Time Mark Compare" "0: No Register Time Mark Interrupt generated,1: Register Time Mark Interrupt if Time Mark =,2: Register Time Mark Interrupt if Time Mark =,3: Register Time Mark Interrupt if Time Mark ="
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bitfld.long 0x00 5. "RTIE,Register Time Mark Interrupt Pulse Enable Register time mark interrupts are configured by register TTTMK" "0: Register Time Mark Interrupt output m_ttcan_rtp,1: Register Time Mark Interrupt output m_ttcan_rtp"
bitfld.long 0x00 3.--4. "SWS,Stop Watch Source" "0: Stop Watch disabled,1: Actual value of cycle time is copied to..,2: Actual value of local time is copied to..,3: Actual value of global time is copied to.."
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bitfld.long 0x00 2. "SWP,Stop Watch Polarity" "0: Rising edge trigger,1: Falling edge trigger"
bitfld.long 0x00 1. "ECS,External Clock Synchronization Writing a '1' to ECS sets TTOST.WECS if the node is the actual Time Master" "0,1"
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bitfld.long 0x00 0. "SGT,Set Global time Writing a '1' to SGT sets TTOST.WGDT if the node is the actual Time Master" "0,1"
group.long 0x118++0x03
line.long 0x00 "TTGTP,TT Global Time Preset"
hexmask.long.word 0x00 16.--31. 1. "CTP,Cycle Time Target Phase CTP is write-protected while TTOCN.ESCN or TTOST.SPL are set (see Section 4.11)"
hexmask.long.word 0x00 0.--15. 1. "TP,N/A"
group.long 0x11C++0x03
line.long 0x00 "TTTMK,TT Time Mark"
rbitfld.long 0x00 31. "LCKM,TT Time Mark Register Locked Always set by a write access to registers TTOCN" "0: Write access to TTTMK enabled,1: Write access to TTTMK locked"
hexmask.long.byte 0x00 16.--22. 1. "TICC,Time Mark Cycle Code Cycle count for which the time mark is valid"
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hexmask.long.word 0x00 0.--15. 1. "TM_,Time Mark 0x0000-FFFF Time Mark"
group.long 0x120++0x03
line.long 0x00 "TTIR,TT Interrupt Register"
bitfld.long 0x00 18. "CER,Configuration Error Trigger out of order" "0: No error found in trigger list,1: Error found in trigger list"
bitfld.long 0x00 17. "AW,Application Watchdog" "0: Application watchdog served in time,1: Application watchdog not served in time"
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bitfld.long 0x00 16. "WT,Watch Trigger" "0: cycle time 0xFF00),1: Missing reference message (Level"
bitfld.long 0x00 15. "IWT,Initialization Watch Trigger The initialization is restarted by resetting IWT" "0: No missing reference message during system..,1: No system startup due to missing reference.."
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bitfld.long 0x00 14. "ELC,Error Level Changed Not set when error level changed during initialization" "0: No change in error level,1: Error level changed"
bitfld.long 0x00 13. "SE2,Scheduling Error 2" "0: No scheduling error 2,1: Scheduling error 2 occurred"
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bitfld.long 0x00 12. "SE1,Scheduling Error 1" "0: No scheduling error 1,1: Scheduling error 1 occurred"
bitfld.long 0x00 11. "TXO,Tx Count Overflow" "0: Number of Tx Trigger as expected,1: More Tx trigger than expected in one matrix.."
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bitfld.long 0x00 10. "TXU,Tx Count Underflow" "0: Number of Tx Trigger as expected,1: Less Tx trigger than expected in one matrix.."
bitfld.long 0x00 9. "GTE,Global Time Error Synchronization deviation SD exceeds limit specified by TTOCF.LDSDL TTCAN Level 0 2 only" "0: Synchronization deviation within limit,1: Synchronization deviation exceeded limit"
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bitfld.long 0x00 8. "GTD,Global Time Discontinuity" "0: No discontinuity of global time,1: Discontinuity of global time"
bitfld.long 0x00 7. "GTW,Global Time Wrap" "0: No global time wrap occurred,1: Global time wrap from 0xFFFF to 0x0000 occurred"
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bitfld.long 0x00 6. "SWE,Stop Watch Event" "0: No rising/falling edge at stop watch trigger..,1: Rising/falling edge at stop watch trigger pin"
bitfld.long 0x00 5. "TTMI,Trigger Time Mark Event Internal Internal time mark events are configured by trigger memory element TMIN (see Section 2.4.7)" "0: cycle time TTOCF.IRTO * 0x200),1: Time mark reached (Level"
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bitfld.long 0x00 4. "RTMI,Register Time Mark Interrupt Set when time referenced by TTOCN.TMC (cycle local or global) equals TTTMK.TM independent of the synchronization state" "0: Time mark not reached,1: Time mark reached"
bitfld.long 0x00 3. "SOG,Start of Gap" "0: No reference message seen with Next_is_Gap..,1: Reference message with Next_is_Gap bit set"
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bitfld.long 0x00 2. "CSM_,Change of Synchronization Mode" "0: No change in master to slave relation or,1: Master to slave relation or schedule"
bitfld.long 0x00 1. "SMC,Start of Matrix Cycle" "0: No Matrix Cycle started since bit has been..,1: Matrix Cycle started"
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bitfld.long 0x00 0. "SBC,Start of Basic Cycle" "0: No Basic Cycle started since bit has been reset,1: Basic Cycle started"
group.long 0x124++0x03
line.long 0x00 "TTIE,TT Interrupt Enable"
bitfld.long 0x00 18. "CERE,Configuration Error Interrupt Enable" "0,1"
bitfld.long 0x00 17. "AWE_,Application Watchdog Interrupt Enable" "0,1"
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bitfld.long 0x00 16. "WTE,Watch Trigger Interrupt Enable" "0,1"
bitfld.long 0x00 15. "IWTE,Initialization Watch Trigger Interrupt Enable" "0,1"
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bitfld.long 0x00 14. "ELCE,Change Error Level Interrupt Enable" "0,1"
bitfld.long 0x00 13. "SE2E,Scheduling Error 2 Interrupt Enable" "0,1"
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bitfld.long 0x00 12. "SE1E,Scheduling Error 1 Interrupt Enable" "0,1"
bitfld.long 0x00 11. "TXOE,Tx Count Overflow Interrupt Enable" "0,1"
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bitfld.long 0x00 10. "TXUE,Tx Count Underflow Interrupt Enable" "0,1"
bitfld.long 0x00 9. "GTEE,Global Time Error Interrupt Enable" "0,1"
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bitfld.long 0x00 8. "GTDE,Global Time Discontinuity Interrupt Enable" "0,1"
bitfld.long 0x00 7. "GTWE,Global Time Wrap Interrupt Enable" "0,1"
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bitfld.long 0x00 6. "SWEE,Stop Watch Event Interrupt Enable" "0,1"
bitfld.long 0x00 5. "TTMIE,Trigger Time Mark Event Internal Enable" "0,1"
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bitfld.long 0x00 4. "RTMIE,Register Time Mark Interrupt Enable" "0,1"
bitfld.long 0x00 3. "SOGE,Start of Gap Interrupt Enable" "0,1"
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bitfld.long 0x00 2. "CSME,Change of Synchronization Mode Interrupt Enable" "0,1"
bitfld.long 0x00 1. "SMCE,Start of Matrix Cycle Interrupt Enable" "0,1"
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bitfld.long 0x00 0. "SBCE,Start of Basic Cycle Interrupt Enable" "0,1"
group.long 0x128++0x03
line.long 0x00 "TTILS,TT Interrupt Line Select"
bitfld.long 0x00 18. "CERL,Configuration Error Interrupt Line" "0,1"
bitfld.long 0x00 17. "AWL_,Application Watchdog Interrupt Line" "0,1"
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bitfld.long 0x00 16. "WTL,Watch Trigger Interrupt Line" "0,1"
bitfld.long 0x00 15. "IWTL,Initialization Watch Trigger Interrupt Line" "0,1"
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bitfld.long 0x00 14. "ELCL,Change Error Level Interrupt Line" "0,1"
bitfld.long 0x00 13. "SE2L,Scheduling Error 2 Interrupt Line" "0,1"
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bitfld.long 0x00 12. "SE1L,Scheduling Error 1 Interrupt Line" "0,1"
bitfld.long 0x00 11. "TXOL,Tx Count Overflow Interrupt Line" "0,1"
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bitfld.long 0x00 10. "TXUL,Tx Count Underflow Interrupt Line" "0,1"
bitfld.long 0x00 9. "GTEL,Global Time Error Interrupt Line" "0,1"
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bitfld.long 0x00 8. "GTDL,Global Time Discontinuity Interrupt Line" "0,1"
bitfld.long 0x00 7. "GTWL,Global Time Wrap Interrupt Line" "0,1"
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bitfld.long 0x00 6. "SWEL,Stop Watch Event Interrupt Line" "0,1"
bitfld.long 0x00 5. "TTMIL,Trigger Time Mark Event Internal Line" "0,1"
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bitfld.long 0x00 4. "RTMIL,Register Time Mark Interrupt Line" "0,1"
bitfld.long 0x00 3. "SOGL,Start of Gap Interrupt Line" "0,1"
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bitfld.long 0x00 2. "CSML,Change of Synchronization Mode Interrupt Line" "0,1"
bitfld.long 0x00 1. "SMCL,Start of Matrix Cycle Interrupt Line" "0,1"
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bitfld.long 0x00 0. "SBCL,Start of Basic Cycle Interrupt Line" "0,1"
rgroup.long 0x12C++0x03
line.long 0x00 "TTOST,TT Operation Status"
bitfld.long 0x00 31. "SPL,Schedule Phase Lock The bit is valid only when external synchronization is enabled (TTOCN.ESCN = '1')" "0: Phase outside range,1: Phase inside range"
bitfld.long 0x00 30. "WECS,Wait for External Clock Synchronization" "0: No external clock synchronization pending,1: Node waits for external clock synchronization.."
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bitfld.long 0x00 29. "AWE,Application Watchdog Event The application watchdog is served by reading TTOST" "0: Application Watchdog served in time,1: Failed to serve Application Watchdog in time"
bitfld.long 0x00 28. "WFE,Wait for Event" "0: No Gap announced reset by a reference message,1: Reference message with Next_is_Gap = '1'.."
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bitfld.long 0x00 27. "GSI,Gap Started Indicator" "0: No Gap in schedule reset by each reference,1: Gap time after Basic Cycle has started"
bitfld.long 0x00 24.--26. "TMP,Time Master Priority 0x0-7 Priority of actual Time Master" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 23. "GFI,Gap Finished Indicator Set when the CPU writes TTOCN.FGP or by a time mark interrupt if TMG = '1' or via input pin m_ttcan_evt if TTOCN.GCS = '1'" "0: Reset at the end of each reference message,1: Gap finished by M_TTCAN"
bitfld.long 0x00 22. "WGTD,Wait for Global Time Discontinuity" "0: No global time preset pending,1: Node waits for the global time preset to take"
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hexmask.long.byte 0x00 8.--15. 1. "RTO,Reference Trigger Offset The Reference Trigger Offset value is a signed integer with a range from -127 (0x81) to 127 (0x7F)"
bitfld.long 0x00 7. "QCS,Quality of Clock Speed Only relevant in TTCAN Level 0 and Level 2 otherwise fixed to '1'" "0: Local clock speed not synchronized to Time,1: Synchronization Deviation <= SDL"
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bitfld.long 0x00 6. "QGTP,Quality of Global Time Phase Only relevant in TTCAN Level 0 and Level 2 otherwise fixed to '0'" "0: Global time not valid,1: Global time in phase with Time Master"
bitfld.long 0x00 4.--5. "SYS,Synchronization State" "0: Out of Synchronization,1: Synchronizing to TTCAN communication,2: Schedule suspended by Gap (In_Gap),3: Synchronized to schedule (In_Schedule)"
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bitfld.long 0x00 2.--3. "MS,Master State" "0: Master_Off no master properties relevant,1: Operating as Time Slave,2: Operating as Backup Time Master,3: Operating as current Time Master"
bitfld.long 0x00 0.--1. "EL,Error Level" "0: No Error,1: Warning,2: Error,3: Severe Error"
rgroup.long 0x130++0x03
line.long 0x00 "TURNA,TUR Numerator Actual"
hexmask.long.tbyte 0x00 0.--17. 1. "NAV,N/A"
rgroup.long 0x134++0x03
line.long 0x00 "TTLGT,TT Local & Global Time"
hexmask.long.word 0x00 16.--31. 1. "GT,Global Time Non-fractional part of the sum of the node's local time and its local offset (see Section 4.5)"
hexmask.long.word 0x00 0.--15. 1. "LT,Local Time Non-fractional part of local time incremented once each local NTU (see Section 4.5)"
rgroup.long 0x138++0x03
line.long 0x00 "TTCTC,TT Cycle Time & Count"
bitfld.long 0x00 16.--21. "CC,Cycle Count 0x00-3F Number of actual Basic Cycle in the System Matrix" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--15. 1. "CT,Cycle Time Non-fractional part of the difference of the node's local time and Ref_Mark (see Section 4.5)"
rgroup.long 0x13C++0x03
line.long 0x00 "TTCPT,TT Capture Time"
hexmask.long.word 0x00 16.--31. 1. "SWV,Stop Watch Value On a rising/falling edge (as configured via TTOCN.SWP) at the Stop Watch Trigger pin m_ttcan_swt when TTOCN.SWS is != '00' and TTIR.SWE is '0' the actual time value as selected by TTOCN.SWS (cycle local global) is copied to SWV and.."
bitfld.long 0x00 0.--5. "CCV,Cycle Count Value Cycle count value captured together with SWV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x140++0x03
line.long 0x00 "TTCSM,TT Cycle Sync Mark"
hexmask.long.word 0x00 0.--15. 1. "CSM,Cycle Sync Mark The Cycle Sync Mark is measured"
tree.end
tree.end
tree.end
endif
tree "CPUSS (CPU Subsystem)"
base ad:0x40100000
group.long 0x00++0x03
line.long 0x00 "CONFIG,Configuration register"
bitfld.long 0x00 0. "VECT_IN_RAM,0': Vector Table is located at 0x0000:0000 in flash '1': Vector Table is located at 0x2000:0000 in SRAM Note that vectors for RESET and FAULT are always fetched from ROM" "0,1"
group.long 0x04++0x03
line.long 0x00 "SYSREQ,SYSCALL control register"
bitfld.long 0x00 31. "SYSCALL_REQ,CPU/DAP writes a '1' to this field to request a SystemCall" "0,1"
rbitfld.long 0x00 30. "HMASTER_0,Indicates the source of the write access to the SYSREQ register" "0,1"
newline
rbitfld.long 0x00 29. "ROM_ACCESS_EN,Indicates that executing from Boot ROM is enabled" "0,1"
bitfld.long 0x00 28. "PRIVILEGED,Indicates whether the system is in privileged ('1') or user mode ('0')" "0,1"
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bitfld.long 0x00 27. "DIS_RESET_VECT_REL,Disable Reset Vector fetch relocation: '0': CPU accesses to locations 0x0000:0000" "0,1"
hexmask.long.word 0x00 0.--15. 1. "SYSCALL_COMMAND,Opcode of the system call being requested"
group.long 0x08++0x03
line.long 0x00 "SYSARG,SYSARG control register"
hexmask.long 0x00 0.--31. 1. "SYSCALL_ARG,Argument to System Call specified in SYSREQ"
group.long 0x0C++0x03
line.long 0x00 "PROTECTION,Protection control register"
bitfld.long 0x00 31. "PROTECTION_LOCK,Setting this field will block (ignore) any further writes to the PROTECTION_MODE field in this register" "0,1"
bitfld.long 0x00 30. "FLASH_LOCK,Setting this bit will force SPCIF.ADDRESS.AXA to be ignored which prevents SM Flash from being erased or overwritten" "0,1"
newline
bitfld.long 0x00 0.--3. "PROTECTION_MODE,Current protection mode this field is available as a global signal everywhere in the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "PRIV_ROM,ROM privilege register"
hexmask.long.word 0x00 16.--25. 1. "SROM_PROT_LIMIT,Indicates the limit where the privileged area of System ROM partition starts in increments of 256 Bytes"
hexmask.long.byte 0x00 0.--7. 1. "BROM_PROT_LIMIT,Indicates the limit where the privileged area of the Boot ROM partition starts in increments of 256 Bytes"
group.long 0x14++0x03
line.long 0x00 "PRIV_RAM,RAM privilege register"
hexmask.long.word 0x00 0.--8. 1. "RAM_PROT_LIMIT,Indicates the limit where the privileged area of SRAM starts in increments of 256 Bytes"
group.long 0x18++0x03
line.long 0x00 "PRIV_FLASH,Flash privilege register"
hexmask.long.word 0x00 0.--11. 1. "FLASH_PROT_LIMIT,Indicates the limit where the privileged area of flash starts in increments of 256 Bytes"
group.long 0x1C++0x03
line.long 0x00 "WOUNDING,Wounding register"
bitfld.long 0x00 24.--26. "RAM1_WOUND,Wounding of RAM 1 (see description of RAM_WOUND)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--22. "FLASH_WOUND,Indicates the amount of accessible flash in this part" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "RAM_WOUND,Indicates the amount of accessible RAM 0 memory capacitty in this part" "0,1,2,3,4,5,6,7"
group.long 0x20++0x03
line.long 0x00 "INT_SEL,Interrupt multiplexer select register"
hexmask.long 0x00 0.--31. 1. "DSI,Specifies interrupt source: '0': Fixed Function"
group.long 0x24++0x03
line.long 0x00 "INT_MODE,DSI interrupt pulse mode register"
hexmask.long 0x00 0.--31. 1. "DSI_INT_PULSE,Specifies DSI interrupt format: '0': level sensitive i.e"
group.long 0x28++0x03
line.long 0x00 "NMI_MODE,DSI NMI pulse mode register"
bitfld.long 0x00 0. "DSI_NMI_PULSE,Specifies DSI NMI format: '0': level sensitive i.e" "0,1"
group.long 0x30++0x03
line.long 0x00 "FLASH_CTL,FLASH control register"
bitfld.long 0x00 16.--17. "ARB,Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky" "0,1,2,3"
bitfld.long 0x00 8. "FLASH_INVALIDATE,1': Invalidates the content of the flash controller's buffers" "0,1"
newline
bitfld.long 0x00 4. "PREF_EN,Prefetch enable: '0': disabled" "0,1"
bitfld.long 0x00 0.--1. "FLASH_WS,Amount of ROM wait states: '0': 0 wait states (fast flash: [0 24] MHz system frequency slow flash: [0 16] MHz system frequency) '1': 1 wait state (fast flash: [24 48] MHz system frequency slow flash: [16 32] MHz system frequency) '2': 2 wait.." "0,1,2,3"
sif cpuis("psoc4100smax")||cpuis("psoc4100sp256kb")
group.long 0x34++0x03
line.long 0x00 "ROM_CTL,ROM control register"
bitfld.long 0x00 16.--17. "ARB,Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky" "0,1,2,3"
bitfld.long 0x00 0. "ROM_WS,Amount of ROM wait states: '0': 0 wait states" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")
group.long 0x34++0x03
line.long 0x00 "ROM_CTL,ROM control register"
bitfld.long 0x00 0. "ROM_WS,Amount of ROM wait states: '0': 0 wait states" "0,1"
endif
group.long 0x38++0x03
line.long 0x00 "RAM_CTL,RAM control register"
bitfld.long 0x00 16.--17. "ARB,Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky" "0,1,2,3"
group.long 0x3C++0x03
line.long 0x00 "DMAC_CTL,DMA controller register"
bitfld.long 0x00 16.--17. "ARB,Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky" "0,1,2,3"
group.long 0xA0++0x03
line.long 0x00 "PRIV_RAM1,RAM 1 privilege register"
hexmask.long.word 0x00 0.--8. 1. "RAM_PROT_LIMIT,See description of PRIV_RAM.RAM_PROT_LIMIT"
group.long 0xA4++0x03
line.long 0x00 "RAM1_CTL,RAM 1 control register"
bitfld.long 0x00 16.--17. "ARB,Arbitration policy (for RAM controller 1): '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky" "0,1,2,3"
group.long 0xB0++0x03
line.long 0x00 "MTB_CTL,MTB control register"
bitfld.long 0x00 0. "CPU_HALT_TSTOP_EN,1': Enable CPU Halt to stop MTB trace" "0,1"
repeat 24. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "SL_CTL[$1],Slave control register $1"
bitfld.long 0x00 16.--17. "ARB,Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky" "0,1,2,3"
repeat.end
tree.end
sif cpuis("CY8C4146P*")||cpuis("CY8C4146L*")||cpuis("CY8C4147*")||cpuis("CY8C4146A*")||cpuis("CY8C4148*")
tree "CSD0 (Capsense Controller)"
sif cpuis("CY8C4146P*")||cpuis("CY8C4146L*")
base ad:0x400C0000
elif cpuis("CY8C4147*")||cpuis("CY8C4146A*")||cpuis("CY8C4148*")
base ad:0x40290000
endif
sif cpuis("psoc4100s")
group.long 0x00++0x03
line.long 0x00 "CONFIG,Configuration and Control"
bitfld.long 0x00 31. "ENABLE,Master enable of the CSDv2 IP" "0,1"
bitfld.long 0x00 30. "LP_MODE,Select the power mode for the CSD components (REFGEN AMBUF CSDCMP HSCMP)" "0: High Power mode,1: Low Power mode"
newline
bitfld.long 0x00 27. "DSI_SENSE_EN,Enables the use of the dsi_sense_in input instead of the internally generated modulation signal to drive csd_sense and csd_shield signals" "0,1"
bitfld.long 0x00 26. "SAMPLE_SYNC,Enables double synchronizing of sample input from DSI (only relevant when DSI_SAMPLE_EN=1)" "0,1"
newline
bitfld.long 0x00 25. "DSI_SAMPLE_EN,Enables the use of the dsi_sample_in input instead of the comparator output to strobe COUNTER" "0,1"
bitfld.long 0x00 24. "DSI_COUNT_SEL,Select what to output on the dsi_count bus" "0: depending on the dsi_count_val_sel input..,1: output ADC_RES.VIN_CNT on the dsi_count bus"
newline
bitfld.long 0x00 19. "CSX_DUAL_CNT,Enable the use of two counters for MUTUAL cap sensing mode (CSX) do not use when MUTUAL_CAP=0" "0: Use one counter for both phases (source and..,1: Use two counters separate count for when.."
bitfld.long 0x00 18. "MUTUAL_CAP,Enables mutual cap sensing mode" "0: Self-cap mode (configure sense line as..,1: Mutual-cap mode (configure Tx line as.."
newline
bitfld.long 0x00 14. "CHARGE_MODE,Enable charging of the Cmod/Csh_tank capacitor using the GPIO digital output buffer using the csd_charge signal" "0: Use this to keep csd_charge signal low,1: Use csd_charge to enable the GPIO Driver to.."
bitfld.long 0x00 12. "SENSE_EN,Enables the sense modulator output" "0: all switches static or dynamic are open and..,1: switches and IDAC can be closed/on as per MMIO"
newline
bitfld.long 0x00 8.--9. "SHIELD_DELAY,Selects the delay by which csd_shield is delayed relative to csd_sense" "0: Delay line is off csd_shield=csd_sense,1: Introduces a 5ns delay (typ),2: Introduces a 10ns delay (typ),3: Introduces a 20ns delay (typ)"
bitfld.long 0x00 4.--6. "FILTER_DELAY,This value determines the number of cycles that the digital filter makes the CSDCMP output ignored while the counter counts and IDAC is on" "0,1,2,3,4,5,6,7"
endif
sif cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x00++0x03
line.long 0x00 "CONFIG,Configuration and Control"
bitfld.long 0x00 31. "ENABLE,Master enable of the CSDv2 IP" "0,1"
bitfld.long 0x00 30. "LP_MODE,Select the power mode for the CSD components (REFGEN AMBUF CSDCMP HSCMP)" "0: High Power mode,1: Low Power mode"
newline
bitfld.long 0x00 27. "DSI_SENSE_EN,Enables the use of the dsi_sense_in input instead of the internally generated modulation signal to drive csd_sense and csd_shield signals" "0,1"
bitfld.long 0x00 26. "SAMPLE_SYNC,Enables double synchronizing of sample input from DSI (only relevant when DSI_SAMPLE_EN=1)" "0,1"
newline
bitfld.long 0x00 25. "DSI_SAMPLE_EN,Enables the use of the dsi_sample_in input instead of the comparator output to strobe COUNTER" "0,1"
bitfld.long 0x00 24. "DSI_COUNT_SEL,Select what to output on the dsi_count bus" "0: depending on the dsi_count_val_sel input..,1: output ADC_RES.VIN_CNT on the dsi_count bus"
newline
bitfld.long 0x00 19. "CSX_DUAL_CNT,Enable the use of two counters for MUTUAL cap sensing mode (CSX) do not use when MUTUAL_CAP=0" "0: Use one counter for both phases (source and..,1: Use two counters separate count for when.."
bitfld.long 0x00 18. "MUTUAL_CAP,Enables mutual cap sensing mode" "0: Self-cap mode (configure sense line as..,1: Mutual-cap mode (configure Tx line as.."
newline
bitfld.long 0x00 17. "FULL_WAVE,Enables full wave cap sensing mode" "0: Half Wave mode (normal),1: Full Wave mode"
bitfld.long 0x00 14. "CHARGE_MODE,Enable charging of the Cmod/Csh_tank capacitor using the GPIO digital output buffer using the csd_charge signal" "0: Use this to keep csd_charge signal low,1: Use csd_charge to enable the GPIO Driver to.."
newline
bitfld.long 0x00 12. "SENSE_EN,Enables the sense modulator output" "0: all switches static or dynamic are open and..,1: switches and IDAC can be closed/on as per MMIO"
bitfld.long 0x00 8.--9. "SHIELD_DELAY,Selects the delay by which csd_shield is delayed relative to csd_sense" "0: Delay line is off csd_shield=csd_sense,1: Introduces a 5ns delay (typ),2: Introduces a 10ns delay (typ),3: Introduces a 20ns delay (typ)"
newline
bitfld.long 0x00 4.--6. "FILTER_DELAY,This value determines the number of cycles that the digital filter makes the CSDCMP output ignored while the counter counts and IDAC is on" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3. "LOW_VDDA,Set this bit when VDDA is known to be below ~2V this bit is used to improve IDACs performance at low voltages" "0,1"
endif
group.long 0x04++0x03
line.long 0x00 "SPARE,Spare MMIO"
bitfld.long 0x00 0.--3. "SPARE,Spare MMIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x80++0x03
line.long 0x00 "STATUS,Status Register"
bitfld.long 0x00 3. "CSDCMP_OUT,Output of main sensing comparator (synchronized)" "0,1"
bitfld.long 0x00 2. "HSCMP_OUT,Output of reference buffer comparator used to charge up Cmod and/or Csh_tank (synchronized)" "0: Vin < Vref,1: Vin > Vref"
newline
bitfld.long 0x00 1. "CSD_SENSE,Signal used to drive the Cs switches" "0,1"
bitfld.long 0x00 0. "CSD_CHARGE,Qualified and possible inverted value of COMP_OUT that is used to drive GPIO's charging Cmod or Csh_tank" "0,1"
rgroup.long 0x84++0x03
line.long 0x00 "STAT_SEQ,Current Sequencer status"
bitfld.long 0x00 16.--18. "ADC_STATE,ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SEQ_STATE,CSD sequencer state" "0,1,2,3,4,5,6,7"
rgroup.long 0x88++0x03
line.long 0x00 "STAT_CNTS,Current status counts"
hexmask.long.word 0x00 0.--15. 1. "NUM_CONV,Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles)"
sif cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0x8C++0x03
line.long 0x00 "STAT_HCNT,Current count of the HSCMP counter"
hexmask.long.word 0x00 0.--15. 1. "CNT,Current value of HSCMP counter"
endif
rgroup.long 0xD0++0x03
line.long 0x00 "RESULT_VAL1,Result CSD/CSX accumulation counter value 1"
hexmask.long.byte 0x00 16.--23. 1. "BAD_CONVS,Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window either because Vref was not crossed at all or if the Vref was already crossed before the window started"
hexmask.long.word 0x00 0.--15. 1. "VALUE,Accumulated counter value for this result"
rgroup.long 0xD4++0x03
line.long 0x00 "RESULT_VAL2,Result CSX accumulation counter value 2"
hexmask.long.word 0x00 0.--15. 1. "VALUE,Only used in case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt) this counter counts when csd_sense is low"
sif cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0xE0++0x03
line.long 0x00 "ADC_RES,ADC measurement"
bitfld.long 0x00 31. "ADC_ABORT,This flag is set when the ADC sequencer was aborted before tripping HSCMP" "0,1"
bitfld.long 0x00 30. "ADC_OVERFLOW,This flag is set when the ADC counter overflows" "0,1"
newline
bitfld.long 0x00 16. "HSCMP_POL,Polarity used for IDACB for this last ADC result" "0: source,1: sink"
hexmask.long.word 0x00 0.--15. 1. "VIN_CNT,Count to source/sink Cref1 + Cref2 from Vin to Vrefhi or Vssa"
endif
sif cpuis("psoc4100s")
rgroup.long 0xE0++0x03
line.long 0x00 "ADC_RES,ADC measurement"
bitfld.long 0x00 31. "ADC_ABORT,This flag is set when the ADC sequencer was aborted before tripping HSCMP" "0,1"
bitfld.long 0x00 30. "ADC_OVERFLOW,This flag is set when the ADC counter overflows" "0,1"
newline
bitfld.long 0x00 16. "HSCMP_POL,Polarity used for IDACB for this last ADC result" "0: source,1: sink"
hexmask.long.word 0x00 0.--15. 1. "VIN_CNT,Count to source/sink Cref1 + Cref2 from Vin to Vrefhi"
endif
group.long 0xF0++0x03
line.long 0x00 "INTR,CSD Interrupt Request Register"
bitfld.long 0x00 8. "ADC_RES,ADC Result ready" "0,1"
bitfld.long 0x00 2. "INIT,Coarse initialization complete or Sample initialization complete (the latter is typically ignored)" "0,1"
newline
bitfld.long 0x00 1. "SAMPLE,A normal sample is complete (CSDv1 compatible interrupt)" "0,1"
group.long 0xF4++0x03
line.long 0x00 "INTR_SET,CSD Interrupt set register"
bitfld.long 0x00 8. "ADC_RES,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "INIT,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "SAMPLE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xF8++0x03
line.long 0x00 "INTR_MASK,CSD Interrupt mask register"
bitfld.long 0x00 8. "ADC_RES,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "INIT,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "SAMPLE,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0xFC++0x03
line.long 0x00 "INTR_MASKED,CSD Interrupt masked register"
bitfld.long 0x00 8. "ADC_RES,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "INIT,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "SAMPLE,Logical and of corresponding request and mask bits" "0,1"
group.long 0x180++0x03
line.long 0x00 "HSCMP,High Speed Comparator configuration"
bitfld.long 0x00 31. "AZ_EN,Auto-Zero enable allow the Sequencer to Auto-Zero this component" "0,1"
bitfld.long 0x00 4. "HSCMP_INVERT,Invert the HSCMP output before it is used to control switches and the CSD sequencer" "0,1"
newline
bitfld.long 0x00 0. "HSCMP_EN,High Speed Comparator enable" "0: Disable comparator output is zero,1: On regular operation"
group.long 0x184++0x03
line.long 0x00 "AMBUF,Reference Generator configuration"
bitfld.long 0x00 0.--1. "PWR_MODE,Amux buffer power level" "0: Disable buffer,1: On normal or low power level depending on..,2: On high or low power level depending on..,?..."
group.long 0x188++0x03
line.long 0x00 "REFGEN,Reference Generator configuration"
bitfld.long 0x00 23. "VREFLO_INT,Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1)" "0,1"
bitfld.long 0x00 16.--20. "VREFLO_SEL,Select resistor string tap for Vreflo/Vreflo_int" "0: minimum vout,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: maximum vout = vrefhi (only works"
newline
bitfld.long 0x00 8.--12. "GAIN,Select resistor string tap for feedback" "0: minimum vout,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: maximum vout = vrefhi -> gain=1"
bitfld.long 0x00 6. "RES_EN,Resistor string enable" "0,1"
newline
bitfld.long 0x00 5. "VDDA_EN,Close Vdda switch to top of resistor string (or Vrefhi?)" "0,1"
bitfld.long 0x00 4. "BYPASS,Bypass selected input reference unbuffered to Vrefhi" "0,1"
newline
bitfld.long 0x00 0. "REFGEN_EN,Reference Generator Enable" "0: Disable Reference Generator,1: On regular operation"
group.long 0x18C++0x03
line.long 0x00 "CSDCMP,CSD Comparator configuration"
bitfld.long 0x00 31. "AZ_EN,Auto-Zero enable allow the Sequencer to Auto-Zero this component" "0,1"
bitfld.long 0x00 29. "FEEDBACK_MODE,This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used" "0: Use feedback from sampling flip-flop (used in..,1: Use feedback from comparator directly (used.."
newline
bitfld.long 0x00 28. "CMP_MODE,Select which signal to output on dsi_sample_out" "0: CSD mode,1: General Purpose mode"
bitfld.long 0x00 8.--9. "CMP_PHASE,Select in what phase(s) the comparator is active" "0: Comparator is active from start of Phi2 and..,1: Comparator is active during Phi1 only,2: Comparator is active during Phi2 only,3: Comparator is activated at the start of both.."
newline
bitfld.long 0x00 4.--5. "POLARITY_SEL,Select which IDAC polarity to use to detect CSDCMP triggering" "0: Use idaca_pol (firmware setting with CSX and..,1: Use idacb_pol (firmware setting with optional..,2: Use the expression (csd_sense ? idaca_pol :..,?..."
bitfld.long 0x00 0. "CSDCMP_EN,CSD Comparator Enable" "0: Disable comparator output is zero,1: On regular operation"
sif cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x1C0++0x03
line.long 0x00 "IDACA,IDACA Configuration"
bitfld.long 0x00 25. "LEG2_EN,output enable for leg 2 to CSDBUSA" "0,1"
bitfld.long 0x00 24. "LEG1_EN,output enable for leg 1 to CSDBUSA" "0,1"
newline
bitfld.long 0x00 22.--23. "RANGE,IDAC multiplier" "0: 1 LSB = 37.5 nA,1: 1 LSB = 300 nA,2: 1 LSB = 2400 nA,3: 1 LSB = 1200 nA"
bitfld.long 0x00 21. "DSI_CTRL_EN,Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled)" "0: no DSI control IDACA_POLARITY = IDACA.POLARITY,1: Mix MMIO with DSI control IDACA_POLARITY ="
newline
bitfld.long 0x00 18.--19. "LEG2_MODE,Controls the usage mode of LEG2" "0: General Purpose static mode,1: General Purpose dynamic mode,2: CSD static mode,3: CSD dynamic mode"
bitfld.long 0x00 16.--17. "LEG1_MODE,Controls the usage mode of LEG1 and the Polarity bit" "0: General Purpose static mode,1: General Purpose dynamic mode,2: CSD static mode,3: CSD dynamic mode"
newline
bitfld.long 0x00 10.--11. "BAL_MODE,Balancing mode: only applies to legs configured as CSD" "0: enabled from start of Phi2 until disabled by..,1: enabled from start of Phi1 and disabled by..,2: enabled from start of Phi2 and disabled by..,3: enabled from start of both Phi1 and Phi2 and.."
bitfld.long 0x00 8.--9. "POLARITY,Selects the polarity of the IDAC (sensing operation)" "0: Normal,1: Inverted,2: The polarity of the IDAC will follow the..,3: The polarity of the IDAC will follow the.."
newline
bitfld.long 0x00 7. "POL_DYN,Polarity is dynamic this bit does not influence the logic in the SoftIP it only goes to the HardIP" "0: Static polarity,1: Dynamic polarity"
hexmask.long.byte 0x00 0.--6. 1. "VAL,Current value setting for this IDAC (7 bits)"
endif
sif cpuis("psoc4100s")
group.long 0x1C0++0x03
line.long 0x00 "IDACA,IDACA Configuration"
bitfld.long 0x00 25. "LEG2_EN,output enable for leg 2 to CSDBUSA" "0,1"
bitfld.long 0x00 24. "LEG1_EN,output enable for leg 1 to CSDBUSA" "0,1"
newline
bitfld.long 0x00 22.--23. "RANGE,IDAC multiplier" "0: 1 LSB = 37.5 nA,1: 1 LSB = 300 nA,2: 1 LSB = 2400 nA,?..."
bitfld.long 0x00 21. "DSI_CTRL_EN,Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled)" "0: no DSI control IDACA_POLARITY = IDACA.POLARITY,1: Mix MMIO with DSI control IDACA_POLARITY ="
newline
bitfld.long 0x00 18.--19. "LEG2_MODE,Controls the usage mode of LEG2" "0: General Purpose static mode,1: General Purpose dynamic mode,2: CSD static mode,3: CSD dynamic mode"
bitfld.long 0x00 16.--17. "LEG1_MODE,Controls the usage mode of LEG1 and the Polarity bit" "0: General Purpose static mode,1: General Purpose dynamic mode,2: CSD static mode,3: CSD dynamic mode"
newline
bitfld.long 0x00 10.--11. "BAL_MODE,Balancing mode: only applies to legs configured as CSD" "0: enabled from start of Phi2 until disabled by..,1: enabled from start of Phi1 and disabled by..,2: enabled from start of Phi2 and disabled by..,3: enabled from start of both Phi1 and Phi2 and.."
bitfld.long 0x00 8.--9. "POLARITY,Selects the polarity of the IDAC (sensing operation)" "0: Normal,1: Inverted,2: The polarity of the IDAC will follow the..,3: The polarity of the IDAC will follow the.."
newline
bitfld.long 0x00 7. "POL_DYN,Polarity is dynamic this bit does not influence the logic in the SoftIP it only goes to the HardIP" "0: Static polarity,1: Dynamic polarity"
hexmask.long.byte 0x00 0.--6. 1. "VAL,Current value setting for this IDAC (7 bits)"
group.long 0x1C4++0x03
line.long 0x00 "IDACB,IDACB Configuration"
bitfld.long 0x00 26. "LEG3_EN,output enable for leg3 to CSDBUSC only allowed when RANGE = IDAC_LO" "0,1"
bitfld.long 0x00 25. "LEG2_EN,output enable for leg 2 to CSDBUSB or CSDBUSA" "0,1"
newline
bitfld.long 0x00 24. "LEG1_EN,output enable for leg 1 to CSDBUSB or CSDBUSA" "0,1"
bitfld.long 0x00 22.--23. "RANGE,IDAC multiplier" "0: 1 LSB = 37.5 nA,1: 1 LSB = 300 nA,2: 1 LSB = 2400 nA,?..."
newline
bitfld.long 0x00 21. "DSI_CTRL_EN,Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled)" "0: no DSI control IDACB_POLARITY = IDACB.POLARITY,1: Mix MMIO with DSI control IDACB_POLARITY ="
bitfld.long 0x00 18.--19. "LEG2_MODE,Controls the usage mode of LEG2" "0: same as corresponding IDACA.LEG2_MODE,1: same as corresponding IDACA.LEG2_MODE,2: same as corresponding IDACA.LEG2_MODE,3: same as corresponding IDACA.LEG2_MODE"
newline
bitfld.long 0x00 16.--17. "LEG1_MODE,Controls the usage mode of LEG1 and the Polarity bit" "0: same as corresponding IDACA.LEG1_MODE,1: same as corresponding IDACA.LEG1_MODE,2: same as corresponding IDACA.LEG1_MODE,3: same as corresponding IDACA.LEG1_MODE"
bitfld.long 0x00 10.--11. "BAL_MODE,same as corresponding IDACA Balancing mode" "0: same as corresponding IDACA Balancing mode,1: same as corresponding IDACA Balancing mode,2: same as corresponding IDACA Balancing mode,3: same as corresponding IDACA Balancing mode"
newline
bitfld.long 0x00 8.--9. "POLARITY,Selects the polarity of the IDAC (sensing operation)" "0: Normal,1: Inverted,2: The polarity of the IDAC will follow the..,3: The polarity of the IDAC will follow the.."
bitfld.long 0x00 7. "POL_DYN,Polarity is dynamic this bit does not influence the logic in the SoftIP it only goes to the HardIP" "0: Static polarity,1: Dynamic polarity"
newline
hexmask.long.byte 0x00 0.--6. 1. "VAL,Current value setting for this IDAC (7 bits)"
endif
sif cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x1C4++0x03
line.long 0x00 "IDACB,IDACB Configuration"
bitfld.long 0x00 26. "LEG3_EN,output enable for leg3 to CSDBUSC only allowed when RANGE = IDAC_LO" "0,1"
bitfld.long 0x00 25. "LEG2_EN,output enable for leg 2 to CSDBUSB or CSDBUSA" "0,1"
newline
bitfld.long 0x00 24. "LEG1_EN,output enable for leg 1 to CSDBUSB or CSDBUSA" "0,1"
bitfld.long 0x00 22.--23. "RANGE,IDAC multiplier" "0: 1 LSB = 37.5 nA,1: 1 LSB = 300 nA,2: 1 LSB = 2400 nA,3: 1 LSB = 1200 nA"
newline
bitfld.long 0x00 21. "DSI_CTRL_EN,Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled)" "0: no DSI control IDACB_POLARITY = IDACB.POLARITY,1: Mix MMIO with DSI control IDACB_POLARITY ="
bitfld.long 0x00 18.--19. "LEG2_MODE,Controls the usage mode of LEG2" "0: same as corresponding IDACA.LEG2_MODE,1: same as corresponding IDACA.LEG2_MODE,2: same as corresponding IDACA.LEG2_MODE,3: same as corresponding IDACA.LEG2_MODE"
newline
bitfld.long 0x00 16.--17. "LEG1_MODE,Controls the usage mode of LEG1 and the Polarity bit" "0: same as corresponding IDACA.LEG1_MODE,1: same as corresponding IDACA.LEG1_MODE,2: same as corresponding IDACA.LEG1_MODE,3: same as corresponding IDACA.LEG1_MODE"
bitfld.long 0x00 10.--11. "BAL_MODE,same as corresponding IDACA Balancing mode" "0: same as corresponding IDACA Balancing mode,1: same as corresponding IDACA Balancing mode,2: same as corresponding IDACA Balancing mode,3: same as corresponding IDACA Balancing mode"
newline
bitfld.long 0x00 8.--9. "POLARITY,Selects the polarity of the IDAC (sensing operation)" "0: Normal,1: Inverted,2: The polarity of the IDAC will follow the..,3: The polarity of the IDAC will follow the.."
bitfld.long 0x00 7. "POL_DYN,Polarity is dynamic this bit does not influence the logic in the SoftIP it only goes to the HardIP" "0: Static polarity,1: Dynamic polarity"
newline
hexmask.long.byte 0x00 0.--6. 1. "VAL,Current value setting for this IDAC (7 bits)"
endif
group.long 0x1F0++0x03
line.long 0x00 "SW_RES,Switch Resistance configuration"
bitfld.long 0x00 18.--19. "RES_F2PT,Select resistance for the corresponding switch" "0,1,2,3"
bitfld.long 0x00 16.--17. "RES_F1PM,Select resistance for the corresponding switch" "0: LOW,1: Medium,2: HIGH,3: RSVD"
newline
bitfld.long 0x00 6.--7. "RES_HCBG,Select resistance or low EMI for the corresponding switch" "0,1,2,3"
bitfld.long 0x00 4.--5. "RES_HCBV,Select resistance or low EMI for the corresponding switch" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "RES_HCAG,Select resistance or low EMI for the corresponding switch" "0,1,2,3"
bitfld.long 0x00 0.--1. "RES_HCAV,Select resistance or low EMI (slow ramp) for the HCAV switch" "0: LOW,1: Medium,2: HIGH,3: Low EMI (slow ramp: 3 switches closed by.."
sif cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x200++0x03
line.long 0x00 "SENSE_PERIOD,Sense clock period"
bitfld.long 0x00 26.--27. "LFSR_BITS,Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period" "0: use 2 bits,1: use 3 bits,2: use 4 bits,3: use 5 bits"
bitfld.long 0x00 25. "SEL_LFSR_MSB,Use the MSB of configured LSFR size as csd_sense signal" "0,1"
newline
bitfld.long 0x00 24. "LFSR_CLEAR,When set forces the LFSR to it's initial state (all ones)" "0,1"
bitfld.long 0x00 20.--23. "LFSR_SCALE,Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--18. "LFSR_SIZE,Selects the length of the LFSR which determines the LFSR repeat period" "0: Don't use clock dithering (=spreadspectrum)..,1: 6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1 period= 63),2: 7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1 period=..,3: 9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1 period= 511),4: 10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1 period=..,5: 8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1 period= 255),6: 12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1 period=..,?..."
hexmask.long.word 0x00 0.--11. 1. "SENSE_DIV,The length-1 of the Sense modulation 'clock' period in clk_csd cycles"
endif
sif cpuis("psoc4100s")
group.long 0x200++0x03
line.long 0x00 "SENSE_PERIOD,Sense clock period"
bitfld.long 0x00 25. "SEL_LFSR_MSB,Use the MSB of configured LSFR size as csd_sense signal" "0,1"
bitfld.long 0x00 24. "LFSR_CLEAR,When set forces the LFSR to it's initial state (all ones)" "0,1"
newline
bitfld.long 0x00 20.--23. "LFSR_SCALE,Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--18. "LFSR_SIZE,Selects the length of the LFSR which determines the LFSR repeat period" "0: Don't use clock dithering (=spreadspectrum)..,1: 6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1 period= 63),2: 7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1 period=..,3: 9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1 period= 511),4: 10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1 period=..,5: 8-bit LFSR (G(x)=X^8 +X^4+X^3+X^2+1 period=..,6: 12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1 period=..,?..."
newline
hexmask.long.word 0x00 0.--11. 1. "SENSE_DIV,The length-1 of the Sense modulation 'clock' period in clk_csd cycles"
endif
group.long 0x204++0x03
line.long 0x00 "SENSE_DUTY,Sense clock duty cycle"
bitfld.long 0x00 19. "OVERLAP_PHI2,Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1)" "0,1"
bitfld.long 0x00 18. "OVERLAP_PHI1,NonOverlap or not for Phi1 (csd_sense=0)" "0: Non-overlap for Phi1 the Phi1 signal is,1: 'Overlap' (= not non-overlap) for Phi1 the Phi1"
newline
bitfld.long 0x00 16. "SENSE_POL,Polarity of the sense clock" "0: start with low phase (typical for regular,1: start with high phase"
hexmask.long.word 0x00 0.--11. 1. "SENSE_WIDTH,Defines the length of the first phase of the sense clock in clk_csd cycles"
group.long 0x280++0x03
line.long 0x00 "SW_HS_P_SEL,HSCMP Pos input switch Waveform selection"
bitfld.long 0x00 28. "SW_HMRH,Set corresponding switch" "0,1"
bitfld.long 0x00 24. "SW_HMCB,Set corresponding switch" "0,1"
newline
bitfld.long 0x00 20. "SW_HMCA,Set corresponding switch" "0,1"
bitfld.long 0x00 16. "SW_HMMB,Set corresponding switch" "0,1"
newline
bitfld.long 0x00 12. "SW_HMMA,Set corresponding switch" "0,1"
bitfld.long 0x00 8. "SW_HMPS,Set corresponding switch" "0,1"
newline
bitfld.long 0x00 4. "SW_HMPT,Set corresponding switch" "0,1"
bitfld.long 0x00 0. "SW_HMPM,Set HMPM switch" "0: static open,1: static closed"
group.long 0x284++0x03
line.long 0x00 "SW_HS_N_SEL,HSCMP Neg input switch Waveform selection"
bitfld.long 0x00 28.--30. "SW_HCRL,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "SW_HCRH,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20. "SW_HCCD,Set corresponding switch" "0,1"
bitfld.long 0x00 16. "SW_HCCC,Set corresponding switch" "0,1"
group.long 0x288++0x03
line.long 0x00 "SW_SHIELD_SEL,Shielding switches Waveform selection"
bitfld.long 0x00 20. "SW_HCCG,Set corresponding switch If the ADC is enabled then this switch is directly controlled by the ADC sequencer" "0,1"
bitfld.long 0x00 16. "SW_HCCV,Set corresponding switch" "0,1"
newline
bitfld.long 0x00 12.--14. "SW_HCBG,Select waveform for corresponding switch using csd_shield as base" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "SW_HCBV,N/A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "SW_HCAG,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SW_HCAV,N/A" "0,1,2,3,4,5,6,7"
sif cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x28C++0x03
line.long 0x00 "SW_HS_P_SEL1,HSCMP Pos input switch Waveform selection 1"
bitfld.long 0x00 0. "SW_HMRE,Set HMRE switch" "0: static open,1: static closed"
endif
group.long 0x290++0x03
line.long 0x00 "SW_AMUXBUF_SEL,Amuxbuffer switches Waveform selection"
bitfld.long 0x00 28. "SW_IRL,Set corresponding switch" "0,1"
bitfld.long 0x00 24. "SW_IRH,Set corresponding switch" "0,1"
newline
bitfld.long 0x00 20. "SW_IRLI,Set corresponding switch" "0,1"
bitfld.long 0x00 16.--18. "SW_ICB,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12. "SW_ICA,Set corresponding switch" "0,1"
bitfld.long 0x00 8. "SW_IRLB,Set corresponding switch" "0,1"
newline
bitfld.long 0x00 4. "SW_IRBY,Set corresponding switch" "0,1"
group.long 0x294++0x03
line.long 0x00 "SW_BYP_SEL,AMUXBUS bypass switches Waveform selection"
bitfld.long 0x00 20. "SW_CBCC,Set corresponding switch If the ADC is enabled then this switch is directly controlled by the ADC sequencer" "0,1"
bitfld.long 0x00 16. "SW_BYB,Set corresponding switch" "0,1"
newline
bitfld.long 0x00 12. "SW_BYA,Set corresponding switch" "0,1"
group.long 0x2A0++0x03
line.long 0x00 "SW_CMP_P_SEL,CSDCMP Pos Switch Waveform selection"
bitfld.long 0x00 24. "SW_SFCB,Set corresponding switch" "0,1"
bitfld.long 0x00 20. "SW_SFCA,Set corresponding switch" "0,1"
newline
bitfld.long 0x00 16. "SW_SFMB,Set corresponding switch" "0,1"
bitfld.long 0x00 12. "SW_SFMA,Set corresponding switch" "0,1"
newline
bitfld.long 0x00 8.--10. "SW_SFPS,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "SW_SFPT,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "SW_SFPM,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
group.long 0x2A4++0x03
line.long 0x00 "SW_CMP_N_SEL,CSDCMP Neg Switch Waveform selection"
bitfld.long 0x00 28.--30. "SW_SCRL,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "SW_SCRH,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
group.long 0x2A8++0x03
line.long 0x00 "SW_REFGEN_SEL,Reference Generator Switch Waveform selection"
bitfld.long 0x00 28. "SW_SGR,Set corresponding switch" "0,1"
bitfld.long 0x00 24. "SW_SGRE,Set corresponding switch" "0,1"
newline
bitfld.long 0x00 16. "SW_SGMB,Set corresponding switch" "0,1"
bitfld.long 0x00 4. "SW_IBCB,Set corresponding switch" "0,1"
newline
bitfld.long 0x00 0. "SW_IAIB,Set corresponding switch" "0,1"
group.long 0x2B0++0x03
line.long 0x00 "SW_FW_MOD_SEL,Full Wave Cmod Switch Waveform selection"
bitfld.long 0x00 28. "SW_C1F1,Set corresponding switch" "0,1"
bitfld.long 0x00 24. "SW_C1CD,Set corresponding switch" "0,1"
newline
bitfld.long 0x00 20. "SW_C1CC,Set corresponding switch" "0,1"
bitfld.long 0x00 16.--18. "SW_F1CA,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "SW_F1MA,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "SW_F1PM,Set corresponding switch" "0,1"
group.long 0x2B4++0x03
line.long 0x00 "SW_FW_TANK_SEL,Full Wave Csh_tank Switch Waveform selection"
bitfld.long 0x00 28. "SW_C2F2,Set corresponding switch" "0,1"
bitfld.long 0x00 24. "SW_C2CD,Set corresponding switch" "0,1"
newline
bitfld.long 0x00 20. "SW_C2CC,Set corresponding switch" "0,1"
bitfld.long 0x00 16.--18. "SW_F2CB,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "SW_F2CA,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "SW_F2MA,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "SW_F2PT,Set corresponding switch" "0,1"
group.long 0x2C0++0x03
line.long 0x00 "SW_DSI_SEL,DSI output switch control Waveform selection"
bitfld.long 0x00 4.--6. "DSI_CMOD,Select waveform for dsi_cmod signal (called dsi_cap_hi_en in CDSv1)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "DSI_CSH_TANK,Select waveform for dsi_csh_tank signal (called dsi_cap_lo_en in CDSv1)" "0,1,2,3,4,5,6,7"
group.long 0x300++0x03
line.long 0x00 "SEQ_TIME,Sequencer Timing"
hexmask.long.byte 0x00 0.--7. 1. "AZ_TIME,Define Auto-Zero time in csd_sense cycles -1"
group.long 0x310++0x03
line.long 0x00 "SEQ_INIT_CNT,Sequencer Initial conversion and sample counts"
hexmask.long.word 0x00 0.--15. 1. "CONV_CNT,Number of conversion per sample if set to 0 the Sample_init state will be skipped"
group.long 0x314++0x03
line.long 0x00 "SEQ_NORM_CNT,Sequencer Normal conversion and sample counts"
hexmask.long.word 0x00 0.--15. 1. "CONV_CNT,Number of conversion per sample if set to 0 the Sample_norm state will be skipped"
group.long 0x320++0x03
line.long 0x00 "ADC_CTL,ADC Control"
bitfld.long 0x00 16.--17. "ADC_MODE,Enable ADC measurement" "0: No ADC measurement,1: Count time A to bring Cref1 + Cref2 up from..,2: Count time B to bring Cref1 + Cref2 back up..,3: Determine HSCMP polarity and count time C to.."
hexmask.long.byte 0x00 0.--7. 1. "ADC_TIME,ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles) either used to discharge Cref1&2 or as the aperture to capture the input voltage on Cref1&2"
group.long 0x340++0x03
line.long 0x00 "SEQ_START,Sequencer start"
bitfld.long 0x00 9. "AZ1_SKIP,When set the AutoZero_1 state will be skipped" "0,1"
bitfld.long 0x00 8. "AZ0_SKIP,When set the AutoZero_0 state will be skipped" "0,1"
newline
bitfld.long 0x00 4. "DSI_START_EN,When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer" "0,1"
bitfld.long 0x00 3. "ABORT,When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared" "0,1"
newline
bitfld.long 0x00 1. "SEQ_MODE," "0,1"
bitfld.long 0x00 0. "START,Start the CSD sequencer" "0,1"
sif cpuis("psoc4100s")
group.long 0xF00++0x03
line.long 0x00 "TRIM_CTRL,Trim control"
bitfld.long 0x00 4.--5. "DELAY_HYS,Hystersis input for Shield Delay block" "0,1,2,3"
bitfld.long 0x00 0.--1. "DELAY_TRIM,Trim input for Shield Delay block" "0,1,2,3"
endif
tree.end
endif
tree "CTBM (Continuous Time Block Mini)"
tree "CTBM0"
base ad:0x40300000
group.long 0x00++0x03
line.long 0x00 "CTB_CTRL,global CTB and power control"
bitfld.long 0x00 31. "ENABLED," "0: CTB IP disabled (put analog in power,1: CTB IP enabled"
bitfld.long 0x00 30. "DEEPSLEEP_ON," "0: CTB IP disabled off during DeepSleep power mode,1: CTB IP remains enabled during DeepSleep power"
group.long 0x04++0x03
line.long 0x00 "OA_RES0_CTRL,Opamp0 and resistor0 control"
bitfld.long 0x00 11. "OA0_PUMP_EN,Opamp0 pump enable" "0,1"
bitfld.long 0x00 8.--9. "OA0_COMPINT,Opamp0 comparator edge detect for interrupt and pulse mode of DSI (trigger)" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
newline
bitfld.long 0x00 7. "OA0_DSI_LEVEL,Opamp0 comparator DSI (trigger) out level" "0: pulse each time an edge is detected (see,1: level DSI output is a synchronized version of"
bitfld.long 0x00 6. "OA0_BYPASS_DSI_SYNC,Opamp0 bypass comparator output synchronization for DSI (trigger) output" "0: synchronize (level or pulse),1: bypass (output async)"
newline
bitfld.long 0x00 5. "OA0_HYST_EN,Opamp0 hysteresis enable (10mV)" "0,1"
bitfld.long 0x00 4. "OA0_COMP_EN,Opamp0 comparator enable" "0,1"
newline
bitfld.long 0x00 2. "OA0_DRIVE_STR_SEL,Opamp0 output strenght select" "0,1"
bitfld.long 0x00 0.--1. "OA0_PWR_MODE,Opamp0 power level" "0: OFF,1: Low compensation setting (smallest cap..,2: Medium compensation setting,3: Highest compensation (largest cap lowest GBW)"
group.long 0x08++0x03
line.long 0x00 "OA_RES1_CTRL,Opamp1 and resistor1 control"
bitfld.long 0x00 11. "OA1_PUMP_EN,Opamp1 pump enable" "0,1"
bitfld.long 0x00 8.--9. "OA1_COMPINT,Opamp1 comparator edge detect for interrupt and pulse mode of DSI (trigger)" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
newline
bitfld.long 0x00 7. "OA1_DSI_LEVEL,Opamp1 comparator DSI (trigger) out level" "0: pulse each time an edge is detected (see,1: level DSI output is a synchronized version of"
bitfld.long 0x00 6. "OA1_BYPASS_DSI_SYNC,Opamp1 bypass comparator output synchronization for DSI output" "0: synchronize,1: bypass"
newline
bitfld.long 0x00 5. "OA1_HYST_EN,Opamp1 hysteresis enable (10mV)" "0,1"
bitfld.long 0x00 4. "OA1_COMP_EN,Opamp1 comparator enable" "0,1"
newline
bitfld.long 0x00 2. "OA1_DRIVE_STR_SEL,Opamp1 output strenght select" "0,1"
bitfld.long 0x00 0.--1. "OA1_PWR_MODE,Opamp1 power level: see description of OA0_PWR_MODE" "0,1,2,3"
rgroup.long 0x0C++0x03
line.long 0x00 "COMP_STAT,Comparator status"
bitfld.long 0x00 16. "OA1_COMP,Opamp1 current comparator status" "0,1"
bitfld.long 0x00 0. "OA0_COMP,Opamp0 current comparator status" "0,1"
group.long 0x20++0x03
line.long 0x00 "INTR,Interrupt request register"
bitfld.long 0x00 1. "COMP1,Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers" "0,1"
bitfld.long 0x00 0. "COMP0,Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers" "0,1"
group.long 0x24++0x03
line.long 0x00 "INTR_SET,Interrupt request set register"
bitfld.long 0x00 1. "COMP1_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "COMP0_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0x28++0x03
line.long 0x00 "INTR_MASK,Interrupt request mask"
bitfld.long 0x00 1. "COMP1_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "COMP0_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0x2C++0x03
line.long 0x00 "INTR_MASKED,Interrupt request masked"
bitfld.long 0x00 1. "COMP1_MASKED,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "COMP0_MASKED,Logical and of corresponding request and mask bits" "0,1"
group.long 0x30++0x03
line.long 0x00 "DFT_CTRL,Was 'Analog DfT controls' now used as Risk Mitigation bits (RMP)"
bitfld.long 0x00 31. "DFT_EN,this bit is combined with the 3 bits 2:0 to form RMP[3:0]" "0,1"
bitfld.long 0x00 0.--2. "DFT_MODE,this bit is combined with bit 31 to form RMP[3:0] it must always be written with '3' for correct operation" "0,1,2,3,4,5,6,7"
group.long 0x80++0x03
line.long 0x00 "OA0_SW,Opamp0 switch control"
bitfld.long 0x00 21. "OA0O_D81,Opamp0 output switch to short 1x with 1L0xdrive" "0,1"
bitfld.long 0x00 18. "OA0O_D51,Opamp0 output sarbus0 (ctbbus2 in CTB)" "0,1"
newline
bitfld.long 0x00 14. "OA0M_A81,Opamp0 negative terminal Opamp0 output" "0,1"
bitfld.long 0x00 8. "OA0M_A11,Opamp0 negative terminal P1" "0,1"
newline
bitfld.long 0x00 3. "OA0P_A30,Opamp0 positive terminal ctbbus0" "0,1"
bitfld.long 0x00 2. "OA0P_A20,Opamp0 positive terminal P0" "0,1"
newline
bitfld.long 0x00 0. "OA0P_A00,Opamp0 positive terminal amuxbusa" "0,1"
group.long 0x84++0x03
line.long 0x00 "OA0_SW_CLEAR,Opamp0 switch control clear"
bitfld.long 0x00 21. "OA0O_D81,see corresponding bit in OA0_SW" "0,1"
bitfld.long 0x00 18. "OA0O_D51,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x00 14. "OA0M_A81,see corresponding bit in OA0_SW" "0,1"
bitfld.long 0x00 8. "OA0M_A11,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x00 3. "OA0P_A30,see corresponding bit in OA0_SW" "0,1"
bitfld.long 0x00 2. "OA0P_A20,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x00 0. "OA0P_A00,see corresponding bit in OA0_SW" "0,1"
group.long 0x88++0x03
line.long 0x00 "OA1_SW,Opamp1 switch control"
bitfld.long 0x00 21. "OA1O_D82,Opamp1 output switch to short 1x with 1L0xdrive" "0,1"
bitfld.long 0x00 19. "OA1O_D62,Opamp1 output sarbus1 (ctbbus3 in CTB)" "0,1"
newline
bitfld.long 0x00 18. "OA1O_D52,Opamp1 output sarbus0 (ctbbus2 in CTB)" "0,1"
bitfld.long 0x00 14. "OA1M_A82,Opamp1 negative terminal Opamp1 output" "0,1"
newline
bitfld.long 0x00 8. "OA1M_A22,Opamp1 negative terminal P4" "0,1"
bitfld.long 0x00 4. "OA1P_A43,Opamp1 positive terminal ctbbus1" "0,1"
newline
bitfld.long 0x00 1. "OA1P_A13,Opamp1 positive terminal P5" "0,1"
bitfld.long 0x00 0. "OA1P_A03,Opamp1 positive terminal amuxbusb" "0,1"
group.long 0x8C++0x03
line.long 0x00 "OA1_SW_CLEAR,Opamp1 switch control clear"
bitfld.long 0x00 21. "OA1O_D82,see corresponding bit in OA1_SW" "0,1"
bitfld.long 0x00 19. "OA1O_D62,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0x00 18. "OA1O_D52,see corresponding bit in OA1_SW" "0,1"
bitfld.long 0x00 14. "OA1M_A82,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0x00 8. "OA1M_A22,see corresponding bit in OA1_SW" "0,1"
bitfld.long 0x00 4. "OA1P_A43,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0x00 1. "OA1P_A13,see corresponding bit in OA1_SW" "0,1"
bitfld.long 0x00 0. "OA1P_A03,see corresponding bit in OA1_SW" "0,1"
group.long 0xC0++0x03
line.long 0x00 "CTB_SW_HW_CTRL,CTB bus switch control"
bitfld.long 0x00 3. "P3_HW_CTRL,for P33 D52 D62 (dsi_out[3])" "0,1"
bitfld.long 0x00 2. "P2_HW_CTRL,for P22 D51 (dsi_out[2])" "0,1"
rgroup.long 0xC4++0x03
line.long 0x00 "CTB_SW_STATUS,CTB bus switch control status"
bitfld.long 0x00 30. "OA1O_D62_STAT,see OA1O_D62 bit in OA1_SW" "0,1"
bitfld.long 0x00 29. "OA1O_D52_STAT,see OA1O_D52 bit in OA1_SW" "0,1"
newline
bitfld.long 0x00 28. "OA0O_D51_STAT,see OA0O_D51 bit in OA0_SW" "0,1"
group.long 0xF00++0x03
line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 trim control"
bitfld.long 0x00 0.--5. "OA0_OFFSET_TRIM,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF04++0x03
line.long 0x00 "OA0_SLOPE_OFFSET_TRIM,Opamp0 trim control"
bitfld.long 0x00 0.--5. "OA0_SLOPE_OFFSET_TRIM,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF08++0x03
line.long 0x00 "OA0_COMP_TRIM,Opamp0 trim control"
bitfld.long 0x00 0.--1. "OA0_COMP_TRIM,Opamp0 Compenation Capacitor Trim" "0,1,2,3"
group.long 0xF0C++0x03
line.long 0x00 "OA1_OFFSET_TRIM,Opamp1 trim control"
bitfld.long 0x00 0.--5. "OA1_OFFSET_TRIM,Opamp1 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF10++0x03
line.long 0x00 "OA1_SLOPE_OFFSET_TRIM,Opamp1 trim control"
bitfld.long 0x00 0.--5. "OA1_SLOPE_OFFSET_TRIM,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF14++0x03
line.long 0x00 "OA1_COMP_TRIM,Opamp1 trim control"
bitfld.long 0x00 0.--1. "OA1_COMP_TRIM,Opamp1 Compenation Capacitor Trim" "0,1,2,3"
tree.end
sif cpuis("CY8C4148*")
tree "CTBM1"
base ad:0x40400000
group.long 0x00++0x03
line.long 0x00 "CTB_CTRL,global CTB and power control"
bitfld.long 0x00 31. "ENABLED," "0: CTB IP disabled (put analog in power,1: CTB IP enabled"
bitfld.long 0x00 30. "DEEPSLEEP_ON," "0: CTB IP disabled off during DeepSleep power mode,1: CTB IP remains enabled during DeepSleep power"
group.long 0x04++0x03
line.long 0x00 "OA_RES0_CTRL,Opamp0 and resistor0 control"
bitfld.long 0x00 11. "OA0_PUMP_EN,Opamp0 pump enable" "0,1"
bitfld.long 0x00 8.--9. "OA0_COMPINT,Opamp0 comparator edge detect for interrupt and pulse mode of DSI (trigger)" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
newline
bitfld.long 0x00 7. "OA0_DSI_LEVEL,Opamp0 comparator DSI (trigger) out level" "0: pulse each time an edge is detected (see,1: level DSI output is a synchronized version of"
bitfld.long 0x00 6. "OA0_BYPASS_DSI_SYNC,Opamp0 bypass comparator output synchronization for DSI (trigger) output" "0: synchronize (level or pulse),1: bypass (output async)"
newline
bitfld.long 0x00 5. "OA0_HYST_EN,Opamp0 hysteresis enable (10mV)" "0,1"
bitfld.long 0x00 4. "OA0_COMP_EN,Opamp0 comparator enable" "0,1"
newline
bitfld.long 0x00 2. "OA0_DRIVE_STR_SEL,Opamp0 output strenght select" "0,1"
bitfld.long 0x00 0.--1. "OA0_PWR_MODE,Opamp0 power level" "0: OFF,1: Low compensation setting (smallest cap..,2: Medium compensation setting,3: Highest compensation (largest cap lowest GBW)"
group.long 0x08++0x03
line.long 0x00 "OA_RES1_CTRL,Opamp1 and resistor1 control"
bitfld.long 0x00 11. "OA1_PUMP_EN,Opamp1 pump enable" "0,1"
bitfld.long 0x00 8.--9. "OA1_COMPINT,Opamp1 comparator edge detect for interrupt and pulse mode of DSI (trigger)" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
newline
bitfld.long 0x00 7. "OA1_DSI_LEVEL,Opamp1 comparator DSI (trigger) out level" "0: pulse each time an edge is detected (see,1: level DSI output is a synchronized version of"
bitfld.long 0x00 6. "OA1_BYPASS_DSI_SYNC,Opamp1 bypass comparator output synchronization for DSI output" "0: synchronize,1: bypass"
newline
bitfld.long 0x00 5. "OA1_HYST_EN,Opamp1 hysteresis enable (10mV)" "0,1"
bitfld.long 0x00 4. "OA1_COMP_EN,Opamp1 comparator enable" "0,1"
newline
bitfld.long 0x00 2. "OA1_DRIVE_STR_SEL,Opamp1 output strenght select" "0,1"
bitfld.long 0x00 0.--1. "OA1_PWR_MODE,Opamp1 power level: see description of OA0_PWR_MODE" "0,1,2,3"
rgroup.long 0x0C++0x03
line.long 0x00 "COMP_STAT,Comparator status"
bitfld.long 0x00 16. "OA1_COMP,Opamp1 current comparator status" "0,1"
bitfld.long 0x00 0. "OA0_COMP,Opamp0 current comparator status" "0,1"
group.long 0x20++0x03
line.long 0x00 "INTR,Interrupt request register"
bitfld.long 0x00 1. "COMP1,Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers" "0,1"
bitfld.long 0x00 0. "COMP0,Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers" "0,1"
group.long 0x24++0x03
line.long 0x00 "INTR_SET,Interrupt request set register"
bitfld.long 0x00 1. "COMP1_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "COMP0_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0x28++0x03
line.long 0x00 "INTR_MASK,Interrupt request mask"
bitfld.long 0x00 1. "COMP1_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "COMP0_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0x2C++0x03
line.long 0x00 "INTR_MASKED,Interrupt request masked"
bitfld.long 0x00 1. "COMP1_MASKED,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "COMP0_MASKED,Logical and of corresponding request and mask bits" "0,1"
group.long 0x30++0x03
line.long 0x00 "DFT_CTRL,Was 'Analog DfT controls' now used as Risk Mitigation bits (RMP)"
bitfld.long 0x00 31. "DFT_EN,this bit is combined with the 3 bits 2:0 to form RMP[3:0]" "0,1"
bitfld.long 0x00 0.--2. "DFT_MODE,this bit is combined with bit 31 to form RMP[3:0] it must always be written with '3' for correct operation" "0,1,2,3,4,5,6,7"
group.long 0x80++0x03
line.long 0x00 "OA0_SW,Opamp0 switch control"
bitfld.long 0x00 21. "OA0O_D81,Opamp0 output switch to short 1x with 1L0xdrive" "0,1"
bitfld.long 0x00 18. "OA0O_D51,Opamp0 output sarbus0 (ctbbus2 in CTB)" "0,1"
newline
bitfld.long 0x00 14. "OA0M_A81,Opamp0 negative terminal Opamp0 output" "0,1"
bitfld.long 0x00 8. "OA0M_A11,Opamp0 negative terminal P1" "0,1"
newline
bitfld.long 0x00 3. "OA0P_A30,Opamp0 positive terminal ctbbus0" "0,1"
bitfld.long 0x00 2. "OA0P_A20,Opamp0 positive terminal P0" "0,1"
newline
bitfld.long 0x00 0. "OA0P_A00,Opamp0 positive terminal amuxbusa" "0,1"
group.long 0x84++0x03
line.long 0x00 "OA0_SW_CLEAR,Opamp0 switch control clear"
bitfld.long 0x00 21. "OA0O_D81,see corresponding bit in OA0_SW" "0,1"
bitfld.long 0x00 18. "OA0O_D51,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x00 14. "OA0M_A81,see corresponding bit in OA0_SW" "0,1"
bitfld.long 0x00 8. "OA0M_A11,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x00 3. "OA0P_A30,see corresponding bit in OA0_SW" "0,1"
bitfld.long 0x00 2. "OA0P_A20,see corresponding bit in OA0_SW" "0,1"
newline
bitfld.long 0x00 0. "OA0P_A00,see corresponding bit in OA0_SW" "0,1"
group.long 0x88++0x03
line.long 0x00 "OA1_SW,Opamp1 switch control"
bitfld.long 0x00 21. "OA1O_D82,Opamp1 output switch to short 1x with 1L0xdrive" "0,1"
bitfld.long 0x00 19. "OA1O_D62,Opamp1 output sarbus1 (ctbbus3 in CTB)" "0,1"
newline
bitfld.long 0x00 18. "OA1O_D52,Opamp1 output sarbus0 (ctbbus2 in CTB)" "0,1"
bitfld.long 0x00 14. "OA1M_A82,Opamp1 negative terminal Opamp1 output" "0,1"
newline
bitfld.long 0x00 8. "OA1M_A22,Opamp1 negative terminal P4" "0,1"
bitfld.long 0x00 4. "OA1P_A43,Opamp1 positive terminal ctbbus1" "0,1"
newline
bitfld.long 0x00 1. "OA1P_A13,Opamp1 positive terminal P5" "0,1"
bitfld.long 0x00 0. "OA1P_A03,Opamp1 positive terminal amuxbusb" "0,1"
group.long 0x8C++0x03
line.long 0x00 "OA1_SW_CLEAR,Opamp1 switch control clear"
bitfld.long 0x00 21. "OA1O_D82,see corresponding bit in OA1_SW" "0,1"
bitfld.long 0x00 19. "OA1O_D62,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0x00 18. "OA1O_D52,see corresponding bit in OA1_SW" "0,1"
bitfld.long 0x00 14. "OA1M_A82,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0x00 8. "OA1M_A22,see corresponding bit in OA1_SW" "0,1"
bitfld.long 0x00 4. "OA1P_A43,see corresponding bit in OA1_SW" "0,1"
newline
bitfld.long 0x00 1. "OA1P_A13,see corresponding bit in OA1_SW" "0,1"
bitfld.long 0x00 0. "OA1P_A03,see corresponding bit in OA1_SW" "0,1"
group.long 0xC0++0x03
line.long 0x00 "CTB_SW_HW_CTRL,CTB bus switch control"
bitfld.long 0x00 3. "P3_HW_CTRL,for P33 D52 D62 (dsi_out[3])" "0,1"
bitfld.long 0x00 2. "P2_HW_CTRL,for P22 D51 (dsi_out[2])" "0,1"
rgroup.long 0xC4++0x03
line.long 0x00 "CTB_SW_STATUS,CTB bus switch control status"
bitfld.long 0x00 30. "OA1O_D62_STAT,see OA1O_D62 bit in OA1_SW" "0,1"
bitfld.long 0x00 29. "OA1O_D52_STAT,see OA1O_D52 bit in OA1_SW" "0,1"
newline
bitfld.long 0x00 28. "OA0O_D51_STAT,see OA0O_D51 bit in OA0_SW" "0,1"
group.long 0xF00++0x03
line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 trim control"
bitfld.long 0x00 0.--5. "OA0_OFFSET_TRIM,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF04++0x03
line.long 0x00 "OA0_SLOPE_OFFSET_TRIM,Opamp0 trim control"
bitfld.long 0x00 0.--5. "OA0_SLOPE_OFFSET_TRIM,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF08++0x03
line.long 0x00 "OA0_COMP_TRIM,Opamp0 trim control"
bitfld.long 0x00 0.--1. "OA0_COMP_TRIM,Opamp0 Compenation Capacitor Trim" "0,1,2,3"
group.long 0xF0C++0x03
line.long 0x00 "OA1_OFFSET_TRIM,Opamp1 trim control"
bitfld.long 0x00 0.--5. "OA1_OFFSET_TRIM,Opamp1 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF10++0x03
line.long 0x00 "OA1_SLOPE_OFFSET_TRIM,Opamp1 trim control"
bitfld.long 0x00 0.--5. "OA1_SLOPE_OFFSET_TRIM,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF14++0x03
line.long 0x00 "OA1_COMP_TRIM,Opamp1 trim control"
bitfld.long 0x00 0.--1. "OA1_COMP_TRIM,Opamp1 Compenation Capacitor Trim" "0,1,2,3"
tree.end
endif
tree.end
sif cpuis("CY8C4149*")||cpuis("CY8C4147*")||cpuis("CY8C4146A*")||cpuis("CY8C4148*")
tree "DMAC (DataWire/DMA Controller)"
base ad:0x40101000
sif cpuis("psoc4100smax")
group.long 0x00++0x03
line.long 0x00 "CTL,Control register"
bitfld.long 0x00 31. "ENABLED,0': IP is disabled" "0,1"
rgroup.long 0x10++0x03
line.long 0x00 "STATUS,Status register"
bitfld.long 0x00 31. "ACTIVE,Specifies if there is a currently active (pending) channel in the data transfer engine: '0': no currently active channel" "0,1"
bitfld.long 0x00 30. "PING_PONG,Specifies whether the PING descriptor ('0') or PONG descriptor ('1') of the channel is currently in use" "0,1"
newline
bitfld.long 0x00 28.--29. "PRIO,Specifies the priority of the currently active channel" "0,1,2,3"
bitfld.long 0x00 24.--26. "STATE,State of the data transfer engine" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--20. "CH_ADDR,Specifies the channel number of the currently active channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 0.--15. 1. "DATA_NR,Specifies the index of the currently active data transfer"
rgroup.long 0x14++0x03
line.long 0x00 "STATUS_SRC_ADDR,Source address status register"
hexmask.long 0x00 0.--31. 1. "ADDR,Base address or current address of source location of currently active channel"
rgroup.long 0x18++0x03
line.long 0x00 "STATUS_DST_ADDR,Destination address register"
hexmask.long 0x00 0.--31. 1. "ADDR,Base address or current address of destination location of currently active channel"
rgroup.long 0x1C++0x03
line.long 0x00 "STATUS_CH_ACT,Channel activation status register"
hexmask.long 0x00 0.--31. 1. "CH,Channel activation status"
repeat 32. (increment 0 1) (increment 0 0x4)
group.long ($2+0x80)++0x03
line.long 0x00 "CH_CTL[$1],Channel control register $1"
bitfld.long 0x00 31. "ENABLED,'0': channel disabled" "0,1"
bitfld.long 0x00 30. "PING_PONG,Each channel has two descriptor structures for double buffering purposes" "0,1"
newline
bitfld.long 0x00 28.--29. "PRIO,Channel priority with '0' representing the highest priority and '3' representing the lowest priority" "0,1,2,3"
repeat.end
group.long 0x7F0++0x03
line.long 0x00 "INTR,Interrupt register"
hexmask.long 0x00 0.--31. 1. "CH,Set to '1' when event is detected"
group.long 0x7F4++0x03
line.long 0x00 "INTR_SET,Interrupt set register"
hexmask.long 0x00 0.--31. 1. "CH,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)"
group.long 0x7F8++0x03
line.long 0x00 "INTR_MASK,Interrupt mask register"
hexmask.long 0x00 0.--31. 1. "CH,Mask for corresponding field in INTR register"
rgroup.long 0x7FC++0x03
line.long 0x00 "INTR_MASKED,Interrupt masked register"
hexmask.long 0x00 0.--31. 1. "CH,Logical and of corresponding request and mask fields"
endif
repeat 16. (increment 0 1)(increment 0 0x20)
tree "DESCR[$1]"
sif cpuis("psoc4100smax")
group.long ($2+0x800)++0x03
line.long 0x00 "PING_SRC,Ping source address"
hexmask.long 0x00 0.--31. 1. "ADDR,Base address of source location"
group.long ($2+0x804)++0x03
line.long 0x00 "PING_DST,Ping destination address"
hexmask.long 0x00 0.--31. 1. "ADDR,Base address of destination location"
group.long ($2+0x808)++0x03
line.long 0x00 "PING_CTL,Ping control word"
bitfld.long 0x00 30.--31. "OPCODE,Specifies the specific data transfer (only when the VALID bit of the descriptor's STATUS word is '1'): '0': A single trigger initiates a single data element transfer (DW mode)" "0,1,2,3"
bitfld.long 0x00 29. "FLIPPING,'1': On completion of the current descriptor structure the current descriptor identifier CHi_CTL.PING_PONG is flipped/inverted" "0,1"
newline
bitfld.long 0x00 28. "PREEMPTABLE,'1': Transfer is preemptable" "0,1"
bitfld.long 0x00 27. "SET_CAUSE,'1': On completion of the current descriptor structure the interrupt cause field of the channel is set to '1' (INTR.CH[i])" "0,1"
newline
bitfld.long 0x00 26. "INV_DESCR,'1': On completion of the current descriptor structure the VALID bit of the descriptor's STATUS word is set to '0'" "0,1"
bitfld.long 0x00 24.--25. "WAIT_FOR_DEACT,Specifies whether the data transfer engine should wait for the channel to be deactivated i.e" "0,1,2,3"
newline
bitfld.long 0x00 23. "SRC_ADDR_INCR,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "0,1"
bitfld.long 0x00 22. "SRC_TRANSFER_SIZE,Specifies the bus transfer size to the source location: '0': As specified by DATA_SIZE" "0,1"
newline
bitfld.long 0x00 21. "DST_ADDR_INCR,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "0,1"
bitfld.long 0x00 20. "DST_TRANSFER_SIZE,Specifies the bus transfer size to the destination location: '0': As specified by DATA_SIZE" "0,1"
newline
bitfld.long 0x00 16.--17. "DATA_SIZE,Specifies the data element size: '0': Byte (8 bits)" "0,1,2,3"
hexmask.long.word 0x00 0.--15. 1. "DATA_NR,Number of data elements that are transferred by a single descriptor"
group.long ($2+0x80C)++0x03
line.long 0x00 "PING_STATUS,Ping status word"
bitfld.long 0x00 31. "VALID,'0': Invalid cannot be used for a data transfer" "0,1"
bitfld.long 0x00 16.--18. "RESPONSE,Response code (the first two codes NO_ERROR and DONE are the result of normal behavior the other codes are the result of erroneous behavior)" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "CURR_DATA_NR,Specifies the index of the current data transfer"
group.long ($2+0x810)++0x03
line.long 0x00 "PONG_SRC,Pong source address"
hexmask.long 0x00 0.--31. 1. "ADDR,See description of PING_SRC"
group.long ($2+0x814)++0x03
line.long 0x00 "PONG_DST,Pong destination address"
hexmask.long 0x00 0.--31. 1. "ADDR,See description of PING_DST"
group.long ($2+0x818)++0x03
line.long 0x00 "PONG_CTL,Pong control word"
bitfld.long 0x00 30.--31. "OPCODE,See description of PING_CTL" "0,1,2,3"
bitfld.long 0x00 29. "FLIPPING,See description of PING_CTL" "0,1"
newline
bitfld.long 0x00 28. "PREEMPTABLE,See description of PING_CTL" "0,1"
bitfld.long 0x00 27. "SET_CAUSE,See description of PING_CTL" "0,1"
newline
bitfld.long 0x00 26. "INV_DESCR,See description of PING_CTL" "0,1"
bitfld.long 0x00 24.--25. "WAIT_FOR_DEACT,See description of PING_CTL" "0,1,2,3"
newline
bitfld.long 0x00 23. "SRC_ADDR_INCR,See description of PING_CTL" "0,1"
bitfld.long 0x00 22. "SRC_TRANSFER_SIZE,See description of PING_CTL" "0,1"
newline
bitfld.long 0x00 21. "DST_ADDR_INCR,See description of PING_CTL" "0,1"
bitfld.long 0x00 20. "DST_TRANSFER_SIZE,See description of PING_CTL" "0,1"
newline
bitfld.long 0x00 16.--17. "DATA_SIZE,See description of PING_CTL" "0,1,2,3"
hexmask.long.word 0x00 0.--15. 1. "DATA_NR,See description of PING_CTL"
group.long ($2+0x81C)++0x03
line.long 0x00 "PONG_STATUS,Pong status word"
bitfld.long 0x00 31. "VALID,See description of PING_STATUS" "0,1"
bitfld.long 0x00 16.--18. "RESPONSE,See description of PING_STATUS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--15. 1. "CURR_DATA_NR,See description of PING_STATUS"
endif
tree.end
repeat.end
tree.end
tree "EXCO (ECO+PLL as SRSSLT clk_eco external source)"
base ad:0x402F0000
sif cpuis("psoc4100smax")||cpuis("psoc4100sp256kb")
group.long 0x00++0x03
line.long 0x00 "CLK_SELECT,Clock Select Register"
bitfld.long 0x00 1.--2. "REF_SEL,Select source for PLL reference" "0: From ECO,1: From external reference,2: From CLK_IMO,?..."
bitfld.long 0x00 0. "CLK_SELECT,When PLL_CONFIG.ENABLE=0 then clk_eco=clk_osc" "0: clk_eco=clk_osc PLL_CONFIG.BYPASS=0x,1: PLL_CONFIG.BYPASS=xx PLL_STATUS.LOCKED = x"
endif
sif cpuis("psoc4100sp")
group.long 0x00++0x03
line.long 0x00 "CLK_SELECT,Clock Select Register"
bitfld.long 0x00 1. "REF_SEL,Select source for PLL reference" "0: from ECO,1: from external reference"
bitfld.long 0x00 0. "CLK_SELECT,When PLL_CONFIG.ENABLE=0 then clk_eco=clk_osc" "0: clk_eco=clk_osc PLL_CONFIG.BYPASS=0x,1: PLL_CONFIG.BYPASS=xx PLL_STATUS.LOCKED = x"
endif
group.long 0x08++0x03
line.long 0x00 "ECO_CONFIG,ECO Configuration Register"
bitfld.long 0x00 31. "ENABLE,Master enable for ECO oscillator" "0,1"
bitfld.long 0x00 1. "AGC_EN,Automatic Gain Control (AGC) enable" "0,1"
newline
bitfld.long 0x00 0. "CLK_EN,Clock Enable" "0,1"
sif cpuis("psoc4100smax")||cpuis("psoc4100sp256kb")
rgroup.long 0x0C++0x03
line.long 0x00 "ECO_STATUS,ECO Status Register"
bitfld.long 0x00 0. "WATCHDOG_ERROR,This bit is set to 1 if the oscillator is stuck" "0,1"
endif
sif cpuis("psoc4100sp")
rgroup.long 0x0C++0x03
line.long 0x00 "ECO_STATUS,ECO Status Register"
bitfld.long 0x00 0. "WATCHDOG_ERROR,This bit is set to 1 if the oscillator is stuck" "0,1"
endif
group.long 0x14++0x03
line.long 0x00 "PLL_CONFIG,PLL Configuration Register"
bitfld.long 0x00 31. "ENABLE,Master enable for PLL power gate" "0: Block is powered off also forces clk_eco =,1: Block is powered on"
bitfld.long 0x00 30. "ISOLATE_N,Isolation control of PLL outputs" "0: Isolate outputs Precharge PLL control voltage..,1: Do not isolate outputs"
newline
bitfld.long 0x00 20.--21. "BYPASS_SEL,Selects the source of the system PLL0 clock" "0: Automatic using lock indicator,1: Same as AUTO,2: Select PLL reference input (bypass mode),3: Select PLL output"
bitfld.long 0x00 16.--18. "ICP_SEL,Programmable charge pump current between 0uA and 7uA" "0: 0uA (Hi-Z) Engineering use only,1: 1uA,2: 2uA,3: 3uA,?..."
newline
bitfld.long 0x00 14.--15. "OUTPUT_DIV,Control bits for Output divider" "0: Pass Through,1: Divide by 2,2: Divide by 4,3: Divide by 8"
bitfld.long 0x00 8.--13. "REFERENCE_DIV,Control bits for reference divider: Divide by" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x00 0.--7. 1. "FEEDBACK_DIV,Control bits for feedback divider: Valid divide is 8-255"
rgroup.long 0x18++0x03
line.long 0x00 "PLL_STATUS,PLL Status Register"
bitfld.long 0x00 0. "LOCKED,PLL Lock Indicator - See CLK_SELECT.CLK_SELECT description for interaction with clk_eco selection" "0,1"
group.long 0x1C++0x03
line.long 0x00 "PLL_TEST,PLL Test Register"
bitfld.long 0x00 4. "UNLOCK_OCCURRED,This bit sets whenever the PLL Lock bit goes low and stays set until cleared by firmware" "0,1"
bitfld.long 0x00 3. "FAST_LOCK_EN,Fast Lock Enable - Speeds up the lock time when set to 1" "0,1"
newline
bitfld.long 0x00 0.--2. "TEST_MODE,Test Mode" "0: Normal Operation,1: Vcontrol Leakage Test Mode Measure frequency..,2: Charge Pump Down Current Test Mode With..,3: Charge Pump Up Current Test Mode With..,4: User Mode with Extended Fast Lock Precharge,5: Reference and Feedback Counter Test Mode,6: Lock Detector Delay Line Test Mode,7: Lock Detector Wait and Extended Fast Lock.."
sif cpuis("psoc4100smax")||cpuis("psoc4100sp256kb")
group.long 0x20++0x03
line.long 0x00 "EXCO_PGM_CLK,EXCO Program Clock"
bitfld.long 0x00 31. "ENABLE,Enable bit-banging test capability in this register" "0,1"
bitfld.long 0x00 4. "EN_CLK_PLL0,Bit bang en_clk_pll0" "0,1"
newline
bitfld.long 0x00 3. "CLK_PLL0_OUT,Bit bang clk_pll0_out" "0,1"
rbitfld.long 0x00 2. "CLK_PLL0_IN,Observation point for clk_pll0_in not retained" "0,1"
newline
bitfld.long 0x00 1. "CLK_ECO,Bit bang clk_eco" "0,1"
endif
sif cpuis("psoc4100sp")
group.long 0x20++0x03
line.long 0x00 "EXCO_PGM_CLK,EXCO Program Clock"
bitfld.long 0x00 31. "ENABLE,Enable bit-banging test capability in this register" "0,1"
bitfld.long 0x00 4. "EN_CLK_PLL0,Bit bang en_clk_pll0" "0,1"
newline
bitfld.long 0x00 3. "CLK_PLL0_OUT,Bit bang clk_pll0_out" "0,1"
rbitfld.long 0x00 2. "CLK_PLL0_IN,Observation point for clk_pll0_in" "0,1"
newline
bitfld.long 0x00 1. "CLK_ECO,Bit bang clk_eco" "0,1"
endif
sif cpuis("psoc4100smax")||cpuis("psoc4100sp256kb")
group.long 0x30++0x03
line.long 0x00 "REF_CTL,Clock Supervision Reference Contol"
bitfld.long 0x00 31. "CSV_EN,Enables clock supervision both frequency and loss" "0,1"
bitfld.long 0x00 18. "CSV_CLK_SW_EN,Enable CSV to cause Clock Switch to IMO when set" "0,1"
newline
bitfld.long 0x00 17. "CSV_TRIG_EN,Enable CSV to cause trigger if a clock switch occurs to IMO" "0,1"
bitfld.long 0x00 16. "CSV_INT_EN,Enable CSV setting INT.CSV_CLK_SW if a clock switch occurs to IMO" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "STARTUP,Startup delay time -1 (in reference clock cycles) after enable or DeepSleep wakeup from reference clock start to monitored clock start"
group.long 0x34++0x03
line.long 0x00 "REF_LIMIT,Clock Supervision Reference Limits"
hexmask.long.word 0x00 16.--31. 1. "UPPER,Cycle time upper limit"
hexmask.long.word 0x00 0.--15. 1. "LOWER,Cycle time lower limit"
group.long 0x38++0x03
line.long 0x00 "MON_CTL,Clock Supervision Monitor Control"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,Period time"
group.long 0x40++0x03
line.long 0x00 "INTR,Interrupt Request Register"
bitfld.long 0x00 2. "CSV_CLK_SW,Clock Supervisor Switched Clock Source to IMO" "0,1"
bitfld.long 0x00 1. "WD_ERR,EXCO Watch Dog Error detected - Oscillator stopped oscillating" "0,1"
newline
bitfld.long 0x00 0. "PLL_LOCK,HW will set this bit when PLL loses lock (PLL 'locked' output goes low)" "0,1"
group.long 0x44++0x03
line.long 0x00 "INTR_SET,Interrupt Set Register"
bitfld.long 0x00 2. "CSV_CLK_SW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "WD_ERR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "PLL_LOCK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0x48++0x03
line.long 0x00 "INTR_MASK,Interrupt Mask Register"
bitfld.long 0x00 2. "CSV_CLK_SW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "WD_ERR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "PLL_LOCK,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0x4C++0x03
line.long 0x00 "INTR_MASKED,Interrrupt Masked Register"
bitfld.long 0x00 2. "CSV_CLK_SW,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 1. "WD_ERR,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 0. "PLL_LOCK,Logical and of corresponding request and mask bits" "0,1"
group.long 0x50++0x03
line.long 0x00 "RSTDLY_CTL,Programmable Delay Counter Control"
bitfld.long 0x00 31. "EN,Programmable Delay Counter Enable '0': Disable '1': Enable" "0,1"
bitfld.long 0x00 0. "LOAD,Programmable Delay Counter Load - Reloads the DLYCOUNT into the COUNT_VAL register" "0: No Action,1: Generate a 1 clock pulse"
group.long 0x54++0x03
line.long 0x00 "RSTDLY,Programmable Delay Counter Initial Amount"
hexmask.long.word 0x00 0.--15. 1. "DLYCOUNT,Delay Count Value"
rgroup.long 0x58++0x03
line.long 0x00 "RSTDLY_COUNT_VAL,Programmable Delay Counter Value"
hexmask.long.word 0x00 0.--15. 1. "COUNT_VAL,Current Programmable Delay Counter value"
endif
group.long 0xFF00++0x03
line.long 0x00 "ECO_TRIM0,ECO Trim0 Register"
bitfld.long 0x00 2.--4. "ATRIM,Amplitude trim to set the crystal drive level when ECO_CONFIG.AGC_EN=1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--1. "WDTRIM,Watch Dog Trim - Delta voltage below stead state level" "0,1,2,3"
group.long 0xFF04++0x03
line.long 0x00 "ECO_TRIM1,ECO Trim1 Register"
bitfld.long 0x00 4.--5. "GTRIM,Gain Trim - Startup time" "0,1,2,3"
bitfld.long 0x00 2.--3. "RTRIM,Feedback resistor Trim" "0,1,2,3"
newline
bitfld.long 0x00 0.--1. "FTRIM,Filter Trim - 3rd harmonic oscillation" "0,1,2,3"
group.long 0xFF08++0x03
line.long 0x00 "ECO_TRIM2,ECO Trim2 Register"
bitfld.long 0x00 0.--5. "ITRIM,Current Trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xFF0C++0x03
line.long 0x00 "PLL_TRIM,PLL Trim Register"
bitfld.long 0x00 4.--5. "LOCK_DELAY,Selects the number of PLL phase frequency detector cycles that the phase error must be in range before declaring lock" "0: 16 PFD clock cycles,1: 32 PFD clock cycles,2: 48 PFD clock cycles,3: 64 PFD clock cycles"
bitfld.long 0x00 2.--3. "LOCK_WINDOW,Selects the allowed phase error before declaring the PLL Unlocked" "0: Delay 25 ns,1: Delay 50 ns,2: Delay 75 ns,3: Delay 100 ns"
newline
bitfld.long 0x00 0.--1. "VCO_GAIN,Programmable VCO frequency characteristic at high freq - set to <10>" "0,1,2,3"
tree.end
endif
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
base ad:0x40040000
sif cpuis("psoc4100smax")
rgroup.long 0x1000++0x03
line.long 0x00 "INTR_CAUSE,Interrupt port cause register"
hexmask.long 0x00 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register"
rgroup.long 0x1020++0x03
line.long 0x00 "GPIOV1P2_DET,GPIOV1P2 Detect output"
bitfld.long 0x00 0. "DET,Indicates HI when VDDIO is in 1.8V range and LOW when VDDIO is in 1.2V range" "0,1"
endif
repeat 13. (increment 0 1)(increment 0 0x100)
tree "PRT[$1]"
sif cpuis("psoc4100smax")
group.long ($2+0x00)++0x03
line.long 0x00 "DR,Port output data register"
bitfld.long 0x00 7. "DATA7,IO pad 7 output data" "0,1"
bitfld.long 0x00 6. "DATA6,IO pad 6 output data" "0,1"
newline
bitfld.long 0x00 5. "DATA5,IO pad 5 output data" "0,1"
bitfld.long 0x00 4. "DATA4,IO pad 4 output data" "0,1"
newline
bitfld.long 0x00 3. "DATA3,IO pad 3 output data" "0,1"
bitfld.long 0x00 2. "DATA2,IO pad 2 output data" "0,1"
newline
bitfld.long 0x00 1. "DATA1,IO pad 1 output data" "0,1"
bitfld.long 0x00 0. "DATA0,IO pad 0 output data" "0,1"
rgroup.long ($2+0x04)++0x03
line.long 0x00 "PS,Port IO pad state register"
bitfld.long 0x00 8. "FLT_DATA,Reads of this register return the logical state of the filtered pin" "0,1"
bitfld.long 0x00 7. "DATA7,IO pad 7 state" "0,1"
newline
bitfld.long 0x00 6. "DATA6,IO pad 6 state" "0,1"
bitfld.long 0x00 5. "DATA5,IO pad 5 state" "0,1"
newline
bitfld.long 0x00 4. "DATA4,IO pad 4 state" "0,1"
bitfld.long 0x00 3. "DATA3,IO pad 3 state" "0,1"
newline
bitfld.long 0x00 2. "DATA2,IO pad 2 state" "0,1"
bitfld.long 0x00 1. "DATA1,IO pad 1 state" "0,1"
newline
bitfld.long 0x00 0. "DATA0,IO pad 0 state" "0: Logic low if the pin voltage is below that,1: Logic high if the pin voltage is above the.."
group.long ($2+0x08)++0x03
line.long 0x00 "PC,Port configuration register"
bitfld.long 0x00 30.--31. "PORT_IB_MODE_SEL,This field selects the input buffer reference" "0,1,2,3"
bitfld.long 0x00 28.--29. "PORT_SLEW_CTL,Slew control" "0: HS mode (100pf < Cb < 400pF 1.71<VDDD<5.5..,1: HS mode (Cb<100pf 1.71<VDDD<5.5 Vext>2.8..,2: HS mode (100pf<Cb<400pf 1.71<VDDD<5.5..,3: HS mode (Cb<100pf 1.71<VDDD<5.5 Vext<=2.8.."
newline
bitfld.long 0x00 27. "PORT_HYST_TRIM,This field is used to improve the hysteresis (to 10 percent of vddio) of the selectable trip point input buffer" "0,1"
bitfld.long 0x00 25. "PORT_SLOW,This field controls the output edge rate of all pins on the port: '0': fast" "0,1"
newline
bitfld.long 0x00 24. "PORT_VTRIP_SEL,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "0: input buffer functions as a CMOS input buffer,1: input buffer functions as a LVTTL input buffer"
bitfld.long 0x00 21.--23. "DM7,The GPIO drive mode for IO pad 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 18.--20. "DM6,The GPIO drive mode for IO pad 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15.--17. "DM5,The GPIO drive mode for IO pad 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "DM4,The GPIO drive mode for IO pad 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9.--11. "DM3,The GPIO drive mode for IO pad 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--8. "DM2,The GPIO drive mode for IO pad 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 3.--5. "DM1,The GPIO drive mode for IO pad 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "DM0,The GPIO drive mode for IO pad 0" "0: Mode 0 (analog mode),1: Mode 1,2: Mode 2,3: Mode 3,4: Mode 4,5: Mode 5,6: Mode 6,7: Mode 7"
group.long ($2+0x0C)++0x03
line.long 0x00 "INTR_CFG,Port interrupt configuration register"
bitfld.long 0x00 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--17. "FLT_EDGE_SEL,Same for the glitch filtered pin (selected by FLT_SELECT)" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
newline
bitfld.long 0x00 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pad 7" "0,1,2,3"
bitfld.long 0x00 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pad 6" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pad 5" "0,1,2,3"
bitfld.long 0x00 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pad 4" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pad 3" "0,1,2,3"
bitfld.long 0x00 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pad 2" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pad 1" "0,1,2,3"
bitfld.long 0x00 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pad 0" "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
group.long ($2+0x10)++0x03
line.long 0x00 "INTR,Port interrupt status register"
rbitfld.long 0x00 24. "PS_FLT_DATA,This is a duplicate of the contents of the PS register provided here to allow reading of both pin state and interrupt state of the port in a single read operation" "0,1"
rbitfld.long 0x00 23. "PS_DATA7,N/A" "0,1"
newline
rbitfld.long 0x00 22. "PS_DATA6,N/A" "0,1"
rbitfld.long 0x00 21. "PS_DATA5,N/A" "0,1"
newline
rbitfld.long 0x00 20. "PS_DATA4,N/A" "0,1"
rbitfld.long 0x00 19. "PS_DATA3,N/A" "0,1"
newline
rbitfld.long 0x00 18. "PS_DATA2,N/A" "0,1"
rbitfld.long 0x00 17. "PS_DATA1,N/A" "0,1"
newline
rbitfld.long 0x00 16. "PS_DATA0,`" "0,1"
bitfld.long 0x00 8. "FLT_DATA,Deglitched interrupt pending (selected by FLT_SELECT)" "0,1"
newline
bitfld.long 0x00 7. "DATA7,Interrupt pending on IO pad 7" "0,1"
bitfld.long 0x00 6. "DATA6,Interrupt pending on IO pad 6" "0,1"
newline
bitfld.long 0x00 5. "DATA5,Interrupt pending on IO pad 5" "0,1"
bitfld.long 0x00 4. "DATA4,Interrupt pending on IO pad 4" "0,1"
newline
bitfld.long 0x00 3. "DATA3,Interrupt pending on IO pad 3" "0,1"
bitfld.long 0x00 2. "DATA2,Interrupt pending on IO pad 2" "0,1"
newline
bitfld.long 0x00 1. "DATA1,Interrupt pending on IO pad 1" "0,1"
bitfld.long 0x00 0. "DATA0,Interrupt pending on IO pad 0" "0,1"
group.long ($2+0x14)++0x03
line.long 0x00 "SIO,Port SIO configuration register"
bitfld.long 0x00 29.--31. "PAIR_VOH67_SEL,See corresponding definition for IO pads 6 and 7" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 27.--28. "PAIR_VREF67_SEL,See corresponding definition for IO pads 6 and 7" "0,1,2,3"
newline
bitfld.long 0x00 26. "PAIR_VTRIP67_SEL,See corresponding definition for IO pads 6 and 7" "0,1"
bitfld.long 0x00 25. "PAIR_IBUF67_SEL,See corresponding definition for IO pads 6 and 7" "0,1"
newline
bitfld.long 0x00 24. "PAIR_VREG67_EN,See corresponding definition for IO pads 6 and 7" "0,1"
bitfld.long 0x00 21.--23. "PAIR_VOH45_SEL,See corresponding definition for IO pads 4 and 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 19.--20. "PAIR_VREF45_SEL,See corresponding definition for IO pads 4 and 5" "0,1,2,3"
bitfld.long 0x00 18. "PAIR_VTRIP45_SEL,See corresponding definition for IO pads 4 and 5" "0,1"
newline
bitfld.long 0x00 17. "PAIR_IBUF45_SEL,See corresponding definition for IO pads 4 and 5" "0,1"
bitfld.long 0x00 16. "PAIR_VREG45_EN,See corresponding definition for IO pads 4 and 5" "0,1"
newline
bitfld.long 0x00 13.--15. "PAIR_VOH23_SEL,See corresponding definition for IO pads 2 and 3" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 11.--12. "PAIR_VREF23_SEL,See corresponding definition for IO pads 2 and 3" "0,1,2,3"
newline
bitfld.long 0x00 10. "PAIR_VTRIP23_SEL,See corresponding definition for IO pads 2 and 3" "0,1"
bitfld.long 0x00 9. "PAIR_IBUF23_SEL,See corresponding definition for IO pads 2 and 3" "0,1"
newline
bitfld.long 0x00 8. "PAIR_VREG23_EN,See corresponding definition for IO pads 2 and 3" "0,1"
bitfld.long 0x00 5.--7. "PAIR_VOH01_SEL,Selects regulated Voh output level and trip point of input buffer for a specific SIO pin pair" "0: Voh = 1*reference e.g,1: Voh = 1.25*reference e.g,2: Voh = 1.49*reference e.g,3: Voh = 1.67*reference e.g,4: Voh = 2.08*reference e.g,5: Voh = 2.5*reference e.g,6: Voh = 2.78*reference e.g,7: Voh = 4.16*reference e.g"
newline
bitfld.long 0x00 3.--4. "PAIR_VREF01_SEL,Selects reference voltage Vref for trip-point of input buffer" "0: trip-point reference of SRSS internal referece,1: trip-point reference of SRSS internal referece,2: trip-point reference of AMUXBUS_A,3: trip-point reference of AMUXBUS_B Please refer"
bitfld.long 0x00 2. "PAIR_VTRIP01_SEL,Selects trip-point of input buffer" "0: input buffer functions as a CMOS input buffer,1: input buffer functions as a LVTTL input buffer"
newline
bitfld.long 0x00 1. "PAIR_IBUF01_SEL,Selects input buffer mode" "0: singled ended input buffer,1: differential input buffer"
bitfld.long 0x00 0. "PAIR_VREG01_EN,Selects output buffer mode" "0: unregulated output buffer,1: regulated output buffer"
group.long ($2+0x18)++0x03
line.long 0x00 "PC2,Port configuration register 2"
bitfld.long 0x00 7. "INP_DIS7,Disables the input buffer for IO pad 7" "0,1"
bitfld.long 0x00 6. "INP_DIS6,Disables the input buffer for IO pad 6" "0,1"
newline
bitfld.long 0x00 5. "INP_DIS5,Disables the input buffer for IO pad 5" "0,1"
bitfld.long 0x00 4. "INP_DIS4,Disables the input buffer for IO pad 4" "0,1"
newline
bitfld.long 0x00 3. "INP_DIS3,Disables the input buffer for IO pad 3" "0,1"
bitfld.long 0x00 2. "INP_DIS2,Disables the input buffer for IO pad 2" "0,1"
newline
bitfld.long 0x00 1. "INP_DIS1,Disables the input buffer for IO pad 1" "0,1"
bitfld.long 0x00 0. "INP_DIS0,Disables the input buffer for IO pad 0 independent of the port control drive mode (PC.DM)" "0,1"
group.long ($2+0x40)++0x03
line.long 0x00 "DR_SET,Port output data set register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,IO pad i: '0': Output state DR.DATA[i] not affected"
group.long ($2+0x44)++0x03
line.long 0x00 "DR_CLR,Port output data clear register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,IO pad i: '0': Output state DR.DATA[i] not affected"
group.long ($2+0x48)++0x03
line.long 0x00 "DR_INV,Port output data invert register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,IO pad i: '0': Output state DR.DATA[i] not affected"
group.long ($2+0x4C)++0x03
line.long 0x00 "DS,Port drive strength register"
bitfld.long 0x00 17. "PORT_V1P2_IB_MODE_SEL,For GPIOV1P2 cell" "0: vtrip_sel register controls the vtrip_sel of..,1: vddio detect cell output controls the vtrip_sel"
bitfld.long 0x00 16. "PORT_V1P2_VTRIP_SEL,For GPIOV1P2" "0: VDDIO 1.8V and VDDI2C 1.8V All other,1: VDDIO 1.2V and VDDI2C 1.8V 0"
newline
bitfld.long 0x00 14.--15. "DS7,The GPIO drive strength for IO pad 7" "0,1,2,3"
bitfld.long 0x00 12.--13. "DS6,The GPIO drive strength for IO pad 6" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "DS5,The GPIO drive strength for IO pad 5" "0,1,2,3"
bitfld.long 0x00 8.--9. "DS4,The GPIO drive strength for IO pad 4" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "DS3,The GPIO drive strength for IO pad 3" "0,1,2,3"
bitfld.long 0x00 4.--5. "DS2,The GPIO drive strength for IO pad 2" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "DS1,The GPIO drive strength for IO pad 1" "0,1,2,3"
bitfld.long 0x00 0.--1. "DS0,The GPIO drive strength for IO pad 0" "0: Refer to s8iom0s8v1p2 BROS Table11,1: Refer to s8iom0s8v1p2 BROS Table11,2: Refer to s8iom0s8v1p2 BROS Table11,3: Refer to s8iom0s8v1p2 BROS Table11"
group.long ($2+0x50)++0x03
line.long 0x00 "FILT_CONFIG,IO filter config register"
bitfld.long 0x00 23. "FILT7_EN,Filter selection for IO pad 7" "0,1"
bitfld.long 0x00 22. "FILT6_EN,Filter selection for IO pad 6" "0,1"
newline
bitfld.long 0x00 21. "FILT5_EN,Filter selection for IO pad 5" "0,1"
bitfld.long 0x00 20. "FILT4_EN,Filter selection for IO pad 4" "0,1"
newline
bitfld.long 0x00 19. "FILT3_EN,Filter selection for IO pad 3" "0,1"
bitfld.long 0x00 18. "FILT2_EN,Filter selection for IO pad 2" "0,1"
newline
bitfld.long 0x00 17. "FILT1_EN,Filter selection for IO pad 1" "0,1"
bitfld.long 0x00 16. "FILT0_EN,Filter selection for IO pad 0" "0,1"
newline
bitfld.long 0x00 14.--15. "TRIM7,trim bits for 50ns filter on IO pad 7" "0,1,2,3"
bitfld.long 0x00 12.--13. "TRIM6,trim bits for 50ns filter on IO pad 6" "0,1,2,3"
newline
bitfld.long 0x00 10.--11. "TRIM5,trim bits for 50ns filter on IO pad 5" "0,1,2,3"
bitfld.long 0x00 8.--9. "TRIM4,trim bits for 50ns filter on IO pad 4" "0,1,2,3"
newline
bitfld.long 0x00 6.--7. "TRIM3,trim bits for 50ns filter on IO pad 3" "0,1,2,3"
bitfld.long 0x00 4.--5. "TRIM2,trim bits for 50ns filter on IO pad 2" "0,1,2,3"
newline
bitfld.long 0x00 2.--3. "TRIM1,trim bits for 50ns filter on IO pad 1" "0,1,2,3"
bitfld.long 0x00 0.--1. "TRIM0,trim bits for 50ns filter on IO pad 0" "0,1,2,3"
group.long ($2+0x80)++0x03
line.long 0x00 "VREFGEN,Reference generator configuration register"
bitfld.long 0x00 8. "VREFGEN_EN,Reference generator enable: '0': Disabled" "0,1"
bitfld.long 0x00 0.--4. "REF_SEL,Reference selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
endif
tree.end
repeat.end
tree.end
tree "HSIOM (High Speed IO Matrix (HSIOM))"
base ad:0x40020000
sif cpuis("psoc4100smax")
group.long 0x2000++0x03
line.long 0x00 "PUMP_CTL,Pump control"
bitfld.long 0x00 31. "ENABLED,Pump enabled: '0': Disabled" "0,1"
bitfld.long 0x00 0. "CLOCK_SEL,Clock select: '0': External clock" "0,1"
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x2100)++0x03
line.long 0x00 "AMUX_SPLIT_CTL[$1],AMUX splitter cell control $1"
bitfld.long 0x00 6. "SWITCH_BB_S0,T-switch control for AMUXBUSB vssa/ground switch" "0,1"
bitfld.long 0x00 5. "SWITCH_BB_SR,T-switch control for Right AMUXBUSB switch" "0,1"
newline
bitfld.long 0x00 4. "SWITCH_BB_SL,T-switch control for Left AMUXBUSB switch" "0,1"
bitfld.long 0x00 2. "SWITCH_AA_S0,T-switch control for AMUXBUSA vssa/ground switch: '0': switch open" "0,1"
newline
bitfld.long 0x00 1. "SWITCH_AA_SR,T-switch control for Right AMUXBUSA switch: '0': switch open" "0,1"
bitfld.long 0x00 0. "SWITCH_AA_SL,T-switch control for Left AMUXBUSA switch: '0': switch open" "0,1"
repeat.end
endif
repeat 13. (increment 0 1)(increment 0 0x100)
tree "PRT[$1]"
sif cpuis("psoc4100smax")
group.long ($2+0x00)++0x03
line.long 0x00 "PORT_SEL,Port selection register"
bitfld.long 0x00 28.--31. "IO7_SEL,Selects connection for IO pad 7 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "IO6_SEL,Selects connection for IO pad 6 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "IO5_SEL,Selects connection for IO pad 5 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "IO4_SEL,Selects connection for IO pad 4 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "IO3_SEL,Selects connection for IO pad 3 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "IO2_SEL,Selects connection for IO pad 2 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "IO1_SEL,Selects connection for IO pad 1 route" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "IO0_SEL,Selects connection for IO pad 0 route" "0: SW controlled GPIO,1: SW controlled 'out' DSI controlled 'oe_n',2: DSI controlled 'out' and 'oe_n',3: DSI controlled 'out' SW controlled 'oe_n',4: CSD sense connection (analog mode),5: CSD shield connection (analog mode),6: AMUXBUS A connection,7: AMUXBUS B connection,8: Chip specific Active source 0 connection,9: Chip specific Active source 1 connection,10: Chip specific Active source 2 connection,11: Chip specific Active source 3 connection,12: LCD common connection,13: LCD segment connection,14: Chip specific DeepSleep source 2 connection,15: Chip specific DeepSleep source 3 connection"
endif
tree.end
repeat.end
tree.end
sif cpuis("CY8C4149*")
tree "I2S0 (I2S registers)"
base ad:0x404F0000
group.long 0x00++0x03
line.long 0x00 "CTL,Control"
bitfld.long 0x00 31. "RX_ENABLED,Enables the I2S RX component: '0': Disabled" "0,1"
bitfld.long 0x00 30. "TX_ENABLED,Enables the I2S TX component: '0': Disabled" "0,1"
group.long 0x10++0x03
line.long 0x00 "CLOCK_CTL,Clock control"
bitfld.long 0x00 8. "CLOCK_SEL,Selects clock to be used by I2S: '0': Internal clock ('clk_audio_i2s') '1': External clock ('clk_i2s_if')" "0,1"
bitfld.long 0x00 0.--5. "CLOCK_DIV,Frequency divisor for generating I2S clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x20++0x03
line.long 0x00 "CMD,Command"
bitfld.long 0x00 16. "RX_START,Receiver enable: '0': Disabled" "0,1"
bitfld.long 0x00 8. "TX_PAUSE,Pause enable: '0': Disabled (TX FIFO data is sent over I2S)" "0,1"
newline
bitfld.long 0x00 0. "TX_START,Transmitter enable: '0': Disabled" "0,1"
group.long 0x40++0x03
line.long 0x00 "TR_CTL,Trigger control"
bitfld.long 0x00 16. "RX_REQ_EN,Trigger output ('tr_i2s_rx_req') enable for requests of DMA transfer in reception '0': Disabled" "0,1"
bitfld.long 0x00 0. "TX_REQ_EN,Trigger output ('tr_i2s_tx_req') enable for requests of DMA transfer in transmission '0': Disabled" "0,1"
group.long 0x80++0x03
line.long 0x00 "TX_CTL,Transmitter control"
bitfld.long 0x00 25. "SCKI_POL,TX slave bit clock polarity" "0,1"
bitfld.long 0x00 24. "SCKO_POL,TX master bit clock polarity" "0,1"
newline
bitfld.long 0x00 20.--22. "WORD_LEN,Word length in number of bits: Note: - When this field is configured to '6' or '7' the length is set to 32-bit (same as '5')" "0: BIT_LEN8,1: BIT_LEN16,2: BIT_LEN18,3: BIT_LEN20,4: BIT_LEN24,5: BIT_LEN32,?..."
bitfld.long 0x00 16.--18. "CH_LEN,Channel length in number of bits: Note: - When this field is configured to '6' or '7' the length is set to 32-bit (same as '5')" "0: BIT_LEN8,1: BIT_LEN16,2: BIT_LEN18,3: BIT_LEN20,4: BIT_LEN24,5: BIT_LEN32,?..."
newline
bitfld.long 0x00 13. "WD_EN,Set watchdog for 'tx_ws_in': '0': Disabled" "0,1"
bitfld.long 0x00 12. "OVHDATA,Set overhead value: '0': Set to '0' '1': Set to '1' (Note: This bit is connected to AR38U12.TX_CFG.TX_OVHDATA)" "0,1"
newline
bitfld.long 0x00 10. "WS_PULSE,Set WS pulse width in TDM mode: (Note: This bit is connected to AR38U12.TX_CFG.TX_WS_PULSE) Note: When not TDM mode must be '1'" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
bitfld.long 0x00 8.--9. "I2S_MODE,Select I2S left-justified or TDM: (Note: These bits are connected to AR38U12.TX_CFG.TX_I2S_MODE)" "0: LEFT_JUSTIFIED,1: I2S mode,2: TDM mode A the 1st Channel align to WSO..,3: TDM mode B the 1st Channel align to WSO.."
newline
bitfld.long 0x00 7. "MS,Set interface in master or slave mode: (Note: This bit is connected to AR38U12.TX_CFG.TX_MS)" "0: SLAVE,1: MASTER"
bitfld.long 0x00 4.--6. "CH_NR,Specifies number of channels per frame: Note: only '2channels' is supported during Left Justfied or I2S mode" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
newline
bitfld.long 0x00 3. "B_CLOCK_INV,Serial data transmission is advanced by 0.5 SCK cycles" "0: SDO transmitted at SCK falling edge when..,1: SDO transmitted at SCK rising edge when.."
group.long 0x84++0x03
line.long 0x00 "TX_WATCHDOG,Transmitter watchdog"
hexmask.long 0x00 0.--31. 1. "WD_COUNTER,Start value of the TX watchdog"
group.long 0xA0++0x03
line.long 0x00 "RX_CTL,Receiver control"
bitfld.long 0x00 25. "SCKI_POL,RX slave bit clock polarity" "0,1"
bitfld.long 0x00 24. "SCKO_POL,RX master bit clock polarity" "0,1"
newline
bitfld.long 0x00 23. "BIT_EXTENSION,When reception word length is shorter than the word length of RX_FIFO_RD extension mode of upper bit should be set" "0,1"
bitfld.long 0x00 20.--22. "WORD_LEN,Word length in number of bits: Note: - When this field is configured to '6' or '7' the length is set to 32-bit (same as '5')" "0: BIT_LEN8,1: BIT_LEN16,2: BIT_LEN18,3: BIT_LEN20,4: BIT_LEN24,5: BIT_LEN32,?..."
newline
bitfld.long 0x00 16.--18. "CH_LEN,Channel length in number of bits: Note: - When this field is configured to '6' or '7' the length is set to 32-bit (same as '5')" "0: BIT_LEN8,1: BIT_LEN16,2: BIT_LEN18,3: BIT_LEN20,4: BIT_LEN24,5: BIT_LEN32,?..."
bitfld.long 0x00 13. "WD_EN,Set watchdog for 'rx_ws_in' '0': Disabled" "0,1"
newline
bitfld.long 0x00 10. "WS_PULSE,Set WS pulse width in TDM mode: (Note: This bit is connected to AR38U12.RX_CFG.RX_WS_PULSE) Note: When not TDM mode must be '1'" "0: Pulse width is 1 SCK period,1: Pulse width is 1 channel length"
bitfld.long 0x00 8.--9. "I2S_MODE,Select I2S left-justified or TDM: (Note: These bits are connected to AR38U12.RX_CFG.RX_I2S_MODE)" "0: LEFT_JUSTIFIED,1: I2S mode,2: TDM mode A the 1st Channel align to WSO..,3: TDM mode B the 1st Channel align to WSO.."
newline
bitfld.long 0x00 7. "MS,Set interface in master or slave mode: (Note: This bit is connected to AR38U12.TX_CFG.RX_MS)" "0: SLAVE,1: MASTER"
bitfld.long 0x00 4.--6. "CH_NR,Specifies number of channels per frame: Note: only '2channels' is supported during Left Justfied or I2S mode" "0: 1 channel,1: 2 channels,2: 3 channels,3: 4 channels,4: 5 channels,5: 6 channels,6: 7 channels,7: 8 channels"
newline
bitfld.long 0x00 3. "B_CLOCK_INV,Serial data capture is delayed by 0.5 SCK cycles" "0: SDI received at SCK rising edge when..,1: SDI received at SCK falling edge when.."
group.long 0xA4++0x03
line.long 0x00 "RX_WATCHDOG,Receiver watchdog"
hexmask.long 0x00 0.--31. 1. "WD_COUNTER,Start value of the RX watchdog"
group.long 0x200++0x03
line.long 0x00 "TX_FIFO_CTL,TX FIFO control"
bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the TX FIFO do not remove FIFO entries" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the TX FIFO and TX_BUF are cleared/invalidated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
rgroup.long 0x204++0x03
line.long 0x00 "TX_FIFO_STATUS,TX FIFO status"
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,TX FIFO write pointer: FIFO location at which a new data frame is written by the host"
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,TX FIFO read pointer: FIFO location from which a data frame is read by the hardware.This field is used only for debugging purposes"
newline
hexmask.long.word 0x00 0.--8. 1. "USED,Number of entries in the TX FIFO"
wgroup.long 0x208++0x03
line.long 0x00 "TX_FIFO_WR,TX FIFO"
hexmask.long 0x00 0.--31. 1. "DATA,Data written into the TX FIFO"
group.long 0x300++0x03
line.long 0x00 "RX_FIFO_CTL,RX FIFO control"
bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the RX FIFO have no effect" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the RX FIFO and RX_BUF are cleared/invalidated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
rgroup.long 0x304++0x03
line.long 0x00 "RX_FIFO_STATUS,RX FIFO status"
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,RX FIFO write pointer: FIFO location at which a new data frame is written by the hardware"
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,RX FIFO read pointer: FIFO location from which a data frame is read by the host"
newline
hexmask.long.word 0x00 0.--8. 1. "USED,Number of entries in the RX FIFO"
rgroup.long 0x308++0x03
line.long 0x00 "RX_FIFO_RD,RX FIFO"
hexmask.long 0x00 0.--31. 1. "DATA,Data read from the RX FIFO"
rgroup.long 0x30C++0x03
line.long 0x00 "RX_FIFO_RD_SILENT,RX FIFO silent"
hexmask.long 0x00 0.--31. 1. "DATA,Data read from the RX FIFO"
group.long 0xF00++0x03
line.long 0x00 "INTR,Interrupt register"
bitfld.long 0x00 24. "RX_WD,Triggers (sets to '1') when the Rx watchdog event occurs" "0,1"
bitfld.long 0x00 22. "RX_UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1"
newline
bitfld.long 0x00 21. "RX_OVERFLOW,Attempt to write to a full RX FIFO" "0,1"
bitfld.long 0x00 19. "RX_FULL,RX FIFO is full" "0,1"
newline
bitfld.long 0x00 18. "RX_NOT_EMPTY,RX FIFO is not empty" "0,1"
bitfld.long 0x00 16. "RX_TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in RX_FIFO_CTRL" "0,1"
newline
bitfld.long 0x00 8. "TX_WD,Triggers (sets to '1') when the Tx watchdog event occurs" "0,1"
bitfld.long 0x00 6. "TX_UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1"
newline
bitfld.long 0x00 5. "TX_OVERFLOW,Attempt to write to a full TX FIFO" "0,1"
bitfld.long 0x00 4. "TX_EMPTY,TX FIFO is empty i.e" "0,1"
newline
bitfld.long 0x00 1. "TX_NOT_FULL,TX FIFO is not full" "0,1"
bitfld.long 0x00 0. "TX_TRIGGER,Less entries in the TX FIFO than the value specified by TRIGGER_LEVEL in TX_FIFO_CTRL" "0,1"
group.long 0xF04++0x03
line.long 0x00 "INTR_SET,Interrupt set register"
bitfld.long 0x00 24. "RX_WD,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 22. "RX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 21. "RX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 19. "RX_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 18. "RX_NOT_EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 16. "RX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "TX_WD,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "TX_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "TX_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "TX_EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "TX_NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TX_TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xF08++0x03
line.long 0x00 "INTR_MASK,Interrupt mask register"
bitfld.long 0x00 24. "RX_WD,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 22. "RX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 21. "RX_OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 19. "RX_FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 18. "RX_NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 16. "RX_TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "TX_WD,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "TX_UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "TX_OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "TX_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "TX_NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TX_TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0xF0C++0x03
line.long 0x00 "INTR_MASKED,Interrupt masked register"
bitfld.long 0x00 24. "RX_WD,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 22. "RX_UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 21. "RX_OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 19. "RX_FULL,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 18. "RX_NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 16. "RX_TRIGGER,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 8. "TX_WD,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 6. "TX_UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 5. "TX_OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 4. "TX_EMPTY,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "TX_NOT_FULL,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "TX_TRIGGER,Logical and of corresponding request and mask bits" "0,1"
tree.end
endif
tree "LCD (LCD Controller Block)"
sif cpuis("CY8C4146P*")||cpuis("CY8C4146L*")
base ad:0x400B0000
elif cpuis("CY8C4147*")||cpuis("CY8C4146A*")||cpuis("CY8C4148*")
base ad:0x402A0000
elif cpuis("CY8C4149*")
base ad:0x40210000
endif
rgroup.long 0x00++0x03
line.long 0x00 "ID,ID & Revision"
hexmask.long.word 0x00 16.--31. 1. "REVISION,the version number is 0x0001"
hexmask.long.word 0x00 0.--15. 1. "ID,the ID of LCD controller peripheral is 0xF0F0"
group.long 0x04++0x03
line.long 0x00 "DIVIDER,LCD Divider Register"
hexmask.long.word 0x00 16.--31. 1. "DEAD_DIV,Length of the dead time period in cycles"
hexmask.long.word 0x00 0.--15. 1. "SUBFR_DIV,Input clock frequency divide value to generate the 1/4 sub-frame period"
group.long 0x08++0x03
line.long 0x00 "CONTROL,LCD Configuration Register"
rbitfld.long 0x00 31. "LS_EN_STAT,LS enable status bit" "0,1"
bitfld.long 0x00 8.--11. "COM_NUM,The number of COM connections minus 2" "0: 2 COM's,1: 3 COM's,?,?,?,?,?,?,?,?,?,?,?,13: 15 COM's,14: 16 COM's,15: undefined"
newline
bitfld.long 0x00 5.--6. "BIAS,PWM bias selection" "0: 1/2 Bias,1: 1/3 Bias,2: 1/4 Bias (not supported by LS generator),3: 1/5 Bias (not supported by LS generator)"
bitfld.long 0x00 4. "OP_MODE,Driving mode configuration" "0: PWM Mode,1: Digital Correlation Mode"
newline
bitfld.long 0x00 3. "TYPE,LCD driving waveform type configuration" "0: Type A - Each frame addresses each COM pin..,1: Type B - Each frame addresses each COM pin.."
bitfld.long 0x00 2. "LCD_MODE,HS/LS Mode selection" "0: Select Low Speed (32kHz) Generator (Works in..,1: Select High Speed (system clock) Generator.."
newline
bitfld.long 0x00 1. "HS_EN,High speed (HS) generator enable" "0: disable,1: enable"
bitfld.long 0x00 0. "LS_EN,Low speed (LS) generator enable" "0: disable,1: enable"
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "DATA[$1],LCD Pin Data Registers $1"
hexmask.long 0x00 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 1-4 (COM1 is lsb)"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "DATA[$1],LCD Pin Data Registers $1"
hexmask.long 0x00 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 5-8 (COM5 is lsb)"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x300)++0x03
line.long 0x00 "DATA[$1],LCD Pin Data Registers $1"
hexmask.long 0x00 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 9-12 (COM9 is lsb)"
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x400)++0x03
line.long 0x00 "DATA[$1],LCD Pin Data Registers $1"
hexmask.long 0x00 0.--31. 1. "DATA,Bits [4i+3:4i] represent the pin data for pin [i] for COMS 13-16 (COM13 is lsb)"
repeat.end
tree.end
tree "LPCOMP (Low-power Comparator)"
sif cpuis("CY8C4146P*")||cpuis("CY8C4146L*")
base ad:0x400D0000
elif cpuis("CY8C4149*")||cpuis("CY8C4147*")||cpuis("CY8C4146A*")||cpuis("CY8C4148*")
base ad:0x402B0000
endif
rgroup.long 0x00++0x03
line.long 0x00 "ID,ID & Revision"
hexmask.long.word 0x00 16.--31. 1. "REVISION,the version number is 0x0001"
hexmask.long.word 0x00 0.--15. 1. "ID,the ID of LPCOMP peripheral is 0xE0E0"
group.long 0x04++0x03
line.long 0x00 "CONFIG,LPCOMP Configuration Register"
bitfld.long 0x00 21. "DSI_LEVEL2,Opamp2 comparator DSI (trigger) out level" "0: pulse,1: level"
bitfld.long 0x00 20. "DSI_BYPASS2,Opamp2 bypass comparator output synchronization for DSI output" "0: synchronize (level or pulse),1: bypass (output async) Note that in DeepSleep"
newline
bitfld.long 0x00 17. "DSI_LEVEL1,Opamp1 comparator DSI (trigger) out level" "0: pulse,1: level"
bitfld.long 0x00 16. "DSI_BYPASS1,Opamp1 bypass comparator output synchronization for DSI output" "0: synchronize (level or pulse),1: bypass (output async) Note that in DeepSleep"
newline
bitfld.long 0x00 15. "ENABLE2,Enable comparator #2" "0,1"
rbitfld.long 0x00 14. "OUT2,Current output value of the comparator" "0,1"
newline
bitfld.long 0x00 12.--13. "INTTYPE2,Sets which edge will trigger an IRQ" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
bitfld.long 0x00 11. "FILTER2,N/A" "0,1"
newline
bitfld.long 0x00 10. "HYST2,Add 10mV hysteresis to the comparator" "0: Enable Hysteresis,1: Disable Hysteresis"
bitfld.long 0x00 8.--9. "MODE2,Operating mode for the comparator" "0: Slow operating mode (uses less power <50uA),1: Fast operating mode (uses more power <400uA),2: Ultra low power operting mode (uses ~2-4uA),?..."
newline
bitfld.long 0x00 7. "ENABLE1,Enable comparator #1" "0,1"
rbitfld.long 0x00 6. "OUT1,Current output value of the comparator" "0,1"
newline
bitfld.long 0x00 4.--5. "INTTYPE1,Sets which edge will trigger an IRQ" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
bitfld.long 0x00 3. "FILTER1,N/A" "0,1"
newline
bitfld.long 0x00 2. "HYST1,Add 10mV hysteresis to the comparator" "0: Enable Hysteresis,1: Disable Hysteresis"
bitfld.long 0x00 0.--1. "MODE1,Operating mode for the comparator" "0: Slow operating mode (uses less power <50uA),1: Fast operating mode (uses more power <400uA),2: Ultra low power operting mode (uses ~2-4uA),?..."
group.long 0x10++0x03
line.long 0x00 "INTR,LPCOMP Interrupt request register"
bitfld.long 0x00 1. "COMP2,Comparator 2 Interrupt: hardware sets this interrupt when comparator 0 triggers" "0,1"
bitfld.long 0x00 0. "COMP1,Comparator 1 Interrupt: hardware sets this interrupt when comparator 0 triggers" "0,1"
group.long 0x14++0x03
line.long 0x00 "INTR_SET,LPCOMP Interrupt set register"
bitfld.long 0x00 1. "COMP2,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "COMP1,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0x18++0x03
line.long 0x00 "INTR_MASK,LPCOMP Interrupt request mask"
bitfld.long 0x00 1. "COMP2_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "COMP1_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0x1C++0x03
line.long 0x00 "INTR_MASKED,LPCOMP Interrupt request masked"
bitfld.long 0x00 1. "COMP2_MASKED,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "COMP1_MASKED,Logical and of corresponding request and mask bits" "0,1"
group.long 0xFF00++0x03
line.long 0x00 "TRIM1,LPCOMP Trim Register"
bitfld.long 0x00 0.--4. "COMP1_TRIMA,Trim A for Comparator #1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xFF04++0x03
line.long 0x00 "TRIM2,LPCOMP Trim Register"
bitfld.long 0x00 0.--4. "COMP1_TRIMB,Trim B for Comparator #1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xFF08++0x03
line.long 0x00 "TRIM3,LPCOMP Trim Register"
bitfld.long 0x00 0.--4. "COMP2_TRIMA,Trim A for Comparator #2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0xFF0C++0x03
line.long 0x00 "TRIM4,LPCOMP Trim Register"
bitfld.long 0x00 0.--4. "COMP2_TRIMB,Trim B for Comparator #2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
sif cpuis("CY8C4148*")
tree "MCA (Motor Control Accellerator)"
repeat 2. (list 0. 1.) (list ad:0x402C0000 ad:0x402C1000)
tree "MCA$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CONFIG,IP Configuration Register"
bitfld.long 0x00 31. "ENABLED,Enable IP" "0,1"
bitfld.long 0x00 0. "BLOCK,Specify whether a SW read access of DIV_QUOTIENT DIV_REMAINDER or SQRT_ROOT should block and result in bus wait states while operation is ongoing" "0: Read access returns immediately,1: Introduce wait state if read access is issued"
group.long 0x04++0x03
line.long 0x00 "CTL,IP Control Register"
bitfld.long 0x00 6. "HOLD_SQRT,Hold Square Root operation.- Pauses the calculation process" "0,1"
bitfld.long 0x00 5. "START_SQRT_PULSE,START_SQRT_PULSE: Start Divisor operation - a 1 clock pulse is sent to the SQR.START input" "0: No Opereration,1: Create 1 clock pulse to SQR.START"
newline
bitfld.long 0x00 4. "START_SQRT_LEVEL,Start Square Root operation Level - Use to continuously enable Square Root operations" "0: SQR.START is disabled,1: SQR.START is asserted continuously"
bitfld.long 0x00 2. "HOLD_DIVIDE,Hold Divide operation.- Pauses the calculation process" "0,1"
newline
bitfld.long 0x00 1. "START_DIVIDE_PULSE,START_DIVIDE_PULSE: Start Divisor operation - a 1 clock pulse is sent to the DIVIDE.START input" "0: No Opereration,1: Create 1 clock pulse to DIVIDE.START"
bitfld.long 0x00 0. "START_DIVIDE_LEVEL,Start Divide operation Level - Use to continuously enable Divide operations" "0: DIVDE.START is disabled,1: DIVIDE.START is asserted continuously"
rgroup.long 0x08++0x03
line.long 0x00 "STAT,IP Status Register"
bitfld.long 0x00 4. "SQRT_COMPLETE,Square Root Operation Complete - This bit is a reflection of the calculation time after SQRT.START de-asserts" "0: Square Root operation is ongoing,1: Square Root operation completes and ready for"
bitfld.long 0x00 1. "DIVIDE_BY_0,DIV_DIVSOR equals 0" "0,1"
newline
bitfld.long 0x00 0. "DIVIDE_COMPLETE,Divide Operation Complete - This bit is a reflection of the calculation time after DIVIDE.START de-asserts" "0: Divide operation is ongoing,1: Divide operation completes and ready for next"
group.long 0x10++0x03
line.long 0x00 "DIV_DIVIDEND,32 bit Dividend"
hexmask.long 0x00 0.--31. 1. "DIVIDEND,Dividend"
group.long 0x14++0x03
line.long 0x00 "DIV_DIVISOR,32 bit Divisor"
hexmask.long 0x00 0.--31. 1. "DIVISOR,Divisor - should not be set to 0 or STAT.DIVIDE_BY_0 will set"
rgroup.long 0x18++0x03
line.long 0x00 "DIV_QUOTIENT,32 bit Quotient"
hexmask.long 0x00 0.--31. 1. "QUOTIENT,Quotient"
rgroup.long 0x1C++0x03
line.long 0x00 "DIV_REMAINDER,32 bit Remainder"
hexmask.long 0x00 0.--31. 1. "REMAINDER,Remainder"
group.long 0x20++0x03
line.long 0x00 "SQRT_RADICAND,Square Root Source Value"
hexmask.long 0x00 0.--31. 1. "RADICAND,If CTL.START_SQRT_LEVEL is used then the square root operation starts once SW writes this register"
rgroup.long 0x24++0x03
line.long 0x00 "SQRT_ROOT,Square Root Result"
hexmask.long.word 0x00 0.--15. 1. "ROOT,The result will keep unchanged until next square root operation starts"
tree.end
repeat.end
tree.end
endif
sif cpuis("CY8C4149*")
tree "MSC (MultiSense Controller)"
repeat 2. (list 0. 1.) (list ad:0x40290000 ad:0x402A0000)
tree "MSC$1"
base $2
group.long 0x00++0x03
line.long 0x00 "CTL,Configuration and Control"
bitfld.long 0x00 31. "ENABLED,Master enable of the MSCv3 IP" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 24. "CLK_MSC_RATIO,Control bit for digital clock divider logic that creates clk_msc from clk_hf" "0: DIVIDED,1: PASSTHROUGH"
newline
bitfld.long 0x00 20. "BUF_MODE,Shield buffer operating mode select" "0: HIGH_BW_MODE,1: SHIELD_MODE"
bitfld.long 0x00 16.--17. "OPERATING_MODE,Sequencer FSM Operating Mode '0': CPU Mode" "0: Frame scan configurations are stored in..,1: Frame scan configurations are stored in..,2: Frame scan configurations are stored in IP RAM,3: Frame scan configurations are stored in IP RAM"
newline
bitfld.long 0x00 12. "EXT_FRAME_START_EN,Control bit to enable external frame start of Sequencer FSM via GPIO" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 8. "CLK_SYNC_EN,Control bit to create external channel sync clock" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 4. "MSCCMP_EN,MSC Comparator Enable" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 0. "SENSE_EN,Enables the sense modulator output" "0: DISABLED,1: ENABLED"
group.long 0x04++0x03
line.long 0x00 "SPARE,Spare MMIO"
bitfld.long 0x00 0.--5. "SPARE,Spare MMIO (Hard IP)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "SCAN_CTL1,Scan Control 1"
hexmask.long.byte 0x00 16.--23. 1. "FRAME_START_PTR,Pointer to first sensor configuration of a frame"
bitfld.long 0x00 12.--14. "DEBUG_CONV_PH_SEL,Debug counter conversion chop phase select for DEBUG_CONV_COUNT" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "RAW_COUNT_MODE,Control bit to handle behaviour when RAW_COUNT exceeds 0xFFFF" "0: SATURATE,1: OVERFLOW"
bitfld.long 0x00 4.--5. "NUM_SAMPLES,Number of samples (minus 1) to be scanned" "0,1,2,3"
newline
bitfld.long 0x00 3. "RESCAN_DEBUG_MODE,If this bit is set all results (good and bad) generated by NUM_AUTO_RESAMPLE are stored" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 0.--2. "NUM_AUTO_RESAMPLE,If Sequencer detects a bad conversion and NUM_AUTO_RESAMPLE != 0 it will not store the bad result" "0,1,2,3,4,5,6,7"
group.long 0x0C++0x03
line.long 0x00 "SCAN_CTL2,Scan Control 2"
bitfld.long 0x00 24. "CHOP_EVEN_HOLD_EN,Use this bit to hold the chop value at the end of every even chop phase of NUM_CONV" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 16. "CHOP_POL,Polarity of first chop phase" "0,1"
newline
hexmask.long.word 0x00 0.--9. 1. "NUM_EPI_CYCLES,Number of clk_mod cycles to be run during EPILOGUE"
group.long 0x10++0x03
line.long 0x00 "INIT_CTL1,Initialisation Control 1"
bitfld.long 0x00 28. "PER_SAMPLE,Decides if coarse initialisation is done per sample when NUM_SAMPLES > 0 (i.e. more than one sample per scan)" "0: DISABLED,1: ENABLED"
hexmask.long.word 0x00 16.--27. 1. "NUM_INIT_CMOD_12_SHORT_CYCLES,Duration of the coarse short phase (shorting Cmod1 and Cmod2 in full-wave mode)"
newline
hexmask.long.word 0x00 0.--11. 1. "NUM_INIT_CMOD_12_RAIL_CYCLES,Duration of the coarse initialisation phase (e.g. connecting Cmod1 to vdda and Cmod2 to vssa in full-wave mode)"
group.long 0x14++0x03
line.long 0x00 "INIT_CTL2,Initialisation Control 2"
hexmask.long.word 0x00 16.--27. 1. "NUM_INIT_CMOD_34_SHORT_CYCLES,Duration of the coarse short phase (shorting Cmod3 and Cmod4 in full-wave mode)"
hexmask.long.word 0x00 0.--11. 1. "NUM_INIT_CMOD_34_RAIL_CYCLES,Duration of the coarse initialisation phase (e.g. connecting Cmod3 to vdda and Cmod4 to vssa in full-wave mode)"
group.long 0x18++0x03
line.long 0x00 "INIT_CTL3,Initialisation Control 3"
bitfld.long 0x00 15. "INIT_MODE,Determines autonomous initialisation behaviour during INIT_CMOD" "0: Used for full and half wave when Vdda is..,1: Used for half-wave when Vref is reference"
bitfld.long 0x00 10.--11. "CMOD_SEL,Select which Cmod are used and the cycle thresholds to be used for coarse initialisation" "0: Used for full-wave,1: Used for full-wave,2: Used for half-wave,3: Used for half-wave"
newline
bitfld.long 0x00 8.--9. "NUM_PRO_OFFSET_TRIPS,Number of comparator trips required to be observed in PRO_OFFSET before proceeding to dummy cycles" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "NUM_PRO_OFFSET_CYCLES,Maximum number of clk_mod cycles to be assigned for the PRO_OFFSET state"
group.long 0x1C++0x03
line.long 0x00 "INIT_CTL4,Initialisation Control 4"
hexmask.long.word 0x00 16.--25. 1. "NUM_PRO_WAIT_CYCLES,Number of clk_mod cycles to be run during PRO_WAIT"
hexmask.long.byte 0x00 0.--7. 1. "NUM_PRO_DUMMY_SUB_CONVS,Number of sub-conversions (dummy cycles) to be run during PRO_DUMMY"
group.long 0x20++0x03
line.long 0x00 "SENSE_DUTY_CTL,Sense Clock Duty Cycle Control"
bitfld.long 0x00 27. "PHASE_WIDTH_SEL,Select which phases the PHASE_WIDTH applies to: '0': PHASE_WIDTH corresponds to width of ph0 and ph2" "0: PH0_AND_PH2,1: PH1_AND_PH3"
hexmask.long.word 0x00 16.--25. 1. "PHASE_SHIFT_CYCLES,Phase shift cycle control for ph0X and ph1X"
newline
hexmask.long.word 0x00 0.--11. 1. "PHASE_WIDTH,Control width (clk_mod cycles) of ph0 and ph2 OR ph1 and ph3"
group.long 0x24++0x03
line.long 0x00 "SENSE_PERIOD_CTL,Sense Clock Period Control"
bitfld.long 0x00 16.--19. "LFSR_SCALE,Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "LFSR_POLY,Programmable polynomial to be used for the sense LFSR"
group.long 0x28++0x03
line.long 0x00 "FILTER_CTL,Filter Control"
bitfld.long 0x00 24. "FILTER_MODE,N/A" "0: Use the standard first order counter low pass..,1: Use CIC2 Filter"
bitfld.long 0x00 16. "BIT_FORMAT,Determines how the synchronised comparator output is interpreted by the filter pipeline" "0: Input values [0 +1],1: Input values [-1 +1]"
group.long 0x30++0x03
line.long 0x00 "CCOMP_CDAC_CTL,Compensation CAPDAC Control"
bitfld.long 0x00 31. "EPILOGUE_EN,Control on whether Ccomp is active during EPILOGUE for final balancing in a conversion" "0: DISABLED,1: ENABLED"
hexmask.long.byte 0x00 8.--15. 1. "SEL_CO_PRO_OFFSET,Select value for Compensation CAPDAC size during PRO_OFFSET until the first comparator trip is observed"
group.long 0x34++0x03
line.long 0x00 "DITHER_CDAC_CTL,Flatspot/Dither CAPDAC Switch Control"
hexmask.long.byte 0x00 16.--23. 1. "LFSR_POLY_FL,Dither/Flatspot CAPDAC LFSR polynomial"
hexmask.long.byte 0x00 0.--7. 1. "SEL_FL,Select value for Dither/Flatspot CAPDAC size"
group.long 0x40++0x03
line.long 0x00 "CSW_CTL,Control Mux Switch Control"
abitfld.long 0x00 0.--31. "CSW_FUNC_MODE,Select between SW_SEL_CSW[x] and SW_SEL_CSW_FUNC" "0x00000000=0: Use SW_CSW_CTL for control MUX x,0x00000001=1: Use SW_SEL_CSW_FUNC[y] for control.."
group.long 0x44++0x03
line.long 0x00 "SW_SEL_GPIO,GPIO Switch Control"
bitfld.long 0x00 24.--26. "SW_DSI_CSH_TANK,MUX select for dsi_csh_tank waveform" "0: LOGIC_0,1: LOGIC_1,2: chop == 1 ? ph0,3: chop == 1 ? ph1,4: PH1,?..."
bitfld.long 0x00 20.--22. "SW_DSI_CMOD,MUX select for dsi_cmod waveform" "0: LOGIC_0,1: LOGIC_1,2: chop == 1 ? ph1,3: chop == 1 ? ph3,4: PH0,?..."
newline
bitfld.long 0x00 16. "SW_CSD_CHARGE,MUX select for csd_charge waveform" "0: LOGIC_0,1: LOGIC_1"
bitfld.long 0x00 12.--13. "SW_CSD_POLARITY,MUX select for csd_polarity waveform" "0: LOGIC_0,1: LOGIC_1,2: PH0_OR_PH1,?..."
newline
bitfld.long 0x00 8. "SW_CSD_MUTUAL,MUX select for csd_mutual waveform" "0: LOGIC_0,1: LOGIC_1"
bitfld.long 0x00 4.--6. "SW_CSD_SHIELD,MUX select for csd_shield waveform" "0: LOGIC_0,1: LOGIC_1,2: PH0,3: PH1,4: PH0_OR_PH3,5: ph0 || [Fs2_ph1 && (ph1 || ph3)],6: PH1X,?..."
newline
bitfld.long 0x00 0.--2. "SW_CSD_SENSE,MUX select for csd_sense waveform" "0: LOGIC_0,1: LOGIC_1,2: PH0,3: PH1,4: PH0_OR_PH3,5: PH0X,6: PH1X,?..."
group.long 0x48++0x03
line.long 0x00 "SW_SEL_CDAC_RE,Reference CAPDAC Switch Control"
bitfld.long 0x00 20.--21. "SW_REBG,Reference CAPDAC bottom plate to vssa_q Switch" "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb)"
bitfld.long 0x00 16.--17. "SW_REBV,Reference CAPDAC bottom plate to vdda_q Switch" "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb)"
newline
bitfld.long 0x00 12.--14. "SW_RETG,Reference CAPDAC top plate to vssa_q Switch" "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode,5: DFT mode,?..."
bitfld.long 0x00 8.--10. "SW_RETV,Reference CAPDAC top plate to vdda_q Switch" "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode,5: DFT mode,?..."
newline
bitfld.long 0x00 4.--6. "SW_RECB,Reference CAPDAC to CSD Bus B Switch" "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_reffb),3: chop == 1 ? sel = 10 (clk_reffb),4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?..."
bitfld.long 0x00 0.--2. "SW_RETCA,Reference CAPDAC top plate to CSD Bus A Switch" "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_reffb),3: chop == 1 ? sel = 10 (clk_reffb),4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?..."
group.long 0x4C++0x03
line.long 0x00 "SW_SEL_CDAC_CO,Compensation CAPDAC Switch Control"
bitfld.long 0x00 20.--21. "SW_COBG,Compensation CAPDAC bottom plate to vssa_q Switch" "0: sel = 00,1: sel = 01,2: sel = 10 (clk_comp),3: sel = 11 (!clk_comp)"
bitfld.long 0x00 16.--17. "SW_COBV,Compensation CAPDAC bottom plate to vdda_q Switch" "0: sel = 00,1: sel = 01,2: sel = 10 (clk_comp),3: sel = 11 (!clk_comp)"
newline
bitfld.long 0x00 12.--14. "SW_COTG,Compensation CAPDAC top plate to vssa_q Switch" "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode,5: DFT mode,?..."
bitfld.long 0x00 8.--10. "SW_COTV,Compensation CAPDAC top plate to vdda_q Switch" "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode,5: DFT mode,?..."
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bitfld.long 0x00 4.--6. "SW_COCB,Compensation CAPDAC to CSD Bus B Switch" "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_comp),3: chop == 1 ? sel = 10 (clk_comp),4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?..."
bitfld.long 0x00 0.--2. "SW_COTCA,Compensation CAPDAC top plate to CSD Bus A Switch" "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_comp),3: chop == 1 ? sel = 10 (clk_comp),4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?..."
group.long 0x50++0x03
line.long 0x00 "SW_SEL_CDAC_CF,Fine CAPDAC Switch Control"
bitfld.long 0x00 20.--21. "SW_CFBG,Fine CAPDAC bottom plate to vssa_q Switch" "0: sel = 00,1: sel = 01,2: FINE_MODE == REFERENCE ? sel = 10 (clk_reffb),3: FINE_MODE == REFERENCE ? sel = 11 (!clk_reffb)"
bitfld.long 0x00 16.--17. "SW_CFBV,Fine CAPDAC bottom plate to vdda_q Switch" "0: sel = 00,1: sel = 01,2: FINE_MODE == REFERENCE ? sel = 10 (clk_reffb),3: FINE_MODE == REFERENCE ? sel = 11 (!clk_reffb)"
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bitfld.long 0x00 12.--14. "SW_CFTG,Fine CAPDAC top plate to vssa_q Switch" "0: sel = 00,1: sel = 01,2: sel = 10 [(FINE_MODE == REFERENCE) ?..,3: sel = 11 [(FINE_MODE == REFERENCE) ?..,4: DFT mode (ph0 ? sel = 01 : sel = 00),5: DFT mode (ph2 ? sel = 01 : sel = 00),?..."
bitfld.long 0x00 8.--10. "SW_CFTV,Fine CAPDAC top plate to vdda_q Switch" "0: sel = 00,1: sel = 01,2: sel = 10 [(FINE_MODE == REFERENCE) ?..,3: sel = 11 [(FINE_MODE == REFERENCE) ?..,4: DFT mode (ph0 ? sel = 01 : sel = 00),5: DFT mode (ph2 ? sel = 01 : sel = 00),?..."
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bitfld.long 0x00 4.--6. "SW_CFTCB,Fine CAPDAC top plate to CSD Bus B Switch" "0: sel = 00,1: sel = 01,2: case({chop FINE_MODE}) {1 REFERENCE},3: case({chop FINE_MODE}) {1 REFERENCE},4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?..."
bitfld.long 0x00 0.--2. "SW_CFTCA,Fine CAPDAC top plate to CSD Bus A Switch" "0: sel = 00,1: sel = 01,2: case({chop FINE_MODE}) {1 REFERENCE},3: case({chop FINE_MODE}) {1 REFERENCE},4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?..."
group.long 0x54++0x03
line.long 0x00 "SW_SEL_CMOD1,CMOD Switch Control 1"
bitfld.long 0x00 31. "ENABLED,CMOD1 enable" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 30. "REF_MODE,CMOD1 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD" "0: DISABLED,1: ENABLED"
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bitfld.long 0x00 24.--27. "SW_C1CG,CMOD1 to vssa_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH1_OR_PH3,6: PH2_OR_PH3,7: PH0X,8: PH1X,9: ph2 || [Fs2_ph1 && (ph1 || ph3)],10: clk_extfb_bar,?..."
bitfld.long 0x00 16.--19. "SW_C1CV,CMOD1 to vdda_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH0_OR_PH1,6: PH0X,7: PH1X,8: ph0 || [Fs2_ph0 && (ph1 || ph3)],9: clk_extfb,?..."
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bitfld.long 0x00 12.--13. "SW_C1CC,CMOD1 to CSD Bus C Switch" "0: OPEN,1: CLOSED,2: PH1_OR_PH3,?..."
bitfld.long 0x00 8.--11. "SW_C1CB,CMOD1 to CSD Bus B Switch" "0: OPEN,1: CLOSED,2: chop == 0 ? ph1,3: chop == 0 ? ph3,4: chop == 0 ? ph1,5: chop == 0 ? ph0,6: PH0,7: PH2,8: chop == 0 ? clk_extfb,9: chop == 1 ? clk_extfb,?..."
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bitfld.long 0x00 0.--3. "SW_C1CA,CMOD1 to CSD Bus A Switch" "0: OPEN,1: CLOSED,2: chop == 0 ? ph0,3: chop == 0 ? ph1,4: chop == 0 ? ph3,5: chop == 0 ? ph1,6: PH1,7: PH3,8: chop == 0 ? clk_extfb,9: chop == 1 ? clk_extfb,?..."
group.long 0x58++0x03
line.long 0x00 "SW_SEL_CMOD2,CMOD Switch Control 2"
bitfld.long 0x00 31. "ENABLED,CMOD2 enable" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 30. "REF_MODE,CMOD2 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD" "0: DISABLED,1: ENABLED"
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bitfld.long 0x00 24.--27. "SW_C2CG,CMOD2 to vssa_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH1_OR_PH3,6: PH2_OR_PH3,7: PH0X,8: PH1X,9: ph2 || [Fs2_ph1 && (ph1 || ph3)],10: clk_extfb_bar,?..."
bitfld.long 0x00 16.--19. "SW_C2CV,CMOD2 to vdda_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH0_OR_PH1,6: PH0X,7: PH1X,8: ph0 || [Fs2_ph0 && (ph1 || ph3)],9: clk_extfb,?..."
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bitfld.long 0x00 12.--13. "SW_C2CC,CMOD2 to CSD Bus C Switch" "0: OPEN,1: CLOSED,2: PH1_OR_PH3,?..."
bitfld.long 0x00 8.--11. "SW_C2CB,CMOD2 to CSD Bus B Switch" "0: OPEN,1: CLOSED,2: chop == 0 ? ph1,3: chop == 0 ? ph3,4: chop == 0 ? ph1,5: chop == 0 ? ph0,6: PH0,7: PH2,8: chop == 0 ? clk_extfb,9: chop == 1 ? clk_extfb,?..."
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bitfld.long 0x00 0.--3. "SW_C2CA,CMOD2 to CSD Bus A Switch" "0: OPEN,1: CLOSED,2: chop == 0 ? ph0,3: chop == 0 ? ph1,4: chop == 0 ? ph3,5: chop == 0 ? ph1,6: PH1,7: PH3,8: chop == 0 ? clk_extfb,9: chop == 1 ? clk_extfb,?..."
group.long 0x5C++0x03
line.long 0x00 "SW_SEL_CMOD3,CMOD Switch Control 3"
bitfld.long 0x00 31. "ENABLED,CMOD3 enable" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 30. "REF_MODE,CMOD3 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD" "0: DISABLED,1: ENABLED"
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bitfld.long 0x00 24.--27. "SW_C3CG,CMOD3 to vssa_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH1_OR_PH3,6: PH2_OR_PH3,7: PH0X,8: PH1X,9: ph2 || [Fs2_ph1 && (ph1 || ph3)],10: clk_extfb_bar,?..."
bitfld.long 0x00 16.--19. "SW_C3CV,CMOD3 to vdda_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH0_OR_PH1,6: PH0X,7: PH1X,8: ph0 || [Fs2_ph0 && (ph1 || ph3)],9: clk_extfb,?..."
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bitfld.long 0x00 12.--13. "SW_C3CC,CMOD3 to CSD Bus C Switch" "0: OPEN,1: CLOSED,2: PH1_OR_PH3,?..."
bitfld.long 0x00 8.--11. "SW_C3CB,CMOD3 to CSD Bus B Switch" "0: OPEN,1: CLOSED,2: chop == 0 ? ph1,3: chop == 0 ? ph3,4: chop == 0 ? ph1,5: chop == 0 ? ph0,6: PH0,7: PH2,8: chop == 0 ? clk_extfb,9: chop == 1 ? clk_extfb,?..."
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bitfld.long 0x00 0.--3. "SW_C3CA,CMOD3 to CSD Bus A Switch" "0: OPEN,1: CLOSED,2: chop == 0 ? ph0,3: chop == 0 ? ph1,4: chop == 0 ? ph3,5: chop == 0 ? ph1,6: PH1,7: PH3,8: chop == 0 ? clk_extfb,9: chop == 1 ? clk_extfb,?..."
group.long 0x60++0x03
line.long 0x00 "SW_SEL_CMOD4,CMOD Switch Control 4"
bitfld.long 0x00 31. "ENABLED,CMOD4 enable" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 30. "REF_MODE,CMOD4 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD" "0: DISABLED,1: ENABLED"
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bitfld.long 0x00 24.--27. "SW_C4CG,CMOD4 to vssa_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH1_OR_PH3,6: PH2_OR_PH3,7: PH0X,8: PH1X,9: ph2 || [Fs2_ph1 && (ph1 || ph3)],10: clk_extfb_bar,?..."
bitfld.long 0x00 16.--19. "SW_C4CV,CMOD4 to vdda_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH0_OR_PH1,6: PH0X,7: PH1X,8: ph0 || [Fs2_ph0 && (ph1 || ph3)],9: clk_extfb,?..."
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bitfld.long 0x00 12.--13. "SW_C4CC,CMOD4 to CSD Bus C Switch" "0: OPEN,1: CLOSED,2: PH1_OR_PH3,?..."
bitfld.long 0x00 8.--11. "SW_C4CB,CMOD4 to CSD Bus B Switch" "0: OPEN,1: CLOSED,2: chop == 0 ? ph1,3: chop == 0 ? ph3,4: chop == 0 ? ph1,5: chop == 0 ? ph0,6: PH0,7: PH2,8: chop == 0 ? clk_extfb,9: chop == 1 ? clk_extfb,?..."
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bitfld.long 0x00 0.--3. "SW_C4CA,CMOD4 to CSD Bus A Switch" "0: OPEN,1: CLOSED,2: chop == 0 ? ph0,3: chop == 0 ? ph1,4: chop == 0 ? ph3,5: chop == 0 ? ph1,6: PH1,7: PH3,8: chop == 0 ? clk_extfb,9: chop == 1 ? clk_extfb,?..."
group.long 0x70++0x03
line.long 0x00 "OBS_CTL,Observability Control"
bitfld.long 0x00 24.--27. "OBSERVE3,Selects the source for observe output signal" "0: N/A,1: COMP_OUT,2: COMP_OUT_ADV,3: COMP_OUT_SYNC,4: COUNTER_LSB,5: SCAN_DONE,6: PH0,7: PH1,8: PH2,9: PH3,10: PH0X,11: PH1X,12: UNUSED_1,13: UNUSED_2,14: UNUSED_3,15: SM_STATE_3"
bitfld.long 0x00 16.--19. "OBSERVE2,Selects the source for observe output signal" "0: N/A,1: COMP_OUT,2: COMP_OUT_ADV,3: COMP_OUT_SYNC,4: COUNTER_LSB,5: SCAN_DONE,6: PH0,7: PH1,8: PH2,9: PH3,10: PH0X,11: PH1X,12: UNUSED_1,13: UNUSED_2,14: UNUSED_3,15: SM_STATE_2"
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bitfld.long 0x00 8.--11. "OBSERVE1,Selects the source for observe output signal" "0: N/A,1: COMP_OUT,2: COMP_OUT_ADV,3: COMP_OUT_SYNC,4: COUNTER_LSB,5: SCAN_DONE,6: PH0,7: PH1,8: PH2,9: PH3,10: PH0X,11: PH1X,12: UNUSED_1,13: UNUSED_2,14: UNUSED_3,15: SM_STATE_1"
bitfld.long 0x00 0.--3. "OBSERVE0,Selects the source for observe output signal" "0: N/A,1: COMP_OUT,2: COMP_OUT_ADV,3: COMP_OUT_SYNC,4: COUNTER_LSB,5: SCAN_DONE,6: PH0,7: PH1,8: PH2,9: PH3,10: PH0X,11: PH1X,12: UNUSED_1,13: UNUSED_2,14: UNUSED_3,15: SM_STATE_0"
group.long 0x80++0x03
line.long 0x00 "WAKEUP_CTL,Wakeup Control"
bitfld.long 0x00 31. "ENABLED,If set then LP AoC FSM will operate when in DEEP_SLEEP" "0: DISABLED,1: ENABLED"
hexmask.long.word 0x00 0.--15. 1. "WAKEUP_TIMER,Timer interval between wakeup scans in LP-AoC mode"
group.long 0x84++0x03
line.long 0x00 "LP_AOC_CTL,LP-AoC Control"
bitfld.long 0x00 24.--27. "DEBOUNCE_THRESHOLD,Global threshold for successive TOUCH_THRESHOLD exceeds to warrant a full system wakeup" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 16.--23. 1. "BUCKET_STEP_SIZE,Global step size for SENSOR_BASELINE adjustment"
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hexmask.long.word 0x00 0.--15. 1. "BUCKET_THRESHOLD,Global threshold to control the per sensor SENSOR_BASELINE updates"
rgroup.long 0x100++0x03
line.long 0x00 "STATUS1,General Status Register 1"
hexmask.long.word 0x00 16.--31. 1. "RAW_COUNT_POS,Useful for determining component counts for positive and negative charge by subtracting from RAW_COUNT"
hexmask.long.word 0x00 0.--15. 1. "RAW_COUNT,Live current raw counter"
rgroup.long 0x104++0x03
line.long 0x00 "STATUS2,General Status Register 2"
hexmask.long.word 0x00 0.--15. 1. "DEBUG_CONV_COUNT,Debug raw count for a particular conversion"
rgroup.long 0x108++0x03
line.long 0x00 "STATUS3,General Status Register 3"
bitfld.long 0x00 28. "MSC_CMP_OUT,Output of main sensing comparator (synchronized)" "0,1"
bitfld.long 0x00 24. "FS_CLOCK,Sense clock Fs control waveform" "0,1"
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bitfld.long 0x00 16.--19. "SEQ_STATE,MSC Sequencer FSM state" "0: IDLE,1: WAIT_DMA_,2: LOAD_CONFIG,3: WAIT_SCAN_START,4: ASSERT_RDY,5: WAIT_CONSENSUS,6: INIT_CMOD,7: INIT_SHORT,8: PRO_OFFSET,9: PRO_DUMMY,10: PRO_WAIT,11: SUB_CONV,12: EPILOGUE,13: WAIT_DMA_READ_NEW_SAMPLE,14: WAIT_DMA_READ_EOF,15: POST_SCAN"
hexmask.long.word 0x00 0.--15. 1. "NUM_SUB_CONVS,Number of sub-conversions remaining while in PRO_DUMMY and SUB_CONV"
rgroup.long 0x10C++0x03
line.long 0x00 "RESULT_FIFO_STATUS,Result FIFO Status"
bitfld.long 0x00 31. "FIFO_OVERFLOW,Set if hardware attempts to write a RAW_COUNT (and associated metrics) to an already full result FIFO" "0,1"
bitfld.long 0x00 30. "FIFO_UNDERFLOW,Hardware sets this field to '1' when reading from an empty FIFO (RESULT_FIFO_STATUS.USED is '0')" "0,1"
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hexmask.long.word 0x00 20.--29. 1. "RD_PTR,Result FIFO write pointer: FIFO location at which a new data is written by the hardware"
hexmask.long.word 0x00 10.--19. 1. "WR_PTR,Result FIFO read pointer: FIFO location from which data is read via AHB"
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hexmask.long.word 0x00 0.--9. 1. "USED,Number of used/occupied entries in the result FIFO"
rgroup.long 0x110++0x03
line.long 0x00 "RESULT_FIFO_RD,Result FIFO Pointer"
bitfld.long 0x00 24.--27. "BAD_CONV_COUNT,Counter to indicate whether conversion of a sample is bad at the end of each chop phase" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--22. "RESAMPLE_COUNT,Counter indicating number of attempted re-samples (via NUM_AUTO_RESAMPLE) for this raw count" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "OVERFLOW,RAW_COUNT overflow" "0,1"
hexmask.long.word 0x00 0.--15. 1. "RAW_COUNT,Accumulated raw count for a sample"
group.long 0x170++0x03
line.long 0x00 "INTR,MSCv3 Interrupt Cause Register"
bitfld.long 0x00 31. "FIFO_OVERFLOW,Result FIFO overflow condition" "0,1"
bitfld.long 0x00 30. "FIFO_UNDERFLOW,Result FIFO underflow condition" "0,1"
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bitfld.long 0x00 24. "CONFIG_REQ,Request for scan configuration and scan start" "0,1"
bitfld.long 0x00 20. "CIC2_ERROR,CIC2 error detected" "0,1"
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bitfld.long 0x00 16. "FRAME,A single frame is complete" "0,1"
bitfld.long 0x00 12. "INIT,Coarse initialisation complete" "0,1"
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bitfld.long 0x00 8. "SCAN,A single scan is complete" "0,1"
bitfld.long 0x00 4. "SAMPLE,A single sample is complete" "0,1"
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bitfld.long 0x00 0. "SUB_SAMPLE,A valid CIC2 sub-sample is complete" "0,1"
group.long 0x174++0x03
line.long 0x00 "INTR_SET,MSCv3 Interrupt Set Register"
bitfld.long 0x00 31. "FIFO_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)" "0,1"
bitfld.long 0x00 30. "FIFO_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)" "0,1"
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bitfld.long 0x00 24. "CONFIG_REQ,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)" "0,1"
bitfld.long 0x00 20. "CIC2_ERROR,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)" "0,1"
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bitfld.long 0x00 16. "FRAME,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)" "0,1"
bitfld.long 0x00 12. "INIT,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)" "0,1"
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bitfld.long 0x00 8. "SCAN,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)" "0,1"
bitfld.long 0x00 4. "SAMPLE,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)" "0,1"
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bitfld.long 0x00 0. "SUB_SAMPLE,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)" "0,1"
group.long 0x178++0x03
line.long 0x00 "INTR_MASK,MSCv3 Interrupt Mask Register"
bitfld.long 0x00 31. "FIFO_OVERFLOW,Mask bit for corresponding bit in interrupt cause register" "0,1"
bitfld.long 0x00 30. "FIFO_UNDERFLOW,Mask bit for corresponding bit in interrupt cause register" "0,1"
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bitfld.long 0x00 24. "CONFIG_REQ,Mask bit for corresponding bit in interrupt cause register" "0,1"
bitfld.long 0x00 20. "CIC2_ERROR,Mask bit for corresponding bit in interrupt cause register" "0,1"
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bitfld.long 0x00 16. "FRAME,Mask bit for corresponding bit in interrupt cause register" "0,1"
bitfld.long 0x00 12. "INIT,Mask bit for corresponding bit in interrupt cause register" "0,1"
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bitfld.long 0x00 8. "SCAN,Mask bit for corresponding bit in interrupt cause register" "0,1"
bitfld.long 0x00 4. "SAMPLE,Mask bit for corresponding bit in interrupt cause register" "0,1"
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bitfld.long 0x00 0. "SUB_SAMPLE,Mask bit for corresponding bit in interrupt cause register" "0,1"
rgroup.long 0x17C++0x03
line.long 0x00 "INTR_MASKED,MSCv3 Interrupt Masked Register"
bitfld.long 0x00 31. "FIFO_OVERFLOW,Logical AND of corresponding INTR and INTR_MASK bits" "0,1"
bitfld.long 0x00 30. "FIFO_UNDERFLOW,Logical AND of corresponding INTR and INTR_MASK bits" "0,1"
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bitfld.long 0x00 24. "CONFIG_REQ,Logical AND of corresponding INTR and INTR_MASK bits" "0,1"
bitfld.long 0x00 20. "CIC2_ERROR,Logical AND of corresponding INTR and INTR_MASK bits" "0,1"
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bitfld.long 0x00 16. "FRAME,Logical AND of corresponding INTR and INTR_MASK bits" "0,1"
bitfld.long 0x00 12. "INIT,Logical AND of corresponding INTR and INTR_MASK bits" "0,1"
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bitfld.long 0x00 8. "SCAN,Logical AND of corresponding INTR and INTR_MASK bits" "0,1"
bitfld.long 0x00 4. "SAMPLE,Logical AND of corresponding INTR and INTR_MASK bits" "0,1"
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bitfld.long 0x00 0. "SUB_SAMPLE,Logical AND of corresponding INTR and INTR_MASK bits" "0,1"
group.long 0x180++0x03
line.long 0x00 "INTR_LP,Low Power Interrupt Cause Register"
bitfld.long 0x00 0. "WAKEUP,LP-AoC has detected wakeup" "0,1"
group.long 0x184++0x03
line.long 0x00 "INTR_LP_SET,Low Power Interrupt Set Register"
bitfld.long 0x00 0. "WAKEUP,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)" "0,1"
group.long 0x188++0x03
line.long 0x00 "INTR_LP_MASK,Low Power Interrupt Mask Register"
bitfld.long 0x00 0. "WAKEUP,Mask bit for corresponding bit in interrupt cause register" "0,1"
rgroup.long 0x18C++0x03
line.long 0x00 "INTR_LP_MASKED,Low Power Interrupt Masked Register"
bitfld.long 0x00 0. "WAKEUP,Logical AND of corresponding INTR_LP and INTR_LP_MASK bits" "0,1"
group.long 0x190++0x03
line.long 0x00 "FRAME_CMD,Frame Command Register"
bitfld.long 0x00 0. "START_FRAME,Start the MSCv3 sequencer frame process" "0,1"
group.long 0x198++0x03
line.long 0x00 "WAKEUP_CMD,Wakeup Command Register"
bitfld.long 0x00 16. "ABORT,Abort the LP-AoC when in WAIT_FOR_DS state" "0,1"
bitfld.long 0x00 0. "WAIT_FOR_DS,Set by firmware to prime the LP-AoC FSM to be ready to detect entry to DEEP_SLEEP" "0,1"
group.long 0x200++0x03
line.long 0x00 "SNS_STRUCT_CTL,Sensor Struct Control"
bitfld.long 0x00 8.--11. "LENGTH,Number of SNS_* registers from OFFSET for current sensor configuration in local IP storage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "OFFSET,Starting offset into SNS_* registers of current sensor configuration in local IP storage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x204++0x03
line.long 0x00 "SNS_LP_AOC_SENSOR_CTL1,LP-AoC Sensor Control 1"
hexmask.long.word 0x00 16.--31. 1. "N_BUCKET,Per sensor bucket for baseline <= raw count adjustments"
hexmask.long.word 0x00 0.--15. 1. "P_BUCKET,Per sensor bucket for baseline greater than raw count adjustments"
group.long 0x208++0x03
line.long 0x00 "SNS_LP_AOC_SENSOR_CTL2,LP-AoC Sensor Control 2"
hexmask.long.word 0x00 16.--27. 1. "TOUCH_THRESHOLD,Per sensor threshold for |baseline - rawCount| to warrant a single touch detect"
hexmask.long.word 0x00 0.--15. 1. "SENSOR_BASELINE,Per sensor baseline value"
repeat 3. (strings "2" "1" "0" )(list 0x00 0x04 0x08 )
group.long ($2+0x20C)++0x03
line.long 0x00 "SNS_SW_SEL_CSW_MASK$1,Control MUX Function Select Mask $1"
hexmask.long 0x00 0.--31. 1. "FUNC_MASK,{SNS_SW_SEL_CSW_MASK2.FUNC_MASK[x] SNS_SW_SEL_CSW_MASK1.FUNC_MASK[x] SNS_SW_SEL_CSW_MASK0.FUNC_MASK[x]} used to select appropriate SW_SEL_CSW_FUNC[x] when CSW_FUNC_MODE[x] = 1"
repeat.end
group.long 0x218++0x03
line.long 0x00 "SNS_SCAN_CTL,Sensor Scan Control"
bitfld.long 0x00 31. "INIT_BYPASS,Coarse initialisation bypass control" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 28.--30. "NUM_CONV,Number of conversions (minus 1) per scanned sample" "0: ONE,1: TWO,?,3: FOUR,?,?,?,7: EIGHT"
newline
hexmask.long.word 0x00 16.--27. 1. "COMP_DIV,The ratio (minus 1) of clk_comp::clk_mod"
hexmask.long.word 0x00 0.--15. 1. "NUM_SUB_CONVS,Number of sub-conversions (minus 1) in a conversion"
group.long 0x21C++0x03
line.long 0x00 "SNS_CDAC_CTL,Sensor CAPDAC Control"
bitfld.long 0x00 28. "LFSR_SCALE_TYPE_FL,Flatspot/Dither CAPDAC shift direction" "0: RIGHT,1: LEFT"
bitfld.long 0x00 24.--26. "LFSR_SCALE_FL,Shift the magnitude portion of the Flatspot/Dither CAPDAC LFSR output code left or right by LSFR_SCALE_FL bits" "?,?,?,?,?,?,6: MAX,?..."
newline
bitfld.long 0x00 23. "FL_EN,Dither/Flatspot LFSR enable control" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 22. "CLOCK_REF_RATE,Used to select clk_mod or clk_mod/2 to as clk_ref" "0: CLK_MOD,1: HALF_CLK_MOD"
newline
bitfld.long 0x00 21. "FINE_MODE,Operational mode for Fine CAPDAC" "0: REFERENCE,1: COMPENSATION"
bitfld.long 0x00 16.--20. "SEL_CF,Select value for Fine CAPDAC size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x00 8.--15. 1. "SEL_CO,Select value for Compensation CAPDAC size"
hexmask.long.byte 0x00 0.--7. 1. "SEL_RE,Select value for Reference CAPDAC size"
group.long 0x220++0x03
line.long 0x00 "SNS_CTL,Sense Control and Command Register"
bitfld.long 0x00 30.--31. "LFSR_BITS,Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period (spread spectrum mode)" "0: Use 2 bits,1: Use 3 bits,2: Use 4 bits,3: Use 5 bits"
bitfld.long 0x00 28.--29. "LFSR_MODE,Mode for generating the sense clock" "0: DIRECT_CLOCK,1: SPREAD_SPECTRUM,2: PRS,?..."
newline
hexmask.long.word 0x00 16.--27. 1. "SENSE_DIV,The length (minus 1) of the sense modulation 'clock' period in clk_mod cycles (frequency = Fs)"
hexmask.long.byte 0x00 8.--15. 1. "DECIM_RATE,Sets the decimation rate for the sinc^2 filter (CIC2)"
newline
bitfld.long 0x00 6.--7. "SENSE_MODE_SEL,Sense mode register structure selection" "0: Use MODE_STRUCT[0],1: Use MODE_STRUCT[1],2: Use MODE_STRUCT[2],3: Use MODE_STRUCT[3]"
bitfld.long 0x00 4.--5. "MULTI_CH_MODE,Multi channel mode configuration" "0: OFF,1: EXTERNAL,2: INTERNAL,?..."
newline
bitfld.long 0x00 2. "LAST,Indicator that current sensor configuration is the last sensor in the frame" "0,1"
bitfld.long 0x00 1. "VALID,Indicator of sensor configuration validity" "0,1"
newline
bitfld.long 0x00 0. "START_SCAN,Start the MSCv3 sequencer scan process" "0,1"
repeat 32. (increment 0 1) (increment 0 0x04)
group.long ($2+0x300)++0x03
line.long 0x00 "SW_SEL_CSW[$1],Control Switch MUX Switch Control $1"
bitfld.long 0x00 31. "ENABLED,Control MUX Sensor N enable" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 30. "REF_MODE,Control MUX Sensor N is used as a reference" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 24.--27. "SW_SNCG,Control MUX Sensor N to vssa_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH1_OR_PH3,6: PH2_OR_PH3,7: PH0X,8: PH1X,9: ph2 || [Fs2_ph1 && (ph1 || ph3)],10: clk_extfb_bar,?..."
bitfld.long 0x00 16.--19. "SW_SNCV,Control MUX Sensor N to vdda_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH0_OR_PH1,6: PH0X,7: PH1X,8: ph0 || [Fs2_ph0 && (ph1 || ph3)],9: clk_extfb,?..."
newline
bitfld.long 0x00 12.--13. "SW_SNCC,Control MUX Sensor N to CSD Bus C Switch" "0: OPEN,1: CLOSED,2: PH1_OR_PH3,?..."
bitfld.long 0x00 8.--11. "SW_SNCB,Control MUX Sensor N to CSD Bus B Switch" "0: OPEN,1: CLOSED,2: chop == 0 ? ph1,3: chop == 0 ? ph3,4: chop == 0 ? ph1,5: chop == 0 ? ph0,6: PH0,7: PH2,8: chop == 0 ? clk_extfb,9: chop == 1 ? clk_extfb,?..."
newline
bitfld.long 0x00 0.--3. "SW_SNCA,Control MUX Sensor N to CSD Bus A Switch" "0: OPEN,1: CLOSED,2: chop == 0 ? ph0,3: chop == 0 ? ph1,4: chop == 0 ? ph3,5: chop == 0 ? ph1,6: PH1,7: PH3,8: chop == 0 ? clk_extfb,9: chop == 1 ? clk_extfb,?..."
repeat.end
repeat 8. (increment 0 1) (increment 0 0x04)
group.long ($2+0x400)++0x03
line.long 0x00 "SW_SEL_CSW_FUNC[$1],Control Switch MUX Switch Control Global Functions $1"
bitfld.long 0x00 31. "ENABLED,Control MUX Sensor enable" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 30. "REF_MODE,Control MUX Sensor is used as a reference" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 24.--27. "SW_SNCG,Control MUX Sensor to vssa_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH1_OR_PH3,6: PH2_OR_PH3,7: PH0X,8: PH1X,9: ph2 || [Fs2_ph1 && (ph1 || ph3)],10: clk_extfb_bar,?..."
bitfld.long 0x00 16.--19. "SW_SNCV,Control MUX Sensor to vdda_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH0_OR_PH1,6: PH0X,7: PH1X,8: ph0 || [Fs2_ph0 && (ph1 || ph3)],9: clk_extfb,?..."
newline
bitfld.long 0x00 12.--13. "SW_SNCC,Control MUX Sensor to CSD Bus C Switch" "0: OPEN,1: CLOSED,2: PH1_OR_PH3,?..."
bitfld.long 0x00 8.--11. "SW_SNCB,Control MUX Sensor to CSD Bus B Switch" "0: OPEN,1: CLOSED,2: chop == 0 ? ph1,3: chop == 0 ? ph3,4: chop == 0 ? ph1,5: chop == 0 ? ph0,6: PH0,7: PH2,8: chop == 0 ? clk_extfb,9: chop == 1 ? clk_extfb,?..."
newline
bitfld.long 0x00 0.--3. "SW_SNCA,Control MUX Sensor to CSD Bus A Switch" "0: OPEN,1: CLOSED,2: chop == 0 ? ph0,3: chop == 0 ? ph1,4: chop == 0 ? ph3,5: chop == 0 ? ph1,6: PH1,7: PH3,8: chop == 0 ? clk_extfb,9: chop == 1 ? clk_extfb,?..."
repeat.end
repeat 4096. (increment 0 1) (increment 0 0x04)
group.long ($2+0x1000)++0x03
line.long 0x00 "SENSOR_DATA[$1],Sensor Configuration Storage $1"
hexmask.long 0x00 0.--31. 1. "DATA,Local IP storage to support per-sensor configuration for AS-MS mode"
repeat.end
group.long 0xFF00++0x03
line.long 0x00 "TRIM_CTL,Trim Control"
bitfld.long 0x00 5. "TRIM_POLARITY,Controls polarity of comparator offset trim" "0,1"
bitfld.long 0x00 4. "TRIM_EN,Enables comparator offset trim" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 0.--3. "TRIM_IN,Controls magnitude of comparator offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
repeat 3. (increment 0 1)(increment 0 0x20)
tree "MODE[$1]"
group.long ($2+0x500)++0x03
line.long 0x00 "SENSE_DUTY_CTL,Sense Clock Duty Cycle Control"
bitfld.long 0x00 28. "PHASE_MODE_SEL,Select 4-phase or 2-phase mode" "0: FOUR_PHASE,1: TWO_PHASE"
bitfld.long 0x00 24. "PHASE_SHIFT_EN,Enable phase shift logic that generates the Ph0X and Ph1X waveforms" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 10. "PHX_GAP_2CYCLE_EN,If set applies a two cycle gap on ph0X/ph1X if the corresponding PHASE_GAP_*_EN is set" "0: ONE_CYCLE,1: TWO_CYCLE"
bitfld.long 0x00 9. "PHASE_GAP_PH1X_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph1x" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 8. "PHASE_GAP_PH0X_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph0x" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 6. "PH_GAP_2CYCLE_EN,If set applies a two cycle gap on ph0/ph1/ph2/ph3/Fs2_ph0/Fs2_ph1 if the corresponding PHASE_GAP_*_EN is set" "0: ONE_CYCLE,1: TWO_CYCLE"
newline
bitfld.long 0x00 5. "PHASE_GAP_FS2_PH1_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of Fs2_ph0" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 4. "PHASE_GAP_FS2_PH0_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of Fs2_ph0" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 3. "PHASE_GAP_PH3_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph3" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 2. "PHASE_GAP_PH2_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph2" "0: DISABLED,1: ENABLED"
newline
bitfld.long 0x00 1. "PHASE_GAP_PH1_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph1" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 0. "PHASE_GAP_PH0_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph0" "0: DISABLED,1: ENABLED"
group.long ($2+0x504)++0x03
line.long 0x00 "SW_SEL_CDAC_FL,Flatspot/Dither CAPDAC Switch Control"
bitfld.long 0x00 31. "ACTIVATION_MODE,Activation event for Dither/Flatspot LFSR" "0: PH0,1: PH0_OR_PH2"
bitfld.long 0x00 20.--22. "SW_FLBG,Flatspot/Dither CAPDAC bottom plate to vssa_q Switch" "0: OPEN,1: CLOSED,2: PH0X,3: PH1X,4: [(msb^ph1)^(ph0||ph1)] & [ph0||ph1],5: (![(msb^ph1)^(ph0||ph1)]) & [ph0||ph1],6: [(msb^(ph2||ph3))^(ph0||ph2)] &..,7: (![(msb^(ph2||ph3))^(ph0||ph2)]) &.."
newline
bitfld.long 0x00 16.--18. "SW_FLBV,Flatspot/Dither CAPDAC bottom plate to vdda_q Switch" "0: OPEN,1: CLOSED,2: PH0X,3: PH1X,4: [(msb^ph1)^(ph0||ph1)] & [ph0||ph1],5: (![(msb^ph1)^(ph0||ph1)]) & [ph0||ph1],6: [(msb^(ph2||ph3))^(ph0||ph2)] &..,7: (![(msb^(ph2||ph3))^(ph0||ph2)]) &.."
bitfld.long 0x00 12.--14. "SW_FLTG,Flatspot/Dither CAPDAC top plate to vssa_q Switch" "0: OPEN,1: CLOSED,2: PH1,3: PH0_OR_PH2,4: DFT mode,5: DFT mode,?..."
newline
bitfld.long 0x00 8.--9. "SW_FLTV,Flatspot/Dither CAPDAC top plate to vdda_q Switch" "0: OPEN,1: CLOSED,2: DFT mode,3: DFT mode"
bitfld.long 0x00 4.--6. "SW_FLCB,Flatspot/Dither CAPDAC to CSD Bus B Switch" "0: OPEN,1: CLOSED,2: chop == 1 ? ph1,3: chop == 1 ? ph3,4: chop == 1 ? ph0,5: chop == 1 ? ph1,?..."
newline
bitfld.long 0x00 0.--2. "SW_FLTCA,Flatspot/Dither CAPDAC top plate to CSD Bus A Switch" "0: OPEN,1: CLOSED,2: chop == 1 ? ph1,3: chop == 1 ? ph3,4: chop == 1 ? ph0,5: chop == 1 ? ph1,?..."
group.long ($2+0x508)++0x03
line.long 0x00 "SW_SEL_TOP,Top Level Switch Control"
bitfld.long 0x00 31. "MBF,AMUXBUSB to Filter Switch" "0: OPEN,1: CLOSED"
bitfld.long 0x00 30. "RMF,Ratiometric Reference to Filter Switch" "0: OPEN,1: CLOSED"
newline
bitfld.long 0x00 29. "BGRF,Bandgap Reference to Filter Switch" "0: OPEN,1: CLOSED"
bitfld.long 0x00 24.--27. "SHG,COAX Shield to vssa_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH3,6: PH0X,7: PH1X,8: ph0 || [Fs2_ph0 && (ph1 || ph3)],9: ph2 || [Fs2_ph1 && (ph1 || ph3)],?..."
newline
bitfld.long 0x00 20.--23. "SHV,COAX Shield to vdda_q Switch" "0: OPEN,1: CLOSED,2: PH0,3: PH1,4: PH2,5: PH3,6: PH0X,7: PH1X,8: ph0 || [Fs2_ph0 && (ph1 || ph3)],9: ph2 || [Fs2_ph1 && (ph1 || ph3)],?..."
bitfld.long 0x00 18.--19. "SOSH,COAX Shield to Shield Buffer Output Switch" "0: OPEN,1: CLOSED,2: PH1_OR_PH3,?..."
newline
bitfld.long 0x00 16.--17. "BYB,AMUXBUS B to CSD Bus B Switch" "0: OPEN_ISOLATED,1: OPEN_NON_ISOLATED_CSDBUS,2: OPEN_NON_ISOLATED_AMUXBUS,?..."
bitfld.long 0x00 15. "AYB_EN,AMUXBUS A to CSD Bus B Switch" "0: Opens first part of AYB switch,1: Closes first part of AYB switch and disables.."
newline
bitfld.long 0x00 12.--14. "AYB_CTL,AMUXBUS A to CSD Bus B Switch" "0: Opens second part of AYB switch,1: CLOSED,2: chop == 0 ? ph1,3: chop == 0 ? ph3,4: chop == 0 ? ph1,5: chop == 0 ? ph0,6: PH0,7: PH2"
bitfld.long 0x00 11. "AYA_EN,AMUXBUS A to CSD Bus A Switch" "0: Opens first part of AYA switch,1: Closes first part of AYA switch and disables.."
newline
bitfld.long 0x00 8.--10. "AYA_CTL,AMUXBUS A to CSD Bus A Switch" "0: Opens second part of AYA switch,1: CLOSED,2: chop == 0 ? ph0,3: chop == 0 ? ph1,4: chop == 0 ? ph3,5: chop == 0 ? ph1,6: PH0,7: PH2"
bitfld.long 0x00 6. "MBCC,AMUXBUSB to CSD Bus C Switch" "0: OPEN,1: CLOSED"
newline
bitfld.long 0x00 4. "CBCC,CSD Bus B to CSD Bus C Switch" "0: OPEN,1: CLOSED"
bitfld.long 0x00 2. "CACC,CSD Bus A to CSD Bus C Switch" "0: OPEN,1: CLOSED"
newline
bitfld.long 0x00 0. "CACB,CSD Bus A to CSD Bus B Switch" "0: OPEN,1: CLOSED"
group.long ($2+0x50C)++0x03
line.long 0x00 "SW_SEL_COMP,MSC Comparator Switch Control"
bitfld.long 0x00 31. "HALF_WAVE_EN,Enables halfwave mode in the comparator where reference is vdda_q" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 22. "CMF,Comparator Minus Terminal to Reference Filter Switch" "0: OPEN,1: CLOSED"
newline
bitfld.long 0x00 20. "CMG,Comparator Minus Terminal to vssa_q Switch" "0: OPEN,1: CLOSED"
bitfld.long 0x00 18. "CMV,Comparator Minus Terminal to vdda_q Switch" "0: OPEN,1: CLOSED"
newline
bitfld.long 0x00 16. "CMCS4,Comparator Minus Terminal to CMOD4 Sense Switch" "0: OPEN,1: CLOSED"
bitfld.long 0x00 14. "CMCS2,Comparator Minus Terminal to CMOD2 Sense Switch" "0: OPEN,1: CLOSED"
newline
bitfld.long 0x00 12. "CPF,Comparator Plus Terminal to Reference Filter Switch" "0: OPEN,1: CLOSED"
bitfld.long 0x00 10. "CMCB,Comparator Minus Terminal to CSD Bus B Switch" "0: OPEN,1: CLOSED"
newline
bitfld.long 0x00 8. "CPCB,Comparator Plus Terminal to CSD Bus B Switch" "0: OPEN,1: CLOSED"
bitfld.long 0x00 6. "CPCA,Comparator Plus Terminal to CSD Bus A Switch" "0: OPEN,1: CLOSED"
newline
bitfld.long 0x00 4. "CPMA,Comparator Plus Terminal to AMUXBUSA Switch" "0: OPEN,1: CLOSED"
bitfld.long 0x00 2. "CPCS3,Comparator Plus Terminal to CMOD3 Sense Switch" "0: OPEN,1: CLOSED"
newline
bitfld.long 0x00 0. "CPCS1,Comparator Plus Terminal to CMOD1 Sense Switch" "0: OPEN,1: CLOSED"
group.long ($2+0x510)++0x03
line.long 0x00 "SW_SEL_SH,Shielding Switch Control"
bitfld.long 0x00 31. "BUF_EN,Enable the shield buffer" "0: DISABLED,1: ENABLED"
bitfld.long 0x00 24.--27. "BUF_SEL,Selects value of compensation capacitance in shield buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 18. "CCSO,CSD Bus C to Shield OpAmp Switch" "0: OPEN,1: CLOSED"
bitfld.long 0x00 16. "FSP,Reference Filter to Shield Positive Terminal Switch" "0: OPEN,1: CLOSED"
newline
bitfld.long 0x00 14. "SPCS3,Shield Minus Terminal to CMOD3 Sense Switch" "0: OPEN,1: CLOSED"
bitfld.long 0x00 12. "SPCS1,Shield Minus Terminal to CMOD1 Sense Switch" "0: OPEN,1: CLOSED"
newline
bitfld.long 0x00 10. "CBSO,CSD Bus B to Shield OpAmp Switch" "0: OPEN,1: CLOSED"
bitfld.long 0x00 8. "SOMB,Shield OpAmp to AMUXBUSB Switch" "0: OPEN,1: CLOSED"
newline
bitfld.long 0x00 6. "C3SH,cmod3_4_sh to sh Switch (Drives cmod3_4_sh with shield signal)" "0: OPEN,1: CLOSED"
bitfld.long 0x00 4. "C3SHG,cmod3_4_sh to vssa Switch" "0: OPEN,1: CLOSED"
newline
bitfld.long 0x00 2. "C1SH,cmod1_2_sh to sh Switch (Drives cmod1_2_sh with shield signal)" "0: OPEN,1: CLOSED"
bitfld.long 0x00 0. "C1SHG,cmod1_2_sh to vssa Switch" "0: OPEN,1: CLOSED"
tree.end
repeat.end
tree.end
repeat.end
tree.end
endif
tree "PASS (PASS top-level MMIO (DSABv2 INTR))"
tree "PASS0"
base ad:0x403F0000
sif cpuis("psoc4100smax")
rgroup.long 0x00++0x03
line.long 0x00 "INTR_CAUSE,Interrupt cause register"
bitfld.long 0x00 3. "CTB3_INT,CTB3 interrupt pending" "0,1"
bitfld.long 0x00 2. "CTB2_INT,CTB2 interrupt pending" "0,1"
newline
bitfld.long 0x00 1. "CTB1_INT,CTB1 interrupt pending" "0,1"
bitfld.long 0x00 0. "CTB0_INT,CTB0 interrupt pending" "0,1"
group.long 0x30++0x03
line.long 0x00 "DFT_CTRL,DFT control register"
bitfld.long 0x00 0. "DSAB_ADFT_RES_EN,Close the switch to connect the DSAB ADFT resistor to the AMUXBUS" "0,1"
group.long 0x108++0x03
line.long 0x00 "PASS_CTRL,PASS Control"
hexmask.long.byte 0x00 8.--15. 1. "RMB_BITS,Risk mitigation bits"
bitfld.long 0x00 1. "PMPCLK_SRC," "0: Pump clk is clk_hf,1: Pump clk is direct from SRSS"
newline
bitfld.long 0x00 0. "PMPCLK_BYP," "0: Pump clk is clk_hf/2,1: Pump clk is selected from PMPCLK_SRC"
group.long 0xF00++0x03
line.long 0x00 "DSAB_TRIM,DSAB Trim bits"
bitfld.long 0x00 4.--5. "DSAB_RMB_BITS,Risk mitigation bits" "0,1,2,3"
bitfld.long 0x00 0.--3. "IBIAS_TRIM," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
tree "DSAB"
sif cpuis("psoc4100smax")
group.long 0xE00++0x03
line.long 0x00 "DSAB_CTRL,global DSAB control"
bitfld.long 0x00 31. "ENABLED,This field (along with SEL_OUT and REF_SWAP_EN) provides bitwise selection of the current sources that drive the DSAB ZTC and PTAT outputs" "0,1"
bitfld.long 0x00 28. "STARTUP_RM,Risk mitigation control" "0,1"
newline
bitfld.long 0x00 24. "BYPASS_MODE_EN," "0,1"
bitfld.long 0x00 16.--19. "REF_SWAP_EN,This field (along with SEL_OUT and ENABLED) provides bitwise selection of the current sources that drive the DSAB ZTC and PTAT outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "SEL_OUT,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "CURRENT_SEL,DSAB DAC control field Nominal DSAB Output Current = CURRENT_SEL * 0.075 uA In products with SRSS-LITE this setting impacts the CTB(m) offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xE04++0x03
line.long 0x00 "DSAB_DFT,DFT bits"
bitfld.long 0x00 0.--3. "EN_DFT," "0: DSAB DFT disabled,1: PTAT<0>,2: PTAT<1>,3: PTAT<1:0>,4: PTAT<2>,?,?,7: PTAT<2:0>,8: PTAT<3>,9: DSAB Reg Out,?,?,?,?,?,15: PTAT<3:0>"
endif
tree.end
tree.end
sif cpuis("CY8C4148*")
tree "PASS1"
base ad:0x404F0000
rgroup.long 0x00++0x03
line.long 0x00 "INTR_CAUSE,Interrupt cause register"
bitfld.long 0x00 3. "CTB3_INT,CTB3 interrupt pending" "0,1"
bitfld.long 0x00 2. "CTB2_INT,CTB2 interrupt pending" "0,1"
newline
bitfld.long 0x00 1. "CTB1_INT,CTB1 interrupt pending" "0,1"
bitfld.long 0x00 0. "CTB0_INT,CTB0 interrupt pending" "0,1"
group.long 0x30++0x03
line.long 0x00 "DFT_CTRL,DFT control register"
bitfld.long 0x00 0. "DSAB_ADFT_RES_EN,Close the switch to connect the DSAB ADFT resistor to the AMUXBUS" "0,1"
group.long 0x108++0x03
line.long 0x00 "PASS_CTRL,PASS Control"
hexmask.long.byte 0x00 8.--15. 1. "RMB_BITS,Risk mitigation bits"
bitfld.long 0x00 1. "PMPCLK_SRC," "0: Pump clk is clk_hf,1: Pump clk is direct from SRSS"
newline
bitfld.long 0x00 0. "PMPCLK_BYP," "0: Pump clk is clk_hf/2,1: Pump clk is selected from PMPCLK_SRC"
group.long 0xF00++0x03
line.long 0x00 "DSAB_TRIM,DSAB Trim bits"
bitfld.long 0x00 4.--5. "DSAB_RMB_BITS,Risk mitigation bits" "0,1,2,3"
bitfld.long 0x00 0.--3. "IBIAS_TRIM," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree "DSAB"
group.long 0xE00++0x03
line.long 0x00 "DSAB_CTRL,global DSAB control"
bitfld.long 0x00 31. "ENABLED,This field (along with SEL_OUT and REF_SWAP_EN) provides bitwise selection of the current sources that drive the DSAB ZTC and PTAT outputs" "0,1"
bitfld.long 0x00 28. "STARTUP_RM,Risk mitigation control" "0,1"
newline
bitfld.long 0x00 24. "BYPASS_MODE_EN," "0,1"
bitfld.long 0x00 16.--19. "REF_SWAP_EN,This field (along with SEL_OUT and ENABLED) provides bitwise selection of the current sources that drive the DSAB ZTC and PTAT outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "SEL_OUT,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--5. "CURRENT_SEL,DSAB DAC control field Nominal DSAB Output Current = CURRENT_SEL * 0.075 uA In products with SRSS-LITE this setting impacts the CTB(m) offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xE04++0x03
line.long 0x00 "DSAB_DFT,DFT bits"
bitfld.long 0x00 0.--3. "EN_DFT," "0: DSAB DFT disabled,1: PTAT<0>,2: PTAT<1>,3: PTAT<1:0>,4: PTAT<2>,?,?,7: PTAT<2:0>,8: PTAT<3>,9: DSAB Reg Out,?,?,?,?,?,15: PTAT<3:0>"
tree.end
tree.end
endif
tree.end
tree "PERI (Peripheral Interconnect)"
base ad:0x40010000
sif cpuis("psoc4100smax")
group.long 0x00++0x03
line.long 0x00 "DIV_CMD,Divider command register"
bitfld.long 0x00 31. "ENABLE,Clock divider enable command (mutually exclusive with DISABLE)" "0: Disable the divider using the DIV_CMD.DISABLE,1: Configure the divider's DIV_XXX_CTL register"
bitfld.long 0x00 30. "DISABLE,Clock divider disable command (mutually exlusive with ENABLE)" "0,1"
newline
bitfld.long 0x00 14.--15. "PA_SEL_TYPE,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
bitfld.long 0x00 8.--13. "PA_SEL_DIV,(PA_SEL_TYPE PA_SEL_DIV) pecifies the divider to which phase alignment is performed for the clock enable command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 6.--7. "SEL_TYPE,Specifies the divider type of the divider on which the command is performed" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
bitfld.long 0x00 0.--5. "SEL_DIV,(SEL_TYPE SEL_DIV) specifies the divider on which the command (DISABLE/ENABLE) is performed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 64. (increment 0 1) (increment 0 0x04)
group.long ($2+0x100)++0x03
line.long 0x00 "PCLK_CTL[$1],Programmable clock control register $1"
bitfld.long 0x00 6.--7. "SEL_TYPE,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers"
bitfld.long 0x00 0.--5. "SEL_DIV,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
repeat 64. (increment 0 1) (increment 0 0x04)
group.long ($2+0x200)++0x03
line.long 0x00 "DIV_8_CTL[$1],Divider control register (for 8.0 divider $1"
hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)"
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
repeat.end
repeat 64. (increment 0 1) (increment 0 0x04)
group.long ($2+0x300)++0x03
line.long 0x00 "DIV_16_CTL[$1],Divider control register (for 16.0 divider $1"
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
repeat.end
repeat 64. (increment 0 1) (increment 0 0x04)
group.long ($2+0x400)++0x03
line.long 0x00 "DIV_16_5_CTL[$1],Divider control register (for 16.5 divider $1"
hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)"
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
repeat.end
repeat 63. (increment 0 1) (increment 0 0x04)
group.long ($2+0x500)++0x03
line.long 0x00 "DIV_24_5_CTL[$1],Divider control register (for 24.5 divider $1"
hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)"
bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 0. "EN,Divider enabled" "0,1"
repeat.end
group.long 0x600++0x03
line.long 0x00 "TR_CTL,Trigger control register"
bitfld.long 0x00 31. "TR_ACT,SW sets this field to '1' by to activate (set to '1') a trigger as identified by TR_SEL and TR_OUT for TR_COUNT cycles" "0,1"
bitfld.long 0x00 30. "TR_OUT,Specifies whether trigger activation is for a specific input or ouput trigger of the trigger multiplexer" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "TR_COUNT,Amount of cycles a specific trigger is activated"
bitfld.long 0x00 8.--11. "TR_GROUP,Specifies the trigger group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.byte 0x00 0.--6. 1. "TR_SEL,Specifies the activated trigger when TR_ACT is '1'"
endif
repeat 4. (increment 0 1)(increment 0 0x200)
tree "TR_GROUP[$1]"
sif cpuis("psoc4100smax")
group.long ($2+0x2000)++0x03
line.long 0x00 "TR_OUT_CTL[0],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2004)++0x03
line.long 0x00 "TR_OUT_CTL[1],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2008)++0x03
line.long 0x00 "TR_OUT_CTL[2],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x200C)++0x03
line.long 0x00 "TR_OUT_CTL[3],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2010)++0x03
line.long 0x00 "TR_OUT_CTL[4],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2014)++0x03
line.long 0x00 "TR_OUT_CTL[5],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2018)++0x03
line.long 0x00 "TR_OUT_CTL[6],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x201C)++0x03
line.long 0x00 "TR_OUT_CTL[7],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2020)++0x03
line.long 0x00 "TR_OUT_CTL[8],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2024)++0x03
line.long 0x00 "TR_OUT_CTL[9],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2028)++0x03
line.long 0x00 "TR_OUT_CTL[10],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x202C)++0x03
line.long 0x00 "TR_OUT_CTL[11],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2030)++0x03
line.long 0x00 "TR_OUT_CTL[12],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2034)++0x03
line.long 0x00 "TR_OUT_CTL[13],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2038)++0x03
line.long 0x00 "TR_OUT_CTL[14],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x203C)++0x03
line.long 0x00 "TR_OUT_CTL[15],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2040)++0x03
line.long 0x00 "TR_OUT_CTL[16],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2044)++0x03
line.long 0x00 "TR_OUT_CTL[17],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2048)++0x03
line.long 0x00 "TR_OUT_CTL[18],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x204C)++0x03
line.long 0x00 "TR_OUT_CTL[19],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2050)++0x03
line.long 0x00 "TR_OUT_CTL[20],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2054)++0x03
line.long 0x00 "TR_OUT_CTL[21],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2058)++0x03
line.long 0x00 "TR_OUT_CTL[22],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x205C)++0x03
line.long 0x00 "TR_OUT_CTL[23],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2060)++0x03
line.long 0x00 "TR_OUT_CTL[24],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2064)++0x03
line.long 0x00 "TR_OUT_CTL[25],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2068)++0x03
line.long 0x00 "TR_OUT_CTL[26],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x206C)++0x03
line.long 0x00 "TR_OUT_CTL[27],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2070)++0x03
line.long 0x00 "TR_OUT_CTL[28],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2074)++0x03
line.long 0x00 "TR_OUT_CTL[29],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2078)++0x03
line.long 0x00 "TR_OUT_CTL[30],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x207C)++0x03
line.long 0x00 "TR_OUT_CTL[31],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2080)++0x03
line.long 0x00 "TR_OUT_CTL[32],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2084)++0x03
line.long 0x00 "TR_OUT_CTL[33],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2088)++0x03
line.long 0x00 "TR_OUT_CTL[34],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x208C)++0x03
line.long 0x00 "TR_OUT_CTL[35],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2090)++0x03
line.long 0x00 "TR_OUT_CTL[36],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2094)++0x03
line.long 0x00 "TR_OUT_CTL[37],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2098)++0x03
line.long 0x00 "TR_OUT_CTL[38],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x209C)++0x03
line.long 0x00 "TR_OUT_CTL[39],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20A0)++0x03
line.long 0x00 "TR_OUT_CTL[40],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20A4)++0x03
line.long 0x00 "TR_OUT_CTL[41],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20A8)++0x03
line.long 0x00 "TR_OUT_CTL[42],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20AC)++0x03
line.long 0x00 "TR_OUT_CTL[43],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20B0)++0x03
line.long 0x00 "TR_OUT_CTL[44],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20B4)++0x03
line.long 0x00 "TR_OUT_CTL[45],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20B8)++0x03
line.long 0x00 "TR_OUT_CTL[46],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20BC)++0x03
line.long 0x00 "TR_OUT_CTL[47],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20C0)++0x03
line.long 0x00 "TR_OUT_CTL[48],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20C4)++0x03
line.long 0x00 "TR_OUT_CTL[49],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20C8)++0x03
line.long 0x00 "TR_OUT_CTL[50],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20CC)++0x03
line.long 0x00 "TR_OUT_CTL[51],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20D0)++0x03
line.long 0x00 "TR_OUT_CTL[52],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20D4)++0x03
line.long 0x00 "TR_OUT_CTL[53],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20D8)++0x03
line.long 0x00 "TR_OUT_CTL[54],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20DC)++0x03
line.long 0x00 "TR_OUT_CTL[55],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20E0)++0x03
line.long 0x00 "TR_OUT_CTL[56],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20E4)++0x03
line.long 0x00 "TR_OUT_CTL[57],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20E8)++0x03
line.long 0x00 "TR_OUT_CTL[58],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20EC)++0x03
line.long 0x00 "TR_OUT_CTL[59],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20F0)++0x03
line.long 0x00 "TR_OUT_CTL[60],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20F4)++0x03
line.long 0x00 "TR_OUT_CTL[61],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20F8)++0x03
line.long 0x00 "TR_OUT_CTL[62],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x20FC)++0x03
line.long 0x00 "TR_OUT_CTL[63],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2100)++0x03
line.long 0x00 "TR_OUT_CTL[64],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2104)++0x03
line.long 0x00 "TR_OUT_CTL[65],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2108)++0x03
line.long 0x00 "TR_OUT_CTL[66],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x210C)++0x03
line.long 0x00 "TR_OUT_CTL[67],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2110)++0x03
line.long 0x00 "TR_OUT_CTL[68],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2114)++0x03
line.long 0x00 "TR_OUT_CTL[69],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2118)++0x03
line.long 0x00 "TR_OUT_CTL[70],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x211C)++0x03
line.long 0x00 "TR_OUT_CTL[71],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2120)++0x03
line.long 0x00 "TR_OUT_CTL[72],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2124)++0x03
line.long 0x00 "TR_OUT_CTL[73],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2128)++0x03
line.long 0x00 "TR_OUT_CTL[74],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x212C)++0x03
line.long 0x00 "TR_OUT_CTL[75],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2130)++0x03
line.long 0x00 "TR_OUT_CTL[76],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2134)++0x03
line.long 0x00 "TR_OUT_CTL[77],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2138)++0x03
line.long 0x00 "TR_OUT_CTL[78],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x213C)++0x03
line.long 0x00 "TR_OUT_CTL[79],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2140)++0x03
line.long 0x00 "TR_OUT_CTL[80],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2144)++0x03
line.long 0x00 "TR_OUT_CTL[81],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2148)++0x03
line.long 0x00 "TR_OUT_CTL[82],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x214C)++0x03
line.long 0x00 "TR_OUT_CTL[83],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2150)++0x03
line.long 0x00 "TR_OUT_CTL[84],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2154)++0x03
line.long 0x00 "TR_OUT_CTL[85],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2158)++0x03
line.long 0x00 "TR_OUT_CTL[86],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x215C)++0x03
line.long 0x00 "TR_OUT_CTL[87],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2160)++0x03
line.long 0x00 "TR_OUT_CTL[88],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2164)++0x03
line.long 0x00 "TR_OUT_CTL[89],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2168)++0x03
line.long 0x00 "TR_OUT_CTL[90],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x216C)++0x03
line.long 0x00 "TR_OUT_CTL[91],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2170)++0x03
line.long 0x00 "TR_OUT_CTL[92],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2174)++0x03
line.long 0x00 "TR_OUT_CTL[93],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2178)++0x03
line.long 0x00 "TR_OUT_CTL[94],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x217C)++0x03
line.long 0x00 "TR_OUT_CTL[95],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2180)++0x03
line.long 0x00 "TR_OUT_CTL[96],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2184)++0x03
line.long 0x00 "TR_OUT_CTL[97],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2188)++0x03
line.long 0x00 "TR_OUT_CTL[98],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x218C)++0x03
line.long 0x00 "TR_OUT_CTL[99],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2190)++0x03
line.long 0x00 "TR_OUT_CTL[100],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2194)++0x03
line.long 0x00 "TR_OUT_CTL[101],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x2198)++0x03
line.long 0x00 "TR_OUT_CTL[102],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x219C)++0x03
line.long 0x00 "TR_OUT_CTL[103],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21A0)++0x03
line.long 0x00 "TR_OUT_CTL[104],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21A4)++0x03
line.long 0x00 "TR_OUT_CTL[105],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21A8)++0x03
line.long 0x00 "TR_OUT_CTL[106],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21AC)++0x03
line.long 0x00 "TR_OUT_CTL[107],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21B0)++0x03
line.long 0x00 "TR_OUT_CTL[108],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21B4)++0x03
line.long 0x00 "TR_OUT_CTL[109],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21B8)++0x03
line.long 0x00 "TR_OUT_CTL[110],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21BC)++0x03
line.long 0x00 "TR_OUT_CTL[111],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21C0)++0x03
line.long 0x00 "TR_OUT_CTL[112],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21C4)++0x03
line.long 0x00 "TR_OUT_CTL[113],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21C8)++0x03
line.long 0x00 "TR_OUT_CTL[114],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21CC)++0x03
line.long 0x00 "TR_OUT_CTL[115],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21D0)++0x03
line.long 0x00 "TR_OUT_CTL[116],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21D4)++0x03
line.long 0x00 "TR_OUT_CTL[117],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21D8)++0x03
line.long 0x00 "TR_OUT_CTL[118],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21DC)++0x03
line.long 0x00 "TR_OUT_CTL[119],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21E0)++0x03
line.long 0x00 "TR_OUT_CTL[120],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21E4)++0x03
line.long 0x00 "TR_OUT_CTL[121],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21E8)++0x03
line.long 0x00 "TR_OUT_CTL[122],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21EC)++0x03
line.long 0x00 "TR_OUT_CTL[123],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21F0)++0x03
line.long 0x00 "TR_OUT_CTL[124],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21F4)++0x03
line.long 0x00 "TR_OUT_CTL[125],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21F8)++0x03
line.long 0x00 "TR_OUT_CTL[126],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
group.long ($2+0x21FC)++0x03
line.long 0x00 "TR_OUT_CTL[127],Trigger control register"
hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger"
endif
tree.end
repeat.end
tree.end
tree "PRGIO (Programmable IO configuration)"
base ad:0x40050000
repeat 3. (increment 0 1)(increment 0 0x100)
tree "PRT[$1]"
sif cpuis("psoc4100smax")
group.long ($2+0x00)++0x03
line.long 0x00 "CTL,Control register"
bitfld.long 0x00 31. "ENABLED,Enable for programmable IO" "0,1"
bitfld.long 0x00 25. "PIPELINE_EN,Enable for pipeline register: '0': Disabled (register is bypassed)" "0,1"
newline
bitfld.long 0x00 24. "HLD_OVR,IO cell hold override functionality" "0,1"
bitfld.long 0x00 8.--12. "CLOCK_SRC,Clock ('clk_fabric') and reset ('rst_fabric_n') source selection: '0': io_data_in[0]/'1'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x00 0.--7. 1. "BYPASS,Bypass of the programmable IO one bit for each IO pin: BYPASS[i] is for IO pin i"
group.long ($2+0x10)++0x03
line.long 0x00 "SYNC_CTL,Synchronization control register"
hexmask.long.byte 0x00 8.--15. 1. "CHIP_SYNC_EN,Synchronization of the chip input signals to 'clk_fabric' one bit for each input: CHIP_SYNC_EN[i] is for input i"
hexmask.long.byte 0x00 0.--7. 1. "IO_SYNC_EN,Synchronization of the IO pin input signals to 'clk_fabric' one bit for each IO pin: IO_SYNC_EN[i] is for IO pin i"
group.long ($2+0x20)++0x03
line.long 0x00 "LUT_SEL[0],LUT component input selection"
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long ($2+0x24)++0x03
line.long 0x00 "LUT_SEL[1],LUT component input selection"
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long ($2+0x28)++0x03
line.long 0x00 "LUT_SEL[2],LUT component input selection"
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long ($2+0x2C)++0x03
line.long 0x00 "LUT_SEL[3],LUT component input selection"
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long ($2+0x30)++0x03
line.long 0x00 "LUT_SEL[4],LUT component input selection"
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long ($2+0x34)++0x03
line.long 0x00 "LUT_SEL[5],LUT component input selection"
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long ($2+0x38)++0x03
line.long 0x00 "LUT_SEL[6],LUT component input selection"
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long ($2+0x3C)++0x03
line.long 0x00 "LUT_SEL[7],LUT component input selection"
bitfld.long 0x00 16.--19. "LUT_TR2_SEL,LUT input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "LUT_TR1_SEL,LUT input signal 'tr1_in' source selection: '0': LUT 0 output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "LUT_TR0_SEL,LUT input signal 'tr0_in' source selection: '0': Data unit output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long ($2+0x40)++0x03
line.long 0x00 "LUT_CTL[0],LUT component control register"
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
group.long ($2+0x44)++0x03
line.long 0x00 "LUT_CTL[1],LUT component control register"
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
group.long ($2+0x48)++0x03
line.long 0x00 "LUT_CTL[2],LUT component control register"
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
group.long ($2+0x4C)++0x03
line.long 0x00 "LUT_CTL[3],LUT component control register"
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
group.long ($2+0x50)++0x03
line.long 0x00 "LUT_CTL[4],LUT component control register"
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
group.long ($2+0x54)++0x03
line.long 0x00 "LUT_CTL[5],LUT component control register"
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
group.long ($2+0x58)++0x03
line.long 0x00 "LUT_CTL[6],LUT component control register"
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
group.long ($2+0x5C)++0x03
line.long 0x00 "LUT_CTL[7],LUT component control register"
bitfld.long 0x00 8.--9. "LUT_OPC,LUT opcode specifies the LUT operation: '0': Combinatoral output no feedback" "0,1,2,3"
hexmask.long.byte 0x00 0.--7. 1. "LUT,LUT configuration"
group.long ($2+0xC0)++0x03
line.long 0x00 "DU_SEL,Data unit component input selection"
bitfld.long 0x00 28.--29. "DU_DATA1_SEL,Data unit input data 'data1_in' source selection" "0,1,2,3"
bitfld.long 0x00 24.--25. "DU_DATA0_SEL,Data unit input data 'data0_in' source selection: '0': Constant '0'" "0,1,2,3"
newline
bitfld.long 0x00 16.--19. "DU_TR2_SEL,Data unit input signal 'tr2_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DU_TR1_SEL,Data unit input signal 'tr1_in' source selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "DU_TR0_SEL,Data unit input signal 'tr0_in' source selection: '0': Constant '0'" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long ($2+0xC4)++0x03
line.long 0x00 "DU_CTL,Data unit component control register"
bitfld.long 0x00 8.--11. "DU_OPC,Data unit opcode specifies the data unit operation: '1': INCR '2': DECR '3': INCR_WRAP '4': DECR_WRAP '5': INCR_DECR '6': INCR_DECR_WRAP '7': ROR '8': SHR '9': AND_OR '10': SHR_MAJ3 '11': SHR_EQL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "DU_SIZE,Size/width of the data unit data operands (in bits) is DU_SIZE+1" "0,1,2,3,4,5,6,7"
group.long ($2+0xF0)++0x03
line.long 0x00 "DATA,Data register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,Data unit input data source"
endif
tree.end
repeat.end
tree.end
tree "SAR (SAR ADC with Sequencer)"
tree "SAR0"
base ad:0x403A0000
group.long 0x00++0x03
line.long 0x00 "CTRL,Analog control register"
bitfld.long 0x00 31. "ENABLED,Before enabling always make sure the SAR is idle (STATUS.BUSY==0)" "0: SAR IP disabled (put analog in power,1: SAR IP enabled"
newline
bitfld.long 0x00 30. "SWITCH_DISABLE,Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control)" "0: Normal mode SAR sequencer changes switches,1: Switches disabled SAR sequencer does not enable"
newline
bitfld.long 0x00 29. "DSI_MODE,SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1)" "0: Normal mode SAR sequencer operates according to,1: CHAN_EN INJ_START_EN and channel configurations"
newline
bitfld.long 0x00 28. "DSI_SYNC_CONFIG," "0: bypass clock domain synchronisation of the DSI,1: synchronize the DSI config signals to.."
newline
bitfld.long 0x00 27. "DEEPSLEEP_ON," "0: SARMUX IP disabled off during DeepSleep power..,1: SARMUX IP remains enabled during DeepSleep.."
newline
bitfld.long 0x00 24.--25. "ICONT_LV,SARADC low power mode" "0: normal power (default) max clk_sar is 18MHz,1: 1/2 power mode max clk_sar is 9MHz,2: 1.333 power mode max clk_sar is 18MHz,3: 1/4 power mode max clk_sar is 4.5MHz"
newline
bitfld.long 0x00 20. "BOOSTPUMP_EN,SARADC internal pump" "0: disabled,1: enabled"
newline
bitfld.long 0x00 16.--19. "SPARE,Spare controls not yet designated for late changes done with an ECO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "PWR_CTRL_VREF,VREF buffer low power mode" "0: normal power (default) bypass cap max clk_sar..,1: deprecated,2: Invalid for PSoC4A otherwise 2X power no..,3: QUARTER_PWR"
newline
bitfld.long 0x00 13. "SAR_HW_CTRL_NEGVREF,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 9.--11. "NEG_SEL,SARADC internal NEG selection for Single ended conversion" "0: NEG input of SARADC is connected to..,1: NEG input of SARADC is connected to VSSA in..,2: NEG input of SARADC is connected to P1 pin of..,3: NEG input of SARADC is connected to P3 pin of..,4: NEG input of SARADC is connected to P5 pin of..,5: NEG input of SARADC is connected to P7 pin of..,6: NEG input of SARADC is connected to an ACORE..,7: NEG input of SARADC is shorted with VREF.."
newline
bitfld.long 0x00 7. "VREF_BYP_CAP_EN,VREF bypass cap enable for when VREF buffer is on" "0,1"
newline
bitfld.long 0x00 4.--6. "VREF_SEL,SARADC internal VREF selection" "0: VREF0 from PRB (VREF buffer on),1: VREF1 from PRB (VREF buffer on),2: VREF2 from PRB (VREF buffer on),3: VREF from AROUTE (VREF buffer on),4: 1.024V from BandGap (VREF buffer on),5: External precision Vref direct from a pin..,6: Vdda/2 (VREF buffer on),7: Vdda"
group.long 0x04++0x03
line.long 0x00 "SAMPLE_CTRL,Sample control register"
bitfld.long 0x00 31. "EOS_DSI_OUT_EN,Enable to output EOS_INTR to DSI" "0,1"
newline
bitfld.long 0x00 19. "DSI_SYNC_TRIGGER," "0: bypass clock domain synchronisation of the DSI,1: synchronize the DSI trigger signal to the SAR"
newline
bitfld.long 0x00 18. "DSI_TRIGGER_LEVEL," "0: DSI trigger signal is a pulse input a positive,1: DSI trigger signal is a level input as long as"
newline
bitfld.long 0x00 17. "DSI_TRIGGER_EN," "0: firmware trigger only,1: enable hardware (DSI) trigger (e.g. from TCPWM"
newline
bitfld.long 0x00 16. "CONTINUOUS," "0: Wait for next FW_TRIGGER (one shot) or hardware,1: Continuously scan enabled channels ignore.."
newline
bitfld.long 0x00 7. "AVG_SHIFT,Averaging shifting: after averaging the result is shifted right to fit in the sample resolution" "0,1"
newline
bitfld.long 0x00 4.--6. "AVG_CNT,Averaging Count for channels that have over sampling enabled (AVG_EN)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "DIFFERENTIAL_SIGNED,Output data from a differential conversion as a signed value" "0: result data is unsigned (zero extended if..,1: Default"
newline
bitfld.long 0x00 2. "SINGLE_ENDED_SIGNED,Output data from a single ended conversion as a signed value" "0: Default,1: result data is signed (sign extended if needed)"
newline
bitfld.long 0x00 1. "LEFT_ALIGN,Left align data in data[15:0] default data is right aligned in data[11:0] with sign extension to 16 bits if the channel is differential" "0,1"
newline
bitfld.long 0x00 0. "SUB_RESOLUTION,Conversion resolution for channels that have sub-resolution enabled (RESOLUTION=1) (otherwise resolution is 12-bit)" "0: 8-bit,1: 10-bit"
group.long 0x10++0x03
line.long 0x00 "SAMPLE_TIME01,Sample time specification ST0 and ST1"
hexmask.long.word 0x00 16.--25. 1. "SAMPLE_TIME1,Sample time1"
newline
hexmask.long.word 0x00 0.--9. 1. "SAMPLE_TIME0,Sample time0 (aperture) in ADC clock cycles"
group.long 0x14++0x03
line.long 0x00 "SAMPLE_TIME23,Sample time specification ST2 and ST3"
hexmask.long.word 0x00 16.--25. 1. "SAMPLE_TIME3,Sample time3"
newline
hexmask.long.word 0x00 0.--9. 1. "SAMPLE_TIME2,Sample time2"
group.long 0x18++0x03
line.long 0x00 "RANGE_THRES,Global range detect threshold register"
hexmask.long.word 0x00 16.--31. 1. "RANGE_HIGH,High threshold for range detect"
newline
hexmask.long.word 0x00 0.--15. 1. "RANGE_LOW,Low threshold for range detect"
group.long 0x1C++0x03
line.long 0x00 "RANGE_COND,Global range detect mode register"
bitfld.long 0x00 30.--31. "RANGE_COND,Range condition select" "0: result < RANGE_LOW,1: RANGE_LOW <= result < RANGE_HIGH,2: RANGE_HIGH <= result,3: result < RANGE_LOW || RANGE_HIGH <= result"
group.long 0x20++0x03
line.long 0x00 "CHAN_EN,Enable bits for the channels"
abitfld.long 0x00 0.--15. "CHAN_EN,Channel enable" "0x0000=0: the corresponding channel is disabled,0x0001=1: the corresponding channel is enabled.."
group.long 0x24++0x03
line.long 0x00 "START_CTRL,Start control register (firmware trigger)"
bitfld.long 0x00 0. "FW_TRIGGER,When firmware writes a 1 here it will trigger the next scan of enabled channels hardware clears this bit when the scan started with this trigger is completed" "0,1"
group.long 0x30++0x03
line.long 0x00 "DFT_CTRL,DFT control register"
bitfld.long 0x00 31. "ADFT_OVERRIDE,During deepsleep/ hibernate mode keep SARMUX active i.e" "0,1"
newline
bitfld.long 0x00 29. "DCEN,Delay Control Enable for latch" "0: doubles the latch enable time,1: normal latch enable time (default)"
newline
bitfld.long 0x00 28. "EN_CSEL_DFT,Mux select signal for DAC control" "0,1"
newline
bitfld.long 0x00 24.--27. "SEL_CSEL_DFT,Usage" "?,1: DFT bits for DAC array Usage,2: For [0]=1 (when dcen=0),?..."
newline
bitfld.long 0x00 20.--22. "DFT_OUTC,DFT control for preamp outputs" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "DFT_INC,DFT control for preamp inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "HIZ,DFT control for getting higher input impedance must be 1 (0 is deprecated)" "0,1"
newline
bitfld.long 0x00 0. "DLY_INC,DFT control: Control for delay circuits on sampling phase =1 doubes the non-overlap delay" "0,1"
repeat 16. (increment 0 1) (increment 0 0x4)
group.long ($2+0x80)++0x03
line.long 0x00 "CHAN_CONFIG[$1],Channel configuration register $1"
bitfld.long 0x00 31. "DSI_OUT_EN,DSI data output enable for this channel" "0: the conversion result for this channel is only,1: the conversion result for this channel is.."
newline
bitfld.long 0x00 12.--13. "SAMPLE_TIME_SEL,Sample time select: select which of the 4 global sample times to use for this channel" "0,1,2,3"
newline
bitfld.long 0x00 10. "AVG_EN,Averaging enable for this channel" "0,1"
newline
bitfld.long 0x00 9. "RESOLUTION,Resolution for this channel" "0: The maximum resolution is used for this..,1: The resolution specified by SUB_RESOLUTION in.."
newline
bitfld.long 0x00 8. "DIFFERENTIAL_EN,Differential enable for this channel" "0: The voltage on the addressed pin is measured,1: The differential voltage on the addressed pin"
newline
bitfld.long 0x00 4.--6. "PORT_ADDR,Address of the port that contains the pin to be sampled by this channel" "0: SARMUX pins,1: CTB0,2: CTB1,3: CTB2,4: CTB3,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)"
newline
bitfld.long 0x00 0.--2. "PIN_ADDR,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x100)++0x03
line.long 0x00 "CHAN_WORK[$1],Channel working data register $1"
bitfld.long 0x00 31. "CHAN_WORK_VALID_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x180)++0x03
line.long 0x00 "CHAN_RESULT[$1],Channel result data register $1"
bitfld.long 0x00 31. "CHAN_RESULT_VALID_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_VALID register" "0,1"
newline
bitfld.long 0x00 30. "RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_RANGE_INTR register" "0,1"
newline
bitfld.long 0x00 29. "SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_SATURATE_INTR register" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
repeat.end
rgroup.long 0x200++0x03
line.long 0x00 "CHAN_WORK_VALID,Channel working data register valid bits"
hexmask.long.word 0x00 0.--15. 1. "CHAN_WORK_VALID,If set the corresponding WORK data is valid i.e"
rgroup.long 0x204++0x03
line.long 0x00 "CHAN_RESULT_VALID,Channel result data register valid bits"
hexmask.long.word 0x00 0.--15. 1. "CHAN_RESULT_VALID,If set the corresponding RESULT data is valid i.e"
rgroup.long 0x208++0x03
line.long 0x00 "STATUS,Current status of internal SAR registers (mostly for debug)"
bitfld.long 0x00 31. "BUSY,If high then the SAR is busy with a conversion" "0,1"
newline
bitfld.long 0x00 30. "SW_VREF_NEG,the current switch status including DSI and sequencer controls of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL)" "0,1"
newline
bitfld.long 0x00 0.--4. "CUR_CHAN,current channel being sampled (channel 16 indicates the injection channel) only valid if BUSY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x20C++0x03
line.long 0x00 "AVG_STAT,Current averaging status (for debug)"
hexmask.long.byte 0x00 24.--31. 1. "CUR_AVG_CNT,the current value of the averaging counter"
newline
hexmask.long.tbyte 0x00 0.--19. 1. "CUR_AVG_ACCU,the current value of the averaging accumulator"
group.long 0x210++0x03
line.long 0x00 "INTR,Interrupt request register"
bitfld.long 0x00 7. "INJ_COLLISION_INTR,Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 && INJ_TAILGATING==0) while the SAR is BUSY" "0,1"
newline
bitfld.long 0x00 6. "INJ_RANGE_INTR,Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers" "0,1"
newline
bitfld.long 0x00 5. "INJ_SATURATE_INTR,Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF (for 12-bit resolution) this is an indication that the ADC likely saturated" "0,1"
newline
bitfld.long 0x00 4. "INJ_EOC_INTR,Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used)" "0,1"
newline
bitfld.long 0x00 3. "DSI_COLLISION_INTR,DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY" "0,1"
newline
bitfld.long 0x00 2. "FW_COLLISION_INTR,Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY" "0,1"
newline
bitfld.long 0x00 1. "OVERFLOW_INTR,Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware" "0,1"
newline
bitfld.long 0x00 0. "EOS_INTR,End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels" "0,1"
group.long 0x214++0x03
line.long 0x00 "INTR_SET,Interrupt set request register"
bitfld.long 0x00 7. "INJ_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "INJ_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "INJ_SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "INJ_EOC_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 3. "DSI_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "FW_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "EOS_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0x218++0x03
line.long 0x00 "INTR_MASK,Interrupt mask register"
bitfld.long 0x00 7. "INJ_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "INJ_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "INJ_SATURATE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "INJ_EOC_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 3. "DSI_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "FW_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "EOS_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0x21C++0x03
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
bitfld.long 0x00 7. "INJ_COLLISION_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 6. "INJ_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 5. "INJ_SATURATE_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 4. "INJ_EOC_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 3. "DSI_COLLISION_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 2. "FW_COLLISION_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 0. "EOS_MASKED,Logical and of corresponding request and mask bits" "0,1"
group.long 0x220++0x03
line.long 0x00 "SATURATE_INTR,Saturate interrupt request register"
hexmask.long.word 0x00 0.--15. 1. "SATURATE_INTR,Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF (for 12-bit resolution) this is an indication that the ADC likely saturated"
group.long 0x224++0x03
line.long 0x00 "SATURATE_INTR_SET,Saturate interrupt set request register"
hexmask.long.word 0x00 0.--15. 1. "SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register"
group.long 0x228++0x03
line.long 0x00 "SATURATE_INTR_MASK,Saturate interrupt mask register"
hexmask.long.word 0x00 0.--15. 1. "SATURATE_MASK,Mask bit for corresponding bit in interrupt request register"
rgroup.long 0x22C++0x03
line.long 0x00 "SATURATE_INTR_MASKED,Saturate interrupt masked request register"
hexmask.long.word 0x00 0.--15. 1. "SATURATE_MASKED,Logical and of corresponding request and mask bits"
group.long 0x230++0x03
line.long 0x00 "RANGE_INTR,Range detect interrupt request register"
hexmask.long.word 0x00 0.--15. 1. "RANGE_INTR,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers"
group.long 0x234++0x03
line.long 0x00 "RANGE_INTR_SET,Range detect interrupt set request register"
hexmask.long.word 0x00 0.--15. 1. "RANGE_SET,Write with '1' to set corresponding bit in interrupt request register"
group.long 0x238++0x03
line.long 0x00 "RANGE_INTR_MASK,Range detect interrupt mask register"
hexmask.long.word 0x00 0.--15. 1. "RANGE_MASK,Mask bit for corresponding bit in interrupt request register"
rgroup.long 0x23C++0x03
line.long 0x00 "RANGE_INTR_MASKED,Range interrupt masked request register"
hexmask.long.word 0x00 0.--15. 1. "RANGE_MASKED,Logical and of corresponding request and mask bits"
rgroup.long 0x240++0x03
line.long 0x00 "INTR_CAUSE,Interrupt cause register"
bitfld.long 0x00 31. "RANGE_MASKED_RED,Reduction OR of all SAR_RANGE_INTR_MASKED bits" "0,1"
newline
bitfld.long 0x00 30. "SATURATE_MASKED_RED,Reduction OR of all SAR_SATURATION_INTR_MASKED bits" "0,1"
newline
bitfld.long 0x00 7. "INJ_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 6. "INJ_RANGE_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 5. "INJ_SATURATE_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 4. "INJ_EOC_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 3. "DSI_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 2. "FW_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 1. "OVERFLOW_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 0. "EOS_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
group.long 0x280++0x03
line.long 0x00 "INJ_CHAN_CONFIG,Injection channel configuration register"
bitfld.long 0x00 31. "INJ_START_EN,Set by firmware to enable the injection channel" "0,1"
newline
bitfld.long 0x00 30. "INJ_TAILGATING,Injection channel tailgating" "0: no tailgating for this channel SAR is,1: injection channel tailgating"
newline
bitfld.long 0x00 12.--13. "INJ_SAMPLE_TIME_SEL,Injection sample time select: select which of the 4 global sample times to use for this channel" "0,1,2,3"
newline
bitfld.long 0x00 10. "INJ_AVG_EN,Averaging enable for this channel" "0,1"
newline
bitfld.long 0x00 9. "INJ_RESOLUTION,Resolution for this channel" "0: 12-bit resolution is used for this channel,1: The resolution specified by SUB_RESOLUTION in.."
newline
bitfld.long 0x00 8. "INJ_DIFFERENTIAL_EN,Differential enable for this channel" "0: The voltage on the addressed pin is measured,1: The differential voltage on the addressed pin"
newline
bitfld.long 0x00 4.--6. "INJ_PORT_ADDR,Address of the port that contains the pin to be sampled by this channel" "0: SARMUX pins,1: CTB0,2: CTB1,3: CTB2,4: CTB3,?,6: AROUTE virtual port,7: SARMUX virtual port"
newline
bitfld.long 0x00 0.--2. "INJ_PIN_ADDR,Address of the pin to be sampled by this injection channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x290++0x03
line.long 0x00 "INJ_RESULT,Injection channel result register"
bitfld.long 0x00 31. "INJ_EOC_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
newline
bitfld.long 0x00 30. "INJ_RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
newline
bitfld.long 0x00 29. "INJ_SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
newline
bitfld.long 0x00 28. "INJ_COLLISION_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "INJ_RESULT,SAR conversion result of the channel"
group.long 0x300++0x03
line.long 0x00 "MUX_SWITCH0,SARMUX Firmware switch controls"
bitfld.long 0x00 29. "MUX_FW_P7_COREIO3,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 28. "MUX_FW_P6_COREIO2,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 27. "MUX_FW_P5_COREIO1,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 26. "MUX_FW_P4_COREIO0,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 25. "MUX_FW_SARBUS1_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 24. "MUX_FW_SARBUS0_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 23. "MUX_FW_SARBUS1_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 22. "MUX_FW_SARBUS0_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 21. "MUX_FW_AMUXBUSB_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 20. "MUX_FW_AMUXBUSA_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 19. "MUX_FW_AMUXBUSB_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 18. "MUX_FW_AMUXBUSA_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 17. "MUX_FW_TEMP_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 16. "MUX_FW_VSSA_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 15. "MUX_FW_P7_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 14. "MUX_FW_P6_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 13. "MUX_FW_P5_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 12. "MUX_FW_P4_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 11. "MUX_FW_P3_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 10. "MUX_FW_P2_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 9. "MUX_FW_P1_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 8. "MUX_FW_P0_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 7. "MUX_FW_P7_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 6. "MUX_FW_P6_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 5. "MUX_FW_P5_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 4. "MUX_FW_P4_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 3. "MUX_FW_P3_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 2. "MUX_FW_P2_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 1. "MUX_FW_P1_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 0. "MUX_FW_P0_VPLUS,Firmware control" "0: open,1: close"
group.long 0x304++0x03
line.long 0x00 "MUX_SWITCH_CLEAR0,SARMUX Firmware switch control clear"
bitfld.long 0x00 29. "MUX_FW_P7_COREIO3,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 28. "MUX_FW_P6_COREIO2,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 27. "MUX_FW_P5_COREIO1,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 26. "MUX_FW_P4_COREIO0,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 25. "MUX_FW_SARBUS1_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 24. "MUX_FW_SARBUS0_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 23. "MUX_FW_SARBUS1_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 22. "MUX_FW_SARBUS0_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 21. "MUX_FW_AMUXBUSB_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 20. "MUX_FW_AMUXBUSA_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 19. "MUX_FW_AMUXBUSB_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 18. "MUX_FW_AMUXBUSA_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 17. "MUX_FW_TEMP_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 16. "MUX_FW_VSSA_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 15. "MUX_FW_P7_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 14. "MUX_FW_P6_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 13. "MUX_FW_P5_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 12. "MUX_FW_P4_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 11. "MUX_FW_P3_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 10. "MUX_FW_P2_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 9. "MUX_FW_P1_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 8. "MUX_FW_P0_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 7. "MUX_FW_P7_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 6. "MUX_FW_P6_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 5. "MUX_FW_P5_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 4. "MUX_FW_P4_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 3. "MUX_FW_P3_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 2. "MUX_FW_P2_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 1. "MUX_FW_P1_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 0. "MUX_FW_P0_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
group.long 0x308++0x03
line.long 0x00 "MUX_SWITCH1,SARMUX Firmware switch controls"
bitfld.long 0x00 3. "MUX_FW_ADFT1_SARBUS1,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 2. "MUX_FW_ADFT0_SARBUS0,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 1. "MUX_FW_P5_DFT_INM,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 0. "MUX_FW_P4_DFT_INP,Firmware control" "0: open,1: close"
group.long 0x30C++0x03
line.long 0x00 "MUX_SWITCH_CLEAR1,SARMUX Firmware switch control clear"
bitfld.long 0x00 3. "MUX_FW_ADFT1_SARBUS1,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
newline
bitfld.long 0x00 2. "MUX_FW_ADFT0_SARBUS0,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
newline
bitfld.long 0x00 1. "MUX_FW_P5_DFT_INM,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
newline
bitfld.long 0x00 0. "MUX_FW_P4_DFT_INP,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
group.long 0x340++0x03
line.long 0x00 "MUX_SWITCH_HW_CTRL,SARMUX switch hardware control"
bitfld.long 0x00 23. "MUX_HW_CTRL_SARBUS1,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 22. "MUX_HW_CTRL_SARBUS0,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 19. "MUX_HW_CTRL_AMUXBUSB,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 18. "MUX_HW_CTRL_AMUXBUSA,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 17. "MUX_HW_CTRL_TEMP,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 16. "MUX_HW_CTRL_VSSA,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 7. "MUX_HW_CTRL_P7,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 6. "MUX_HW_CTRL_P6,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 5. "MUX_HW_CTRL_P5,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 4. "MUX_HW_CTRL_P4,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 3. "MUX_HW_CTRL_P3,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 2. "MUX_HW_CTRL_P2,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 1. "MUX_HW_CTRL_P1,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 0. "MUX_HW_CTRL_P0,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
rgroup.long 0x348++0x03
line.long 0x00 "MUX_SWITCH_STATUS,SARMUX switch status"
bitfld.long 0x00 25. "MUX_FW_SARBUS1_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 24. "MUX_FW_SARBUS0_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 23. "MUX_FW_SARBUS1_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 22. "MUX_FW_SARBUS0_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 21. "MUX_FW_AMUXBUSB_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 20. "MUX_FW_AMUXBUSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 19. "MUX_FW_AMUXBUSB_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 18. "MUX_FW_AMUXBUSA_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 17. "MUX_FW_TEMP_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 16. "MUX_FW_VSSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 15. "MUX_FW_P7_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 14. "MUX_FW_P6_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 13. "MUX_FW_P5_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 12. "MUX_FW_P4_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 11. "MUX_FW_P3_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 10. "MUX_FW_P2_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 9. "MUX_FW_P1_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 8. "MUX_FW_P0_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 7. "MUX_FW_P7_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 6. "MUX_FW_P6_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 5. "MUX_FW_P5_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 4. "MUX_FW_P4_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 3. "MUX_FW_P3_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 2. "MUX_FW_P2_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 1. "MUX_FW_P1_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 0. "MUX_FW_P0_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
group.long 0x380++0x03
line.long 0x00 "PUMP_CTRL,Switch pump control"
bitfld.long 0x00 31. "ENABLED," "0,1"
newline
bitfld.long 0x00 0. "CLOCK_SEL,Clock select" "0: external clock,1: internal clock (deprecated)"
group.long 0xF00++0x03
line.long 0x00 "ANA_TRIM,Analog trim register"
bitfld.long 0x00 3. "TRIMUNIT,Attenuation cap trimming" "0,1"
newline
bitfld.long 0x00 0.--2. "CAP_TRIM,Attenuation cap trimming" "0,1,2,3,4,5,6,7"
group.long 0xF04++0x03
line.long 0x00 "WOUNDING,SAR wounding register"
bitfld.long 0x00 0.--1. "WOUND_RESOLUTION,Maximum SAR resolution allowed" "0: unwounded,1: wounded,2: wounded,3: wounded"
tree.end
sif cpuis("CY8C4148*")
tree "SAR1"
base ad:0x404A0000
group.long 0x00++0x03
line.long 0x00 "CTRL,Analog control register"
bitfld.long 0x00 31. "ENABLED,Before enabling always make sure the SAR is idle (STATUS.BUSY==0)" "0: SAR IP disabled (put analog in power,1: SAR IP enabled"
newline
bitfld.long 0x00 30. "SWITCH_DISABLE,Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control)" "0: Normal mode SAR sequencer changes switches,1: Switches disabled SAR sequencer does not enable"
newline
bitfld.long 0x00 29. "DSI_MODE,SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1)" "0: Normal mode SAR sequencer operates according to,1: CHAN_EN INJ_START_EN and channel configurations"
newline
bitfld.long 0x00 28. "DSI_SYNC_CONFIG," "0: bypass clock domain synchronisation of the DSI,1: synchronize the DSI config signals to.."
newline
bitfld.long 0x00 27. "DEEPSLEEP_ON," "0: SARMUX IP disabled off during DeepSleep power..,1: SARMUX IP remains enabled during DeepSleep.."
newline
bitfld.long 0x00 24.--25. "ICONT_LV,SARADC low power mode" "0: normal power (default) max clk_sar is 18MHz,1: 1/2 power mode max clk_sar is 9MHz,2: 1.333 power mode max clk_sar is 18MHz,3: 1/4 power mode max clk_sar is 4.5MHz"
newline
bitfld.long 0x00 20. "BOOSTPUMP_EN,SARADC internal pump" "0: disabled,1: enabled"
newline
bitfld.long 0x00 16.--19. "SPARE,Spare controls not yet designated for late changes done with an ECO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "PWR_CTRL_VREF,VREF buffer low power mode" "0: normal power (default) bypass cap max clk_sar..,1: deprecated,2: Invalid for PSoC4A otherwise 2X power no..,3: QUARTER_PWR"
newline
bitfld.long 0x00 13. "SAR_HW_CTRL_NEGVREF,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 9.--11. "NEG_SEL,SARADC internal NEG selection for Single ended conversion" "0: NEG input of SARADC is connected to..,1: NEG input of SARADC is connected to VSSA in..,2: NEG input of SARADC is connected to P1 pin of..,3: NEG input of SARADC is connected to P3 pin of..,4: NEG input of SARADC is connected to P5 pin of..,5: NEG input of SARADC is connected to P7 pin of..,6: NEG input of SARADC is connected to an ACORE..,7: NEG input of SARADC is shorted with VREF.."
newline
bitfld.long 0x00 7. "VREF_BYP_CAP_EN,VREF bypass cap enable for when VREF buffer is on" "0,1"
newline
bitfld.long 0x00 4.--6. "VREF_SEL,SARADC internal VREF selection" "0: VREF0 from PRB (VREF buffer on),1: VREF1 from PRB (VREF buffer on),2: VREF2 from PRB (VREF buffer on),3: VREF from AROUTE (VREF buffer on),4: 1.024V from BandGap (VREF buffer on),5: External precision Vref direct from a pin..,6: Vdda/2 (VREF buffer on),7: Vdda"
group.long 0x04++0x03
line.long 0x00 "SAMPLE_CTRL,Sample control register"
bitfld.long 0x00 31. "EOS_DSI_OUT_EN,Enable to output EOS_INTR to DSI" "0,1"
newline
bitfld.long 0x00 19. "DSI_SYNC_TRIGGER," "0: bypass clock domain synchronisation of the DSI,1: synchronize the DSI trigger signal to the SAR"
newline
bitfld.long 0x00 18. "DSI_TRIGGER_LEVEL," "0: DSI trigger signal is a pulse input a positive,1: DSI trigger signal is a level input as long as"
newline
bitfld.long 0x00 17. "DSI_TRIGGER_EN," "0: firmware trigger only,1: enable hardware (DSI) trigger (e.g. from TCPWM"
newline
bitfld.long 0x00 16. "CONTINUOUS," "0: Wait for next FW_TRIGGER (one shot) or hardware,1: Continuously scan enabled channels ignore.."
newline
bitfld.long 0x00 7. "AVG_SHIFT,Averaging shifting: after averaging the result is shifted right to fit in the sample resolution" "0,1"
newline
bitfld.long 0x00 4.--6. "AVG_CNT,Averaging Count for channels that have over sampling enabled (AVG_EN)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 3. "DIFFERENTIAL_SIGNED,Output data from a differential conversion as a signed value" "0: result data is unsigned (zero extended if..,1: Default"
newline
bitfld.long 0x00 2. "SINGLE_ENDED_SIGNED,Output data from a single ended conversion as a signed value" "0: Default,1: result data is signed (sign extended if needed)"
newline
bitfld.long 0x00 1. "LEFT_ALIGN,Left align data in data[15:0] default data is right aligned in data[11:0] with sign extension to 16 bits if the channel is differential" "0,1"
newline
bitfld.long 0x00 0. "SUB_RESOLUTION,Conversion resolution for channels that have sub-resolution enabled (RESOLUTION=1) (otherwise resolution is 12-bit)" "0: 8-bit,1: 10-bit"
group.long 0x10++0x03
line.long 0x00 "SAMPLE_TIME01,Sample time specification ST0 and ST1"
hexmask.long.word 0x00 16.--25. 1. "SAMPLE_TIME1,Sample time1"
newline
hexmask.long.word 0x00 0.--9. 1. "SAMPLE_TIME0,Sample time0 (aperture) in ADC clock cycles"
group.long 0x14++0x03
line.long 0x00 "SAMPLE_TIME23,Sample time specification ST2 and ST3"
hexmask.long.word 0x00 16.--25. 1. "SAMPLE_TIME3,Sample time3"
newline
hexmask.long.word 0x00 0.--9. 1. "SAMPLE_TIME2,Sample time2"
group.long 0x18++0x03
line.long 0x00 "RANGE_THRES,Global range detect threshold register"
hexmask.long.word 0x00 16.--31. 1. "RANGE_HIGH,High threshold for range detect"
newline
hexmask.long.word 0x00 0.--15. 1. "RANGE_LOW,Low threshold for range detect"
group.long 0x1C++0x03
line.long 0x00 "RANGE_COND,Global range detect mode register"
bitfld.long 0x00 30.--31. "RANGE_COND,Range condition select" "0: result < RANGE_LOW,1: RANGE_LOW <= result < RANGE_HIGH,2: RANGE_HIGH <= result,3: result < RANGE_LOW || RANGE_HIGH <= result"
group.long 0x20++0x03
line.long 0x00 "CHAN_EN,Enable bits for the channels"
abitfld.long 0x00 0.--15. "CHAN_EN,Channel enable" "0x0000=0: the corresponding channel is disabled,0x0001=1: the corresponding channel is enabled.."
group.long 0x24++0x03
line.long 0x00 "START_CTRL,Start control register (firmware trigger)"
bitfld.long 0x00 0. "FW_TRIGGER,When firmware writes a 1 here it will trigger the next scan of enabled channels hardware clears this bit when the scan started with this trigger is completed" "0,1"
group.long 0x30++0x03
line.long 0x00 "DFT_CTRL,DFT control register"
bitfld.long 0x00 31. "ADFT_OVERRIDE,During deepsleep/ hibernate mode keep SARMUX active i.e" "0,1"
newline
bitfld.long 0x00 29. "DCEN,Delay Control Enable for latch" "0: doubles the latch enable time,1: normal latch enable time (default)"
newline
bitfld.long 0x00 28. "EN_CSEL_DFT,Mux select signal for DAC control" "0,1"
newline
bitfld.long 0x00 24.--27. "SEL_CSEL_DFT,Usage" "?,1: DFT bits for DAC array Usage,2: For [0]=1 (when dcen=0),?..."
newline
bitfld.long 0x00 20.--22. "DFT_OUTC,DFT control for preamp outputs" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--19. "DFT_INC,DFT control for preamp inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1. "HIZ,DFT control for getting higher input impedance must be 1 (0 is deprecated)" "0,1"
newline
bitfld.long 0x00 0. "DLY_INC,DFT control: Control for delay circuits on sampling phase =1 doubes the non-overlap delay" "0,1"
repeat 16. (increment 0 1) (increment 0 0x4)
group.long ($2+0x80)++0x03
line.long 0x00 "CHAN_CONFIG[$1],Channel configuration register $1"
bitfld.long 0x00 31. "DSI_OUT_EN,DSI data output enable for this channel" "0: the conversion result for this channel is only,1: the conversion result for this channel is.."
newline
bitfld.long 0x00 12.--13. "SAMPLE_TIME_SEL,Sample time select: select which of the 4 global sample times to use for this channel" "0,1,2,3"
newline
bitfld.long 0x00 10. "AVG_EN,Averaging enable for this channel" "0,1"
newline
bitfld.long 0x00 9. "RESOLUTION,Resolution for this channel" "0: The maximum resolution is used for this..,1: The resolution specified by SUB_RESOLUTION in.."
newline
bitfld.long 0x00 8. "DIFFERENTIAL_EN,Differential enable for this channel" "0: The voltage on the addressed pin is measured,1: The differential voltage on the addressed pin"
newline
bitfld.long 0x00 4.--6. "PORT_ADDR,Address of the port that contains the pin to be sampled by this channel" "0: SARMUX pins,1: CTB0,2: CTB1,3: CTB2,4: CTB3,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)"
newline
bitfld.long 0x00 0.--2. "PIN_ADDR,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x100)++0x03
line.long 0x00 "CHAN_WORK[$1],Channel working data register $1"
bitfld.long 0x00 31. "CHAN_WORK_VALID_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel"
repeat.end
repeat 16. (increment 0 1) (increment 0 0x04)
rgroup.long ($2+0x180)++0x03
line.long 0x00 "CHAN_RESULT[$1],Channel result data register $1"
bitfld.long 0x00 31. "CHAN_RESULT_VALID_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_VALID register" "0,1"
newline
bitfld.long 0x00 30. "RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_RANGE_INTR register" "0,1"
newline
bitfld.long 0x00 29. "SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_SATURATE_INTR register" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel"
repeat.end
rgroup.long 0x200++0x03
line.long 0x00 "CHAN_WORK_VALID,Channel working data register valid bits"
hexmask.long.word 0x00 0.--15. 1. "CHAN_WORK_VALID,If set the corresponding WORK data is valid i.e"
rgroup.long 0x204++0x03
line.long 0x00 "CHAN_RESULT_VALID,Channel result data register valid bits"
hexmask.long.word 0x00 0.--15. 1. "CHAN_RESULT_VALID,If set the corresponding RESULT data is valid i.e"
rgroup.long 0x208++0x03
line.long 0x00 "STATUS,Current status of internal SAR registers (mostly for debug)"
bitfld.long 0x00 31. "BUSY,If high then the SAR is busy with a conversion" "0,1"
newline
bitfld.long 0x00 30. "SW_VREF_NEG,the current switch status including DSI and sequencer controls of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL)" "0,1"
newline
bitfld.long 0x00 0.--4. "CUR_CHAN,current channel being sampled (channel 16 indicates the injection channel) only valid if BUSY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x20C++0x03
line.long 0x00 "AVG_STAT,Current averaging status (for debug)"
hexmask.long.byte 0x00 24.--31. 1. "CUR_AVG_CNT,the current value of the averaging counter"
newline
hexmask.long.tbyte 0x00 0.--19. 1. "CUR_AVG_ACCU,the current value of the averaging accumulator"
group.long 0x210++0x03
line.long 0x00 "INTR,Interrupt request register"
bitfld.long 0x00 7. "INJ_COLLISION_INTR,Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 && INJ_TAILGATING==0) while the SAR is BUSY" "0,1"
newline
bitfld.long 0x00 6. "INJ_RANGE_INTR,Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers" "0,1"
newline
bitfld.long 0x00 5. "INJ_SATURATE_INTR,Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF (for 12-bit resolution) this is an indication that the ADC likely saturated" "0,1"
newline
bitfld.long 0x00 4. "INJ_EOC_INTR,Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used)" "0,1"
newline
bitfld.long 0x00 3. "DSI_COLLISION_INTR,DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY" "0,1"
newline
bitfld.long 0x00 2. "FW_COLLISION_INTR,Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY" "0,1"
newline
bitfld.long 0x00 1. "OVERFLOW_INTR,Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware" "0,1"
newline
bitfld.long 0x00 0. "EOS_INTR,End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels" "0,1"
group.long 0x214++0x03
line.long 0x00 "INTR_SET,Interrupt set request register"
bitfld.long 0x00 7. "INJ_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "INJ_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "INJ_SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "INJ_EOC_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 3. "DSI_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "FW_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "EOS_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0x218++0x03
line.long 0x00 "INTR_MASK,Interrupt mask register"
bitfld.long 0x00 7. "INJ_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "INJ_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "INJ_SATURATE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "INJ_EOC_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 3. "DSI_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "FW_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "EOS_MASK,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0x21C++0x03
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
bitfld.long 0x00 7. "INJ_COLLISION_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 6. "INJ_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 5. "INJ_SATURATE_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 4. "INJ_EOC_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 3. "DSI_COLLISION_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 2. "FW_COLLISION_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 0. "EOS_MASKED,Logical and of corresponding request and mask bits" "0,1"
group.long 0x220++0x03
line.long 0x00 "SATURATE_INTR,Saturate interrupt request register"
hexmask.long.word 0x00 0.--15. 1. "SATURATE_INTR,Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF (for 12-bit resolution) this is an indication that the ADC likely saturated"
group.long 0x224++0x03
line.long 0x00 "SATURATE_INTR_SET,Saturate interrupt set request register"
hexmask.long.word 0x00 0.--15. 1. "SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register"
group.long 0x228++0x03
line.long 0x00 "SATURATE_INTR_MASK,Saturate interrupt mask register"
hexmask.long.word 0x00 0.--15. 1. "SATURATE_MASK,Mask bit for corresponding bit in interrupt request register"
rgroup.long 0x22C++0x03
line.long 0x00 "SATURATE_INTR_MASKED,Saturate interrupt masked request register"
hexmask.long.word 0x00 0.--15. 1. "SATURATE_MASKED,Logical and of corresponding request and mask bits"
group.long 0x230++0x03
line.long 0x00 "RANGE_INTR,Range detect interrupt request register"
hexmask.long.word 0x00 0.--15. 1. "RANGE_INTR,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers"
group.long 0x234++0x03
line.long 0x00 "RANGE_INTR_SET,Range detect interrupt set request register"
hexmask.long.word 0x00 0.--15. 1. "RANGE_SET,Write with '1' to set corresponding bit in interrupt request register"
group.long 0x238++0x03
line.long 0x00 "RANGE_INTR_MASK,Range detect interrupt mask register"
hexmask.long.word 0x00 0.--15. 1. "RANGE_MASK,Mask bit for corresponding bit in interrupt request register"
rgroup.long 0x23C++0x03
line.long 0x00 "RANGE_INTR_MASKED,Range interrupt masked request register"
hexmask.long.word 0x00 0.--15. 1. "RANGE_MASKED,Logical and of corresponding request and mask bits"
rgroup.long 0x240++0x03
line.long 0x00 "INTR_CAUSE,Interrupt cause register"
bitfld.long 0x00 31. "RANGE_MASKED_RED,Reduction OR of all SAR_RANGE_INTR_MASKED bits" "0,1"
newline
bitfld.long 0x00 30. "SATURATE_MASKED_RED,Reduction OR of all SAR_SATURATION_INTR_MASKED bits" "0,1"
newline
bitfld.long 0x00 7. "INJ_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 6. "INJ_RANGE_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 5. "INJ_SATURATE_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 4. "INJ_EOC_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 3. "DSI_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 2. "FW_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 1. "OVERFLOW_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
newline
bitfld.long 0x00 0. "EOS_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1"
group.long 0x280++0x03
line.long 0x00 "INJ_CHAN_CONFIG,Injection channel configuration register"
bitfld.long 0x00 31. "INJ_START_EN,Set by firmware to enable the injection channel" "0,1"
newline
bitfld.long 0x00 30. "INJ_TAILGATING,Injection channel tailgating" "0: no tailgating for this channel SAR is,1: injection channel tailgating"
newline
bitfld.long 0x00 12.--13. "INJ_SAMPLE_TIME_SEL,Injection sample time select: select which of the 4 global sample times to use for this channel" "0,1,2,3"
newline
bitfld.long 0x00 10. "INJ_AVG_EN,Averaging enable for this channel" "0,1"
newline
bitfld.long 0x00 9. "INJ_RESOLUTION,Resolution for this channel" "0: 12-bit resolution is used for this channel,1: The resolution specified by SUB_RESOLUTION in.."
newline
bitfld.long 0x00 8. "INJ_DIFFERENTIAL_EN,Differential enable for this channel" "0: The voltage on the addressed pin is measured,1: The differential voltage on the addressed pin"
newline
bitfld.long 0x00 4.--6. "INJ_PORT_ADDR,Address of the port that contains the pin to be sampled by this channel" "0: SARMUX pins,1: CTB0,2: CTB1,3: CTB2,4: CTB3,?,6: AROUTE virtual port,7: SARMUX virtual port"
newline
bitfld.long 0x00 0.--2. "INJ_PIN_ADDR,Address of the pin to be sampled by this injection channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x290++0x03
line.long 0x00 "INJ_RESULT,Injection channel result register"
bitfld.long 0x00 31. "INJ_EOC_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
newline
bitfld.long 0x00 30. "INJ_RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
newline
bitfld.long 0x00 29. "INJ_SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
newline
bitfld.long 0x00 28. "INJ_COLLISION_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1"
newline
hexmask.long.word 0x00 0.--15. 1. "INJ_RESULT,SAR conversion result of the channel"
group.long 0x300++0x03
line.long 0x00 "MUX_SWITCH0,SARMUX Firmware switch controls"
bitfld.long 0x00 29. "MUX_FW_P7_COREIO3,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 28. "MUX_FW_P6_COREIO2,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 27. "MUX_FW_P5_COREIO1,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 26. "MUX_FW_P4_COREIO0,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 25. "MUX_FW_SARBUS1_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 24. "MUX_FW_SARBUS0_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 23. "MUX_FW_SARBUS1_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 22. "MUX_FW_SARBUS0_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 21. "MUX_FW_AMUXBUSB_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 20. "MUX_FW_AMUXBUSA_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 19. "MUX_FW_AMUXBUSB_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 18. "MUX_FW_AMUXBUSA_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 17. "MUX_FW_TEMP_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 16. "MUX_FW_VSSA_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 15. "MUX_FW_P7_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 14. "MUX_FW_P6_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 13. "MUX_FW_P5_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 12. "MUX_FW_P4_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 11. "MUX_FW_P3_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 10. "MUX_FW_P2_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 9. "MUX_FW_P1_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 8. "MUX_FW_P0_VMINUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 7. "MUX_FW_P7_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 6. "MUX_FW_P6_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 5. "MUX_FW_P5_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 4. "MUX_FW_P4_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 3. "MUX_FW_P3_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 2. "MUX_FW_P2_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 1. "MUX_FW_P1_VPLUS,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 0. "MUX_FW_P0_VPLUS,Firmware control" "0: open,1: close"
group.long 0x304++0x03
line.long 0x00 "MUX_SWITCH_CLEAR0,SARMUX Firmware switch control clear"
bitfld.long 0x00 29. "MUX_FW_P7_COREIO3,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 28. "MUX_FW_P6_COREIO2,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 27. "MUX_FW_P5_COREIO1,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 26. "MUX_FW_P4_COREIO0,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 25. "MUX_FW_SARBUS1_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 24. "MUX_FW_SARBUS0_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 23. "MUX_FW_SARBUS1_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 22. "MUX_FW_SARBUS0_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 21. "MUX_FW_AMUXBUSB_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 20. "MUX_FW_AMUXBUSA_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 19. "MUX_FW_AMUXBUSB_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 18. "MUX_FW_AMUXBUSA_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 17. "MUX_FW_TEMP_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 16. "MUX_FW_VSSA_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 15. "MUX_FW_P7_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 14. "MUX_FW_P6_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 13. "MUX_FW_P5_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 12. "MUX_FW_P4_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 11. "MUX_FW_P3_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 10. "MUX_FW_P2_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 9. "MUX_FW_P1_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 8. "MUX_FW_P0_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 7. "MUX_FW_P7_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 6. "MUX_FW_P6_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 5. "MUX_FW_P5_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 4. "MUX_FW_P4_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 3. "MUX_FW_P3_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 2. "MUX_FW_P2_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 1. "MUX_FW_P1_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 0. "MUX_FW_P0_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1"
group.long 0x308++0x03
line.long 0x00 "MUX_SWITCH1,SARMUX Firmware switch controls"
bitfld.long 0x00 3. "MUX_FW_ADFT1_SARBUS1,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 2. "MUX_FW_ADFT0_SARBUS0,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 1. "MUX_FW_P5_DFT_INM,Firmware control" "0: open,1: close"
newline
bitfld.long 0x00 0. "MUX_FW_P4_DFT_INP,Firmware control" "0: open,1: close"
group.long 0x30C++0x03
line.long 0x00 "MUX_SWITCH_CLEAR1,SARMUX Firmware switch control clear"
bitfld.long 0x00 3. "MUX_FW_ADFT1_SARBUS1,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
newline
bitfld.long 0x00 2. "MUX_FW_ADFT0_SARBUS0,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
newline
bitfld.long 0x00 1. "MUX_FW_P5_DFT_INM,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
newline
bitfld.long 0x00 0. "MUX_FW_P4_DFT_INP,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1"
group.long 0x340++0x03
line.long 0x00 "MUX_SWITCH_HW_CTRL,SARMUX switch hardware control"
bitfld.long 0x00 23. "MUX_HW_CTRL_SARBUS1,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 22. "MUX_HW_CTRL_SARBUS0,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 19. "MUX_HW_CTRL_AMUXBUSB,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 18. "MUX_HW_CTRL_AMUXBUSA,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 17. "MUX_HW_CTRL_TEMP,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 16. "MUX_HW_CTRL_VSSA,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 7. "MUX_HW_CTRL_P7,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 6. "MUX_HW_CTRL_P6,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 5. "MUX_HW_CTRL_P5,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 4. "MUX_HW_CTRL_P4,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 3. "MUX_HW_CTRL_P3,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 2. "MUX_HW_CTRL_P2,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 1. "MUX_HW_CTRL_P1,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
newline
bitfld.long 0x00 0. "MUX_HW_CTRL_P0,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for"
rgroup.long 0x348++0x03
line.long 0x00 "MUX_SWITCH_STATUS,SARMUX switch status"
bitfld.long 0x00 25. "MUX_FW_SARBUS1_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 24. "MUX_FW_SARBUS0_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 23. "MUX_FW_SARBUS1_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 22. "MUX_FW_SARBUS0_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 21. "MUX_FW_AMUXBUSB_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 20. "MUX_FW_AMUXBUSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 19. "MUX_FW_AMUXBUSB_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 18. "MUX_FW_AMUXBUSA_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 17. "MUX_FW_TEMP_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 16. "MUX_FW_VSSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 15. "MUX_FW_P7_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 14. "MUX_FW_P6_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 13. "MUX_FW_P5_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 12. "MUX_FW_P4_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 11. "MUX_FW_P3_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 10. "MUX_FW_P2_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 9. "MUX_FW_P1_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 8. "MUX_FW_P0_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 7. "MUX_FW_P7_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 6. "MUX_FW_P6_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 5. "MUX_FW_P5_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 4. "MUX_FW_P4_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 3. "MUX_FW_P3_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 2. "MUX_FW_P2_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 1. "MUX_FW_P1_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
newline
bitfld.long 0x00 0. "MUX_FW_P0_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1"
group.long 0x380++0x03
line.long 0x00 "PUMP_CTRL,Switch pump control"
bitfld.long 0x00 31. "ENABLED," "0,1"
newline
bitfld.long 0x00 0. "CLOCK_SEL,Clock select" "0: external clock,1: internal clock (deprecated)"
group.long 0xF00++0x03
line.long 0x00 "ANA_TRIM,Analog trim register"
bitfld.long 0x00 3. "TRIMUNIT,Attenuation cap trimming" "0,1"
newline
bitfld.long 0x00 0.--2. "CAP_TRIM,Attenuation cap trimming" "0,1,2,3,4,5,6,7"
group.long 0xF04++0x03
line.long 0x00 "WOUNDING,SAR wounding register"
bitfld.long 0x00 0.--1. "WOUND_RESOLUTION,Maximum SAR resolution allowed" "0: unwounded,1: wounded,2: wounded,3: wounded"
tree.end
endif
tree.end
tree "SCB (Serial Communications Block (SPI/UART/I2C))"
repeat 3. (list 0. 1. 2.) (list ad:0x40080000 ad:0x40090000 ad:0x400A0000) (list ad:0x40240000 ad:0x40250000 ad:0x40260000)
tree "SCB$1"
sif cpuis("CY8C4146P*")||cpuis("CY8C4146L*")
base $2
elif cpuis("CY8C4149*")||cpuis("CY8C4147*")||cpuis("CY8C4146A*")||cpuis("CY8C4148*")
base $3
endif
sif cpuis("psoc4100smax")
group.long 0x00++0x03
line.long 0x00 "CTRL,Generic control"
bitfld.long 0x00 31. "ENABLED,IP enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory" "0: enable clock_scb_en has no effect on ec_busy_pp,1: disable clock_scb_en enable ec_busy_pp (grant"
newline
bitfld.long 0x00 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode,1: Serial Peripheral Interface (SPI) mode,2: Universal Asynchronous Receiver/Transmitter..,?..."
bitfld.long 0x00 17. "BLOCK,Only used in externally clocked mode" "0,1"
newline
bitfld.long 0x00 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')" "0,1"
bitfld.long 0x00 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element depending on physical SRAM cell data width" "0: 8-bit FIFO data elements,1: 16-bit FIFO data elements,2: 32-bit FIFO data elements,3: RSVD"
newline
bitfld.long 0x00 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled" "0,1"
bitfld.long 0x00 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')" "0,1"
newline
bitfld.long 0x00 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation" "0,1"
bitfld.long 0x00 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI)" "0,1"
newline
bitfld.long 0x00 0.--3. "OVS,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x00++0x03
line.long 0x00 "CTRL,Generic control register"
bitfld.long 0x00 31. "ENABLED,IP enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode,1: Serial Peripheral Interface (SPI) mode,2: Universal Asynchronous Receiver/Transmitter..,?..."
newline
bitfld.long 0x00 17. "BLOCK,Only used in externally clocked mode" "0,1"
bitfld.long 0x00 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled" "0,1"
bitfld.long 0x00 11. "BYTE_MODE,Determines the number of bits per FIFO data element: '0': 16-bit FIFO data elements" "0,1"
newline
bitfld.long 0x00 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')" "0,1"
bitfld.long 0x00 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation" "0,1"
newline
bitfld.long 0x00 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI)" "0,1"
bitfld.long 0x00 0.--3. "OVS,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x04++0x03
line.long 0x00 "STATUS,Generic status"
bitfld.long 0x00 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode)" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0x04++0x03
line.long 0x00 "STATUS,Generic status register"
bitfld.long 0x00 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode)" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0x08++0x03
line.long 0x00 "CMD_RESP_CTRL,Command/response control"
hexmask.long.word 0x00 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode"
hexmask.long.word 0x00 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x08++0x03
line.long 0x00 "CMD_RESP_CTRL,Command/response control register"
hexmask.long.word 0x00 16.--24. 1. "BASE_WR_ADDR,I2C/SPI read base address for CMD_RESP mode"
hexmask.long.word 0x00 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode"
rgroup.long 0x0C++0x03
line.long 0x00 "CMD_RESP_STATUS,Command/response status register"
bitfld.long 0x00 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1')" "0,1"
bitfld.long 0x00 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP" "0,1"
newline
hexmask.long.word 0x00 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode"
hexmask.long.word 0x00 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x0C++0x03
line.long 0x00 "CMD_RESP_STATUS,Command/response status"
bitfld.long 0x00 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1')" "0,1"
bitfld.long 0x00 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP" "0,1"
newline
hexmask.long.word 0x00 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode"
hexmask.long.word 0x00 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x20++0x03
line.long 0x00 "SPI_CTRL,SPI control register"
bitfld.long 0x00 31. "MASTER_MODE,Master ('1') or slave ('0') mode" "0,1"
bitfld.long 0x00 26.--27. "SLAVE_SELECT,Selects one of the four outgoing SPI slave select signals" "0: Slave 0 SPI_SELECT[0],1: Slave 1 SPI_SELECT[1],2: Slave 2 SPI_SELECT[2],3: Slave 3 SPI_SELECT[3]"
newline
bitfld.long 0x00 24.--25. "MODE,N/A" "0: SPI Motorola submode,1: SPI Texas Instruments submode,2: SPI National Semiconducturs submode,?..."
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
newline
bitfld.long 0x00 11. "SSEL_POLARITY3,Slave select polarity" "0,1"
bitfld.long 0x00 10. "SSEL_POLARITY2,Slave select polarity" "0,1"
newline
bitfld.long 0x00 9. "SSEL_POLARITY1,Slave select polarity" "0,1"
bitfld.long 0x00 8. "SSEL_POLARITY0,Slave select polarity" "0,1"
newline
bitfld.long 0x00 5. "SCLK_CONTINUOUS,Only applicable in master mode" "0,1"
bitfld.long 0x00 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured" "0,1"
newline
bitfld.long 0x00 3. "CPOL,Indicates the clock polarity" "0,1"
bitfld.long 0x00 2. "CPHA,Only applicable in SPI Motorola submode" "0,1"
newline
bitfld.long 0x00 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode" "0,1"
bitfld.long 0x00 0. "CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0')" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0x20++0x03
line.long 0x00 "SPI_CTRL,SPI control"
bitfld.long 0x00 31. "MASTER_MODE,Master ('1') or slave ('0') mode" "0,1"
bitfld.long 0x00 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals" "0: Slave 0 SSEL[0],1: Slave 1 SSEL[1],2: Slave 2 SSEL[2],3: Slave 3 SSEL[3]"
newline
bitfld.long 0x00 24.--25. "MODE,N/A" "0: SPI Motorola submode,1: SPI Texas Instruments submode,2: SPI National Semiconductors submode,?..."
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
newline
bitfld.long 0x00 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)" "0,1"
bitfld.long 0x00 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MISO bit and SELECT deactivation)" "0,1"
newline
bitfld.long 0x00 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MISO bit)" "0,1"
bitfld.long 0x00 11. "SSEL_POLARITY3,Slave select polarity" "0,1"
newline
bitfld.long 0x00 10. "SSEL_POLARITY2,Slave select polarity" "0,1"
bitfld.long 0x00 9. "SSEL_POLARITY1,Slave select polarity" "0,1"
newline
bitfld.long 0x00 8. "SSEL_POLARITY0,Slave select polarity" "0,1"
bitfld.long 0x00 5. "SCLK_CONTINUOUS,Only applicable in master mode" "0,1"
newline
bitfld.long 0x00 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured" "0,1"
bitfld.long 0x00 3. "CPOL,Indicates the clock polarity" "0,1"
newline
bitfld.long 0x00 2. "CPHA,Indicates the clock phase" "0,1"
bitfld.long 0x00 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode" "0,1"
newline
bitfld.long 0x00 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0')" "0,1"
rgroup.long 0x24++0x03
line.long 0x00 "SPI_STATUS,SPI status"
hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address"
hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address"
newline
bitfld.long 0x00 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode)" "0,1"
bitfld.long 0x00 0. "BUS_BUSY,SPI bus is busy" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0x24++0x03
line.long 0x00 "SPI_STATUS,SPI status register"
hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address"
hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address"
newline
bitfld.long 0x00 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode)" "0,1"
bitfld.long 0x00 0. "BUS_BUSY,SPI bus is busy" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0x28++0x03
line.long 0x00 "SPI_TX_CTRL,SPI transmitter control"
bitfld.long 0x00 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive" "0: retain the level of last data bit,1: change to high (MOSI level is high before the"
bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
group.long 0x2C++0x03
line.long 0x00 "SPI_RX_CTRL,SPI receiver control"
bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails" "0,1"
bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
group.long 0x40++0x03
line.long 0x00 "UART_CTRL,UART control"
bitfld.long 0x00 24.--25. "MODE,N/A" "0: Standard UART submode,1: SmartCard (ISO7816) submode,2: Infrared Data Association (IrDA) submode,?..."
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x40++0x03
line.long 0x00 "UART_CTRL,UART control register"
bitfld.long 0x00 24.--25. "MODE,N/A" "0: Standard UART submode,1: SmartCard (ISO7816) submode,2: Infrared Data Association (IrDA) submode,?..."
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0x44++0x03
line.long 0x00 "UART_TX_CTRL,UART transmitter control"
bitfld.long 0x00 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received" "0,1"
bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x44++0x03
line.long 0x00 "UART_TX_CTRL,UART transmitter control register"
bitfld.long 0x00 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received" "0,1"
bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7"
group.long 0x48++0x03
line.long 0x00 "UART_RX_CTRL,UART receiver control register"
bitfld.long 0x00 16.--19. "BREAK_WIDTH,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 13. "SKIP_START,Only applicable in standard UART submode" "0,1"
newline
bitfld.long 0x00 12. "LIN_MODE,Only applicable in standard UART submode" "0,1"
bitfld.long 0x00 10. "MP_MODE,Multi-processor mode" "0,1"
newline
bitfld.long 0x00 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period" "0,1"
bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behaviour when a parity check fails" "0,1"
newline
bitfld.long 0x00 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'" "0,1"
bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7"
endif
sif cpuis("psoc4100smax")
group.long 0x48++0x03
line.long 0x00 "UART_RX_CTRL,UART receiver control"
bitfld.long 0x00 24. "BREAK_LEVEL," "0,1"
bitfld.long 0x00 16.--19. "BREAK_WIDTH,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "SKIP_START,Only applicable in standard UART submode" "0,1"
bitfld.long 0x00 12. "LIN_MODE,Only applicable in standard UART submode" "0,1"
newline
bitfld.long 0x00 10. "MP_MODE,Multi-processor mode" "0,1"
bitfld.long 0x00 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period" "0,1"
newline
bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails" "0,1"
bitfld.long 0x00 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'" "0,1"
newline
bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
newline
bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0x4C++0x03
line.long 0x00 "UART_RX_STATUS,UART receiver status register"
hexmask.long.word 0x00 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x4C++0x03
line.long 0x00 "UART_RX_STATUS,UART receiver status"
hexmask.long.word 0x00 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver"
group.long 0x50++0x03
line.long 0x00 "UART_FLOW_CTRL,UART flow control"
bitfld.long 0x00 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled" "0,1"
bitfld.long 0x00 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive" "0,1"
newline
bitfld.long 0x00 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x50++0x03
line.long 0x00 "UART_FLOW_CTRL,UART flow control register"
bitfld.long 0x00 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled" "0,1"
bitfld.long 0x00 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive" "0,1"
newline
bitfld.long 0x00 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
endif
sif cpuis("psoc4100smax")
group.long 0x60++0x03
line.long 0x00 "I2C_CTRL,I2C control"
bitfld.long 0x00 31. "MASTER_MODE,Master mode enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
bitfld.long 0x00 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only" "0: clock stretching is performed (till the..,1: a received data element byte the slave is"
newline
bitfld.long 0x00 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0')" "0: clock stretching is performed (till the,1: a received (matching or general) slave address"
bitfld.long 0x00 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full" "0,1"
newline
bitfld.long 0x00 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full" "0,1"
bitfld.long 0x00 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address" "0,1"
newline
bitfld.long 0x00 9. "M_NOT_READY_DATA_NACK,for I2C master the NACKed byte should be properly received" "0,1"
bitfld.long 0x00 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full" "0,1"
newline
bitfld.long 0x00 4.--7. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x60++0x03
line.long 0x00 "I2C_CTRL,I2C control register"
bitfld.long 0x00 31. "MASTER_MODE,Master mode enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
bitfld.long 0x00 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only" "0: clock stretching is performed (till the..,1: a received data element byte the slave is"
newline
bitfld.long 0x00 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0')" "0: clock stretching is performed (till the,1: a received (matching or general) slave address"
bitfld.long 0x00 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full" "0,1"
newline
bitfld.long 0x00 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full" "0,1"
bitfld.long 0x00 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address" "0,1"
newline
bitfld.long 0x00 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full" "0,1"
bitfld.long 0x00 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full" "0,1"
newline
bitfld.long 0x00 4.--7. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x64++0x03
line.long 0x00 "I2C_STATUS,I2C status register"
hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address"
hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address"
newline
bitfld.long 0x00 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0')" "0,1"
bitfld.long 0x00 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0')" "0,1"
newline
bitfld.long 0x00 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode)" "0,1"
bitfld.long 0x00 0. "BUS_BUSY,I2C bus is busy" "0,1"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x64++0x03
line.long 0x00 "I2C_STATUS,I2C status"
bitfld.long 0x00 24. "HS_MODE,this is to indicate I2C Hs-mode transfer it is set after 'Start master-code NACK'' pattern for I2CM at SCL falling edge (INTR_M.I2C_HS_ENTER triggers) for I2CS_IC at SCL falling edge (INTR_S.I2C_HS_ENTER triggers) for I2CS_EC at SCL rising edge.." "0,1"
hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address"
newline
hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address"
bitfld.long 0x00 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0')" "0,1"
newline
bitfld.long 0x00 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0')" "0,1"
bitfld.long 0x00 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master" "0,1"
newline
bitfld.long 0x00 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode)" "0,1"
bitfld.long 0x00 0. "BUS_BUSY,I2C bus is busy" "0,1"
group.long 0x68++0x03
line.long 0x00 "I2C_M_CMD,I2C master command"
bitfld.long 0x00 4. "M_STOP,When '1' attempt to transmit a STOP" "0,1"
bitfld.long 0x00 3. "M_NACK,for I2C master the NACKed byte should be properly received" "0,1"
newline
bitfld.long 0x00 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
bitfld.long 0x00 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')" "0,1"
newline
bitfld.long 0x00 0. "M_START,When '1' transmit a START or REPEATED START" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x68++0x03
line.long 0x00 "I2C_M_CMD,I2C master command register"
bitfld.long 0x00 4. "M_STOP,When '1' attempt to transmit a STOP" "0,1"
bitfld.long 0x00 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1"
newline
bitfld.long 0x00 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
bitfld.long 0x00 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')" "0,1"
newline
bitfld.long 0x00 0. "M_START,When '1' transmit a START or REPEATED START" "0,1"
group.long 0x6C++0x03
line.long 0x00 "I2C_S_CMD,I2C slave command register"
bitfld.long 0x00 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1"
bitfld.long 0x00 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0x6C++0x03
line.long 0x00 "I2C_S_CMD,I2C slave command"
bitfld.long 0x00 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected" "0,1"
bitfld.long 0x00 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty" "0,1"
newline
bitfld.long 0x00 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1"
bitfld.long 0x00 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x70++0x03
line.long 0x00 "I2C_CFG,I2C configuration register"
bitfld.long 0x00 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns" "0,1,2,3"
bitfld.long 0x00 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3"
bitfld.long 0x00 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3"
newline
bitfld.long 0x00 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay: '0': 0 ns" "0,1"
bitfld.long 0x00 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter" "0,1,2,3"
newline
bitfld.long 0x00 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay: '0': 0 ns" "0,1"
bitfld.long 0x00 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
endif
sif cpuis("psoc4100smax")
group.long 0x70++0x03
line.long 0x00 "I2C_CFG,I2C configuration"
bitfld.long 0x00 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns" "0,1,2,3"
bitfld.long 0x00 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3"
bitfld.long 0x00 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3"
newline
bitfld.long 0x00 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay: '0': 0 ns" "0,1"
bitfld.long 0x00 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter" "0,1,2,3"
newline
bitfld.long 0x00 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay: '0': 0 ns" "0,1"
bitfld.long 0x00 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
group.long 0x74++0x03
line.long 0x00 "I2C_STRETCH_CTRL,I2C stretch control"
bitfld.long 0x00 0.--3. "STRETCH_THRESHOLD,stretch threthold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x78++0x03
line.long 0x00 "I2C_STRETCH_STATUS,I2C stretch status"
bitfld.long 0x00 8. "STRETCHING,I2C SCL is stretched by this block (DUT) for I2C master this can happen when TX FIFO is empty or RX_FIFO is full or ACK/NACK is not decided or RESTART/STOP is not decided" "0,1"
bitfld.long 0x00 5. "SYNC_DETECTED,synchronization detected" "0,1"
newline
bitfld.long 0x00 4. "STRETCH_DETECTED,stretch detected" "0,1"
bitfld.long 0x00 0.--3. "STRETCH_COUNT,stretch count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80++0x03
line.long 0x00 "I2C_CTRL_HS,I2C control for High-Speed mode"
bitfld.long 0x00 31. "HS_ENABLED,0': I2C Hs-mode is disabled '1': I2C Hs-mode is enabled when I2C Hs-mode is disabled and the IP is in I2C slave mode slave address bytes in Hs-mode transfers are NACKed" "0,1"
bitfld.long 0x00 4.--7. "LOVS_HS,Serial I2C interface low phase oversampling factor for I2C Hs-mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "HOVS_HS,Serial I2C interface high phase oversampling factor for I2C Hs-mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x200++0x03
line.long 0x00 "TX_CTRL,Transmitter control"
bitfld.long 0x00 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'" "0,1"
bitfld.long 0x00 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'" "0,1"
newline
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
bitfld.long 0x00 0.--4. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x200++0x03
line.long 0x00 "TX_CTRL,Transmitter control register"
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x204++0x03
line.long 0x00 "TX_FIFO_CTRL,Transmitter FIFO control register"
bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
endif
sif cpuis("psoc4100smax")
group.long 0x204++0x03
line.long 0x00 "TX_FIFO_CTRL,Transmitter FIFO control"
bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0x208++0x03
line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO status register"
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written"
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware"
newline
bitfld.long 0x00 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0')" "0,1"
hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the transmitter FIFO"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x208++0x03
line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO status"
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written"
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware"
newline
bitfld.long 0x00 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0')" "0,1"
hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the transmitter FIFO"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
wgroup.long 0x240++0x03
line.long 0x00 "TX_FIFO_WR,Transmitter FIFO write register"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data frame written into the transmitter FIFO"
endif
sif cpuis("psoc4100smax")
wgroup.long 0x240++0x03
line.long 0x00 "TX_FIFO_WR,Transmitter FIFO"
hexmask.long 0x00 0.--31. 1. "DATA,Data frame written into the transmitter FIFO"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x300++0x03
line.long 0x00 "RX_CTRL,Receiver control register"
bitfld.long 0x00 9. "MEDIAN,Median filter" "0,1"
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
newline
bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("psoc4100smax")
group.long 0x300++0x03
line.long 0x00 "RX_CTRL,Receiver control"
bitfld.long 0x00 9. "MEDIAN,Median filter" "0,1"
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
newline
bitfld.long 0x00 0.--4. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x304++0x03
line.long 0x00 "RX_FIFO_CTRL,Receiver FIFO control register"
bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
endif
sif cpuis("psoc4100smax")
group.long 0x304++0x03
line.long 0x00 "RX_FIFO_CTRL,Receiver FIFO control"
bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0x308++0x03
line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO status register"
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware"
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is"
newline
bitfld.long 0x00 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0')" "0,1"
hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the receiver FIFO"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x308++0x03
line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO status"
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware"
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is"
newline
bitfld.long 0x00 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0')" "0,1"
hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the receiver FIFO"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x310++0x03
line.long 0x00 "RX_MATCH,Slave address and mask register"
hexmask.long.byte 0x00 16.--23. 1. "MASK,Slave device address mask"
hexmask.long.byte 0x00 0.--7. 1. "ADDR,Slave device address"
endif
sif cpuis("psoc4100smax")
group.long 0x310++0x03
line.long 0x00 "RX_MATCH,Slave address and mask"
hexmask.long.byte 0x00 16.--23. 1. "MASK,Slave device address mask"
hexmask.long.byte 0x00 0.--7. 1. "ADDR,Slave device address"
rgroup.long 0x340++0x03
line.long 0x00 "RX_FIFO_RD,Receiver FIFO"
hexmask.long 0x00 0.--31. 1. "DATA,Data read from the receiver FIFO"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0x340++0x03
line.long 0x00 "RX_FIFO_RD,Receiver FIFO read register"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO"
rgroup.long 0x344++0x03
line.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO read register"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x344++0x03
line.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
hexmask.long 0x00 0.--31. 1. "DATA,Data read from the receiver FIFO"
rgroup.long 0xE00++0x03
line.long 0x00 "INTR_CAUSE,Active clocked interrupt signal"
bitfld.long 0x00 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0" "0,1"
bitfld.long 0x00 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0" "0,1"
newline
bitfld.long 0x00 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0" "0,1"
bitfld.long 0x00 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0" "0,1"
newline
bitfld.long 0x00 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0" "0,1"
bitfld.long 0x00 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0xE00++0x03
line.long 0x00 "INTR_CAUSE,Active clocked interrupt signal register"
bitfld.long 0x00 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0" "0,1"
bitfld.long 0x00 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0" "0,1"
newline
bitfld.long 0x00 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0" "0,1"
bitfld.long 0x00 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0" "0,1"
newline
bitfld.long 0x00 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0" "0,1"
bitfld.long 0x00 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xE80++0x03
line.long 0x00 "INTR_I2C_EC,Externally clocked I2C interrupt request"
bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xE80++0x03
line.long 0x00 "INTR_I2C_EC,Externally clocked I2C interrupt request register"
bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1"
group.long 0xE88++0x03
line.long 0x00 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask register"
bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xE88++0x03
line.long 0x00 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0xE8C++0x03
line.long 0x00 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0xE8C++0x03
line.long 0x00 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked register"
bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1"
group.long 0xEC0++0x03
line.long 0x00 "INTR_SPI_EC,Externally clocked SPI interrupt request register"
bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xEC0++0x03
line.long 0x00 "INTR_SPI_EC,Externally clocked SPI interrupt request"
bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xEC8++0x03
line.long 0x00 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask register"
bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xEC8++0x03
line.long 0x00 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0xECC++0x03
line.long 0x00 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked register"
bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100smax")
rgroup.long 0xECC++0x03
line.long 0x00 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF00++0x03
line.long 0x00 "INTR_M,Master interrupt request register"
bitfld.long 0x00 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent and the transmit FIFO and shift register are empty" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,I2C master STOP" "0,1"
bitfld.long 0x00 2. "I2C_ACK,I2C master acknowledgement" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,I2C master negative acknowledgement" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF00++0x03
line.long 0x00 "INTR_M,Master interrupt request"
bitfld.long 0x00 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence" "0,1"
newline
bitfld.long 0x00 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,I2C master STOP" "0,1"
bitfld.long 0x00 2. "I2C_ACK,I2C master acknowledgement" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,I2C master negative acknowledgement" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF04++0x03
line.long 0x00 "INTR_M_SET,Master interrupt set request register"
bitfld.long 0x00 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF04++0x03
line.long 0x00 "INTR_M_SET,Master interrupt set request"
bitfld.long 0x00 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF08++0x03
line.long 0x00 "INTR_M_MASK,Master interrupt mask register"
bitfld.long 0x00 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF08++0x03
line.long 0x00 "INTR_M_MASK,Master interrupt mask"
bitfld.long 0x00 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0xF0C++0x03
line.long 0x00 "INTR_M_MASKED,Master interrupt masked request"
bitfld.long 0x00 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 9. "SPI_DONE,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0xF0C++0x03
line.long 0x00 "INTR_M_MASKED,Master interrupt masked request register"
bitfld.long 0x00 9. "SPI_DONE,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF40++0x03
line.long 0x00 "INTR_S,Slave interrupt request"
bitfld.long 0x00 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence" "0,1"
newline
bitfld.long 0x00 16. "I2C_RESTART,I2C slave RESTART received" "0,1"
bitfld.long 0x00 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer" "0,1"
newline
bitfld.long 0x00 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred" "0,1"
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred" "0,1"
newline
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition)" "0,1"
bitfld.long 0x00 7. "I2C_GENERAL,I2C slave general call address received" "0,1"
newline
bitfld.long 0x00 6. "I2C_ADDR_MATCH,I2C slave matching address received" "0,1"
bitfld.long 0x00 5. "I2C_START,I2C slave START received" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed)" "0,1"
bitfld.long 0x00 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed)" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,I2C slave acknowledgement received" "0,1"
bitfld.long 0x00 1. "I2C_NACK,I2C slave negative acknowledgement received" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1')" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF40++0x03
line.long 0x00 "INTR_S,Slave interrupt request register"
bitfld.long 0x00 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer" "0,1"
bitfld.long 0x00 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred" "0,1"
newline
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition)" "0,1"
newline
bitfld.long 0x00 7. "I2C_GENERAL,I2C slave general call address received" "0,1"
bitfld.long 0x00 6. "I2C_ADDR_MATCH,I2C slave matching address received" "0,1"
newline
bitfld.long 0x00 5. "I2C_START,I2C slave START received" "0,1"
bitfld.long 0x00 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed)" "0,1"
newline
bitfld.long 0x00 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed)" "0,1"
bitfld.long 0x00 2. "I2C_ACK,I2C slave acknowledgement received" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,I2C slave negative acknowledgement received" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1')" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF44++0x03
line.long 0x00 "INTR_S_SET,Slave interrupt set request"
bitfld.long 0x00 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF44++0x03
line.long 0x00 "INTR_S_SET,Slave interrupt set request register"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF48++0x03
line.long 0x00 "INTR_S_MASK,Slave interrupt mask"
bitfld.long 0x00 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "I2C_START,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF48++0x03
line.long 0x00 "INTR_S_MASK,Slave interrupt mask register"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "I2C_START,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0xF4C++0x03
line.long 0x00 "INTR_S_MASKED,Slave interrupt masked request register"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 7. "I2C_GENERAL,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 5. "I2C_START,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100smax")
rgroup.long 0xF4C++0x03
line.long 0x00 "INTR_S_MASKED,Slave interrupt masked request"
bitfld.long 0x00 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 16. "I2C_RESTART,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 7. "I2C_GENERAL,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 5. "I2C_START,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
group.long 0xF80++0x03
line.long 0x00 "INTR_TX,Transmitter interrupt request"
bitfld.long 0x00 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line" "0,1"
bitfld.long 0x00 9. "UART_DONE,UART transmitter done event" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode" "0,1"
bitfld.long 0x00 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full TX FIFO" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,TX FIFO is empty i.e" "0,1"
bitfld.long 0x00 1. "NOT_FULL,TX FIFO is not full" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF80++0x03
line.long 0x00 "INTR_TX,Transmitter interrupt request register"
bitfld.long 0x00 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line" "0,1"
bitfld.long 0x00 9. "UART_DONE,UART transmitter done event" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode" "0,1"
bitfld.long 0x00 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full TX FIFO" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,TX FIFO is empty i.e" "0,1"
bitfld.long 0x00 1. "NOT_FULL,TX FIFO is not full" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL" "0,1"
group.long 0xF84++0x03
line.long 0x00 "INTR_TX_SET,Transmitter interrupt set request register"
bitfld.long 0x00 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF84++0x03
line.long 0x00 "INTR_TX_SET,Transmitter interrupt set request"
bitfld.long 0x00 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF88++0x03
line.long 0x00 "INTR_TX_MASK,Transmitter interrupt mask register"
bitfld.long 0x00 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF88++0x03
line.long 0x00 "INTR_TX_MASK,Transmitter interrupt mask"
bitfld.long 0x00 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0xF8C++0x03
line.long 0x00 "INTR_TX_MASKED,Transmitter interrupt masked request register"
bitfld.long 0x00 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 9. "UART_DONE,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100smax")
rgroup.long 0xF8C++0x03
line.long 0x00 "INTR_TX_MASKED,Transmitter interrupt masked request"
bitfld.long 0x00 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 9. "UART_DONE,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
group.long 0xFC0++0x03
line.long 0x00 "INTR_RX,Receiver interrupt request"
bitfld.long 0x00 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,LIN baudrate detection is completed" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Parity error in received data frame" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Frame error in received data frame" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full RX FIFO" "0,1"
bitfld.long 0x00 3. "FULL,RX FIFO is full" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,RX FIFO is not empty" "0,1"
bitfld.long 0x00 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xFC0++0x03
line.long 0x00 "INTR_RX,Receiver interrupt request register"
bitfld.long 0x00 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,LIN baudrate detection is completed" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Parity error in received data frame" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Frame error in received data frame" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full RX FIFO" "0,1"
bitfld.long 0x00 3. "FULL,RX FIFO is full" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,RX FIFO is not empty" "0,1"
bitfld.long 0x00 0. "TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xFC4++0x03
line.long 0x00 "INTR_RX_SET,Receiver interrupt set request"
bitfld.long 0x00 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 3. "FULL,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xFC4++0x03
line.long 0x00 "INTR_RX_SET,Receiver interrupt set request register"
bitfld.long 0x00 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 3. "FULL,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xFC8++0x03
line.long 0x00 "INTR_RX_MASK,Receiver interrupt mask register"
bitfld.long 0x00 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 3. "FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xFC8++0x03
line.long 0x00 "INTR_RX_MASK,Receiver interrupt mask"
bitfld.long 0x00 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 3. "FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0xFCC++0x03
line.long 0x00 "INTR_RX_MASKED,Receiver interrupt masked request"
bitfld.long 0x00 11. "BREAK_DETECT,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 3. "FULL,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0xFCC++0x03
line.long 0x00 "INTR_RX_MASKED,Receiver interrupt masked request register"
bitfld.long 0x00 11. "BREAK_DETECT,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 3. "FULL,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
endif
tree.end
repeat.end
sif cpuis("CY8C4149*")||cpuis("CY8C4147*")||cpuis("CY8C4146A*")||cpuis("CY8C4148*")
repeat 2. (list 3. 4.) (list ad:0x40270000 ad:0x40280000)
tree "SCB$1"
base $2
sif cpuis("psoc4100smax")
group.long 0x00++0x03
line.long 0x00 "CTRL,Generic control"
bitfld.long 0x00 31. "ENABLED,IP enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory" "0: enable clock_scb_en has no effect on ec_busy_pp,1: disable clock_scb_en enable ec_busy_pp (grant"
newline
bitfld.long 0x00 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode,1: Serial Peripheral Interface (SPI) mode,2: Universal Asynchronous Receiver/Transmitter..,?..."
bitfld.long 0x00 17. "BLOCK,Only used in externally clocked mode" "0,1"
newline
bitfld.long 0x00 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')" "0,1"
bitfld.long 0x00 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element depending on physical SRAM cell data width" "0: 8-bit FIFO data elements,1: 16-bit FIFO data elements,2: 32-bit FIFO data elements,3: RSVD"
newline
bitfld.long 0x00 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled" "0,1"
bitfld.long 0x00 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')" "0,1"
newline
bitfld.long 0x00 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation" "0,1"
bitfld.long 0x00 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI)" "0,1"
newline
bitfld.long 0x00 0.--3. "OVS,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x00++0x03
line.long 0x00 "CTRL,Generic control register"
bitfld.long 0x00 31. "ENABLED,IP enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode,1: Serial Peripheral Interface (SPI) mode,2: Universal Asynchronous Receiver/Transmitter..,?..."
newline
bitfld.long 0x00 17. "BLOCK,Only used in externally clocked mode" "0,1"
bitfld.long 0x00 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled" "0,1"
bitfld.long 0x00 11. "BYTE_MODE,Determines the number of bits per FIFO data element: '0': 16-bit FIFO data elements" "0,1"
newline
bitfld.long 0x00 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')" "0,1"
bitfld.long 0x00 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation" "0,1"
newline
bitfld.long 0x00 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI)" "0,1"
bitfld.long 0x00 0.--3. "OVS,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x04++0x03
line.long 0x00 "STATUS,Generic status"
bitfld.long 0x00 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode)" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0x04++0x03
line.long 0x00 "STATUS,Generic status register"
bitfld.long 0x00 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode)" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0x08++0x03
line.long 0x00 "CMD_RESP_CTRL,Command/response control"
hexmask.long.word 0x00 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode"
hexmask.long.word 0x00 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x08++0x03
line.long 0x00 "CMD_RESP_CTRL,Command/response control register"
hexmask.long.word 0x00 16.--24. 1. "BASE_WR_ADDR,I2C/SPI read base address for CMD_RESP mode"
hexmask.long.word 0x00 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode"
rgroup.long 0x0C++0x03
line.long 0x00 "CMD_RESP_STATUS,Command/response status register"
bitfld.long 0x00 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1')" "0,1"
bitfld.long 0x00 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP" "0,1"
newline
hexmask.long.word 0x00 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode"
hexmask.long.word 0x00 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x0C++0x03
line.long 0x00 "CMD_RESP_STATUS,Command/response status"
bitfld.long 0x00 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1')" "0,1"
bitfld.long 0x00 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP" "0,1"
newline
hexmask.long.word 0x00 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode"
hexmask.long.word 0x00 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x20++0x03
line.long 0x00 "SPI_CTRL,SPI control register"
bitfld.long 0x00 31. "MASTER_MODE,Master ('1') or slave ('0') mode" "0,1"
bitfld.long 0x00 26.--27. "SLAVE_SELECT,Selects one of the four outgoing SPI slave select signals" "0: Slave 0 SPI_SELECT[0],1: Slave 1 SPI_SELECT[1],2: Slave 2 SPI_SELECT[2],3: Slave 3 SPI_SELECT[3]"
newline
bitfld.long 0x00 24.--25. "MODE,N/A" "0: SPI Motorola submode,1: SPI Texas Instruments submode,2: SPI National Semiconducturs submode,?..."
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
newline
bitfld.long 0x00 11. "SSEL_POLARITY3,Slave select polarity" "0,1"
bitfld.long 0x00 10. "SSEL_POLARITY2,Slave select polarity" "0,1"
newline
bitfld.long 0x00 9. "SSEL_POLARITY1,Slave select polarity" "0,1"
bitfld.long 0x00 8. "SSEL_POLARITY0,Slave select polarity" "0,1"
newline
bitfld.long 0x00 5. "SCLK_CONTINUOUS,Only applicable in master mode" "0,1"
bitfld.long 0x00 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured" "0,1"
newline
bitfld.long 0x00 3. "CPOL,Indicates the clock polarity" "0,1"
bitfld.long 0x00 2. "CPHA,Only applicable in SPI Motorola submode" "0,1"
newline
bitfld.long 0x00 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode" "0,1"
bitfld.long 0x00 0. "CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0')" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0x20++0x03
line.long 0x00 "SPI_CTRL,SPI control"
bitfld.long 0x00 31. "MASTER_MODE,Master ('1') or slave ('0') mode" "0,1"
bitfld.long 0x00 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals" "0: Slave 0 SSEL[0],1: Slave 1 SSEL[1],2: Slave 2 SSEL[2],3: Slave 3 SSEL[3]"
newline
bitfld.long 0x00 24.--25. "MODE,N/A" "0: SPI Motorola submode,1: SPI Texas Instruments submode,2: SPI National Semiconductors submode,?..."
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
newline
bitfld.long 0x00 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)" "0,1"
bitfld.long 0x00 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MISO bit and SELECT deactivation)" "0,1"
newline
bitfld.long 0x00 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MISO bit)" "0,1"
bitfld.long 0x00 11. "SSEL_POLARITY3,Slave select polarity" "0,1"
newline
bitfld.long 0x00 10. "SSEL_POLARITY2,Slave select polarity" "0,1"
bitfld.long 0x00 9. "SSEL_POLARITY1,Slave select polarity" "0,1"
newline
bitfld.long 0x00 8. "SSEL_POLARITY0,Slave select polarity" "0,1"
bitfld.long 0x00 5. "SCLK_CONTINUOUS,Only applicable in master mode" "0,1"
newline
bitfld.long 0x00 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured" "0,1"
bitfld.long 0x00 3. "CPOL,Indicates the clock polarity" "0,1"
newline
bitfld.long 0x00 2. "CPHA,Indicates the clock phase" "0,1"
bitfld.long 0x00 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode" "0,1"
newline
bitfld.long 0x00 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0')" "0,1"
rgroup.long 0x24++0x03
line.long 0x00 "SPI_STATUS,SPI status"
hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address"
hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address"
newline
bitfld.long 0x00 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode)" "0,1"
bitfld.long 0x00 0. "BUS_BUSY,SPI bus is busy" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0x24++0x03
line.long 0x00 "SPI_STATUS,SPI status register"
hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address"
hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address"
newline
bitfld.long 0x00 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode)" "0,1"
bitfld.long 0x00 0. "BUS_BUSY,SPI bus is busy" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0x28++0x03
line.long 0x00 "SPI_TX_CTRL,SPI transmitter control"
bitfld.long 0x00 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive" "0: retain the level of last data bit,1: change to high (MOSI level is high before the"
bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
group.long 0x2C++0x03
line.long 0x00 "SPI_RX_CTRL,SPI receiver control"
bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails" "0,1"
bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
group.long 0x40++0x03
line.long 0x00 "UART_CTRL,UART control"
bitfld.long 0x00 24.--25. "MODE,N/A" "0: Standard UART submode,1: SmartCard (ISO7816) submode,2: Infrared Data Association (IrDA) submode,?..."
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x40++0x03
line.long 0x00 "UART_CTRL,UART control register"
bitfld.long 0x00 24.--25. "MODE,N/A" "0: Standard UART submode,1: SmartCard (ISO7816) submode,2: Infrared Data Association (IrDA) submode,?..."
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0x44++0x03
line.long 0x00 "UART_TX_CTRL,UART transmitter control"
bitfld.long 0x00 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received" "0,1"
bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x44++0x03
line.long 0x00 "UART_TX_CTRL,UART transmitter control register"
bitfld.long 0x00 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received" "0,1"
bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7"
group.long 0x48++0x03
line.long 0x00 "UART_RX_CTRL,UART receiver control register"
bitfld.long 0x00 16.--19. "BREAK_WIDTH,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 13. "SKIP_START,Only applicable in standard UART submode" "0,1"
newline
bitfld.long 0x00 12. "LIN_MODE,Only applicable in standard UART submode" "0,1"
bitfld.long 0x00 10. "MP_MODE,Multi-processor mode" "0,1"
newline
bitfld.long 0x00 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period" "0,1"
bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behaviour when a parity check fails" "0,1"
newline
bitfld.long 0x00 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'" "0,1"
bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7"
endif
sif cpuis("psoc4100smax")
group.long 0x48++0x03
line.long 0x00 "UART_RX_CTRL,UART receiver control"
bitfld.long 0x00 24. "BREAK_LEVEL," "0,1"
bitfld.long 0x00 16.--19. "BREAK_WIDTH,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13. "SKIP_START,Only applicable in standard UART submode" "0,1"
bitfld.long 0x00 12. "LIN_MODE,Only applicable in standard UART submode" "0,1"
newline
bitfld.long 0x00 10. "MP_MODE,Multi-processor mode" "0,1"
bitfld.long 0x00 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period" "0,1"
newline
bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails" "0,1"
bitfld.long 0x00 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'" "0,1"
newline
bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 4. "PARITY,Parity bit" "0,1"
newline
bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0x4C++0x03
line.long 0x00 "UART_RX_STATUS,UART receiver status register"
hexmask.long.word 0x00 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x4C++0x03
line.long 0x00 "UART_RX_STATUS,UART receiver status"
hexmask.long.word 0x00 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver"
group.long 0x50++0x03
line.long 0x00 "UART_FLOW_CTRL,UART flow control"
bitfld.long 0x00 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled" "0,1"
bitfld.long 0x00 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive" "0,1"
newline
bitfld.long 0x00 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x50++0x03
line.long 0x00 "UART_FLOW_CTRL,UART flow control register"
bitfld.long 0x00 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled" "0,1"
bitfld.long 0x00 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive" "0,1"
newline
bitfld.long 0x00 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
endif
sif cpuis("psoc4100smax")
group.long 0x60++0x03
line.long 0x00 "I2C_CTRL,I2C control"
bitfld.long 0x00 31. "MASTER_MODE,Master mode enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
bitfld.long 0x00 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only" "0: clock stretching is performed (till the..,1: a received data element byte the slave is"
newline
bitfld.long 0x00 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0')" "0: clock stretching is performed (till the,1: a received (matching or general) slave address"
bitfld.long 0x00 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full" "0,1"
newline
bitfld.long 0x00 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full" "0,1"
bitfld.long 0x00 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address" "0,1"
newline
bitfld.long 0x00 9. "M_NOT_READY_DATA_NACK,for I2C master the NACKed byte should be properly received" "0,1"
bitfld.long 0x00 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full" "0,1"
newline
bitfld.long 0x00 4.--7. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x60++0x03
line.long 0x00 "I2C_CTRL,I2C control register"
bitfld.long 0x00 31. "MASTER_MODE,Master mode enabled ('1') or not ('0')" "0,1"
bitfld.long 0x00 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')" "0,1"
newline
bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1"
bitfld.long 0x00 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only" "0: clock stretching is performed (till the..,1: a received data element byte the slave is"
newline
bitfld.long 0x00 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0')" "0: clock stretching is performed (till the,1: a received (matching or general) slave address"
bitfld.long 0x00 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full" "0,1"
newline
bitfld.long 0x00 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full" "0,1"
bitfld.long 0x00 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address" "0,1"
newline
bitfld.long 0x00 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full" "0,1"
bitfld.long 0x00 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full" "0,1"
newline
bitfld.long 0x00 4.--7. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x64++0x03
line.long 0x00 "I2C_STATUS,I2C status register"
hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address"
hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address"
newline
bitfld.long 0x00 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0')" "0,1"
bitfld.long 0x00 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0')" "0,1"
newline
bitfld.long 0x00 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode)" "0,1"
bitfld.long 0x00 0. "BUS_BUSY,I2C bus is busy" "0,1"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x64++0x03
line.long 0x00 "I2C_STATUS,I2C status"
bitfld.long 0x00 24. "HS_MODE,this is to indicate I2C Hs-mode transfer it is set after 'Start master-code NACK'' pattern for I2CM at SCL falling edge (INTR_M.I2C_HS_ENTER triggers) for I2CS_IC at SCL falling edge (INTR_S.I2C_HS_ENTER triggers) for I2CS_EC at SCL rising edge.." "0,1"
hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address"
newline
hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address"
bitfld.long 0x00 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0')" "0,1"
newline
bitfld.long 0x00 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0')" "0,1"
bitfld.long 0x00 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master" "0,1"
newline
bitfld.long 0x00 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode)" "0,1"
bitfld.long 0x00 0. "BUS_BUSY,I2C bus is busy" "0,1"
group.long 0x68++0x03
line.long 0x00 "I2C_M_CMD,I2C master command"
bitfld.long 0x00 4. "M_STOP,When '1' attempt to transmit a STOP" "0,1"
bitfld.long 0x00 3. "M_NACK,for I2C master the NACKed byte should be properly received" "0,1"
newline
bitfld.long 0x00 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
bitfld.long 0x00 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')" "0,1"
newline
bitfld.long 0x00 0. "M_START,When '1' transmit a START or REPEATED START" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x68++0x03
line.long 0x00 "I2C_M_CMD,I2C master command register"
bitfld.long 0x00 4. "M_STOP,When '1' attempt to transmit a STOP" "0,1"
bitfld.long 0x00 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1"
newline
bitfld.long 0x00 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
bitfld.long 0x00 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')" "0,1"
newline
bitfld.long 0x00 0. "M_START,When '1' transmit a START or REPEATED START" "0,1"
group.long 0x6C++0x03
line.long 0x00 "I2C_S_CMD,I2C slave command register"
bitfld.long 0x00 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1"
bitfld.long 0x00 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0x6C++0x03
line.long 0x00 "I2C_S_CMD,I2C slave command"
bitfld.long 0x00 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected" "0,1"
bitfld.long 0x00 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty" "0,1"
newline
bitfld.long 0x00 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1"
bitfld.long 0x00 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x70++0x03
line.long 0x00 "I2C_CFG,I2C configuration register"
bitfld.long 0x00 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns" "0,1,2,3"
bitfld.long 0x00 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3"
bitfld.long 0x00 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3"
newline
bitfld.long 0x00 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay: '0': 0 ns" "0,1"
bitfld.long 0x00 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter" "0,1,2,3"
newline
bitfld.long 0x00 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay: '0': 0 ns" "0,1"
bitfld.long 0x00 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
endif
sif cpuis("psoc4100smax")
group.long 0x70++0x03
line.long 0x00 "I2C_CFG,I2C configuration"
bitfld.long 0x00 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns" "0,1,2,3"
bitfld.long 0x00 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3"
newline
bitfld.long 0x00 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3"
bitfld.long 0x00 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3"
newline
bitfld.long 0x00 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay: '0': 0 ns" "0,1"
bitfld.long 0x00 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter" "0,1,2,3"
newline
bitfld.long 0x00 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay: '0': 0 ns" "0,1"
bitfld.long 0x00 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
group.long 0x74++0x03
line.long 0x00 "I2C_STRETCH_CTRL,I2C stretch control"
bitfld.long 0x00 0.--3. "STRETCH_THRESHOLD,stretch threthold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x78++0x03
line.long 0x00 "I2C_STRETCH_STATUS,I2C stretch status"
bitfld.long 0x00 8. "STRETCHING,I2C SCL is stretched by this block (DUT) for I2C master this can happen when TX FIFO is empty or RX_FIFO is full or ACK/NACK is not decided or RESTART/STOP is not decided" "0,1"
bitfld.long 0x00 5. "SYNC_DETECTED,synchronization detected" "0,1"
newline
bitfld.long 0x00 4. "STRETCH_DETECTED,stretch detected" "0,1"
bitfld.long 0x00 0.--3. "STRETCH_COUNT,stretch count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x80++0x03
line.long 0x00 "I2C_CTRL_HS,I2C control for High-Speed mode"
bitfld.long 0x00 31. "HS_ENABLED,0': I2C Hs-mode is disabled '1': I2C Hs-mode is enabled when I2C Hs-mode is disabled and the IP is in I2C slave mode slave address bytes in Hs-mode transfers are NACKed" "0,1"
bitfld.long 0x00 4.--7. "LOVS_HS,Serial I2C interface low phase oversampling factor for I2C Hs-mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "HOVS_HS,Serial I2C interface high phase oversampling factor for I2C Hs-mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x200++0x03
line.long 0x00 "TX_CTRL,Transmitter control"
bitfld.long 0x00 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'" "0,1"
bitfld.long 0x00 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'" "0,1"
newline
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
bitfld.long 0x00 0.--4. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x200++0x03
line.long 0x00 "TX_CTRL,Transmitter control register"
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x204++0x03
line.long 0x00 "TX_FIFO_CTRL,Transmitter FIFO control register"
bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
endif
sif cpuis("psoc4100smax")
group.long 0x204++0x03
line.long 0x00 "TX_FIFO_CTRL,Transmitter FIFO control"
bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0x208++0x03
line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO status register"
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written"
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware"
newline
bitfld.long 0x00 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0')" "0,1"
hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the transmitter FIFO"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x208++0x03
line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO status"
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written"
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware"
newline
bitfld.long 0x00 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0')" "0,1"
hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the transmitter FIFO"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
wgroup.long 0x240++0x03
line.long 0x00 "TX_FIFO_WR,Transmitter FIFO write register"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data frame written into the transmitter FIFO"
endif
sif cpuis("psoc4100smax")
wgroup.long 0x240++0x03
line.long 0x00 "TX_FIFO_WR,Transmitter FIFO"
hexmask.long 0x00 0.--31. 1. "DATA,Data frame written into the transmitter FIFO"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x300++0x03
line.long 0x00 "RX_CTRL,Receiver control register"
bitfld.long 0x00 9. "MEDIAN,Median filter" "0,1"
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
newline
bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif cpuis("psoc4100smax")
group.long 0x300++0x03
line.long 0x00 "RX_CTRL,Receiver control"
bitfld.long 0x00 9. "MEDIAN,Median filter" "0,1"
bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1"
newline
bitfld.long 0x00 0.--4. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x304++0x03
line.long 0x00 "RX_FIFO_CTRL,Receiver FIFO control register"
bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
endif
sif cpuis("psoc4100smax")
group.long 0x304++0x03
line.long 0x00 "RX_FIFO_CTRL,Receiver FIFO control"
bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect" "0,1"
bitfld.long 0x00 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated" "0,1"
newline
hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0x308++0x03
line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO status register"
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware"
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is"
newline
bitfld.long 0x00 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0')" "0,1"
hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the receiver FIFO"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x308++0x03
line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO status"
hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware"
hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is"
newline
bitfld.long 0x00 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0')" "0,1"
hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the receiver FIFO"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0x310++0x03
line.long 0x00 "RX_MATCH,Slave address and mask register"
hexmask.long.byte 0x00 16.--23. 1. "MASK,Slave device address mask"
hexmask.long.byte 0x00 0.--7. 1. "ADDR,Slave device address"
endif
sif cpuis("psoc4100smax")
group.long 0x310++0x03
line.long 0x00 "RX_MATCH,Slave address and mask"
hexmask.long.byte 0x00 16.--23. 1. "MASK,Slave device address mask"
hexmask.long.byte 0x00 0.--7. 1. "ADDR,Slave device address"
rgroup.long 0x340++0x03
line.long 0x00 "RX_FIFO_RD,Receiver FIFO"
hexmask.long 0x00 0.--31. 1. "DATA,Data read from the receiver FIFO"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0x340++0x03
line.long 0x00 "RX_FIFO_RD,Receiver FIFO read register"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO"
rgroup.long 0x344++0x03
line.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO read register"
hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO"
endif
sif cpuis("psoc4100smax")
rgroup.long 0x344++0x03
line.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
hexmask.long 0x00 0.--31. 1. "DATA,Data read from the receiver FIFO"
rgroup.long 0xE00++0x03
line.long 0x00 "INTR_CAUSE,Active clocked interrupt signal"
bitfld.long 0x00 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0" "0,1"
bitfld.long 0x00 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0" "0,1"
newline
bitfld.long 0x00 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0" "0,1"
bitfld.long 0x00 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0" "0,1"
newline
bitfld.long 0x00 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0" "0,1"
bitfld.long 0x00 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0xE00++0x03
line.long 0x00 "INTR_CAUSE,Active clocked interrupt signal register"
bitfld.long 0x00 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0" "0,1"
bitfld.long 0x00 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0" "0,1"
newline
bitfld.long 0x00 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0" "0,1"
bitfld.long 0x00 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0" "0,1"
newline
bitfld.long 0x00 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0" "0,1"
bitfld.long 0x00 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xE80++0x03
line.long 0x00 "INTR_I2C_EC,Externally clocked I2C interrupt request"
bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xE80++0x03
line.long 0x00 "INTR_I2C_EC,Externally clocked I2C interrupt request register"
bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1"
group.long 0xE88++0x03
line.long 0x00 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask register"
bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xE88++0x03
line.long 0x00 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0xE8C++0x03
line.long 0x00 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0xE8C++0x03
line.long 0x00 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked register"
bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1"
group.long 0xEC0++0x03
line.long 0x00 "INTR_SPI_EC,Externally clocked SPI interrupt request register"
bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xEC0++0x03
line.long 0x00 "INTR_SPI_EC,Externally clocked SPI interrupt request"
bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xEC8++0x03
line.long 0x00 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask register"
bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xEC8++0x03
line.long 0x00 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0xECC++0x03
line.long 0x00 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked register"
bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100smax")
rgroup.long 0xECC++0x03
line.long 0x00 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF00++0x03
line.long 0x00 "INTR_M,Master interrupt request register"
bitfld.long 0x00 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent and the transmit FIFO and shift register are empty" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,I2C master STOP" "0,1"
bitfld.long 0x00 2. "I2C_ACK,I2C master acknowledgement" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,I2C master negative acknowledgement" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF00++0x03
line.long 0x00 "INTR_M,Master interrupt request"
bitfld.long 0x00 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence" "0,1"
newline
bitfld.long 0x00 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,I2C master STOP" "0,1"
bitfld.long 0x00 2. "I2C_ACK,I2C master acknowledgement" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,I2C master negative acknowledgement" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF04++0x03
line.long 0x00 "INTR_M_SET,Master interrupt set request register"
bitfld.long 0x00 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF04++0x03
line.long 0x00 "INTR_M_SET,Master interrupt set request"
bitfld.long 0x00 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF08++0x03
line.long 0x00 "INTR_M_MASK,Master interrupt mask register"
bitfld.long 0x00 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF08++0x03
line.long 0x00 "INTR_M_MASK,Master interrupt mask"
bitfld.long 0x00 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0xF0C++0x03
line.long 0x00 "INTR_M_MASKED,Master interrupt masked request"
bitfld.long 0x00 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 9. "SPI_DONE,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0xF0C++0x03
line.long 0x00 "INTR_M_MASKED,Master interrupt masked request register"
bitfld.long 0x00 9. "SPI_DONE,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF40++0x03
line.long 0x00 "INTR_S,Slave interrupt request"
bitfld.long 0x00 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence" "0,1"
newline
bitfld.long 0x00 16. "I2C_RESTART,I2C slave RESTART received" "0,1"
bitfld.long 0x00 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer" "0,1"
newline
bitfld.long 0x00 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred" "0,1"
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred" "0,1"
newline
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition)" "0,1"
bitfld.long 0x00 7. "I2C_GENERAL,I2C slave general call address received" "0,1"
newline
bitfld.long 0x00 6. "I2C_ADDR_MATCH,I2C slave matching address received" "0,1"
bitfld.long 0x00 5. "I2C_START,I2C slave START received" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed)" "0,1"
bitfld.long 0x00 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed)" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,I2C slave acknowledgement received" "0,1"
bitfld.long 0x00 1. "I2C_NACK,I2C slave negative acknowledgement received" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1')" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF40++0x03
line.long 0x00 "INTR_S,Slave interrupt request register"
bitfld.long 0x00 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer" "0,1"
bitfld.long 0x00 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred" "0,1"
newline
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition)" "0,1"
newline
bitfld.long 0x00 7. "I2C_GENERAL,I2C slave general call address received" "0,1"
bitfld.long 0x00 6. "I2C_ADDR_MATCH,I2C slave matching address received" "0,1"
newline
bitfld.long 0x00 5. "I2C_START,I2C slave START received" "0,1"
bitfld.long 0x00 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed)" "0,1"
newline
bitfld.long 0x00 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed)" "0,1"
bitfld.long 0x00 2. "I2C_ACK,I2C slave acknowledgement received" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,I2C slave negative acknowledgement received" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1')" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF44++0x03
line.long 0x00 "INTR_S_SET,Slave interrupt set request"
bitfld.long 0x00 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF44++0x03
line.long 0x00 "INTR_S_SET,Slave interrupt set request register"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF48++0x03
line.long 0x00 "INTR_S_MASK,Slave interrupt mask"
bitfld.long 0x00 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "I2C_START,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF48++0x03
line.long 0x00 "INTR_S_MASK,Slave interrupt mask register"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "I2C_START,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0xF4C++0x03
line.long 0x00 "INTR_S_MASKED,Slave interrupt masked request register"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 7. "I2C_GENERAL,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 5. "I2C_START,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100smax")
rgroup.long 0xF4C++0x03
line.long 0x00 "INTR_S_MASKED,Slave interrupt masked request"
bitfld.long 0x00 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 16. "I2C_RESTART,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 7. "I2C_GENERAL,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 5. "I2C_START,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
group.long 0xF80++0x03
line.long 0x00 "INTR_TX,Transmitter interrupt request"
bitfld.long 0x00 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line" "0,1"
bitfld.long 0x00 9. "UART_DONE,UART transmitter done event" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode" "0,1"
bitfld.long 0x00 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full TX FIFO" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,TX FIFO is empty i.e" "0,1"
bitfld.long 0x00 1. "NOT_FULL,TX FIFO is not full" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF80++0x03
line.long 0x00 "INTR_TX,Transmitter interrupt request register"
bitfld.long 0x00 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line" "0,1"
bitfld.long 0x00 9. "UART_DONE,UART transmitter done event" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode" "0,1"
bitfld.long 0x00 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full TX FIFO" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,TX FIFO is empty i.e" "0,1"
bitfld.long 0x00 1. "NOT_FULL,TX FIFO is not full" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL" "0,1"
group.long 0xF84++0x03
line.long 0x00 "INTR_TX_SET,Transmitter interrupt set request register"
bitfld.long 0x00 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF84++0x03
line.long 0x00 "INTR_TX_SET,Transmitter interrupt set request"
bitfld.long 0x00 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xF88++0x03
line.long 0x00 "INTR_TX_MASK,Transmitter interrupt mask register"
bitfld.long 0x00 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xF88++0x03
line.long 0x00 "INTR_TX_MASK,Transmitter interrupt mask"
bitfld.long 0x00 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0xF8C++0x03
line.long 0x00 "INTR_TX_MASKED,Transmitter interrupt masked request register"
bitfld.long 0x00 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 9. "UART_DONE,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100smax")
rgroup.long 0xF8C++0x03
line.long 0x00 "INTR_TX_MASKED,Transmitter interrupt masked request"
bitfld.long 0x00 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 9. "UART_DONE,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 8. "UART_NACK,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 4. "EMPTY,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 1. "NOT_FULL,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
group.long 0xFC0++0x03
line.long 0x00 "INTR_RX,Receiver interrupt request"
bitfld.long 0x00 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,LIN baudrate detection is completed" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Parity error in received data frame" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Frame error in received data frame" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full RX FIFO" "0,1"
bitfld.long 0x00 3. "FULL,RX FIFO is full" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,RX FIFO is not empty" "0,1"
bitfld.long 0x00 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xFC0++0x03
line.long 0x00 "INTR_RX,Receiver interrupt request register"
bitfld.long 0x00 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,LIN baudrate detection is completed" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Parity error in received data frame" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Frame error in received data frame" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full RX FIFO" "0,1"
bitfld.long 0x00 3. "FULL,RX FIFO is full" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,RX FIFO is not empty" "0,1"
bitfld.long 0x00 0. "TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xFC4++0x03
line.long 0x00 "INTR_RX_SET,Receiver interrupt set request"
bitfld.long 0x00 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 3. "FULL,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
group.long 0xFC4++0x03
line.long 0x00 "INTR_RX_SET,Receiver interrupt set request register"
bitfld.long 0x00 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 3. "FULL,Write with '1' to set corresponding bit in interrupt status register" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long 0xFC8++0x03
line.long 0x00 "INTR_RX_MASK,Receiver interrupt mask register"
bitfld.long 0x00 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 3. "FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
endif
sif cpuis("psoc4100smax")
group.long 0xFC8++0x03
line.long 0x00 "INTR_RX_MASK,Receiver interrupt mask"
bitfld.long 0x00 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 3. "FULL,Mask bit for corresponding bit in interrupt request register" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long 0xFCC++0x03
line.long 0x00 "INTR_RX_MASKED,Receiver interrupt masked request"
bitfld.long 0x00 11. "BREAK_DETECT,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 3. "FULL,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
endif
sif cpuis("psoc4100s")||cpuis("psoc4100sp")||cpuis("psoc4100sp256kb")
rgroup.long 0xFCC++0x03
line.long 0x00 "INTR_RX_MASKED,Receiver interrupt masked request register"
bitfld.long 0x00 11. "BREAK_DETECT,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 10. "BAUD_DETECT,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 9. "PARITY_ERROR,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 8. "FRAME_ERROR,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 3. "FULL,Logical and of corresponding request and mask bits" "0,1"
newline
bitfld.long 0x00 2. "NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1"
endif
tree.end
repeat.end
endif
tree.end
tree "SPCIF (Flash Control Interface)"
base ad:0x40110000
group.long 0x00++0x03
line.long 0x00 "GEOMETRY,Flash/NVL geometry information"
bitfld.long 0x00 31. "DE_CPD_LP,0': SRAM busy wait loop has not been copied" "0,1"
hexmask.long.byte 0x00 24.--30. 1. "NVL,NVLatch size in Byte multiples (chip dependent): '0': 0 Bytes '1': 1 Byte"
newline
rbitfld.long 0x00 22.--23. "FLASH_ROW,Page size in 64 Byte multiples (chip dependent): '0': 64 byte '1': 128 byte '2': 192 byte '3': 256 byte The page size is used to detemine the number of Bytes in a page for Flash page based operations (e.g. PGM_PAGE)" "0,1,2,3"
rbitfld.long 0x00 20.--21. "NUM_FLASH,Number of flash macros (chip dependent): '0': 1 flash macro '1': 2 flash macros '2': 3 flash macros '3': 4 flash macros" "0,1,2,3"
newline
rbitfld.long 0x00 14.--19. "SFLASH,Supervisory flash capacity in 256 Byte multiples (chip dependent)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 0.--13. 1. "FLASH,Regular flash capacity in 256 Byte multiples (chip dependent)"
group.long 0x1C++0x03
line.long 0x00 "NVL_WR_DATA,NVL write data register"
hexmask.long.byte 0x00 0.--7. 1. "DATA,Data to be written to NVLatch array"
group.long 0x7F0++0x03
line.long 0x00 "INTR,SPCIF interrupt request register"
bitfld.long 0x00 0. "TIMER,Timer counter value reaches '0'" "0,1"
group.long 0x7F4++0x03
line.long 0x00 "INTR_SET,SPCIF interrupt set request register"
bitfld.long 0x00 0. "TIMER,Write INTR_SET field with '1' to set corresponding INTR field" "0,1"
group.long 0x7F8++0x03
line.long 0x00 "INTR_MASK,SPCIF interrupt mask register"
bitfld.long 0x00 0. "TIMER,Mask for corresponding field in INTR register" "0,1"
rgroup.long 0x7FC++0x03
line.long 0x00 "INTR_MASKED,SPCIF interrupt masked request register"
bitfld.long 0x00 0. "TIMER,Logical and of corresponding request and mask fields" "0,1"
tree.end
tree "SRSSLT (System Resources Lite Subsystem)"
base ad:0x40030000
group.long 0x00++0x03
line.long 0x00 "PWR_CONTROL,Power Mode Control"
bitfld.long 0x00 23. "EXT_VCCD,Always write 0 except as noted below" "0,1"
rbitfld.long 0x00 18.--19. "SPARE,Spare AHB readback bits that are hooked to PWR_PWRSYS_TRIM1.SPARE_TRIM[1:0] through spare logic equivalent to bitwise inversion" "0,1,2,3"
newline
bitfld.long 0x00 17. "OVER_TEMP_THRESH,Over-temperature threshold" "0: TEMP_HIGH condition occurs between 120C and..,1: TEMP_HIGH condition occurs between 60C and 75C"
bitfld.long 0x00 16. "OVER_TEMP_EN,Enables the die over temperature sensor" "0,1"
newline
rbitfld.long 0x00 5. "LPM_READY,Indicates whether the low power mode regulator is ready to enter DEEPSLEEP mode" "0: If DEEPSLEEP mode is requested device will..,1: Normal operation"
rbitfld.long 0x00 4. "DEBUG_SESSION,Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)" "0: No debug session active,1: Debug session is active"
newline
rbitfld.long 0x00 0.--3. "POWER_MODE,Current power mode of the device" "0: RESET state,1: ACTIVE state,2: SLEEP state,3: DEEP_SLEEP state,?..."
group.long 0x04++0x03
line.long 0x00 "PWR_KEY_DELAY,Power System Key&Delay Register"
hexmask.long.word 0x00 0.--9. 1. "WAKEUP_HOLDOFF,Delay to wait for references to settle on wakeup from deepsleep"
group.long 0x0C++0x03
line.long 0x00 "PWR_DDFT_SELECT,Power DDFT Mode Selection Register"
bitfld.long 0x00 4.--7. "DDFT1_SEL,Select signal for power DDFT output #1" "0: WAKEUP,1: AWAKE,2: ACT_POWER_EN,3: ACT_POWER_UP,4: ACT_POWER_GOOD,5: ACT_REF_VALID,6: ACT_REG_VALID,7: ACT_COMP_OUT,8: ACT_TEMP_HIGH,9: DPSLP_COMP_OUT,10: DPSLP_POWER_UP,11: AWAKE_DELAYED,12: LPM_READY,13: SLEEPHOLDACK_N,14: 1'b0,15: 1'b1"
bitfld.long 0x00 0.--3. "DDFT0_SEL,Select signal for power DDFT output #0" "0: WAKEUP,1: AWAKE,2: ACT_POWER_EN,3: ACT_POWER_UP,4: ACT_POWER_GOOD,5: srss_adft_control_act_ref_en,6: srss_adft_control_act_comp_en,7: srss_adft_control_dpslp_ref_en,8: srss_adft_control_dpslp_reg_en,9: srss_adft_control_dpslp_comp_en,10: pwr_control_over_temp_en,11: SLEEPHOLDREQ_N,12: ADFT_BUF_EN,13: ATPG observe point (no functional purpose),14: 1'b0,15: 1'b1"
group.long 0x14++0x03
line.long 0x00 "TST_MODE,Test Mode Control Register"
bitfld.long 0x00 31. "TEST_MODE," "0,1"
rbitfld.long 0x00 30. "TEST_KEY_DFT_EN,This bit is set when a XRES test mode key is shifted in" "0,1"
newline
bitfld.long 0x00 28. "BLOCK_ALT_XRES,Relevant only for parts that have the alternate XRES mechanism of overloading a GPIO pin temporarily as alternate XRES during test" "0,1"
rbitfld.long 0x00 2. "SWD_CONNECTED," "0,1"
group.long 0x28++0x03
line.long 0x00 "CLK_SELECT,Clock Select Register"
bitfld.long 0x00 6.--7. "SYSCLK_DIV,Select clk_sys prescaler value" "0: clk_sys= clk_hf/1,1: clk_sys= clk_hf/2,2: clk_sys= clk_hf/4,3: clk_sys= clk_hf/8"
bitfld.long 0x00 4.--5. "PUMP_SEL,Selects clock source for charge pump clock" "0: No clock connect to gnd,1: Use main IMO output,2: Use clk_hf (using selected source after..,?..."
newline
bitfld.long 0x00 2.--3. "HFCLK_DIV,Selects clk_hf predivider value" "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8"
bitfld.long 0x00 0.--1. "HFCLK_SEL,Selects a source for clk_hf and dsi_in[0]" "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator or PLL..,?..."
group.long 0x2C++0x03
line.long 0x00 "CLK_ILO_CONFIG,ILO Configuration"
bitfld.long 0x00 31. "ENABLE,Master enable for ILO oscillator" "0,1"
group.long 0x30++0x03
line.long 0x00 "CLK_IMO_CONFIG,IMO Configuration"
bitfld.long 0x00 31. "ENABLE,Master enable for IMO oscillator" "0,1"
group.long 0x34++0x03
line.long 0x00 "CLK_DFT_SELECT,Clock DFT Mode Selection Register"
bitfld.long 0x00 14. "DFT_EDGE1,Edge sensitivity for in-line divider on output #1 (only relevant when DIV1>0)" "0: Use posedge for divider,1: Use negedge for divider"
bitfld.long 0x00 12.--13. "DFT_DIV1,DFT Output Divide Down" "0: Direct Output,1: Divide by 2,2: Divide by 4,3: Divide by 8"
newline
bitfld.long 0x00 8.--11. "DFT_SEL1,Select signal for DFT output #1" "0: Disabled - output is 0,1: clk_ilo,2: clk_imo,3: clk_eco,4: clk_ext,5: clk_hf,6: clk_lf,7: clk_sys,8: clk_pump,9: clk_slpctrl,?..."
bitfld.long 0x00 6. "DFT_EDGE0,Edge sensitivity for in-line divider on output #0 (only relevant when DIV0>0)" "0: Use posedge for divider,1: Use negedge for divider"
newline
bitfld.long 0x00 4.--5. "DFT_DIV0,DFT Output Divide Down" "0: Direct Output,1: Divide by 2,2: Divide by 4,3: Divide by 8"
bitfld.long 0x00 0.--3. "DFT_SEL0,Select signal for DFT output #0" "0: Disabled - output is 0,1: clk_ilo,2: clk_imo,3: clk_eco,4: clk_ext,5: clk_hf,6: clk_lf,7: clk_sys,8: clk_pump,9: clk_slpctrl,?..."
group.long 0x38++0x03
line.long 0x00 "WDT_DISABLE_KEY,Watchdog Disable Key Register"
hexmask.long 0x00 0.--31. 1. "KEY,Disables WDT reset when equal to 0xACED8865"
rgroup.long 0x3C++0x03
line.long 0x00 "WDT_COUNTER,Watchdog Counter Register"
hexmask.long.word 0x00 0.--15. 1. "COUNTER,Current value of WDT Counter"
group.long 0x40++0x03
line.long 0x00 "WDT_MATCH,Watchdog Match Register"
bitfld.long 0x00 16.--19. "IGNORE_BITS,The number of MSB bits of the watchdog timer that are NOT checked against MATCH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "MATCH,Match value for Watchdog counter"
group.long 0x44++0x03
line.long 0x00 "SRSS_INTR,SRSS Interrupt Register"
bitfld.long 0x00 1. "TEMP_HIGH,Regulator over-temp interrupt" "0,1"
bitfld.long 0x00 0. "WDT_MATCH,WDT Interrupt Request" "0,1"
group.long 0x48++0x03
line.long 0x00 "SRSS_INTR_SET,SRSS Interrupt Set Register"
bitfld.long 0x00 1. "TEMP_HIGH,Writing 1 to this bit internally sets the overtemp interrupt" "0,1"
group.long 0x4C++0x03
line.long 0x00 "SRSS_INTR_MASK,SRSS Interrupt Mask Register"
bitfld.long 0x00 1. "TEMP_HIGH,Masks REG_OVERTEMP interrupt" "0,1"
bitfld.long 0x00 0. "WDT_MATCH,Clearing this bit will not forward the interrupt to the CPU" "0,1"
group.long 0x54++0x03
line.long 0x00 "RES_CAUSE,Reset Cause Observation Register"
bitfld.long 0x00 4. "RESET_SOFT,Cortex-M0 requested a system reset through it's SYSRESETREQ" "0,1"
bitfld.long 0x00 3. "RESET_PROT_FAULT,A protection violation occurred that requires a RESET" "0,1"
newline
bitfld.long 0x00 0. "RESET_WDT,A WatchDog Timer reset has occurred since last power cycle" "0,1"
group.long 0xF00++0x03
line.long 0x00 "PWR_BG_TRIM1,Bandgap Trim Register"
bitfld.long 0x00 0.--5. "REF_VTRIM,Trims the bandgap reference voltage output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF04++0x03
line.long 0x00 "PWR_BG_TRIM2,Bandgap Trim Register"
bitfld.long 0x00 0.--5. "REF_ITRIM,Trims the bandgap reference current output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0xF08++0x03
line.long 0x00 "CLK_IMO_SELECT,IMO Frequency Select Register"
bitfld.long 0x00 0.--2. "FREQ,Select operating frequency" "0: IMO runs at 24 MHz,1: IMO runs at 28 MHz,2: IMO runs at 32 MHz,3: IMO runs at 36 MHz,4: IMO runs at 40 MHz,5: IMO runs at 44 MHz,6: IMO runs at 48 MHz,?..."
group.long 0xF0C++0x03
line.long 0x00 "CLK_IMO_TRIM1,IMO Trim Register"
hexmask.long.byte 0x00 0.--7. 1. "OFFSET,Frequency trim bits"
group.long 0xF10++0x03
line.long 0x00 "CLK_IMO_TRIM2,IMO Trim Register"
bitfld.long 0x00 0.--2. "FSOFFSET,Frequency trim bits" "0,1,2,3,4,5,6,7"
group.long 0xF14++0x03
line.long 0x00 "PWR_PWRSYS_TRIM1,Power System Trim Register"
bitfld.long 0x00 4.--7. "SPARE_TRIM,Active-Reference temperature compensation trim (repurposed from spare bits)" "0: TC = 0 (unchanged),1: TC = -50ppm/C,?,?,?,?,?,?,?,?,10: TC = -80ppm/C,11: TC = +150ppm/C,?..."
bitfld.long 0x00 0.--3. "DPSLP_REF_TRIM,Trims the DeepSleep reference that is used by the DeepSleep regulator and DeepSleep power comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xF18++0x03
line.long 0x00 "CLK_IMO_TRIM3,IMO Trim Register"
bitfld.long 0x00 5.--6. "TCTRIM,IMO temperature compesation trim" "0,1,2,3"
bitfld.long 0x00 0.--4. "STEPSIZE,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
tree "TCPWM (Timer/Counter/PWM)"
sif cpuis("CY8C4146P*")||cpuis("CY8C4146L*")
base ad:0x40060000
elif cpuis("CY8C4149*")||cpuis("CY8C4147*")||cpuis("CY8C4146A*")||cpuis("CY8C4148*")
base ad:0x40200000
endif
sif cpuis("psoc4100smax")
group.long 0x00++0x03
line.long 0x00 "CTRL,TCPWM control register 0"
hexmask.long.byte 0x00 0.--7. 1. "COUNTER_ENABLED,Counter enables for counters 0 up to CNT_NR-1"
group.long 0x08++0x03
line.long 0x00 "CMD,TCPWM command register"
hexmask.long.byte 0x00 24.--31. 1. "COUNTER_START,Counters SW start trigger"
hexmask.long.byte 0x00 16.--23. 1. "COUNTER_STOP,Counters SW stop trigger"
newline
hexmask.long.byte 0x00 8.--15. 1. "COUNTER_RELOAD,Counters SW reload trigger"
hexmask.long.byte 0x00 0.--7. 1. "COUNTER_CAPTURE,Counters SW capture trigger"
rgroup.long 0x0C++0x03
line.long 0x00 "INTR_CAUSE,TCPWM Counter interrupt cause register"
hexmask.long.byte 0x00 0.--7. 1. "COUNTER_INT,Counters interrupt signal active"
endif
repeat 8. (increment 0 1)(increment 0 0x40)
tree "CNT[$1]"
sif cpuis("psoc4100smax")
group.long ($2+0x100)++0x03
line.long 0x00 "CTRL,Counter control register"
bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,?,2: Capture mode,3: Quadrature encoding mode,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,?..."
bitfld.long 0x00 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4)" "0: X1 encoding (QUAD mode),1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),?..."
newline
bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1"
bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')"
newline
hexmask.long.byte 0x00 8.--15. 1. "GENERIC,Generic 8-bit control field"
bitfld.long 0x00 3. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1"
newline
bitfld.long 0x00 2. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1"
bitfld.long 0x00 1. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1"
newline
bitfld.long 0x00 0. "AUTO_RELOAD_CC,Specifies switching of the CC and buffered CC values" "0,1"
rgroup.long ($2+0x104)++0x03
line.long 0x00 "STATUS,Counter status register"
bitfld.long 0x00 31. "RUNNING,When '0' the counter is NOT running" "0,1"
hexmask.long.byte 0x00 8.--15. 1. "GENERIC,Generic 8-bit counter field"
newline
bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1"
group.long ($2+0x108)++0x03
line.long 0x00 "COUNTER,Counter count register"
hexmask.long.word 0x00 0.--15. 1. "COUNTER,16-bit counter value"
group.long ($2+0x10C)++0x03
line.long 0x00 "CC,Counter compare/capture register"
hexmask.long.word 0x00 0.--15. 1. "CC,In CAPTURE mode captures the counter value"
group.long ($2+0x110)++0x03
line.long 0x00 "CC_BUFF,Counter buffered compare/capture register"
hexmask.long.word 0x00 0.--15. 1. "CC,Additional buffer for counter CC register"
group.long ($2+0x114)++0x03
line.long 0x00 "PERIOD,Counter period register"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,Period value: upper value of the counter"
group.long ($2+0x118)++0x03
line.long 0x00 "PERIOD_BUFF,Counter buffered period register"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,Additional buffer for counter PERIOD register"
group.long ($2+0x120)++0x03
line.long 0x00 "TR_CTRL0,Counter trigger control register 0"
bitfld.long 0x00 16.--19. "START_SEL,Selects one of the 16 input triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long ($2+0x124)++0x03
line.long 0x00 "TR_CTRL1,Counter trigger control register 1"
bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
newline
bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
newline
bitfld.long 0x00 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is"
group.long ($2+0x128)++0x03
line.long 0x00 "TR_CTRL2,Counter trigger control register 2"
bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
newline
bitfld.long 0x00 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE"
group.long ($2+0x130)++0x03
line.long 0x00 "INTR,Interrupt request register"
bitfld.long 0x00 1. "CC_MATCH,Counter matches CC register event" "0,1"
bitfld.long 0x00 0. "TC,Terminal count event" "0,1"
group.long ($2+0x134)++0x03
line.long 0x00 "INTR_SET,Interrupt set request register"
bitfld.long 0x00 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1"
group.long ($2+0x138)++0x03
line.long 0x00 "INTR_MASK,Interrupt mask register"
bitfld.long 0x00 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1"
bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1"
rgroup.long ($2+0x13C)++0x03
line.long 0x00 "INTR_MASKED,Interrupt masked request register"
bitfld.long 0x00 1. "CC_MATCH,Logical and of corresponding request and mask bits" "0,1"
bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1"
endif
tree.end
repeat.end
tree.end
tree "WCO (32KHz Oscillator)"
sif cpuis("CY8C4146P*")||cpuis("CY8C4146L*")
base ad:0x40070000
elif cpuis("CY8C4149*")||cpuis("CY8C4147*")||cpuis("CY8C4146A*")||cpuis("CY8C4148*")
base ad:0x40220000
endif
group.long 0x00++0x03
line.long 0x00 "CONFIG,WCO Configuration Register"
bitfld.long 0x00 31. "IP_ENABLE,Master enable for IP - disables both WCO and DPLL" "0,1"
bitfld.long 0x00 30. "DPLL_ENABLE,Enable DPLL operation" "0,1"
newline
hexmask.long.byte 0x00 16.--23. 1. "ENBUS,Test Mode Control bits enbus[7] - N/A enbus[6]"
bitfld.long 0x00 2. "EXT_INPUT_EN,Disables the load resistor and allows external clock input for pad_xin" "0,1"
newline
bitfld.long 0x00 1. "LPM_AUTO,Automatically control low power mode (only relevant when LPM_EN=0)" "0: Do not enter low power mode (LPM) in DeepSleep,1: Enter low power mode (LPM) in DeepSleep"
bitfld.long 0x00 0. "LPM_EN,Force block into Low Power Mode" "0: Do not force low power mode (LPM) on,1: Force low power mode (LPM) on"
rgroup.long 0x04++0x03
line.long 0x00 "STATUS,WCO Status Register"
bitfld.long 0x00 0. "OUT_BLNK_A,Indicates that output has transitioned - This bit is intended for Test Mode Only and is not a reliable indicator" "0,1"
group.long 0x08++0x03
line.long 0x00 "DPLL,WCO DPLL Register"
hexmask.long.byte 0x00 22.--29. 1. "DPLL_LF_LIMIT,Maximum IMO offset allowed (used to prevent DPLL dynamics from selecting an IMO frequency that the logic cannot support)"
bitfld.long 0x00 19.--21. "DPLL_LF_PGAIN,DPLL Loop Filter Proportionial Gain Setting" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "DPLL_LF_IGAIN,DPLL Loop Filter Integral Gain Setting" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 0.--10. 1. "DPLL_MULT,Multiplier to determine IMO frequency in multiples of the WCO frequency Fimo = (DPLL_MULT + 1) * Fwco"
rgroup.long 0x200++0x03
line.long 0x00 "WDT_CTRLOW,Watchdog Counters 0/1"
hexmask.long.word 0x00 16.--31. 1. "WDT_CTR1,Current value of WDT Counter 1"
hexmask.long.word 0x00 0.--15. 1. "WDT_CTR0,Current value of WDT Counter 0"
rgroup.long 0x204++0x03
line.long 0x00 "WDT_CTRHIGH,Watchdog Counter 2"
hexmask.long 0x00 0.--31. 1. "WDT_CTR2,Current value of WDT Counter 2"
group.long 0x208++0x03
line.long 0x00 "WDT_MATCH,Watchdog counter match values"
hexmask.long.word 0x00 16.--31. 1. "WDT_MATCH1,Match value for Watchdog Counter 1"
hexmask.long.word 0x00 0.--15. 1. "WDT_MATCH0,Match value for Watchdog Counter 0"
group.long 0x20C++0x03
line.long 0x00 "WDT_CONFIG,Watchdog Counters Configuration"
bitfld.long 0x00 30.--31. "LFCLK_SEL,N/A" "0,1,2,3"
bitfld.long 0x00 24.--28. "WDT_BITS2,Bit to observe for WDT_INT2" "0: Assert when bit0 of WDT_CTR2 toggles (one int,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: Assert when bit31 of WDT_CTR2 toggles (one int"
newline
bitfld.long 0x00 16. "WDT_MODE2,Watchdog Counter 2 Mode" "0: Free running counter with no interrupt requests,1: Free running counter with interrupt request.."
bitfld.long 0x00 11. "WDT_CASCADE1_2,Cascade Watchdog Counters 1 2" "0: Independent counters,1: Cascaded counters"
newline
bitfld.long 0x00 10. "WDT_CLEAR1,Clear Watchdog Counter when WDT_CTR1=WDT_MATCH1" "0: Free running counter,1: Clear on match"
bitfld.long 0x00 8.--9. "WDT_MODE1,Watchdog Counter Action on Match (WDT_CTR1=WDT_MATCH1)" "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset - Not Supported - here for..,3: Assert WDT_INTx assert WDT Reset after 3rd.."
newline
bitfld.long 0x00 3. "WDT_CASCADE0_1,Cascade Watchdog Counters 0 1" "0: Independent counters,1: Cascaded counters"
bitfld.long 0x00 2. "WDT_CLEAR0,Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0" "0: Free running counter,1: Clear on match"
newline
bitfld.long 0x00 0.--1. "WDT_MODE0,Watchdog Counter Action on Match (WDT_CTR0=WDT_MATCH0)" "0: Do nothing,1: Assert WDT_INTx,2: Assert WDT Reset - Not Supported - here for..,3: Assert WDT_INTx assert WDT Reset after 3rd.."
group.long 0x210++0x03
line.long 0x00 "WDT_CONTROL,Watchdog Counters Control"
bitfld.long 0x00 19. "WDT_RESET2,Resets counter 2 back to 0000_0000" "0,1"
bitfld.long 0x00 18. "WDT_INT2,WDT Interrupt Request" "0,1"
newline
rbitfld.long 0x00 17. "WDT_ENABLED2,Indicates actual state of counter" "0,1"
bitfld.long 0x00 16. "WDT_ENABLE2,Enable Counter 2" "0: Counter is disabled (not clocked),1: Counter is enabled (counting up)"
newline
bitfld.long 0x00 11. "WDT_RESET1,Resets counter 1 back to 0000" "0,1"
bitfld.long 0x00 10. "WDT_INT1,WDT Interrupt Request" "0,1"
newline
rbitfld.long 0x00 9. "WDT_ENABLED1,Indicates actual state of counter" "0,1"
bitfld.long 0x00 8. "WDT_ENABLE1,Enable Counter 1" "0: Counter is disabled (not clocked),1: Counter is enabled (counting up)"
newline
bitfld.long 0x00 3. "WDT_RESET0,Resets counter 0 back to 0000" "0,1"
bitfld.long 0x00 2. "WDT_INT0,WDT Interrupt Request" "0,1"
newline
rbitfld.long 0x00 1. "WDT_ENABLED0,Indicates actual state of counter" "0,1"
bitfld.long 0x00 0. "WDT_ENABLE0,Enable Counter 0" "0: Counter is disabled (not clocked),1: Counter is enabled (counting up)"
group.long 0x214++0x03
line.long 0x00 "WDT_CLKEN,Watchdog Counters Clock Enable"
bitfld.long 0x00 1. "CLK_ILO_EN_FOR_WDT,Enables the ILO clock for use by the WDT logic" "0,1"
bitfld.long 0x00 0. "CLK_WCO_EN_FOR_WDT,Enables the WCO clock for use by the WDT logic" "0,1"
group.long 0xF00++0x03
line.long 0x00 "TRIM,WCO Trim Register"
bitfld.long 0x00 4.--5. "LPM_GM,GM setting for LPM (bandwidth = DC/ms) - Used when WCO.LPM_AUTO=0 or when LPM_AUTO=1 and not in DeepSleep mode" "0,1,2,3"
bitfld.long 0x00 0.--2. "XGM,Amplifier GM setting - Used when WCO.LPM_AUTO=0 or when LPM_AUTO=1 and not in DeepSleep mode" "0,1,2,3,4,5,6,7"
tree.end
autoindent.off
newline
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