17482 lines
1.3 MiB
17482 lines
1.3 MiB
; --------------------------------------------------------------------------------
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; @Title: CY8C4XXX On-Chip Peripherals
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; @Props: Released
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; @Author: BFG
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; @Changelog: 2017-07-25 BFG
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; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation
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; @Doc: CY8C4Axx_PSoC_Analog_Coprocessor_Registers_Technical_Reference_Manual.pdf(Rev. **, 2015-12-18)
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; PSoC_Analog_Coprocessor_Architecture_TRM.pdf(Rev. **, 2015-12-18)
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; PSOC_ANALOG_COPROCESSOR_CY8C4AXX_FAMILY_DATASHEET_PROGRAMMABLE_SYSTEM-ON-CHIP_PSOC_0.pdf(Rev. *E, 2015-07-30)
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; @Chip: CY8C4A24AZI-433, CY8C4A24AZI-443, CY8C4A24FNI-443, CY8C4A24LQI-443,
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; CY8C4A24PVI-431, CY8C4A24PVI-441, CY8C4A25AZI-473, CY8C4A25AZI-483,
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; CY8C4A25FNI-473, CY8C4A25FNI-483, CY8C4A25LQI-473, CY8C4A25LQI-483,
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; CY8C4A25PVI-471, CY8C4A25PVI-481, CY8C4A45AZI-473, CY8C4A45AZI-483,
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; CY8C4A45FNI-473, CY8C4A45FNI-483, CY8C4A45LQI-473, CY8C4A45LQI-483,
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; CY8C4A45PVI-471, CY8C4A45PVI-481
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; @Core: Cortex-M0P
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perpsoc.per 8461 2017-11-06 14:38:10Z askoncej $
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config 16. 8.
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width 0x0B
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; Known Problems:
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; MODULE REGISTER DESCRIPTION
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; --------------------------------------------------------------------------------
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; DSAB PASS_DSAB_DSAB_CTRL SEL_OUT [8:11]: No truth tables
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; CM0P SCR No such module in percortexm0p.ph
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; SFLASH AV_PAIRS_8B84 & CSDV2_CSD1_ADC_TRIM1 Registers have the same address
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; SFLASH AV_PAIRS_8B85 & CSDV2_CSD1_ADC_TRIM2 Registers have the same address
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; CTB2 No address specified for module
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; only CTB0&CTB1 have register map
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; CTB3 No address specified for module
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; only CTB0&CTB1 have register map
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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textline " "
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|
textline " "
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|
endif
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|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
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group.long 0xD9C++0x03 "Region 2"
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saveout 0xD98 %l 0x2
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|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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|
textline " "
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|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "AROUTE"
|
|
base ad:0x40380000
|
|
width 24.
|
|
if (((per.l(ad:0x40380000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Global AROUTE Control"
|
|
bitfld.long 0x00 31. " ENABLED ,AROUTE enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DEEPSLEEP_ON ,AROUTE during DeepSleep power mode enable" "Disabled,Enabled"
|
|
group.long 0x10++0x0F
|
|
line.long 0x00 "SARMUXVPLUS_SW,Sarmux_vplus Switch Control"
|
|
bitfld.long 0x00 24. " SMP_SRP ,Connect sarmux_vplus to sar_vplus" "Not connected,Connected"
|
|
bitfld.long 0x00 17. " SMP_AU1 ,Connect sarmux_vplus to acore_u1" "Not connected,Connected"
|
|
bitfld.long 0x00 7. " SMP_U1O1 ,Connect sarmux_vplus to uab1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x00 6. " SMP_U1O0 ,Connect sarmux_vplus to uab1_vout0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SMP_C1O1 ,Connect sarmux_vplus to ctb1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x00 4. " SMP_C1O0 ,Connect sarmux_vplus to ctb1_vout0" "Not connected,Connected"
|
|
bitfld.long 0x00 3. " SMP_U0O1 ,Connect sarmux_vplus to uab0_vout1" "Not connected,Connected"
|
|
bitfld.long 0x00 2. " SMP_U0D0 ,Connect sarmux_vplus to uab0_vout0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SMP_C0O1 ,Connect sarmux_vplus to ctb0 _vout1" "Not connected,Connected"
|
|
bitfld.long 0x00 0. " SMP_C0O0 ,Connect sarmux_vplus to ctb0_vout0" "Not connected,Connected"
|
|
line.long 0x04 "SARMUXVPLUS_SW_CLR,Sarmux_vplus Switch Control Clear"
|
|
eventfld.long 0x04 24. " SMP_SRP ,Connect sarmux_vplus to sar_vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 17. " SMP_AU1 ,Connect sarmux_vplus to acore_u1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 7. " SMP_U1O1 ,Connect sarmux_vplus to uab1_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 6. " SMP_U1O0 ,Connect sarmux_vplus to uab1_vout0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 5. " SMP_C1O1 ,Connect sarmux_vplus to ctb1_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 4. " SMP_C1O0 ,Connect sarmux_vplus to ctb1_vout0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 3. " SMP_U0O1 ,Connect sarmux_vplus to uab0_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " SMP_U0D0 ,Connect sarmux_vplus to uab0_vout0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 1. " SMP_C0O1 ,Connect sarmux_vplus to ctb0 _vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 0. " SMP_C0O0 ,Connect sarmux_vplus to ctb0_vout0" "Not cleared,Cleared"
|
|
line.long 0x08 "SARMUXVMINUS_SW,Sarmux_vminus Switch Control"
|
|
bitfld.long 0x08 31. " VSSA_SRM ,Connect vssa to sar_vminus" "Not connected,Connected"
|
|
bitfld.long 0x08 25. " SMM_SRM ,Connect sarmux_vminus to sar_vminus" "Not connected,Connected"
|
|
bitfld.long 0x08 18. " SMM_AU2 ,Connect sarmux_vminus to acore_u2" "Not connected,Connected"
|
|
bitfld.long 0x08 16. " SMM_AU0 ,Connect sarmux_vminus to acore_u0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x08 7. " SMM_U1O1 ,Connect sarmux_vminus to uab1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x08 6. " SMM_U1O0 ,Connect sarmux_vminus to uab1_vout0" "Not connected,Connected"
|
|
bitfld.long 0x08 5. " SMM_C1O1 ,Connect sarmux_vminus to ctb1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x08 4. " SMM_C1O0 ,Connect sarmux_vminus to ctb1_vout0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SMM_U0O1 ,Connect sarmux_vminus to uab0_vout1" "Not connected,Connected"
|
|
bitfld.long 0x08 2. " SMM_U0O0 ,Connect sarmux_vminus to uab0_vout0" "Not connected,Connected"
|
|
bitfld.long 0x08 1. " SMM_C0O1 ,Connect sarmux_vminus to ctb0_vout1" "Not connected,Connected"
|
|
bitfld.long 0x08 0. " SMM_C0O0 ,Connect sarmux_vminus to ctb0_vout0" "Not connected,Connected"
|
|
line.long 0x0C "SARMUXVMINUS_SW_CLR,Sarmux_vminus Switch Control Clear"
|
|
eventfld.long 0x0C 31. " VSSA_SRM ,Connect vssa to sar_vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 25. " SMM_SRM ,Connect sarmux_vminus to sar_vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 18. " SMM_AU2 ,Connect sarmux_vminus to acore_u2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 16. " SMM_AU0 ,Connect sarmux_vminus to acore_u0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 7. " SMM_U1O1 ,Connect sarmux_vminus to uab1_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 6. " SMM_U1O0 ,Connect sarmux_vminus to uab1_vout0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 5. " SMM_C1O1 ,Connect sarmux_vminus to ctb1_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 4. " SMM_C1O0 ,Connect sarmux_vminus to ctb1_vout0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 3. " SMM_U0O1 ,Connect sarmux_vminus to uab0_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 2. " SMM_U0O0 ,Connect sarmux_vminus to uab0_vout0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 1. " SMM_C0O1 ,Connect sarmux_vminus to ctb0_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 0. " SMM_C0O0 ,Connect sarmux_vminus to ctb0_vout0" "Not cleared,Cleared"
|
|
group.long 0x20++0x1F
|
|
line.long 0x00 "SARMUXCOREIO0_SW,Sarmux_coreio0 Switch Control"
|
|
bitfld.long 0x00 25. " SMC0_SRM ,Connect sarmux_coreio0 to sar_vminus" "Not connected,Connected"
|
|
bitfld.long 0x00 24. " SMC0_SRP ,Connect sarmux_coreio0 to sar_vplus" "Not connected,Connected"
|
|
bitfld.long 0x00 18. " SMC0_AU2 ,Connect sarmux_coreio0 to acore_u2" "Not connected,Connected"
|
|
bitfld.long 0x00 4. " SMC0_C1O0 ,Connect sarmux_coreio0 to ctb1_vout0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SMC0_C0O0 ,Connect sarmux_coreio0 to ctb0_vout0" "Not connected,Connected"
|
|
line.long 0x04 "SARMUXCOREIO0_SW_CLR,Sarmux_coreio0 Switch Control Clear"
|
|
eventfld.long 0x04 25. " SMC0_SRM ,Clear sarmux_coreio0 to sar_vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 24. " SMC0_SRP ,Clear sarmux_coreio0 to sar_vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 18. " SMC0_AU2 ,Clear sarmux_coreio0 to acore_u2" "Not cleared,Cleared"
|
|
eventfld.long 0x04 4. " SMC0_C1O0 ,Clear sarmux_coreio0 to ctb1_vout0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 0. " SMC0_C0O0 ,Clear sarmux_coreio0 to ctb0_vout0" "Not cleared,Cleared"
|
|
line.long 0x08 "SARMUXCOREIO1_SW,Sarmux_coreio1 Switch Control"
|
|
bitfld.long 0x08 25. " SMC1_SRM ,Connect sarmux_coreio1 to sar_vminus" "Not connected,Connected"
|
|
bitfld.long 0x08 24. " SMC1_SRP ,Connect sarmux_coreio1 to sar_vplus" "Not connected,Connected"
|
|
bitfld.long 0x08 5. " SMC1_C1O1 ,Connect sarmux_coreio1 to ctb1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x08 1. " SMC1_C0O1 ,Connect sarmux_coreio1 to ctb0_vout1" "Not connected,Connected"
|
|
line.long 0x0C "SARMUXCOREIO1_SW_CLR,Sarmux_coreio1 Switch Control"
|
|
eventfld.long 0x0C 25. " SMC1_SRM ,Clear sarmux_coreio1 to sar_vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 24. " SMC1_SRP ,Clear sarmux_coreio1 to sar_vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 5. " SMC1_C1O1 ,Clear sarmux_coreio1 to ctb1_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 1. " SMC1_C0O1 ,Clear sarmux_coreio1 to ctb0_vout1" "Not cleared,Cleared"
|
|
line.long 0x10 "SARMUXCOREIO2_SW,Sarmux_coreio2 Switch Control"
|
|
bitfld.long 0x10 25. " SMC2_SRM ,Connect sarmux_coreio2 to sar_vminus" "Not connected,Connected"
|
|
bitfld.long 0x10 24. " SMC2_SRP ,Connect sarmux_coreio2 to sar_vplus" "Not connected,Connected"
|
|
bitfld.long 0x10 16. " SMC2_AU0 ,Connect sarmux_coreio2 to acore_u0" "Not connected,Connected"
|
|
bitfld.long 0x10 6. " SMC2_U1O0 ,Connect sarmux_coreio2 to uab1_vout0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x10 2. " SMC2_U0O0 ,Connect sarmux_coreio2 to uab0_vout0" "Not connected,Connected"
|
|
line.long 0x14 "SARMUXCOREIO2_SW_CLR,Sarmux_coreio2 Switch Control Clear"
|
|
eventfld.long 0x14 25. " SMC2_SRM ,Clear sarmux_coreio2 to sar_vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x14 24. " SMC2_SRP ,Clear sarmux_coreio2 to sar_vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x14 16. " SMC2_AU0 ,Clear sarmux_coreio2 to acore_u0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 6. " SMC2_U1O0 ,Clear sarmux_coreio2 to uab1_vout0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 2. " SMC2_U0O0 ,Clear sarmux_coreio2 to uab0_vout0" "Not cleared,Cleared"
|
|
line.long 0x18 "SARMUXCOREIO3_SW,Sarmux_coreio3 Switch Control"
|
|
bitfld.long 0x18 25. " SMC3_SRM ,Connect sarmux_coreio3 to sar_vminus" "Not connected,Connected"
|
|
bitfld.long 0x18 24. " SMC3_SRP ,Connect sarmux_coreio3 to sar_vplus" "Not connected,Connected"
|
|
bitfld.long 0x18 17. " SMC3_AU1 ,Connect sarmux_coreio3 to acore_u1" "Not connected,Connected"
|
|
bitfld.long 0x18 7. " SMC3_U1O1 ,Connect sarmux_coreio3 to uab1_vout1" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x18 3. " SMC3_U0O1 ,Connect sarmux_coreio3 to uab0_vout1" "Not connected,Connected"
|
|
line.long 0x1C "SARMUXCOREIO3_SW_CLR,Sarmux_coreio3 Switch Control Clear"
|
|
eventfld.long 0x1C 25. " SMC3_SRM ,Clear sarmux_coreio3 to sar_vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x1C 24. " SMC3_SRP ,Clear sarmux_coreio3 to sar_vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x1C 17. " SMC3_AU1 ,Clear sarmux_coreio3 to acore_u1" "Not cleared,Cleared"
|
|
eventfld.long 0x1C 7. " SMC3_U1O1 ,Clear sarmux_coreio3 to uab1_vout1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x1C 3. " SMC3_U0O1 ,Clear sarmux_coreio3 to uab0_vout1" "Not cleared,Cleared"
|
|
group.long 0x40++0x0F
|
|
line.long 0x00 "SARAROUTEVREF_SW,Sar_aroute_vef Switch Control"
|
|
bitfld.long 0x00 18. " SRV_AU2 ,Connect sar_aroute_vref to acore_u2" "Not connected,Connected"
|
|
bitfld.long 0x00 16. " SRV_AU0 ,Connect sar_aroute_vref to acore_u0" "Not connected,Connected"
|
|
line.long 0x04 "SARAROUTEVREF_SW_CLR,Sar_aroute_vref Switch Control Clear"
|
|
eventfld.long 0x04 18. " SRV_AU2 ,Clear sar_aroute_vref to acore_u2" "Not cleared,Cleared"
|
|
eventfld.long 0x04 16. " SRV_AU0 ,Clear sar_aroute_vref to acore_u0" "Not cleared,Cleared"
|
|
line.long 0x08 "SARAROUTEVDDA_SW,Sar_aroute_vdda Switch Control"
|
|
bitfld.long 0x08 17. " VDA_AU1 ,Connect sar_aroute_vdda to acore_u1" "Not connected,Connected"
|
|
bitfld.long 0x08 16. " VDA_AU0 ,Connect sar_aroute_vdda to acore_u0" "Not connected,Connected"
|
|
line.long 0x0C "SARAROUTEVDDA_SW_CLR,Sar_aroute_vdda Switch Control Clear"
|
|
eventfld.long 0x0C 17. " VDA_AU1 ,Clear sar_aroute_vdda to acore_u1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 16. " VDA_AU0 ,Clear sar_aroute_vdda to acore_u0" "Not cleared,Cleared"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SARMUX_SW_HW_CTRL,AROUTE SARMUX VPLUS/VMINUS Hardware Control"
|
|
bitfld.long 0x00 31. " SW_VSSA ,Software VSSA" "0,1"
|
|
bitfld.long 0x00 16. " SW_AU0 ,Software AU0" "0,1"
|
|
bitfld.long 0x00 7. " SW_U1O1 ,Software U1O1" "0,1"
|
|
bitfld.long 0x00 6. " SW_U1O0 ,Software U1O0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SW_C1O1 ,Software C1O1" "0,1"
|
|
bitfld.long 0x00 4. " SW_C1O0 ,Software C1O0" "0,1"
|
|
bitfld.long 0x00 3. " SW_U0O1 ,Software U0O1" "0,1"
|
|
bitfld.long 0x00 2. " SW_U0O1 ,Software U0O0" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SW_C0O1 ,Software C0O1" "0,1"
|
|
bitfld.long 0x00 0. " SW_C0O0 ,Software C0O0" "0,1"
|
|
rgroup.long 0x64++0x07
|
|
line.long 0x00 "SARMUXVPLUS_SW_STATUS,AROUTE SARMUX VPLUS Switch Control Status"
|
|
bitfld.long 0x00 24. " SW_SRP ,Connect sarmux_vplus to sar_vplus" "Not connected,Connected"
|
|
bitfld.long 0x00 17. " SW_AU1 ,Connect sarmux_vplus to acore_u1" "Not connected,Connected"
|
|
bitfld.long 0x00 7. " SW_U1O1 ,Connect sarmux_vplus to uab1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x00 6. " SW_U1O0 ,Connect sarmux_vplus to uab1_vout0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SW_C1O1 ,Connect sarmux_vplus to ctb1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x00 4. " SW_C1O0 ,Connect sarmux_vplus to ctb1_vout0" "Not connected,Connected"
|
|
bitfld.long 0x00 3. " SW_U0O1 ,Connect sarmux_vplus to uab0_vout1" "Not connected,Connected"
|
|
bitfld.long 0x00 2. " SW_U0D0 ,Connect sarmux_vplus to uab0_vout0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SW_C0O1 ,Connect sarmux_vplus to ctb0 _vout1" "Not connected,Connected"
|
|
bitfld.long 0x00 0. " SW_C0O0 ,Connect sarmux_vplus to ctb0_vout0" "Not connected,Connected"
|
|
line.long 0x04 "SARMUXVMINUS_SW_STATUS,AROUTE SAR VMINUS Switch Control Status"
|
|
bitfld.long 0x04 31. " SW_VSSA ,Connect vssa to sar_vminus" "Not connected,Connected"
|
|
bitfld.long 0x04 25. " SW_SRM ,Connect sarmux_vminus to sar_vminus" "Not connected,Connected"
|
|
bitfld.long 0x04 18. " SW_AU2 ,Connect sarmux_vminus to acore_u2" "Not connected,Connected"
|
|
bitfld.long 0x04 16. " SW_AU0 ,Connect sarmux_vminus to acore_u0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x04 7. " SW_U1O1 ,Connect sarmux_vminus to uab1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x04 6. " SW_U1O0 ,Connect sarmux_vminus to uab1_vout0" "Not connected,Connected"
|
|
bitfld.long 0x04 5. " SW_C1O1 ,Connect sarmux_vminus to ctb1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x04 4. " SW_C1O0 ,Connect sarmux_vminus to ctb1_vout0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SW_U0O1 ,Connect sarmux_vminus to uab0_vout1" "Not connected,Connected"
|
|
bitfld.long 0x04 2. " SW_U0O0 ,Connect sarmux_vminus to uab0_vout0" "Not connected,Connected"
|
|
bitfld.long 0x04 1. " SW_C0O1 ,Connect sarmux_vminus to ctb0_vout1" "Not connected,Connected"
|
|
bitfld.long 0x04 0. " SW_C0O0 ,Connect sarmux_vminus to ctb0_vout0" "Not connected,Connected"
|
|
group.long 0x100++0x4F
|
|
line.long 0x00 "UAB0VIN00_SW,Uab0_vin00 Switch Control"
|
|
bitfld.long 0x00 17. " U0I00_AU1 ,Connect uab0_vin00 to acore_u1" "Not connected,Connected"
|
|
bitfld.long 0x00 6. " U0I00_U1O0 ,Connect uab0_vin00 to uab1_vout0" "Not connected,Connected"
|
|
bitfld.long 0x00 1. " U0I00_C0O1 ,Connect uab0_vin00 to ctb0_vout1" "Not connected,Connected"
|
|
line.long 0x04 "UAB0VIN00_SW_CLR,Uab0_vin00 Switch Control Clear"
|
|
eventfld.long 0x04 17. " U0I00_AU1 ,Clear uab0_vin00 to acore_u1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 6. " U0I00_U1O0 ,Clear uab0_vin00 to uab1_vout0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 1. " U0I00_C0O1 ,Clear uab0_vin00 to ctb0_vout1" "Not cleared,Cleared"
|
|
line.long 0x08 "UAB0VIN01_SW,Uab0_vin01 Control"
|
|
bitfld.long 0x08 18. " U0I01_AU2 ,Connect uab0_vin01 to acore_u2" "Not connected,Connected"
|
|
bitfld.long 0x08 16. " U0I01_AU0 ,Connect uab0_vin01 to acore_u0" "Not connected,Connected"
|
|
bitfld.long 0x08 7. " U0I01_U1O1 ,Connect uab0_vin01 to uab1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x08 5. " U0I01_C1O1 ,Connect uab0_vin01 to ctb1_vout1" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x08 0. " U0I01_C0O0 ,Connect uab0_vin01 to ctb0_vout0" "Not connected,Connected"
|
|
line.long 0x0C "UAB0VIN01_SW_CLR,Uab0_vin01 Switch Control Clear"
|
|
eventfld.long 0x0C 18. " U0I01_AU2 ,Clear uab0_vin01 to acore_u2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 16. " U0I01_AU0 ,Clear uab0_vin01 to acore_u0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 7. " U0I01_U1O1 ,Clear uab0_vin01 to uab1_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 5. " U0I01_C1O1 ,Clear uab0_vin01 to ctb1_vout1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 0. " U0I01_C0O0 ,Clear uab0_vin01 to ctb0_vout0" "Not cleared,Cleared"
|
|
line.long 0x10 "UAB0VIN02_SW,Uab0_vin02 Switch Control"
|
|
bitfld.long 0x10 31. " U0I02_C0C2 ,Connect uab0_vin02 to ctb0_ctbus2" "Not connected,Connected"
|
|
bitfld.long 0x10 17. " U0I02_AU1 ,Connect uab0_vin02 to acore_u1" "Not connected,Connected"
|
|
bitfld.long 0x10 4. " U0I02_C1O0 ,Connect uab0_vin02 to ctb1_vout0" "Not connected,Connected"
|
|
bitfld.long 0x10 3. " U0I02_U0O1 ,Connect uab0_vin02 to uab0_vout1" "Not connected,Connected"
|
|
line.long 0x14 "UAB0VIN02_SW_CLR,Uab0_vin02 Switch Control Clear"
|
|
eventfld.long 0x14 31. " U0I02_C0C2 ,Clear uab0_vin02 to ctb0_ctbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 17. " U0I02_AU1 ,Clear uab0_vin02 to acore_u1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 4. " U0I02_C1O0 ,Clear uab0_vin02 to ctb1_vout0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 3. " U0I02_U0O1 ,Clear uab0_vin02 to uab0_vout1" "Not cleared,Cleared"
|
|
line.long 0x18 "UAB0VIN03_SW,Uab0_vin03 Switch Control"
|
|
bitfld.long 0x18 31. " U0I03_C0C1 ,Connect uab0_vin03 to ctb0_ctbus1" "Not connected,Connected"
|
|
bitfld.long 0x18 30. " U0I03_U0I10 ,Connect uab0_vin03 to uab0_vin10" "Not connected,Connected"
|
|
bitfld.long 0x18 18. " U0I03_AU2 ,Connect uab0_vin03 to acore_u2" "Not connected,Connected"
|
|
bitfld.long 0x18 16. " U0I03_AU0 ,Connect uab0_vin03 to uab1_vout0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x18 6. " U0I03_U1O0 ,Connect uab0_vin03 to uab0_vout0" "Not connected,Connected"
|
|
bitfld.long 0x18 2. " U0I03_U1O0 ,Connect uab0_vin03 to uab0_vout0" "Not connected,Connected"
|
|
bitfld.long 0x18 1. " U0I03_C0O1 ,Connect uab0_vin03 to ctb0_vout1" "Not connected,Connected"
|
|
line.long 0x1C "UAB0VIN03_SW_CLR,Uab0_vin03 Switch Control Clear"
|
|
eventfld.long 0x1C 31. " U0I03_C0C1 ,Clear uab0_vin03 to ctb0_ctbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x1C 30. " U0I03_U0I10 ,Clear uab0_vin03 to uab0_vin10" "Not cleared,Cleared"
|
|
eventfld.long 0x1C 18. " U0I03_AU2 ,Clear uab0_vin03 to acore_u2" "Not cleared,Cleared"
|
|
eventfld.long 0x1C 16. " U0I03_AU0 ,Clear uab0_vin03 to uab1_vout0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x1C 6. " U0I03_U1O0 ,Clear uab0_vin03 to uab0_vout0" "Not cleared,Cleared"
|
|
eventfld.long 0x1C 2. " U0I03_U1O0 ,Clear uab0_vin03 to uab0_vout0" "Not cleared,Cleared"
|
|
eventfld.long 0x1C 1. " U0I03_C0O1 ,Clear uab0_vin03 to ctb0_vout1" "Not cleared,Cleared"
|
|
line.long 0x20 "UAB0VIN10_SW,Uab0_vin10 Switch Control"
|
|
bitfld.long 0x20 31. " U0I10_C0C0 ,Connect uab0_vin10 to ctb0_ctbus0" "Not connected,Connected"
|
|
bitfld.long 0x20 17. " U0I10_AU1 ,Connect uab0_vin10 to acore_u1" "Not connected,Connected"
|
|
bitfld.long 0x20 7. " U0I10_U1O1 ,Connect uab0_vin10 to uab1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x20 5. " U0I10_C1O1 ,Connect uab0_vin10 to ctb1_vout1" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x20 3. " U0I10_U0O1 ,Connect uab0_vin10 to uab0_vout1" "Not connected,Connected"
|
|
bitfld.long 0x20 0. " U0I10_C0O0 ,Connect uab0_vin10 to ctb0_vout0" "Not connected,Connected"
|
|
line.long 0x24 "UAB0VIN10_SW_CLR,Uab0_vin10 Switch Control Clear"
|
|
eventfld.long 0x24 31. " U0I10_C0C0 ,Clear uab0_vin10 to ctb0_ctbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x24 17. " U0I10_AU1 ,Clear uab0_vin10 to acore_u1" "Not cleared,Cleared"
|
|
eventfld.long 0x24 7. " U0I10_U1O1 ,Clear uab0_vin10 to uab1_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x24 5. " U0I10_C1O1 ,Clear uab0_vin10 to ctb1_vout1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x24 3. " U0I10_U0O1 ,Clear uab0_vin10 to uab0_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x24 0. " U0I10_C0O0 ,Clear uab0_vin10 to ctb0_vout0" "Not cleared,Cleared"
|
|
line.long 0x28 "UAB0VIN11_SW,Uab0_vin11 Switch Control"
|
|
bitfld.long 0x28 31. " U0I11_C0C3 ,Connect uab0_vin11 to ctb0_ctbus3" "Not connected,Connected"
|
|
bitfld.long 0x28 18. " U0I11_AU2 ,Connect uab0_vin11 to acore_u2" "Not connected,Connected"
|
|
bitfld.long 0x28 16. " U0I11_AU0 ,Connect uab0_vin11 to acore_u0" "Not connected,Connected"
|
|
bitfld.long 0x28 4. " U0I11_C1O0 ,Connect uab0_vin11 to ctb1_vout0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x28 2. " U0I11_U0O0 ,Connect uab0_vin11 to uab0_vout0" "Not connected,Connected"
|
|
line.long 0x2C "UAB0VIN11_SW_CLR,Uab0_vin11 Switch Control Clear"
|
|
eventfld.long 0x2C 31. " U0I11_C0C3 ,Clear uab0_vin11 to ctb0_ctbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x2C 18. " U0I11_AU2 ,Clear uab0_vin11 to acore_u2" "Not cleared,Cleared"
|
|
eventfld.long 0x2C 16. " U0I11_AU0 ,Clear uab0_vin11 to acore_u0" "Not cleared,Cleared"
|
|
eventfld.long 0x2C 4. " U0I11_C1O0 ,Clear uab0_vin11 to ctb1_vout0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x2C 2. " U0I11_U0O0 ,Clear uab0_vin11 to uab0_vout0" "Not cleared,Cleared"
|
|
line.long 0x30 "UAB0VIN12_SW,Uab0_vin12 Switch Control"
|
|
bitfld.long 0x30 17. " U0I12_AU1 ,Connect uab0_vin12 to acore_u1" "Not connected,Connected"
|
|
bitfld.long 0x30 6. " U0I12_U1O0 ,Connect uab0_vin12 to uab1_vout0" "Not connected,Connected"
|
|
bitfld.long 0x30 1. " U0I12_C0O1 ,Connect uab0_vin12 to ctb0_vout1" "Not connected,Connected"
|
|
line.long 0x34 "UAB0VIN12_SW_CLR,Uab0_vin12 Switch Control Clear"
|
|
eventfld.long 0x34 17. " U0I12_AU1 ,Clear uab0_vin12 to acore_u1" "Not cleared,Cleared"
|
|
eventfld.long 0x34 6. " U0I12_U1O0 ,Clear uab0_vin12 to uab1_vout0" "Not cleared,Cleared"
|
|
eventfld.long 0x34 1. " U0I12_C0O1 ,Clear uab0_vin12 to ctb0_vout1" "Not cleared,Cleared"
|
|
line.long 0x38 "UAB0VIN13_SW,Uab0_vin13 Switch Control"
|
|
bitfld.long 0x38 18. " U0I13_AU2 ,Connect uab0_vin13 to acore_u2" "Not connected,Connected"
|
|
bitfld.long 0x38 16. " U0I13_AU0 ,Connect uab0_vin13 to acore_u0" "Not connected,Connected"
|
|
bitfld.long 0x38 7. " U0I13_U1O1 ,Connect uab0_vin13 to uab1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x38 5. " U0I13_C1O1 ,Connect uab0_vin13 to ctb1_vout1" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x38 0. " U0I13_C0O0 ,Connect uab0_vin13 to ctb0_vout0" "Not connected,Connected"
|
|
line.long 0x3C "UAB0VIN13_SW_CLR,Uab0_vin13 Switch Control Clear"
|
|
eventfld.long 0x3C 18. " U0I13_AU2 ,Clear uab0_vin13 to acore_u2" "Not cleared,Cleared"
|
|
eventfld.long 0x3C 16. " U0I13_AU0 ,Clear uab0_vin13 to acore_u0" "Not cleared,Cleared"
|
|
eventfld.long 0x3C 7. " U0I13_U1O1 ,Clear uab0_vin13 to uab1_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x3C 5. " U0I13_C1O1 ,Clear uab0_vin13 to ctb1_vout1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x3C 0. " U0I13_C0O0 ,Clear uab0_vin13 to ctb0_vout0" "Not cleared,Cleared"
|
|
line.long 0x40 "CTB0VREF_SW,Ctb0_vref0 Switch Control"
|
|
bitfld.long 0x40 19. " C0V1_V3 ,Connect ctb0_vref1 to vref3" "Not connected,Connected"
|
|
bitfld.long 0x40 18. " C0V1_V2 ,Connect ctb0_vref1 to vref2" "Not connected,Connected"
|
|
bitfld.long 0x40 17. " C0V1_V1 ,Connect ctb0_vref1 to vref1" "Not connected,Connected"
|
|
bitfld.long 0x40 16. " C0V1_V0 ,Connect ctb0_vref1 to vref0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x40 3. " C0V0_V3 ,Connect ctb0_vref0 to vref3" "Not connected,Connected"
|
|
bitfld.long 0x40 2. " C0V0_V2 ,Connect ctb0_vref0 to vref2" "Not connected,Connected"
|
|
bitfld.long 0x40 1. " C0V0_V1 ,Connect ctb0_vref0 to vref1" "Not connected,Connected"
|
|
bitfld.long 0x40 0. " C0V0_V0 ,Connect ctb0_vref0 to vref0" "Not connected,Connected"
|
|
line.long 0x44 "CTB0VREF_SW_CLR,Ctb0_vref0 Switch Control Clear"
|
|
eventfld.long 0x44 19. " C0V1_V3 ,Clear ctb0_vref1 to vref3" "Not cleared,Cleared"
|
|
eventfld.long 0x44 18. " C0V1_V2 ,Clear ctb0_vref1 to vref2" "Not cleared,Cleared"
|
|
eventfld.long 0x44 17. " C0V1_V1 ,Clear ctb0_vref1 to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x44 16. " C0V1_V0 ,Clear ctb0_vref1 to vref0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x44 3. " C0V0_V3 ,Clear ctb0_vref0 to vref3" "Not cleared,Cleared"
|
|
eventfld.long 0x44 2. " C0V0_V2 ,Clear ctb0_vref0 to vref2" "Not cleared,Cleared"
|
|
eventfld.long 0x44 1. " C0V0_V1 ,Clear ctb0_vref0 to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x44 0. " C0V0_V0 ,Clear ctb0_vref0 to vref0" "Not cleared,Cleared"
|
|
line.long 0x48 "UAB0VREF_SW,Uab0_vref00 Switch Control"
|
|
bitfld.long 0x48 27. " U0V11_V3 ,Connect uab0_vref11 to vref3" "Not connected,Connected"
|
|
bitfld.long 0x48 26. " U0V11_V2 ,Connect uab0_vref11 to vref2" "Not connected,Connected"
|
|
bitfld.long 0x48 25. " U0V11_V1 ,Connect uab0_vref11 to vref1" "Not connected,Connected"
|
|
bitfld.long 0x48 24. " U0V11_V0 ,Connect uab0_vref11 to vref0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x48 19. " U0V10_V3 ,Connect uab0_vref10 to vref3" "Not connected,Connected"
|
|
bitfld.long 0x48 18. " U0V10_V2 ,Connect uab0_vref10 to vref2" "Not connected,Connected"
|
|
bitfld.long 0x48 17. " U0V10_V1 ,Connect uab0_vref10 to vref1" "Not connected,Connected"
|
|
bitfld.long 0x48 16. " U0V10_V0 ,Connect uab0_vref10 to vref0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x48 11. " U0V01_V3 ,Connect uab0_vref01 to vref3" "Not connected,Connected"
|
|
bitfld.long 0x48 10. " U0V01_V2 ,Connect uab0_vref01 to vref2" "Not connected,Connected"
|
|
bitfld.long 0x48 9. " U0V01_V1 ,Connect uab0_vref01 to vref1" "Not connected,Connected"
|
|
bitfld.long 0x48 8. " U0V01_V0 ,Connect uab0_vref01 to vref0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x48 3. " U0V00_V3 ,Connect uab0_vref00 to vref3" "Not connected,Connected"
|
|
bitfld.long 0x48 2. " U0V00_V2 ,Connect uab0_vref00 to vref2" "Not connected,Connected"
|
|
bitfld.long 0x48 1. " U0V00_V1 ,Connect uab0_vref00 to vref1" "Not connected,Connected"
|
|
bitfld.long 0x48 0. " U0V00_V0 ,Connect uab0_vref00 to vref0" "Not connected,Connected"
|
|
line.long 0x4C "UAB0VREF_SW_CLR,Uab0_vref00 Switch Control Clear"
|
|
eventfld.long 0x4C 27. " U0V11_V3 ,Clear uab0_vref11 to vref3" "Not cleared,Cleared"
|
|
eventfld.long 0x4C 26. " U0V11_V2 ,Clear uab0_vref11 to vref2" "Not cleared,Cleared"
|
|
eventfld.long 0x4C 25. " U0V11_V1 ,Clear uab0_vref11 to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x4C 24. " U0V11_V0 ,Clear uab0_vref11 to vref0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x4C 19. " U0V10_V3 ,Clear uab0_vref10 to vref3" "Not cleared,Cleared"
|
|
eventfld.long 0x4C 18. " U0V10_V2 ,Clear uab0_vref10 to vref2" "Not cleared,Cleared"
|
|
eventfld.long 0x4C 17. " U0V10_V1 ,Clear uab0_vref10 to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x4C 16. " U0V10_V0 ,Clear uab0_vref10 to vref0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x4C 11. " U0V01_V3 ,Clear uab0_vref01 to vref3" "Not cleared,Cleared"
|
|
eventfld.long 0x4C 10. " U0V01_V2 ,Clear uab0_vref01 to vref2" "Not cleared,Cleared"
|
|
eventfld.long 0x4C 9. " U0V01_V1 ,Clear uab0_vref01 to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x4C 8. " U0V01_V0 ,Clear uab0_vref01 to vref0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x4C 3. " U0V00_V3 ,Clear uab0_vref00 to vref3" "Not cleared,Cleared"
|
|
eventfld.long 0x4C 2. " U0V00_V2 ,Clear uab0_vref00 to vref2" "Not cleared,Cleared"
|
|
eventfld.long 0x4C 1. " U0V00_V1 ,Clear uab0_vref00 to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x4C 0. " U0V00_V0 ,Clear uab0_vref00 to vref0" "Not cleared,Cleared"
|
|
group.long 0x180++0x47
|
|
line.long 0x00 "UAB1VIN00_SW,Uab1_vin00 Switch Control"
|
|
bitfld.long 0x00 18. " U1I00_AU2 ,Connect uab1_vin00 to acore_u2" "Not connected,Connected"
|
|
bitfld.long 0x00 16. " U1I00_AU0 ,Connect uab1_vin00 to acore_u2" "Not connected,Connected"
|
|
bitfld.long 0x00 5. " U1I00_C1O1 ,Connect uab1_vin00 to ctb1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x00 2. " U1I00_U0O0 ,Connect uab1_vin00 to uab0_vout0" "Not connected,Connected"
|
|
line.long 0x04 "UAB1VIN00_SW_CLR,Uab1_vin00 Switch Control Clear"
|
|
eventfld.long 0x04 18. " U1I00_AU2 ,Clear uab1_vin00 to acore_u2" "Not cleared,Cleared"
|
|
eventfld.long 0x04 16. " U1I00_AU0 ,Clear uab1_vin00 to acore_u2" "Not cleared,Cleared"
|
|
eventfld.long 0x04 5. " U1I00_C1O1 ,Clear uab1_vin00 to ctb1_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " U1I00_U0O0 ,Clear uab1_vin00 to uab0_vout0" "Not cleared,Cleared"
|
|
line.long 0x08 "UAB1VIN01_SW,Uab1_vin01 Switch Control"
|
|
bitfld.long 0x08 17. " U1I01_AU1 ,Connect uab1_vin01 to acore_u1" "Not connected,Connected"
|
|
bitfld.long 0x08 4. " U1I01_C1O0 ,Connect uab1_vin01 to ctb1_vout0" "Not connected,Connected"
|
|
bitfld.long 0x08 3. " U1I01_U0O1 ,Connect uab1_vin01 to uab0_vout1" "Not connected,Connected"
|
|
bitfld.long 0x08 1. " U1I01_C0O1 ,Connect uab1_vin01 to ctb0_vout1" "Not connected,Connected"
|
|
line.long 0x0C "UAB1VIN01_SW_CLR,Uab1_vin01 Switch Control Clear"
|
|
eventfld.long 0x0C 17. " U1I01_AU1 ,Clear uab1_vin01 to acore_u1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 4. " U1I01_C1O0 ,Clear uab1_vin01 to ctb1_vout0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 3. " U1I01_U0O1 ,Clear uab1_vin01 to uab0_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 1. " U1I01_C0O1 ,Clear uab1_vin01 to ctb0_vout1" "Not cleared,Cleared"
|
|
line.long 0x10 "UAB1VIN02_SW,Uab1_vin02 Switch Control"
|
|
bitfld.long 0x10 31. " U1I02_C1C2 ,Connect uab1_vin02 to ctb1_ctbus2" "Not connected,Connected"
|
|
bitfld.long 0x10 18. " U1I02_AU2 ,Connect uab1_vin02 to acore_u2" "Not connected,Connected"
|
|
bitfld.long 0x10 16. " U1I02_AU0 ,Connect uab1_vin02 to acore_u0" "Not connected,Connected"
|
|
bitfld.long 0x10 7. " U1I02_U1O1 ,Connect uab1_vin02 to uab1_vout1" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x10 0. " U1I02_C0O0 ,Connect uab1_vin02 to ctb0_vout0" "Not connected,Connected"
|
|
line.long 0x14 "UAB1VIN02_SW_CLR,Uab1_vin02 Switch Control Clear"
|
|
eventfld.long 0x14 31. " U1I02_C1C2 ,Clear uab1_vin02 to ctb1_ctbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 18. " U1I02_AU2 ,Clear uab1_vin02 to acore_u2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 16. " U1I02_AU0 ,Clear uab1_vin02 to acore_u0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 7. " U1I02_U1O1 ,Clear uab1_vin02 to uab1_vout1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 0. " U1I02_C0O0 ,Clear uab1_vin02 to ctb0_vout0" "Not cleared,Cleared"
|
|
line.long 0x18 "UAB1VIN03_SW,Uab1_vin03 Switch Control"
|
|
bitfld.long 0x18 31. " U1I03_C1C1 ,Connect uab1_vin03 to ctb1_ctbus1" "Not connected,Connected"
|
|
bitfld.long 0x18 30. " U1I03_U1I10 ,Connect uab1_vin03 to uab1_vin10" "Not connected,Connected"
|
|
bitfld.long 0x18 17. " U1I03_AU1 ,Connect uab1_vin03 to acore_u1" "Not connected,Connected"
|
|
bitfld.long 0x18 6. " U1I03_U1O0 ,Connect uab1_vin03 to uab1_vout0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x18 5. " U1I03_C1O1 ,Connect uab1_vin03 to ctb1_vout0" "Not connected,Connected"
|
|
bitfld.long 0x18 2. " U1I03_U0O0 ,Connect uab1_vin03 to uab0_vout0" "Not connected,Connected"
|
|
line.long 0x1C "UAB1VIN03_SW_CLR,Uab1_vin03 Switch Control Clear"
|
|
eventfld.long 0x1C 31. " U1I03_C1C1 ,Clear uab1_vin03 to ctb1_ctbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x1C 30. " U1I03_U1I10 ,Clear uab1_vin03 to uab1_vin10" "Not cleared,Cleared"
|
|
eventfld.long 0x1C 17. " U1I03_AU1 ,Clear uab1_vin03 to acore_u1" "Not cleared,Cleared"
|
|
eventfld.long 0x1C 6. " U1I03_U1O0 ,Clear uab1_vin03 to uab1_vout0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x1C 5. " U1I03_C1O1 ,Clear uab1_vin03 to ctb1_vout0" "Not cleared,Cleared"
|
|
eventfld.long 0x1C 2. " U1I03_U0O0 ,Clear uab1_vin03 to uab0_vout0" "Not cleared,Cleared"
|
|
line.long 0x20 "UAB1VIN10_SW,Uab1_vin10 Switch Control"
|
|
bitfld.long 0x20 31. " U1I10_C1C0 ,Connect uab1_vin10 to ctb1_ctbus0" "Not connected,Connected"
|
|
bitfld.long 0x20 18. " U1I10_AU2 ,Connect uab1_vin10 to acore_u2" "Not connected,Connected"
|
|
bitfld.long 0x20 16. " U1I10_AU0 ,Connect uab1_vin10 to acore_u0" "Not connected,Connected"
|
|
bitfld.long 0x20 7. " U1I10_U1O1 ,Connect uab1_vin10 to uab1_vout1" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x20 4. " U1I10_C1O0 ,Connect uab1_vin10 to ctb1_vout0" "Not connected,Connected"
|
|
bitfld.long 0x20 3. " U1I10_U0O1 ,Connect uab1_vin10 to uab0_vout1" "Not connected,Connected"
|
|
bitfld.long 0x20 1. " U1I10_C0O1 ,Connect uab1_vin10 to ctb0_vout1" "Not connected,Connected"
|
|
line.long 0x24 "UAB1VIN10_SW_CLR,Uab1_vin10 Switch Control Clear"
|
|
eventfld.long 0x24 31. " U1I10_C1C0 ,Clear uab1_vin10 to ctb1_ctbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x24 18. " U1I10_AU2 ,Clear uab1_vin10 to acore_u2" "Not cleared,Cleared"
|
|
eventfld.long 0x24 16. " U1I10_AU0 ,Clear uab1_vin10 to acore_u0" "Not cleared,Cleared"
|
|
eventfld.long 0x24 7. " U1I10_U1O1 ,Clear uab1_vin10 to uab1_vout1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x24 4. " U1I10_C1O0 ,Clear uab1_vin10 to ctb1_vout0" "Not cleared,Cleared"
|
|
eventfld.long 0x24 3. " U1I10_U0O1 ,Clear uab1_vin10 to uab0_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x24 1. " U1I10_C0O1 ,Clear uab1_vin10 to ctb0_vout1" "Not cleared,Cleared"
|
|
line.long 0x28 "UAB1VIN11_SW,Uab1_vin11 Switch Control"
|
|
bitfld.long 0x28 31. " U1I11_C1C3 ,Connect uab1_vin11 to ctb1_ctbus3" "Not connected,Connected"
|
|
bitfld.long 0x28 17. " U1I11_AU1 ,Connect uab1_vin11 to acore_u1" "Not connected,Connected"
|
|
bitfld.long 0x28 6. " U1I11_U1O0 ,Connect uab1_vin11 to uab1_vout0" "Not connected,Connected"
|
|
bitfld.long 0x28 0. " U1I11_C0O0 ,Connect uab1_vin11 to ctb0_vout0" "Not connected,Connected"
|
|
line.long 0x2C "UAB1VIN11_SW_CLR,Uab1_vin11 Switch Control Clear"
|
|
eventfld.long 0x2C 31. " U1I11_C1C3 ,Clear uab1_vin11 to ctb1_ctbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x2C 17. " U1I11_AU1 ,Clear uab1_vin11 to acore_u1" "Not cleared,Cleared"
|
|
eventfld.long 0x2C 6. " U1I11_U1O0 ,Clear uab1_vin11 to uab1_vout0" "Not cleared,Cleared"
|
|
eventfld.long 0x2C 0. " U1I11_C0O0 ,Clear uab1_vin11 to ctb0_vout0" "Not cleared,Cleared"
|
|
line.long 0x30 "UAB1VIN12_SW,Uab1_vin12 Switch Control"
|
|
bitfld.long 0x30 18. " U1I12_AU2 ,Connect uab1_vin12 to acore_u2" "Not connected,Connected"
|
|
bitfld.long 0x30 16. " U1I12_AU0 ,Connect uab1_vin12 to acore_u0" "Not connected,Connected"
|
|
bitfld.long 0x30 5. " U1I12_C1O1 ,Connect uab1_vin12 to ctb1_vout1" "Not connected,Connected"
|
|
bitfld.long 0x30 2. " U1I12_U0O0 ,Connect uab1_vin12 to uab0_vout0" "Not connected,Connected"
|
|
line.long 0x34 "UAB1VIN12_SW_CLR,Uab1_vin12 Switch Control Clear"
|
|
eventfld.long 0x34 18. " U1I12_AU2 ,Clear uab1_vin12 to acore_u2" "Not cleared,Cleared"
|
|
eventfld.long 0x34 16. " U1I12_AU0 ,Clear uab1_vin12 to acore_u0" "Not cleared,Cleared"
|
|
eventfld.long 0x34 5. " U1I12_C1O1 ,Clear uab1_vin12 to ctb1_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x34 2. " U1I12_U0O0 ,Clear uab1_vin12 to uab0_vout0" "Not cleared,Cleared"
|
|
line.long 0x38 "UAB1VIN13_SW,Uab1_vin13 Switch Control"
|
|
bitfld.long 0x38 17. " U1I13_AU1 ,Connect uab1_vin13 to acore_u1" "Not connected,Connected"
|
|
bitfld.long 0x38 4. " U1I13_C1O0 ,Connect uab1_vin13 to ctb1_vout0" "Not connected,Connected"
|
|
bitfld.long 0x38 3. " U1I13_U0O1 ,Connect uab1_vin13 to uab0_vout1" "Not connected,Connected"
|
|
bitfld.long 0x38 1. " U1I13_C0O1 ,Connect uab1_vin13 to ctb0_vout1" "Not connected,Connected"
|
|
line.long 0x3C "UAB1VIN13_SW_CLR,Uab1_vin13 Switch Control Clear"
|
|
eventfld.long 0x3C 17. " U1I13_AU1 ,Clear uab1_vin13 to acore_u1" "Not cleared,Cleared"
|
|
eventfld.long 0x3C 4. " U1I13_C1O0 ,Clear uab1_vin13 to ctb1_vout0" "Not cleared,Cleared"
|
|
eventfld.long 0x3C 3. " U1I13_U0O1 ,Clear uab1_vin13 to uab0_vout1" "Not cleared,Cleared"
|
|
eventfld.long 0x3C 1. " U1I13_C0O1 ,Clear uab1_vin13 to ctb0_vout1" "Not cleared,Cleared"
|
|
line.long 0x40 "CTB1VREF_SW,Ctb1_vref0 Switch Control"
|
|
bitfld.long 0x40 19. " C1V1_V3 ,Connect ctb1_vref1 to vref3" "Not connected,Connected"
|
|
bitfld.long 0x40 18. " C1V1_V2 ,Connect ctb1_vref1 to vref2" "Not connected,Connected"
|
|
bitfld.long 0x40 17. " C1V1_V1 ,Connect ctb1_vref1 to vref1" "Not connected,Connected"
|
|
bitfld.long 0x40 16. " C1V1_V0 ,Connect ctb1_vref1 to vref0" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x40 3. " C1V0_V3 ,Connect ctb1_vref0 to vref3" "Not connected,Connected"
|
|
bitfld.long 0x40 2. " C1V0_V2 ,Connect ctb1_vref0 to vref2" "Not connected,Connected"
|
|
bitfld.long 0x40 1. " C1V0_V1 ,Connect ctb1_vref0 to vref1" "Not connected,Connected"
|
|
bitfld.long 0x40 0. " C1V0_V0 ,Connect ctb1_vref0 to vref0" "Not connected,Connected"
|
|
line.long 0x44 "CTB1VREF_SW_CLR,Ctb1_vref0 Switch Control Clear"
|
|
eventfld.long 0x44 19. " C1V1_V3 ,Clear ctb1_vref1 to vref3" "Not cleared,Cleared"
|
|
eventfld.long 0x44 18. " C1V1_V2 ,Clear ctb1_vref1 to vref2" "Not cleared,Cleared"
|
|
eventfld.long 0x44 17. " C1V1_V1 ,Clear ctb1_vref1 to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x44 16. " C1V1_V0 ,Clear ctb1_vref1 to vref0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x44 3. " C1V0_V3 ,Clear ctb1_vref0 to vref3" "Not cleared,Cleared"
|
|
eventfld.long 0x44 2. " C1V0_V2 ,Clear ctb1_vref0 to vref2" "Not cleared,Cleared"
|
|
eventfld.long 0x44 1. " C1V0_V1 ,Clear ctb1_vref0 to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x44 0. " C1V0_V0 ,Clear ctb1_vref0 to vref0" "Not cleared,Cleared"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Global AROUTE Control"
|
|
bitfld.long 0x00 31. " ENABLED ,AROUTE enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "CNT (TCPWM - Individual Counter)"
|
|
tree "CNT 0"
|
|
base ad:0x40010100
|
|
width 20.
|
|
if (((per.l(ad:0x40010000))&0x1<<0.)==0x1<<0.)
|
|
if (((per.l(ad:0x40010100))&0x7000000)==0x3000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "X1,X2,X4,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
elif (((per.l(ad:0x40010100))&0x7000000)==(0x4000000||0x5000000))
|
|
if (((per.l(ad:0x40010100))&0x7000000)==0x4000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,8-bit generic control field"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
endif
|
|
elif (((per.l(ad:0x40010100))&0x07000000)==0x06000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
elif (((per.l(ad:0x40010100))&0x07000000)==0x00000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
endif
|
|
if (((per.l(ad:0x40010100))&0x7000000)==0x5000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic counter field"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic counter field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
endif
|
|
if (((per.l(ad:0x40010100+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "CC,Counter Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CC ,Counter compare"
|
|
line.long 0x04 "CC_BUFF,Counter Buffered Compare/capture Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CC ,Additional buffer for counter CC register"
|
|
line.long 0x08 "PERIOD,Counter Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERIOD ,Period value"
|
|
line.long 0x0C "PERIOD_BUFF,Counter Buffered Period Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0"
|
|
bitfld.long 0x00 16.--19. " START_SEL ,Selects one of the 16 triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " STOP_SEL ,Selects one of the 16 triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RELOAD_SEL ,Selects one of the 16 triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " COUNT_SEL ,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Selects one of the 16 input trigger as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1"
|
|
bitfld.long 0x04 8.--9. " START_EDGE ,Start event will start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop event will stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Reload event will initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 2.--3. " COUNT_EDGE ,Counter event will increase or decrease the counter by 1" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Capture event will copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2"
|
|
bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Determines the effect of a counter underflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Determines the effect of a counter overflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Determines the effect of a compare match event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " TC ,Terminal count event" "Not detected,Detected"
|
|
line.long 0x04 "INTR_SET,Interrupt Set Request Register"
|
|
bitfld.long 0x04 1. " CC_MATCH ,Set counter matches CC register event" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " TC ,Set terminal count event" "Not detected,Detected"
|
|
line.long 0x08 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register"
|
|
rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CNT 1"
|
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base ad:0x40010140
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width 20.
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if (((per.l(ad:0x40010000))&0x1<<1.)==0x1<<1.)
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if (((per.l(ad:0x40010140))&0x7000000)==0x3000000)
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group.long 0x00++0x03
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line.long 0x00 "CTRL,Counter Control Register"
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bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
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bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "X1,X2,X4,?..."
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bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
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bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
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textline " "
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bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
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elif (((per.l(ad:0x40010140))&0x7000000)==(0x4000000||0x5000000))
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if (((per.l(ad:0x40010140))&0x7000000)==0x4000000)
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group.long 0x00++0x03
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line.long 0x00 "CTRL,Counter Control Register"
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bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
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bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
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bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
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bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
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textline " "
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bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
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bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
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bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
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bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
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textline " "
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bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
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else
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group.long 0x00++0x03
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line.long 0x00 "CTRL,Counter Control Register"
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bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
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bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
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bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
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bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,8-bit generic control field"
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bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
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bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
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bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
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textline " "
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bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
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endif
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elif (((per.l(ad:0x40010140))&0x07000000)==0x06000000)
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group.long 0x00++0x03
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line.long 0x00 "CTRL,Counter Control Register"
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bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
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bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "?..."
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bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
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bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
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textline " "
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bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
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bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
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bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
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textline " "
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bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
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elif (((per.l(ad:0x40010140))&0x07000000)==0x00000000)
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group.long 0x00++0x03
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line.long 0x00 "CTRL,Counter Control Register"
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bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
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bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
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bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
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textline " "
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bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
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bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
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else
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group.long 0x00++0x03
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line.long 0x00 "CTRL,Counter Control Register"
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bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
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bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
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bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
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textline " "
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bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
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endif
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if (((per.l(ad:0x40010140))&0x7000000)==0x5000000)
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rgroup.long 0x04++0x03
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line.long 0x00 "STATUS,Counter Status Register"
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bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
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hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic counter field"
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bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
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else
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rgroup.long 0x04++0x03
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line.long 0x00 "STATUS,Counter Status Register"
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bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
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bitfld.long 0x00 8.--10. " GENERIC ,Generic counter field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
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bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
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endif
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if (((per.l(ad:0x40010140+0x04))&0x80000000)==0x80000000)
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rgroup.long 0x08++0x03
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line.long 0x00 "COUNTER,Counter Count Register"
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hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
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else
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group.long 0x08++0x03
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line.long 0x00 "COUNTER,Counter Count Register"
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hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
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endif
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group.long 0x0C++0x0F
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line.long 0x00 "CC,Counter Compare Register"
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hexmask.long.word 0x00 0.--15. 1. " CC ,Counter compare"
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line.long 0x04 "CC_BUFF,Counter Buffered Compare/capture Register"
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hexmask.long.word 0x04 0.--15. 1. " CC ,Additional buffer for counter CC register"
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line.long 0x08 "PERIOD,Counter Period Register"
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hexmask.long.word 0x08 0.--15. 1. " PERIOD ,Period value"
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line.long 0x0C "PERIOD_BUFF,Counter Buffered Period Register"
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hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register"
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group.long 0x20++0x0B
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line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0"
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bitfld.long 0x00 16.--19. " START_SEL ,Selects one of the 16 triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. " STOP_SEL ,Selects one of the 16 triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " RELOAD_SEL ,Selects one of the 16 triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. " COUNT_SEL ,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Selects one of the 16 input trigger as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1"
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bitfld.long 0x04 8.--9. " START_EDGE ,Start event will start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
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bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop event will stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
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bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Reload event will initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
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bitfld.long 0x04 2.--3. " COUNT_EDGE ,Counter event will increase or decrease the counter by 1" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
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textline " "
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bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Capture event will copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
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line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2"
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bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Determines the effect of a counter underflow event" "SET,CLEAR,INVERT,NO_CHANGE"
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bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Determines the effect of a counter overflow event" "SET,CLEAR,INVERT,NO_CHANGE"
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bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Determines the effect of a compare match event" "SET,CLEAR,INVERT,NO_CHANGE"
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group.long 0x30++0x0F
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line.long 0x00 "INTR,Interrupt Request Register"
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eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Not detected,Detected"
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eventfld.long 0x00 0. " TC ,Terminal count event" "Not detected,Detected"
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line.long 0x04 "INTR_SET,Interrupt Set Request Register"
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bitfld.long 0x04 1. " CC_MATCH ,Set counter matches CC register event" "Not detected,Detected"
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bitfld.long 0x04 0. " TC ,Set terminal count event" "Not detected,Detected"
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line.long 0x08 "INTR_MASK,Interrupt Mask Register"
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bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
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bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
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line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register"
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rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
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rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
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endif
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width 0x0B
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tree.end
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tree "CNT 2"
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base ad:0x40010180
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width 20.
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if (((per.l(ad:0x40010000))&0x1<<2.)==0x1<<2.)
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if (((per.l(ad:0x40010180))&0x7000000)==0x3000000)
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group.long 0x00++0x03
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line.long 0x00 "CTRL,Counter Control Register"
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bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
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bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "X1,X2,X4,?..."
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bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
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bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
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textline " "
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bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
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elif (((per.l(ad:0x40010180))&0x7000000)==(0x4000000||0x5000000))
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if (((per.l(ad:0x40010180))&0x7000000)==0x4000000)
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group.long 0x00++0x03
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line.long 0x00 "CTRL,Counter Control Register"
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bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
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bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
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bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
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bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
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textline " "
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bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
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bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
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bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
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bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
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textline " "
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bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
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else
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group.long 0x00++0x03
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line.long 0x00 "CTRL,Counter Control Register"
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bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
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bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
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bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
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bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
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textline " "
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hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,8-bit generic control field"
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bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
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bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
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bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
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textline " "
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bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
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endif
|
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elif (((per.l(ad:0x40010180))&0x07000000)==0x06000000)
|
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group.long 0x00++0x03
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line.long 0x00 "CTRL,Counter Control Register"
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bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
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bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "?..."
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bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
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bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
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textline " "
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bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
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bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
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bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
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bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
elif (((per.l(ad:0x40010180))&0x07000000)==0x00000000)
|
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group.long 0x00++0x03
|
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line.long 0x00 "CTRL,Counter Control Register"
|
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bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
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bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
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bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
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bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
endif
|
|
if (((per.l(ad:0x40010180))&0x7000000)==0x5000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic counter field"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic counter field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
endif
|
|
if (((per.l(ad:0x40010180+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "CC,Counter Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CC ,Counter compare"
|
|
line.long 0x04 "CC_BUFF,Counter Buffered Compare/capture Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CC ,Additional buffer for counter CC register"
|
|
line.long 0x08 "PERIOD,Counter Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERIOD ,Period value"
|
|
line.long 0x0C "PERIOD_BUFF,Counter Buffered Period Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0"
|
|
bitfld.long 0x00 16.--19. " START_SEL ,Selects one of the 16 triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " STOP_SEL ,Selects one of the 16 triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RELOAD_SEL ,Selects one of the 16 triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " COUNT_SEL ,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Selects one of the 16 input trigger as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1"
|
|
bitfld.long 0x04 8.--9. " START_EDGE ,Start event will start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop event will stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Reload event will initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 2.--3. " COUNT_EDGE ,Counter event will increase or decrease the counter by 1" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Capture event will copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2"
|
|
bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Determines the effect of a counter underflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Determines the effect of a counter overflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Determines the effect of a compare match event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " TC ,Terminal count event" "Not detected,Detected"
|
|
line.long 0x04 "INTR_SET,Interrupt Set Request Register"
|
|
bitfld.long 0x04 1. " CC_MATCH ,Set counter matches CC register event" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " TC ,Set terminal count event" "Not detected,Detected"
|
|
line.long 0x08 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register"
|
|
rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CNT 3"
|
|
base ad:0x400101C0
|
|
width 20.
|
|
if (((per.l(ad:0x40010000))&0x1<<3.)==0x1<<3.)
|
|
if (((per.l(ad:0x400101C0))&0x7000000)==0x3000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "X1,X2,X4,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
elif (((per.l(ad:0x400101C0))&0x7000000)==(0x4000000||0x5000000))
|
|
if (((per.l(ad:0x400101C0))&0x7000000)==0x4000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,8-bit generic control field"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
endif
|
|
elif (((per.l(ad:0x400101C0))&0x07000000)==0x06000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
elif (((per.l(ad:0x400101C0))&0x07000000)==0x00000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
endif
|
|
if (((per.l(ad:0x400101C0))&0x7000000)==0x5000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic counter field"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic counter field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
endif
|
|
if (((per.l(ad:0x400101C0+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "CC,Counter Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CC ,Counter compare"
|
|
line.long 0x04 "CC_BUFF,Counter Buffered Compare/capture Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CC ,Additional buffer for counter CC register"
|
|
line.long 0x08 "PERIOD,Counter Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERIOD ,Period value"
|
|
line.long 0x0C "PERIOD_BUFF,Counter Buffered Period Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0"
|
|
bitfld.long 0x00 16.--19. " START_SEL ,Selects one of the 16 triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " STOP_SEL ,Selects one of the 16 triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RELOAD_SEL ,Selects one of the 16 triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " COUNT_SEL ,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Selects one of the 16 input trigger as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1"
|
|
bitfld.long 0x04 8.--9. " START_EDGE ,Start event will start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop event will stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Reload event will initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 2.--3. " COUNT_EDGE ,Counter event will increase or decrease the counter by 1" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Capture event will copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2"
|
|
bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Determines the effect of a counter underflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Determines the effect of a counter overflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Determines the effect of a compare match event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " TC ,Terminal count event" "Not detected,Detected"
|
|
line.long 0x04 "INTR_SET,Interrupt Set Request Register"
|
|
bitfld.long 0x04 1. " CC_MATCH ,Set counter matches CC register event" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " TC ,Set terminal count event" "Not detected,Detected"
|
|
line.long 0x08 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register"
|
|
rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("CY8C4A24*"))
|
|
tree "CNT 4"
|
|
base ad:0x40010200
|
|
width 20.
|
|
if (((per.l(ad:0x40010000))&0x1<<4.)==0x1<<4.)
|
|
if (((per.l(ad:0x40010200))&0x7000000)==0x3000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "X1,X2,X4,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
elif (((per.l(ad:0x40010200))&0x7000000)==(0x4000000||0x5000000))
|
|
if (((per.l(ad:0x40010200))&0x7000000)==0x4000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,8-bit generic control field"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
endif
|
|
elif (((per.l(ad:0x40010200))&0x07000000)==0x06000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
elif (((per.l(ad:0x40010200))&0x07000000)==0x00000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
endif
|
|
if (((per.l(ad:0x40010200))&0x7000000)==0x5000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic counter field"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic counter field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
endif
|
|
if (((per.l(ad:0x40010200+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "CC,Counter Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CC ,Counter compare"
|
|
line.long 0x04 "CC_BUFF,Counter Buffered Compare/capture Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CC ,Additional buffer for counter CC register"
|
|
line.long 0x08 "PERIOD,Counter Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERIOD ,Period value"
|
|
line.long 0x0C "PERIOD_BUFF,Counter Buffered Period Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0"
|
|
bitfld.long 0x00 16.--19. " START_SEL ,Selects one of the 16 triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " STOP_SEL ,Selects one of the 16 triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RELOAD_SEL ,Selects one of the 16 triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " COUNT_SEL ,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Selects one of the 16 input trigger as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1"
|
|
bitfld.long 0x04 8.--9. " START_EDGE ,Start event will start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop event will stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Reload event will initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 2.--3. " COUNT_EDGE ,Counter event will increase or decrease the counter by 1" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Capture event will copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2"
|
|
bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Determines the effect of a counter underflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Determines the effect of a counter overflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Determines the effect of a compare match event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " TC ,Terminal count event" "Not detected,Detected"
|
|
line.long 0x04 "INTR_SET,Interrupt Set Request Register"
|
|
bitfld.long 0x04 1. " CC_MATCH ,Set counter matches CC register event" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " TC ,Set terminal count event" "Not detected,Detected"
|
|
line.long 0x08 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register"
|
|
rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CNT 5"
|
|
base ad:0x40010240
|
|
width 20.
|
|
if (((per.l(ad:0x40010000))&0x1<<5.)==0x1<<5.)
|
|
if (((per.l(ad:0x40010240))&0x7000000)==0x3000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "X1,X2,X4,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
elif (((per.l(ad:0x40010240))&0x7000000)==(0x4000000||0x5000000))
|
|
if (((per.l(ad:0x40010240))&0x7000000)==0x4000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,8-bit generic control field"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
endif
|
|
elif (((per.l(ad:0x40010240))&0x07000000)==0x06000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
elif (((per.l(ad:0x40010240))&0x07000000)==0x00000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
endif
|
|
if (((per.l(ad:0x40010240))&0x7000000)==0x5000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic counter field"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic counter field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
endif
|
|
if (((per.l(ad:0x40010240+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "CC,Counter Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CC ,Counter compare"
|
|
line.long 0x04 "CC_BUFF,Counter Buffered Compare/capture Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CC ,Additional buffer for counter CC register"
|
|
line.long 0x08 "PERIOD,Counter Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERIOD ,Period value"
|
|
line.long 0x0C "PERIOD_BUFF,Counter Buffered Period Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0"
|
|
bitfld.long 0x00 16.--19. " START_SEL ,Selects one of the 16 triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " STOP_SEL ,Selects one of the 16 triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RELOAD_SEL ,Selects one of the 16 triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " COUNT_SEL ,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Selects one of the 16 input trigger as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1"
|
|
bitfld.long 0x04 8.--9. " START_EDGE ,Start event will start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop event will stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Reload event will initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 2.--3. " COUNT_EDGE ,Counter event will increase or decrease the counter by 1" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Capture event will copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2"
|
|
bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Determines the effect of a counter underflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Determines the effect of a counter overflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Determines the effect of a compare match event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " TC ,Terminal count event" "Not detected,Detected"
|
|
line.long 0x04 "INTR_SET,Interrupt Set Request Register"
|
|
bitfld.long 0x04 1. " CC_MATCH ,Set counter matches CC register event" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " TC ,Set terminal count event" "Not detected,Detected"
|
|
line.long 0x08 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register"
|
|
rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CNT 6"
|
|
base ad:0x40010280
|
|
width 20.
|
|
if (((per.l(ad:0x40010000))&0x1<<6.)==0x1<<6.)
|
|
if (((per.l(ad:0x40010280))&0x7000000)==0x3000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "X1,X2,X4,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
elif (((per.l(ad:0x40010280))&0x7000000)==(0x4000000||0x5000000))
|
|
if (((per.l(ad:0x40010280))&0x7000000)==0x4000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,8-bit generic control field"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
endif
|
|
elif (((per.l(ad:0x40010280))&0x07000000)==0x06000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
elif (((per.l(ad:0x40010280))&0x07000000)==0x00000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
endif
|
|
if (((per.l(ad:0x40010280))&0x7000000)==0x5000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic counter field"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic counter field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
endif
|
|
if (((per.l(ad:0x40010280+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "CC,Counter Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CC ,Counter compare"
|
|
line.long 0x04 "CC_BUFF,Counter Buffered Compare/capture Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CC ,Additional buffer for counter CC register"
|
|
line.long 0x08 "PERIOD,Counter Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERIOD ,Period value"
|
|
line.long 0x0C "PERIOD_BUFF,Counter Buffered Period Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0"
|
|
bitfld.long 0x00 16.--19. " START_SEL ,Selects one of the 16 triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " STOP_SEL ,Selects one of the 16 triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RELOAD_SEL ,Selects one of the 16 triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " COUNT_SEL ,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Selects one of the 16 input trigger as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1"
|
|
bitfld.long 0x04 8.--9. " START_EDGE ,Start event will start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop event will stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Reload event will initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 2.--3. " COUNT_EDGE ,Counter event will increase or decrease the counter by 1" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Capture event will copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2"
|
|
bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Determines the effect of a counter underflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Determines the effect of a counter overflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Determines the effect of a compare match event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " TC ,Terminal count event" "Not detected,Detected"
|
|
line.long 0x04 "INTR_SET,Interrupt Set Request Register"
|
|
bitfld.long 0x04 1. " CC_MATCH ,Set counter matches CC register event" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " TC ,Set terminal count event" "Not detected,Detected"
|
|
line.long 0x08 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register"
|
|
rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CNT 7"
|
|
base ad:0x400102C0
|
|
width 20.
|
|
if (((per.l(ad:0x40010000))&0x1<<7.)==0x1<<7.)
|
|
if (((per.l(ad:0x400102C0))&0x7000000)==0x3000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "X1,X2,X4,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
elif (((per.l(ad:0x400102C0))&0x7000000)==(0x4000000||0x5000000))
|
|
if (((per.l(ad:0x400102C0))&0x7000000)==0x4000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" ",INV_OUT,INV_COMPL_OUT,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,8-bit generic control field"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 2. " PWM_SYNC_KILL ,Specifies asynchronous/synchronous kill behavior" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
endif
|
|
elif (((per.l(ad:0x400102C0))&0x07000000)==0x06000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature mode" "?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,PWM stop on kill event" "Not stopped,Stopped"
|
|
bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Specifies switching of the PERIOD and buffered PERIOD values" "Never switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
elif (((per.l(ad:0x400102C0))&0x07000000)==0x00000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Specifies switching of the CC and buffered CC values" "Never switched,Switched"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Counter Control Register"
|
|
bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..."
|
|
bitfld.long 0x00 18. " ONE_SHOT ,One shot" "Turned on,Turned off"
|
|
bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic control field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
endif
|
|
if (((per.l(ad:0x400102C0))&0x7000000)==0x5000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic counter field"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Counter Status Register"
|
|
bitfld.long 0x00 31. " RUNNING ,Running" "Not running,Running"
|
|
bitfld.long 0x00 8.--10. " GENERIC ,Generic counter field" "DIVBY1,DIVBY2,DIVBY4,DIVBY8,DIVBY16,DIVBY32,DIVBY64,DIVBY128"
|
|
bitfld.long 0x00 0. " DOWN ,Determines counting" "Counting up,Counting down"
|
|
endif
|
|
if (((per.l(ad:0x400102C0+0x04))&0x80000000)==0x80000000)
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "COUNTER,Counter Count Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Counter values"
|
|
endif
|
|
group.long 0x0C++0x0F
|
|
line.long 0x00 "CC,Counter Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CC ,Counter compare"
|
|
line.long 0x04 "CC_BUFF,Counter Buffered Compare/capture Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CC ,Additional buffer for counter CC register"
|
|
line.long 0x08 "PERIOD,Counter Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERIOD ,Period value"
|
|
line.long 0x0C "PERIOD_BUFF,Counter Buffered Period Register"
|
|
hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0"
|
|
bitfld.long 0x00 16.--19. " START_SEL ,Selects one of the 16 triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " STOP_SEL ,Selects one of the 16 triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " RELOAD_SEL ,Selects one of the 16 triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " COUNT_SEL ,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Selects one of the 16 input trigger as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1"
|
|
bitfld.long 0x04 8.--9. " START_EDGE ,Start event will start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop event will stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Reload event will initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
bitfld.long 0x04 2.--3. " COUNT_EDGE ,Counter event will increase or decrease the counter by 1" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Capture event will copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET"
|
|
line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2"
|
|
bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Determines the effect of a counter underflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Determines the effect of a counter overflow event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Determines the effect of a compare match event" "SET,CLEAR,INVERT,NO_CHANGE"
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Not detected,Detected"
|
|
eventfld.long 0x00 0. " TC ,Terminal count event" "Not detected,Detected"
|
|
line.long 0x04 "INTR_SET,Interrupt Set Request Register"
|
|
bitfld.long 0x04 1. " CC_MATCH ,Set counter matches CC register event" "Not detected,Detected"
|
|
bitfld.long 0x04 0. " TC ,Set terminal count event" "Not detected,Detected"
|
|
line.long 0x08 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register"
|
|
rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "CPUSS (CPU Sub System)"
|
|
base ad:0x40100004
|
|
width 11.
|
|
if (((per.l(ad:0x40100004))&0x20000000)==0x20000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SYSREQ,SYSCALL Control Register"
|
|
bitfld.long 0x00 31. " SYSCALL_REQ ,System call request" "Not requested,Requested"
|
|
rbitfld.long 0x00 30. " HMASTER_0 ,Indicates the source of the write access to the SYSREQ register" "CPU,DAP"
|
|
textline " "
|
|
rbitfld.long 0x00 29. " ROM_ACCESS_EN ,Indicates that executing from boot ROM is enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " PRIVILEGED ,Indicates whether the system is in privileged or user mode" "User mode,Privileged mode"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DIS_RESET_VECT_REL ,Disable reset vector fetch relocation" "ROM,Flash"
|
|
hexmask.long.word 0x00 0.--15. 1. " SYSCALL_COMMAND ,16-bit opcode of the system call being requested"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SYSREQ,SYSCALL Control Register"
|
|
bitfld.long 0x00 31. " SYSCALL_REQ ,System call request" "Not requested,Requested"
|
|
rbitfld.long 0x00 30. " HMASTER_0 ,Indicates the source of the write access to the SYSREQ register" "CPU,DAP"
|
|
textline " "
|
|
rbitfld.long 0x00 29. " ROM_ACCESS_EN ,Indicates that executing from boot ROM is enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 28. " PRIVILEGED ,Indicates whether the system is in privileged or user mode" "User mode,Privileged mode"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DIS_RESET_VECT_REL ,Disable reset vector fetch relocation" "ROM,Flash"
|
|
hexmask.long.word 0x00 0.--15. 1. " SYSCALL_COMMAND ,16-bit opcode of the system call being requested"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SYSARG,SYSARG Control Register"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "FLASH_CTL,FLASH Control Register"
|
|
bitfld.long 0x00 16.--17. " ARB ,Arbitration policy" "CPU,DW/DMA,Roundrobin,Roundrobin-sticky"
|
|
bitfld.long 0x00 8. " FLASH_INVALIDATE ,Flash invalidate" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PREF_EN ,Prefetch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " FLASH_WS ,Amount of ROM wait states" "0 wait,1 wait,2 wait,Undefined"
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "ROM_CTL,ROM Control Register"
|
|
bitfld.long 0x00 0. " ROM_WS ,Amount of ROM wait states" "0 wait,1 wait"
|
|
line.long 0x04 "RAM_CTL,RAM Control Register"
|
|
bitfld.long 0x04 16.--17. " ARB ,Arbitration policy" "CPU,DW/DMA,Roundrobin,Roundrobin-sticky"
|
|
line.long 0x08 "DMAC_CTL,DMA Controller Register"
|
|
bitfld.long 0x08 16.--17. " ARB ,Arbitration policy" "CPU,DW/DMA,Roundrobin,Roundrobin-sticky"
|
|
group.long 0xFC++0x07
|
|
line.long 0x00 "SL_CTL0,Slave Control Register 0"
|
|
bitfld.long 0x00 16.--17. " ARB ,Arbitration" "CPU,DMA,Roundrobin,Roundrobin-sticky"
|
|
line.long 0x04 "SL_CTL1,Slave Control Register 1"
|
|
bitfld.long 0x04 16.--17. " ARB ,Arbitration" "CPU,DMA,Roundrobin,Roundrobin-sticky"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpu()!="CY8C4A24PVI-431"&&cpu()!="CY8C4A24AZI-433"&&cpu()!="CY8C4A25PVI-471"&&cpu()!="CY8C4A25FNI-473"&&cpu()!="CY8C4A25LQI-473"&&cpu()!="CY8C4A25AZI-473"&&cpu()!="CY8C4A45PVI-471"&&cpu()!="CY8C4A45FNI-473"&&cpu()!="CY8C4A45LQI-473"&&cpu()!="CY8C4A45AZI-473")
|
|
tree "CSD (CapSense Sigma Delta)"
|
|
base ad:0x400C0000
|
|
width 16.
|
|
if (((per.l(ad:0x400C0000))&0x40000)==0x40000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG,Configuration And Control"
|
|
bitfld.long 0x00 31. " ENABLE ,Enables CapSense block" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LP_MODE ,Selects power mode for the CSD components" "High,Low"
|
|
sif CPUIS("CY8C6*")
|
|
bitfld.long 0x00 27. " DSI_SENSE_EN ,Enables the use of the dsi_sense_in input instead of the internally generated clock to drive senseclk and shieldclk signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SAMPLE_SYNC ,Enables double synchronizing of sample input from DSI" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 27. " DSI_SENSE_EN ,Enables the use of the dsi_sense_in input instead of the internally generated clock to drive senseclk and shieldclk signals" "DSI,PRS/Divide-by-2/DIRECT_CLOCK"
|
|
bitfld.long 0x00 26. " SAMPLE_SYNC ,Enables double synchronizing of sample input from DSI" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 25. " DSI_SAMPLE_EN ,Enables the use of dsi_sample_in input instead of the comparator output to strobe COUNTER" "CSD modulator,DSI"
|
|
bitfld.long 0x00 24. " DSI_COUNT_SEL ,Select dsi_count bus signal" "CSD_RESULT,ADC_RESULT"
|
|
bitfld.long 0x00 19. " CSX_DUAL_CNT ,Enables the use of two counters for MUTUAL cap sensing mode" "One,Two"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MUTUAL_CAP ,Selects self-cap or mutual-cap mode of operation" "Selfcap,Mutualcap"
|
|
sif CPUIS("CY8C6*")
|
|
textline " "
|
|
bitfld.long 0x00 17. " FULL_WAVE ,Enable full wave cap sensing mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SENSE_EN ,Enables the sense modulator output" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SHIELD_DELAY ,Selects the delay by which csd_shield is delayed relative to csd_sense" "OFF,D5NS,D10NS,D20NS"
|
|
bitfld.long 0x00 4.--8. " FILTER_DELAY ,Determine the number of cycles that the digital filter makes the CSDCMP output ignored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IREF_SEL ,Select Iref supply" "IREF_SRSS,IREF_PASS"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 14. " CHARGE_MODE ,Enables charging of Cmod/Csh_tank capacitor using GPIO digital output buffer" "CHARGE_OFF,CHARGE_IO"
|
|
bitfld.long 0x00 12. " SENSE_EN ,Enables the sense modulator output" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " SHIELD_DELAY ,Configures the delay between shieldclk ans senseclk signal" "Off,D5NS,D10NS,D20NS"
|
|
bitfld.long 0x00 4.--6. " FILTER_DELAY ,Enables digital filtering on the CSD comparator output" "Off,1,2,3,4,5,6,7"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG,Configuration And Control"
|
|
bitfld.long 0x00 31. " ENABLE ,Enables capsense block" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LP_MODE ,Selects power mode for the CSD components" "High,Low"
|
|
sif CPUIS("CY8C6*")
|
|
bitfld.long 0x00 27. " DSI_SENSE_EN ,Enables the use of the dsi_sense_in input instead of the internally generated clock to drive senseclk and shieldclk signals" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " SAMPLE_SYNC ,Enables double synchronizing of sample input from DSI" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 27. " DSI_SENSE_EN ,Enables the use of the dsi_sense_in input instead of the internally generated clock to drive senseclk and shieldclk signals" "DSI,PRS/Divide-by-2/DIRECT_CLOCK"
|
|
bitfld.long 0x00 26. " SAMPLE_SYNC ,Enables double synchronizing of sample input from DSI" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 25. " DSI_SAMPLE_EN ,Enables the use of dsi_sample_in input instead of the comparator output to strobe COUNTER" "CSD modulator,DSI"
|
|
bitfld.long 0x00 24. " DSI_COUNT_SEL ,Select dsi_count bus signal" "CSD_RESULT,ADC_RESULT"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MUTUAL_CAP ,Selects Self-cap or mutual cap mode of operation" "Selfcap,Mutualcap"
|
|
sif CPUIS("CY8C6*")
|
|
textline " "
|
|
bitfld.long 0x00 17. " FULL_WAVE ,Enable full wave cap sensing mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " SENSE_EN ,Enables the sense modulator output" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SHIELD_DELAY ,Selects the delay by which csd_shield is delayed relative to csd_sense" "OFF,D5NS,D10NS,D20NS"
|
|
bitfld.long 0x00 4.--8. " FILTER_DELAY ,Determine the number of cycles that the digital filter makes the CSDCMP output ignored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IREF_SEL ,Select Iref supply" "IREF_SRSS,IREF_PASS"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x00 14. " CHARGE_MODE ,Enables charging of Cmod/Csh_tank capacitor using GPIO digital output buffer" "CHARGE_OFF,CHARGE_IO"
|
|
bitfld.long 0x00 12. " SENSE_EN ,Enables the sense modulator output" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " SHIELD_DELAY ,Configures the delay between shieldclk ans senseclk signal" "Off,D5NS,D10NS,D20NS"
|
|
bitfld.long 0x00 4.--6. " FILTER_DELAY ,Enables digital filtering on the CSD comparator output" "Off,1,2,3,4,5,6,7"
|
|
endif
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SPARE,Spare MMIO"
|
|
bitfld.long 0x00 0.--3. " SPARE ,Spare MMIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x80++0x0B
|
|
line.long 0x00 "STATUS,Status Register"
|
|
bitfld.long 0x00 3. " CSDCMP_OUT ,This field is used to monitor the output status of CSDCOMP" "0,1"
|
|
bitfld.long 0x00 2. " HSCMP_OUT ,This field is used to monitor the output status of HSCOMP" "C_LT_VREF,C_GT_VREF"
|
|
bitfld.long 0x00 1. " CSD_SENSE ,This field is used to monitor the status of SenseClk signal" "0,1"
|
|
sif !CPUIS("CY8C6*")
|
|
bitfld.long 0x00 0. " CSD_CHARGE ,This field is used to monitor the output of Cmod/Ctank capacitors during charging/discharging by the GPIO pin" "0,1"
|
|
endif
|
|
line.long 0x04 "STAT_SEQ,Current Sequencer Status"
|
|
bitfld.long 0x04 16.--18. " ADC_STATE ,Specifies ADC sequencer current state" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--2. " SEQ_STATE ,Specifies CSD sequencer current state" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "STAT_CNTS,Current Status Counts"
|
|
hexmask.long.word 0x08 0.--15. 1. " NUM_CONV ,Specifies the current number of conversions remaining when in sample_* states"
|
|
rgroup.long 0xD0++0x03
|
|
line.long 0x00 "RESULT_VAL1,Result CSD/CSX Accumulation Counter Value 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BAD_CONVS ,Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Specifies the raw count value for current conversion"
|
|
sif CPUIS("CY8C6*")
|
|
if (((per.l(ad:0x400C0000+0x00))&0xC0000)==0xC0000)
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "RESULT_VAL2,Result CSX Accumulation Counter Value 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Counts when csd_sense is low"
|
|
else
|
|
hgroup.long 0xD4++0x03
|
|
hide.long 0x00 "RESULT_VAL2,Result CSX Accumulation Counter Value 2"
|
|
endif
|
|
else
|
|
rgroup.long 0xD4++0x03
|
|
line.long 0x00 "RESULT_VAL2,Result CSX Accumulation Counter Value 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " VALUE ,Specifies the raw count value of second counter when mutual capacitance measurement with dual counter is enabled"
|
|
endif
|
|
rgroup.long 0xE0++0x03
|
|
line.long 0x00 "ADC_RES,ADC Measurement"
|
|
bitfld.long 0x00 31. " ADC_ABORT ,This flag is set when the ADC sequencer was aborted before tripping HSCMP" "Not aborted,Aborted"
|
|
bitfld.long 0x00 30. " ADC_OVERFLOW ,This flag is set when the ADC counter overflows" "No overflow,Overflow"
|
|
bitfld.long 0x00 16. " HSCMP_POL ,Polarity used for IDACB for the last ADC result" "Source,Sink"
|
|
hexmask.long.word 0x00 0.--15. 1. " VIN_CNT ,Specifies ADC counter value"
|
|
group.long 0xF0++0x0B
|
|
line.long 0x00 "INTR,CSD Interrupt Request Register"
|
|
eventfld.long 0x00 8. " ADC_RES ,ADC result ready" "Not ready,Ready"
|
|
eventfld.long 0x00 2. " INIT ,Coarse/sample initialization complete" "Not completed,Completed"
|
|
eventfld.long 0x00 1. " SAMPLE ,Normal sample is complete" "Not completed,Completed"
|
|
line.long 0x04 "INTR_SET,CSD Interrupt Set Register"
|
|
bitfld.long 0x04 8. " ADC_RES ,Set INTR.ADC_RES" "No effect,Set"
|
|
bitfld.long 0x04 2. " INIT ,Set INTR.INIT" "No effect,Set"
|
|
bitfld.long 0x04 1. " SAMPLE ,Set INTR.SAMPLE" "No effect,Set"
|
|
line.long 0x08 "INTR_MASK,CSD Interrupt Mask Register"
|
|
bitfld.long 0x08 8. " ADC_RES ,Mask INTR.ADC_RES" "Masked,Not masked"
|
|
bitfld.long 0x08 2. " INIT ,Mask INTR.INIT" "Masked,Not masked"
|
|
bitfld.long 0x08 1. " SAMPLE ,Mask INTR.SAMPLE" "Masked,Not masked"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "INTR_MASKED,CSD Interrupt Masked Register"
|
|
bitfld.long 0x00 8. " ADC_RES ,Logical 'AND' of corresponding request and mask bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " INIT ,Logical 'AND' of corresponding request and mask bit" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " SAMPLE ,Logical 'AND' of corresponding request and mask bit" "No interrupt,Interrupt"
|
|
group.long 0x180++0x07
|
|
line.long 0x00 "HSCMP,High Speed Comparator Configuration"
|
|
bitfld.long 0x00 31. " AZ_EN ,Enables or disables Auto-Zero for HSCOMP" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " HSCMP_INVERT ,Inverts the output HSCMP before it is used to control switches and the CSD sequencer" "Not inverted,Inverted"
|
|
bitfld.long 0x00 0. " HSCMP_EN ,Enables or disables HSCOMP" "Disabled,Enabled"
|
|
line.long 0x04 "AMBUF,Reference Generator Configuration"
|
|
bitfld.long 0x04 0.--1. " PWR_MODE ,This field specifies the AMUXBUFFER power level" "OFF,NORM,HI,?..."
|
|
if (((per.l(ad:0x400C0000+0x188))&0x40)==0x40)
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "REFGEN,Reference Generator Configuration"
|
|
bitfld.long 0x00 23. " VREFLO_INT ,This field selects the output of the resistor string tap to either Vreflo or Vreflo_int" "Vreflo,Vreflo_int"
|
|
bitfld.long 0x00 16.--20. " VREFLO_SEL ,Selects resistor string tap to Vreflo/Vreflo_int" "Minimum,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Maximum"
|
|
bitfld.long 0x00 8.--12. " GAIN ,Specifies resistor string tap for feedback" "Minimum,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,Maximum"
|
|
bitfld.long 0x00 6. " RES_EN ,Enables or disables resistor string" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VDDA_EN ,This field when set closes Vdda switch to top of resistor string" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BYPASS ,This field when set bypasses the selected input reference unbuffered to Vrefhi" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 0. " REFGEN_EN ,Enables/disables reference generator (Refgen)" "Disabled,Enabled"
|
|
else
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "REFGEN,Reference Generator Configuration"
|
|
bitfld.long 0x00 23. " VREFLO_INT ,This field selects the output of the resistor string tap to either Vreflo or Vreflo_int" "Vreflo,Vreflo_int"
|
|
bitfld.long 0x00 6. " RES_EN ,Enables or disables resistor string" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VDDA_EN ,This field when set closes Vdda switch to top of resistor string" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " BYPASS ,This field when set bypasses the selected input reference unbuffered to Vrefhi" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 0. " REFGEN_EN ,Enables/disables reference generator (Refgen)" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "CSDCMP,CSD Comparator Configuration"
|
|
bitfld.long 0x00 31. " AZ_EN ,Enables or disables Auto-Zero for CSDCOMP" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FEEDBACK_MODE ,This field controls whether the direct output from CSDCOMP or the flopped version of CSDCOMP is used for capsense operations" "FLOP,COMP"
|
|
bitfld.long 0x00 28. " CMP_MODE ,Selects which signal to output on dsi_sample_out" "CSD,GP"
|
|
bitfld.long 0x00 8.--9. " CMP_PHASE ,This field is used to select in what phase(s) the CSDCOMP is active" "FULL,PHI1,PHI2,PHI1_2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " POLARITY_SET ,This field selects which IDAC polarity to use to detect CSDCMP triggering" "IDACA_POL,IDACB_POL,DUAL_POL,?..."
|
|
bitfld.long 0x00 0. " CSDCMP_EN ,This field is used to enable or disable CSD comparator" "Disabled,Enabled"
|
|
sif !CPUIS("CY8C6*")
|
|
if (((per.l(ad:0x400C0000+0x1C0))&0x80)==0x80)
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "IDACA,IDACA Configuration"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs with MMIO controls or not" "No DSI,MMIO with DSI"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,This field controls the usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,This field controls usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,This field specified the duration for which IDAC is enabled" "FULL,PHI1,PHI2,PHI1_2"
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Selects the polarity of the IDAC" "VSSA_SRC,VDDA_SNK,SENSE,SENSE_INV"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,This field specifies IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
else
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "IDACA,IDACA Configuration"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs with MMIO controls or not" "No DSI,MMIO with DSI"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,This field controls the usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,This field controls usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,This field specified the duration for which IDAC is enabled" "FULL,PHI1,PHI2,PHI1_2"
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Selects the polarity of the IDAC" "VSSA_SRC,VDDA_SNK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,This field specifies IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
endif
|
|
if (((per.l(ad:0x400C0000+0x1C4))&0x80)==0x80)
|
|
if (((per.l(ad:0x400C0000+0x320))&0x30000)>0x00000)
|
|
if (((per.l(ad:0x400C0000+0x1C4))&0xC00000)==0x000000)
|
|
if (((per.l(ad:0x400C0000+0x1C4))&0x04000000)==0x04000000)
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
bitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs with MMIO controls or not" "No DSI,MMIO with DSI"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,This field specified the duration for which IDAC is enabled" "FULL,PHI1,PHI2,PHI1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Selects the polarity of the IDAC" "VSSA_SRC,VDDA_SNK,SENSE,SENSE_INV"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,This field specifies IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
else
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
bitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs whit MMIO controls or not" "No DSI,MMIO with DSI"
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,This field controls the usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,This field controls usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,This field specified the duration for which IDAC is enabled" "FULL,PHI1,PHI2,PHI1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Selects the polarity of the IDAC" "VSSA_SRC,VDDA_SNK,SENSE,SENSE_INV"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,This field specifies IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x400C0000+0x1C4))&0x04000000)==0x04000000)
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
rbitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs with MMIO controls or not" "No DSI,MMIO with DSI"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,This field specified the duration for which IDAC is enabled" "FULL,PHI1,PHI2,PHI1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Selects the polarity of the IDAC" "VSSA_SRC,VDDA_SNK,SENSE,SENSE_INV"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,This field specifies IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
else
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
rbitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs whit MMIO controls or not" "No DSI,MMIO with DSI"
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,This field controls the usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,This field controls usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,This field specified the duration for which IDAC is enabled" "FULL,PHI1,PHI2,PHI1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Selects the polarity of the IDAC" "VSSA_SRC,VDDA_SNK,SENSE,SENSE_INV"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,This field specifies IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
endif
|
|
endif
|
|
else
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs with MMIO controls or not" "No DSI,MMIO with DSI"
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,This field controls the usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,This field controls usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,This field specified the duration for which IDAC is enabled" "FULL,PHI1,PHI2,PHI1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Selects the polarity of the IDAC" "VSSA_SRC,VDDA_SNK,SENSE,SENSE_INV"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,This field specifies IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x400C0000+0x320))&0x30000)>0x00000)
|
|
if (((per.l(ad:0x400C0000+0x1C4))&0xC00000)==0x000000)
|
|
if (((per.l(ad:0x400C0000+0x1C4))&0x04000000)==0x04000000)
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
bitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs with MMIO controls or not" "No DSI,MMIO with DSI"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,This field specified the duration for which IDAC is enabled" "FULL,PHI1,PHI2,PHI1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Selects the polarity of the IDAC" "VSSA_SRC,VDDA_SNK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,This field specifies IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
else
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
bitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs whit MMIO controls or not" "No DSI,MMIO with DSI"
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,This field controls the usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,This field controls usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,This field specified the duration for which IDAC is enabled" "FULL,PHI1,PHI2,PHI1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Selects the polarity of the IDAC" "VSSA_SRC,VDDA_SNK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,This field specifies IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x400C0000+0x1C4))&0x04000000)==0x04000000)
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
rbitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs with MMIO controls or not" "No DSI,MMIO with DSI"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,This field specified the duration for which IDAC is enabled" "FULL,PHI1,PHI2,PHI1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Selects the polarity of the IDAC" "VSSA_SRC,VDDA_SNK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,This field specifies IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
else
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
rbitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs whit MMIO controls or not" "No DSI,MMIO with DSI"
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,This field controls the usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,This field controls usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,This field specified the duration for which IDAC is enabled" "FULL,PHI1,PHI2,PHI1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Selects the polarity of the IDAC" "VSSA_SRC,VDDA_SNK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,This field specifies IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
endif
|
|
endif
|
|
else
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs with MMIO controls or not" "No DSI,MMIO with DSI"
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,This field controls the usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,This field controls usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,This field specified the duration for which IDAC is enabled" "FULL,PHI1,PHI2,PHI1_2"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Selects the polarity of the IDAC" "VSSA_SRC,VDDA_SNK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,This field specifies IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "SW_RES,Switch Resistance Configuration"
|
|
bitfld.long 0x00 18.--19. " RES_F2PT ,Selects resistance for the corresponding switch" "LOW,MED,HIGH,?..."
|
|
bitfld.long 0x00 16.--17. " RES_F1PM ,Selects resistance or low EMI for the corresponding switch" "LOW,MED,HIGH,?..."
|
|
bitfld.long 0x00 6.--7. " RES_HCBG ,Selects resistance or low EMI for the corresponding switch" "LOW,MED,HIGH,LOWEMI"
|
|
bitfld.long 0x00 4.--5. " RES_HCBV ,Selects resistance or low EMI for the corresponding switch" "LOW,MED,HIGH,LOWEMI"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " RES_HCAG ,Selects resistance or low EMI for the corresponding switch" "LOW,MED,HIGH,LOWEMI"
|
|
bitfld.long 0x00 0.--1. " RES_HCAV ,Selects resistance or low EMI for the HCAV switch" "LOW,MED,HIGH,LOWEMI"
|
|
if (((per.l(ad:0x400C0000+0x200))&0x70000)==(0x050000||0x060000))
|
|
if (((per.l(ad:0x400C0000+0x200))&0x02000000)==0x00000000)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SENSE_PERIOD,Sense Clock Period"
|
|
sif CPUIS("CY8C6*")
|
|
bitfld.long 0x00 26.--27. " LFSR_BITS ,Select the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period" "2B,3B,4B,5B"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " SEL_LFSR_MSB ,Use the MSB of configured LSFR size as senseclk signal" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " LFSR_CLEAR ,This field when set forces the LFST to its initial state" "Not cleared,Cleared"
|
|
bitfld.long 0x00 20.--23. " LFSR_SCALE ,This field specifies the left shift value by which the LFSR output is scaled before adding to SENSE_DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " LFSR_SIZE ,This field selects the number of bits to be used in the LSFR to provide the clock dithering variation" "OFF,2B,3B,4B,5B,8B,12B,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " SENSE_DIV ,This field specifies the period of senseclk in terms of samplclk period"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SENSE_PERIOD,Sense Clock Period"
|
|
sif CPUIS("CY8C6*")
|
|
bitfld.long 0x00 26.--27. " LFSR_BITS ,Select the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period" "2B,3B,4B,5B"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " SEL_LFSR_MSB ,Use the MSB of configured LSFR size as senseclk signal" "Not selected,Selected"
|
|
bitfld.long 0x00 24. " LFSR_CLEAR ,This field when set forces the LFST to its initial state" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " LFSR_SIZE ,This field selects the number of bits to be used in the LSFR to provide the clock dithering variation" "OFF,2B,3B,4B,5B,8B,12B,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " SENSE_DIV ,12-bit this field specifies the period of senseclk in terms of samplclk period"
|
|
endif
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SENSE_PERIOD,Sense Clock Period"
|
|
bitfld.long 0x00 24. " LFSR_CLEAR ,This field when set forces the LFST to its initial state" "Not cleared,Cleared"
|
|
bitfld.long 0x00 20.--23. " LFSR_SCALE ,This field specifies the left shift value by which the LFSR output is scaled before adding to SENSE_DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " LFSR_SIZE ,This field selects the number of bits to be used in the LSFR to provide the clock dithering variation" "OFF,2B,3B,4B,5B,8B,12B,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " SENSE_DIV ,This field specifies the period of senseclk in terms of samplclk period"
|
|
endif
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "SENSE_DUTY,Sense Clock Duty Cycle"
|
|
bitfld.long 0x00 19. " OVERLAP_PHI2 ,This field specifies whether phi2 signal is Not-Overlapping signal or 'NOT' of senseclk" "Non-overlapped,Overlapped"
|
|
bitfld.long 0x00 18. " OVERLAP_PHI1 ,This field specifies whether phi1 signal is Not-Overlapping signal or 'NOT' of senseclk" "Non-overlapped,Overlapped"
|
|
bitfld.long 0x00 16. " SENSE_POL ,This field specifies the polarity of the sense clock" "Low,High"
|
|
hexmask.long.word 0x00 0.--11. 1. " SENSE_WIDTH ,This field defines the length of the first phase of the senseclk in terms of sampleclk cycles"
|
|
group.long 0x280++0x0B
|
|
line.long 0x00 "SW_HS_P_SEL,HSCMP Pos Input Switch Waveform Selection"
|
|
bitfld.long 0x00 28. " SW_HMRH ,Controls HMRH switch" "Open,Closed"
|
|
bitfld.long 0x00 24. " SW_HMCB ,Controls HMCB switch" "Open,Closed"
|
|
bitfld.long 0x00 20. " SW_HMCA ,Controls HMCA switch" "Open,Closed"
|
|
bitfld.long 0x00 16. " SW_HMMB ,Controls HMMB switch" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SW_HMMA ,Controls HMMA switch" "Open,Closed"
|
|
bitfld.long 0x00 8. " SW_HMPS ,Controls HMPS switch" "Open,Closed"
|
|
bitfld.long 0x00 4. " SW_HMPT ,Controls HMPT switch" "Open,Closed"
|
|
bitfld.long 0x00 0. " SW_HMPM ,Controls HMPM switch" "Open,Closed"
|
|
line.long 0x04 "SW_HS_N_SEL,HSCMP Neg Input Switch Waveform Selection"
|
|
bitfld.long 0x04 28.--30. " SW_HCRL ,Select waveform for HCRL switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
bitfld.long 0x04 24.--26. " SW_HCRH ,Select waveform for HCRH switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
bitfld.long 0x04 20. " SW_HCCD ,Controls HCCD switch" "Open,Closed"
|
|
bitfld.long 0x04 16. " SW_HCCC ,Controls HCCC switch" "Open,Closed"
|
|
line.long 0x08 "SW_SHIELD_SEL,Shielding Switches Waveform Selection"
|
|
bitfld.long 0x08 20. " SW_HCCG ,Controls HCCG switch" "Open,Closed"
|
|
bitfld.long 0x08 16. " SW_HCCV ,Controls HCCV switch" "Open,Closed"
|
|
bitfld.long 0x08 12.--14. " SW_HCBG ,Select waveform for HCBG switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
bitfld.long 0x08 8.--10. " SW_HCBV ,Select waveform for HCBV switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " SW_HCAG ,Select waveform for HCAG switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
bitfld.long 0x08 0.--2. " SW_HCAV ,Select waveform HCAV switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
group.long 0x290++0x07
|
|
line.long 0x00 "SW_AMUXBUF_SEL,Amuxbuffer Switches Waveform Selection"
|
|
bitfld.long 0x00 28. " SW_IRL ,Controls IRL switch" "Open,Closed"
|
|
bitfld.long 0x00 24. " SW_IRH ,Controls IRH switch" "Open,Closed"
|
|
bitfld.long 0x00 20. " SW_IRLI ,Controls IRLI switch" "Open,Closed"
|
|
bitfld.long 0x00 16.--18. " SW_ICB ,Selects waveform for ICB switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " SW_ICA ,Controls ICA switch" "Open,Closed"
|
|
bitfld.long 0x00 8. " SW_IRLB ,Controls IRLB switch" "Open,Closed"
|
|
bitfld.long 0x00 4. " SW_IRBY ,Controls IRBY switch" "Open,Closed"
|
|
line.long 0x04 "SW_BYP_SEL,AMUXBUS Bypass Switches Waveform Selection"
|
|
bitfld.long 0x04 20. " SW_CBCC ,Controls CBCC switch" "Open,Closed"
|
|
bitfld.long 0x04 16. " SW_BYB ,Controls BYB switch" "Open,Closed"
|
|
bitfld.long 0x04 12. " SW_BYA ,Controls BYA switch" "Open,Closed"
|
|
group.long 0x2A0++0x0B
|
|
line.long 0x00 "SW_CMP_P_SEL,CSDCMP Pos Switch Waveform Selection"
|
|
bitfld.long 0x00 24. " SW_SFCB ,Controls SFCB switch" "Open,Closed"
|
|
bitfld.long 0x00 20. " SW_SFCA ,Controls SFCA switch" "Open,Closed"
|
|
bitfld.long 0x00 16. " SW_SFMB ,Controls SFMB switch" "Open,Closed"
|
|
bitfld.long 0x00 12. " SW_SDMA ,Controls SDMA switch" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SW_SFPS ,Selects waveform for SFPS switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
bitfld.long 0x00 4.--6. " SW_SFPT ,Select waveform for SFPT switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
bitfld.long 0x00 0.--2. " SW_SFPM ,Select waveform for SFPM switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
line.long 0x04 "SW_CMP_N_SEL,CSDCMP Neg Switch Waveform Selection"
|
|
bitfld.long 0x04 28.--30. " SW_SCRL ,Select waveform for SCRL switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
bitfld.long 0x04 24.--26. " SW_SCRH ,Select waveform SCRH switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
line.long 0x08 "SW_REFGEN_SEL,Reference Generator Switch Waveform Selection"
|
|
bitfld.long 0x08 28. " SW_SGR ,Controls SGR switch" "Open,Closed"
|
|
bitfld.long 0x08 24. " SW_SGRE ,Controls SGRE switch" "Open,Closed"
|
|
sif CPUIS("CY8C6*")
|
|
textline " "
|
|
bitfld.long 0x08 20. " SW_SGRP ,Controls SGRP switch" "Open,Closed"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 16. " SW_SGMB ,Controls SGMB switch" "Open,Closed"
|
|
bitfld.long 0x08 4. " SW_IBCB ,Controls IBCB switch" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SW_IAIB ,Controls IAIB switch" "Open,Closed"
|
|
group.long 0x2B0++0x07
|
|
line.long 0x00 "SW_FW_MOD_SEL,Full Wave Cmod Switch Waveform Selection"
|
|
bitfld.long 0x00 28. " SW_C1F1 ,Controls C1F1 switch" "Open,Closed"
|
|
bitfld.long 0x00 24. " SW_C1CD ,Controls C1CD switch" "Open,Closed"
|
|
bitfld.long 0x00 20. " SW_C1CC ,Controls C1CC switch" "Open,Closed"
|
|
bitfld.long 0x00 16.--18. " SW_F1CA ,Select waveform for F1CA switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " SW_F1MA ,Select waveform for F1MA switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
bitfld.long 0x00 0. " SW_F1PM ,Controls F1PM switch" "Open,Closed"
|
|
line.long 0x04 "SW_FW_TANK_SEL,Full Wave Csh_tank Switch Waveform Selection"
|
|
bitfld.long 0x04 28. " SW_C2F2 ,Controls C2F2 switch" "Open,Closed"
|
|
bitfld.long 0x04 24. " SW_C2CD ,Controls C2CD switch" "Open,Closed"
|
|
bitfld.long 0x04 20. " SW_C2CC ,Controls C2CC switch" "Open,Closed"
|
|
bitfld.long 0x04 16.--18. " SW_F2CB ,Select waveform for F2CB switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " SW_F2CA ,Select waveform for F2CA switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
bitfld.long 0x04 8.--10. " SW_F2MA ,Select waveform for F2MA switch" "Open,Closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,?..."
|
|
bitfld.long 0x04 4. " SW_F2PT ,Controls F2PT switch" "Open,Closed"
|
|
sif CPUIS("CY8C6*")
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SW_DSI_SEL,DSI Output Switch Control Waveform Selection"
|
|
bitfld.long 0x00 4.--7. " DSI_CMOD ,Select waveform for dsi_cmod output signal" "Static open,Static closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,!Sense,Phi1 delayed,Phi2 delayed,!Phi1,!Phi2,!(Phi1&HSCMP),!(Phi2&HSCMP),!HSCMP,Sense"
|
|
bitfld.long 0x00 0.--3. " DSI_CSH_TANK ,Select waveform for dsi_csh_tank output signal" "Static open,Static closed,Phi1,Phi2,Phi1 & HSCMP,Phi2 & HSCMP,HSCMP,!Sense,Phi1 delayed,Phi2 delayed,!Phi1,!Phi2,!(Phi1&HSCMP),!(Phi2&HSCMP),!HSCMP,Sense"
|
|
else
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "SW_DSI_SEL,DSI Output Switch Control Waveform Selection"
|
|
bitfld.long 0x00 4.--6. " DSI_CMOD ,This field select waveform for dsi_cmod signal" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " DSI_CSH_TANK ,This field select waveform for dsi_csh_tank signal" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif CPUIS("CY8C6*")
|
|
textline " "
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "IO_SEL,IO output control Waveform selection"
|
|
bitfld.long 0x00 24.--27. " CSD_TX_N_AMUXA_EN ,Select waveform for csd_tx_n_amuxa_en output signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " CSD_TX_N_OUT_EN ,Select waveform for csd_tx_n_out_en output signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " CSD_TX_N_OUT ,Select waveform for csd_tx_n_out output signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CSD_TX_AMUXB_EN ,Select waveform for csd_tx_amuxb_en output signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 4.--7. " CSD_TX_OUT_EN ,Select waveform for csd_tx_out_en output signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " CSD_TX_OUT ,Select waveform for csd_tx_out output signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
endif
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "SEQ_TIME,Sequencer Timing"
|
|
hexmask.long.byte 0x00 0.--7. 1. " AZ_TIME ,Auto-zero time in terms of senseclk cycles"
|
|
group.long 0x310++0x07
|
|
line.long 0x00 "SEQ_INIT_CNT,Sequencer Initial Conversion And Sample Counts"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONV_CNT ,Number of conversions per initialization sample"
|
|
line.long 0x04 "SEQ_NORM_CNT,Sequencer Normal Conversion And Sample Counts"
|
|
hexmask.long.word 0x04 0.--15. 1. " CONV_CNT ,Number of conversions per sample"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "ADC_CTL,ADC Control"
|
|
bitfld.long 0x00 16.--17. " ADC_MODE ,Enables ADC measurement" "OFF,VREF_CNT,VREF_BY2_CNT,VIN_CNT"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ADC_TIME ,This field specifies the duration for which ADC captures the input voltage or discharges the CREF1 and CREF2 capacitors"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "SEQ_START,Sequencer Start"
|
|
sif CPUIS("CY8C6*")
|
|
bitfld.long 0x00 9. " AZ1_SKIP ,Skip AutoZero_1 state" "Not skipped,Skipped"
|
|
bitfld.long 0x00 8. " AZ0_SKIP ,Skip AutoZero_0 state" "Not skipped,Skipped"
|
|
else
|
|
bitfld.long 0x00 9. " AZ1_SKIP ,This field enables or disables the autozero_1 state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " AZ0_SKIP ,This field enables or disables the autozero_0 state" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 4. " DSI_START_EN ,When bit is set A positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " ABORT ,This field when set to '1' aborts the CSD and ADC sequencers operations and clears the START bit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SEQ_MODE ,This field specifies the sequencer mode" "Regular,Coarse"
|
|
bitfld.long 0x00 0. " START ,This field when set to '1' starts the CSD sequencer" "Not started,Started"
|
|
sif CPUIS("CY8C6*")
|
|
if (((per.l(ad:0x400C0000+0x400))&0x80)==0x80)
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "IDACA,IDACA Configuration"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs with MMIO controls or not" "No DSI control,MMIO mixed with DSI control"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,Usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,Usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,Balancing mode" "FULL,PHI1,PHI2,PHI1_2"
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Polarity of the IDAC" "VSSA_SRC,VDDA_SNK,SENSE,SENSE_INV"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
else
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "IDACA,IDACA Configuration"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA" "Disabled,Enabled"
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs with MMIO controls or not" "No DSI control,MMIO mixed with DSI control"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,Usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,Usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,Balancing mode" "FULL,PHI1,PHI2,PHI1_2"
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Polarity of the IDAC" "VSSA_SRC,VDDA_SNK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,IDAC polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
endif
|
|
textline " "
|
|
if (((per.l(ad:0x400C0000+0x500))&0x80)==0x80)
|
|
if (((per.l(ad:0x400C0000+0x500))&0xC00000)==0x000000)
|
|
if (((per.l(ad:0x400C0000+0x500))&0x04000000)==0x04000000)
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
bitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA or CSDBUSB" "Disabled,?..."
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA or CSDBUSB" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs with MMIO controls or not" "No DSI control,MMIO mixed with DSI control"
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,Usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,Usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,Balancing mode" "FULL,PHI1,PHI2,PHI1_2"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,Polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
else
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
bitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs whit MMIO controls or not" "No DSI control,MMIO mixed with DSI control"
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,Usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,Usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,Balancing mode" "FULL,PHI1,PHI2,PHI1_2"
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Polarity of the IDAC (sensing operation)" "VSSA_SRC,VDDA_SNK,SENSE,SENSE_INV"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,Polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
endif
|
|
else
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
bitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs whit MMIO controls or not" "No DSI control,MMIO mixed with DSI control"
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,Usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,Usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,Balancing mode" "FULL,PHI1,PHI2,PHI1_2"
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Polarity of the IDAC (sensing operation)" "VSSA_SRC,VDDA_SNK,SENSE,SENSE_INV"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,Polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x400C0000+0x500))&0xC00000)==0x000000)
|
|
if (((per.l(ad:0x400C0000+0x500))&0x04000000)==0x04000000)
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
bitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA or CSDBUSB" "Disabled,?..."
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA or CSDBUSB" "Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs with MMIO controls or not" "No DSI control,MMIO mixed with DSI control"
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,Usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,Usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,Balancing mode" "FULL,PHI1,PHI2,PHI1_2"
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,Polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
else
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
bitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs whit MMIO controls or not" "No DSI control,MMIO mixed with DSI control"
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,Usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,Usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,Balancing mode" "FULL,PHI1,PHI2,PHI1_2"
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Polarity of the IDAC (sensing operation)" "VSSA_SRC,VDDA_SNK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,Polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
endif
|
|
else
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "IDACB,IDACB Configuration"
|
|
bitfld.long 0x00 26. " LEG3_EN ,Output enable for leg 3 to CSDBUSC" "Disabled,"
|
|
bitfld.long 0x00 25. " LEG2_EN ,Output enable for leg 2 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " LEG1_EN ,Output enable for leg 1 to CSDBUSA or CSDBUSB" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " RANGE ,IDAC multiplier" "IDAC_LO,IDAC_MED,IDAC_HI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " DSI_CTRL_EN ,Mix DSI inputs whit MMIO controls or not" "No DSI control,MMIO mixed with DSI control"
|
|
bitfld.long 0x00 18.--19. " LEG2_MODE ,Usage mode of LEG2" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
bitfld.long 0x00 16.--17. " LEG1_MODE ,Usage mode of LEG1 and the polarity bit" "GP_STATIC,GP,CSD_STATIC,CSD"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " BAL_MODE ,Balancing mode" "FULL,PHI1,PHI2,PHI1_2"
|
|
bitfld.long 0x00 8.--9. " POLARITY ,Polarity of the IDAC (sensing operation)" "VSSA_SRC,VDDA_SNK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " POL_DYN ,Polarity" "STATIC,DYNAMIC"
|
|
hexmask.long.byte 0x00 0.--6. 1. " VAL ,Current value setting for this IDAC"
|
|
endif
|
|
endif
|
|
endif
|
|
sif !CPUIS("CY8C6*")
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "TRIM_CTRL,Trim Control"
|
|
bitfld.long 0x00 4.--5. " DELAY_HYS ,Hysteresis input for shield delay block" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. " DELAY_TRIM ,Trim input for shield delay block" "0,1,2,3"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.open "CTB"
|
|
tree "CTB 0"
|
|
base ad:0x40300000
|
|
width 23.
|
|
if (((per.l(ad:0x40300000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTB_CTRL,Global CTB And Power Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DEEPSLEEP_ON ,DeepSleep mode" "Disabled,Enabled"
|
|
line.long 0x04 "OA_RES0_CTRL,Opamp0 And Resistor0 Control"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x04 31. " VALID_SEL0_EN ,Enable UAB valid selection" "Disabled,Enabled"
|
|
bitfld.long 0x04 28.--30. " VALID_SEL0 ,Select which UAB valid to use to sample the comparator output" "Valid 0,Valid 1,?..."
|
|
bitfld.long 0x04 24.--27. " C0_FB ,Feed back cap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 21. " RES0_TAP_OVR ,RES0 tap override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x04 20. " RES0_SWAP ,Swap top and bottom resistor value" "Not swapped,Swapped"
|
|
bitfld.long 0x04 16.--19. " RES0_TAP ,PGA gain" "1.0,1.42,2.0,2.78,4.0,5.82,8.0,5.82,8.0,10.67,16.0,21.33,32.0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " OA0_PUMP_EN ,Opamp0 pump enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--9. " OA0_COMPINT ,Opamp0 comparator edge detect for output and interrupt" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OA0_DSI_LEVEL ,Opamp0 comparator output" "Pulse,Level"
|
|
bitfld.long 0x04 6. " OA0_DSI_BYPASS ,Opamp0 bypass comparator output synchronization" "Synchronized,Bypassed"
|
|
bitfld.long 0x04 5. " OA0_HYST_EN ,Opamp0 hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " OA0_COMP_EN ,Opamp0 comparator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " OA0_DRIVE_STR_SEL ,Opamp0 output strength select" "1x,10x"
|
|
bitfld.long 0x04 0.--1. " OA0_PWR_MODE ,Opamp0 power level" "OFF,Low Power,Medium Power,High Power"
|
|
line.long 0x08 "OA_RES1_CTRL,Opamp1 And Resistor1 Control"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x08 31. " VALID_SEL1_EN ,Enable UAB valid selection" "Disabled,Enabled"
|
|
bitfld.long 0x08 28.--30. " VALID_SEL1 ,Select which UAB valid to use to sample the comparator output" "Valid 0,Valid 1,?..."
|
|
bitfld.long 0x08 24.--27. " C1_FB ,Feed back cap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 21. " RES1_TAP_OVR ,RES1 tap override" "Not override,Override"
|
|
textline " "
|
|
bitfld.long 0x08 20. " RES1_SWAP ,Swap top and bottom resistor value" "Not swapped,Swapped"
|
|
bitfld.long 0x08 16.--19. " RES1_TAP ,PGA gain" "1.0,1.42,2.0,2.78,4.0,5.82,8.0,5.82,8.0,10.67,16.0,21.33,32.0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 11. " OA1_PUMP_EN ,Opamp1 pump enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8.--9. " OA1_COMPINT ,Opamp1 comparator edge detect for output and interrupt" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x08 7. " OA1_DSI_LEVEL ,Opamp1 comparator output" "Pulse,Level"
|
|
bitfld.long 0x08 6. " OA1_DSI_BYPASS ,Opamp1 bypass comparator output synchronization" "Synchronize,Bypass"
|
|
bitfld.long 0x08 5. " OA1_HYST_EN ,Opamp1 hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " OA1_COMP_EN ,Opamp1 comparator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " OA1_DRIVE_STR_SEL ,Opamp1 output strength select" "1x,10x"
|
|
bitfld.long 0x08 0.--1. " OA1_PWR_MODE ,Opamp1 power level" "OFF,Low power,Medium power,High power"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "COMP_STAT,Comparator Status"
|
|
bitfld.long 0x00 16. " OA1_COMP ,Opamp1 current comparator status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OA0_COMP ,Opamp0 current comparator status" "Disabled,Enabled"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " COMP1 ,Comparator 1 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " COMP0 ,Comparator 0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,Interrupt Request Set Register"
|
|
bitfld.long 0x04 1. " COMP1_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " COMP0_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,Interrupt Request Mask"
|
|
bitfld.long 0x08 1. " COMP1_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " COMP0_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt Request Masked"
|
|
bitfld.long 0x00 1. " COMP1_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " COMP0_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DFT_CTRL,Risk Mitigation Bits"
|
|
bitfld.long 0x00 31. " DFT_EN ,Risk mitigation bit 3" "0,1"
|
|
bitfld.long 0x00 0.--2. " DFT_MODE ,Risk mitigation bits 0-2" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x80++0x17
|
|
line.long 0x00 "OA0_SW,Opamp0 Switch Control"
|
|
bitfld.long 0x00 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OA0O_D51 ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 14. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x04 "OA0_SW_CLEAR,Opamp0 Switch Control Clear"
|
|
eventfld.long 0x04 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 18. " OA0O_D51 ,Opamp0 output to sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 14. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x04 8. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
line.long 0x08 "OA1_SW,Opamp1 Switch Control"
|
|
bitfld.long 0x08 21. " OA1O_D82 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OA1O_D62 ,Opamp0 output to sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 18. " OA1O_D52 ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 14. " OA1M_A82 ,Opamp1 negative terminal to opamp1 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 8. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus01" "Not switched,Switched"
|
|
bitfld.long 0x08 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not switched,Switched"
|
|
bitfld.long 0x08 0. " OA1P_A03 ,Opamp1 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x0C "OA1_SW_CLEAR,Opamp1 Switch Control Clear"
|
|
eventfld.long 0x0C 21. " OA1O_D82 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " OA1O_D62 ,Opamp0 output to sarbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 18. " OA1O_D52 ,Opamp0 output to sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 14. " OA1M_A82 ,Opamp1 negative terminal to opamp1 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 8. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus01" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 0. " OA1P_A03 ,Opamp1 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTB_SW_HW_CTRL,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 3. " P3_HW_CTRL ,Pin P3 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " P2_HW_CTRL ,Pin P2 switches" "Not switched,Switched"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CTB_SW_STATUS,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp0 output to sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
group.long 0xF00++0x17
|
|
line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x00 0.--5. " OA0_OFFSET_TRIM ,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "OA0_SLOPE_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x04 0.--5. " OA0_SLOPE_OFFSET_TRIM ,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "OA0_COMP_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x08 0.--1. " OA0_COMP_TRIM ,Opamp0 compenation capacitor trim" "0,1,2,3"
|
|
line.long 0x0C "OA1_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x0C 0.--5. " OA1_OFFSET_TRIM ,Opamp1 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "OA1_SLOPE_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x10 0.--5. " OA1_SLOPE_OFFSET_TRIM ,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "OA1_COMP_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x14 0.--1. " OA1_COMP_TRIM ,Opamp1 compenation capacitor trim" "0,1,2,3"
|
|
else
|
|
group.long 0x80++0x17
|
|
line.long 0x00 "OA0_SW,Opamp0 Switch Control"
|
|
bitfld.long 0x00 30. " RES0_R81 ,Resistor0 tap to opamp0 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " RES0_R71 ,Resistor0 tap to opamp0 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " RES0_R61 ,Resistor0 bottom to VSSA" "Not switched,Switched"
|
|
bitfld.long 0x00 27. " RES0_R41 ,Resistor0 bottom to opamp1 negative terminal" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RES0_R31 ,Resistor0 bottom to opamp0 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 25. " RES0_R11 ,Resistor0 bottom to opamp1 output" "Not switched,Switched"
|
|
bitfld.long 0x00 24. " RES0_R01 ,Resistor0 bottom to pin P1" "Not switched,Switched"
|
|
bitfld.long 0x00 23. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " OA0O_D71 ,Opamp0 output to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 21. " OA0O_D51 ,Opamp0 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 20. " OA0O_D31 ,Opamp0 output to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 19. " OA0M_A91 ,Opamp0 negative terminal to pin P2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x00 17. " OA0M_A71 ,Opamp0 negative terminal to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " OA0M_A61 ,Opamp0 negative terminal to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " OA0M_A51 ,Opamp0 negative terminal to ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OA0M_A41 ,Opamp0 negative terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 13. " OA0M_A31 ,Opamp0 negative terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not switched,Switched"
|
|
bitfld.long 0x00 9. " OA0P_A90 ,Opamp0 positive terminal to uabin1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OA0P_A80 ,Opamp0 positive terminal to uabin0" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " OA0P_A70 ,Opamp0 positive terminal to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 6. " OA0P_A60 ,Opamp0 positive terminal to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 5. " OA0P_A50 ,Opamp0 positive terminal to ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OA0P_A40 ,Opamp0 positive terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not switched,Switched"
|
|
bitfld.long 0x00 1. " OA0P_A10 ,Opamp0 positive terminal to pin P1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x04 "OA0_SW_CLEAR,Opamp0 Switch Control Clear"
|
|
eventfld.long 0x04 30. " RES0_R81 ,Resistor0 tap to opamp0 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 29. " RES0_R71 ,Resistor0 tap to opamp0 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 28. " RES0_R61 ,Resistor0 bottom to VSSA" "Not cleared,Cleared"
|
|
eventfld.long 0x04 27. " RES0_R41 ,Resistor0 bottom to opamp1 negative terminal" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 26. " RES0_R31 ,Resistor0 bottom to opamp0 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 25. " RES0_R11 ,Resistor0 bottom to opamp1 output" "Not cleared,Cleared"
|
|
eventfld.long 0x04 24. " RES0_R01 ,Resistor0 bottom to pin P1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 23. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 22. " OA0O_D71 ,Opamp0 output to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 21. " OA0O_D51 ,Opamp0 output to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x04 20. " OA0O_D31 ,Opamp0 output to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 19. " OA0M_A91 ,Opamp0 negative terminal to pin P2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 18. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x04 17. " OA0M_A71 ,Opamp0 negative terminal to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 16. " OA0M_A61 ,Opamp0 negative terminal to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x04 15. " OA0M_A51 ,Opamp0 negative terminal to ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 14. " OA0M_A41 ,Opamp0 negative terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 13. " OA0M_A31 ,Opamp0 negative terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 11. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 9. " OA0P_A90 ,Opamp0 positive terminal to uabin1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 8. " OA0P_A80 ,Opamp0 positive terminal to uabin0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 7. " OA0P_A70 ,Opamp0 positive terminal to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 6. " OA0P_A60 ,Opamp0 positive terminal to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x04 5. " OA0P_A50 ,Opamp0 positive terminal to ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 4. " OA0P_A40 ,Opamp0 positive terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 1. " OA0P_A10 ,Opamp0 positive terminal to pin P1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
line.long 0x08 "OA1_SW,Opamp1 Switch Control"
|
|
bitfld.long 0x08 31. " RES1_R92 ,Resistor1 tap to opamp0 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 30. " RES1_R82 ,Resistor1 tap to opamp1 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 29. " RES1_R72 ,Resistor1 tap to opamp1 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 28. " RES1_R62 ,Resistor1 bottom to VSSA" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 27. " RES1_R52 ,Resistor1 bottom to resistor0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 26. " RES1_R32 ,Resistor1 bottom to opamp1 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 25. " RES1_R02 ,Resistor1 bottom to pin P4" "Not switched,Switched"
|
|
bitfld.long 0x08 24. " OA10_D82 ,Opamp1 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OA1O_D72 ,Opamp1 output to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 22. " OA1O_D62 ,Opamp1 output to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x08 21. " OA1O_D52 ,Opamp1 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 20. " OA1O_D42 ,Opamp1 output to ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OA1M_A92 ,Opamp1 negative terminal to pin P3" "Not switched,Switched"
|
|
bitfld.long 0x08 18. " OA1M_A82 ,Opamp1 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 17. " OA1M_A72 ,Opamp1 negative terminal to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 16. " OA1M_A62 ,Opamp1 negative terminal to ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OA1M_A52 ,Opamp1 negative terminal to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 14. " OA1M_A42 ,Opamp1 negative terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 13. " OA1M_A32 ,Opamp1 negative terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 12. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OA1P_A93 ,Opamp1 positive terminal to uabin1" "Not switched,Switched"
|
|
bitfld.long 0x08 8. " OA1P_A83 ,Opamp1 positive terminal to uabin0" "Not switched,Switched"
|
|
bitfld.long 0x08 7. " OA1P_A73 ,Opamp1 positive terminal to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 6. " OA1P_A63 ,Opamp1 positive terminal to ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OA1P_A53 ,Opamp1 positive terminal to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 3. " OA1P_A33 ,Opamp1 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 2. " OA1P_A23 ,Opamp1 positive terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not switched,Switched"
|
|
bitfld.long 0x08 0. " OA1P_A03 ,Opamp positive terminal to amuxbusb" "Not switched,Switched"
|
|
line.long 0x0C "OA1_SW_CLEAR,Opamp1 Switch Control Clear"
|
|
eventfld.long 0x0C 31. " RES1_R92 ,Resistor1 tap to opamp0 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 30. " RES1_R82 ,Resistor1 tap to opamp1 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 29. " RES1_R72 ,Resistor1 tap to opamp1 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 28. " RES1_R62 ,Resistor1 bottom to VSSA" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 27. " RES1_R52 ,Resistor1 bottom to resistor0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 26. " RES1_R32 ,Resistor1 bottom to opamp1 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 25. " RES1_R02 ,Resistor1 bottom to pin P4" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 24. " OA10_D82 ,Opamp1 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 23. " OA1O_D72 ,Opamp1 output to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 22. " OA1O_D62 ,Opamp1 output to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 21. " OA1O_D52 ,Opamp1 output to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 20. " OA1O_D42 ,Opamp1 output to ctbbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " OA1M_A92 ,Opamp1 negative terminal to pin P3" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 18. " OA1M_A82 ,Opamp1 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 17. " OA1M_A72 ,Opamp1 negative terminal to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 16. " OA1M_A62 ,Opamp1 negative terminal to ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 15. " OA1M_A52 ,Opamp1 negative terminal to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 14. " OA1M_A42 ,Opamp1 negative terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 13. " OA1M_A32 ,Opamp1 negative terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 12. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 9. " OA1P_A93 ,Opamp1 positive terminal to uabin1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 8. " OA1P_A83 ,Opamp1 positive terminal to uabin0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 7. " OA1P_A73 ,Opamp1 positive terminal to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 6. " OA1P_A63 ,Opamp1 positive terminal to ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 5. " OA1P_A53 ,Opamp1 positive terminal to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 3. " OA1P_A33 ,Opamp1 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 2. " OA1P_A23 ,Opamp1 positive terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 0. " OA1P_A03 ,Opamp positive terminal to amuxbusb" "Not cleared,Cleared"
|
|
line.long 0x10 "CTBBUS_SW,CTB Bus Switch Control"
|
|
bitfld.long 0x10 28. " CB2_G50 ,Ctbbus2 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 27. " CB3_G61 ,Ctbbus3 sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 26. " CB2_G52 ,Ctbbus2 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 25. " CB1_G41 ,Ctbbus1 sarbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 24. " CB0_G32 ,Ctbbus0 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 23. " CB3_G63 ,Ctbbus3 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 22. " CB2_G53 ,Ctbbus2 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 21. " CB1_G43 ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 20. " CB0_G33 ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 19. " CB3_P37 ,P7 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 18. " CB3_P35 ,P5 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 17. " CB3_P33 ,P3 ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 16. " CB3_P31 ,P1 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 15. " CB2_P26 ,P6 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 14. " CB2_P24 ,P4 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 13. " CB2_P22 ,P2 ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 12. " CB2_P20 ,P0 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 11. " CB1_P17 ,P7 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 10. " CB1_P15 ,P5 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 9. " CB1_P13 ,P3 ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 8. " CB1_P11 ,P1 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 7. " CB0_P07 ,P7 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 6. " CB0_P06 ,P6 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 5. " CB0_P05 ,P5 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 4. " CB0_P04 ,P4 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 3. " CB0_P03 ,P3 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 2. " CB0_P02 ,P2 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 1. " CB0_P01 ,P1 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CB0_P00 ,P0 ctbbus0" "Not switched,Switched"
|
|
line.long 0x14 "CTBBUS_SW_CLEAR,CTB Bus Switch Control Clear"
|
|
eventfld.long 0x14 28. " CB2_G50 ,Ctbbus2 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 27. " CB3_G61 ,Ctbbus3 sarbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 26. " CB2_G52 ,Ctbbus2 sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 25. " CB1_G41 ,Ctbbus1 sarbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 24. " CB0_G32 ,Ctbbus0 sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 23. " CB3_G63 ,Ctbbus3 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 22. " CB2_G53 ,Ctbbus2 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 21. " CB1_G43 ,Ctbbus1 right neighbor" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 20. " CB0_G33 ,Ctbbus1 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 19. " CB3_P37 ,P7 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 18. " CB3_P35 ,P5 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 17. " CB3_P33 ,P3 ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 16. " CB3_P31 ,P1 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 15. " CB2_P26 ,P6 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 14. " CB2_P24 ,P4 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 13. " CB2_P22 ,P2 ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 12. " CB2_P20 ,P0 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 11. " CB1_P17 ,P7 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 10. " CB1_P15 ,P5 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 9. " CB1_P13 ,P3 ctbbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 8. " CB1_P11 ,P1 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 7. " CB0_P07 ,P7 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 6. " CB0_P06 ,P6 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 5. " CB0_P05 ,P5 ctbbus0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 4. " CB0_P04 ,P4 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 3. " CB0_P03 ,P3 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 2. " CB0_P02 ,P2 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 1. " CB0_P01 ,P1 ctbbus0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 0. " CB0_P00 ,P0 ctbbus0" "Not cleared,Cleared"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTB_SW_HW_CTRL,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 17. " SARBUS1_HW_CTRL ,Sarbus1 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " SARBUS0_HW_CTRL ,Sarbus0 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " P7_HW_CTRL23 ,For P37" "Not switched,Switched"
|
|
bitfld.long 0x00 14. " P6_HW_CTRL23 ,For P26" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P5_HW_CTRL23 ,For P35" "Not switched,Switched"
|
|
bitfld.long 0x00 12. " P4_HW_CTRL23 ,For P24" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " P3_HW_CTRL23 ,For P33 D52 D62" "Not switched,Switched"
|
|
bitfld.long 0x00 10. " P2_HW_CTRL23 ,For P22 D51" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P1_HW_CTRL23 ,For P31" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " P0_HW_CTRL23 ,For P20" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " P7_HW_CTRL01 ,For P07 P17" "Not switched,Switched"
|
|
bitfld.long 0x00 6. " P6_HW_CTRL01 ,For P06" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5_HW_CTRL01 ,For P05 P15" "Not switched,Switched"
|
|
bitfld.long 0x00 4. " P4_HW_CTRL01 ,For P04" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " P3_HW_CTRL01 ,For P03 P13" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " P2_HW_CTRL01 ,For P02" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1_HW_CTRL01 ,For P01 P11" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " P0_HW_CTRL01 ,For P00" "Not switched,Switched"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CTB_SW_STATUS,CTB Switch Control Status"
|
|
bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp1 output to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp1 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 27. " CB3_G61_STAT ,Ctbbus3 sarbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CB2_G52_STAT ,Ctbbus2 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 25. " CB1_G41_STAT ,Ctbbus1 sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 24. " CB0_G32_STAT ,Ctbbus0 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 23. " CB3_G63_STAT ,Ctbbus3 right neighbor" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CB2_G53_STAT ,Ctbbus2 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 21. " CB1_G43_STAT ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 20. " CB0_G33_STAT ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 19. " CB3_P37_STAT ,P7 ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CB3_P35_STAT ,P5 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 17. " CB3_P33_STAT ,P3 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " CB3_P31_STAT ,P1 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " CB2_P26_STAT ,P6 ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CB2_P24_STAT ,P4 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 13. " CB2_P22_STAT ,P2 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 12. " CB2_P20_STAT ,P0 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " CB1_P17_STAT ,P7 ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CB1_P15_STAT ,P5 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 9. " CB1_P13_STAT ,P3 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " CB1_P11_STAT ,P1 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " CB0_P07_STAT ,P7 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CB0_P06_STAT ,P6 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 5. " CB0_P05_STAT ,P5 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 4. " CB0_P04_STAT ,P4 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " CB0_P03_STAT ,P3 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CB0_P02_STAT ,P2 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 1. " CB0_P01_STAT ,P1 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " CB0_P00_STAT ,P0 ctbbus0" "Not switched,Switched"
|
|
group.long 0xF00++0x1B
|
|
line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x00 0.--5. " OA0_OFFSET_TRIM ,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "OA0_SLOPE_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x04 0.--5. " OA0_SLOPE_OFFSET_T ,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "OA0_COMP_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x08 0.--1. " OA0_COMP_TRIM ,Opamp0 compensation capacitor trim" "0,1,2,3"
|
|
line.long 0x0C "OA1_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x0C 0.--5. " OA1_OFFSET_TRIM ,Opamp1 offs et trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "OA1_SLOPE_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x10 0.--5. " OA1_SLOPE_OFFSET_T ,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "OA1_COMP_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x14 0.--1. " OA1_COMP_TRIM ,Opamp1 compensation capacitor trim" "0,1,2,3"
|
|
line.long 0x18 "RMP_TRIM,Risk Mitigation Bits"
|
|
bitfld.long 0x18 0.--3. " RMP_TRIM ,Risk mitigation trim bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTB_CTRL,Global CTB And Power Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "CTB 1"
|
|
base ad:0x40310000
|
|
width 23.
|
|
if (((per.l(ad:0x40310000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTB_CTRL,Global CTB And Power Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DEEPSLEEP_ON ,DeepSleep mode" "Disabled,Enabled"
|
|
line.long 0x04 "OA_RES0_CTRL,Opamp0 And Resistor0 Control"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x04 31. " VALID_SEL0_EN ,Enable UAB valid selection" "Disabled,Enabled"
|
|
bitfld.long 0x04 28.--30. " VALID_SEL0 ,Select which UAB valid to use to sample the comparator output" "Valid 0,Valid 1,?..."
|
|
bitfld.long 0x04 24.--27. " C0_FB ,Feed back cap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 21. " RES0_TAP_OVR ,RES0 tap override" "No override,Override"
|
|
textline " "
|
|
bitfld.long 0x04 20. " RES0_SWAP ,Swap top and bottom resistor value" "Not swapped,Swapped"
|
|
bitfld.long 0x04 16.--19. " RES0_TAP ,PGA gain" "1.0,1.42,2.0,2.78,4.0,5.82,8.0,5.82,8.0,10.67,16.0,21.33,32.0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " OA0_PUMP_EN ,Opamp0 pump enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8.--9. " OA0_COMPINT ,Opamp0 comparator edge detect for output and interrupt" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OA0_DSI_LEVEL ,Opamp0 comparator output" "Pulse,Level"
|
|
bitfld.long 0x04 6. " OA0_DSI_BYPASS ,Opamp0 bypass comparator output synchronization" "Synchronized,Bypassed"
|
|
bitfld.long 0x04 5. " OA0_HYST_EN ,Opamp0 hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " OA0_COMP_EN ,Opamp0 comparator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " OA0_DRIVE_STR_SEL ,Opamp0 output strength select" "1x,10x"
|
|
bitfld.long 0x04 0.--1. " OA0_PWR_MODE ,Opamp0 power level" "OFF,Low Power,Medium Power,High Power"
|
|
line.long 0x08 "OA_RES1_CTRL,Opamp1 And Resistor1 Control"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x08 31. " VALID_SEL1_EN ,Enable UAB valid selection" "Disabled,Enabled"
|
|
bitfld.long 0x08 28.--30. " VALID_SEL1 ,Select which UAB valid to use to sample the comparator output" "Valid 0,Valid 1,?..."
|
|
bitfld.long 0x08 24.--27. " C1_FB ,Feed back cap value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 21. " RES1_TAP_OVR ,RES1 tap override" "Not override,Override"
|
|
textline " "
|
|
bitfld.long 0x08 20. " RES1_SWAP ,Swap top and bottom resistor value" "Not swapped,Swapped"
|
|
bitfld.long 0x08 16.--19. " RES1_TAP ,PGA gain" "1.0,1.42,2.0,2.78,4.0,5.82,8.0,5.82,8.0,10.67,16.0,21.33,32.0,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 11. " OA1_PUMP_EN ,Opamp1 pump enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8.--9. " OA1_COMPINT ,Opamp1 comparator edge detect for output and interrupt" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x08 7. " OA1_DSI_LEVEL ,Opamp1 comparator output" "Pulse,Level"
|
|
bitfld.long 0x08 6. " OA1_DSI_BYPASS ,Opamp1 bypass comparator output synchronization" "Synchronize,Bypass"
|
|
bitfld.long 0x08 5. " OA1_HYST_EN ,Opamp1 hysteresis enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " OA1_COMP_EN ,Opamp1 comparator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " OA1_DRIVE_STR_SEL ,Opamp1 output strength select" "1x,10x"
|
|
bitfld.long 0x08 0.--1. " OA1_PWR_MODE ,Opamp1 power level" "OFF,Low power,Medium power,High power"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "COMP_STAT,Comparator Status"
|
|
bitfld.long 0x00 16. " OA1_COMP ,Opamp1 current comparator status" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " OA0_COMP ,Opamp0 current comparator status" "Disabled,Enabled"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 1. " COMP1 ,Comparator 1 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " COMP0 ,Comparator 0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,Interrupt Request Set Register"
|
|
bitfld.long 0x04 1. " COMP1_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " COMP0_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,Interrupt Request Mask"
|
|
bitfld.long 0x08 1. " COMP1_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " COMP0_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt Request Masked"
|
|
bitfld.long 0x00 1. " COMP1_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " COMP0_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DFT_CTRL,Risk Mitigation Bits"
|
|
bitfld.long 0x00 31. " DFT_EN ,Risk mitigation bit 3" "0,1"
|
|
bitfld.long 0x00 0.--2. " DFT_MODE ,Risk mitigation bits 0-2" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x80++0x17
|
|
line.long 0x00 "OA0_SW,Opamp0 Switch Control"
|
|
bitfld.long 0x00 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OA0O_D51 ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 14. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x04 "OA0_SW_CLEAR,Opamp0 Switch Control Clear"
|
|
eventfld.long 0x04 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 18. " OA0O_D51 ,Opamp0 output to sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 14. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x04 8. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
line.long 0x08 "OA1_SW,Opamp1 Switch Control"
|
|
bitfld.long 0x08 21. " OA1O_D82 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OA1O_D62 ,Opamp0 output to sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 18. " OA1O_D52 ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 14. " OA1M_A82 ,Opamp1 negative terminal to opamp1 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 8. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus01" "Not switched,Switched"
|
|
bitfld.long 0x08 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not switched,Switched"
|
|
bitfld.long 0x08 0. " OA1P_A03 ,Opamp1 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x0C "OA1_SW_CLEAR,Opamp1 Switch Control Clear"
|
|
eventfld.long 0x0C 21. " OA1O_D82 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " OA1O_D62 ,Opamp0 output to sarbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 18. " OA1O_D52 ,Opamp0 output to sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 14. " OA1M_A82 ,Opamp1 negative terminal to opamp1 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 8. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus01" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 0. " OA1P_A03 ,Opamp1 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTB_SW_HW_CTRL,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 3. " P3_HW_CTRL ,Pin P3 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " P2_HW_CTRL ,Pin P2 switches" "Not switched,Switched"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CTB_SW_STATUS,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp0 output to sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output to sarbus0" "Not switched,Switched"
|
|
group.long 0xF00++0x17
|
|
line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x00 0.--5. " OA0_OFFSET_TRIM ,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "OA0_SLOPE_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x04 0.--5. " OA0_SLOPE_OFFSET_TRIM ,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "OA0_COMP_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x08 0.--1. " OA0_COMP_TRIM ,Opamp0 compenation capacitor trim" "0,1,2,3"
|
|
line.long 0x0C "OA1_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x0C 0.--5. " OA1_OFFSET_TRIM ,Opamp1 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "OA1_SLOPE_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x10 0.--5. " OA1_SLOPE_OFFSET_TRIM ,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "OA1_COMP_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x14 0.--1. " OA1_COMP_TRIM ,Opamp1 compenation capacitor trim" "0,1,2,3"
|
|
else
|
|
group.long 0x80++0x17
|
|
line.long 0x00 "OA0_SW,Opamp0 Switch Control"
|
|
bitfld.long 0x00 30. " RES0_R81 ,Resistor0 tap to opamp0 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " RES0_R71 ,Resistor0 tap to opamp0 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " RES0_R61 ,Resistor0 bottom to VSSA" "Not switched,Switched"
|
|
bitfld.long 0x00 27. " RES0_R41 ,Resistor0 bottom to opamp1 negative terminal" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RES0_R31 ,Resistor0 bottom to opamp0 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x00 25. " RES0_R11 ,Resistor0 bottom to opamp1 output" "Not switched,Switched"
|
|
bitfld.long 0x00 24. " RES0_R01 ,Resistor0 bottom to pin P1" "Not switched,Switched"
|
|
bitfld.long 0x00 23. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " OA0O_D71 ,Opamp0 output to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 21. " OA0O_D51 ,Opamp0 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 20. " OA0O_D31 ,Opamp0 output to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 19. " OA0M_A91 ,Opamp0 negative terminal to pin P2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x00 17. " OA0M_A71 ,Opamp0 negative terminal to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " OA0M_A61 ,Opamp0 negative terminal to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " OA0M_A51 ,Opamp0 negative terminal to ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OA0M_A41 ,Opamp0 negative terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 13. " OA0M_A31 ,Opamp0 negative terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not switched,Switched"
|
|
bitfld.long 0x00 9. " OA0P_A90 ,Opamp0 positive terminal to uabin1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OA0P_A80 ,Opamp0 positive terminal to uabin0" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " OA0P_A70 ,Opamp0 positive terminal to vref0" "Not switched,Switched"
|
|
bitfld.long 0x00 6. " OA0P_A60 ,Opamp0 positive terminal to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 5. " OA0P_A50 ,Opamp0 positive terminal to ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OA0P_A40 ,Opamp0 positive terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not switched,Switched"
|
|
bitfld.long 0x00 1. " OA0P_A10 ,Opamp0 positive terminal to pin P1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not switched,Switched"
|
|
line.long 0x04 "OA0_SW_CLEAR,Opamp0 Switch Control Clear"
|
|
eventfld.long 0x04 30. " RES0_R81 ,Resistor0 tap to opamp0 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 29. " RES0_R71 ,Resistor0 tap to opamp0 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 28. " RES0_R61 ,Resistor0 bottom to VSSA" "Not cleared,Cleared"
|
|
eventfld.long 0x04 27. " RES0_R41 ,Resistor0 bottom to opamp1 negative terminal" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 26. " RES0_R31 ,Resistor0 bottom to opamp0 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 25. " RES0_R11 ,Resistor0 bottom to opamp1 output" "Not cleared,Cleared"
|
|
eventfld.long 0x04 24. " RES0_R01 ,Resistor0 bottom to pin P1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 23. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 22. " OA0O_D71 ,Opamp0 output to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 21. " OA0O_D51 ,Opamp0 output to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x04 20. " OA0O_D31 ,Opamp0 output to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 19. " OA0M_A91 ,Opamp0 negative terminal to pin P2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 18. " OA0M_A81 ,Opamp0 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x04 17. " OA0M_A71 ,Opamp0 negative terminal to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 16. " OA0M_A61 ,Opamp0 negative terminal to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x04 15. " OA0M_A51 ,Opamp0 negative terminal to ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 14. " OA0M_A41 ,Opamp0 negative terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 13. " OA0M_A31 ,Opamp0 negative terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 11. " OA0M_A11 ,Opamp0 negative terminal to pin P1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 9. " OA0P_A90 ,Opamp0 positive terminal to uabin1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 8. " OA0P_A80 ,Opamp0 positive terminal to uabin0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 7. " OA0P_A70 ,Opamp0 positive terminal to vref0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 6. " OA0P_A60 ,Opamp0 positive terminal to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x04 5. " OA0P_A50 ,Opamp0 positive terminal to ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 4. " OA0P_A40 ,Opamp0 positive terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x04 3. " OA0P_A30 ,Opamp0 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " OA0P_A20 ,Opamp0 positive terminal to pin P0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 1. " OA0P_A10 ,Opamp0 positive terminal to pin P1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 0. " OA0P_A00 ,Opamp0 positive terminal to amuxbusa" "Not cleared,Cleared"
|
|
line.long 0x08 "OA1_SW,Opamp1 Switch Control"
|
|
bitfld.long 0x08 31. " RES1_R92 ,Resistor1 tap to opamp0 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 30. " RES1_R82 ,Resistor1 tap to opamp1 positive terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 29. " RES1_R72 ,Resistor1 tap to opamp1 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 28. " RES1_R62 ,Resistor1 bottom to VSSA" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 27. " RES1_R52 ,Resistor1 bottom to resistor0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 26. " RES1_R32 ,Resistor1 bottom to opamp1 negative terminal" "Not switched,Switched"
|
|
bitfld.long 0x08 25. " RES1_R02 ,Resistor1 bottom to pin P4" "Not switched,Switched"
|
|
bitfld.long 0x08 24. " OA10_D82 ,Opamp1 output switch to short 1x with 10x drive" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 23. " OA1O_D72 ,Opamp1 output to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 22. " OA1O_D62 ,Opamp1 output to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x08 21. " OA1O_D52 ,Opamp1 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 20. " OA1O_D42 ,Opamp1 output to ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 19. " OA1M_A92 ,Opamp1 negative terminal to pin P3" "Not switched,Switched"
|
|
bitfld.long 0x08 18. " OA1M_A82 ,Opamp1 negative terminal to opamp0 bottom" "Not switched,Switched"
|
|
bitfld.long 0x08 17. " OA1M_A72 ,Opamp1 negative terminal to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 16. " OA1M_A62 ,Opamp1 negative terminal to ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 15. " OA1M_A52 ,Opamp1 negative terminal to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 14. " OA1M_A42 ,Opamp1 negative terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 13. " OA1M_A32 ,Opamp1 negative terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 12. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OA1P_A93 ,Opamp1 positive terminal to uabin1" "Not switched,Switched"
|
|
bitfld.long 0x08 8. " OA1P_A83 ,Opamp1 positive terminal to uabin0" "Not switched,Switched"
|
|
bitfld.long 0x08 7. " OA1P_A73 ,Opamp1 positive terminal to vref1" "Not switched,Switched"
|
|
bitfld.long 0x08 6. " OA1P_A63 ,Opamp1 positive terminal to ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OA1P_A53 ,Opamp1 positive terminal to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x08 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x08 3. " OA1P_A33 ,Opamp1 positive terminal to ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x08 2. " OA1P_A23 ,Opamp1 positive terminal to pin P4" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x08 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not switched,Switched"
|
|
bitfld.long 0x08 0. " OA1P_A03 ,Opamp positive terminal to amuxbusb" "Not switched,Switched"
|
|
line.long 0x0C "OA1_SW_CLEAR,Opamp1 Switch Control Clear"
|
|
eventfld.long 0x0C 31. " RES1_R92 ,Resistor1 tap to opamp0 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 30. " RES1_R82 ,Resistor1 tap to opamp1 positive terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 29. " RES1_R72 ,Resistor1 tap to opamp1 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 28. " RES1_R62 ,Resistor1 bottom to VSSA" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 27. " RES1_R52 ,Resistor1 bottom to resistor0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 26. " RES1_R32 ,Resistor1 bottom to opamp1 negative terminal" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 25. " RES1_R02 ,Resistor1 bottom to pin P4" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 24. " OA10_D82 ,Opamp1 output switch to short 1x with 10x drive" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 23. " OA1O_D72 ,Opamp1 output to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 22. " OA1O_D62 ,Opamp1 output to ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 21. " OA1O_D52 ,Opamp1 output to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 20. " OA1O_D42 ,Opamp1 output to ctbbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " OA1M_A92 ,Opamp1 negative terminal to pin P3" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 18. " OA1M_A82 ,Opamp1 negative terminal to opamp0 bottom" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 17. " OA1M_A72 ,Opamp1 negative terminal to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 16. " OA1M_A62 ,Opamp1 negative terminal to ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 15. " OA1M_A52 ,Opamp1 negative terminal to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 14. " OA1M_A42 ,Opamp1 negative terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 13. " OA1M_A32 ,Opamp1 negative terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 12. " OA1M_A22 ,Opamp1 negative terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 9. " OA1P_A93 ,Opamp1 positive terminal to uabin1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 8. " OA1P_A83 ,Opamp1 positive terminal to uabin0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 7. " OA1P_A73 ,Opamp1 positive terminal to vref1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 6. " OA1P_A63 ,Opamp1 positive terminal to ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 5. " OA1P_A53 ,Opamp1 positive terminal to ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 4. " OA1P_A43 ,Opamp1 positive terminal to ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 3. " OA1P_A33 ,Opamp1 positive terminal to ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 2. " OA1P_A23 ,Opamp1 positive terminal to pin P4" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x0C 1. " OA1P_A13 ,Opamp1 positive terminal to pin P5" "Not cleared,Cleared"
|
|
eventfld.long 0x0C 0. " OA1P_A03 ,Opamp positive terminal to amuxbusb" "Not cleared,Cleared"
|
|
line.long 0x10 "CTBBUS_SW,CTB Bus Switch Control"
|
|
bitfld.long 0x10 28. " CB2_G50 ,Ctbbus2 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 27. " CB3_G61 ,Ctbbus3 sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 26. " CB2_G52 ,Ctbbus2 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 25. " CB1_G41 ,Ctbbus1 sarbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 24. " CB0_G32 ,Ctbbus0 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 23. " CB3_G63 ,Ctbbus3 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 22. " CB2_G53 ,Ctbbus2 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 21. " CB1_G43 ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 20. " CB0_G33 ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x10 19. " CB3_P37 ,P7 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 18. " CB3_P35 ,P5 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 17. " CB3_P33 ,P3 ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 16. " CB3_P31 ,P1 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x10 15. " CB2_P26 ,P6 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 14. " CB2_P24 ,P4 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 13. " CB2_P22 ,P2 ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 12. " CB2_P20 ,P0 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x10 11. " CB1_P17 ,P7 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 10. " CB1_P15 ,P5 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 9. " CB1_P13 ,P3 ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 8. " CB1_P11 ,P1 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x10 7. " CB0_P07 ,P7 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 6. " CB0_P06 ,P6 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 5. " CB0_P05 ,P5 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 4. " CB0_P04 ,P4 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 3. " CB0_P03 ,P3 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 2. " CB0_P02 ,P2 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x10 1. " CB0_P01 ,P1 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CB0_P00 ,P0 ctbbus0" "Not switched,Switched"
|
|
line.long 0x14 "CTBBUS_SW_CLEAR,CTB Bus Switch Control Clear"
|
|
eventfld.long 0x14 28. " CB2_G50 ,Ctbbus2 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 27. " CB3_G61 ,Ctbbus3 sarbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 26. " CB2_G52 ,Ctbbus2 sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 25. " CB1_G41 ,Ctbbus1 sarbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 24. " CB0_G32 ,Ctbbus0 sarbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 23. " CB3_G63 ,Ctbbus3 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 22. " CB2_G53 ,Ctbbus2 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 21. " CB1_G43 ,Ctbbus1 right neighbor" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 20. " CB0_G33 ,Ctbbus1 right neighbor" "Not cleared,Cleared"
|
|
eventfld.long 0x14 19. " CB3_P37 ,P7 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 18. " CB3_P35 ,P5 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 17. " CB3_P33 ,P3 ctbbus3" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 16. " CB3_P31 ,P1 ctbbus3" "Not cleared,Cleared"
|
|
eventfld.long 0x14 15. " CB2_P26 ,P6 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 14. " CB2_P24 ,P4 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 13. " CB2_P22 ,P2 ctbbus2" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 12. " CB2_P20 ,P0 ctbbus2" "Not cleared,Cleared"
|
|
eventfld.long 0x14 11. " CB1_P17 ,P7 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 10. " CB1_P15 ,P5 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 9. " CB1_P13 ,P3 ctbbus1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 8. " CB1_P11 ,P1 ctbbus1" "Not cleared,Cleared"
|
|
eventfld.long 0x14 7. " CB0_P07 ,P7 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 6. " CB0_P06 ,P6 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 5. " CB0_P05 ,P5 ctbbus0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 4. " CB0_P04 ,P4 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 3. " CB0_P03 ,P3 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 2. " CB0_P02 ,P2 ctbbus0" "Not cleared,Cleared"
|
|
eventfld.long 0x14 1. " CB0_P01 ,P1 ctbbus0" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x14 0. " CB0_P00 ,P0 ctbbus0" "Not cleared,Cleared"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CTB_SW_HW_CTRL,CTB Bus Switch Control Status"
|
|
bitfld.long 0x00 17. " SARBUS1_HW_CTRL ,Sarbus1 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " SARBUS0_HW_CTRL ,Sarbus0 switches" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " P7_HW_CTRL23 ,For P37" "Not switched,Switched"
|
|
bitfld.long 0x00 14. " P6_HW_CTRL23 ,For P26" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " P5_HW_CTRL23 ,For P35" "Not switched,Switched"
|
|
bitfld.long 0x00 12. " P4_HW_CTRL23 ,For P24" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " P3_HW_CTRL23 ,For P33 D52 D62" "Not switched,Switched"
|
|
bitfld.long 0x00 10. " P2_HW_CTRL23 ,For P22 D51" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " P1_HW_CTRL23 ,For P31" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " P0_HW_CTRL23 ,For P20" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " P7_HW_CTRL01 ,For P07 P17" "Not switched,Switched"
|
|
bitfld.long 0x00 6. " P6_HW_CTRL01 ,For P06" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P5_HW_CTRL01 ,For P05 P15" "Not switched,Switched"
|
|
bitfld.long 0x00 4. " P4_HW_CTRL01 ,For P04" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " P3_HW_CTRL01 ,For P03 P13" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " P2_HW_CTRL01 ,For P02" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " P1_HW_CTRL01 ,For P01 P11" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " P0_HW_CTRL01 ,For P00" "Not switched,Switched"
|
|
rgroup.long 0xC4++0x03
|
|
line.long 0x00 "CTB_SW_STATUS,CTB Switch Control Status"
|
|
bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp1 output to ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp1 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output to ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 27. " CB3_G61_STAT ,Ctbbus3 sarbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 26. " CB2_G52_STAT ,Ctbbus2 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 25. " CB1_G41_STAT ,Ctbbus1 sarbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 24. " CB0_G32_STAT ,Ctbbus0 sarbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 23. " CB3_G63_STAT ,Ctbbus3 right neighbor" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CB2_G53_STAT ,Ctbbus2 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 21. " CB1_G43_STAT ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 20. " CB0_G33_STAT ,Ctbbus1 right neighbor" "Not switched,Switched"
|
|
bitfld.long 0x00 19. " CB3_P37_STAT ,P7 ctbbus3" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CB3_P35_STAT ,P5 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 17. " CB3_P33_STAT ,P3 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 16. " CB3_P31_STAT ,P1 ctbbus3" "Not switched,Switched"
|
|
bitfld.long 0x00 15. " CB2_P26_STAT ,P6 ctbbus2" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CB2_P24_STAT ,P4 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 13. " CB2_P22_STAT ,P2 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 12. " CB2_P20_STAT ,P0 ctbbus2" "Not switched,Switched"
|
|
bitfld.long 0x00 11. " CB1_P17_STAT ,P7 ctbbus1" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CB1_P15_STAT ,P5 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 9. " CB1_P13_STAT ,P3 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " CB1_P11_STAT ,P1 ctbbus1" "Not switched,Switched"
|
|
bitfld.long 0x00 7. " CB0_P07_STAT ,P7 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CB0_P06_STAT ,P6 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 5. " CB0_P05_STAT ,P5 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 4. " CB0_P04_STAT ,P4 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " CB0_P03_STAT ,P3 ctbbus0" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CB0_P02_STAT ,P2 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 1. " CB0_P01_STAT ,P1 ctbbus0" "Not switched,Switched"
|
|
bitfld.long 0x00 0. " CB0_P00_STAT ,P0 ctbbus0" "Not switched,Switched"
|
|
group.long 0xF00++0x1B
|
|
line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x00 0.--5. " OA0_OFFSET_TRIM ,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "OA0_SLOPE_OFFSET_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x04 0.--5. " OA0_SLOPE_OFFSET_T ,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "OA0_COMP_TRIM,Opamp0 Trim Control"
|
|
bitfld.long 0x08 0.--1. " OA0_COMP_TRIM ,Opamp0 compensation capacitor trim" "0,1,2,3"
|
|
line.long 0x0C "OA1_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x0C 0.--5. " OA1_OFFSET_TRIM ,Opamp1 offs et trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "OA1_SLOPE_OFFSET_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x10 0.--5. " OA1_SLOPE_OFFSET_T ,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x14 "OA1_COMP_TRIM,Opamp1 Trim Control"
|
|
bitfld.long 0x14 0.--1. " OA1_COMP_TRIM ,Opamp1 compensation capacitor trim" "0,1,2,3"
|
|
line.long 0x18 "RMP_TRIM,Risk Mitigation Bits"
|
|
bitfld.long 0x18 0.--3. " RMP_TRIM ,Risk mitigation trim bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CTB_CTRL,Global CTB And Power Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("CY8C4A45*"))
|
|
tree "DMAC (Direct-Memory Access)"
|
|
base ad:0x40101000
|
|
width 22.
|
|
if (((per.l(ad:0x40101000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
rgroup.long 0x10++0x0F
|
|
line.long 0x00 "STATUS,Status"
|
|
bitfld.long 0x00 31. " ACTIVE ,Specifies if there is a currently active channel in the data transfer engine" "Not active,Active"
|
|
bitfld.long 0x00 30. " PING_PONG ,Specifies whether the PING descriptor or PONG descriptor of the channel is currently in use" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Specifies the priority of the currently active channel" "Highest,2,1,Lowest"
|
|
bitfld.long 0x00 24.--26. " STATE ,State of the data transfer engine" "DEFAULT,Loading descriptor,Loading data,Storing data,Storing descriptor,Wait for trigger,Storing descriptor with error responses,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " CH_ADDR ,Specifies the channel number of the currently active channel" "CH0,CH1,CH2,CH3,CH4,CH5,CH6,CH7"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Specifies the index of the currently active data transfer"
|
|
line.long 0x04 "STATUS_SRC_ADDR,Source Address Status Register"
|
|
line.long 0x08 "STATUS_DST_ADDR,Destination Address Register"
|
|
line.long 0x0C "STATUS_CH_ACT,Channel Activation Status Register"
|
|
bitfld.long 0x0C 7. " CH[7] ,Channel 7 activation status bit" "Not pending,Pending"
|
|
bitfld.long 0x0C 6. " [6] ,Channel 6 activation status bit" "Not pending,Pending"
|
|
bitfld.long 0x0C 5. " [5] ,Channel 5 activation status bit" "Not pending,Pending"
|
|
bitfld.long 0x0C 4. " [4] ,Channel 4 activation status bit" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " [3] ,Channel 3 activation status bit" "Not pending,Pending"
|
|
bitfld.long 0x0C 2. " [2] ,Channel 2 activation status bit" "Not pending,Pending"
|
|
bitfld.long 0x0C 1. " [1] ,Channel 1 activation status bit" "Not pending,Pending"
|
|
bitfld.long 0x0C 0. " [0] ,Channel 0 activation status bit" "Not pending,Pending"
|
|
if (((per.l(ad:0x40101000+0x80))&0x80000000)==0x80000000)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH_CTL0,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH_CTL0,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x84))&0x80000000)==0x80000000)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CH_CTL1,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CH_CTL1,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x88))&0x80000000)==0x80000000)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CH_CTL2,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CH_CTL2,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x8C))&0x80000000)==0x80000000)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CH_CTL3,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CH_CTL3,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x90))&0x80000000)==0x80000000)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH_CTL4,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH_CTL4,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x94))&0x80000000)==0x80000000)
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CH_CTL5,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CH_CTL5,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x98))&0x80000000)==0x80000000)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CH_CTL6,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CH_CTL6,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x9C))&0x80000000)==0x80000000)
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CH_CTL7,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " PING_PONG ,Determines the type of descriptor" "PING,PONG"
|
|
bitfld.long 0x00 28.--29. " PRIO ,Channel priority" "Highest,2,1,Lowest"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CH_CTL7,Channel Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x7F0++0x0B
|
|
line.long 0x00 "INTR,Interrupt Register"
|
|
eventfld.long 0x00 7. " CH[7] ,Channel 7 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " [6] ,Channel 6 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Channel 5 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Channel 4 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Channel 3 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Channel 2 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Channel 1 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " [0] ,Channel 0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,Interrupt Set Register"
|
|
bitfld.long 0x04 7. " CH[7] ,Channel 7 interrupt set" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " [6] ,Channel 6 interrupt set" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " [5] ,Channel 5 interrupt set" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " [4] ,Channel 4 interrupt set" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Channel 3 interrupt set" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " [2] ,Channel 2 interrupt set" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " [1] ,Channel 1 interrupt set" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " [0] ,Channel 0 interrupt set" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x08 7. " CH[7] ,Mask channel 7 interrupt" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " [6] ,Mask channel 6 interrupt" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " [5] ,Mask channel 5 interrupt" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " [4] ,Mask channel 4 interrupt" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 3. " [3] ,Mask channel 3 interrupt" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " [2] ,Mask channel 2 interrupt" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " [1] ,Mask channel 1 interrupt" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " [0] ,Mask channel 0 interrupt" "Not masked,Masked"
|
|
rgroup.long 0x7FC++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt Masked Register"
|
|
bitfld.long 0x00 7. " CH[7] ,Logical AND of corresponding request and mask field for channel 7" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " [6] ,Logical AND of corresponding request and mask field for channel 6" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " [5] ,Logical AND of corresponding request and mask field for channel 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Logical AND of corresponding request and mask field for channel 4" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Logical AND of corresponding request and mask field for channel 3" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " [2] ,Logical AND of corresponding request and mask field for channel 2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Logical AND of corresponding request and mask field for channel 1" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " [0] ,Logical AND of corresponding request and mask field for channel 0" "Not masked,Masked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTL,Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree "Direct-Memory Access Descriptor"
|
|
base ad:0x40101800
|
|
width 21.
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x000000)
|
|
if (((per.l(ad:0x40101000+0x80))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x80))&0x40000000)==0x00000000)
|
|
group.long 0x0++0x07
|
|
line.long 0x00 "DESCR0_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR0_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0x0+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "DESCR0_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "DESCR0_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0x0+0x0C)++0x03
|
|
line.long 0x00 "DESCR0_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0x0+0x10)++0x07
|
|
line.long 0x00 "DESCR0_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR0_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0x0+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0x0+0x18)++0x03
|
|
line.long 0x00 "DESCR0_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x0+0x18)++0x03
|
|
line.long 0x00 "DESCR0_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR0_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x010000)
|
|
if (((per.l(ad:0x40101000+0x84))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x84))&0x40000000)==0x00000000)
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DESCR1_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR1_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0x20+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DESCR1_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DESCR1_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0x20+0x0C)++0x03
|
|
line.long 0x00 "DESCR1_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0x20+0x10)++0x07
|
|
line.long 0x00 "DESCR1_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR1_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0x20+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0x20+0x18)++0x03
|
|
line.long 0x00 "DESCR1_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x20+0x18)++0x03
|
|
line.long 0x00 "DESCR1_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR1_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x020000)
|
|
if (((per.l(ad:0x40101000+0x88))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x88))&0x40000000)==0x00000000)
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "DESCR2_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR2_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0x40+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DESCR2_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DESCR2_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0x40+0x0C)++0x03
|
|
line.long 0x00 "DESCR2_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0x40+0x10)++0x07
|
|
line.long 0x00 "DESCR2_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR2_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0x40+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "DESCR2_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x40+0x18)++0x03
|
|
line.long 0x00 "DESCR2_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR2_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x030000)
|
|
if (((per.l(ad:0x40101000+0x8C))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x8C))&0x40000000)==0x00000000)
|
|
group.long 0x60++0x07
|
|
line.long 0x00 "DESCR3_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR3_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0x60+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DESCR3_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DESCR3_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "DESCR3_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0x60+0x10)++0x07
|
|
line.long 0x00 "DESCR3_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR3_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0x60+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0x60+0x18)++0x03
|
|
line.long 0x00 "DESCR3_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x60+0x18)++0x03
|
|
line.long 0x00 "DESCR3_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR3_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x040000)
|
|
if (((per.l(ad:0x40101000+0x90))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x90))&0x40000000)==0x00000000)
|
|
group.long 0x80++0x07
|
|
line.long 0x00 "DESCR4_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR4_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0x80+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DESCR4_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DESCR4_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0x80+0x0C)++0x03
|
|
line.long 0x00 "DESCR4_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0x80+0x10)++0x07
|
|
line.long 0x00 "DESCR4_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR4_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0x80+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0x80+0x18)++0x03
|
|
line.long 0x00 "DESCR4_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0x80+0x18)++0x03
|
|
line.long 0x00 "DESCR4_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR4_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x050000)
|
|
if (((per.l(ad:0x40101000+0x94))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x94))&0x40000000)==0x00000000)
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "DESCR5_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR5_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0xA0+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "DESCR5_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "DESCR5_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0xA0+0x0C)++0x03
|
|
line.long 0x00 "DESCR5_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0xA0+0x10)++0x07
|
|
line.long 0x00 "DESCR5_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR5_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0xA0+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0xA0+0x18)++0x03
|
|
line.long 0x00 "DESCR5_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0xA0+0x18)++0x03
|
|
line.long 0x00 "DESCR5_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR5_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x060000)
|
|
if (((per.l(ad:0x40101000+0x98))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x98))&0x40000000)==0x00000000)
|
|
group.long 0xC0++0x07
|
|
line.long 0x00 "DESCR6_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR6_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0xC0+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "DESCR6_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "DESCR6_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0xC0+0x0C)++0x03
|
|
line.long 0x00 "DESCR6_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0xC0+0x10)++0x07
|
|
line.long 0x00 "DESCR6_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR6_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0xC0+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0xC0+0x18)++0x03
|
|
line.long 0x00 "DESCR6_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0xC0+0x18)++0x03
|
|
line.long 0x00 "DESCR6_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR6_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40101000+0x10))&0x070000)==0x070000)
|
|
if (((per.l(ad:0x40101000+0x9C))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40101000+0x9C))&0x40000000)==0x00000000)
|
|
group.long 0xE0++0x07
|
|
line.long 0x00 "DESCR7_PING_SRC,Ping Source Address"
|
|
line.long 0x04 "DESCR7_PING_DST,Ping Destination Address"
|
|
if (((per.l(ad:0x40101800+0xE0+0x0C))&0x80000000)==0x80000000)
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "DESCR7_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "DESCR7_PING_CTL,Ping Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long (0xE0+0x0C)++0x03
|
|
line.long 0x00 "DESCR7_PING_STATUS,Ping Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Specifies the index of the current data transfer"
|
|
else
|
|
group.long (0xE0+0x10)++0x07
|
|
line.long 0x00 "DESCR7_PONG_SRC,Pong Source Address"
|
|
line.long 0x04 "DESCR7_PONG_DST,Pong Destination Address"
|
|
if (((per.l(ad:0x40101800+0xE0+0x1C))&0x80000000)==0x80000000)
|
|
group.long (0xE0+0x18)++0x03
|
|
line.long 0x00 "DESCR7_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 30.--31. " OPCODE ,Specifies the specific data transfer" "Single data element,Single descriptor transfer,Descriptor list transfer,?..."
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,Word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
else
|
|
group.long (0xE0+0x18)++0x03
|
|
line.long 0x00 "DESCR7_PONG_CTL,Pong Control Word"
|
|
bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped"
|
|
bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " SET_CAUSE ,Set interrupt cause" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 26. " INV_DESCR ,Invalidate descriptor" "Not invalidated,Invalidated"
|
|
bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Specifies whether the data transfer engine should wait for the channel to be deactivated" "Do not wait,Wait 4 cycles,Wait 8 cycles,Wait indefinitely"
|
|
bitfld.long 0x00 23. " SRC_ADDR_INCR ,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Specifies the bus transfer size to the source location" "DATA_SIZE,32-bit word"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DST_ADDR_INCR ,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "No increment,Increment"
|
|
bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Specifies the bus transfer size to the destination location" "DATA_SIZE,32-bit word"
|
|
bitfld.long 0x00 16.--17. " DATA_SIZE ,Specifies the data element size" "Byte,Halfword,Word,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,16-bit number of data elements that are transferred by a single descriptor"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DESCR7_PONG_STATUS,Pong Status Word"
|
|
bitfld.long 0x00 31. " VALID ,Valid" "Invalid,Valid"
|
|
bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..."
|
|
hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,16-bit specifies the index of the current data transfer"
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "DSAB (Deep Sleep Amplifier Bias)"
|
|
base ad:0x403F0E00
|
|
width 21.
|
|
if (((per.l(ad:0x403F0E00))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "PASS_DSAB_DSAB_CTRL,Global DSAB Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled DSAB" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x00 28. " STARTUP_RM ,Risk mitigation control" "0,Force start"
|
|
bitfld.long 0x00 24. " BYPASS_MODE_EN ,Bypass mode enable" "DSAB,VDDA"
|
|
bitfld.long 0x00 16.--19. " REF_SWAP_EN ,This field provides bitwise selection of the current sources that drive the DSAB ZTC and PTAT outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " SEL_OUT ,Select output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--5. " CURRENT_SEL ,DSAB DAC control field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "PASS_DSAB_DSAB_DFT,DFT Bits"
|
|
bitfld.long 0x04 0.--3. " EN_DFT ,Enable DFT" "Disabled,Enabled,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PASS_DSAB_DSAB_CTRL,Global DSAB Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Enabled DSAB" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO (General Purpose Input/Output)"
|
|
base ad:0x40041000
|
|
width 17.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "INTR_CAUSE,Interrupt Port Cause Register"
|
|
sif cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x00 6. " PORT_INT[6] ,IO port interrupt 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " PORT_INT[5] ,IO port interrupt 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " PORT_INT[4] ,IO port interrupt 4" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " PORT_INT[3] ,IO port interrupt 3" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PORT_INT[2] ,IO port interrupt 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " PORT_INT[1] ,IO port interrupt 1" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " PORT_INT[0] ,IO port interrupt 0" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 0.--5. " PORT_INT ,Each IO port has an associated bit field in this register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
width 0x0B
|
|
tree.open "Port Specific"
|
|
tree "PRT0"
|
|
base ad:0x40040000
|
|
width 10.
|
|
sif (cpu()=="CY8C4A24PVI-431"||cpu()=="CY8C4A24PVI-441"||cpu()=="CY8C4A25PVI-471"||cpu()=="CY8C4A25PVI-481"||cpu()=="CY8C4A45PVI-471"||cpu()=="CY8C4A45PVI-481")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
elif (cpu()=="CY8C4A24LQI-443"||cpu()=="CY8C4A25LQI-473"||cpu()=="CY8C4A25LQI-483"||cpu()=="CY8C4A45LQI-473"||cpu()=="CY8C4A45LQI-483"||cpu()=="CY8C4A24AZI-433"||cpu()=="CY8C4A24AZI-443"||cpu()=="CY8C4A25AZI-473"||cpu()=="CY8C4A25AZI-483"||cpu()=="CY8C4A45AZI-473"||cpu()=="CY8C4A45AZI-483"||cpu()=="CY8C4A24FNI-443"||cpu()=="CY8C4A25FNI-473"||cpu()=="CY8C4A25FNI-483"||cpu()=="CY8C4A45FNI-473"||cpu()=="CY8C4A45FNI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRT1"
|
|
base ad:0x40040100
|
|
width 10.
|
|
sif (cpu()=="CY8C4A24PVI-431"||cpu()=="CY8C4A24PVI-441"||cpu()=="CY8C4A25PVI-471"||cpu()=="CY8C4A25PVI-481"||cpu()=="CY8C4A45PVI-471"||cpu()=="CY8C4A45PVI-481")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
elif (cpu()=="CY8C4A24LQI-443"||cpu()=="CY8C4A25LQI-473"||cpu()=="CY8C4A25LQI-483"||cpu()=="CY8C4A45LQI-473"||cpu()=="CY8C4A45LQI-483"||cpu()=="CY8C4A24AZI-433"||cpu()=="CY8C4A24AZI-443"||cpu()=="CY8C4A25AZI-473"||cpu()=="CY8C4A25AZI-483"||cpu()=="CY8C4A45AZI-473"||cpu()=="CY8C4A45AZI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
elif (cpu()=="CY8C4A24FNI-443"||cpu()=="CY8C4A25FNI-473"||cpu()=="CY8C4A25FNI-483"||cpu()=="CY8C4A45FNI-473"||cpu()=="CY8C4A45FNI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRT2"
|
|
base ad:0x40040200
|
|
width 10.
|
|
sif (cpu()=="CY8C4A24PVI-431"||cpu()=="CY8C4A24PVI-441"||cpu()=="CY8C4A25PVI-471"||cpu()=="CY8C4A25PVI-481"||cpu()=="CY8C4A45PVI-471"||cpu()=="CY8C4A45PVI-481")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
elif (cpu()=="CY8C4A24LQI-443"||cpu()=="CY8C4A25LQI-473"||cpu()=="CY8C4A25LQI-483"||cpu()=="CY8C4A45LQI-473"||cpu()=="CY8C4A45LQI-483"||cpu()=="CY8C4A24AZI-433"||cpu()=="CY8C4A24AZI-443"||cpu()=="CY8C4A25AZI-473"||cpu()=="CY8C4A25AZI-483"||cpu()=="CY8C4A45AZI-473"||cpu()=="CY8C4A45AZI-483"||cpu()=="CY8C4A24FNI-443"||cpu()=="CY8C4A25FNI-473"||cpu()=="CY8C4A25FNI-483"||cpu()=="CY8C4A45FNI-473"||cpu()=="CY8C4A45FNI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRT3"
|
|
base ad:0x40040300
|
|
width 10.
|
|
sif (cpu()=="CY8C4A24PVI-431"||cpu()=="CY8C4A24PVI-441"||cpu()=="CY8C4A25PVI-471"||cpu()=="CY8C4A25PVI-481"||cpu()=="CY8C4A45PVI-471"||cpu()=="CY8C4A45PVI-481")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" ",1,2,3,,,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
elif (cpu()=="CY8C4A24LQI-443"||cpu()=="CY8C4A25LQI-473"||cpu()=="CY8C4A25LQI-483"||cpu()=="CY8C4A45LQI-473"||cpu()=="CY8C4A45LQI-483"||cpu()=="CY8C4A24AZI-433"||cpu()=="CY8C4A24AZI-443"||cpu()=="CY8C4A25AZI-473"||cpu()=="CY8C4A25AZI-483"||cpu()=="CY8C4A45AZI-473"||cpu()=="CY8C4A45AZI-483"||cpu()=="CY8C4A24FNI-443"||cpu()=="CY8C4A25FNI-473"||cpu()=="CY8C4A25FNI-483"||cpu()=="CY8C4A45FNI-473"||cpu()=="CY8C4A45FNI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 7. " DATA7 ,IO pad 7 output data" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,IO pad 6 output data" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,IO pad 5 output data" "Low,High"
|
|
bitfld.long 0x00 4. " DATA4 ,IO pad 4 output data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High"
|
|
bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High"
|
|
bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 21.--23. " DM7 ,The GPIO drive mode for IO pad 7" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " DM6 ,The GPIO drive mode for IO pad 6" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 15.--17. " DM5 ,The GPIO drive mode for IO pad 5" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 12.--14. " DM4 ,The GPIO drive mode for IO pad 4" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 14.--15. " EDGE7_SEL ,Sets which edge will trigger an IRQ for IO pad 7" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 12.--13. " EDGE6_SEL ,Sets which edge will trigger an IRQ for IO pad 6" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EDGE5_SEL ,Sets which edge will trigger an IRQ for IO pad 5" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 8.--9. " EDGE4_SEL ,Sets which edge will trigger an IRQ for IO pad 4" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 23. " PS_DATA7 ,Interrupt status for port data 7" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 22. " PS_DATA6 ,Interrupt status for port data 6" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 21. " PS_DATA5 ,Interrupt status for port data 5" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 20. " PS_DATA4 ,Interrupt status for port data 4" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 7. " DATA7 ,Interrupt pending on IO pad 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 6. " DATA6 ,Interrupt pending on IO pad 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " DATA5 ,Interrupt pending on IO pad 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 4. " DATA4 ,Interrupt pending on IO pad 4" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 7. " INP_DIS7 ,Disables the input buffer for IO pad 7" "No,Yes"
|
|
bitfld.long 0x00 6. " INP_DIS6 ,Disables the input buffer for IO pad 6" "No,Yes"
|
|
bitfld.long 0x00 5. " INP_DIS5 ,Disables the input buffer for IO pad 5" "No,Yes"
|
|
bitfld.long 0x00 4. " INP_DIS4 ,Disables the input buffer for IO pad 4" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpu()!="CY8C4A24PVI-431"&&cpu()!="CY8C4A24PVI-441"&&cpu()!="CY8C4A25PVI-471"&&cpu()!="CY8C4A25PVI-481"&&cpu()!="CY8C4A45PVI-471"&&cpu()!="CY8C4A45PVI-481")
|
|
tree "PRT4"
|
|
base ad:0x40040400
|
|
width 10.
|
|
sif (cpu()=="CY8C4A24LQI-443"||cpu()=="CY8C4A25LQI-473"||cpu()=="CY8C4A25LQI-483"||cpu()=="CY8C4A45LQI-473"||cpu()=="CY8C4A45LQI-483"||cpu()=="CY8C4A24AZI-433"||cpu()=="CY8C4A24AZI-443"||cpu()=="CY8C4A25AZI-473"||cpu()=="CY8C4A25AZI-483"||cpu()=="CY8C4A45AZI-473"||cpu()=="CY8C4A45AZI-483"||cpu()=="CY8C4A24FNI-443"||cpu()=="CY8C4A25FNI-473"||cpu()=="CY8C4A25FNI-483"||cpu()=="CY8C4A45FNI-473"||cpu()=="CY8C4A45FNI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,This bit should always be 0" "0,?..."
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "PRT5"
|
|
base ad:0x40040500
|
|
width 10.
|
|
sif (cpu()=="CY8C4A24PVI-431"||cpu()=="CY8C4A24PVI-441"||cpu()=="CY8C4A25PVI-471"||cpu()=="CY8C4A25PVI-481"||cpu()=="CY8C4A45PVI-471"||cpu()=="CY8C4A45PVI-481")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,,2,3,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
elif (cpu()=="CY8C4A24LQI-443"||cpu()=="CY8C4A25LQI-473"||cpu()=="CY8C4A25LQI-483"||cpu()=="CY8C4A45LQI-473"||cpu()=="CY8C4A45LQI-483"||cpu()=="CY8C4A24AZI-433"||cpu()=="CY8C4A24AZI-443"||cpu()=="CY8C4A25AZI-473"||cpu()=="CY8C4A25AZI-483"||cpu()=="CY8C4A45AZI-473"||cpu()=="CY8C4A45AZI-483"||cpu()=="CY8C4A24FNI-443"||cpu()=="CY8C4A25FNI-473"||cpu()=="CY8C4A25FNI-483"||cpu()=="CY8C4A45FNI-473"||cpu()=="CY8C4A45FNI-483")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 3. " DATA3 ,IO pad 3 output data" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,IO pad 2 output data" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High"
|
|
bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,This bit should always be 0" "0,?..."
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 9.--11. " DM3 ,The GPIO drive mode for IO pad 3" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " DM2 ,The GPIO drive mode for IO pad 2" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,?..."
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 6.--7. " EDGE3_SEL ,Sets which edge will trigger an IRQ for IO pad 3" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 4.--5. " EDGE2_SEL ,Sets which edge will trigger an IRQ for IO pad 2" "Disable,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 19. " PS_DATA3 ,Interrupt status for port data 3" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 18. " PS_DATA2 ,Interrupt status for port data 2" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 3. " DATA3 ,Interrupt pending on IO pad 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 2. " DATA2 ,Interrupt pending on IO pad 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 3. " INP_DIS3 ,Disables the input buffer for IO pad 3" "No,Yes"
|
|
bitfld.long 0x00 2. " INP_DIS2 ,Disables the input buffer for IO pad 2" "No,Yes"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DR,Port Output Data Register"
|
|
bitfld.long 0x00 1. " DATA1 ,IO pad 1 output data" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,IO pad 0 output data" "Low,High"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PS,Port IO Pad State Register"
|
|
bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High"
|
|
bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High"
|
|
bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "PC,Port Configuration Register"
|
|
bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Input buffer reference" "CMOS,Vcchib,OVT,Reference"
|
|
bitfld.long 0x00 25. " PORT_SLOW ,This field controls the output edge rate of all pins on the port" "Fast,Slow"
|
|
bitfld.long 0x00 24. " PORT_VTRIP_SEL ,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage" "CMOS,LVTTL"
|
|
bitfld.long 0x00 3.--5. " DM1 ,The GPIO drive mode for IO pad 1" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " DM0 ,The GPIO drive mode for IO pad 0" "OFF,INPUT,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU"
|
|
line.long 0x04 "INTR_CFG,Port Interrupt Configuration Register"
|
|
bitfld.long 0x04 18.--20. " FLT_SEL ,Selects which pin is routed through the 50ns glitch filter to provide a Glitch-safe interrupt" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 16.--17. " FLT_EDGE_SEL ,Sets which edge will trigger an IRQ for glitch filtered pin" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 2.--3. " EDGE1_SEL ,Sets which edge will trigger an IRQ for IO pad 1" "Disable,Rising,Falling,Both"
|
|
bitfld.long 0x04 0.--1. " EDGE0_SEL ,Sets which edge will trigger an IRQ for IO pad 0" "Disable,Rising,Falling,Both"
|
|
line.long 0x08 "INTR,Port Interrupt Status Register"
|
|
rbitfld.long 0x08 24. " PS_FLT_DATA ,Interrupt status for port data FLT " "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 17. " PS_DATA1 ,Interrupt status for port data 1" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 16. " PS_DATA0 ,Interrupt status for port data 0" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 8. " FLT_DATA ,Deglitched interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 1. " DATA1 ,Interrupt pending on IO pad 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 0. " DATA0 ,Interrupt pending on IO pad 0" "No interrupt,Interrupt"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PC2,Port Configuration Register 2"
|
|
bitfld.long 0x00 1. " INP_DIS1 ,Disables the input buffer for IO pad 1" "No,Yes"
|
|
bitfld.long 0x00 0. " INP_DIS0 ,Disables the input buffer for IO pad 0" "No,Yes"
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "DR_SET,Port Output Data Set Register"
|
|
bitfld.long 0x00 7. " DATA[7] ,IO pad 7" "Not set,Set"
|
|
bitfld.long 0x00 6. " DATA[6] ,IO pad 6" "Not set,Set"
|
|
bitfld.long 0x00 5. " DATA[5] ,IO pad 5" "Not set,Set"
|
|
bitfld.long 0x00 4. " DATA[4] ,IO pad 4" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DATA[3] ,IO pad 3" "Not set,Set"
|
|
bitfld.long 0x00 2. " DATA[2] ,IO pad 2" "Not set,Set"
|
|
bitfld.long 0x00 1. " DATA[1] ,IO pad 1" "Not set,Set"
|
|
bitfld.long 0x00 0. " DATA[0] ,IO pad 0" "Not set,Set"
|
|
line.long 0x04 "DR_CLR,Port Output Data Clear Register"
|
|
bitfld.long 0x04 7. " DATA[7] ,IO pad 7" "No effect,Clear"
|
|
bitfld.long 0x04 6. " DATA[6] ,IO pad 6" "No effect,Clear"
|
|
bitfld.long 0x04 5. " DATA[5] ,IO pad 5" "No effect,Clear"
|
|
bitfld.long 0x04 4. " DATA[4] ,IO pad 4" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DATA[3] ,IO pad 3" "No effect,Clear"
|
|
bitfld.long 0x04 2. " DATA[2] ,IO pad 2" "No effect,Clear"
|
|
bitfld.long 0x04 1. " DATA[1] ,IO pad 1" "No effect,Clear"
|
|
bitfld.long 0x04 0. " DATA[0] ,IO pad 0" "No effect,Clear"
|
|
line.long 0x08 "DR_INV,Port Output Data Invert Register"
|
|
bitfld.long 0x08 7. " DATA[7] ,IO pad 7" "No effect,Inverted"
|
|
bitfld.long 0x08 6. " DATA[6] ,IO pad 6" "No effect,Inverted"
|
|
bitfld.long 0x08 5. " DATA[5] ,IO pad 5" "No effect,Inverted"
|
|
bitfld.long 0x08 4. " DATA[4] ,IO pad 4" "No effect,Inverted"
|
|
textline " "
|
|
bitfld.long 0x08 3. " DATA[3] ,IO pad 3" "No effect,Inverted"
|
|
bitfld.long 0x08 2. " DATA[2] ,IO pad 2" "No effect,Inverted"
|
|
bitfld.long 0x08 1. " DATA[1] ,IO pad 1" "No effect,Inverted"
|
|
bitfld.long 0x08 0. " DATA[0] ,IO pad 0" "No effect,Inverted"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "HSIOM (High Speed IO Matrix)"
|
|
base ad:0x40022100
|
|
width 17.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "AMUX_SPLIT_CTL0,AMUX Splitter Cell Control"
|
|
bitfld.long 0x00 6. " SWITCH_BB_S0 ,T-switch control for AMUXBUSB vssa/ground switch" "Open,Closed"
|
|
bitfld.long 0x00 5. " SWITCH_BB_SR ,T-switch control for right AMUXBUSB switch" "Open,Closed"
|
|
bitfld.long 0x00 4. " SWITCH_BB_SL ,T-switch control for left AMUXBUSB switch" "Open,Closed"
|
|
bitfld.long 0x00 2. " SWITCH_AA_S0 ,T-switch control for AMUXBUSA vssa/ground switch" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWITCH_AA_SR ,T-switch control for right AMUXBUSA switch" "Open,Closed"
|
|
bitfld.long 0x00 0. " SWITCH_AA_SL ,T-switch control for left AMUXBUSA switch" "Open,Closed"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "AMUX_SPLIT_CTL1,AMUX Splitter Cell Control"
|
|
bitfld.long 0x00 6. " SWITCH_BB_S0 ,T-switch control for AMUXBUSB vssa/ground switch" "Open,Closed"
|
|
bitfld.long 0x00 5. " SWITCH_BB_SR ,T-switch control for right AMUXBUSB switch" "Open,Closed"
|
|
bitfld.long 0x00 4. " SWITCH_BB_SL ,T-switch control for left AMUXBUSB switch" "Open,Closed"
|
|
bitfld.long 0x00 2. " SWITCH_AA_S0 ,T-switch control for AMUXBUSA vssa/ground switch" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWITCH_AA_SR ,T-switch control for right AMUXBUSA switch" "Open,Closed"
|
|
bitfld.long 0x00 0. " SWITCH_AA_SL ,T-switch control for left AMUXBUSA switch" "Open,Closed"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "AMUX_SPLIT_CTL2,AMUX Splitter Cell Control"
|
|
bitfld.long 0x00 6. " SWITCH_BB_S0 ,T-switch control for AMUXBUSB vssa/ground switch" "Open,Closed"
|
|
bitfld.long 0x00 5. " SWITCH_BB_SR ,T-switch control for right AMUXBUSB switch" "Open,Closed"
|
|
bitfld.long 0x00 4. " SWITCH_BB_SL ,T-switch control for left AMUXBUSB switch" "Open,Closed"
|
|
bitfld.long 0x00 2. " SWITCH_AA_S0 ,T-switch control for AMUXBUSA vssa/ground switch" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SWITCH_AA_SR ,T-switch control for right AMUXBUSA switch" "Open,Closed"
|
|
bitfld.long 0x00 0. " SWITCH_AA_SL ,T-switch control for left AMUXBUSA switch" "Open,Closed"
|
|
width 0x0B
|
|
tree "Port Specific"
|
|
base ad:0x40020000
|
|
width 17.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "PORT_SEL0,Port Selection Register"
|
|
bitfld.long 0x00 28.--31. " IO7_SEL ,Selects connection for IO pad 7 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 24.--27. " IO6_SEL ,Selects connection for IO pad 6 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 20.--23. " IO5_SEL ,Selects connection for IO pad 5 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 16.--19. " IO4_SEL ,Selects connection for IO pad 4 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " IO3_SEL ,Selects connection for IO pad 3 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 8.--11. " IO2_SEL ,Selects connection for IO pad 2 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 4.--7. " IO1_SEL ,Selects connection for IO pad 1 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 0.--3. " IO0_SEL ,Selects connection for IO pad 0 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PORT_SEL1,Port Selection Register"
|
|
bitfld.long 0x00 28.--31. " IO7_SEL ,Selects connection for IO pad 7 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 24.--27. " IO6_SEL ,Selects connection for IO pad 6 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 20.--23. " IO5_SEL ,Selects connection for IO pad 5 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 16.--19. " IO4_SEL ,Selects connection for IO pad 4 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " IO3_SEL ,Selects connection for IO pad 3 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 8.--11. " IO2_SEL ,Selects connection for IO pad 2 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 4.--7. " IO1_SEL ,Selects connection for IO pad 1 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 0.--3. " IO0_SEL ,Selects connection for IO pad 0 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PORT_SEL2,Port Selection Register"
|
|
bitfld.long 0x00 28.--31. " IO7_SEL ,Selects connection for IO pad 7 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 24.--27. " IO6_SEL ,Selects connection for IO pad 6 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 20.--23. " IO5_SEL ,Selects connection for IO pad 5 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 16.--19. " IO4_SEL ,Selects connection for IO pad 4 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " IO3_SEL ,Selects connection for IO pad 3 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 8.--11. " IO2_SEL ,Selects connection for IO pad 2 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 4.--7. " IO1_SEL ,Selects connection for IO pad 1 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 0.--3. " IO0_SEL ,Selects connection for IO pad 0 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "PORT_SEL3,Port Selection Register"
|
|
bitfld.long 0x00 28.--31. " IO7_SEL ,Selects connection for IO pad 7 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 24.--27. " IO6_SEL ,Selects connection for IO pad 6 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 20.--23. " IO5_SEL ,Selects connection for IO pad 5 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 16.--19. " IO4_SEL ,Selects connection for IO pad 4 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " IO3_SEL ,Selects connection for IO pad 3 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 8.--11. " IO2_SEL ,Selects connection for IO pad 2 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 4.--7. " IO1_SEL ,Selects connection for IO pad 1 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 0.--3. " IO0_SEL ,Selects connection for IO pad 0 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "PORT_SEL4,Port Selection Register"
|
|
bitfld.long 0x00 4.--7. " IO1_SEL ,Selects connection for IO pad 1 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM,DS_0,DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 0.--3. " IO0_SEL ,Selects connection for IO pad 0 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM,DS_0,DS_1,DS_2,DS_3"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "PORT_SEL5,Port Selection Register"
|
|
bitfld.long 0x00 12.--15. " IO3_SEL ,Selects connection for IO pad 3 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 8.--11. " IO2_SEL ,Selects connection for IO pad 2 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 4.--7. " IO1_SEL ,Selects connection for IO pad 1 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
bitfld.long 0x00 0.--3. " IO0_SEL ,Selects connection for IO pad 0 route" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,ACT_3,LCD_COM/DS_0,LCD_SEG/DS_1,DS_2,DS_3"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
sif (cpu()!="CY8C4A24PVI-431"&&cpu()!="CY8C4A24AZI-433"&&cpu()!="CY8C4A25PVI-471"&&cpu()!="CY8C4A25FNI-473"&&cpu()!="CY8C4A25LQI-473"&&cpu()!="CY8C4A25AZI-473"&&cpu()!="CY8C4A45PVI-471"&&cpu()!="CY8C4A45FNI-473"&&cpu()!="CY8C4A45LQI-473"&&cpu()!="CY8C4A45AZI-473")
|
|
tree "LCD"
|
|
base ad:0x400B0000
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ID,ID & Revision"
|
|
hexmask.long.word 0x00 16.--31. 1. " REVISION ,Version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " ID ,ID of LCD controller peripheral"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DIVIDER,LCD Divider Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " DEAD_DIV ,Length of the dead time period in cycles"
|
|
hexmask.long.word 0x00 0.--15. 1. " SUBFR_DIV ,Input clock frequency divide value"
|
|
if (((per.l(ad:0x400B0000+0x08))&0x4)==0x0)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONTROL,LCD Configuration Register"
|
|
rbitfld.long 0x00 31. " LS_EN_STAT ,LS enable status bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " COM_NUM ,The number of COM connections minus 2" "2 COM's,3 COM's,4 COM's,5 COM's,6 COM's,7 COM's,8 COM's,9 COM's,10 COM's,11 COM's,12 COM's,13 COM's,14 COM's,15 COM's,16 COM's,?..."
|
|
bitfld.long 0x00 5.--6. " BIAS ,PWM bias selection" "HALF,THIRD,FOURTH,FIFTH"
|
|
bitfld.long 0x00 4. " OP_MODE ,Driving mode configuration" "PWM,CORRELATION"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TYPE ,LCD driving waveform type configuration" "TYPE_A,TYPE_B"
|
|
bitfld.long 0x00 2. " LCD_MODE ,HS/LS mode selection" "LS,HS"
|
|
bitfld.long 0x00 0. " LS_EN ,Low speed generator enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CONTROL,LCD Configuration Register"
|
|
rbitfld.long 0x00 31. " LS_EN_STAT ,LS enable status bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " COM_NUM ,The number of COM connections minus 2" "2 COM's,3 COM's,4 COM's,5 COM's,6 COM's,7 COM's,8 COM's,9 COM's,10 COM's,11 COM's,12 COM's,13 COM's,14 COM's,15 COM's,16 COM's,?..."
|
|
bitfld.long 0x00 5.--6. " BIAS ,PWM bias selection" "HALF,THIRD,FOURTH,FIFTH"
|
|
bitfld.long 0x00 4. " OP_MODE ,Driving mode configuration" "PWM,CORRELATION"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TYPE ,LCD driving waveform type configuration" "TYPE_A,TYPE_B"
|
|
bitfld.long 0x00 2. " LCD_MODE ,HS/LS mode selection" "LS,HS"
|
|
bitfld.long 0x00 1. " HS_EN ,High speed generator enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DATA0,LCD Pin Data Register"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DATA1,LCD Pin Data Register"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DATA2,LCD Pin Data Register"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DATA3,LCD Pin Data Register"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DATA4,LCD Pin Data Register"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DATA5,LCD Pin Data Register"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DATA6,LCD Pin Data Register"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DATA7,LCD Pin Data Register"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DATA00,LCD Pin Data Registers"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "DATA01,LCD Pin Data Registers"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "DATA02,LCD Pin Data Registers"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "DATA03,LCD Pin Data Registers"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DATA04,LCD Pin Data Registers"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "DATA05,LCD Pin Data Registers"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "DATA06,LCD Pin Data Registers"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "DATA07,LCD Pin Data Registers"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "DATA08,LCD Pin Data Registers"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "DATA09,LCD Pin Data Registers"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "DATA10,LCD Pin Data Registers"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "DATA11,LCD Pin Data Registers"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "DATA12,LCD Pin Data Registers"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "DATA13,LCD Pin Data Registers"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "DATA14,LCD Pin Data Registers"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "DATA15,LCD Pin Data Registers"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "DATA16,LCD Pin Data Registers"
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "DATA17,LCD Pin Data Registers"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "LPCOMP (Low Power Comparator)"
|
|
base ad:0x400E0000
|
|
width 20.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ID,ID & Revision"
|
|
hexmask.long.word 0x00 16.--31. 1. " REVISION ,Version number"
|
|
hexmask.long.word 0x00 0.--15. 1. " ID ,ID of LPCOMP peripheral"
|
|
if ((((per.l(ad:0x400E0000+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x400E0000+0x04))&0x80)==0x80))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CONFIG,LPCOMP Configuration Register"
|
|
bitfld.long 0x00 21. " DSI_LEVEL2 ,Opamp2 comperator DSI out level" "Pulse,Level"
|
|
bitfld.long 0x00 20. " DSI_BYPASS2 ,Opamp2 bypass comparator output synchronization for DSI output" "Synchronize,Bypass"
|
|
bitfld.long 0x00 16. " DSI_LEVEL1 ,Opamp1 comparator DSI out level" "Pulse,Level"
|
|
bitfld.long 0x00 15. " DSI_BYPASS1 ,Opamp1 bypass comparator output synchronization for DSI output" "Synchronize,Bypass"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ENABLE2 ,Enable comparator 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " OUT2 ,Current output value of the comparator 1" "Low,High"
|
|
bitfld.long 0x00 12.--13. " INTTYPE2 ,Sets which edge in the comparator 1 output triggers an interrupt" "DISABLE,RISING,FALLING,BOTH"
|
|
bitfld.long 0x00 10. " HYST2 ,10mV hysteresis for comparator 1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Sets the operating mode for comparator 1" "SLOW,FAST,ULP,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE1 ,Enable comparator 0" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " OUT1 ,Current output value of the comparator 0" "Low,High"
|
|
bitfld.long 0x00 4.--5. " INTTYPE1 ,Sets which edge in the comparator 0 output triggers an interrupt" "DISABLE,RISING,FALLING,BOTH"
|
|
bitfld.long 0x00 2. " HYST1 ,10mV hysteresis for comparator 0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE1 ,Sets the operating mode for comparator 0" "SLOW,FAST,ULP,?..."
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "INTR,LPCOMP Interrupt Request Register"
|
|
eventfld.long 0x00 1. " COMP2 ,Comparator 1 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " COMP1 ,Comparator 0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,LPCOMP Interrupt Set Register"
|
|
bitfld.long 0x04 1. " COMP2 ,Set COMP2 bit in the interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " COMP1 ,Set COMP1 bit in the interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,LPCOMP Interrupt Request Mask"
|
|
bitfld.long 0x08 1. " COMP2_MASK ,Interrupt mask bit for comparator 1" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " COMP1_MASK ,Interrupt mask bit for comparator 0" "Not masked,Masked"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "INTR_MASKED,LPCOMP Interrupt Request Masked"
|
|
bitfld.long 0x00 1. " COMP2_MASKED ,Logical AND of the comparator 1 interrupt request register bit and the interrupt mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " COMP1_MASKED ,Logical AND of the comparator 0 interrupt request register bit and the interrupt mask bit" "Not masked,Masked"
|
|
group.long 0xFF00++0x0F
|
|
line.long 0x00 "TRIM1,LPCOMP Trim Register"
|
|
bitfld.long 0x00 0.--4. " COMP1_TRIMA ,Trim A for comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TRIM2,LPCOMP Trim Register"
|
|
bitfld.long 0x04 0.--4. " COMP1_TRIMB ,Trim B for comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "TRIM3,LPCOMP Trim Register"
|
|
bitfld.long 0x08 0.--4. " COMP2_TRIMA ,Trim A for comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x0C "TRIM4,LPCOMP Trim Register"
|
|
bitfld.long 0x0C 0.--4. " COMP2_TRIMB ,Trim B for comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif ((((per.l(ad:0x400E0000+0x04))&0x8000)==0x8000)&&(((per.l(ad:0x400E0000+0x04))&0x80)==0x00))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CONFIG,LPCOMP Configuration Register"
|
|
bitfld.long 0x00 21. " DSI_LEVEL2 ,Opamp2 comperator DSI out level" "Pulse,Level"
|
|
bitfld.long 0x00 20. " DSI_BYPASS2 ,Opamp2 bypass comparator output synchronization for DSI output" "Synchronize,Bypass"
|
|
bitfld.long 0x00 16. " DSI_LEVEL1 ,Opamp1 comparator DSI out level" "Pulse,Level"
|
|
bitfld.long 0x00 15. " DSI_BYPASS1 ,Opamp1 bypass comparator output synchronization for DSI output" "Synchronize,Bypass"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ENABLE2 ,Enable comparator 1" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " OUT2 ,Current output value of the comparator 1" "Low,High"
|
|
bitfld.long 0x00 12.--13. " INTTYPE2 ,Sets which edge in the comparator 1 output triggers an interrupt" "DISABLE,RISING,FALLING,BOTH"
|
|
bitfld.long 0x00 10. " HYST2 ,10mV hysteresis for comparator 1" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODE2 ,Sets the operating mode for comparator 1" "SLOW,FAST,ULP,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE1 ,Enable comparator 0" "Disabled,Enabled"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "INTR,LPCOMP Interrupt Request Register"
|
|
eventfld.long 0x00 1. " COMP2 ,Comparator 1 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,LPCOMP Interrupt Set Register"
|
|
bitfld.long 0x04 1. " COMP2 ,Set COMP2 bit in the interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,LPCOMP Interrupt Request Mask"
|
|
bitfld.long 0x08 1. " COMP2_MASK ,Interrupt mask bit for comparator 1" "Not masked,Masked"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "INTR_MASKED,LPCOMP Interrupt Request Masked"
|
|
bitfld.long 0x00 1. " COMP2_MASKED ,Logical AND of the comparator 1 interrupt request register bit and the interrupt mask bit" "Not masked,Masked"
|
|
group.long 0xFF08++0x07
|
|
line.long 0x00 "TRIM3,LPCOMP Trim Register"
|
|
bitfld.long 0x00 0.--4. " COMP2_TRIMA ,Trim A for comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TRIM4,LPCOMP Trim Register"
|
|
bitfld.long 0x04 0.--4. " COMP2_TRIMB ,Trim B for comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
elif ((((per.l(ad:0x400E0000+0x04))&0x8000)==0x0000)&&(((per.l(ad:0x400E0000+0x04))&0x80)==0x80))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CONFIG,LPCOMP Configuration Register"
|
|
bitfld.long 0x00 21. " DSI_LEVEL2 ,Opamp2 comperator DSI out level" "Pulse,Level"
|
|
bitfld.long 0x00 20. " DSI_BYPASS2 ,Opamp2 bypass comparator output synchronization for DSI output" "Synchronize,Bypass"
|
|
bitfld.long 0x00 16. " DSI_LEVEL1 ,Opamp1 comparator DSI out level" "Pulse,Level"
|
|
bitfld.long 0x00 15. " DSI_BYPASS1 ,Opamp1 bypass comparator output synchronization for DSI output" "Synchronize,Bypass"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ENABLE2 ,Enable comparator 1" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE1 ,Enable comparator 0" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " OUT1 ,Current output value of the comparator 0" "Low,High"
|
|
bitfld.long 0x00 4.--5. " INTTYPE1 ,Sets which edge in the comparator 0 output triggers an interrupt" "DISABLE,RISING,FALLING,BOTH"
|
|
bitfld.long 0x00 2. " HYST1 ,10mV hysteresis for comparator 0" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODE1 ,Sets the operating mode for comparator 0" "SLOW,FAST,ULP,?..."
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "INTR,LPCOMP Interrupt Request Register"
|
|
eventfld.long 0x00 0. " COMP1 ,Comparator 0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,LPCOMP Interrupt Set Register"
|
|
bitfld.long 0x04 0. " COMP1 ,Set COMP1 bit in the interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,LPCOMP Interrupt Request Mask"
|
|
bitfld.long 0x08 0. " COMP1_MASK ,Interrupt mask bit for comparator 0" "Not masked,Masked"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "INTR_MASKED,LPCOMP Interrupt Request Masked"
|
|
bitfld.long 0x00 0. " COMP1_MASKED ,Logical AND of the comparator 0 interrupt request register bit and the interrupt mask bit" "Not masked,Masked"
|
|
group.long 0xFF00++0x07
|
|
line.long 0x00 "TRIM1,LPCOMP Trim Register"
|
|
bitfld.long 0x00 0.--4. " COMP1_TRIMA ,Trim A for comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "TRIM2,LPCOMP Trim Register"
|
|
bitfld.long 0x04 0.--4. " COMP1_TRIMB ,Trim B for comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CONFIG,LPCOMP Configuration Register"
|
|
bitfld.long 0x00 15. " ENABLE2 ,Enable comparator 1" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE1 ,Enable comparator 0" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PASS MMIO (Programmable Analog Sub System Memory Mapped IO)"
|
|
base ad:0x403F0000
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "INTR_CAUSE,Interrupt Cause Register"
|
|
bitfld.long 0x00 8. " UAB0_INT ,UAB0 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " CTB1_INT ,CTB1 interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " CTB0_INT ,CTB0 interrupt pending" "Not pending,Pending"
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "TRIG_SYNC,Trigger Synchronization Bypass"
|
|
bitfld.long 0x00 8.--13. " DSI_SYNC0_EN ,Synchronize DSI input 1" "Bypass synchronization,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x04 "SAR_TRIG_SEL,Trigger Select For SAR"
|
|
bitfld.long 0x04 24.--28. " TRIG_SEL ,Trigger select" "UAB0 half 0 out,UAB0 half 1 out,UAB1 half 0 out,UAB1 half 1 out,UAB2 half 0 out,UAB2 half 1 out,UAB3 half 0 out,UAB3 half 1 out,Generic trigger input 0,Generic trigger input 1,Generic trigger input 2,Generic trigger input 3,Generic trigger input 4,Generic trigger input 5,Generic trigger input 6,Generic trigger input 7,Generic trigger input 8,Generic trigger input 9,Generic trigger input 10,Generic trigger input 11,Generic trigger input 12,Generic trigger input 13,Generic trigger input 14,Generic trigger input 15,Generic trigger input 16,Generic trigger input 17,Generic trigger input 18,Generic trigger input 19,Generic trigger input 20,Generic trigger input 21,Generic trigger input 22,SAR"
|
|
line.long 0x08 "PASS_CTRL,PASS Control"
|
|
hexmask.long.byte 0x08 8.--15. 1. " RMB_BITS ,8-bit risk mitigation bits"
|
|
bitfld.long 0x08 1. " PMPCLK_SRC ,PMPCLK source" "Clk_hf,Srss"
|
|
bitfld.long 0x08 0. " PMPCLK_BYP ,PMPCLK bypass" "Clk_hf/2,PMPCLK_SRC"
|
|
if (((per.l(ad:0x403F0000+0x200))&0x80000000)==0x80000000)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PRB_CTRL,Global PRB Control"
|
|
bitfld.long 0x00 31. " ENABLED ,PRB IP status" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DEEPSLEEP_ON ,ON DeepSleep status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VDDA_ENABLE ,VDDA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " VBGR_BUF_GAIN ,VBGR buffer gain" "OFF,1,2,?..."
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "PRB_REF0,VREF0 Control"
|
|
bitfld.long 0x00 4.--7. " VREF0_SEL ,Level select" "1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16,1"
|
|
bitfld.long 0x00 1. " VREF0_SUP_SEL ,Supply select" "VGBR*gain,VDDA"
|
|
bitfld.long 0x00 0. " VREF0_ENABLE ,Enable VREF0" "Disconnected,Connected"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "PRB_REF1,VREF1 Control"
|
|
bitfld.long 0x00 4.--7. " VREF1_SEL ,Level select" "1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16,1"
|
|
bitfld.long 0x00 1. " VREF1_SUP_SEL ,Supply select" "VGBR*gain,VDDA"
|
|
bitfld.long 0x00 0. " VREF1_ENABLE ,Enable VREF1" "Disconnected,Connected"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "PRB_REF2,VREF2 Control"
|
|
bitfld.long 0x00 4.--7. " VREF2_SEL ,Level select" "1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16,1"
|
|
bitfld.long 0x00 1. " VREF2_SUP_SEL ,Supply select" "VGBR*gain,VDDA"
|
|
bitfld.long 0x00 0. " VREF2_ENABLE ,Enable VREF2" "Disconnected,Connected"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "PRB_REF3,VREF3 Control"
|
|
bitfld.long 0x00 4.--7. " VREF3_SEL ,Level select" "1/16,2/16,3/16,4/16,5/16,6/16,7/16,8/16,9/16,10/16,11/16,12/16,13/16,14/16,15/16,1"
|
|
bitfld.long 0x00 1. " VREF3_SUP_SEL ,Supply select" "VGBR*gain,VDDA"
|
|
bitfld.long 0x00 0. " VREF3_ENABLE ,Enable VREF3" "Disconnected,Connected"
|
|
else
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "PRB_CTRL,Global PRB Control"
|
|
bitfld.long 0x00 31. " ENABLED ,PRB IP status" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x403F0000+0x300))&0x80000000)==0x80000000)
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "LNFE_CTRL,Global LNFE Control"
|
|
bitfld.long 0x00 31. " ENABLED ,LNFE IP enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DEEPSLEEP_ON ,ON DeepSleep status" "Disabled,Enabled"
|
|
line.long 0x04 "LNFE_SW,LNFE Switch Control"
|
|
bitfld.long 0x04 1. " LE ,Connect NPN emitter to pin" "Not connected,Connected"
|
|
bitfld.long 0x04 0. " LB ,Connect NPN base to pin" "Not connected,Connected"
|
|
else
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "LNFE_CTRL,Global LNFE Control"
|
|
bitfld.long 0x00 31. " ENABLED ,LNFE IP enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0xF00++0x07
|
|
line.long 0x00 "DSAB_TRIM,DSAB Trim Bits"
|
|
bitfld.long 0x00 4.--5. " DSAB_RMB_BITS ,Risk mitigation bits" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. " IDIAS_TRIM ,IDIAS trim bits" "1111,1110,1101,1100,1011,1010,1001,1000,0111,0110,0101,0100,0011,0010,0001,0000"
|
|
line.long 0x04 "PRB_TRIM,PRB Trim Bits"
|
|
bitfld.long 0x04 8.--9. " PRB_RMB_BITS ,Risk mitigation bits" "0,1,2,3"
|
|
bitfld.long 0x04 0.--5. " VBGR_BUF_TRIM ,6 bits signed value [-32..31] ~1mV per step" "-32,-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "PERI (Clock Dividers and Peripheral Interconnect)"
|
|
base ad:0x40000000
|
|
width 20.
|
|
if (((per.l(ad:0x40000000))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40000000))&0x40000000)==0x40000000)
|
|
hgroup.long 0x00++0x03
|
|
hide.long 0x00 "DIV_CMD,Divider Command Register"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DIV_CMD,Divider Command Register"
|
|
bitfld.long 0x00 31. " ENABLE ,Clock divider enable command" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PA_SEL_TYPE ,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command" "8.0,16.0,16.5,25.5"
|
|
bitfld.long 0x00 8.--13. " PA_SEL_DIV ,Specifies the divider to which phase alignment is performed for the clock enable command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies the divider type of the divider on which the command is performed" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--5. " SEL_DIV ,Specifies the divider on which the command is performed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40000000))&0x40000000)==0x40000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DIV_CMD,Divider Command Register"
|
|
bitfld.long 0x00 30. " DISABLE ,Clock divider disable command" "No,Yes"
|
|
bitfld.long 0x00 14.--15. " PA_SEL_TYPE ,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command" "8.0,16.0,16.5,25.5"
|
|
bitfld.long 0x00 8.--13. " PA_SEL_DIV ,Specifies the divider to which phase alignment is performed for the clock enable command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies the divider type of the divider on which the command is performed" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--5. " SEL_DIV ,Specifies the divider on which the command is performed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DIV_CMD,Divider Command Register"
|
|
bitfld.long 0x00 31. " ENABLE ,Clock divider enable command" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DISABLE ,Clock divider disable command" "No,Yes"
|
|
bitfld.long 0x00 14.--15. " PA_SEL_TYPE ,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command" "8.0,16.0,16.5,25.5"
|
|
bitfld.long 0x00 8.--13. " PA_SEL_DIV ,Specifies the divider to which phase alignment is performed for the clock enable command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies the divider type of the divider on which the command is performed" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--5. " SEL_DIV ,Specifies the divider on which the command is performed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
endif
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PCLK_CTL0,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "PCLK_CTL1,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "PCLK_CTL2,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "PCLK_CTL3,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PCLK_CTL4,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "PCLK_CTL5,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PCLK_CTL6,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PCLK_CTL7,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PCLK_CTL8,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PCLK_CTL9,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "PCLK_CTL10,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "PCLK_CTL11,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PCLK_CTL12,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "PCLK_CTL13,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "PCLK_CTL14,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "PCLK_CTL15,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--3. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "DIV_16_CTL0,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DIV_16_CTL1,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "DIV_16_CTL2,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "DIV_16_CTL3,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "DIV_16_CTL4,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DIV_16_CTL5,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "DIV_16_CTL6,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "DIV_16_CTL7,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "DIV_16_CTL8,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x324++0x03
|
|
line.long 0x00 "DIV_16_CTL9,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "DIV_16_5_CTL0,Divider Control Register For 16.5 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by FRAC5_DIV/32" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
rbitfld.long 0x00 0. " EN ,Divider enable" "Disabled,Enabled"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "DIV_16_5_CTL1,Divider Control Register For 16.5 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by FRAC5_DIV/32" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
rbitfld.long 0x00 0. " EN ,Divider enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PCLK_CTL0,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "PCLK_CTL1,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "PCLK_CTL2,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "PCLK_CTL3,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "PCLK_CTL4,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "PCLK_CTL5,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "PCLK_CTL6,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "PCLK_CTL7,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "PCLK_CTL8,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PCLK_CTL9,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "PCLK_CTL10,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "PCLK_CTL11,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PCLK_CTL12,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "PCLK_CTL13,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "PCLK_CTL14,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "PCLK_CTL15,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "PCLK_CTL16,Programmable Clock Control Register"
|
|
bitfld.long 0x00 6.--7. " SEL_TYPE ,Specifies divider type" "8.0,16.0,16.5,24.5"
|
|
bitfld.long 0x00 0.--2. " SEL_DIV ,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "DIV_16_CTL0,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "DIV_16_CTL1,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "DIV_16_CTL2,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "DIV_16_CTL3,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "DIV_16_CTL4,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "DIV_16_CTL5,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "DIV_16_CTL6,Divider Control Register For 16.0 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "DIV_16_5_CTL0,Divider Control Register For 16.5 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by FRAC5_DIV/32" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
bitfld.long 0x00 0. " EN ,Divider enable" "Disabled,Enabled"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "DIV_16_5_CTL1,Divider Control Register For 16.5 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by FRAC5_DIV/32" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
bitfld.long 0x00 0. " EN ,Divider enable" "Disabled,Enabled"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "DIV_16_5_CTL2,Divider Control Register For 16.5 Divider"
|
|
hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,16-bit integer division by 1+INT16_DIV"
|
|
bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by FRAC5_DIV/32" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
bitfld.long 0x00 0. " EN ,Divider enable" "Disabled,Enabled"
|
|
group.long 0x500++0x03
|
|
line.long 0x00 "DIV_24_5_CTL,Divider Control Register For 24.5 Divider"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " INT24_DIV ,23-bit integer division by 1+INT24_DIV"
|
|
bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by FRAC5_DIV/32" "0/32,1/32,2/32,3/32,4/32,5/32,6/32,7/32,8/32,9/32,10/32,11/32,12/32,13/32,14/32,15/32,16/32,17/32,18/32,19/32,20/32,21/32,22/32,23/32,24/32,25/32,26/32,27/32,28/32,29/32,30/32,31/32"
|
|
rbitfld.long 0x00 0. " EN ,Divider enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40000000+0x600))&0x80000000)==0x80000000)
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "TR_CTL,Trigger Control Register"
|
|
bitfld.long 0x00 31. " TR_ACT ,SW sets this field to '1' by to activate a trigger" "Deactivated,Activated"
|
|
bitfld.long 0x00 30. " TR_OUT ,Specifies whether trigger activation is for specific input or output trigger of the trigger multiplexer" "Input,Output"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TR_COUNT ,8-bit amount of cycles a specific trigger is activated"
|
|
bitfld.long 0x00 8.--11. " TR_GROUP ,Specifies the trigger group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " TR_SEL ,7-bit specifies the activated trigger when TR_ACT is '1'"
|
|
else
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "TR_CTL,Trigger Control Register"
|
|
bitfld.long 0x00 31. " TR_ACT ,SW sets this field to '1' by to activate a trigger" "Deactivated,Activated"
|
|
bitfld.long 0x00 30. " TR_OUT ,Specifies whether trigger activation is for specific input or output trigger of the trigger multiplexer" "Input,Output"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TR_COUNT ,8-bit amount of cycles a specific trigger is activated"
|
|
bitfld.long 0x00 8.--11. " TR_GROUP ,Specifies the trigger group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PRGIO_PRT0"
|
|
base ad:0x40050000
|
|
width 21.
|
|
if (((per.l(ad:0x40050000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PRT0_CTL,Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enable for programmable IO" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " PIPELINE_EN ,Enable for pipeline register" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " HLD_OVR ,IO cell hold override functionality" "Not held,Held"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CLOCK_SRC ,Clock and reset source selection" "Io_data_in[0]/'1',Io_data_in[1]/'1',Io_data_in[2]/'1',Io_data_in[3]/'1',Io_data_in[4]/'1',Io_data_in[5]/'1',Io_data_in[6]/'1',Io_data_in[7]/'1',Chip_data[0]/'1',Chip_data[1]/'1',Chip_data[2]/'1',Chip_data[3]/'1',Chip_data[4]/'1',Chip_data[5]/'1',Chip_data[6]/'1',Chip_data[7]/'1',Clk_prgio/Rst_sys_act_n,Clk_prgio/Rst_sys_dpslp_n,Clk_lf/Rst_lf_dpslp_n,0,0,0,0,0,0,0,0,0,0,0,Clk_sys/'1',?..."
|
|
hexmask.long.byte 0x00 0.--7. 1. " BYPASS ,Bypass for programmable IO"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PRT0_SYNC_CTL,Synchronization Control Register"
|
|
bitfld.long 0x00 15. " CHIP_SYNC_EN[7] ,Synchronization of the chip input signals to 'clk_block' for input 7" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 14. " CHIP_SYNC_EN[6] ,Synchronization of the chip input signals to 'clk_block' for input 6" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 13. " CHIP_SYNC_EN[5] ,Synchronization of the chip input signals to 'clk_block' for input 5" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CHIP_SYNC_EN[4] ,Synchronization of the chip input signals to 'clk_block' for input 4" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 11. " CHIP_SYNC_EN[3] ,Synchronization of the chip input signals to 'clk_block' for input 3" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 10. " CHIP_SYNC_EN[2] ,Synchronization of the chip input signals to 'clk_block' for input 2" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CHIP_SYNC_EN[1] ,Synchronization of the chip input signals to 'clk_block' for input 1" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 8. " CHIP_SYNC_EN[0] ,Synchronization of the chip input signals to 'clk_block' for input 0" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 7. " IO_SYNC_EN[7] ,Synchronization of the IO pin input signals to 'clk_block' for IO pin 7" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IO_SYNC_EN[6] ,Synchronization of the IO pin input signals to 'clk_block' for IO pin 6" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 5. " IO_SYNC_EN[5] ,Synchronization of the IO pin input signals to 'clk_block' for IO pin 5" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 4. " IO_SYNC_EN[4] ,Synchronization of the IO pin input signals to 'clk_block' for IO pin 4" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IO_SYNC_EN[3] ,Synchronization of the IO pin input signals to 'clk_block' for IO pin 3" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 2. " IO_SYNC_EN[2] ,Synchronization of the IO pin input signals to 'clk_block' for IO pin 2" "Not synchronized,Synchronized"
|
|
bitfld.long 0x00 1. " IO_SYNC_EN[1] ,Synchronization of the IO pin input signals to 'clk_block' for IO pin 1" "Not synchronized,Synchronized"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IO_SYNC_EN[0] ,Synchronization of the IO pin input signals to 'clk_block' for IO pin 0" "Not synchronized,Synchronized"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PRT0_LUT_SEL0,LUT Component Input Selection"
|
|
bitfld.long 0x00 16.--19. " LUT_TR2_SEL ,LUT input signal,'tr2_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[0],Chip_data[1],Chip_data[2],Chip_data[3],Io_data[0],Io_data[1],Io_data[2],Io_data[3]"
|
|
bitfld.long 0x00 8.--11. " LUT_TR1_SEL ,LUT input signal 'tr1_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[0],Chip_data[1],Chip_data[2],Chip_data[3],Io_data[0],Io_data[1],Io_data[2],Io_data[3]"
|
|
bitfld.long 0x00 0.--3. " LUT_TR1_SEL ,LUT input signal 'tr0_in' source selection" "Data unit,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[0],Chip_data[1],Chip_data[2],Chip_data[3],Io_data[0],Io_data[1],Io_data[2],Io_data[3]"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PRT0_LUT_SEL1,LUT Component Input Selection"
|
|
bitfld.long 0x00 16.--19. " LUT_TR2_SEL ,LUT input signal,'tr2_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[0],Chip_data[1],Chip_data[2],Chip_data[3],Io_data[0],Io_data[1],Io_data[2],Io_data[3]"
|
|
bitfld.long 0x00 8.--11. " LUT_TR1_SEL ,LUT input signal 'tr1_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[0],Chip_data[1],Chip_data[2],Chip_data[3],Io_data[0],Io_data[1],Io_data[2],Io_data[3]"
|
|
bitfld.long 0x00 0.--3. " LUT_TR1_SEL ,LUT input signal 'tr0_in' source selection" "Data unit,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[0],Chip_data[1],Chip_data[2],Chip_data[3],Io_data[0],Io_data[1],Io_data[2],Io_data[3]"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PRT0_LUT_SEL2,LUT Component Input Selection"
|
|
bitfld.long 0x00 16.--19. " LUT_TR2_SEL ,LUT input signal,'tr2_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[0],Chip_data[1],Chip_data[2],Chip_data[3],Io_data[0],Io_data[1],Io_data[2],Io_data[3]"
|
|
bitfld.long 0x00 8.--11. " LUT_TR1_SEL ,LUT input signal 'tr1_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[0],Chip_data[1],Chip_data[2],Chip_data[3],Io_data[0],Io_data[1],Io_data[2],Io_data[3]"
|
|
bitfld.long 0x00 0.--3. " LUT_TR1_SEL ,LUT input signal 'tr0_in' source selection" "Data unit,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[0],Chip_data[1],Chip_data[2],Chip_data[3],Io_data[0],Io_data[1],Io_data[2],Io_data[3]"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PRT0_LUT_SEL3,LUT Component Input Selection"
|
|
bitfld.long 0x00 16.--19. " LUT_TR2_SEL ,LUT input signal,'tr2_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[0],Chip_data[1],Chip_data[2],Chip_data[3],Io_data[0],Io_data[1],Io_data[2],Io_data[3]"
|
|
bitfld.long 0x00 8.--11. " LUT_TR1_SEL ,LUT input signal 'tr1_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[0],Chip_data[1],Chip_data[2],Chip_data[3],Io_data[0],Io_data[1],Io_data[2],Io_data[3]"
|
|
bitfld.long 0x00 0.--3. " LUT_TR1_SEL ,LUT input signal 'tr0_in' source selection" "Data unit,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[0],Chip_data[1],Chip_data[2],Chip_data[3],Io_data[0],Io_data[1],Io_data[2],Io_data[3]"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PRT0_LUT_SEL4,LUT Component Input Selection"
|
|
bitfld.long 0x00 16.--19. " LUT_TR2_SEL ,LUT input signal,'tr2_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[4],Chip_data[5],Chip_data[6],Chip_data[7],Io_data[4],Io_data[5],Io_data[6],Io_data[7]"
|
|
bitfld.long 0x00 8.--11. " LUT_TR1_SEL ,LUT input signal 'tr1_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[4],Chip_data[5],Chip_data[6],Chip_data[7],Io_data[4],Io_data[5],Io_data[6],Io_data[7]"
|
|
bitfld.long 0x00 0.--3. " LUT_TR1_SEL ,LUT input signal 'tr0_in' source selection" "Data unit,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[4],Chip_data[5],Chip_data[6],Chip_data[7],Io_data[4],Io_data[5],Io_data[6],Io_data[7]"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "PRT0_LUT_SEL5,LUT Component Input Selection"
|
|
bitfld.long 0x00 16.--19. " LUT_TR2_SEL ,LUT input signal,'tr2_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[4],Chip_data[5],Chip_data[6],Chip_data[7],Io_data[4],Io_data[5],Io_data[6],Io_data[7]"
|
|
bitfld.long 0x00 8.--11. " LUT_TR1_SEL ,LUT input signal 'tr1_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[4],Chip_data[5],Chip_data[6],Chip_data[7],Io_data[4],Io_data[5],Io_data[6],Io_data[7]"
|
|
bitfld.long 0x00 0.--3. " LUT_TR1_SEL ,LUT input signal 'tr0_in' source selection" "Data unit,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[4],Chip_data[5],Chip_data[6],Chip_data[7],Io_data[4],Io_data[5],Io_data[6],Io_data[7]"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "PRT0_LUT_SEL6,LUT Component Input Selection"
|
|
bitfld.long 0x00 16.--19. " LUT_TR2_SEL ,LUT input signal,'tr2_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[4],Chip_data[5],Chip_data[6],Chip_data[7],Io_data[4],Io_data[5],Io_data[6],Io_data[7]"
|
|
bitfld.long 0x00 8.--11. " LUT_TR1_SEL ,LUT input signal 'tr1_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[4],Chip_data[5],Chip_data[6],Chip_data[7],Io_data[4],Io_data[5],Io_data[6],Io_data[7]"
|
|
bitfld.long 0x00 0.--3. " LUT_TR1_SEL ,LUT input signal 'tr0_in' source selection" "Data unit,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[4],Chip_data[5],Chip_data[6],Chip_data[7],Io_data[4],Io_data[5],Io_data[6],Io_data[7]"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "PRT0_LUT_SEL7,LUT Component Input Selection"
|
|
bitfld.long 0x00 16.--19. " LUT_TR2_SEL ,LUT input signal,'tr2_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[4],Chip_data[5],Chip_data[6],Chip_data[7],Io_data[4],Io_data[5],Io_data[6],Io_data[7]"
|
|
bitfld.long 0x00 8.--11. " LUT_TR1_SEL ,LUT input signal 'tr1_in' source selection" "LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[4],Chip_data[5],Chip_data[6],Chip_data[7],Io_data[4],Io_data[5],Io_data[6],Io_data[7]"
|
|
bitfld.long 0x00 0.--3. " LUT_TR1_SEL ,LUT input signal 'tr0_in' source selection" "Data unit,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,Chip_data[4],Chip_data[5],Chip_data[6],Chip_data[7],Io_data[4],Io_data[5],Io_data[6],Io_data[7]"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PRT0_LUT_CTL0,LUT Component Control Register"
|
|
bitfld.long 0x00 8.--9. " LUT_OPC ,LUT opcode specifies LUT operation" "Combinatoral output/No feedback,Combinatoral output/Feedback,Sequential output/No feedback,Register with asynchronous set and reset"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LUT ,LUT configuration"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "PRT0_LUT_CTL1,LUT Component Control Register"
|
|
bitfld.long 0x00 8.--9. " LUT_OPC ,LUT opcode specifies LUT operation" "Combinatoral output/No feedback,Combinatoral output/Feedback,Sequential output/No feedback,Register with asynchronous set and reset"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LUT ,LUT configuration"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "PRT0_LUT_CTL2,LUT Component Control Register"
|
|
bitfld.long 0x00 8.--9. " LUT_OPC ,LUT opcode specifies LUT operation" "Combinatoral output/No feedback,Combinatoral output/Feedback,Sequential output/No feedback,Register with asynchronous set and reset"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LUT ,LUT configuration"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PRT0_LUT_CTL3,LUT Component Control Register"
|
|
bitfld.long 0x00 8.--9. " LUT_OPC ,LUT opcode specifies LUT operation" "Combinatoral output/No feedback,Combinatoral output/Feedback,Sequential output/No feedback,Register with asynchronous set and reset"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LUT ,LUT configuration"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PRT0_LUT_CTL4,LUT Component Control Register"
|
|
bitfld.long 0x00 8.--9. " LUT_OPC ,LUT opcode specifies LUT operation" "Combinatoral output/No feedback,Combinatoral output/Feedback,Sequential output/No feedback,Register with asynchronous set and reset"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LUT ,LUT configuration"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "PRT0_LUT_CTL5,LUT Component Control Register"
|
|
bitfld.long 0x00 8.--9. " LUT_OPC ,LUT opcode specifies LUT operation" "Combinatoral output/No feedback,Combinatoral output/Feedback,Sequential output/No feedback,Register with asynchronous set and reset"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LUT ,LUT configuration"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PRT0_LUT_CTL6,LUT Component Control Register"
|
|
bitfld.long 0x00 8.--9. " LUT_OPC ,LUT opcode specifies LUT operation" "Combinatoral output/No feedback,Combinatoral output/Feedback,Sequential output/No feedback,Register with asynchronous set and reset"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LUT ,LUT configuration"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PRT0_LUT_CTL7,LUT Component Control Register"
|
|
bitfld.long 0x00 8.--9. " LUT_OPC ,LUT opcode specifies LUT operation" "Combinatoral output/No feedback,Combinatoral output/Feedback,Sequential output/No feedback,Register with asynchronous set and reset"
|
|
hexmask.long.byte 0x00 0.--7. 1. " LUT ,LUT configuration"
|
|
group.long 0xC0++0x07
|
|
line.long 0x00 "PRT0_DU_SEL,Data Unit Component Input Selection"
|
|
bitfld.long 0x00 28.--29. " DU_DATA1_SEL ,Data unit input data data1_in source selection" "Constant 0,Chip_data[7:0],Io_data_in[7:0],PRGIO_PRTx_DATA"
|
|
bitfld.long 0x00 24.--25. " DU_DATA0_SEL ,Data unit input data data0_in source selection" "Constant 0,Chip_data[7:0],Io_data_in[7:0],PRGIO_PRTx_DATA"
|
|
bitfld.long 0x00 16.--19. " DU_TR2_SEL ,Data unit input signal tr2_in source selection" "Constant 0,Constant 1,Data unit output,LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " DU_TR1_SEL ,Data unit input signal tr1_in selection" "Constant 0,Constant 1,Data unit output,LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,?..."
|
|
bitfld.long 0x00 0.--3. " DU_TR0_SEL ,Data unit input signal tr0_in source selection" "Constant 0,Constant 1,Data unit output,LUT 0,LUT 1,LUT 2,LUT 3,LUT 4,LUT 5,LUT 6,LUT 7,?..."
|
|
line.long 0x04 "PRT0_DU_CTL,Data Unit Component Control Register"
|
|
bitfld.long 0x04 8.--11. " DU_OPC ,Data unit opcode" ",INCR,DECR,INCR_WRAP,DECR_WRAP,INCR_DECR,INCR_DECR_WRAP,ROR,SHR,AND_OR,SHR_MAJ3,SHR_EQL,?..."
|
|
bitfld.long 0x04 0.--2. " DU_SIZE ,Size/width of the data unit data operands" "0/1,1/2,2/3,3/4,4/5,5/6,6/7,7/8"
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "PRT0_DATA,Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data unit input data source"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PRT0_CTL,Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,Enable for programmable IO" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SAR (Successive Approximation Register)"
|
|
base ad:0x403A0000
|
|
width 22.
|
|
if (((per.l(ad:0x403A0000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Analog Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,SAR enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SWITCH_DISABLE ,Disable SAR sequencer from enabling routing switches" "Normal mode,Disabled"
|
|
bitfld.long 0x00 29. " DSI_MODE ,SAR sequencer takes configuration from DSI signals" "Normal mode,Ignore mode"
|
|
textline " "
|
|
sif !cpuis("CY8C4*-BL*")
|
|
bitfld.long 0x00 28. " DSI_SYNC_CONFIG ,Synchronize the DSI config signals" "No,Yes"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " DEEPSLEEP_ON ,Enabled during DeepSleep mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " ICONT_LV ,SARADC low power mode" "NORMAL_PWR,HALF_PWR,THIRD_PWR,QUARTER_PWR"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 21. " REFBUF_EN ,SARREFBUF enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " BOOSTPUMP_EN ,SARDAC internal pump" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " PWR_CTRL_VREF ,VREF buffer low power mode" "NORMAL_PWR,HALF_PWR,MORE_PWR,QUARTER_PWR"
|
|
bitfld.long 0x00 13. " SAR_HW_CTRL_NEGVREF ,Hardware control" "Firmware,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " NEG_SEL ,SARADAC internal NEG selection for single ended conversion" "Vssa_kelvin,Art_vssa,P1,P3,P5,P7,Acore,Vref"
|
|
bitfld.long 0x00 7. " VREF_BYP_CAP_EN ,VREF bypass cap enable for when VREF buffer is on" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " VREF_SEL ,SARADAC internal VREF selection" "Vref0,Vref1,Vref2,Vref_aroute,Vbgr,Vref_ext,Vdda_div2,Vdda"
|
|
if (((per.l(ad:0x403A0000+0x04))&0x10000000)==0x10000000)
|
|
if (((per.l(ad:0x403A0000+0x04))&0x400000)==0x400000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SAMPLE_CTRL,Sample Control Register"
|
|
bitfld.long 0x00 31. " EOS_DSI_OUT_EN ,Enable to output EOS_INTR" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 30. " TRIGGER_OUT_EN ,SAR output trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " VALID_IGNORE ,Ignore UAB valid signal" "Not ignored,Ignored"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 22. " UAB_SCAN_MODE ,Select whether uabs are scheduled or unscheduled" "Unscheduled,Scheduled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " DSI_SYNC_TRIGGER ,Hardware trigger signal" "Pulse,Level"
|
|
sif cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 18. " DSI_TRIGGER_LEVEL ,DSI trigger signal input" "Pulse,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSI_TRIGGER_EN ,DSI hardware trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CONTINOUS ,Continous scan" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 8. " AVG_MODE ,Averaging mode" "Accundump,Interleaved"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " AVG_SHIFT ,Averaging shift" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVG_CNT ,Averaging count for channels that have averaging enabled" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " DIFFERENTIAL_SIGNED ,Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NED_ADDR_EN is set to 1" "Unsigned,Signed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINGLE_ENDED_SIGNED ,Output data from a single ended conversion as a signed value" "Unsigned,Signed"
|
|
bitfld.long 0x00 1. " LEFT_ALIGN ,Left align data in data" "Right align,Left align"
|
|
bitfld.long 0x00 0. " SUB_RESOLUTION ,Conversion resolution for channels that have sub-resolution enabled" "8b,10b"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SAMPLE_CTRL,Sample Control Register"
|
|
bitfld.long 0x00 31. " EOS_DSI_OUT_EN ,Enable to output EOS_INTR" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 30. " TRIGGER_OUT_EN ,SAR output trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " VALID_IGNORE ,Ignore UAB valid signal" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x00 23. " REPEAT_INVALID ,For unscheduled UAB_SCAN_MODE only" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 22. " UAB_SCAN_MODE ,Select whether uabs are scheduled or unscheduled" "UNSCHEDULED,SCHEDULED"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " DSI_SYNC_TRIGGER ,Hardware trigger signal" "Pulse,Level"
|
|
sif (cpuis("CY8C4*-BL*")||cpuis("CY8C4*-4*"))
|
|
textline " "
|
|
bitfld.long 0x00 18. " DSI_TRIGGER_LEVEL ,DSI trigger signal input" "Pulse,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSI_TRIGGER_EN ,DSI hardware trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CONTINOUS ,Continous scan" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 8. " AVG_MODE ,Averaging mode" "Accundump,Interleaved"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " AVG_SHIFT ,Averaging shift" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVG_CNT ,Averaging count for channels that have averaging enabled" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " DIFFERENTIAL_SIGNED ,Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NED_ADDR_EN is set to 1" "Unsigned,Signed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINGLE_ENDED_SIGNED ,Output data from a single ended conversion as a signed value" "Unsigned,Signed"
|
|
bitfld.long 0x00 1. " LEFT_ALIGN ,Left align data in data" "Right align,Left align"
|
|
bitfld.long 0x00 0. " SUB_RESOLUTION ,Conversion resolution for channels that have sub-resolution enabled" "8b,10b"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x403A0000+0x04))&0x400000)==0x400000)
|
|
if (((per.l(ad:0x403A0000+0x04))&0x08000000)==0x08000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SAMPLE_CTRL,Sample Control Register"
|
|
bitfld.long 0x00 31. " EOS_DSI_OUT_EN ,Enable to output EOS_INTR" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 30. " TRIGGER_OUT_EN ,SAR output trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " VALID_IGNORE ,Ignore UAB valid signal" "Not ignored,Ignored"
|
|
bitfld.long 0x00 27. " VALID_SEL_EN ,Enable static UAB valid selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " VALID_SEL ,Static UAB valid select" "UAB0 half 0,UAB0 half 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " UAB_SCAN_MODE ,Select whether uabs are scheduled or unscheduled" "Unscheduled,Scheduled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " DSI_SYNC_TRIGGER ,Hardware trigger signal" "Pulse,Level"
|
|
sif cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 18. " DSI_TRIGGER_LEVEL ,DSI trigger signal input" "Pulse,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSI_TRIGGER_EN ,DSI hardware trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CONTINOUS ,Continous scan" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 8. " AVG_MODE ,Averaging mode" "Accundump,Interleaved"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " AVG_SHIFT ,Averaging shift" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVG_CNT ,Averaging count for channels that have averaging enabled" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " DIFFERENTIAL_SIGNED ,Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NED_ADDR_EN is set to 1" "Unsigned,Signed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINGLE_ENDED_SIGNED ,Output data from a single ended conversion as a signed value" "Unsigned,Signed"
|
|
bitfld.long 0x00 1. " LEFT_ALIGN ,Left align data in data" "Right align,Left align"
|
|
bitfld.long 0x00 0. " SUB_RESOLUTION ,Conversion resolution for channels that have Sub-resolution enabled" "8b,10b"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SAMPLE_CTRL,Sample Control Register"
|
|
bitfld.long 0x00 31. " EOS_DSI_OUT_EN ,Enable to output EOS_INTR" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 30. " TRIGGER_OUT_EN ,SAR output trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " VALID_IGNORE ,Ignore UAB valid signal" "Not ignored,Ignored"
|
|
bitfld.long 0x00 27. " VALID_SEL_EN ,Enable static UAB valid selection" "Disabled,Enabled"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 22. " UAB_SCAN_MODE ,Select whether uabs are scheduled or unscheduled" "Unscheduled,Scheduled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " DSI_SYNC_TRIGGER ,Hardware trigger signal" "Pulse,Level"
|
|
sif cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 18. " DSI_TRIGGER_LEVEL ,DSI trigger signal input" "Pulse,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSI_TRIGGER_EN ,DSI hardware trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CONTINOUS ,Continous scan" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 8. " AVG_MODE ,Averaging mode" "Accundump,Interleaved"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " AVG_SHIFT ,Averaging shift" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVG_CNT ,Averaging count for channels that have averaging enabled" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " DIFFERENTIAL_SIGNED ,Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NED_ADDR_EN is set to 1" "Unsigned,Signed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINGLE_ENDED_SIGNED ,Output data from a single ended conversion as a signed value" "Unsigned,Signed"
|
|
bitfld.long 0x00 1. " LEFT_ALIGN ,Left align data in data" "Right align,Left align"
|
|
bitfld.long 0x00 0. " SUB_RESOLUTION ,Conversion resolution for channels that have Sub-resolution enabled" "8b,10b"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x403A0000+0x04))&0x08000000)==0x08000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SAMPLE_CTRL,Sample Control Register"
|
|
bitfld.long 0x00 31. " EOS_DSI_OUT_EN ,Enable to output EOS_INTR" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 30. " TRIGGER_OUT_EN ,SAR output trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " VALID_IGNORE ,Ignore UAB valid signal" "Not ignored,Ignored"
|
|
bitfld.long 0x00 27. " VALID_SEL_EN ,Enable static UAB valid selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " VALID_SEL ,Static UAB valid select" "UAB0 half 0,UAB0 half 1,?..."
|
|
bitfld.long 0x00 23. " REPEAT_INVALID ,For unscheduled UAB_SCAN_MODE only" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 22. " UAB_SCAN_MODE ,Select whether uabs are scheduled or unscheduled" "Unscheduled,Scheduled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " DSI_SYNC_TRIGGER ,Hardware trigger signal" "Pulse,Level"
|
|
sif (cpuis("CY8C4*-BL*")||cpuis("CY8C4*-4*"))
|
|
textline " "
|
|
bitfld.long 0x00 18. " DSI_TRIGGER_LEVEL ,DSI trigger signal input" "Pulse,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSI_TRIGGER_EN ,DSI hardware trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CONTINOUS ,Continous scan" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 8. " AVG_MODE ,Averaging mode" "Accundump,Interleaved"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " AVG_SHIFT ,Averaging shift" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVG_CNT ,Averaging count for channels that have averaging enabled" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " DIFFERENTIAL_SIGNED ,Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NED_ADDR_EN is set to 1" "Unsigned,Signed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINGLE_ENDED_SIGNED ,Output data from a single ended conversion as a signed value" "Unsigned,Signed"
|
|
bitfld.long 0x00 1. " LEFT_ALIGN ,Left align data in data" "Right align,Left align"
|
|
bitfld.long 0x00 0. " SUB_RESOLUTION ,Conversion resolution for channels that have Sub-resolution enabled" "8b,10b"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SAMPLE_CTRL,Sample Control Register"
|
|
bitfld.long 0x00 31. " EOS_DSI_OUT_EN ,Enable to output EOS_INTR" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 30. " TRIGGER_OUT_EN ,SAR output trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " VALID_IGNORE ,Ignore UAB valid signal" "Not ignored,Ignored"
|
|
bitfld.long 0x00 27. " VALID_SEL_EN ,Enable static UAB valid selection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " REPEAT_INVALID ,For unscheduled UAB_SCAN_MODE only" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 22. " UAB_SCAN_MODE ,Select whether uabs are scheduled or unscheduled" "Unscheduled,Scheduled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 19. " DSI_SYNC_TRIGGER ,Hardware trigger signal" "Pulse,Level"
|
|
sif (cpuis("CY8C4*-BL*")||cpuis("CY8C4*-4*"))
|
|
textline " "
|
|
bitfld.long 0x00 18. " DSI_TRIGGER_LEVEL ,DSI trigger signal input" "Pulse,Level"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSI_TRIGGER_EN ,DSI hardware trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CONTINOUS ,Continous scan" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 8. " AVG_MODE ,Averaging mode" "Accundump,Interleaved"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 7. " AVG_SHIFT ,Averaging shift" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " AVG_CNT ,Averaging count for channels that have averaging enabled" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " DIFFERENTIAL_SIGNED ,Output data from a differential conversion as a signed value when DIFFERENTIAL_EN or NED_ADDR_EN is set to 1" "Unsigned,Signed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SINGLE_ENDED_SIGNED ,Output data from a single ended conversion as a signed value" "Unsigned,Signed"
|
|
bitfld.long 0x00 1. " LEFT_ALIGN ,Left align data in data" "Right align,Left align"
|
|
bitfld.long 0x00 0. " SUB_RESOLUTION ,Conversion resolution for channels that have Sub-resolution enabled" "8b,10b"
|
|
endif
|
|
endif
|
|
endif
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "SAMPLE_TIME01,Sample Time Specification ST0 And ST1"
|
|
hexmask.long.word 0x00 16.--25. 1. " SAMPLE_TIME1 ,10-bit sample time1"
|
|
hexmask.long.word 0x00 0.--9. 1. " SAMPLE_TIME0 ,10-bit sample time0 in ADC clock cycles"
|
|
line.long 0x04 "SAMPLE_TIME23,Sample Time Specification ST2 And ST3"
|
|
hexmask.long.word 0x04 16.--25. 1. " SAMPLE_TIME3 ,10-bit sample time3"
|
|
hexmask.long.word 0x04 0.--9. 1. " SAMPLE_TIME2 ,10-bit sample time2"
|
|
line.long 0x08 "RANGE_THRES,Global Range Detect Threshold Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " RANGE_HIGH ,16-bit high threshold for range detect"
|
|
hexmask.long.word 0x08 0.--15. 1. " RANGE_LOW ,16-bit low threshold for range detect"
|
|
line.long 0x0C "RANGE_COND,Global Range Detect Mode Register"
|
|
bitfld.long 0x0C 30.--31. " RANGE_COND ,Range condition select" "Below,Inside,Above,Outside"
|
|
line.long 0x10 "CHAN_EN,Enable Bits For The Channels"
|
|
bitfld.long 0x10 15. " CHAN15_EN ,Channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " CHAN14_EN ,Channel 14 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " CHAN13_EN ,Channel 13 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 12. " CHAN12_EN ,Channel 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " CHAN11_EN ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " CHAN10_EN ,Channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " CHAN9_EN ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " CHAN8_EN ,Channel 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 7. " CHAN7_EN ,Channel 7 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 6. " CHAN6_EN ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " CHAN5_EN ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " CHAN4_EN ,Channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " CHAN3_EN ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " CHAN2_EN ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " CHAN1_EN ,Channel 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CHAN0_EN ,Channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x14 "START_CTRL,Start Control Register"
|
|
bitfld.long 0x14 0. " FW_TRIGGER ,Firmware trigger" "Scan disabled,Scan enabled"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DFT_CTRL,DFT Control Register"
|
|
bitfld.long 0x00 31. " ADFT_OVERRIDE ,ADFT override" "No override,Override"
|
|
bitfld.long 0x00 29. " DCEN ,Delay control enable for latch" "Double time,Normal time"
|
|
bitfld.long 0x00 28. " EN_CSEL_DFT ,Mux select signal for DAC control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " SEL_CSEL_DFT ,DFT bits for DAC array" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--22. " DFT_OUTC ,DFT control for preamp outputs" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--19. " DFT_INC ,DFT control for preamp inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HIZ ,DFT control for getting higher input impedance" "0,1"
|
|
bitfld.long 0x00 0. " DLY_INC ,Control for delay circuits on sampling phase" "Normal delay,Double delay"
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<0.))==0x01<<0.)
|
|
if (((per.l(ad:0x403A0000+0x80))&0x0100)==0x0100)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CHAN_CONFIG0,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CHAN_CONFIG0,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<1.))==0x01<<1.)
|
|
if (((per.l(ad:0x403A0000+0x84))&0x0100)==0x0100)
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CHAN_CONFIG1,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CHAN_CONFIG1,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<2.))==0x01<<2.)
|
|
if (((per.l(ad:0x403A0000+0x88))&0x0100)==0x0100)
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CHAN_CONFIG2,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CHAN_CONFIG2,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<3.))==0x01<<3.)
|
|
if (((per.l(ad:0x403A0000+0x8C))&0x0100)==0x0100)
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHAN_CONFIG3,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CHAN_CONFIG3,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<4.))==0x01<<4.)
|
|
if (((per.l(ad:0x403A0000+0x90))&0x0100)==0x0100)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CHAN_CONFIG4,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CHAN_CONFIG4,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<5.))==0x01<<5.)
|
|
if (((per.l(ad:0x403A0000+0x94))&0x0100)==0x0100)
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CHAN_CONFIG5,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CHAN_CONFIG5,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<6.))==0x01<<6.)
|
|
if (((per.l(ad:0x403A0000+0x98))&0x0100)==0x0100)
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CHAN_CONFIG6,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CHAN_CONFIG6,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<7.))==0x01<<7.)
|
|
if (((per.l(ad:0x403A0000+0x9C))&0x0100)==0x0100)
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CHAN_CONFIG7,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CHAN_CONFIG7,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<8.))==0x01<<8.)
|
|
if (((per.l(ad:0x403A0000+0xA0))&0x0100)==0x0100)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CHAN_CONFIG8,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CHAN_CONFIG8,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<9.))==0x01<<9.)
|
|
if (((per.l(ad:0x403A0000+0xA4))&0x0100)==0x0100)
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CHAN_CONFIG9,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CHAN_CONFIG9,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<10.))==0x01<<10.)
|
|
if (((per.l(ad:0x403A0000+0xA8))&0x0100)==0x0100)
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CHAN_CONFIG10,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CHAN_CONFIG10,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<11.))==0x01<<11.)
|
|
if (((per.l(ad:0x403A0000+0xAC))&0x0100)==0x0100)
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CHAN_CONFIG11,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CHAN_CONFIG11,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<12.))==0x01<<12.)
|
|
if (((per.l(ad:0x403A0000+0xB0))&0x0100)==0x0100)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CHAN_CONFIG12,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "CHAN_CONFIG12,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<13.))==0x01<<13.)
|
|
if (((per.l(ad:0x403A0000+0xB4))&0x0100)==0x0100)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CHAN_CONFIG13,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CHAN_CONFIG13,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<14.))==0x01<<14.)
|
|
if (((per.l(ad:0x403A0000+0xB8))&0x0100)==0x0100)
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CHAN_CONFIG14,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CHAN_CONFIG14,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
if ((((per.l(ad:0x403A0000+0x20))&0x01<<15.))==0x01<<15.)
|
|
if (((per.l(ad:0x403A0000+0xBC))&0x0100)==0x0100)
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CHAN_CONFIG15,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 0.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
else
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CHAN_CONFIG15,Channel Configuration Register"
|
|
bitfld.long 0x00 31. " DSI_OUT_EN ,Data output enable for this channel" "Disabled,Enabled"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 24. " NEG_ADDR_EN ,Negative address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "Sarmux,,,,,Aroute_virt2,Aroute_virt1,?..."
|
|
bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "0,1,2,3"
|
|
bitfld.long 0x00 10. " AVG_EN ,Averaging enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RESOLUTION ,Resolution for this channel" "Maxres,Subres"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--6. " POS_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "Sarmux,Ctb0,Ctb1,Ctb2,Ctb3,Aroute_virt2,Aroute_virt1,Sarmux_virt"
|
|
bitfld.long 0x00 1.--2. " POS_PIN_ADDR ,Address of the pin to be sampled by this channel" "0,1,2,3"
|
|
endif
|
|
endif
|
|
rgroup.long 0x100++0x03
|
|
line.long 0x00 "CHAN_WORK0,Channel 0 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x104++0x03
|
|
line.long 0x00 "CHAN_WORK1,Channel 1 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x108++0x03
|
|
line.long 0x00 "CHAN_WORK2,Channel 2 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "CHAN_WORK3,Channel 3 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x110++0x03
|
|
line.long 0x00 "CHAN_WORK4,Channel 4 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x114++0x03
|
|
line.long 0x00 "CHAN_WORK5,Channel 5 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x118++0x03
|
|
line.long 0x00 "CHAN_WORK6,Channel 6 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x11C++0x03
|
|
line.long 0x00 "CHAN_WORK7,Channel 7 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x120++0x03
|
|
line.long 0x00 "CHAN_WORK8,Channel 8 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x124++0x03
|
|
line.long 0x00 "CHAN_WORK9,Channel 9 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x128++0x03
|
|
line.long 0x00 "CHAN_WORK10,Channel 10 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x12C++0x03
|
|
line.long 0x00 "CHAN_WORK11,Channel 11 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x130++0x03
|
|
line.long 0x00 "CHAN_WORK12,Channel 12 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x134++0x03
|
|
line.long 0x00 "CHAN_WORK13,Channel 13 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x138++0x03
|
|
line.long 0x00 "CHAN_WORK14,Channel 14 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x13C++0x03
|
|
line.long 0x00 "CHAN_WORK15,Channel 15 Working Data Register"
|
|
bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_UPDATED register" "Disabled,Updated"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_WORK_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_WORK_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " WORK ,16-bit SAR conversion working data of the channel"
|
|
rgroup.long 0x180++0x03
|
|
line.long 0x00 "CHAN_RESULT0,Channel 0 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x184++0x03
|
|
line.long 0x00 "CHAN_RESULT1,Channel 1 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "CHAN_RESULT2,Channel 2 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "CHAN_RESULT3,Channel 3 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "CHAN_RESULT4,Channel 4 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "CHAN_RESULT5,Channel 5 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "CHAN_RESULT6,Channel 6 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "CHAN_RESULT7,Channel 7 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "CHAN_RESULT8,Channel 8 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "CHAN_RESULT9,Channel 9 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "CHAN_RESULT10,Channel 10 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1AC++0x03
|
|
line.long 0x00 "CHAN_RESULT11,Channel 11 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "CHAN_RESULT12,Channel 12 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "CHAN_RESULT13,Channel 13 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "CHAN_RESULT14,Channel 14 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "CHAN_RESULT15,Channel 15 Result Data Register"
|
|
bitfld.long 0x00 31. " CHAN_RESULT_UPDATE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_UPDATED register" "Disabled,Updated"
|
|
bitfld.long 0x00 30. " RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_RANGE_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_SATURATE_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " CHAN_RESULT_NEWVALUE_MIR ,Mirror bit of corresponding bit in SAR_CHAN_RESULT_NEWVALUE register" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " RESULT ,16-bit SAR conversion result of the channel"
|
|
rgroup.long 0x200++0x07
|
|
line.long 0x00 "CHAN_WORK_VALID,Channel Working Data Register Valid Bits"
|
|
bitfld.long 0x00 15. " CHAN_WORK_VALID[15] ,Corresponding WORK register for channel 15 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 14. " [14] ,Corresponding WORK register for channel 14 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 13. " [13] ,Corresponding WORK register for channel 13 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Corresponding WORK register for channel 12 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 11. " [11] ,Corresponding WORK register for channel 11 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 10. " [10] ,Corresponding WORK register for channel 10 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 9. " [9] ,Corresponding WORK register for channel 9 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 8. " [8] ,Corresponding WORK register for channel 8 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 7. " [7] ,Corresponding WORK register for channel 7 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Corresponding WORK register for channel 6 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " [5] ,Corresponding WORK register for channel 5 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 4. " [4] ,Corresponding WORK register for channel 4 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Corresponding WORK register for channel 3 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 2. " [2] ,Corresponding WORK register for channel 2 is valid" "Not valid,Valid"
|
|
bitfld.long 0x00 1. " [1] ,Corresponding WORK register for channel 1 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Corresponding WORK register for channel 0 is valid" "Not valid,Valid"
|
|
line.long 0x04 "CHAN_RESULT_VALID,Channel Result Data Register Updated Bits"
|
|
bitfld.long 0x04 15. " CHAN_RESULT_VALID[15] ,Corresponding RESULT register for channel 15 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 14. " [14] ,Corresponding RESULT register for channel 14 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 13. " [13] ,Corresponding RESULT register for channel 13 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 12. " [12] ,Corresponding RESULT register for channel 12 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 11. " [11] ,Corresponding RESULT register for channel 11 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 10. " [10] ,Corresponding RESULT register for channel 10 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [9] ,Corresponding RESULT register for channel 9 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 8. " [8] ,Corresponding RESULT register for channel 8 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 7. " [7] ,Corresponding RESULT register for channel 7 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 6. " [6] ,Corresponding RESULT register for channel 6 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 5. " [5] ,Corresponding RESULT register for channel 5 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 4. " [4] ,Corresponding RESULT register for channel 4 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Corresponding RESULT register for channel 3 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 2. " [2] ,Corresponding RESULT register for channel 2 is valid" "Not valid,Valid"
|
|
bitfld.long 0x04 1. " [1] ,Corresponding RESULT register for channel 1 is valid" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 0. " [0] ,Corresponding RESULT register for channel 0 is valid" "Not valid,Valid"
|
|
sif cpuis("CY8C4*-BL*")
|
|
if (((per.l(ad:0x403A0000+0x208))&0x80000000)==0x80000000)
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "STATUS,Current Status Of Internal SAR Registers"
|
|
bitfld.long 0x00 31. " BUSY ,SAR busy" "Idle,Busy"
|
|
bitfld.long 0x00 30. " SW_VREF_NEG ,Current switch status" "Not switched,Switched"
|
|
bitfld.long 0x00 0.--4. " CUR_CHAN ,Current channel being sampled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "STATUS,Current Status Of Internal SAR Registers"
|
|
bitfld.long 0x00 31. " BUSY ,SAR busy" "Idle,Busy"
|
|
bitfld.long 0x00 30. " SW_VREF_NEG ,Current switch status" "Not switched,Switched"
|
|
endif
|
|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "AVG_STAT,Current Averaging Status"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CUR_AVG_CNT ,The current value of the averaging counter"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CUR_AVG_ACCU ,The current value of the averaging accumulator"
|
|
else
|
|
rgroup.long 0x208++0x07
|
|
line.long 0x00 "CHAN_WORK_NEWVALUE,Channel Working Data Register 'New Value' Bits"
|
|
bitfld.long 0x00 15. " CHAN_WORK_NEWVALUE[15] ,Corresponding WORK data register for channel 15 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 14. " [14] ,Corresponding WORK data register for channel 14 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 13. " [13] ,Corresponding WORK data register for channel 13 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 12. " [12] ,Corresponding WORK data register for channel 12 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 11. " [11] ,Corresponding WORK data register for channel 11 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 10. " [10] ,Corresponding WORK data register for channel 10 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 9. " [9] ,Corresponding WORK data register for channel 9 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 8. " [8] ,Corresponding WORK data register for channel 8 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 7. " [7] ,Corresponding WORK data register for channel 7 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 6. " [6] ,Corresponding WORK data register for channel 6 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 5. " [5] ,Corresponding WORK data register for channel 5 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 4. " [4] ,Corresponding WORK data register for channel 4 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 3. " [3] ,Corresponding WORK data register for channel 3 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 2. " [2] ,Corresponding WORK data register for channel 2 received a new value" "Not received,Received"
|
|
bitfld.long 0x00 1. " [1] ,Corresponding WORK data register for channel 1 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x00 0. " [0] ,Corresponding WORK data register for channel 0 received a new value" "Not received,Received"
|
|
line.long 0x04 "CHAN_RESULT_NEWVALUE,Channel Result Data Register 'New Value' Bits"
|
|
bitfld.long 0x04 15. " CHAN_RESULT_NEWVALUE[15] ,Corresponding RESULT data register for channel 15 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 14. " [14] ,Corresponding RESULT data register for channel 14 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 13. " [13] ,Corresponding RESULT data register for channel 13 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 12. " [12] ,Corresponding RESULT data register for channel 12 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 11. " [11] ,Corresponding RESULT data register for channel 11 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 10. " [10] ,Corresponding RESULT data register for channel 10 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [9] ,Corresponding RESULT data register for channel 9 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 8. " [8] ,Corresponding RESULT data register for channel 8 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 7. " [7] ,Corresponding RESULT data register for channel 7 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 6. " [6] ,Corresponding RESULT data register for channel 6 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 5. " [5] ,Corresponding RESULT data register for channel 5 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 4. " [4] ,Corresponding RESULT data register for channel 4 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Corresponding RESULT data register for channel 3 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 2. " [2] ,Corresponding RESULT data register for channel 2 received a new value" "Not received,Received"
|
|
bitfld.long 0x04 1. " [1] ,Corresponding RESULT data register for channel 1 received a new value" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 0. " [0] ,Corresponding RESULT data register for channel 0 received a new value" "Not received,Received"
|
|
endif
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 7. " INJ_COLLISION_INTR ,Injection collision interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " INJ_RANGE_INTR ,Injection range detect interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " INJ_SATURATE_INTR ,Injection saturate interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " INJ_EOC_INTR ,Injection end of conversion interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " DSI_COLLISION_INTR ,DSI collision interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " FW_COLLISION_INTR ,Firmware collision interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " OVERFLOW_INTR ,Overflow interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " EOS_INTR ,End of scan interrupt" "No interrupt,Interrupt"
|
|
group.long 0x214++0x07
|
|
line.long 0x00 "INTR_SET,Interrupt Set Request Register"
|
|
bitfld.long 0x00 7. " INJ_COLLISION_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " INJ_RANGE_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " INJ_SATURATE_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INJ_EOC_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 3. " DSI_COLLISION_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " FW_COLLISION_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVERFLOW_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " EOS_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_MASK,Interrupt Mask Register"
|
|
bitfld.long 0x04 7. " INJ_COLLISION_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x04 6. " INJ_RANGE_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x04 5. " INJ_SATURATE_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " INJ_EOC_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x04 3. " DSI_COLLISION_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " FW_COLLISION_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x04 1. " OVERFLOW_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x04 0. " EOS_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt Masked Request Register"
|
|
bitfld.long 0x00 7. " INJ_COLLISION_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " INJ_RANGE_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " INJ_SATURATE_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INJ_EOC_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " DSI_COLLISION_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " FW_COLLISION_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " OVERFLOW_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " EOS_MASKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0x220++0x0B
|
|
line.long 0x00 "SATURATE_INTR,Saturate Interrupt Request Register"
|
|
eventfld.long 0x00 15. " SATURATE_INTR[15] ,Saturate interrupt channel 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Saturate interrupt channel 14" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Saturate interrupt channel 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 12. " [12] ,Saturate interrupt channel 12" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " [11] ,Saturate interrupt channel 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Saturate interrupt channel 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " [9] ,Saturate interrupt channel 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " [8] ,Saturate interrupt channel 8" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " [7] ,Saturate interrupt channel 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 6. " [6] ,Saturate interrupt channel 6" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Saturate interrupt channel 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Saturate interrupt channel 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " [3] ,Saturate interrupt channel 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Saturate interrupt channel 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Saturate interrupt channel 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " [0] ,Saturate interrupt channel 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "SATURATE_INTR_SET,Saturate Interrupt Set Request Register"
|
|
bitfld.long 0x04 15. " SATURATE_SET[15] ,Set corresponding bit in interrupt request register for channel 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " [14] ,Set corresponding bit in interrupt request register for channel 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " [13] ,Set corresponding bit in interrupt request register for channel 13" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 12. " [12] ,Set corresponding bit in interrupt request register for channel 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " [11] ,Set corresponding bit in interrupt request register for channel 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " [10] ,Set corresponding bit in interrupt request register for channel 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [9] ,Set corresponding bit in interrupt request register for channel 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " [8] ,Set corresponding bit in interrupt request register for channel 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " [7] ,Set corresponding bit in interrupt request register for channel 7" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 6. " [6] ,Set corresponding bit in interrupt request register for channel 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " [5] ,Set corresponding bit in interrupt request register for channel 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " [4] ,Set corresponding bit in interrupt request register for channel 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 3. " [3] ,Set corresponding bit in interrupt request register for channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " [2] ,Set corresponding bit in interrupt request register for channel 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " [1] ,Set corresponding bit in interrupt request register for channel 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " [0] ,Set corresponding bit in interrupt request register for channel 0" "No interrupt,Interrupt"
|
|
line.long 0x08 "SATURATE_INTR_MASK,Saturate Interrupt Mask Register"
|
|
bitfld.long 0x08 15. " SATURATE_MASK[15] ,Mask bit for corresponding bit in interrupt request register for channel 15" "Not masked,Masked"
|
|
bitfld.long 0x08 14. " [14] ,Mask bit for corresponding bit in interrupt request register for channel 14" "Not masked,Masked"
|
|
bitfld.long 0x08 13. " [13] ,Mask bit for corresponding bit in interrupt request register for channel 13" "Not masked,Masked"
|
|
textline " "
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|
bitfld.long 0x08 12. " [12] ,Mask bit for corresponding bit in interrupt request register for channel 12" "Not masked,Masked"
|
|
bitfld.long 0x08 11. " [11] ,Mask bit for corresponding bit in interrupt request register for channel 11" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " [10] ,Mask bit for corresponding bit in interrupt request register for channel 10" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x08 9. " [9] ,Mask bit for corresponding bit in interrupt request register for channel 9" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " [8] ,Mask bit for corresponding bit in interrupt request register for channel 8" "Not masked,Masked"
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|
bitfld.long 0x08 7. " [7] ,Mask bit for corresponding bit in interrupt request register for channel 7" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x08 6. " [6] ,Mask bit for corresponding bit in interrupt request register for channel 6" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " [5] ,Mask bit for corresponding bit in interrupt request register for channel 5" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " [4] ,Mask bit for corresponding bit in interrupt request register for channel 4" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x08 3. " [3] ,Mask bit for corresponding bit in interrupt request register for channel 3" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " [2] ,Mask bit for corresponding bit in interrupt request register for channel 2" "Not masked,Masked"
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|
bitfld.long 0x08 1. " [1] ,Mask bit for corresponding bit in interrupt request register for channel 1" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x08 0. " [0] ,Mask bit for corresponding bit in interrupt request register for channel 0" "Not masked,Masked"
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|
rgroup.long 0x22C++0x03
|
|
line.long 0x00 "SATURATE_INTR_MASKED,Saturate Interrupt Masked Request Register"
|
|
bitfld.long 0x00 15. " SATURATE_MASKED[15] ,Logical AND of corresponding request and mask bit for channel 15" "Not masked,Masked"
|
|
bitfld.long 0x00 14. " [14] ,Logical AND of corresponding request and mask bit for channel 14" "Not masked,Masked"
|
|
bitfld.long 0x00 13. " [13] ,Logical AND of corresponding request and mask bit for channel 13" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x00 12. " [12] ,Logical AND of corresponding request and mask bit for channel 12" "Not masked,Masked"
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|
bitfld.long 0x00 11. " [11] ,Logical AND of corresponding request and mask bit for channel 11" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " [10] ,Logical AND of corresponding request and mask bit for channel 10" "Not masked,Masked"
|
|
textline " "
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|
bitfld.long 0x00 9. " [9] ,Logical AND of corresponding request and mask bit for channel 9" "Not masked,Masked"
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|
bitfld.long 0x00 8. " [8] ,Logical AND of corresponding request and mask bit for channel 8" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " [7] ,Logical AND of corresponding request and mask bit for channel 7" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x00 6. " [6] ,Logical AND of corresponding request and mask bit for channel 6" "Not masked,Masked"
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|
bitfld.long 0x00 5. " [5] ,Logical AND of corresponding request and mask bit for channel 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Logical AND of corresponding request and mask bit for channel 4" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x00 3. " [3] ,Logical AND of corresponding request and mask bit for channel 3" "Not masked,Masked"
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|
bitfld.long 0x00 2. " [2] ,Logical AND of corresponding request and mask bit for channel 2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Logical AND of corresponding request and mask bit for channel 1" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x00 0. " [0] ,Logical AND of corresponding request and mask bit for channel 0" "Not masked,Masked"
|
|
group.long 0x230++0x0B
|
|
line.long 0x00 "RANGE_INTR,Range Detect Interrupt Request Register"
|
|
eventfld.long 0x00 15. " RANGE_INTR[15] ,Range detect interrupt for channel 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " [14] ,Range detect interrupt for channel 14" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " [13] ,Range detect interrupt for channel 13" "No interrupt,Interrupt"
|
|
textline " "
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eventfld.long 0x00 12. " [12] ,Range detect interrupt for channel 12" "No interrupt,Interrupt"
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|
eventfld.long 0x00 11. " [11] ,Range detect interrupt for channel 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " [10] ,Range detect interrupt for channel 10" "No interrupt,Interrupt"
|
|
textline " "
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eventfld.long 0x00 9. " [9] ,Range detect interrupt for channel 9" "No interrupt,Interrupt"
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eventfld.long 0x00 8. " [8] ,Range detect interrupt for channel 8" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " [7] ,Range detect interrupt for channel 7" "No interrupt,Interrupt"
|
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textline " "
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eventfld.long 0x00 6. " [6] ,Range detect interrupt for channel 6" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " [5] ,Range detect interrupt for channel 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " [4] ,Range detect interrupt for channel 4" "No interrupt,Interrupt"
|
|
textline " "
|
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eventfld.long 0x00 3. " [3] ,Range detect interrupt for channel 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " [2] ,Range detect interrupt for channel 2" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " [1] ,Range detect interrupt for channel 1" "No interrupt,Interrupt"
|
|
textline " "
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eventfld.long 0x00 0. " [0] ,Range detect interrupt for channel 0" "No interrupt,Interrupt"
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|
line.long 0x04 "RANGE_INTR_SET,Range Detect Interrupt Set Request Register"
|
|
bitfld.long 0x04 15. " RANGE_SET[15] ,Set corresponding bit in interrupt request register for channel 15" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 14. " [14] ,Set corresponding bit in interrupt request register for channel 14" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 13. " [13] ,Set corresponding bit in interrupt request register for channel 13" "No interrupt,Interrupt"
|
|
textline " "
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bitfld.long 0x04 12. " [12] ,Set corresponding bit in interrupt request register for channel 12" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 11. " [11] ,Set corresponding bit in interrupt request register for channel 11" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " [10] ,Set corresponding bit in interrupt request register for channel 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 9. " [9] ,Set corresponding bit in interrupt request register for channel 9" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " [8] ,Set corresponding bit in interrupt request register for channel 8" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " [7] ,Set corresponding bit in interrupt request register for channel 7" "No interrupt,Interrupt"
|
|
textline " "
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bitfld.long 0x04 6. " [6] ,Set corresponding bit in interrupt request register for channel 6" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " [5] ,Set corresponding bit in interrupt request register for channel 5" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " [4] ,Set corresponding bit in interrupt request register for channel 4" "No interrupt,Interrupt"
|
|
textline " "
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|
bitfld.long 0x04 3. " [3] ,Set corresponding bit in interrupt request register for channel 3" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " [2] ,Set corresponding bit in interrupt request register for channel 2" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " [1] ,Set corresponding bit in interrupt request register for channel 1" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " [0] ,Set corresponding bit in interrupt request register for channel 0" "No interrupt,Interrupt"
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|
line.long 0x08 "RANGE_INTR_MASK,Range Detect Interrupt Mask Register"
|
|
bitfld.long 0x08 15. " RANGE_INTR_MASK[15] ,Mask bit for corresponding bit in interrupt request register for channel 15" "Not masked,Masked"
|
|
bitfld.long 0x08 14. " [14] ,Mask bit for corresponding bit in interrupt request register for channel 14" "Not masked,Masked"
|
|
bitfld.long 0x08 13. " [13] ,Mask bit for corresponding bit in interrupt request register for channel 13" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x08 12. " [12] ,Mask bit for corresponding bit in interrupt request register for channel 12" "Not masked,Masked"
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|
bitfld.long 0x08 11. " [11] ,Mask bit for corresponding bit in interrupt request register for channel 11" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " [10] ,Mask bit for corresponding bit in interrupt request register for channel 10" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x08 9. " [9] ,Mask bit for corresponding bit in interrupt request register for channel 9" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " [8] ,Mask bit for corresponding bit in interrupt request register for channel 8" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " [7] ,Mask bit for corresponding bit in interrupt request register for channel 7" "Not masked,Masked"
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|
textline " "
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bitfld.long 0x08 6. " [6] ,Mask bit for corresponding bit in interrupt request register for channel 6" "Not masked,Masked"
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|
bitfld.long 0x08 5. " [5] ,Mask bit for corresponding bit in interrupt request register for channel 5" "Not masked,Masked"
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bitfld.long 0x08 4. " [4] ,Mask bit for corresponding bit in interrupt request register for channel 4" "Not masked,Masked"
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textline " "
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bitfld.long 0x08 3. " [3] ,Mask bit for corresponding bit in interrupt request register for channel 3" "Not masked,Masked"
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bitfld.long 0x08 2. " [2] ,Mask bit for corresponding bit in interrupt request register for channel 2" "Not masked,Masked"
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bitfld.long 0x08 1. " [1] ,Mask bit for corresponding bit in interrupt request register for channel 1" "Not masked,Masked"
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|
textline " "
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bitfld.long 0x08 0. " [0] ,Mask bit for corresponding bit in interrupt request register for channel 0" "Not masked,Masked"
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|
rgroup.long 0x23C++0x07
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line.long 0x00 "RANGE_INTR_MASKED,Range Interrupt Masked Request Register"
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bitfld.long 0x00 15. " RANGE_MASKED[15] ,Logical AND of corresponding request and mask bit for channel 15" "Not masked,Masked"
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|
bitfld.long 0x00 14. " [14] ,Logical AND of corresponding request and mask bit for channel 14" "Not masked,Masked"
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|
bitfld.long 0x00 13. " [13] ,Logical AND of corresponding request and mask bit for channel 13" "Not masked,Masked"
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textline " "
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bitfld.long 0x00 12. " [12] ,Logical AND of corresponding request and mask bit for channel 12" "Not masked,Masked"
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bitfld.long 0x00 11. " [11] ,Logical AND of corresponding request and mask bit for channel 11" "Not masked,Masked"
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|
bitfld.long 0x00 10. " [10] ,Logical AND of corresponding request and mask bit for channel 10" "Not masked,Masked"
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|
textline " "
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bitfld.long 0x00 9. " [9] ,Logical AND of corresponding request and mask bit for channel 9" "Not masked,Masked"
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bitfld.long 0x00 8. " [8] ,Logical AND of corresponding request and mask bit for channel 8" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " [7] ,Logical AND of corresponding request and mask bit for channel 7" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x00 6. " [6] ,Logical AND of corresponding request and mask bit for channel 6" "Not masked,Masked"
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bitfld.long 0x00 5. " [5] ,Logical AND of corresponding request and mask bit for channel 5" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " [4] ,Logical AND of corresponding request and mask bit for channel 4" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x00 3. " [3] ,Logical AND of corresponding request and mask bit for channel 3" "Not masked,Masked"
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|
bitfld.long 0x00 2. " [2] ,Logical AND of corresponding request and mask bit for channel 2" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " [1] ,Logical AND of corresponding request and mask bit for channel 1" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x00 0. " [0] ,Logical AND of corresponding request and mask bit for channel 0" "Not masked,Masked"
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line.long 0x04 "INTR_CAUSE,Interrupt Cause Register"
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bitfld.long 0x04 31. " RANGE_MASKED_RED ,Reduction OR of all SAR_RANGE_INTR_MASKED bits" "Disabled,Enabled"
|
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bitfld.long 0x04 30. " SATURATE_MASKED_RED ,Reduction OR of all SAR_SATURATION_INTR_MASKED bits" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " INJ_COLLISION_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x04 6. " INJ_RANGE_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
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bitfld.long 0x04 5. " INJ_SATURATE_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
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bitfld.long 0x04 4. " INJ_EOC_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
|
textline " "
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bitfld.long 0x04 3. " DSI_COLLISION_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
|
bitfld.long 0x04 2. " FW_COLLISION_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
|
bitfld.long 0x04 1. " OVERFLOW_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
|
textline " "
|
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bitfld.long 0x04 0. " EOS_MASKED_MIR ,Mirror copy of corresponding bit in SAR_INTR_MASKED" "Not masked,Masked"
|
|
group.long 0x280++0x03
|
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line.long 0x00 "INJ_CHAN_CONFIG,Injection Channel Configuration Register"
|
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bitfld.long 0x00 31. " INJ_START_EN ,Set by firmware to enable the injection channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " INJ_TAILGATING ,Injection channel tailgating" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " INJ_SAMPLE_TIME_SEL ,Injection sample time select" "0,1,2,3"
|
|
textline " "
|
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bitfld.long 0x00 10. " INJ_AVG_EN ,Averaging enable from this channel" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " INJ_RESOLUTION ,RESOLUTION for this channel" "12B,SUBRES"
|
|
bitfld.long 0x00 8. " INJ_DIFFERENTIAL_EN ,Differential enable for this channel" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x00 4.--6. " INJ_PORT_ADDR ,Address of the port that contains the pin to be sampled by this channel" "SARMUX,CTB0,CTB1,CTB2,CTB3,,AROUTE_VIRT,SARMUX_VIRT"
|
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bitfld.long 0x00 0.--2. " INJ_PIN_ADDR ,Address of the pin to be sampled by this injection channel" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x290++0x03
|
|
line.long 0x00 "INJ_RESULT,Injection Channel Result Register"
|
|
bitfld.long 0x00 31. " INJ_EOC_INTR_MIR ,Mirror bit of corresponding bit in SAR_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 30. " INJ_RANGE_INTR_MIR ,Mirror bit of corresponding bit in SAR_INTR register" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " INJ_SATURATE_INTR_MIR ,Mirror bit of corresponding bit in SAR_INTR register" "No interrupt,Interrupt"
|
|
textline " "
|
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bitfld.long 0x00 28. " INJ_COLLISION_INTR_MIR ,Mirror bit of corresponding bit in SAR_INTR register" "No interrupt,Interrupt"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
textline " "
|
|
bitfld.long 0x00 27. " INJ_NEWVALUE ,The data in this register received a new value" "Not received,Received"
|
|
endif
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " INJ_RESULT ,16-bit SAR conversion result of the channel"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
if (((per.l(ad:0x403A0000+0x2A0))&0x80000000)==0x80000000)
|
|
rgroup.long 0x2A0++0x03
|
|
line.long 0x00 "STATUS,Current Status Of Internal SAR Registers"
|
|
bitfld.long 0x00 31. " BUSY ,If high then the SAR is busy with a conversion" "Idle,Busy"
|
|
bitfld.long 0x00 30. " SW_VREF_NEG ,The current switch status" "0,1"
|
|
bitfld.long 0x00 0.--4. " CUR_CHAN ,Current channel being sampled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
rgroup.long 0x2A0++0x03
|
|
line.long 0x00 "STATUS,Current Status Of Internal SAR Registers"
|
|
bitfld.long 0x00 31. " BUSY ,If high then the SAR is busy with a conversion" "Idle,Busy"
|
|
bitfld.long 0x00 30. " SW_VREF_NEG ,The current switch status" "0,1"
|
|
endif
|
|
rgroup.long 0x2A4++0x03
|
|
line.long 0x00 "AVG_STAT,Current Averaging Status"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CUR_AVG_CNT ,7-bit current value of the averaging counter"
|
|
bitfld.long 0x00 23. " INTRLV_BUSY ,If high then the SAR is in the middle of interleaved averaging spanning several scans" "Idle,Busy"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " CUR_AVG_ACCU ,20-bit current value of averaging accumulator"
|
|
endif
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "MUX_SWITCH0,SARMUX Firmware Switch Controls"
|
|
bitfld.long 0x00 29. " MUX_FW_P7_COREIO3 ,Firmware control switch between pin P7 and coreio3" "Open,Closed"
|
|
bitfld.long 0x00 28. " MUX_FW_P6_COREIO2 ,Firmware control switch between pin P6 and coreio2" "Open,Closed"
|
|
bitfld.long 0x00 27. " MUX_FW_P5_COREIO1 ,Firmware control switch between pin P5 and coreio1" "Open,Closed"
|
|
textline " "
|
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bitfld.long 0x00 26. " MUX_FW_P4_COREIO0 ,Firmware control switch between pin P4 and coreio0" "Open,Closed"
|
|
bitfld.long 0x00 25. " MUX_FW_SARBUS1_VMINUS ,Firmware control switch between sarbus1 and vminus" "Open,Closed"
|
|
bitfld.long 0x00 24. " MUX_FW_SARBUS0_VMINUS ,Firmware control switch between sarbus0 and vminus" "Open,Closed"
|
|
textline " "
|
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bitfld.long 0x00 23. " MUX_FW_SARBUS1_VPLUS ,Firmware control switch between sarbus1 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 22. " MUX_FW_SARBUS0_VPLUS ,Firmware control switch between sarbus0 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 21. " MUX_FW_AMUXBUSB_VMINUS ,Firmware control switch between amuxbusb and vminus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 20. " MUX_FW_AMUXBUSA_VMINUS ,Firmware control switch between amuxbusa and vminus" "Open,Closed"
|
|
bitfld.long 0x00 19. " MUX_FW_AMUXBUSB_VPLUS ,Firmware control switch between amuxbusb and vplus" "Open,Closed"
|
|
bitfld.long 0x00 18. " MUX_FW_AMUXBUSA_VPLUS ,Firmware control switch between amuxbusa and vplus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MUX_FW_TEMP_VPLUS ,Firmware control switch between temperature sensor and vplus also powers on the temperature sensor" "Open,Closed"
|
|
bitfld.long 0x00 16. " MUX_FW_VSSA_VMINUS ,Firmware control switch between vssa_kelvin and vminus" "Open,Closed"
|
|
bitfld.long 0x00 15. " MUX_FW_P7_VMINUS ,Firmware control switch between pin P7 and vminus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " MUX_FW_P6_VMINUS ,Firmware control switch betweeen pin P6 and vminus" "Open,Closed"
|
|
bitfld.long 0x00 13. " MUX_FW_P5_VMINUS ,Firmware control switch betweeen pin P5 and vminus" "Open,Closed"
|
|
bitfld.long 0x00 12. " MUX_FW_P4_VMINUS ,Firmware control switch betweeen pin P4 and vminus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MUX_FW_P3_VMINUS ,Firmware control switch betweeen pin P3 and vminus" "Open,Closed"
|
|
bitfld.long 0x00 10. " MUX_FW_P2_VMINUS ,Firmware control switch betweeen pin P2 and vminus" "Open,Closed"
|
|
bitfld.long 0x00 9. " MUX_FW_P1_VMINUS ,Firmware control switch betweeen pin P1 and vminus" "Open,Closed"
|
|
textline " "
|
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bitfld.long 0x00 8. " MUX_FW_P0_VMINUS ,Firmware control switch betweeen pin P0 and vminus" "Open,Closed"
|
|
bitfld.long 0x00 7. " MUX_FW_P7_VPLUS ,Firmware control switch betweeen pin P7 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 6. " MUX_FW_P6_VPLUS ,Firmware control switch betweeen pin P6 and vplus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " MUX_FW_P5_VPLUS ,Firmware control switch betweeen pin P5 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 4. " MUX_FW_P4_VPLUS ,Firmware control switch betweeen pin P4 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 3. " MUX_FW_P3_VPLUS ,Firmware control switch betweeen pin P3 and vplus" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MUX_FW_P2_VPLUS ,Firmware control switch betweeen pin P2 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 1. " MUX_FW_P1_VPLUS ,Firmware control switch betweeen pin P1 and vplus" "Open,Closed"
|
|
bitfld.long 0x00 0. " MUX_FW_P0_VPLUS ,Firmware control switch betweeen pin P0 and vplus" "Open,Closed"
|
|
line.long 0x04 "MUX_SWITCH_CLEAR0,SARMUX Firmware Switch Control Clear"
|
|
eventfld.long 0x04 29. " MUX_FW_P7_COREIO3 ,Firmware control switch between pin P7 and coreio3" "Not cleared,Cleared"
|
|
eventfld.long 0x04 28. " MUX_FW_P6_COREIO2 ,Firmware control switch between pin P6 and coreio2" "Not cleared,Cleared"
|
|
eventfld.long 0x04 27. " MUX_FW_P5_COREIO1 ,Firmware control switch between pin P5 and coreio1" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 26. " MUX_FW_P4_COREIO0 ,Firmware control switch between pin P4 and coreio0" "Not cleared,Cleared"
|
|
eventfld.long 0x04 25. " MUX_FW_SARBUS1_VMINUS ,Firmware control switch between sarbus1 and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 24. " MUX_FW_SARBUS0_VMINUS ,Firmware control switch between sarbus0 and vminus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 23. " MUX_FW_SARBUS1_VPLUS ,Firmware control switch between sarbus1 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 22. " MUX_FW_SARBUS0_VPLUS ,Firmware control switch between sarbus0 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 21. " MUX_FW_AMUXBUSB_VMINUS ,Firmware control switch between amuxbusb and vminus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 20. " MUX_FW_AMUXBUSA_VMINUS ,Firmware control switch between amuxbusa and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 19. " MUX_FW_AMUXBUSB_VPLUS ,Firmware control switch between amuxbusb and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 18. " MUX_FW_AMUXBUSA_VPLUS ,Firmware control switch between amuxbusa and vplus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 17. " MUX_FW_TEMP_VPLUS ,Firmware control switch between temperature sensor and vplus also powers on the temperature sensor" "Not cleared,Cleared"
|
|
eventfld.long 0x04 16. " MUX_FW_VSSA_VMINUS ,Firmware control switch between vssa_kelvin and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 15. " MUX_FW_P7_VMINUS ,Firmware control switch between pin P7 and vminus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 14. " MUX_FW_P6_VMINUS ,Firmware control switch betweeen pin P6 and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 13. " MUX_FW_P5_VMINUS ,Firmware control switch betweeen pin P5 and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 12. " MUX_FW_P4_VMINUS ,Firmware control switch betweeen pin P4 and vminus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 11. " MUX_FW_P3_VMINUS ,Firmware control switch betweeen pin P3 and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 10. " MUX_FW_P2_VMINUS ,Firmware control switch betweeen pin P2 and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 9. " MUX_FW_P1_VMINUS ,Firmware control switch betweeen pin P1 and vminus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 8. " MUX_FW_P0_VMINUS ,Firmware control switch betweeen pin P0 and vminus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 7. " MUX_FW_P7_VPLUS ,Firmware control switch betweeen pin P7 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 6. " MUX_FW_P6_VPLUS ,Firmware control switch betweeen pin P6 and vplus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 5. " MUX_FW_P5_VPLUS ,Firmware control switch betweeen pin P5 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 4. " MUX_FW_P4_VPLUS ,Firmware control switch betweeen pin P4 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 3. " MUX_FW_P3_VPLUS ,Firmware control switch betweeen pin P3 and vplus" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 2. " MUX_FW_P2_VPLUS ,Firmware control switch betweeen pin P2 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 1. " MUX_FW_P1_VPLUS ,Firmware control switch betweeen pin P1 and vplus" "Not cleared,Cleared"
|
|
eventfld.long 0x04 0. " MUX_FW_P0_VPLUS ,Firmware control switch betweeen pin P0 and vplus" "Not cleared,Cleared"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0x308++0x07
|
|
line.long 0x00 "MUX_SWITCH1,SARMUX Firmware Switch Controls"
|
|
bitfld.long 0x00 3. " MUX_FW_ADFT1_SARBUS1 ,Switch between adft1 signal and sarbus1 signal" "Open,Closed"
|
|
bitfld.long 0x00 2. " MUX_FW_ADFT0_SARBUS0 ,Switch between adft0 signal and sarbus0 signal" "Open,Closed"
|
|
bitfld.long 0x00 1. " MUX_FW_P5_DFT_INM ,Switch between P5 pin and dft_inm signal" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MUX_FW_P4_DFT_INP ,Switch between P4 pin and dft_inp signal" "Open,Closed"
|
|
line.long 0x04 "MUX_SWITCH_CLEAR1,SARMUX Firmware Switch Control Clear"
|
|
eventfld.long 0x04 3. " MUX_FW_ADFT1_SARBUS1 ,Switch between adft1 signal and sarbus1 signal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 2. " MUX_FW_ADFT0_SARBUS0 ,Switch between adft0 signal and sarbus0 signal" "Not cleared,Cleared"
|
|
eventfld.long 0x04 1. " MUX_FW_P5_DFT_INM ,Switch between P5 pin and dft_inm signal" "Not cleared,Cleared"
|
|
textline " "
|
|
eventfld.long 0x04 0. " MUX_FW_P4_DFT_INP ,Switch between P4 pin and dft_inp signal" "Not cleared,Cleared"
|
|
endif
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "MUX_SWITCH_HW_CTRL,SARMUX Switch Hardware Control"
|
|
bitfld.long 0x00 23. " MUX_HW_CTRL_SARBUS1 ,Hardware control masked by firmware setting for sarbus1 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 22. " MUX_HW_CTRL_SARBUS0 ,Hardware control masked by firmware setting for sarbus0 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 19. " MUX_HW_CTRL_AMUXBUSB ,Hardware control masked by firmware setting for amuxbusb switches" "Firmware,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MUX_HW_CTRL_AMUXBUSA ,Hardware control masked by firmware setting for amuxbusa switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 17. " MUX_HW_CTRL_TEMP ,Hardware control masked by firmware setting for temp switch" "Firmware,Hardware"
|
|
bitfld.long 0x00 16. " MUX_HW_CTRL_VSSA ,Hardware control masked by firmware setting for vssa switch" "Firmware,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MUX_HW_CTRL_P7 ,Hardware control masked by firmware setting for pin P7 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 6. " MUX_HW_CTRL_P6 ,Hardware control masked by firmware setting for pin P6 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 5. " MUX_HW_CTRL_P5 ,Hardware control masked by firmware setting for pin P5 switches" "Firmware,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MUX_HW_CTRL_P4 ,Hardware control masked by firmware setting for pin P4 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 3. " MUX_HW_CTRL_P3 ,Hardware control masked by firmware setting for pin P3 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 2. " MUX_HW_CTRL_P2 ,Hardware control masked by firmware setting for pin P2 switches" "Firmware,Hardware"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUX_HW_CTRL_P1 ,Hardware control masked by firmware setting for pin P1 switches" "Firmware,Hardware"
|
|
bitfld.long 0x00 0. " MUX_HW_CTRL_P0 ,Hardware control masked by firmware setting for pin P0 switches" "Firmware,Hardware"
|
|
rgroup.long 0x348++0x03
|
|
line.long 0x00 "MUX_SWITCH_STATUS,SARMUX Switch Status"
|
|
bitfld.long 0x00 25. " MUX_FW_SARBUS1_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 24. " MUX_FW_SARBUS0_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 23. " MUX_FW_SARBUS1_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MUX_FW_SARBUS0_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 21. " MUX_FW_AMUXBUSB_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 20. " MUX_FW_AMUXBUSA_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MUX_FW_AMUXBUSB_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 18. " MUX_FW_AMUXBUSA_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 17. " MUX_FW_TEMP_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MUX_FW_VSSA_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 15. " MUX_FW_P7_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 14. " MUX_FW_P6_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MUX_FW_P5_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 12. " MUX_FW_P4_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 11. " MUX_FW_P3_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MUX_FW_P2_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 9. " MUX_FW_P1_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 8. " MUX_FW_P0_VMINUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MUX_FW_P7_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 6. " MUX_FW_P6_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 5. " MUX_FW_P5_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MUX_FW_P4_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 3. " MUX_FW_P3_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 2. " MUX_FW_P2_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUX_FW_P1_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
bitfld.long 0x00 0. " MUX_FW_P0_VPLUS ,Switch status of corresponding bit in MUX_SWITCH0" "Open,Closed"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "PUMP_CTRL,Switch Pump Control"
|
|
bitfld.long 0x00 31. " ENABLED ,SAR pump output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CLOCK_SEL ,Clock select" "External,Internal"
|
|
group.long 0xF00++0x03
|
|
line.long 0x00 "ANA_TRIM,Analog Trim Register"
|
|
bitfld.long 0x00 3. " TRIMUNIT ,Attenuation cap trimming" "0,1"
|
|
bitfld.long 0x00 0.--2. " CAP_TRIM ,Attenuation cap trimming" "0,1,2,3,4,5,6,7"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.long 0xF04++0x03
|
|
line.long 0x00 "WOUNDING,SAR Wounding Register"
|
|
bitfld.long 0x00 0.--1. " WOUND_RESOLUTION ,Maximum SAR resolution allowed" "12bit,10bit,8bit,8bit"
|
|
endif
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Analog Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,SAR enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "SCB (Serial Communication Block)"
|
|
tree "SCB0"
|
|
base ad:0x40070000
|
|
if (((per.l(ad:0x40070000))&0x3000000)==0x0000000)
|
|
width 12.
|
|
if (((per.l(ad:0x40070000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40070000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40070000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40070000+0x60))&0xC0000000)==0xC0000000)
|
|
if (((per.l(ad:0x40070000))&0x100)==0x100)&&((((per.l(ad:0x40070000))&0x200)==0x000)||(((per.l(ad:0x40070000+0x60))&0x800)==0x800)||(((per.l(ad:0x40070000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40070000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40070000))&0x100)==0x000)&&(((per.l(ad:0x40070000))&0x200)==0x000)&&(((per.l(ad:0x40070000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40070000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40070000+0x60))&0xC0000000)==0x80000000)
|
|
if (((per.l(ad:0x40070000))&0x100)==0x100)&&((((per.l(ad:0x40070000))&0x200)==0x000)||(((per.l(ad:0x40070000+0x60))&0x800)==0x800)||(((per.l(ad:0x40070000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40070000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif (((per.l(ad:0x40070000))&0x100)==0x000)&&(((per.l(ad:0x40070000))&0x200)==0x000)&&(((per.l(ad:0x40070000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((per.l(ad:0x40070000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40070000+0x60))&0xC0000000)==0x40000000)
|
|
if (((per.l(ad:0x40070000))&0x100)==0x100)&&((((per.l(ad:0x40070000))&0x200)==0x000)||(((per.l(ad:0x40070000+0x60))&0x800)==0x800)||(((per.l(ad:0x40070000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40070000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40070000))&0x100)==0x000)&&(((per.l(ad:0x40070000))&0x200)==0x000)&&(((per.l(ad:0x40070000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40070000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40070000))&0x100)==0x100)&&((((per.l(ad:0x40070000))&0x200)==0x000)||(((per.l(ad:0x40070000+0x60))&0x800)==0x800)||(((per.l(ad:0x40070000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40070000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40070000))&0x100)==0x000)&&(((per.l(ad:0x40070000))&0x200)==0x000)&&(((per.l(ad:0x40070000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40070000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40070000))&0x200)==0x000)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "I2C_STATUS,I2C Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BASE_EZ_ADDR ,I2C slave base EZ address"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CURR_EZ_ADDR ,I2C slave current EZ address"
|
|
bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer"
|
|
textline " "
|
|
bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer"
|
|
bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy"
|
|
else
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "I2C_STATUS,I2C Status Register"
|
|
bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer"
|
|
textline " "
|
|
bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer"
|
|
bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy"
|
|
endif
|
|
if (((per.l(ad:0x40070000+0x60))&0x80000000)==0x80000000)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "I2C_M_CMD,I2C Master Command Register"
|
|
bitfld.long 0x00 4. " M_STOP ,Master transmit STOP" "Disabled,ENABLED"
|
|
bitfld.long 0x00 3. " M_NACK ,Master negative acknowledgement transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " M_ACK ,Master acknowledgement transmit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M_START_ON_IDLE ,Master START on idle" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " M_START ,Master transmit START" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "I2C_M_CMD,I2C Master Command Register"
|
|
endif
|
|
if (((per.l(ad:0x40070000+0x60))&0x40000000)==0x40000000)
|
|
if (((per.l(ad:0x40070000))&0x400)==0x400)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " S_ACK ,Slave acknowledgement transmit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "I2C_CFG,I2C Configuration Register"
|
|
bitfld.long 0x00 28.--29. " SDA_OUT_FILT_SEL ,Selection of cumulative 'i2c_sda_out' filter delay" "0 ns,50 ns,100 ns,150 ns"
|
|
bitfld.long 0x00 20.--21. " SDA_OUT_FILT2_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " SDA_OUT_FILT1_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SDA_OUT_FILT0_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3"
|
|
bitfld.long 0x00 12. " SCL_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns"
|
|
bitfld.long 0x00 8.--9. " SCL_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SDA_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns"
|
|
bitfld.long 0x00 0.--1. " SDA_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
|
|
width 0x0B
|
|
elif (((per.l(ad:0x40070000))&0x3000000)==0x1000000)
|
|
width 22.
|
|
if (((per.l(ad:0x40070000+0x20))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40070000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40070000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40070000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40070000+0x20))&0x3000000)==0x0000000)
|
|
if (((per.l(ad:0x40070000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.l(ad:0x40070000+0x20))&0x3000000)==0x2000000)
|
|
if (((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.l(ad:0x40070000+0x20))&0x3000000)==0x1000000)
|
|
if (((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40070000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40070000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40070000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40070000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40070000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40070000+0x20))&0x3000000)==0x0000000)
|
|
if (((per.l(ad:0x40070000+0x20))&0x8)==0x0)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
endif
|
|
elif (((per.l(ad:0x40070000+0x20))&0x3000000)==0x2000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
elif (((per.l(ad:0x40070000+0x20))&0x3000000)==0x1000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40070000))&0x200)==0x000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SPI_STATUS,SPI Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " BASE_EZ_ADDR ,SPI base EZ address"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " CURR_EZ_ADDR ,SPI current EZ address"
|
|
bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SPI_STATUS,SPI Status Register"
|
|
bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x40070000))&0x3000000)==0x2000000)
|
|
width 21.
|
|
if (((per.l(ad:0x40070000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40070000))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40070000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40070000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40070000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40070000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40070000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40070000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..."
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40070000))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40070000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40070000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40070000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40070000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40070000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40070000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "UART_CTRL,UART Control Register"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of UART operation" "UART_STD,UART_SMARTCARD,UART_IRDA,?..."
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
if (((per.l(ad:0x40070000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 5. " PARITY_ENABLED ,Parity generation enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 13. " SKIP_START ,Skips start bit detection for the first received data frame" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LIN_MODE ,Break detection and baud rate detection on the incoming data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PARITY_ENABLED ,Parity checking enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40070000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 8. " RETRY_ON_NACK ,Retransmitted when negative acknowledgement is received" "Not retransmitted,Retransmitted"
|
|
rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40070000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 6. " POLARITY ,Inverts incoming RX line signal" "Low,High"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "UART_RX_STATUS,UART Receiver Status Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " BR_COUNTER ,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "UART_FLOW_CTRL,UART Flow Control Register"
|
|
bitfld.long 0x00 25. " CTS_ENABLED ,Enable use of CTS input signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CTS_POLARITY ,Polarity of the CTS input signal" "Low,High"
|
|
bitfld.long 0x00 16. " RTS_POLARITY ,Polarity of the RTS output signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
else
|
|
width 18.
|
|
if (((per.l(ad:0x40070000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
endif
|
|
endif
|
|
textline " "
|
|
width 20.
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "TX_CTRL,Transmitter Control Register"
|
|
bitfld.long 0x00 8. " MSB_FIRST ,Least significant bit first or most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TX_FIFO_CTRL,Transmitter FIFO Control Register"
|
|
bitfld.long 0x04 17. " FREEZE ,Freeze will not advance TX FIFO read pointer" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CLEAR ,Transmitter FIFO and transmitter shift register cleared" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO Status Register"
|
|
bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " SR_VALID ,Indicates whether the TX shift registers holds a valid data frame" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " USED ,Amount of entries in the transmitter FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
wgroup.long 0x240++0x03
|
|
line.long 0x00 "TX_FIFO_WR,Transmitter FIFO Write Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,16-bit data frame written into the transmitter FIFO"
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "RX_CTRL,Receiver Control Register"
|
|
bitfld.long 0x00 9. " MEDIAN ,Median filter" "0,Digital 3 taps median filter"
|
|
bitfld.long 0x00 8. " MSB_FIRST ,Least significant bit first or most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "RX_FIFO_CTRL,Receiver FIFO Control Register"
|
|
bitfld.long 0x04 17. " FREEZE ,Freeze will not advance TX FIFO read pointer" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CLEAR ,Transmitter FIFO and transmitter shift register cleared" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO Status Register"
|
|
bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " SR_VALID ,Indicates whether the RX shift registers holds a valid data frame" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " USED ,Amount od enties in the receiver FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "RX_MATCH,Slave Address And Mask Register"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " MASK ,Slave device address mask"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Slave device address"
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "RX_FIFO_RD,Receiver FIFO Read Register"
|
|
in
|
|
hgroup.long 0x344++0x03
|
|
hide.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO Read Register"
|
|
in
|
|
hgroup.long 0x400++0x03
|
|
hide.long 0x00 "EZ_DATA0,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x404++0x03
|
|
hide.long 0x00 "EZ_DATA1,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x408++0x03
|
|
hide.long 0x00 "EZ_DATA2,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x40C++0x03
|
|
hide.long 0x00 "EZ_DATA3,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "EZ_DATA4,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "EZ_DATA5,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "EZ_DATA6,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "EZ_DATA7,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x00 "EZ_DATA8,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x424++0x03
|
|
hide.long 0x00 "EZ_DATA9,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x428++0x03
|
|
hide.long 0x00 "EZ_DATA10,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x42C++0x03
|
|
hide.long 0x00 "EZ_DATA11,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x430++0x03
|
|
hide.long 0x00 "EZ_DATA12,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x434++0x03
|
|
hide.long 0x00 "EZ_DATA13,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x438++0x03
|
|
hide.long 0x00 "EZ_DATA14,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x43C++0x03
|
|
hide.long 0x00 "EZ_DATA15,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x440++0x03
|
|
hide.long 0x00 "EZ_DATA16,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x444++0x03
|
|
hide.long 0x00 "EZ_DATA17,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x448++0x03
|
|
hide.long 0x00 "EZ_DATA18,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x44C++0x03
|
|
hide.long 0x00 "EZ_DATA19,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x450++0x03
|
|
hide.long 0x00 "EZ_DATA20,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x454++0x03
|
|
hide.long 0x00 "EZ_DATA21,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x458++0x03
|
|
hide.long 0x00 "EZ_DATA22,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x45C++0x03
|
|
hide.long 0x00 "EZ_DATA23,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x460++0x03
|
|
hide.long 0x00 "EZ_DATA24,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x464++0x03
|
|
hide.long 0x00 "EZ_DATA25,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x468++0x03
|
|
hide.long 0x00 "EZ_DATA26,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x46C++0x03
|
|
hide.long 0x00 "EZ_DATA27,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x470++0x03
|
|
hide.long 0x00 "EZ_DATA28,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x474++0x03
|
|
hide.long 0x00 "EZ_DATA29,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x478++0x03
|
|
hide.long 0x00 "EZ_DATA30,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x47C++0x03
|
|
hide.long 0x00 "EZ_DATA31,Memory Buffer Registers"
|
|
in
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "INTR_CAUSE,Active Clock Interrupt Signal Register"
|
|
bitfld.long 0x00 5. " SPI_EC ,Externally clocked SPI interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 4. " I2C_EC ,Externally clocked I2C interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RX ,Receiver interrupt active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX ,Transmitter interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S ,Slave interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 0. " M ,Master interrupt active" "Inactive,Active"
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register"
|
|
eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt"
|
|
group.long 0xE88++0x03
|
|
line.long 0x00 "INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xE8C++0x03
|
|
line.long 0x00 "INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xEC0++0x03
|
|
line.long 0x00 "INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register"
|
|
eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt"
|
|
group.long 0xEC8++0x03
|
|
line.long 0x00 "INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xECC++0x03
|
|
line.long 0x00 "INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF00++0x0B
|
|
line.long 0x00 "INTR_M,Master Interrupt Request Register"
|
|
eventfld.long 0x00 9. " SPI_DONE ,SPI master transfer done event" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " I2C_BUS_ERROR ,I2C master bus error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " I2C_STOP ,I2C master STOP" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " I2C_ACK ,I2C master acknowledgement" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " I2C_NACK ,I2C master negative acknowledgement" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " I2C_ARB_LOST ,I2C master lost arbitration" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_M_SET,Master Interrupt Set Request Register"
|
|
bitfld.long 0x04 9. " SPI_DONE ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " I2C_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I2C_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " I2C_ACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I2C_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I2C_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_M_MASK,Master Interrupt Mask Register"
|
|
bitfld.long 0x08 9. " SPI_DONE ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " I2C_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " I2C_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " I2C_ACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " I2C_NACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " I2C_ARB_LOST ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xF0C++0x03
|
|
line.long 0x00 "INTR_M_MASKED,Master Interrupt Masked Request Register"
|
|
bitfld.long 0x00 9. " SPI_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF40++0x0B
|
|
line.long 0x00 "INTR_S,Slave Interrupt Request Register"
|
|
eventfld.long 0x00 11. " SPI_BUS_ERROR ,SPI slave deselected at an unexpected time in the SPI transfer" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " SPI_EZ_STOP ,SPI slave deselected after any EZ SPI transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,SPI slave deselected after a write EZ SPI transfer occurred" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " I2C_BUS_ERROR ,I2C slave bus error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " I2C_GENERAL ,I2C slave general call address received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " I2C_ADDR_MATCH ,I2C slave matching address received" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " I2C_START ,I2C slave START received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " I2C_STOP ,I2C STOP event for I2C transfer intended for this slave" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " I2C_WRITE_STOP ,I2C STOP event for I2C write transfer intended for this slave" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " I2C_ACK ,I2C slave acknowledgement received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " I2C_NACK ,I2C slave negative acknowledgement received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " I2C_ARB_LOST ,I2C slave lost arbitration" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_S_SET,Slave Interrupt Set Request Register"
|
|
bitfld.long 0x04 11. " SPI_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " SPI_EZ_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " SPI_EZ_WRITE_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " I2C_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " I2C_GENERAL ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " I2C_ADDR_MATCH ,Set corresponding bit in interrupt request registe" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I2C_START ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I2C_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " I2C_WRITE_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " I2C_ACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I2C_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I2C_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_S_MASK,Slave Interrupt Mask Register"
|
|
bitfld.long 0x08 11. " SPI_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " SPI_EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " SPI_EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 8. " I2C_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " I2C_GENERAL ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " I2C_ADDR_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 5. " I2C_START ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " I2C_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " I2C_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " I2C_ACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " I2C_NACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " I2C_ARB_LOST ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xF4C++0x03
|
|
line.long 0x00 "INTR_S_MASKED,Slave Interrupt Masked Request Register"
|
|
bitfld.long 0x00 11. " SPI_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " SPI_EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " I2C_GENERAL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " I2C_ADDR_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I2C_START ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " I2C_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF80++0x0B
|
|
line.long 0x00 "INTR_TX,Transmitter Interrupt Request Register"
|
|
eventfld.long 0x00 10. " UART_ARB_LOST ,UART lost arbitration" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " UART_DONE ,UART transmitter done event" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " UART_NACK ,UART transmitter received a negative acknowledgement in smartcard mode" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " BLOCKED ,AHB-Lite write transfer can not get access to the EZ memory" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty TX FIFO" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full TX FIFO" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " EMPTY ,TX FIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " NOT_FULL ,TX FIFO is not full" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " TRIGGER ,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_TX_SET,Transmitter Interrupt Set Request Register"
|
|
bitfld.long 0x04 10. " UART_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " UART_DONE ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " UART_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " BLOCKED ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " UNDERFLOW ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " OVERFLOW ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " EMPTY ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " NOT_FULL ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " TIGGER ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_TX_MASK,Transmitter Interrupt Mask Register"
|
|
bitfld.long 0x08 10. " UART_ARB_LOST ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " UART_DONE ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " UART_NACK ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " BLOCKED ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " UNDERFLOW ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " OVERFLOW ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 4. " EMPTY ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " NOT_FULL ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TRIGGER ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
rgroup.long 0xF8C++0x03
|
|
line.long 0x00 "INTR_TX_MASKED,Transmitter Interrupt Masked Request Register"
|
|
bitfld.long 0x00 10. " UART_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " UART_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " UART_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " NOT_FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xFC0++0x0B
|
|
line.long 0x00 "INTR_RX,Receiver Interrupt Request Register"
|
|
eventfld.long 0x00 11. " BREAK_DETECT ,Break detection successful" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " BAUD_DETECT ,LIN baudrate detection is completed" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " PARITY_ERROR ,Parity error in received data frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " FRAME_ERROR ,Frame error in received data frame" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " BLOCKED ,AHB-Lite read transfer can not get access to the EZ memory" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty RX FIFO" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full RX FIFO" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " FULL ,RX FIFO is full" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " NOT_EMPTY ,RX FIFO is not empty" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TRIGGER ,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_RX_SET,Receiver Interrupt Set Request Register"
|
|
bitfld.long 0x04 11. " BREAK_DETECT ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " BAUD_DETECT ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " PARITY_ERROR ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " FRAME_ERROR ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " BLOCKED ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " UNDERFLOW ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OVERFLOW ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " FULL ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " NOT_EMPTY ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRIGGER ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_RX_MASK,Receiver Interrupt Mask Register"
|
|
bitfld.long 0x08 11. " BREAK_DETECT ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " BAUD_DETECT ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " PARITY_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 8. " FRAME_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " BLOCKED ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " UNDERFLOW ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OVERFLOW ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " FULL ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " NOT_EMPTY ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TRIGGER ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "INTR_RX_MASKED,Receiver Interrupt Masked Request Register"
|
|
bitfld.long 0x00 11. " BREAK_DETECT ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " BAUD_DETECT ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " PARITY_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FRAME_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " NOT_EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCB1"
|
|
base ad:0x40080000
|
|
if (((per.l(ad:0x40080000))&0x3000000)==0x0000000)
|
|
width 12.
|
|
if (((per.l(ad:0x40080000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40080000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40080000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40080000+0x60))&0xC0000000)==0xC0000000)
|
|
if (((per.l(ad:0x40080000))&0x100)==0x100)&&((((per.l(ad:0x40080000))&0x200)==0x000)||(((per.l(ad:0x40080000+0x60))&0x800)==0x800)||(((per.l(ad:0x40080000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40080000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40080000))&0x100)==0x000)&&(((per.l(ad:0x40080000))&0x200)==0x000)&&(((per.l(ad:0x40080000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40080000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40080000+0x60))&0xC0000000)==0x80000000)
|
|
if (((per.l(ad:0x40080000))&0x100)==0x100)&&((((per.l(ad:0x40080000))&0x200)==0x000)||(((per.l(ad:0x40080000+0x60))&0x800)==0x800)||(((per.l(ad:0x40080000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40080000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif (((per.l(ad:0x40080000))&0x100)==0x000)&&(((per.l(ad:0x40080000))&0x200)==0x000)&&(((per.l(ad:0x40080000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((per.l(ad:0x40080000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40080000+0x60))&0xC0000000)==0x40000000)
|
|
if (((per.l(ad:0x40080000))&0x100)==0x100)&&((((per.l(ad:0x40080000))&0x200)==0x000)||(((per.l(ad:0x40080000+0x60))&0x800)==0x800)||(((per.l(ad:0x40080000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40080000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40080000))&0x100)==0x000)&&(((per.l(ad:0x40080000))&0x200)==0x000)&&(((per.l(ad:0x40080000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40080000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40080000))&0x100)==0x100)&&((((per.l(ad:0x40080000))&0x200)==0x000)||(((per.l(ad:0x40080000+0x60))&0x800)==0x800)||(((per.l(ad:0x40080000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40080000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40080000))&0x100)==0x000)&&(((per.l(ad:0x40080000))&0x200)==0x000)&&(((per.l(ad:0x40080000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40080000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40080000))&0x200)==0x000)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "I2C_STATUS,I2C Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BASE_EZ_ADDR ,I2C slave base EZ address"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CURR_EZ_ADDR ,I2C slave current EZ address"
|
|
bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer"
|
|
textline " "
|
|
bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer"
|
|
bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy"
|
|
else
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "I2C_STATUS,I2C Status Register"
|
|
bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer"
|
|
textline " "
|
|
bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer"
|
|
bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy"
|
|
endif
|
|
if (((per.l(ad:0x40080000+0x60))&0x80000000)==0x80000000)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "I2C_M_CMD,I2C Master Command Register"
|
|
bitfld.long 0x00 4. " M_STOP ,Master transmit STOP" "Disabled,ENABLED"
|
|
bitfld.long 0x00 3. " M_NACK ,Master negative acknowledgement transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " M_ACK ,Master acknowledgement transmit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M_START_ON_IDLE ,Master START on idle" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " M_START ,Master transmit START" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "I2C_M_CMD,I2C Master Command Register"
|
|
endif
|
|
if (((per.l(ad:0x40080000+0x60))&0x40000000)==0x40000000)
|
|
if (((per.l(ad:0x40080000))&0x400)==0x400)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " S_ACK ,Slave acknowledgement transmit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "I2C_CFG,I2C Configuration Register"
|
|
bitfld.long 0x00 28.--29. " SDA_OUT_FILT_SEL ,Selection of cumulative 'i2c_sda_out' filter delay" "0 ns,50 ns,100 ns,150 ns"
|
|
bitfld.long 0x00 20.--21. " SDA_OUT_FILT2_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " SDA_OUT_FILT1_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SDA_OUT_FILT0_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3"
|
|
bitfld.long 0x00 12. " SCL_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns"
|
|
bitfld.long 0x00 8.--9. " SCL_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SDA_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns"
|
|
bitfld.long 0x00 0.--1. " SDA_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
|
|
width 0x0B
|
|
elif (((per.l(ad:0x40080000))&0x3000000)==0x1000000)
|
|
width 22.
|
|
if (((per.l(ad:0x40080000+0x20))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40080000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40080000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40080000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40080000+0x20))&0x3000000)==0x0000000)
|
|
if (((per.l(ad:0x40080000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.l(ad:0x40080000+0x20))&0x3000000)==0x2000000)
|
|
if (((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.l(ad:0x40080000+0x20))&0x3000000)==0x1000000)
|
|
if (((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40080000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40080000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40080000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40080000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40080000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40080000+0x20))&0x3000000)==0x0000000)
|
|
if (((per.l(ad:0x40080000+0x20))&0x8)==0x0)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
endif
|
|
elif (((per.l(ad:0x40080000+0x20))&0x3000000)==0x2000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
elif (((per.l(ad:0x40080000+0x20))&0x3000000)==0x1000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40080000))&0x200)==0x000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SPI_STATUS,SPI Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " BASE_EZ_ADDR ,SPI base EZ address"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " CURR_EZ_ADDR ,SPI current EZ address"
|
|
bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SPI_STATUS,SPI Status Register"
|
|
bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x40080000))&0x3000000)==0x2000000)
|
|
width 21.
|
|
if (((per.l(ad:0x40080000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40080000))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40080000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40080000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40080000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40080000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40080000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40080000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..."
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40080000))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40080000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40080000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40080000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40080000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40080000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40080000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "UART_CTRL,UART Control Register"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of UART operation" "UART_STD,UART_SMARTCARD,UART_IRDA,?..."
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
if (((per.l(ad:0x40080000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 5. " PARITY_ENABLED ,Parity generation enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 13. " SKIP_START ,Skips start bit detection for the first received data frame" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LIN_MODE ,Break detection and baud rate detection on the incoming data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PARITY_ENABLED ,Parity checking enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40080000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 8. " RETRY_ON_NACK ,Retransmitted when negative acknowledgement is received" "Not retransmitted,Retransmitted"
|
|
rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40080000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 6. " POLARITY ,Inverts incoming RX line signal" "Low,High"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "UART_RX_STATUS,UART Receiver Status Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " BR_COUNTER ,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "UART_FLOW_CTRL,UART Flow Control Register"
|
|
bitfld.long 0x00 25. " CTS_ENABLED ,Enable use of CTS input signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CTS_POLARITY ,Polarity of the CTS input signal" "Low,High"
|
|
bitfld.long 0x00 16. " RTS_POLARITY ,Polarity of the RTS output signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
else
|
|
width 18.
|
|
if (((per.l(ad:0x40080000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
endif
|
|
endif
|
|
textline " "
|
|
width 20.
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "TX_CTRL,Transmitter Control Register"
|
|
bitfld.long 0x00 8. " MSB_FIRST ,Least significant bit first or most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TX_FIFO_CTRL,Transmitter FIFO Control Register"
|
|
bitfld.long 0x04 17. " FREEZE ,Freeze will not advance TX FIFO read pointer" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CLEAR ,Transmitter FIFO and transmitter shift register cleared" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO Status Register"
|
|
bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " SR_VALID ,Indicates whether the TX shift registers holds a valid data frame" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " USED ,Amount of entries in the transmitter FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
wgroup.long 0x240++0x03
|
|
line.long 0x00 "TX_FIFO_WR,Transmitter FIFO Write Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,16-bit data frame written into the transmitter FIFO"
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "RX_CTRL,Receiver Control Register"
|
|
bitfld.long 0x00 9. " MEDIAN ,Median filter" "0,Digital 3 taps median filter"
|
|
bitfld.long 0x00 8. " MSB_FIRST ,Least significant bit first or most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "RX_FIFO_CTRL,Receiver FIFO Control Register"
|
|
bitfld.long 0x04 17. " FREEZE ,Freeze will not advance TX FIFO read pointer" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CLEAR ,Transmitter FIFO and transmitter shift register cleared" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO Status Register"
|
|
bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " SR_VALID ,Indicates whether the RX shift registers holds a valid data frame" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " USED ,Amount od enties in the receiver FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "RX_MATCH,Slave Address And Mask Register"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " MASK ,Slave device address mask"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Slave device address"
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "RX_FIFO_RD,Receiver FIFO Read Register"
|
|
in
|
|
hgroup.long 0x344++0x03
|
|
hide.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO Read Register"
|
|
in
|
|
hgroup.long 0x400++0x03
|
|
hide.long 0x00 "EZ_DATA0,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x404++0x03
|
|
hide.long 0x00 "EZ_DATA1,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x408++0x03
|
|
hide.long 0x00 "EZ_DATA2,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x40C++0x03
|
|
hide.long 0x00 "EZ_DATA3,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "EZ_DATA4,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "EZ_DATA5,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "EZ_DATA6,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "EZ_DATA7,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x00 "EZ_DATA8,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x424++0x03
|
|
hide.long 0x00 "EZ_DATA9,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x428++0x03
|
|
hide.long 0x00 "EZ_DATA10,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x42C++0x03
|
|
hide.long 0x00 "EZ_DATA11,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x430++0x03
|
|
hide.long 0x00 "EZ_DATA12,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x434++0x03
|
|
hide.long 0x00 "EZ_DATA13,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x438++0x03
|
|
hide.long 0x00 "EZ_DATA14,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x43C++0x03
|
|
hide.long 0x00 "EZ_DATA15,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x440++0x03
|
|
hide.long 0x00 "EZ_DATA16,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x444++0x03
|
|
hide.long 0x00 "EZ_DATA17,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x448++0x03
|
|
hide.long 0x00 "EZ_DATA18,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x44C++0x03
|
|
hide.long 0x00 "EZ_DATA19,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x450++0x03
|
|
hide.long 0x00 "EZ_DATA20,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x454++0x03
|
|
hide.long 0x00 "EZ_DATA21,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x458++0x03
|
|
hide.long 0x00 "EZ_DATA22,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x45C++0x03
|
|
hide.long 0x00 "EZ_DATA23,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x460++0x03
|
|
hide.long 0x00 "EZ_DATA24,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x464++0x03
|
|
hide.long 0x00 "EZ_DATA25,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x468++0x03
|
|
hide.long 0x00 "EZ_DATA26,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x46C++0x03
|
|
hide.long 0x00 "EZ_DATA27,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x470++0x03
|
|
hide.long 0x00 "EZ_DATA28,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x474++0x03
|
|
hide.long 0x00 "EZ_DATA29,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x478++0x03
|
|
hide.long 0x00 "EZ_DATA30,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x47C++0x03
|
|
hide.long 0x00 "EZ_DATA31,Memory Buffer Registers"
|
|
in
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "INTR_CAUSE,Active Clock Interrupt Signal Register"
|
|
bitfld.long 0x00 5. " SPI_EC ,Externally clocked SPI interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 4. " I2C_EC ,Externally clocked I2C interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RX ,Receiver interrupt active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX ,Transmitter interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S ,Slave interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 0. " M ,Master interrupt active" "Inactive,Active"
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register"
|
|
eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt"
|
|
group.long 0xE88++0x03
|
|
line.long 0x00 "INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xE8C++0x03
|
|
line.long 0x00 "INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xEC0++0x03
|
|
line.long 0x00 "INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register"
|
|
eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt"
|
|
group.long 0xEC8++0x03
|
|
line.long 0x00 "INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xECC++0x03
|
|
line.long 0x00 "INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF00++0x0B
|
|
line.long 0x00 "INTR_M,Master Interrupt Request Register"
|
|
eventfld.long 0x00 9. " SPI_DONE ,SPI master transfer done event" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " I2C_BUS_ERROR ,I2C master bus error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " I2C_STOP ,I2C master STOP" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " I2C_ACK ,I2C master acknowledgement" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " I2C_NACK ,I2C master negative acknowledgement" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " I2C_ARB_LOST ,I2C master lost arbitration" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_M_SET,Master Interrupt Set Request Register"
|
|
bitfld.long 0x04 9. " SPI_DONE ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " I2C_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I2C_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " I2C_ACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I2C_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I2C_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_M_MASK,Master Interrupt Mask Register"
|
|
bitfld.long 0x08 9. " SPI_DONE ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " I2C_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " I2C_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " I2C_ACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " I2C_NACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " I2C_ARB_LOST ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xF0C++0x03
|
|
line.long 0x00 "INTR_M_MASKED,Master Interrupt Masked Request Register"
|
|
bitfld.long 0x00 9. " SPI_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF40++0x0B
|
|
line.long 0x00 "INTR_S,Slave Interrupt Request Register"
|
|
eventfld.long 0x00 11. " SPI_BUS_ERROR ,SPI slave deselected at an unexpected time in the SPI transfer" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " SPI_EZ_STOP ,SPI slave deselected after any EZ SPI transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,SPI slave deselected after a write EZ SPI transfer occurred" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " I2C_BUS_ERROR ,I2C slave bus error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " I2C_GENERAL ,I2C slave general call address received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " I2C_ADDR_MATCH ,I2C slave matching address received" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " I2C_START ,I2C slave START received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " I2C_STOP ,I2C STOP event for I2C transfer intended for this slave" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " I2C_WRITE_STOP ,I2C STOP event for I2C write transfer intended for this slave" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " I2C_ACK ,I2C slave acknowledgement received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " I2C_NACK ,I2C slave negative acknowledgement received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " I2C_ARB_LOST ,I2C slave lost arbitration" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_S_SET,Slave Interrupt Set Request Register"
|
|
bitfld.long 0x04 11. " SPI_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " SPI_EZ_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " SPI_EZ_WRITE_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " I2C_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " I2C_GENERAL ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " I2C_ADDR_MATCH ,Set corresponding bit in interrupt request registe" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I2C_START ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I2C_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " I2C_WRITE_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " I2C_ACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I2C_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I2C_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_S_MASK,Slave Interrupt Mask Register"
|
|
bitfld.long 0x08 11. " SPI_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " SPI_EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " SPI_EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 8. " I2C_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " I2C_GENERAL ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " I2C_ADDR_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 5. " I2C_START ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " I2C_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " I2C_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " I2C_ACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " I2C_NACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " I2C_ARB_LOST ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xF4C++0x03
|
|
line.long 0x00 "INTR_S_MASKED,Slave Interrupt Masked Request Register"
|
|
bitfld.long 0x00 11. " SPI_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " SPI_EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " I2C_GENERAL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " I2C_ADDR_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I2C_START ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " I2C_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF80++0x0B
|
|
line.long 0x00 "INTR_TX,Transmitter Interrupt Request Register"
|
|
eventfld.long 0x00 10. " UART_ARB_LOST ,UART lost arbitration" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " UART_DONE ,UART transmitter done event" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " UART_NACK ,UART transmitter received a negative acknowledgement in smartcard mode" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " BLOCKED ,AHB-Lite write transfer can not get access to the EZ memory" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty TX FIFO" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full TX FIFO" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " EMPTY ,TX FIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " NOT_FULL ,TX FIFO is not full" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " TRIGGER ,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_TX_SET,Transmitter Interrupt Set Request Register"
|
|
bitfld.long 0x04 10. " UART_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " UART_DONE ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " UART_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " BLOCKED ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " UNDERFLOW ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " OVERFLOW ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " EMPTY ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " NOT_FULL ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " TIGGER ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_TX_MASK,Transmitter Interrupt Mask Register"
|
|
bitfld.long 0x08 10. " UART_ARB_LOST ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " UART_DONE ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " UART_NACK ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " BLOCKED ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " UNDERFLOW ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " OVERFLOW ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 4. " EMPTY ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " NOT_FULL ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TRIGGER ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
rgroup.long 0xF8C++0x03
|
|
line.long 0x00 "INTR_TX_MASKED,Transmitter Interrupt Masked Request Register"
|
|
bitfld.long 0x00 10. " UART_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " UART_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " UART_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " NOT_FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xFC0++0x0B
|
|
line.long 0x00 "INTR_RX,Receiver Interrupt Request Register"
|
|
eventfld.long 0x00 11. " BREAK_DETECT ,Break detection successful" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " BAUD_DETECT ,LIN baudrate detection is completed" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " PARITY_ERROR ,Parity error in received data frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " FRAME_ERROR ,Frame error in received data frame" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " BLOCKED ,AHB-Lite read transfer can not get access to the EZ memory" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty RX FIFO" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full RX FIFO" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " FULL ,RX FIFO is full" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " NOT_EMPTY ,RX FIFO is not empty" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TRIGGER ,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_RX_SET,Receiver Interrupt Set Request Register"
|
|
bitfld.long 0x04 11. " BREAK_DETECT ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " BAUD_DETECT ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " PARITY_ERROR ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " FRAME_ERROR ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " BLOCKED ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " UNDERFLOW ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OVERFLOW ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " FULL ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " NOT_EMPTY ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRIGGER ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_RX_MASK,Receiver Interrupt Mask Register"
|
|
bitfld.long 0x08 11. " BREAK_DETECT ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " BAUD_DETECT ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " PARITY_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 8. " FRAME_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " BLOCKED ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " UNDERFLOW ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OVERFLOW ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " FULL ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " NOT_EMPTY ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TRIGGER ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "INTR_RX_MASKED,Receiver Interrupt Masked Request Register"
|
|
bitfld.long 0x00 11. " BREAK_DETECT ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " BAUD_DETECT ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " PARITY_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FRAME_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " NOT_EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
width 0x0B
|
|
tree.end
|
|
sif (!cpuis("CY8C4A24*"))
|
|
tree "SCB2"
|
|
base ad:0x40090000
|
|
if (((per.l(ad:0x40090000))&0x3000000)==0x0000000)
|
|
width 12.
|
|
if (((per.l(ad:0x40090000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40090000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40090000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40090000+0x60))&0xC0000000)==0xC0000000)
|
|
if (((per.l(ad:0x40090000))&0x100)==0x100)&&((((per.l(ad:0x40090000))&0x200)==0x000)||(((per.l(ad:0x40090000+0x60))&0x800)==0x800)||(((per.l(ad:0x40090000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40090000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40090000))&0x100)==0x000)&&(((per.l(ad:0x40090000))&0x200)==0x000)&&(((per.l(ad:0x40090000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40090000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40090000+0x60))&0xC0000000)==0x80000000)
|
|
if (((per.l(ad:0x40090000))&0x100)==0x100)&&((((per.l(ad:0x40090000))&0x200)==0x000)||(((per.l(ad:0x40090000+0x60))&0x800)==0x800)||(((per.l(ad:0x40090000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40090000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
elif (((per.l(ad:0x40090000))&0x100)==0x000)&&(((per.l(ad:0x40090000))&0x200)==0x000)&&(((per.l(ad:0x40090000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
if (((per.l(ad:0x40090000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
elif (((per.l(ad:0x40090000+0x60))&0xC0000000)==0x40000000)
|
|
if (((per.l(ad:0x40090000))&0x100)==0x100)&&((((per.l(ad:0x40090000))&0x200)==0x000)||(((per.l(ad:0x40090000+0x60))&0x800)==0x800)||(((per.l(ad:0x40090000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40090000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40090000))&0x100)==0x000)&&(((per.l(ad:0x40090000))&0x200)==0x000)&&(((per.l(ad:0x40090000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40090000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40090000))&0x100)==0x100)&&((((per.l(ad:0x40090000))&0x200)==0x000)||(((per.l(ad:0x40090000+0x60))&0x800)==0x800)||(((per.l(ad:0x40090000))&0x400)==0x400))
|
|
if (((per.l(ad:0x40090000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
elif (((per.l(ad:0x40090000))&0x100)==0x000)&&(((per.l(ad:0x40090000))&0x200)==0x000)&&(((per.l(ad:0x40090000))&0x400)==0x000)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
if (((per.l(ad:0x40090000))&0x400)==0x400)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "I2C_CTRL,I2C Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK"
|
|
bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready"
|
|
bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored"
|
|
bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready"
|
|
textline " "
|
|
bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40090000))&0x200)==0x000)
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "I2C_STATUS,I2C Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " BASE_EZ_ADDR ,I2C slave base EZ address"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CURR_EZ_ADDR ,I2C slave current EZ address"
|
|
bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer"
|
|
textline " "
|
|
bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer"
|
|
bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy"
|
|
else
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "I2C_STATUS,I2C Status Register"
|
|
bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer"
|
|
textline " "
|
|
bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer"
|
|
bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy"
|
|
endif
|
|
if (((per.l(ad:0x40090000+0x60))&0x80000000)==0x80000000)
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "I2C_M_CMD,I2C Master Command Register"
|
|
bitfld.long 0x00 4. " M_STOP ,Master transmit STOP" "Disabled,ENABLED"
|
|
bitfld.long 0x00 3. " M_NACK ,Master negative acknowledgement transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " M_ACK ,Master acknowledgement transmit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " M_START_ON_IDLE ,Master START on idle" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " M_START ,Master transmit START" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x68++0x03
|
|
hide.long 0x00 "I2C_M_CMD,I2C Master Command Register"
|
|
endif
|
|
if (((per.l(ad:0x40090000+0x60))&0x40000000)==0x40000000)
|
|
if (((per.l(ad:0x40090000))&0x400)==0x400)
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " S_ACK ,Slave acknowledgement transmit" "Disabled,Enabled"
|
|
else
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
hgroup.long 0x6C++0x03
|
|
hide.long 0x00 "I2C_S_CMD,I2C Slave Command Register"
|
|
endif
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "I2C_CFG,I2C Configuration Register"
|
|
bitfld.long 0x00 28.--29. " SDA_OUT_FILT_SEL ,Selection of cumulative 'i2c_sda_out' filter delay" "0 ns,50 ns,100 ns,150 ns"
|
|
bitfld.long 0x00 20.--21. " SDA_OUT_FILT2_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3"
|
|
bitfld.long 0x00 18.--19. " SDA_OUT_FILT1_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SDA_OUT_FILT0_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3"
|
|
bitfld.long 0x00 12. " SCL_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns"
|
|
bitfld.long 0x00 8.--9. " SCL_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SDA_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns"
|
|
bitfld.long 0x00 0.--1. " SDA_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3"
|
|
width 0x0B
|
|
elif (((per.l(ad:0x40090000))&0x3000000)==0x1000000)
|
|
width 22.
|
|
if (((per.l(ad:0x40090000+0x20))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40090000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40090000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40090000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40090000+0x20))&0x3000000)==0x0000000)
|
|
if (((per.l(ad:0x40090000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.l(ad:0x40090000+0x20))&0x3000000)==0x2000000)
|
|
if (((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
elif (((per.l(ad:0x40090000+0x20))&0x3000000)==0x1000000)
|
|
if (((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides"
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x0000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x4000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0x8000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40090000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40090000+0x20))&0xC000000)==0xC000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI"
|
|
bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High"
|
|
bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40090000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40090000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40090000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
if (((per.l(ad:0x40090000+0x20))&0x3000000)==0x0000000)
|
|
if (((per.l(ad:0x40090000+0x20))&0x8)==0x0)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1"
|
|
bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge"
|
|
endif
|
|
elif (((per.l(ad:0x40090000+0x20))&0x3000000)==0x2000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
elif (((per.l(ad:0x40090000+0x20))&0x3000000)==0x1000000)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SPI_CTRL,SPI Control Register"
|
|
bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..."
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40090000))&0x200)==0x000)
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SPI_STATUS,SPI Status Register"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " BASE_EZ_ADDR ,SPI base EZ address"
|
|
hexmask.long.byte 0x00 8.--15. 0x01 " CURR_EZ_ADDR ,SPI current EZ address"
|
|
bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy"
|
|
else
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SPI_STATUS,SPI Status Register"
|
|
bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy"
|
|
endif
|
|
width 0x0B
|
|
elif (((per.l(ad:0x40090000))&0x3000000)==0x2000000)
|
|
width 21.
|
|
if (((per.l(ad:0x40090000))&0x200)==0x200)
|
|
if (((per.l(ad:0x40090000))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40090000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40090000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40090000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40090000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40090000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40090000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..."
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40090000))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40090000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40090000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40090000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..."
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40090000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40090000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.l(ad:0x40090000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted"
|
|
bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit"
|
|
bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked"
|
|
bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..."
|
|
endif
|
|
endif
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "STATUS,Generic Status Register"
|
|
bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "UART_CTRL,UART Control Register"
|
|
bitfld.long 0x00 24.--25. " MODE ,Submode of UART operation" "UART_STD,UART_SMARTCARD,UART_IRDA,?..."
|
|
bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1"
|
|
if (((per.l(ad:0x40090000+0x40))&0x3000000)==0x0000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 5. " PARITY_ENABLED ,Parity generation enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 13. " SKIP_START ,Skips start bit detection for the first received data frame" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LIN_MODE ,Break detection and baud rate detection on the incoming data" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 5. " PARITY_ENABLED ,Parity checking enabled" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40090000+0x40))&0x3000000)==0x1000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 8. " RETRY_ON_NACK ,Retransmitted when negative acknowledgement is received" "Not retransmitted,Retransmitted"
|
|
rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l(ad:0x40090000+0x40))&0x3000000)==0x2000000)
|
|
group.long 0x44++0x07
|
|
line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register"
|
|
bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register"
|
|
bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped"
|
|
textline " "
|
|
bitfld.long 0x04 6. " POLARITY ,Inverts incoming RX line signal" "Low,High"
|
|
bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "UART_RX_STATUS,UART Receiver Status Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " BR_COUNTER ,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "UART_FLOW_CTRL,UART Flow Control Register"
|
|
bitfld.long 0x00 25. " CTS_ENABLED ,Enable use of CTS input signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " CTS_POLARITY ,Polarity of the CTS input signal" "Low,High"
|
|
bitfld.long 0x00 16. " RTS_POLARITY ,Polarity of the RTS output signal" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
width 0x0B
|
|
else
|
|
width 18.
|
|
if (((per.l(ad:0x40090000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,Generic Control Register"
|
|
bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..."
|
|
endif
|
|
endif
|
|
textline " "
|
|
width 20.
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "TX_CTRL,Transmitter Control Register"
|
|
bitfld.long 0x00 8. " MSB_FIRST ,Least significant bit first or most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "TX_FIFO_CTRL,Transmitter FIFO Control Register"
|
|
bitfld.long 0x04 17. " FREEZE ,Freeze will not advance TX FIFO read pointer" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CLEAR ,Transmitter FIFO and transmitter shift register cleared" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO Status Register"
|
|
bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " SR_VALID ,Indicates whether the TX shift registers holds a valid data frame" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " USED ,Amount of entries in the transmitter FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
wgroup.long 0x240++0x03
|
|
line.long 0x00 "TX_FIFO_WR,Transmitter FIFO Write Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " DATA ,16-bit data frame written into the transmitter FIFO"
|
|
group.long 0x300++0x07
|
|
line.long 0x00 "RX_CTRL,Receiver Control Register"
|
|
bitfld.long 0x00 9. " MEDIAN ,Median filter" "0,Digital 3 taps median filter"
|
|
bitfld.long 0x00 8. " MSB_FIRST ,Least significant bit first or most significant bit first" "LSB,MSB"
|
|
bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "RX_FIFO_CTRL,Receiver FIFO Control Register"
|
|
bitfld.long 0x04 17. " FREEZE ,Freeze will not advance TX FIFO read pointer" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " CLEAR ,Transmitter FIFO and transmitter shift register cleared" "Not cleared,Cleared"
|
|
bitfld.long 0x04 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO Status Register"
|
|
bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. " SR_VALID ,Indicates whether the RX shift registers holds a valid data frame" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " USED ,Amount od enties in the receiver FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "RX_MATCH,Slave Address And Mask Register"
|
|
hexmask.long.byte 0x00 16.--23. 0x01 " MASK ,Slave device address mask"
|
|
hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Slave device address"
|
|
hgroup.long 0x340++0x03
|
|
hide.long 0x00 "RX_FIFO_RD,Receiver FIFO Read Register"
|
|
in
|
|
hgroup.long 0x344++0x03
|
|
hide.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO Read Register"
|
|
in
|
|
hgroup.long 0x400++0x03
|
|
hide.long 0x00 "EZ_DATA0,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x404++0x03
|
|
hide.long 0x00 "EZ_DATA1,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x408++0x03
|
|
hide.long 0x00 "EZ_DATA2,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x40C++0x03
|
|
hide.long 0x00 "EZ_DATA3,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x410++0x03
|
|
hide.long 0x00 "EZ_DATA4,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x414++0x03
|
|
hide.long 0x00 "EZ_DATA5,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x418++0x03
|
|
hide.long 0x00 "EZ_DATA6,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x41C++0x03
|
|
hide.long 0x00 "EZ_DATA7,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x420++0x03
|
|
hide.long 0x00 "EZ_DATA8,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x424++0x03
|
|
hide.long 0x00 "EZ_DATA9,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x428++0x03
|
|
hide.long 0x00 "EZ_DATA10,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x42C++0x03
|
|
hide.long 0x00 "EZ_DATA11,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x430++0x03
|
|
hide.long 0x00 "EZ_DATA12,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x434++0x03
|
|
hide.long 0x00 "EZ_DATA13,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x438++0x03
|
|
hide.long 0x00 "EZ_DATA14,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x43C++0x03
|
|
hide.long 0x00 "EZ_DATA15,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x440++0x03
|
|
hide.long 0x00 "EZ_DATA16,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x444++0x03
|
|
hide.long 0x00 "EZ_DATA17,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x448++0x03
|
|
hide.long 0x00 "EZ_DATA18,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x44C++0x03
|
|
hide.long 0x00 "EZ_DATA19,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x450++0x03
|
|
hide.long 0x00 "EZ_DATA20,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x454++0x03
|
|
hide.long 0x00 "EZ_DATA21,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x458++0x03
|
|
hide.long 0x00 "EZ_DATA22,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x45C++0x03
|
|
hide.long 0x00 "EZ_DATA23,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x460++0x03
|
|
hide.long 0x00 "EZ_DATA24,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x464++0x03
|
|
hide.long 0x00 "EZ_DATA25,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x468++0x03
|
|
hide.long 0x00 "EZ_DATA26,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x46C++0x03
|
|
hide.long 0x00 "EZ_DATA27,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x470++0x03
|
|
hide.long 0x00 "EZ_DATA28,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x474++0x03
|
|
hide.long 0x00 "EZ_DATA29,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x478++0x03
|
|
hide.long 0x00 "EZ_DATA30,Memory Buffer Registers"
|
|
in
|
|
hgroup.long 0x47C++0x03
|
|
hide.long 0x00 "EZ_DATA31,Memory Buffer Registers"
|
|
in
|
|
rgroup.long 0xE00++0x03
|
|
line.long 0x00 "INTR_CAUSE,Active Clock Interrupt Signal Register"
|
|
bitfld.long 0x00 5. " SPI_EC ,Externally clocked SPI interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 4. " I2C_EC ,Externally clocked I2C interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 3. " RX ,Receiver interrupt active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TX ,Transmitter interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 1. " S ,Slave interrupt active" "Inactive,Active"
|
|
bitfld.long 0x00 0. " M ,Master interrupt active" "Inactive,Active"
|
|
group.long 0xE80++0x03
|
|
line.long 0x00 "INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register"
|
|
eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt"
|
|
group.long 0xE88++0x03
|
|
line.long 0x00 "INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xE8C++0x03
|
|
line.long 0x00 "INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xEC0++0x03
|
|
line.long 0x00 "INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register"
|
|
eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt"
|
|
group.long 0xEC8++0x03
|
|
line.long 0x00 "INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xECC++0x03
|
|
line.long 0x00 "INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register"
|
|
bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF00++0x0B
|
|
line.long 0x00 "INTR_M,Master Interrupt Request Register"
|
|
eventfld.long 0x00 9. " SPI_DONE ,SPI master transfer done event" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " I2C_BUS_ERROR ,I2C master bus error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " I2C_STOP ,I2C master STOP" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " I2C_ACK ,I2C master acknowledgement" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " I2C_NACK ,I2C master negative acknowledgement" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " I2C_ARB_LOST ,I2C master lost arbitration" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_M_SET,Master Interrupt Set Request Register"
|
|
bitfld.long 0x04 9. " SPI_DONE ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " I2C_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I2C_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " I2C_ACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I2C_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I2C_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_M_MASK,Master Interrupt Mask Register"
|
|
bitfld.long 0x08 9. " SPI_DONE ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " I2C_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " I2C_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " I2C_ACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " I2C_NACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " I2C_ARB_LOST ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xF0C++0x03
|
|
line.long 0x00 "INTR_M_MASKED,Master Interrupt Masked Request Register"
|
|
bitfld.long 0x00 9. " SPI_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF40++0x0B
|
|
line.long 0x00 "INTR_S,Slave Interrupt Request Register"
|
|
eventfld.long 0x00 11. " SPI_BUS_ERROR ,SPI slave deselected at an unexpected time in the SPI transfer" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " SPI_EZ_STOP ,SPI slave deselected after any EZ SPI transfer occurred" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,SPI slave deselected after a write EZ SPI transfer occurred" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " I2C_BUS_ERROR ,I2C slave bus error" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " I2C_GENERAL ,I2C slave general call address received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " I2C_ADDR_MATCH ,I2C slave matching address received" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " I2C_START ,I2C slave START received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " I2C_STOP ,I2C STOP event for I2C transfer intended for this slave" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " I2C_WRITE_STOP ,I2C STOP event for I2C write transfer intended for this slave" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " I2C_ACK ,I2C slave acknowledgement received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " I2C_NACK ,I2C slave negative acknowledgement received" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " I2C_ARB_LOST ,I2C slave lost arbitration" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_S_SET,Slave Interrupt Set Request Register"
|
|
bitfld.long 0x04 11. " SPI_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " SPI_EZ_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " SPI_EZ_WRITE_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " I2C_BUS_ERROR ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " I2C_GENERAL ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " I2C_ADDR_MATCH ,Set corresponding bit in interrupt request registe" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " I2C_START ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " I2C_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " I2C_WRITE_STOP ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 2. " I2C_ACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " I2C_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " I2C_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_S_MASK,Slave Interrupt Mask Register"
|
|
bitfld.long 0x08 11. " SPI_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " SPI_EZ_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " SPI_EZ_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 8. " I2C_BUS_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " I2C_GENERAL ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " I2C_ADDR_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 5. " I2C_START ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 4. " I2C_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " I2C_WRITE_STOP ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 2. " I2C_ACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " I2C_NACK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " I2C_ARB_LOST ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xF4C++0x03
|
|
line.long 0x00 "INTR_S_MASKED,Slave Interrupt Masked Request Register"
|
|
bitfld.long 0x00 11. " SPI_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " SPI_EZ_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " I2C_GENERAL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " I2C_ADDR_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I2C_START ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " I2C_WRITE_STOP ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xF80++0x0B
|
|
line.long 0x00 "INTR_TX,Transmitter Interrupt Request Register"
|
|
eventfld.long 0x00 10. " UART_ARB_LOST ,UART lost arbitration" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " UART_DONE ,UART transmitter done event" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " UART_NACK ,UART transmitter received a negative acknowledgement in smartcard mode" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " BLOCKED ,AHB-Lite write transfer can not get access to the EZ memory" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty TX FIFO" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full TX FIFO" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " EMPTY ,TX FIFO is empty" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " NOT_FULL ,TX FIFO is not full" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " TRIGGER ,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_TX_SET,Transmitter Interrupt Set Request Register"
|
|
bitfld.long 0x04 10. " UART_ARB_LOST ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " UART_DONE ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 8. " UART_NACK ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 7. " BLOCKED ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " UNDERFLOW ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 5. " OVERFLOW ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 4. " EMPTY ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " NOT_FULL ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " TIGGER ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_TX_MASK,Transmitter Interrupt Mask Register"
|
|
bitfld.long 0x08 10. " UART_ARB_LOST ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " UART_DONE ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 8. " UART_NACK ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 7. " BLOCKED ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " UNDERFLOW ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 5. " OVERFLOW ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 4. " EMPTY ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 1. " NOT_FULL ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " TRIGGER ,Mask bit for corresponding bit in interr request register" "Not masked,Masked"
|
|
rgroup.long 0xF8C++0x03
|
|
line.long 0x00 "INTR_TX_MASKED,Transmitter Interrupt Masked Request Register"
|
|
bitfld.long 0x00 10. " UART_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " UART_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " UART_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 1. " NOT_FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
group.long 0xFC0++0x0B
|
|
line.long 0x00 "INTR_RX,Receiver Interrupt Request Register"
|
|
eventfld.long 0x00 11. " BREAK_DETECT ,Break detection successful" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " BAUD_DETECT ,LIN baudrate detection is completed" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " PARITY_ERROR ,Parity error in received data frame" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " FRAME_ERROR ,Frame error in received data frame" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " BLOCKED ,AHB-Lite read transfer can not get access to the EZ memory" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty RX FIFO" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full RX FIFO" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " FULL ,RX FIFO is full" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " NOT_EMPTY ,RX FIFO is not empty" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TRIGGER ,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_RX_SET,Receiver Interrupt Set Request Register"
|
|
bitfld.long 0x04 11. " BREAK_DETECT ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 10. " BAUD_DETECT ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 9. " PARITY_ERROR ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 8. " FRAME_ERROR ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7. " BLOCKED ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 6. " UNDERFLOW ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 5. " OVERFLOW ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 3. " FULL ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " NOT_EMPTY ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TRIGGER ,Set corresponding bit in interrupt status register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_RX_MASK,Receiver Interrupt Mask Register"
|
|
bitfld.long 0x08 11. " BREAK_DETECT ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 10. " BAUD_DETECT ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 9. " PARITY_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 8. " FRAME_ERROR ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 7. " BLOCKED ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 6. " UNDERFLOW ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 5. " OVERFLOW ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 3. " FULL ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " NOT_EMPTY ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 0. " TRIGGER ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "INTR_RX_MASKED,Receiver Interrupt Masked Request Register"
|
|
bitfld.long 0x00 11. " BREAK_DETECT ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 10. " BAUD_DETECT ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 9. " PARITY_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " FRAME_ERROR ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 3. " FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " NOT_EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "SFLASH (Supervisory Flash)"
|
|
base ad:0x0FFFF000
|
|
width 32.
|
|
group.byte 0x0++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW0,Per Page Write Protection"
|
|
group.byte 0x1++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW1,Per Page Write Protection"
|
|
group.byte 0x2++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW2,Per Page Write Protection"
|
|
group.byte 0x3++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW3,Per Page Write Protection"
|
|
group.byte 0x4++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW4,Per Page Write Protection"
|
|
group.byte 0x5++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW5,Per Page Write Protection"
|
|
group.byte 0x6++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW6,Per Page Write Protection"
|
|
group.byte 0x7++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW7,Per Page Write Protection"
|
|
group.byte 0x8++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW8,Per Page Write Protection"
|
|
group.byte 0x9++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW9,Per Page Write Protection"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW10,Per Page Write Protection"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW11,Per Page Write Protection"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW12,Per Page Write Protection"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW13,Per Page Write Protection"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW14,Per Page Write Protection"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW15,Per Page Write Protection"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW16,Per Page Write Protection"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW17,Per Page Write Protection"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW18,Per Page Write Protection"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW19,Per Page Write Protection"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW20,Per Page Write Protection"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW21,Per Page Write Protection"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW22,Per Page Write Protection"
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW23,Per Page Write Protection"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW24,Per Page Write Protection"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW25,Per Page Write Protection"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW26,Per Page Write Protection"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW27,Per Page Write Protection"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW28,Per Page Write Protection"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW29,Per Page Write Protection"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW30,Per Page Write Protection"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW31,Per Page Write Protection"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW32,Per Page Write Protection"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW33,Per Page Write Protection"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW34,Per Page Write Protection"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW35,Per Page Write Protection"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW36,Per Page Write Protection"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW37,Per Page Write Protection"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW38,Per Page Write Protection"
|
|
group.byte 0x27++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW39,Per Page Write Protection"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW40,Per Page Write Protection"
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW41,Per Page Write Protection"
|
|
group.byte 0x2A++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW42,Per Page Write Protection"
|
|
group.byte 0x2B++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW43,Per Page Write Protection"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW44,Per Page Write Protection"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW45,Per Page Write Protection"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW46,Per Page Write Protection"
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW47,Per Page Write Protection"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW48,Per Page Write Protection"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW49,Per Page Write Protection"
|
|
group.byte 0x32++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW50,Per Page Write Protection"
|
|
group.byte 0x33++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW51,Per Page Write Protection"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW52,Per Page Write Protection"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW53,Per Page Write Protection"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW54,Per Page Write Protection"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW55,Per Page Write Protection"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW56,Per Page Write Protection"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW57,Per Page Write Protection"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW58,Per Page Write Protection"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW59,Per Page Write Protection"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW60,Per Page Write Protection"
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW61,Per Page Write Protection"
|
|
group.byte 0x3E++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW62,Per Page Write Protection"
|
|
group.byte 0x3F++0x00
|
|
line.byte 0x00 "SFLASH_PROT_ROW63,Per Page Write Protection"
|
|
group.byte 0x7F++0x00
|
|
line.byte 0x00 "PROT_PROTECTION,Protection Level"
|
|
bitfld.byte 0x00 0.--1. " PROT_LEVEL ,Current protection mode" "OPEN,VIRGIN,PROTECTED,KILL"
|
|
tree "8b Addr/Value pair Section Registers"
|
|
group.byte 0x80++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B0,8b Addr/Value Pair Section"
|
|
group.byte 0x81++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B1,8b Addr/Value Pair Section"
|
|
group.byte 0x82++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B2,8b Addr/Value Pair Section"
|
|
group.byte 0x83++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B3,8b Addr/Value Pair Section"
|
|
group.byte 0x84++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B4,8b Addr/Value Pair Section"
|
|
group.byte 0x85++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B5,8b Addr/Value Pair Section"
|
|
group.byte 0x86++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B6,8b Addr/Value Pair Section"
|
|
group.byte 0x87++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B7,8b Addr/Value Pair Section"
|
|
group.byte 0x88++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B8,8b Addr/Value Pair Section"
|
|
group.byte 0x89++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B9,8b Addr/Value Pair Section"
|
|
group.byte 0x8A++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B10,8b Addr/Value Pair Section"
|
|
group.byte 0x8B++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B11,8b Addr/Value Pair Section"
|
|
group.byte 0x8C++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B12,8b Addr/Value Pair Section"
|
|
group.byte 0x8D++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B13,8b Addr/Value Pair Section"
|
|
group.byte 0x8E++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B14,8b Addr/Value Pair Section"
|
|
group.byte 0x8F++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B15,8b Addr/Value Pair Section"
|
|
group.byte 0x90++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B16,8b Addr/Value Pair Section"
|
|
group.byte 0x91++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B17,8b Addr/Value Pair Section"
|
|
group.byte 0x92++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B18,8b Addr/Value Pair Section"
|
|
group.byte 0x93++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B19,8b Addr/Value Pair Section"
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B20,8b Addr/Value Pair Section"
|
|
group.byte 0x95++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B21,8b Addr/Value Pair Section"
|
|
group.byte 0x96++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B22,8b Addr/Value Pair Section"
|
|
group.byte 0x97++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B23,8b Addr/Value Pair Section"
|
|
group.byte 0x98++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B24,8b Addr/Value Pair Section"
|
|
group.byte 0x99++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B25,8b Addr/Value Pair Section"
|
|
group.byte 0x9A++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B26,8b Addr/Value Pair Section"
|
|
group.byte 0x9B++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B27,8b Addr/Value Pair Section"
|
|
group.byte 0x9C++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B28,8b Addr/Value Pair Section"
|
|
group.byte 0x9D++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B29,8b Addr/Value Pair Section"
|
|
group.byte 0x9E++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B30,8b Addr/Value Pair Section"
|
|
group.byte 0x9F++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B31,8b Addr/Value Pair Section"
|
|
group.byte 0xA0++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B32,8b Addr/Value Pair Section"
|
|
group.byte 0xA1++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B33,8b Addr/Value Pair Section"
|
|
group.byte 0xA2++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B34,8b Addr/Value Pair Section"
|
|
group.byte 0xA3++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B35,8b Addr/Value Pair Section"
|
|
group.byte 0xA4++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B36,8b Addr/Value Pair Section"
|
|
group.byte 0xA5++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B37,8b Addr/Value Pair Section"
|
|
group.byte 0xA6++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B38,8b Addr/Value Pair Section"
|
|
group.byte 0xA7++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B39,8b Addr/Value Pair Section"
|
|
group.byte 0xA8++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B40,8b Addr/Value Pair Section"
|
|
group.byte 0xA9++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B41,8b Addr/Value Pair Section"
|
|
group.byte 0xAA++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B42,8b Addr/Value Pair Section"
|
|
group.byte 0xAB++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B43,8b Addr/Value Pair Section"
|
|
group.byte 0xAC++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B44,8b Addr/Value Pair Section"
|
|
group.byte 0xAD++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B45,8b Addr/Value Pair Section"
|
|
group.byte 0xAE++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B46,8b Addr/Value Pair Section"
|
|
group.byte 0xAF++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B47,8b Addr/Value Pair Section"
|
|
group.byte 0xB0++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B48,8b Addr/Value Pair Section"
|
|
group.byte 0xB1++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B49,8b Addr/Value Pair Section"
|
|
group.byte 0xB2++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B50,8b Addr/Value Pair Section"
|
|
group.byte 0xB3++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B51,8b Addr/Value Pair Section"
|
|
group.byte 0xB4++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B52,8b Addr/Value Pair Section"
|
|
group.byte 0xB5++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B53,8b Addr/Value Pair Section"
|
|
group.byte 0xB6++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B54,8b Addr/Value Pair Section"
|
|
group.byte 0xB7++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B55,8b Addr/Value Pair Section"
|
|
group.byte 0xB8++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B56,8b Addr/Value Pair Section"
|
|
group.byte 0xB9++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B57,8b Addr/Value Pair Section"
|
|
group.byte 0xBA++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B58,8b Addr/Value Pair Section"
|
|
group.byte 0xBB++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B59,8b Addr/Value Pair Section"
|
|
group.byte 0xBC++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B60,8b Addr/Value Pair Section"
|
|
group.byte 0xBD++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B61,8b Addr/Value Pair Section"
|
|
group.byte 0xBE++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B62,8b Addr/Value Pair Section"
|
|
group.byte 0xBF++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B63,8b Addr/Value Pair Section"
|
|
group.byte 0xC0++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B64,8b Addr/Value Pair Section"
|
|
group.byte 0xC1++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B65,8b Addr/Value Pair Section"
|
|
group.byte 0xC2++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B66,8b Addr/Value Pair Section"
|
|
group.byte 0xC3++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B67,8b Addr/Value Pair Section"
|
|
group.byte 0xC4++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B68,8b Addr/Value Pair Section"
|
|
group.byte 0xC5++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B69,8b Addr/Value Pair Section"
|
|
group.byte 0xC6++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B70,8b Addr/Value Pair Section"
|
|
group.byte 0xC7++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B71,8b Addr/Value Pair Section"
|
|
group.byte 0xC8++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B72,8b Addr/Value Pair Section"
|
|
group.byte 0xC9++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B73,8b Addr/Value Pair Section"
|
|
group.byte 0xCA++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B74,8b Addr/Value Pair Section"
|
|
group.byte 0xCB++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B75,8b Addr/Value Pair Section"
|
|
group.byte 0xCC++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B76,8b Addr/Value Pair Section"
|
|
group.byte 0xCD++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B77,8b Addr/Value Pair Section"
|
|
group.byte 0xCE++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B78,8b Addr/Value Pair Section"
|
|
group.byte 0xCF++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B79,8b Addr/Value Pair Section"
|
|
group.byte 0xD0++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B80,8b Addr/Value Pair Section"
|
|
group.byte 0xD1++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B81,8b Addr/Value Pair Section"
|
|
group.byte 0xD2++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B82,8b Addr/Value Pair Section"
|
|
group.byte 0xD3++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B83,8b Addr/Value Pair Section"
|
|
group.byte 0xD4++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B84,8b Addr/Value Pair Section"
|
|
group.byte 0xD5++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B85,8b Addr/Value Pair Section"
|
|
group.byte 0xD6++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B86,8b Addr/Value Pair Section"
|
|
group.byte 0xD7++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B87,8b Addr/Value Pair Section"
|
|
group.byte 0xD8++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B88,8b Addr/Value Pair Section"
|
|
group.byte 0xD9++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B89,8b Addr/Value Pair Section"
|
|
group.byte 0xDA++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B90,8b Addr/Value Pair Section"
|
|
group.byte 0xDB++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B91,8b Addr/Value Pair Section"
|
|
group.byte 0xDC++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B92,8b Addr/Value Pair Section"
|
|
group.byte 0xDD++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B93,8b Addr/Value Pair Section"
|
|
group.byte 0xDE++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B94,8b Addr/Value Pair Section"
|
|
group.byte 0xDF++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B95,8b Addr/Value Pair Section"
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B96,8b Addr/Value Pair Section"
|
|
group.byte 0xE1++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B97,8b Addr/Value Pair Section"
|
|
group.byte 0xE2++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B98,8b Addr/Value Pair Section"
|
|
group.byte 0xE3++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B99,8b Addr/Value Pair Section"
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B100,8b Addr/Value Pair Section"
|
|
group.byte 0xE5++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B101,8b Addr/Value Pair Section"
|
|
group.byte 0xE6++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B102,8b Addr/Value Pair Section"
|
|
group.byte 0xE7++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B103,8b Addr/Value Pair Section"
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B104,8b Addr/Value Pair Section"
|
|
group.byte 0xE9++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B105,8b Addr/Value Pair Section"
|
|
group.byte 0xEA++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B106,8b Addr/Value Pair Section"
|
|
group.byte 0xEB++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B107,8b Addr/Value Pair Section"
|
|
group.byte 0xEC++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B108,8b Addr/Value Pair Section"
|
|
group.byte 0xED++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B109,8b Addr/Value Pair Section"
|
|
group.byte 0xEE++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B110,8b Addr/Value Pair Section"
|
|
group.byte 0xEF++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B111,8b Addr/Value Pair Section"
|
|
group.byte 0xF0++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B112,8b Addr/Value Pair Section"
|
|
group.byte 0xF1++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B113,8b Addr/Value Pair Section"
|
|
group.byte 0xF2++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B114,8b Addr/Value Pair Section"
|
|
group.byte 0xF3++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B115,8b Addr/Value Pair Section"
|
|
group.byte 0xF4++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B116,8b Addr/Value Pair Section"
|
|
group.byte 0xF5++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B117,8b Addr/Value Pair Section"
|
|
group.byte 0xF6++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B118,8b Addr/Value Pair Section"
|
|
group.byte 0xF7++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B119,8b Addr/Value Pair Section"
|
|
group.byte 0xF8++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B120,8b Addr/Value Pair Section"
|
|
group.byte 0xF9++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B121,8b Addr/Value Pair Section"
|
|
group.byte 0xFA++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B122,8b Addr/Value Pair Section"
|
|
group.byte 0xFB++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B123,8b Addr/Value Pair Section"
|
|
group.byte 0xFC++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B124,8b Addr/Value Pair Section"
|
|
group.byte 0xFD++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B125,8b Addr/Value Pair Section"
|
|
group.byte 0xFE++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B126,8b Addr/Value Pair Section"
|
|
group.byte 0xFF++0x00
|
|
line.byte 0x00 "AV_PAIRS_8B127,8b Addr/Value Pair Section"
|
|
tree.end
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "AV_PAIRS_32B0,32b Addr/Value Pair Section"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "AV_PAIRS_32B1,32b Addr/Value Pair Section"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "AV_PAIRS_32B2,32b Addr/Value Pair Section"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "AV_PAIRS_32B3,32b Addr/Value Pair Section"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "AV_PAIRS_32B4,32b Addr/Value Pair Section"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "AV_PAIRS_32B5,32b Addr/Value Pair Section"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "AV_PAIRS_32B6,32b Addr/Value Pair Section"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "AV_PAIRS_32B7,32b Addr/Value Pair Section"
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "AV_PAIRS_32B8,32b Addr/Value Pair Section"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "AV_PAIRS_32B9,32b Addr/Value Pair Section"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "AV_PAIRS_32B10,32b Addr/Value Pair Section"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "AV_PAIRS_32B11,32b Addr/Value Pair Section"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "AV_PAIRS_32B12,32b Addr/Value Pair Section"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "AV_PAIRS_32B13,32b Addr/Value Pair Section"
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "AV_PAIRS_32B14,32b Addr/Value Pair Section"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "AV_PAIRS_32B15,32b Addr/Value Pair Section"
|
|
group.long 0x140++0x07
|
|
line.long 0x00 "CPUSS_WOUNDING,CPUSS Wounding Register"
|
|
line.long 0x04 "SILICON_ID,Silicon ID"
|
|
hexmask.long.word 0x04 0.--15. 1. " ID ,Silicon ID"
|
|
group.word 0x148++0x0B
|
|
line.word 0x00 "CPUSS_PRIV_RAM,RAM Privileged Limit"
|
|
hexmask.word 0x00 0.--8. 1. " RAM_PROT_LIMIT ,Limit where the privileged are of SRAM starts in increments of 256 bytes"
|
|
line.word 0x02 "CPUSS_PRIV_ROM_BROM,Boot ROM Privileged Limit"
|
|
hexmask.word.byte 0x02 0.--7. 1. " BROM_PROT_LIMIT ,Limit where the privileged area of the boot ROM partition starts in increments of 256 bytes"
|
|
line.word 0x04 "CPUSS_PRIV_FLASH,Flash Privileged Limit"
|
|
hexmask.word 0x04 0.--10. 1. " FLASH_PROT_LIMIT ,Limit where the privileged area of flash starts in increments of 256 bytes"
|
|
line.word 0x06 "CPUSS_PRIV_ROM_SROM,System ROM Privileged Limit"
|
|
hexmask.word 0x06 0.--9. 1. " SROM_PROT_LIMIT ,Limit where the privileged area of system ROM partition starts in increments of 256 bytes"
|
|
line.word 0x08 "HIB_KEY_DELAY,Hibernate Wakeup Value For PWR_KEY_DELAY"
|
|
hexmask.word 0x08 0.--9. 1. " WAKEUP_HOLDOFF ,Delay to wait for references to settle on wakeup from hibernate/DeepSleep"
|
|
line.word 0x0A "DPSLP_KEY_DELAY,DeepSleep Wakeup Value For PWR_KEY_DELAY"
|
|
hexmask.word 0x0A 0.--9. 1. " WAKEUP_HOLDOFF ,Delay to wait for references to settle on wakeup from hibernate/DeepSleep"
|
|
group.byte 0x154++0x00
|
|
line.byte 0x00 "SWD_CONFIG,SWD Pinout Selector"
|
|
bitfld.byte 0x00 0. " SWD_SELECT ,SWD select" "Primary SWD location,Alternate SWD location"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.byte 0x155++0x03
|
|
line.byte 0x00 "INITIAL_SPCIF_TRIM_M1_DAC0,FLASH IDAC Trim Used During Boot"
|
|
bitfld.byte 0x00 5.--7. " SLOPE ,Slope" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--4. " IDAC ,Idac" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.long 0x158++0x07
|
|
line.long 0x00 "SWD_LISTEN,Listen Window Length"
|
|
line.long 0x04 "FLASH_START,Flash Image Start Address"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.byte 0x160++0x03
|
|
line.byte 0x00 "CSD_TRIM1_HVIDAC,CSD Trim Data For HVIDAC Operation"
|
|
line.byte 0x01 "CSD_TRIM2_HVIDAC,CSD Trim Data For HVIDAC Operation"
|
|
line.byte 0x02 "CSD_TRIM1_CSD,CSD Trim Data For (Normal) CSD Operation"
|
|
line.byte 0x03 "CSD_TRIM2_CSD,CSD Trim Data For (Normal) CSD Operation"
|
|
else
|
|
group.byte 0x160++0x01
|
|
line.byte 0x00 "CSDV2_CSD0_ADC_TRIM1,CSDv2 CSD0 ADC Trim 2"
|
|
bitfld.byte 0x00 5.--7. " ADCTRIM_2P4V_2_0 ,1.2V trim data - low order 3 bits of 5 bit field" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x00 0.--4. " ADCTRIM_1P2V ,1.2V trim data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "CSDV2_CSD0_ADC_TRIM2,CSDv2 CSD0 ADC Trim 1"
|
|
bitfld.byte 0x01 5.--6. " ADCTRIM_2P4V_5_4 ,1.2V trim data - high order 2 bits of 5 bit field" "0,1,2,3"
|
|
bitfld.byte 0x01 0.--4. " ADCTRIM_3P84V_2_0 ,1.2V trim data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word 0x164++0x03
|
|
line.word 0x00 "SAR_TEMP_MULTIPLIER,SAR Temperature Sensor Multiplication Factor"
|
|
line.word 0x02 "SAR_TEMP_OFFSET,SAR Temperature Sensor Offset"
|
|
group.byte 0x169++0x00
|
|
line.byte 0x00 "SKIP_CHECKSUM,Checksum Skip Option Register"
|
|
sif !cpuis("CY8C4*-BL*")
|
|
group.byte 0x16A++0x05
|
|
line.byte 0x00 "INITIAL_PWR_BG_TRIM1,SRSSLT BG Vref Trim Used During Boot"
|
|
bitfld.byte 0x00 0.--5. " REF_ITRIM ,Vref trim used during boot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "INITIAL_PWR_BG_TRIM1_INV,SRSSLT BG Vref Trim Used During Boot"
|
|
bitfld.byte 0x01 0.--5. " REF_ITRIM ,Vref trim used during boot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "INITIAL_PWR_BG_TRIM2,SRSSLT BG Iref Trim Used During Boot"
|
|
bitfld.byte 0x02 0.--5. " REF_ITRIM ,Vref trim used during boot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x03 "INITIAL_PWR_BG_TRIM2_INV,SRSSLT BG Iref Trim Used During Boot"
|
|
bitfld.byte 0x03 0.--5. " REF_ITRIM ,Vreg trim used during boot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x04 "INITIAL_SPCIF_TRIM_M0_DAC0,FLASH IDAC Trim Used During Boot"
|
|
bitfld.byte 0x04 5.--7. " SLOPE ,Slope" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x04 0.--4. " IDAC ,IDAC trim used during boot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x05 "INITIAL_SPCIF_TRIM_M0_DAC0_INV,FLASH IDAC Trim Used During Boot"
|
|
bitfld.byte 0x05 5.--7. " SLOPE ,Slope" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x05 0.--4. " IDAC ,IDAC trim used during boot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.byte 0x170++0x0F
|
|
line.byte 0x00 "PROT_VIRGINKEY0,Virgin Protection Mode Key"
|
|
line.byte 0x01 "PROT_VIRGINKEY1,Virgin Protection Mode Key"
|
|
line.byte 0x02 "PROT_VIRGINKEY2,Virgin Protection Mode Key"
|
|
line.byte 0x03 "PROT_VIRGINKEY3,Virgin Protection Mode Key"
|
|
line.byte 0x04 "PROT_VIRGINKEY4,Virgin Protection Mode Key"
|
|
line.byte 0x05 "PROT_VIRGINKEY5,Virgin Protection Mode Key"
|
|
line.byte 0x06 "PROT_VIRGINKEY6,Virgin Protection Mode Key"
|
|
line.byte 0x07 "PROT_VIRGINKEY7,Virgin Protection Mode Key"
|
|
line.byte 0x08 "DIE_LOT0,Lot Number"
|
|
line.byte 0x09 "DIE_LOT1,Lot Number"
|
|
line.byte 0x0A "DIE_LOT2,Lot Number"
|
|
line.byte 0x0B "DIE_WAFER,Wafer Number"
|
|
line.byte 0x0C "DIE_X,X Position On Wafer"
|
|
line.byte 0x0D "DIE_Y,Y Position On Wafer"
|
|
line.byte 0x0E "DIE_SORT,Sort1/2/3 Pass/fail Bin"
|
|
bitfld.byte 0x0E 5. " ENG_PASS ,ENG pass bin" "Failed,Passed"
|
|
bitfld.byte 0x0E 4. " CHI_PASS ,CHI pass bin" "Failed,Passed"
|
|
bitfld.byte 0x0E 3. " CRI_PASS ,CRI pass bin" "Failed,Passed"
|
|
bitfld.byte 0x0E 2. " S3_PASS ,SORT3 pass bin" "Failed,Passed"
|
|
textline " "
|
|
bitfld.byte 0x0E 1. " S2_PASS ,SORT2 pass bin" "Failed,Passed"
|
|
bitfld.byte 0x0E 0. " S1_PASS ,SORT1 pass bin" "Failed,Passed"
|
|
line.byte 0x0F "DIE_MINOR,Minor Revision Number"
|
|
group.byte 0x180++0x00
|
|
line.byte 0x00 "PE_TE_DATA0,PE/TE Data"
|
|
group.byte 0x181++0x00
|
|
line.byte 0x00 "PE_TE_DATA1,PE/TE Data"
|
|
group.byte 0x182++0x00
|
|
line.byte 0x00 "PE_TE_DATA2,PE/TE Data"
|
|
group.byte 0x183++0x00
|
|
line.byte 0x00 "PE_TE_DATA3,PE/TE Data"
|
|
group.byte 0x184++0x00
|
|
line.byte 0x00 "PE_TE_DATA4,PE/TE Data"
|
|
group.byte 0x185++0x00
|
|
line.byte 0x00 "PE_TE_DATA5,PE/TE Data"
|
|
group.byte 0x186++0x00
|
|
line.byte 0x00 "PE_TE_DATA6,PE/TE Data"
|
|
group.byte 0x187++0x00
|
|
line.byte 0x00 "PE_TE_DATA7,PE/TE Data"
|
|
group.byte 0x188++0x00
|
|
line.byte 0x00 "PE_TE_DATA8,PE/TE Data"
|
|
group.byte 0x189++0x00
|
|
line.byte 0x00 "PE_TE_DATA9,PE/TE Data"
|
|
group.byte 0x18A++0x00
|
|
line.byte 0x00 "PE_TE_DATA10,PE/TE Data"
|
|
group.byte 0x18B++0x00
|
|
line.byte 0x00 "PE_TE_DATA11,PE/TE Data"
|
|
group.byte 0x18C++0x00
|
|
line.byte 0x00 "PE_TE_DATA12,PE/TE Data"
|
|
group.byte 0x18D++0x00
|
|
line.byte 0x00 "PE_TE_DATA13,PE/TE Data"
|
|
group.byte 0x18E++0x00
|
|
line.byte 0x00 "PE_TE_DATA14,PE/TE Data"
|
|
group.byte 0x18F++0x00
|
|
line.byte 0x00 "PE_TE_DATA15,PE/TE Data"
|
|
group.byte 0x190++0x00
|
|
line.byte 0x00 "PE_TE_DATA16,PE/TE Data"
|
|
group.byte 0x191++0x00
|
|
line.byte 0x00 "PE_TE_DATA17,PE/TE Data"
|
|
group.byte 0x192++0x00
|
|
line.byte 0x00 "PE_TE_DATA18,PE/TE Data"
|
|
group.byte 0x193++0x00
|
|
line.byte 0x00 "PE_TE_DATA19,PE/TE Data"
|
|
group.byte 0x194++0x00
|
|
line.byte 0x00 "PE_TE_DATA20,PE/TE Data"
|
|
group.byte 0x195++0x00
|
|
line.byte 0x00 "PE_TE_DATA21,PE/TE Data"
|
|
group.byte 0x196++0x00
|
|
line.byte 0x00 "PE_TE_DATA22,PE/TE Data"
|
|
group.byte 0x197++0x00
|
|
line.byte 0x00 "PE_TE_DATA23,PE/TE Data"
|
|
group.byte 0x198++0x00
|
|
line.byte 0x00 "PE_TE_DATA24,PE/TE Data"
|
|
group.byte 0x199++0x00
|
|
line.byte 0x00 "PE_TE_DATA25,PE/TE Data"
|
|
group.byte 0x19A++0x00
|
|
line.byte 0x00 "PE_TE_DATA26,PE/TE Data"
|
|
group.byte 0x19B++0x00
|
|
line.byte 0x00 "PE_TE_DATA27,PE/TE Data"
|
|
group.byte 0x19C++0x00
|
|
line.byte 0x00 "PE_TE_DATA28,PE/TE Data"
|
|
group.byte 0x19D++0x00
|
|
line.byte 0x00 "PE_TE_DATA29,PE/TE Data"
|
|
group.byte 0x19E++0x00
|
|
line.byte 0x00 "PE_TE_DATA30,PE/TE Data"
|
|
group.byte 0x19F++0x00
|
|
line.byte 0x00 "PE_TE_DATA31,PE/TE Data"
|
|
group.long 0x1A0++0x1B
|
|
line.long 0x00 "PP,Preprogram Settings"
|
|
bitfld.long 0x00 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x04 "E,Erase Settings"
|
|
bitfld.long 0x04 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x08 "P,Program Settings"
|
|
bitfld.long 0x08 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x0C "EA_E,Erase All - Erase Settings"
|
|
bitfld.long 0x0C 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x10 "EA_P,Erase All - Program Settings"
|
|
bitfld.long 0x10 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x14 "ES_E,Erase Sector - Erase Settings"
|
|
bitfld.long 0x14 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
line.long 0x18 "ES_P_EO,Erase Sector - Program EO Settings"
|
|
bitfld.long 0x18 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks"
|
|
sif cpuis("CY8C4*-BL*")
|
|
group.byte 0x1BC++0x01
|
|
line.byte 0x00 "E_VCTAT,Bandgap Trim Register"
|
|
bitfld.byte 0x00 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "P_VCTAT,Bandgap Trim Register"
|
|
bitfld.byte 0x01 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3"
|
|
bitfld.byte 0x01 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x1C0++0x02
|
|
line.byte 0x00 "IMO_MAXF0,Max Frequency For Trim Pair 0"
|
|
bitfld.byte 0x00 0.--5. " MAXFREQ ,Max frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "IMO_ABS0,Value For PWR_BG_TRIM4 0"
|
|
bitfld.byte 0x01 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "IMO_TMPCO0,Value For PWR_BG_TRIM5 0"
|
|
bitfld.byte 0x02 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x1C1++0x02
|
|
line.byte 0x00 "IMO_MAXF1,Max Frequency For Trim Pair 1"
|
|
bitfld.byte 0x00 0.--5. " MAXFREQ ,Max frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "IMO_ABS1,Value For PWR_BG_TRIM4 1"
|
|
bitfld.byte 0x01 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "IMO_TMPCO1,Value For PWR_BG_TRIM5 1"
|
|
bitfld.byte 0x02 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x1C2++0x02
|
|
line.byte 0x00 "IMO_MAXF2,Max Frequency For Trim Pair 2"
|
|
bitfld.byte 0x00 0.--5. " MAXFREQ ,Max frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "IMO_ABS2,Value For PWR_BG_TRIM4 2"
|
|
bitfld.byte 0x01 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "IMO_TMPCO2,Value For PWR_BG_TRIM5 2"
|
|
bitfld.byte 0x02 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x1C3++0x02
|
|
line.byte 0x00 "IMO_MAXF3,Max Frequency For Trim Pair 3"
|
|
bitfld.byte 0x00 0.--5. " MAXFREQ ,Max frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "IMO_ABS3,Value For PWR_BG_TRIM4 3"
|
|
bitfld.byte 0x01 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x02 "IMO_TMPCO3,Value For PWR_BG_TRIM5 3"
|
|
bitfld.byte 0x02 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x1CC++0x01
|
|
line.byte 0x00 "IMO_ABS4,Value For PWR_BG_TRIM4"
|
|
bitfld.byte 0x00 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.byte 0x01 "IMO_TMPCO4,Value For PWR_BG_TRIM5"
|
|
bitfld.byte 0x01 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.byte 0x1D0++0x00
|
|
line.byte 0x00 "IMO_TRIM0,IMO Trim Register 0"
|
|
group.byte 0x1D1++0x00
|
|
line.byte 0x00 "IMO_TRIM1,IMO Trim Register 1"
|
|
group.byte 0x1D2++0x00
|
|
line.byte 0x00 "IMO_TRIM2,IMO Trim Register 2"
|
|
group.byte 0x1D3++0x00
|
|
line.byte 0x00 "IMO_TRIM3,IMO Trim Register 3"
|
|
group.byte 0x1D4++0x00
|
|
line.byte 0x00 "IMO_TRIM4,IMO Trim Register 4"
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "IMO_TRIM5,IMO Trim Register 5"
|
|
group.byte 0x1D6++0x00
|
|
line.byte 0x00 "IMO_TRIM6,IMO Trim Register 6"
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "IMO_TRIM7,IMO Trim Register 7"
|
|
group.byte 0x1D8++0x00
|
|
line.byte 0x00 "IMO_TRIM8,IMO Trim Register 8"
|
|
group.byte 0x1D9++0x00
|
|
line.byte 0x00 "IMO_TRIM9,IMO Trim Register 9"
|
|
group.byte 0x1DA++0x00
|
|
line.byte 0x00 "IMO_TRIM10,IMO Trim Register 10"
|
|
group.byte 0x1DB++0x00
|
|
line.byte 0x00 "IMO_TRIM11,IMO Trim Register 11"
|
|
group.byte 0x1DC++0x00
|
|
line.byte 0x00 "IMO_TRIM12,IMO Trim Register 12"
|
|
group.byte 0x1DD++0x00
|
|
line.byte 0x00 "IMO_TRIM13,IMO Trim Register 13"
|
|
group.byte 0x1DE++0x00
|
|
line.byte 0x00 "IMO_TRIM14,IMO Trim Register 14"
|
|
group.byte 0x1DF++0x00
|
|
line.byte 0x00 "IMO_TRIM15,IMO Trim Register 15"
|
|
group.byte 0x1E0++0x00
|
|
line.byte 0x00 "IMO_TRIM16,IMO Trim Register 16"
|
|
group.byte 0x1E1++0x00
|
|
line.byte 0x00 "IMO_TRIM17,IMO Trim Register 17"
|
|
group.byte 0x1E2++0x00
|
|
line.byte 0x00 "IMO_TRIM18,IMO Trim Register 18"
|
|
group.byte 0x1E3++0x00
|
|
line.byte 0x00 "IMO_TRIM19,IMO Trim Register 19"
|
|
group.byte 0x1E4++0x00
|
|
line.byte 0x00 "IMO_TRIM20,IMO Trim Register 20"
|
|
group.byte 0x1E5++0x00
|
|
line.byte 0x00 "IMO_TRIM21,IMO Trim Register 21"
|
|
group.byte 0x1E6++0x00
|
|
line.byte 0x00 "IMO_TRIM22,IMO Trim Register 22"
|
|
group.byte 0x1E7++0x00
|
|
line.byte 0x00 "IMO_TRIM23,IMO Trim Register 23"
|
|
group.byte 0x1E8++0x00
|
|
line.byte 0x00 "IMO_TRIM24,IMO Trim Register 24"
|
|
group.byte 0x1E9++0x00
|
|
line.byte 0x00 "IMO_TRIM25,IMO Trim Register 25"
|
|
group.byte 0x1EA++0x00
|
|
line.byte 0x00 "IMO_TRIM26,IMO Trim Register 26"
|
|
group.byte 0x1EB++0x00
|
|
line.byte 0x00 "IMO_TRIM27,IMO Trim Register 27"
|
|
group.byte 0x1EC++0x00
|
|
line.byte 0x00 "IMO_TRIM28,IMO Trim Register 28"
|
|
group.byte 0x1ED++0x00
|
|
line.byte 0x00 "IMO_TRIM29,IMO Trim Register 29"
|
|
group.byte 0x1EE++0x00
|
|
line.byte 0x00 "IMO_TRIM30,IMO Trim Register 30"
|
|
group.byte 0x1EF++0x00
|
|
line.byte 0x00 "IMO_TRIM31,IMO Trim Register 31"
|
|
group.byte 0x1F0++0x00
|
|
line.byte 0x00 "IMO_TRIM32,IMO Trim Register 32"
|
|
group.byte 0x1F1++0x00
|
|
line.byte 0x00 "IMO_TRIM33,IMO Trim Register 33"
|
|
group.byte 0x1F2++0x00
|
|
line.byte 0x00 "IMO_TRIM34,IMO Trim Register 34"
|
|
group.byte 0x1F3++0x00
|
|
line.byte 0x00 "IMO_TRIM35,IMO Trim Register 35"
|
|
group.byte 0x1F4++0x00
|
|
line.byte 0x00 "IMO_TRIM36,IMO Trim Register 36"
|
|
group.byte 0x1F5++0x00
|
|
line.byte 0x00 "IMO_TRIM37,IMO Trim Register 37"
|
|
group.byte 0x1F6++0x00
|
|
line.byte 0x00 "IMO_TRIM38,IMO Trim Register 38"
|
|
group.byte 0x1F7++0x00
|
|
line.byte 0x00 "IMO_TRIM39,IMO Trim Register 39"
|
|
group.byte 0x1F8++0x00
|
|
line.byte 0x00 "IMO_TRIM40,IMO Trim Register 40"
|
|
group.byte 0x1F9++0x00
|
|
line.byte 0x00 "IMO_TRIM41,IMO Trim Register 41"
|
|
group.byte 0x1FA++0x00
|
|
line.byte 0x00 "IMO_TRIM42,IMO Trim Register 42"
|
|
group.byte 0x1FB++0x00
|
|
line.byte 0x00 "IMO_TRIM43,IMO Trim Register 43"
|
|
group.byte 0x1FC++0x00
|
|
line.byte 0x00 "IMO_TRIM44,IMO Trim Register 44"
|
|
group.byte 0x1FD++0x00
|
|
line.byte 0x00 "IMO_TRIM45,IMO Trim Register 45"
|
|
group.word 0x1FE++0x01
|
|
line.word 0x00 "CHECKSUM,Boot Checksum"
|
|
group.byte 0x400++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW0,Per Page Write Protection 0"
|
|
group.byte 0x401++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW1,Per Page Write Protection 1"
|
|
group.byte 0x402++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW2,Per Page Write Protection 2"
|
|
group.byte 0x403++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW3,Per Page Write Protection 3"
|
|
group.byte 0x404++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW4,Per Page Write Protection 4"
|
|
group.byte 0x405++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW5,Per Page Write Protection 5"
|
|
group.byte 0x406++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW6,Per Page Write Protection 6"
|
|
group.byte 0x407++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW7,Per Page Write Protection 7"
|
|
group.byte 0x408++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW8,Per Page Write Protection 8"
|
|
group.byte 0x409++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW9,Per Page Write Protection 9"
|
|
group.byte 0x40A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW10,Per Page Write Protection 10"
|
|
group.byte 0x40B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW11,Per Page Write Protection 11"
|
|
group.byte 0x40C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW12,Per Page Write Protection 12"
|
|
group.byte 0x40D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW13,Per Page Write Protection 13"
|
|
group.byte 0x40E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW14,Per Page Write Protection 14"
|
|
group.byte 0x40F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW15,Per Page Write Protection 15"
|
|
group.byte 0x410++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW16,Per Page Write Protection 16"
|
|
group.byte 0x411++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW17,Per Page Write Protection 17"
|
|
group.byte 0x412++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW18,Per Page Write Protection 18"
|
|
group.byte 0x413++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW19,Per Page Write Protection 19"
|
|
group.byte 0x414++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW20,Per Page Write Protection 20"
|
|
group.byte 0x415++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW21,Per Page Write Protection 21"
|
|
group.byte 0x416++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW22,Per Page Write Protection 22"
|
|
group.byte 0x417++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW23,Per Page Write Protection 23"
|
|
group.byte 0x418++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW24,Per Page Write Protection 24"
|
|
group.byte 0x419++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW25,Per Page Write Protection 25"
|
|
group.byte 0x41A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW26,Per Page Write Protection 26"
|
|
group.byte 0x41B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW27,Per Page Write Protection 27"
|
|
group.byte 0x41C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW28,Per Page Write Protection 28"
|
|
group.byte 0x41D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW29,Per Page Write Protection 29"
|
|
group.byte 0x41E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW30,Per Page Write Protection 30"
|
|
group.byte 0x41F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW31,Per Page Write Protection 31"
|
|
group.byte 0x420++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW32,Per Page Write Protection 32"
|
|
group.byte 0x421++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW33,Per Page Write Protection 33"
|
|
group.byte 0x422++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW34,Per Page Write Protection 34"
|
|
group.byte 0x423++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW35,Per Page Write Protection 35"
|
|
group.byte 0x424++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW36,Per Page Write Protection 36"
|
|
group.byte 0x425++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW37,Per Page Write Protection 37"
|
|
group.byte 0x426++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW38,Per Page Write Protection 38"
|
|
group.byte 0x427++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW39,Per Page Write Protection 39"
|
|
group.byte 0x428++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW40,Per Page Write Protection 40"
|
|
group.byte 0x429++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW41,Per Page Write Protection 41"
|
|
group.byte 0x42A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW42,Per Page Write Protection 42"
|
|
group.byte 0x42B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW43,Per Page Write Protection 43"
|
|
group.byte 0x42C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW44,Per Page Write Protection 44"
|
|
group.byte 0x42D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW45,Per Page Write Protection 45"
|
|
group.byte 0x42E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW46,Per Page Write Protection 46"
|
|
group.byte 0x42F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW47,Per Page Write Protection 47"
|
|
group.byte 0x430++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW48,Per Page Write Protection 48"
|
|
group.byte 0x431++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW49,Per Page Write Protection 49"
|
|
group.byte 0x432++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW50,Per Page Write Protection 50"
|
|
group.byte 0x433++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW51,Per Page Write Protection 51"
|
|
group.byte 0x434++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW52,Per Page Write Protection 52"
|
|
group.byte 0x435++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW53,Per Page Write Protection 53"
|
|
group.byte 0x436++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW54,Per Page Write Protection 54"
|
|
group.byte 0x437++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW55,Per Page Write Protection 55"
|
|
group.byte 0x438++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW56,Per Page Write Protection 56"
|
|
group.byte 0x439++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW57,Per Page Write Protection 57"
|
|
group.byte 0x43A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW58,Per Page Write Protection 58"
|
|
group.byte 0x43B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW59,Per Page Write Protection 59"
|
|
group.byte 0x43C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW60,Per Page Write Protection 60"
|
|
group.byte 0x43D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW61,Per Page Write Protection 61"
|
|
group.byte 0x43E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW62,Per Page Write Protection 62"
|
|
group.byte 0x43F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW63,Per Page Write Protection 63"
|
|
group.byte 0x440++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW64,Per Page Write Protection 64"
|
|
group.byte 0x441++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW65,Per Page Write Protection 65"
|
|
group.byte 0x442++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW66,Per Page Write Protection 66"
|
|
group.byte 0x443++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW67,Per Page Write Protection 67"
|
|
group.byte 0x444++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW68,Per Page Write Protection 68"
|
|
group.byte 0x445++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW69,Per Page Write Protection 69"
|
|
group.byte 0x446++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW70,Per Page Write Protection 70"
|
|
group.byte 0x447++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW71,Per Page Write Protection 71"
|
|
group.byte 0x448++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW72,Per Page Write Protection 72"
|
|
group.byte 0x449++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW73,Per Page Write Protection 73"
|
|
group.byte 0x44A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW74,Per Page Write Protection 74"
|
|
group.byte 0x44B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW75,Per Page Write Protection 75"
|
|
group.byte 0x44C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW76,Per Page Write Protection 76"
|
|
group.byte 0x44D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW77,Per Page Write Protection 77"
|
|
group.byte 0x44E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW78,Per Page Write Protection 78"
|
|
group.byte 0x44F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW79,Per Page Write Protection 79"
|
|
group.byte 0x450++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW80,Per Page Write Protection 80"
|
|
group.byte 0x451++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW81,Per Page Write Protection 81"
|
|
group.byte 0x452++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW82,Per Page Write Protection 82"
|
|
group.byte 0x453++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW83,Per Page Write Protection 83"
|
|
group.byte 0x454++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW84,Per Page Write Protection 84"
|
|
group.byte 0x455++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW85,Per Page Write Protection 85"
|
|
group.byte 0x456++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW86,Per Page Write Protection 86"
|
|
group.byte 0x457++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW87,Per Page Write Protection 87"
|
|
group.byte 0x458++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW88,Per Page Write Protection 88"
|
|
group.byte 0x459++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW89,Per Page Write Protection 89"
|
|
group.byte 0x45A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW90,Per Page Write Protection 90"
|
|
group.byte 0x45B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW91,Per Page Write Protection 91"
|
|
group.byte 0x45C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW92,Per Page Write Protection 92"
|
|
group.byte 0x45D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW93,Per Page Write Protection 93"
|
|
group.byte 0x45E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW94,Per Page Write Protection 94"
|
|
group.byte 0x45F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW95,Per Page Write Protection 95"
|
|
group.byte 0x460++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW96,Per Page Write Protection 96"
|
|
group.byte 0x461++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW97,Per Page Write Protection 97"
|
|
group.byte 0x462++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW98,Per Page Write Protection 98"
|
|
group.byte 0x463++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW99,Per Page Write Protection 99"
|
|
group.byte 0x464++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW100,Per Page Write Protection 100"
|
|
group.byte 0x465++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW101,Per Page Write Protection 101"
|
|
group.byte 0x466++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW102,Per Page Write Protection 102"
|
|
group.byte 0x467++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW103,Per Page Write Protection 103"
|
|
group.byte 0x468++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW104,Per Page Write Protection 104"
|
|
group.byte 0x469++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW105,Per Page Write Protection 105"
|
|
group.byte 0x46A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW106,Per Page Write Protection 106"
|
|
group.byte 0x46B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW107,Per Page Write Protection 107"
|
|
group.byte 0x46C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW108,Per Page Write Protection 108"
|
|
group.byte 0x46D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW109,Per Page Write Protection 109"
|
|
group.byte 0x46E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW110,Per Page Write Protection 110"
|
|
group.byte 0x46F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW111,Per Page Write Protection 111"
|
|
group.byte 0x470++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW112,Per Page Write Protection 112"
|
|
group.byte 0x471++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW113,Per Page Write Protection 113"
|
|
group.byte 0x472++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW114,Per Page Write Protection 114"
|
|
group.byte 0x473++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW115,Per Page Write Protection 115"
|
|
group.byte 0x474++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW116,Per Page Write Protection 116"
|
|
group.byte 0x475++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW117,Per Page Write Protection 117"
|
|
group.byte 0x476++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW118,Per Page Write Protection 118"
|
|
group.byte 0x477++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW119,Per Page Write Protection 119"
|
|
group.byte 0x478++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW120,Per Page Write Protection 120"
|
|
group.byte 0x479++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW121,Per Page Write Protection 121"
|
|
group.byte 0x47A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW122,Per Page Write Protection 122"
|
|
group.byte 0x47B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW123,Per Page Write Protection 123"
|
|
group.byte 0x47C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW124,Per Page Write Protection 124"
|
|
group.byte 0x47D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW125,Per Page Write Protection 125"
|
|
group.byte 0x47E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW126,Per Page Write Protection 126"
|
|
group.byte 0x47F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW127,Per Page Write Protection 127"
|
|
group.byte 0x480++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW128,Per Page Write Protection 128"
|
|
group.byte 0x481++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW129,Per Page Write Protection 129"
|
|
group.byte 0x482++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW130,Per Page Write Protection 130"
|
|
group.byte 0x483++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW131,Per Page Write Protection 131"
|
|
group.byte 0x484++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW132,Per Page Write Protection 132"
|
|
group.byte 0x485++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW133,Per Page Write Protection 133"
|
|
group.byte 0x486++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW134,Per Page Write Protection 134"
|
|
group.byte 0x487++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW135,Per Page Write Protection 135"
|
|
group.byte 0x488++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW136,Per Page Write Protection 136"
|
|
group.byte 0x489++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW137,Per Page Write Protection 137"
|
|
group.byte 0x48A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW138,Per Page Write Protection 138"
|
|
group.byte 0x48B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW139,Per Page Write Protection 139"
|
|
group.byte 0x48C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW140,Per Page Write Protection 140"
|
|
group.byte 0x48D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW141,Per Page Write Protection 141"
|
|
group.byte 0x48E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW142,Per Page Write Protection 142"
|
|
group.byte 0x48F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW143,Per Page Write Protection 143"
|
|
group.byte 0x490++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW144,Per Page Write Protection 144"
|
|
group.byte 0x491++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW145,Per Page Write Protection 145"
|
|
group.byte 0x492++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW146,Per Page Write Protection 146"
|
|
group.byte 0x493++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW147,Per Page Write Protection 147"
|
|
group.byte 0x494++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW148,Per Page Write Protection 148"
|
|
group.byte 0x495++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW149,Per Page Write Protection 149"
|
|
group.byte 0x496++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW150,Per Page Write Protection 150"
|
|
group.byte 0x497++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW151,Per Page Write Protection 151"
|
|
group.byte 0x498++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW152,Per Page Write Protection 152"
|
|
group.byte 0x499++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW153,Per Page Write Protection 153"
|
|
group.byte 0x49A++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW154,Per Page Write Protection 154"
|
|
group.byte 0x49B++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW155,Per Page Write Protection 155"
|
|
group.byte 0x49C++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW156,Per Page Write Protection 156"
|
|
group.byte 0x49D++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW157,Per Page Write Protection 157"
|
|
group.byte 0x49E++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW158,Per Page Write Protection 158"
|
|
group.byte 0x49F++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW159,Per Page Write Protection 159"
|
|
group.byte 0x4A0++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW160,Per Page Write Protection 160"
|
|
group.byte 0x4A1++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW161,Per Page Write Protection 161"
|
|
group.byte 0x4A2++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW162,Per Page Write Protection 162"
|
|
group.byte 0x4A3++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW163,Per Page Write Protection 163"
|
|
group.byte 0x4A4++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW164,Per Page Write Protection 164"
|
|
group.byte 0x4A5++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW165,Per Page Write Protection 165"
|
|
group.byte 0x4A6++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW166,Per Page Write Protection 166"
|
|
group.byte 0x4A7++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW167,Per Page Write Protection 167"
|
|
group.byte 0x4A8++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW168,Per Page Write Protection 168"
|
|
group.byte 0x4A9++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW169,Per Page Write Protection 169"
|
|
group.byte 0x4AA++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW170,Per Page Write Protection 170"
|
|
group.byte 0x4AB++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW171,Per Page Write Protection 171"
|
|
group.byte 0x4AC++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW172,Per Page Write Protection 172"
|
|
group.byte 0x4AD++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW173,Per Page Write Protection 173"
|
|
group.byte 0x4AE++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW174,Per Page Write Protection 174"
|
|
group.byte 0x4AF++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW175,Per Page Write Protection 175"
|
|
group.byte 0x4B0++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW176,Per Page Write Protection 176"
|
|
group.byte 0x4B1++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW177,Per Page Write Protection 177"
|
|
group.byte 0x4B2++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW178,Per Page Write Protection 178"
|
|
group.byte 0x4B3++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW179,Per Page Write Protection 179"
|
|
group.byte 0x4B4++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW180,Per Page Write Protection 180"
|
|
group.byte 0x4B5++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW181,Per Page Write Protection 181"
|
|
group.byte 0x4B6++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW182,Per Page Write Protection 182"
|
|
group.byte 0x4B7++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW183,Per Page Write Protection 183"
|
|
group.byte 0x4B8++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW184,Per Page Write Protection 184"
|
|
group.byte 0x4B9++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW185,Per Page Write Protection 185"
|
|
group.byte 0x4BA++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW186,Per Page Write Protection 186"
|
|
group.byte 0x4BB++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW187,Per Page Write Protection 187"
|
|
group.byte 0x4BC++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW188,Per Page Write Protection 188"
|
|
group.byte 0x4BD++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW189,Per Page Write Protection 189"
|
|
group.byte 0x4BE++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW190,Per Page Write Protection 190"
|
|
group.byte 0x4BF++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW191,Per Page Write Protection 191"
|
|
group.byte 0x4C0++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW192,Per Page Write Protection 192"
|
|
group.byte 0x4C1++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW193,Per Page Write Protection 193"
|
|
group.byte 0x4C2++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW194,Per Page Write Protection 194"
|
|
group.byte 0x4C3++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW195,Per Page Write Protection 195"
|
|
group.byte 0x4C4++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW196,Per Page Write Protection 196"
|
|
group.byte 0x4C5++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW197,Per Page Write Protection 197"
|
|
group.byte 0x4C6++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW198,Per Page Write Protection 198"
|
|
group.byte 0x4C7++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW199,Per Page Write Protection 199"
|
|
group.byte 0x4C8++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW200,Per Page Write Protection 200"
|
|
group.byte 0x4C9++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW201,Per Page Write Protection 201"
|
|
group.byte 0x4CA++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW202,Per Page Write Protection 202"
|
|
group.byte 0x4CB++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW203,Per Page Write Protection 203"
|
|
group.byte 0x4CC++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW204,Per Page Write Protection 204"
|
|
group.byte 0x4CD++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW205,Per Page Write Protection 205"
|
|
group.byte 0x4CE++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW206,Per Page Write Protection 206"
|
|
group.byte 0x4CF++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW207,Per Page Write Protection 207"
|
|
group.byte 0x4D0++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW208,Per Page Write Protection 208"
|
|
group.byte 0x4D1++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW209,Per Page Write Protection 209"
|
|
group.byte 0x4D2++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW210,Per Page Write Protection 210"
|
|
group.byte 0x4D3++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW211,Per Page Write Protection 211"
|
|
group.byte 0x4D4++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW212,Per Page Write Protection 212"
|
|
group.byte 0x4D5++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW213,Per Page Write Protection 213"
|
|
group.byte 0x4D6++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW214,Per Page Write Protection 214"
|
|
group.byte 0x4D7++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW215,Per Page Write Protection 215"
|
|
group.byte 0x4D8++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW216,Per Page Write Protection 216"
|
|
group.byte 0x4D9++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW217,Per Page Write Protection 217"
|
|
group.byte 0x4DA++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW218,Per Page Write Protection 218"
|
|
group.byte 0x4DB++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW219,Per Page Write Protection 219"
|
|
group.byte 0x4DC++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW220,Per Page Write Protection 220"
|
|
group.byte 0x4DD++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW221,Per Page Write Protection 221"
|
|
group.byte 0x4DE++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW222,Per Page Write Protection 222"
|
|
group.byte 0x4DF++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW223,Per Page Write Protection 223"
|
|
group.byte 0x4E0++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW224,Per Page Write Protection 224"
|
|
group.byte 0x4E1++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW225,Per Page Write Protection 225"
|
|
group.byte 0x4E2++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW226,Per Page Write Protection 226"
|
|
group.byte 0x4E3++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW227,Per Page Write Protection 227"
|
|
group.byte 0x4E4++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW228,Per Page Write Protection 228"
|
|
group.byte 0x4E5++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW229,Per Page Write Protection 229"
|
|
group.byte 0x4E6++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW230,Per Page Write Protection 230"
|
|
group.byte 0x4E7++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW231,Per Page Write Protection 231"
|
|
group.byte 0x4E8++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW232,Per Page Write Protection 232"
|
|
group.byte 0x4E9++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW233,Per Page Write Protection 233"
|
|
group.byte 0x4EA++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW234,Per Page Write Protection 234"
|
|
group.byte 0x4EB++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW235,Per Page Write Protection 235"
|
|
group.byte 0x4EC++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW236,Per Page Write Protection 236"
|
|
group.byte 0x4ED++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW237,Per Page Write Protection 237"
|
|
group.byte 0x4EE++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW238,Per Page Write Protection 238"
|
|
group.byte 0x4EF++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW239,Per Page Write Protection 239"
|
|
group.byte 0x4F0++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW240,Per Page Write Protection 240"
|
|
group.byte 0x4F1++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW241,Per Page Write Protection 241"
|
|
group.byte 0x4F2++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW242,Per Page Write Protection 242"
|
|
group.byte 0x4F3++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW243,Per Page Write Protection 243"
|
|
group.byte 0x4F4++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW244,Per Page Write Protection 244"
|
|
group.byte 0x4F5++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW245,Per Page Write Protection 245"
|
|
group.byte 0x4F6++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW246,Per Page Write Protection 246"
|
|
group.byte 0x4F7++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW247,Per Page Write Protection 247"
|
|
group.byte 0x4F8++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW248,Per Page Write Protection 248"
|
|
group.byte 0x4F9++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW249,Per Page Write Protection 249"
|
|
group.byte 0x4FA++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW250,Per Page Write Protection 250"
|
|
group.byte 0x4FB++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW251,Per Page Write Protection 251"
|
|
group.byte 0x4FC++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW252,Per Page Write Protection 252"
|
|
group.byte 0x4FD++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW253,Per Page Write Protection 253"
|
|
group.byte 0x4FE++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW254,Per Page Write Protection 254"
|
|
group.byte 0x4FF++0x00
|
|
line.byte 0x00 "ALT_PROT_ROW255,Per Page Write Protection 255"
|
|
group.long 0x5A0++0x1B
|
|
line.long 0x00 "ALT_PP,Preprogram Settings"
|
|
bitfld.long 0x00 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
line.long 0x04 "ALT_E,Erase Settings"
|
|
bitfld.long 0x04 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
line.long 0x08 "ALT_P,Program Settings"
|
|
bitfld.long 0x08 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
line.long 0x0C "ALT_EA_E,Erase All - Erase Settings"
|
|
bitfld.long 0x0C 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
line.long 0x10 "ALT_EA_P,Erase All - Program Settings"
|
|
bitfld.long 0x10 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
line.long 0x14 "ALT_ES_E,Erase Sector - Erase Settings"
|
|
bitfld.long 0x14 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
line.long 0x18 "ALT_ES_P_EO,Erase Sector - Program EO Settings"
|
|
bitfld.long 0x18 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x18 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " PERIOD ,24-bit period of timer in clk_spcif_timer ticks"
|
|
group.byte 0x5BC++0x01
|
|
line.byte 0x00 "E_VCTAT,Bandgap Trim Register"
|
|
bitfld.byte 0x00 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x01 "P_VCTAT,Bandgap Trim Register"
|
|
bitfld.byte 0x01 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3"
|
|
bitfld.byte 0x01 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.byte 0x1BE++0x01
|
|
line.byte 0x00 "IMO_TRIM_USBMODE_24,USB IMO TRIM 24mhz"
|
|
line.byte 0x01 "IMO_TRIM_USBMODE_48,USB IMO TRIM 48mhz"
|
|
group.byte 0x1CC++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT0,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1CD++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT1,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1CE++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT2,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1CF++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT3,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D0++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT4,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D1++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT5,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D2++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT6,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D3++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT7,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D4++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT8,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D5++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT9,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D6++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT10,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D7++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT11,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D8++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT12,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1D9++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT13,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1DA++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT14,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1DB++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT15,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1DC++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT16,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1DD++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT17,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1DE++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT18,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1DF++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT19,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1E0++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT20,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1E1++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT21,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1E2++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT22,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1E3++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT23,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1E4++0x00
|
|
line.byte 0x00 "IMO_TCTRIM_LT24,IMO Tempco Trim Register"
|
|
bitfld.byte 0x00 5.--6. " TCTRIM ,Imo temperature compesation trim" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x1E5++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT0,IMO Frequency Trim Register"
|
|
group.byte 0x1E6++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT1,IMO Frequency Trim Register"
|
|
group.byte 0x1E7++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT2,IMO Frequency Trim Register"
|
|
group.byte 0x1E8++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT3,IMO Frequency Trim Register"
|
|
group.byte 0x1E9++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT4,IMO Frequency Trim Register"
|
|
group.byte 0x1EA++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT5,IMO Frequency Trim Register"
|
|
group.byte 0x1EB++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT6,IMO Frequency Trim Register"
|
|
group.byte 0x1EC++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT7,IMO Frequency Trim Register"
|
|
group.byte 0x1ED++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT8,IMO Frequency Trim Register"
|
|
group.byte 0x1EE++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT9,IMO Frequency Trim Register"
|
|
group.byte 0x1EF++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT10,IMO Frequency Trim Register"
|
|
group.byte 0x1F0++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT11,IMO Frequency Trim Register"
|
|
group.byte 0x1F1++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT12,IMO Frequency Trim Register"
|
|
group.byte 0x1F2++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT13,IMO Frequency Trim Register"
|
|
group.byte 0x1F3++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT14,IMO Frequency Trim Register"
|
|
group.byte 0x1F4++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT15,IMO Frequency Trim Register"
|
|
group.byte 0x1F5++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT16,IMO Frequency Trim Register"
|
|
group.byte 0x1F6++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT17,IMO Frequency Trim Register"
|
|
group.byte 0x1F7++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT18,IMO Frequency Trim Register"
|
|
group.byte 0x1F8++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT19,IMO Frequency Trim Register"
|
|
group.byte 0x1F9++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT20,IMO Frequency Trim Register"
|
|
group.byte 0x1FA++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT21,IMO Frequency Trim Register"
|
|
group.byte 0x1FB++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT22,IMO Frequency Trim Register"
|
|
group.byte 0x1FC++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT23,IMO Frequency Trim Register"
|
|
group.byte 0x1FD++0x00
|
|
line.byte 0x00 "IMO_TRIM_LT24,IMO Frequency Trim Register"
|
|
group.word 0x1FE++0x01
|
|
line.word 0x00 "CHECKSUM,Boot Checksum"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPCIF (System Performance Controller Interface)"
|
|
base ad:0x40110000
|
|
width 19.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "GEOMETRY,Flash/NVL Geometry Information"
|
|
bitfld.long 0x00 31. " DE_CPD_LP ,Busy wait loop copy to SRAM" "Not copied,Copied"
|
|
sif cpuis("CY8C4*-BL*")
|
|
hexmask.long.byte 0x00 24.--30. 1. " NVL ,NVLatch size in byte multiples"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
rbitfld.long 0x00 22.--23. " FLASH_ROW ,Page size in 64 byte multiplies" "64 bytes,128 bytes,192 bytes,256 bytes"
|
|
rbitfld.long 0x00 20.--21. " NUM_FLASH ,Number of flash macros" "0,1,2,3"
|
|
sif cpuis("CY8C4*-BL*")
|
|
rbitfld.long 0x00 16.--19. " SFLASH ,Supervisory flash capacity in 256 byte multiplies" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " FLASH ,Regular flash capacity in 256 byte multiplies"
|
|
else
|
|
rbitfld.long 0x00 14.--19. " SFLASH ,Supervisory flash capacity in 256 byte multiplies" "256 bytes,512 bytes,768 bytes,1024 bytes,1280 bytes,1536 bytes,1792 bytes,2048 bytes,2304 bytes,2560 bytes,2816 bytes,3072 bytes,3328 bytes,3584 bytes,3840 bytes,4096 bytes,4352 bytes,4608 bytes,4864 bytes,5120 bytes,5376 bytes,5632 bytes,5888 bytes,6144 bytes,6400 bytes,6656 bytes,6912 bytes,7168 bytes,7424 bytes,7680 bytes,7936 bytes,8192 bytes,8448 bytes,8704 bytes,8960 bytes,9216 bytes,9472 bytes,9728 bytes,9984 bytes,10240 bytes,10496 bytes,10752 bytes,11008 bytes,11264 bytes,11520 bytes,11776 bytes,12032 bytes,12288 bytes,12544 bytes,12800 bytes,13056 bytes,13312 bytes,13568 bytes,13824 bytes,14080 bytes,14336 bytes,14592 bytes,14848 bytes,15104 bytes,15360 bytes,15616 bytes,15872 bytes,16128 bytes,16384 bytes"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--13. 1. " FLASH ,Regular flash capacity in 256 byte multiplies"
|
|
endif
|
|
group.long 0x7F0++0x0B
|
|
line.long 0x00 "INTR,SPCIF Interrupt Request Register"
|
|
eventfld.long 0x00 0. " TIMER ,Timer count value reaches '0'" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,SPCIF Interrupt Set Request Register"
|
|
bitfld.long 0x04 0. " TIMER ,Set corresponding INTR field" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,SPCIF Interrupt Mask Register"
|
|
bitfld.long 0x08 0. " TIMER ,Mask for corresponding field in INTR register" "Not masked,Masked"
|
|
rgroup.long 0x7FC++0x03
|
|
line.long 0x00 "INTR_MASKED,SPCIF Interrupt Masked Request Register"
|
|
bitfld.long 0x00 0. " TIMER ,Logical AND of corresponding and mask field" "Not masked,Masked"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SRSS (System Resources Sub System)"
|
|
base ad:0x40030000
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PWR_CONTROL,Power Mode Control"
|
|
bitfld.long 0x00 23. " EXT_VCCD ,External VCCD" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 17. " OVER_TEMP_THRESH ,Over-temperature threshold" "Occurs between 120C and 125C,Occurs between 60C and 75C"
|
|
bitfld.long 0x00 16. " OVER_TEMP_EN ,Enables the die over temperature sensor" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " LPM_READY ,Indicates whether the low power mode regulator is ready to enter DEEPSLEEP mode" "Enter SLEEP mode,Normal operation"
|
|
rbitfld.long 0x00 4. " DEBUG_SESSION ,Indicates whether a debug session is active" "NO_SESSION,SESSION_ACTIVE"
|
|
rbitfld.long 0x00 0.--3. " POWER_MODE ,Current power mode of the device" "RESET,ACTIVE,SLEEP,DEEP_SLEEP,?..."
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PWR_KEY_DELAY,Power System Key Register"
|
|
hexmask.long.word 0x00 0.--9. 1. " WAKEUP_HOLDOFF ,Delay to wait for references to settle on wake up from DeepSleep"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TST_MODE,Test Mode Control Register"
|
|
bitfld.long 0x00 31. " TEST_MODE ,Setting this bit will prevent bootrom from yielding execution to flash image" "Normal mode,Test mode"
|
|
bitfld.long 0x00 28. " BLOCK_ALT_XRES ,Relevant only for parts that have the alternate XRES mechanism of overloading a GPIO pin temporarily as alternate XRES during test" "Not blocked,Blocked"
|
|
rbitfld.long 0x00 2. " SWD_CONNECTED ,SWD connected" "Not active,Active"
|
|
group.long 0x28++0x0B
|
|
line.long 0x00 "CLK_SELECT,Clock Select Register"
|
|
bitfld.long 0x00 6.--7. " SYSCLK_DIV ,Select clk_sys prescaler value" "NO_DIV,DIV_BY_2,DIV_BY_4,DIV_BY_8"
|
|
bitfld.long 0x00 4.--5. " PUMP_SEL ,Selects clock source for charge pump clock" "GND,IMO,HFCLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " HFCLK_DIV ,Selects HFCLK predivider value" "NO_DIV,DIV_BY_2,DIV_BY_4,DIV_BY_8"
|
|
bitfld.long 0x00 0.--1. " HFCLK_SEL ,Selects a source for HFCLK" "IMO,EXTCLK,?..."
|
|
line.long 0x04 "CLK_ILO_CONFIG,ILO Configuration"
|
|
bitfld.long 0x04 31. " ENABLE ,Master enable for ILO oscillator" "Disabled,Enabled"
|
|
line.long 0x08 "CLK_IMO_CONFIG,IMO Configuration"
|
|
bitfld.long 0x08 31. " ENABLE ,Master enable for IMO oscillator" "Disabled,Enabled"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "WDT_DISABLE_KEY,Watchdog Disable Key Register"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "WDT_COUNTER,Watchdog Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " COUNTER ,Current value of WDT counter"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "WDT_MATCH,Watchdog Match Register"
|
|
bitfld.long 0x00 16.--19. " IGNORE_BITS ,The number of MSB bits of the watchdog timer that are NOT checked against MATCH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. " MATCH ,Match value for watchdog counter"
|
|
group.long 0x44++0x0B
|
|
line.long 0x00 "INTR,SRSS Interrupt Register"
|
|
eventfld.long 0x00 1. " TEMP_HIGH ,Regulator Over-temp interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " WDT_MATCH ,WDT interrupt request" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,SRSS Interrupt Set Register"
|
|
bitfld.long 0x04 1. " TEMP_HIGH ,Sets overtemp interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,SRSS Interrupt Mask Register"
|
|
bitfld.long 0x08 1. " TEMP_HIGH ,Masks REG_OVERTEMP interrupt" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " WDT_MATCH ,Clering this bit will not forward the interrupt to the CPU" "Not masked,Masked"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "RES_CAUSE,Reset Cause Observation Register"
|
|
eventfld.long 0x00 4. " RESET_SOFT ,Cortex-M0 requested a system reset through it's SYSRESETREQ" "No reset,Reset"
|
|
eventfld.long 0x00 3. " RESET_PROT_FAULT ,A protection violation occurred that requires a RESET" "No reset,Reset"
|
|
eventfld.long 0x00 0. " RESET_WDT ,A watchdog timer reset has occurred since last power cycle" "No reset,Reset"
|
|
group.long 0xF08++0x0B
|
|
line.long 0x00 "CLK_IMO_SELECT,IMO Frequency Select Register"
|
|
bitfld.long 0x00 0.--2. " FREQ ,Select operation frequency" "24_MHZ,28_MHZ,32_MHZ,36_MHZ,40_MHZ,44_MHZ,48_MHZ,?..."
|
|
line.long 0x04 "CLK_IMO_TRIM1,IMO Trim Register"
|
|
hexmask.long.byte 0x04 0.--7. 0x01 " OFFSET ,Frequency trim bits"
|
|
line.long 0x08 "CLK_IMO_TRIM2,IMO Trim Register"
|
|
bitfld.long 0x08 0.--2. " FSOFFSET ,Frequency trim bits" "0,1,2,3,4,5,6,7"
|
|
group.long 0xF18++0x03
|
|
line.long 0x00 "CLK_IMO_TRIM3,IMO Trim Register"
|
|
bitfld.long 0x00 5.--6. " TCTRIM ,IMO temperature compensation trim" "0,1,2,3"
|
|
bitfld.long 0x00 0.--4. " STEPSIZE ,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TCPWM (Timer Counter PWM)"
|
|
base ad:0x40010000
|
|
width 12.
|
|
sif (cpuis("CY8C4A24*"))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,TCPWM Control Register 0"
|
|
bitfld.long 0x00 3. " COUNTER_ENABLED[3] ,Counter enable for counter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " COUNTER_ENABLED[2] ,Counter enable for counter 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COUNTER_ENABLED[1] ,Counter enable for counter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COUNTER_ENABLED[0] ,Counter enable for counter 0" "Disabled,Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMD,TCPWM Command Register"
|
|
bitfld.long 0x00 27. " COUNTER_START[3] ,Counter 3 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 26. " COUNTER_START[2] ,Counter 2 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 25. " COUNTER_START[1] ,Counter 1 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 24. " COUNTER_START[0] ,Counter 0 SW start trigger" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 19. " COUNTER_STOP[3] ,Counter 3 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 18. " COUNTER_STOP[2] ,Counter 2 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 17. " COUNTER_STOP[1] ,Counter 1 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 16. " COUNTER_STOP[0] ,Counter 0 SW stop trigger" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COUNTER_RELOAD[3] ,Counter 3 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 10. " COUNTER_RELOAD[2] ,Counter 2 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 9. " COUNTER_RELOAD[1] ,Counter 1 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 8. " COUNTER_RELOAD[0] ,Counter 0 SW reload trigger" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COUNTER_CAPTURE[3] ,Counter 3 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 2. " COUNTER_CAPTURE[2] ,Counter 2 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 1. " COUNTER_CAPTURE[1] ,Counter 1 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 0. " COUNTER_CAPTURE[0] ,Counter 0 SW capture trigger" "Not captured,Captured"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "INTR_CAUSE,TCPWM Counter Interrupt Cause Register"
|
|
bitfld.long 0x00 3. " COUNTER_INT[3] ,Counter 3 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " COUNTER_INT[2] ,Counter 2 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " COUNTER_INT[1] ,Counter 1 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " COUNTER_INT[0] ,Counter 0 interrupt signal active" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CTRL,TCPWM Control Register 0"
|
|
bitfld.long 0x00 7. " COUNTER_ENABLED[7] ,Counter enable for counter 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " COUNTER_ENABLED[6] ,Counter enable for counter 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " COUNTER_ENABLED[5] ,Counter enable for counter 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " COUNTER_ENABLED[4] ,Counter enable for counter 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COUNTER_ENABLED[3] ,Counter enable for counter 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " COUNTER_ENABLED[2] ,Counter enable for counter 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " COUNTER_ENABLED[1] ,Counter enable for counter 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " COUNTER_ENABLED[0] ,Counter enable for counter 0" "Disabled,Enabled"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMD,TCPWM Command Register"
|
|
bitfld.long 0x00 31. " COUNTER_START[7] ,Counter 7 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 30. " COUNTER_START[6] ,Counter 6 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 29. " COUNTER_START[5] ,Counter 5 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 28. " COUNTER_START[4] ,Counter 4 SW start trigger" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 27. " COUNTER_START[3] ,Counter 3 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 26. " COUNTER_START[2] ,Counter 2 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 25. " COUNTER_START[1] ,Counter 1 SW start trigger" "Not started,Started"
|
|
bitfld.long 0x00 24. " COUNTER_START[0] ,Counter 0 SW start trigger" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 23. " COUNTER_STOP[7] ,Counter 7 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 22. " COUNTER_STOP[6] ,Counter 6 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 21. " COUNTER_STOP[5] ,Counter 5 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 20. " COUNTER_STOP[4] ,Counter 4 SW stop trigger" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 19. " COUNTER_STOP[3] ,Counter 3 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 18. " COUNTER_STOP[2] ,Counter 2 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 17. " COUNTER_STOP[1] ,Counter 1 SW stop trigger" "Not stopped,Stopped"
|
|
bitfld.long 0x00 16. " COUNTER_STOP[0] ,Counter 0 SW stop trigger" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 15. " COUNTER_RELOAD[7] ,Counter 7 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 14. " COUNTER_RELOAD[6] ,Counter 6 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 13. " COUNTER_RELOAD[5] ,Counter 5 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 12. " COUNTER_RELOAD[4] ,Counter 4 SW reload trigger" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COUNTER_RELOAD[3] ,Counter 3 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 10. " COUNTER_RELOAD[2] ,Counter 2 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 9. " COUNTER_RELOAD[1] ,Counter 1 SW reload trigger" "Not reloaded,Reloaded"
|
|
bitfld.long 0x00 8. " COUNTER_RELOAD[0] ,Counter 0 SW reload trigger" "Not reloaded,Reloaded"
|
|
textline " "
|
|
bitfld.long 0x00 7. " COUNTER_CAPTURE[7] ,Counter 7 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 6. " COUNTER_CAPTURE[6] ,Counter 6 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 5. " COUNTER_CAPTURE[5] ,Counter 5 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 4. " COUNTER_CAPTURE[4] ,Counter 4 SW capture trigger" "Not captured,Captured"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COUNTER_CAPTURE[3] ,Counter 3 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 2. " COUNTER_CAPTURE[2] ,Counter 2 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 1. " COUNTER_CAPTURE[1] ,Counter 1 SW capture trigger" "Not captured,Captured"
|
|
bitfld.long 0x00 0. " COUNTER_CAPTURE[0] ,Counter 0 SW capture trigger" "Not captured,Captured"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "INTR_CAUSE,TCPWM Counter Interrupt Cause Register"
|
|
bitfld.long 0x00 7. " COUNTER_INT[7] ,Counter 7 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 6. " COUNTER_INT[6] ,Counter 6 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " COUNTER_INT[5] ,Counter 5 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " COUNTER_INT[4] ,Counter 4 interrupt signal active" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " COUNTER_INT[3] ,Counter 3 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " COUNTER_INT[2] ,Counter 2 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " COUNTER_INT[1] ,Counter 1 interrupt signal active" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " COUNTER_INT[0] ,Counter 0 interrupt signal active" "No interrupt,Interrupt"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PERITGC (PERI Trigger Group Control)"
|
|
base ad:0x40002000
|
|
width 24.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "TR_GROUP0_TR_OUT_CTL0,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "TR_GROUP0_TR_OUT_CTL1,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "TR_GROUP0_TR_OUT_CTL2,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "TR_GROUP0_TR_OUT_CTL3,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TR_GROUP0_TR_OUT_CTL4,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TR_GROUP0_TR_OUT_CTL5,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TR_GROUP0_TR_OUT_CTL6,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TR_GROUP0_TR_OUT_CTL7,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "TR_GROUP1_TR_OUT_CTL0,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "TR_GROUP1_TR_OUT_CTL1,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "TR_GROUP1_TR_OUT_CTL2,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "TR_GROUP1_TR_OUT_CTL3,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "TR_GROUP1_TR_OUT_CTL4,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "TR_GROUP1_TR_OUT_CTL5,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "TR_GROUP1_TR_OUT_CTL6,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "TR_GROUP2_TR_OUT_CTL0,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "TR_GROUP2_TR_OUT_CTL1,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "TR_GROUP2_TR_OUT_CTL2,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "TR_GROUP2_TR_OUT_CTL3,Trigger Control Register"
|
|
bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "TR_GROUP3_TR_OUT_CTL0,Trigger Control Register"
|
|
bitfld.long 0x00 0.--2. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "TR_GROUP3_TR_OUT_CTL1,Trigger Control Register"
|
|
bitfld.long 0x00 0.--2. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "TR_GROUP3_TR_OUT_CTL2,Trigger Control Register"
|
|
bitfld.long 0x00 0.--2. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60C++0x03
|
|
line.long 0x00 "TR_GROUP3_TR_OUT_CTL3,Trigger Control Register"
|
|
bitfld.long 0x00 0.--2. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7"
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL0,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL1,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL2,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL3,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL4,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x814++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL5,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL6,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x81C++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL7,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x820++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL8,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x824++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL9,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x828++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL10,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x82C++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL11,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x830++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL12,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x834++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL13,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x838++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL14,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x83C++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL15,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x840++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL16,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL17,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x848++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL18,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x84C++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL19,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x850++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL20,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x854++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL21,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x858++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL22,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x85C++0x03
|
|
line.long 0x00 "TR_GROUP4_TR_OUT_CTL23,Trigger Control Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UAB (Universal Analog Block)"
|
|
base ad:0x40340000
|
|
width 17.
|
|
if (((per.l(ad:0x40340000))&0x80000000)==0x80000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UAB_CTRL,Global UAB Control"
|
|
bitfld.long 0x00 31. " ENABLED ,UAB enable" "Disabled,Enabled"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "INTR,Interrupt Request Register"
|
|
eventfld.long 0x00 18. " DC1_RES ,Decimator 1 result interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 17. " VDAC1_EMPTY ,VDAC 1 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " COMP1 ,Comparator 1 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " DC0_RES ,Decimator 0 result interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " VDAC0_EMPTY ,VDAC 0 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " COMP0 ,Comparator 0 interrupt" "No interrupt,Interrupt"
|
|
line.long 0x04 "INTR_SET,Interrupt Request Set Register"
|
|
bitfld.long 0x04 18. " DC1_RES_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 17. " VDAC1_EMPTY_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 16. " COMP1_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " DC0_RES_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x04 1. " VDAC0_EMPTY_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " COMP0_SET ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt"
|
|
line.long 0x08 "INTR_MASK,Interrupt Request Mask"
|
|
bitfld.long 0x08 18. " DC1_RES_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 17. " VDAC1_EMPTY_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 16. " COMP1_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 2. " DC0_RES_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x08 1. " VDAC0_EMPTY_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
bitfld.long 0x08 0. " COMP0_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "INTR_MASKED,Interrupt Request Masked"
|
|
bitfld.long 0x00 18. " DC1_RES_MASKED ,Logical AND of corresponding request and mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 17. " VDAC1_EMPTY_MASKED ,Logical AND of corresponding request and mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 16. " COMP1_MASKED ,Logical AND of corresponding request and mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " DC0_RES_MASKED ,Logical AND of corresponding request and mask bit" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " VDAC0_EMPTY_MASKED ,Logical AND of corresponding request and mask bit" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " COMP0_MASKED ,Logical AND of corresponding request and mask bit" "Not masked,Masked"
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "OA0_CTRL,Opamp/Comparator/Buffer Controls"
|
|
bitfld.long 0x00 30.--31. " H0_PWR ,UAB half power profile" "NORMAL,ULTRA_LOW,ULTRA_HIGH,?..."
|
|
bitfld.long 0x00 25. " SPARE0_EN ,Spare reference enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SW_GG ,Connect outputs of Agnd0 and Agnd1 buffer" "Not connected,Connected"
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bitfld.long 0x00 23. " AGND0_PTS ,Pull Agnd0 buffer output to ADDA" "Not pulled,Pulled"
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textline " "
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bitfld.long 0x00 20.--22. " AGND0_PWR ,Agnd0 buffer power level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19. " REF0_PTS ,Reference0 buffer output to VDDA" "Not pulled,Pulled"
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bitfld.long 0x00 16.--18. " REF0_PWR ,Reference0 buffer power level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 14. " CMP0_DSI_LEVEL ,Comparator0 output" "Pulse,Level"
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textline " "
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bitfld.long 0x00 12.--13. " CMP0_EDGE ,Comparator0 edge detect for output and interrupt" "DISABLE,RISING,FALLING,BOTH"
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bitfld.long 0x00 8.--10. " CMP0_PWR ,Comparator0 power level" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. " OA0_PWR ,Opamp0 power level" "0,1,2,3,4,5,6,7"
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line.long 0x04 "CAP_CTRL0,Capacitance Controls"
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bitfld.long 0x04 30.--31. " DAC0_MODE ,DAC mode" "UNSIGNED12,VIRT_SIGNED12,SIGNED13,?..."
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bitfld.long 0x04 29. " DAC0_MODE_EN ,DAC0 mode enable" "Disabled,Enabled"
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bitfld.long 0x04 28. " FRC0_SIGN_BIT ,Forces the sign bit to be 1 in DAC mode" "Not forced,Forced"
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bitfld.long 0x04 6. " CC0_GND ,Ground unused caps of CC0 array" "Leave unused,Ground unused"
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textline " "
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bitfld.long 0x04 5. " CB0_GND ,Ground unused caps of CB0 array" "Leave unused,Ground unused"
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line.long 0x08 "CAP_ABCF0_VAL,Capacitance Values For CA0 CB0 CC0 And CF0"
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bitfld.long 0x08 24.--28. " CF0_VAL ,Cap F0 value" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64"
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bitfld.long 0x08 16.--21. " CC0_VAL ,Cap C0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 13. " CB0_64 ,Enable 64th cap of CB0 array" "Disabled,Enabled"
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bitfld.long 0x08 12. " SIGN0_VAL ,Sign bit value" "Unsigned,Signed"
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textline " "
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bitfld.long 0x08 6.--11. " CA0_VAL ,Cap A0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 0.--5. " CB0_VAL ,Cap B0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x0C "CAP_AB0_VAL_NXT,Next Capacitance Values For CA0 And CB0"
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bitfld.long 0x0C 12. " SIGN0_VAL ,Sign bit value" "Unsigned,Signed"
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bitfld.long 0x0C 6.--11. " CA0_VAL ,Cap A0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 0.--5. " CB0_VAL ,Cap B0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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line.long 0x10 "CAP_CF0_VAL_NXT,Next Capacitance Values For CC0 And CF0"
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bitfld.long 0x10 31. " CF0_VAL_UPDATE ,Cap F0 value update" "Not updated,Updated"
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bitfld.long 0x10 30. " CC0_VAL_UPDATE ,Cap C0 value update" "Not updated,Updated"
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bitfld.long 0x10 24.--28. " CF0_VAL ,Cap F0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16.--21. " CC0_VAL ,Cap C0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x220++0x07
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line.long 0x00 "STARTUP_DELAY0,Startup Delay"
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bitfld.long 0x00 16. " ALIGN_MODE ,Alignment mode" "Scheduled,Unscheduled"
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hexmask.long.word 0x00 0.--15. 1. " STARTUP_DELAY ,Startup delay to synchronize the UAB-SAR interface"
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line.long 0x04 "SUBSAMPLE_CTRL0,Subsample Control"
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hexmask.long.byte 0x04 8.--15. 1. " SUBSAMPLE_INIT ,Initial value of the subsampling down counter"
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hexmask.long.byte 0x04 0.--7. 1. " SUBSAMPLE ,Subsampling"
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group.long 0x230++0x07
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line.long 0x00 "SW_STATIC0,Static Switches For Half 0 Of The UAB"
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bitfld.long 0x00 29. " STRB_RST0_EN ,Enable VDAC strobe or UAB Analog-reset" "VDAC,Analog"
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bitfld.long 0x00 24.--28. " STRB_RST0_SEL ,Select source either for VDAC strobe or Analog-reset to discharge all caps" "Decimator0 half 0 analog,Decimator0 half 1 analog,2,3,4,5,6,7,Trigger 0,Trigger 1 input,Trigger 2 input,Trigger 3 input,Trigger 4 input,Trigger 5 input,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--19. " RMB0_BITS ,Risk mitigation bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 13. " EARLY_P0O ,OUT0 to VOUT0 switch timing" "Regular,Early"
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textline " "
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bitfld.long 0x00 12. " EARLY_P0S ,OUT0 to sum0 switch timing" "Regular,Early"
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bitfld.long 0x00 10. " SW_Q0T ,OUT1 to cmp0.vminus" "Not switched,Switched"
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bitfld.long 0x00 9. " SW_G0T ,Agnd0 to cmp0.vminus" "Not switched,Switched"
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bitfld.long 0x00 8. " SW_R0T ,REF0 to cmp0.vminus" "Not switched,Switched"
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textline " "
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bitfld.long 0x00 5. " SW_G0G ,Agnd0 to oa0.vplus" "Not switched,Switched"
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bitfld.long 0x00 4. " SW_R0G ,REF0 to oa0.vplus" "Not switched,Switched"
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bitfld.long 0x00 3. " SW_G03 ,VIN03 to oa0.vplus" "Not switched,Switched"
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bitfld.long 0x00 2. " SW_G02 ,VIN02 to oa0.vplus" "Not switched,Switched"
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textline " "
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bitfld.long 0x00 1. " SW_G01 ,VIN01 to oa0.vplus" "Not switched,Switched"
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bitfld.long 0x00 0. " SW_G00 ,VIN00 to oa0.vplus" "Not switched,Switched"
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line.long 0x04 "SW_MODBIT_SRC0,Select Source Of Modbit For A/B/C Branches Of Half 0"
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bitfld.long 0x04 8.--12. " MODBIT1_SRC0_SEL ,Select source of modbit for C branch" "UAB0 half 0 comparator,UAB0 half 1 comparator,,,,,,,Trigger 0 input,Trigger 1 input,Trigger 2 input,Trigger 3 input,Trigger 4 input,Trigger 5 input,,,,,,,,,,,,,,,,,,SIGN0_VAL"
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bitfld.long 0x04 0.--4. " MODBIT0_SRC0_SEL ,Select source of modbit for A & B branch" "UAB0 half 0 comparator,UAB0 half 1 comparator,,,,,,,Trigger 0 input,Trigger 1 input,Trigger 2 input,Trigger 3 input,Trigger 4 input,Trigger 5 input,,,,,,,,,,,,,,,,,,SIGN0_VAL"
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group.long 0x240++0x0B
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line.long 0x00 "SW_CA0_IN0,Cap A0 Input Switches Set 0"
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bitfld.long 0x00 20.--23. " SW_A0Q ,OUT1 to cap A0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " SW_A0P ,OUT0 to cap A0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. " SW_A03_CMP ,VIN03 to cap A0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SW_A02_CMP ,VIN02 to cap A0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 4.--7. " SW_A01_CMP ,VIN01 to cap A0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SW_A00_CMP ,VIN00 to cap A0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "SW_CA0_IN1,Cap A0 Input Switches Set 1"
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bitfld.long 0x04 12.--15. " SW_A0V_CMP ,VSS to cap A0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 8.--11. " SW_A0G_CMP ,Agnd0 to cap A0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 4.--7. " SW_A0R_CMP ,REF0 to cap A0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " SW_AA ,Cap A0 input to cap A1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "SW_CA0_TOP,Cap A0 Top Plate Switches"
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bitfld.long 0x08 16.--19. " SW_S0A ,Cap A0 top plate to SUM0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 8.--11. " SW_V0A_CMP ,Cap A0 top plate to VSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4.--7. " SW_G0A_CMP ,Cap A0 top plate to Agnd0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 0.--3. " SW_R0A_CMP ,Cap A0 top plate to REF0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x250++0x0B
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line.long 0x00 "SW_CB0_IN0,Cap B0 Input Switches Set 0"
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bitfld.long 0x00 20.--23. " SW_B0Q ,OUT1 to cap B0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " SW_B0P ,OUT0 to cap B0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. " SW_B03_CMP ,VIN03 to cap B0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SW_B02_CMP ,VIN02 to cap B0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 4.--7. " SW_B01_CMP ,VIN01 to cap B0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SW_B00_CMP ,VIN00 to cap B0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "SW_CB0_IN1,Cap B0 Input Switches Set 1"
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bitfld.long 0x04 12.--15. " SW_B0V_CMP ,VSS to cap B0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 8.--11. " SW_B0G_CMP ,Agnd0 to cap B0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 4.--7. " SW_B0R_CMP ,REF0 to cap B0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " SW_BB ,Cap B0 input to cap B1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "SW_CB0_TOP,Cap A0 Top Plates Switches"
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bitfld.long 0x08 16.--19. " SW_S0B ,Cap B0 top plate to SUM0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 12.--15. " SW_T0B ,Cap B0 top plate trim/attenuation bypass" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 8.--11. " SW_V0B_CMP ,Cap B0 top plate to VSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 4.--7. " SW_G0B_CMP ,Cap B0 top plate to Agnd0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x08 0.--3. " SW_R0B_CMP ,Cap B0 top plate to REF0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x260++0x17
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line.long 0x00 "SW_CC0_IN0,Cap C0 Input Switches Set 0"
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bitfld.long 0x00 20.--23. " SW_C0Q ,OUT1 to cap C0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. " SW_C0P ,OUT0 to cap C0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. " SW_C03_CMP ,VIN03 to cap C0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. " SW_C02_CMP ,VIN02 to cap C0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x00 4.--7. " SW_C01_CMP ,VIN01 to cap C0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. " SW_C00_CMP ,VIN00 to cap C0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x04 "SW_CC0_IN1,Cap C0 Input Switches Set 1"
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bitfld.long 0x04 12.--15. " SW_C0V_CMP ,VSS to cap C0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 8.--11. " SW_C0G_CMP ,Agnd0 to cap C0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 4.--7. " SW_C0R_CMP ,REF0 to cap C0 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " SW_CC ,Cap C0 input to cap C1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "SW_CC0_TOP,Cap A0 Top Plates Switches"
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bitfld.long 0x08 20.--23. " SW_S10 ,Cap C0 top plate to SUM1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. " SW_S0C ,Cap C0 top plate to SUM0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 12.--15. " SW_T0C ,Cap C0 top plate trim/attenuation bypass" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 8.--11. " SW_V0C_CMP ,Cap C0 top plate to VSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x08 4.--7. " SW_G0C_CMP ,Cap C0 top plate to Agnd0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 0.--3. " SW_R0C_CMP ,Cap C0 top plate to REF0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x0C "SW_CF0_BOT,CAP F0 Bottom Plate And Output Switches"
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bitfld.long 0x0C 12.--15. " SW_P0O ,OUT0 TO VOUT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 8.--11. " SW_P0S ,Cap F bypass OUT0 to SUM0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 4.--7. " SW_P0F ,Cap F0 bottom plate to OUT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 0.--3. " SW_G0F ,Cap F0 bottom plate to Agnd0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x10 "SW_OTHER0,Other Clocked Controls"
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bitfld.long 0x10 28.--31. " STROBE_RST0 ,Use the positive edge of the selected clocking waveform to synchronize" "Capacitor value,UAB analog-reset,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
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bitfld.long 0x10 24.--27. " STROBE_SW0 ,Strobe for dsi_sw_ctrl update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. " TRIG0_OUT ,Trigger output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 4.--7. " VALID0 ,Valid0 output flag to indicated that VOUT0 is valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x10 0.--3. " CMP0_FF ,Clock for Flip-Flop after comparator 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x14 "SW_BOOST_CTRL0,Bootstrap Clock Control"
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bitfld.long 0x14 20.--23. " PUMP0_WAVE ,Clock for pump in half0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. " SUM0_BOOST ,Clock for boot strap master in summing node branch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 12.--15. " CF0_BOOST ,Clock for boot strap master in F branch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. " CC0_BOOST ,Clock for boot strap master in C branch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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bitfld.long 0x14 4.--7. " CB0_BOOST ,Clock for boot strap master in B branch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 0.--3. " CA0_BOOST ,Clock for boot strap master in A branch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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if (((per.l(ad:0x40340000+0x278))&0x20000000)==0x20000000)
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "SRAM0_CTRL,SRAM Programmed Size"
|
|
bitfld.long 0x00 31. " RUN ,Set to start executing the waveform" "Stop,Start"
|
|
bitfld.long 0x00 29. " TRIGGER_EN ,Enable input trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " TRIG_SEL0 ,Input trigger select" "UAB0 half 0,UAB half 1,,,,,,,Trigger 0 input,Trigger 1 input,Trigger 2 input,Trigger 3 input,Trigger 4 input,Trigger 5 input,,,,,,,,,,,,,,,,,,SAR trigger"
|
|
bitfld.long 0x00 0.--3. " LAST_STEP ,Last step of wave programmed in the SRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "SRAM0_CTRL,SRAM Programmed Size"
|
|
bitfld.long 0x00 31. " RUN ,Set to start executing the waveform" "Stop,Start"
|
|
bitfld.long 0x00 29. " TRIGGER_EN ,Enable input trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " LAST_STEP ,Last step of wave programmed in the SRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
rgroup.long 0x27C++0x03
|
|
line.long 0x00 "STAT0,Status Current SRAM Counter And Comparator"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CURR_SUBSAMPLE ,Current value of the subsampling down counter"
|
|
bitfld.long 0x00 4. " COMP ,Current comparator status" "0,1"
|
|
bitfld.long 0x00 0.--3. " CURR_STEP ,Current step executed from the SRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "SRAM00,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "SRAM01,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "SRAM02,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "SRAM03,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "SRAM04,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "SRAM05,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "SRAM06,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "SRAM07,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "SRAM08,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "SRAM09,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "SRAM010,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "SRAM011,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "SRAM012,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "SRAM013,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "SRAM014,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "SRAM015,Waveform For Half 0 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x300++0x13
|
|
line.long 0x00 "OA1_CTRL,Opamp/Comparator/Buffer Controls"
|
|
bitfld.long 0x00 30.--31. " H1_PWR ,UAB half power profile" "NORMAL,ULTRA_LOW,ULTRA_HIGH,?..."
|
|
bitfld.long 0x00 25. " SPARE1_EN ,Spare reference enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SW_RR ,Connect outputs of reference0 and reference1 buffer" "Not connected,Connected"
|
|
bitfld.long 0x00 23. " AGND1_PTS ,Pull agnd1 buffer output to VDDA" "Not pulled,Pulled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " AGND1_PWR ,Agnd1 buffer power" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 19. " REF1_PTS ,Pull the reference1 buffer output to VDDA" "Not pulled,Pulled"
|
|
bitfld.long 0x00 16.--18. " REF1_PWR ,Reference1 buffer power level" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " CTRL1_SPARE ,Spare bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CMP1_DSI_LEVEL ,Comparator trigger out level" "Pulse,Level"
|
|
bitfld.long 0x00 12.--13. " CMP1_EDGE ,Comparator1 edge detect for interrupt and trigger" "DISABLE,RISING,FALLING,BOTH"
|
|
bitfld.long 0x00 8.--10. " CMP1_PWR ,Comparator1 power level" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. " OA1_PWR ,Opamp1 power level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "CAP_CTRL1,Capacitance Controls"
|
|
bitfld.long 0x04 30.--31. " DAC1_MODE ,DAC mode" "UNSIGNED12,VIRT_SIGNED12,SIGNED13,?..."
|
|
bitfld.long 0x04 29. " DAC1_MODE_EN ,DAC1 mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " FRC1_SIGN_BIT ,Forces the sign bit to be 1 in DAC mode" "Unsigned,Signed"
|
|
bitfld.long 0x04 6. " CC1_GND ,Ground unused caps of CC1 array" "Leave unused,Ground unused"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CB1_GND ,Ground unused caps of CB1 array" "Leave unused,Ground unused"
|
|
line.long 0x08 "CAP_ABCF1_VAL,Capacitance Values For CA1 CB1 CC1 And CF1"
|
|
bitfld.long 0x08 24.--28. " CF1_VAL ,Cap F1 value" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64"
|
|
bitfld.long 0x08 16.--21. " CC1_VAL ,Cap C1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 13. " CB1_64 ,Enable 64th cap of CB1 array" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " SIGN1_VAL ,Sign bit value" "Unsigned,Signed"
|
|
textline " "
|
|
bitfld.long 0x08 6.--11. " CA1_VAL ,Cap A1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x08 0.--5. " CB1_VAL ,Cap B1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x0C "CAP_AB1_VAL_NXT,Next Capacitance Values For CA1 And CB1"
|
|
bitfld.long 0x0C 12. " SIGN1_VAL ,Sign bit value" "Unsigned,Signed"
|
|
bitfld.long 0x0C 6.--11. " CA1_VAL ,Cap A1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x0C 0.--5. " CB1_VAL ,Cap B1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x10 "CAP_CF1_VAL_NXT,Next Capacitance Values For CC1 And CF1"
|
|
bitfld.long 0x10 31. " CF1_VAL_UPDATE ,Cap F1 value update" "Not updated,Updated"
|
|
bitfld.long 0x10 30. " CC1_VAL_UPDATE ,Cap C1 value update" "Not updated,Updated"
|
|
bitfld.long 0x10 24.--28. " CF1_VAL ,Cap F1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x10 16.--21. " CC1_VAL ,Cap C1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x320++0x07
|
|
line.long 0x00 "STARTUP_DELAY1,Startup Delay"
|
|
bitfld.long 0x00 16. " ALIGN_MODE ,Alignment mode" "Scheduled,Unscheduled"
|
|
hexmask.long.word 0x00 0.--15. 1. " STARTUP_DELAY ,Startup delay to synchronize the UAB-SAR interface"
|
|
line.long 0x04 "SUBSAMPLE_CTRL1,Subsample Control"
|
|
hexmask.long.byte 0x04 8.--15. 1. " SUBSAMPLE_INIT ,Initial value of the subsampling down counter"
|
|
hexmask.long.byte 0x04 0.--7. 1. " SUBSAMPLE ,Subsampling"
|
|
group.long 0x330++0x07
|
|
line.long 0x00 "SW_STATIC1,Static Switches For Half 1 Of The UAB"
|
|
bitfld.long 0x00 29. " STRB_RST1_EN ,Enable VDAC strobe or UAB Analog-reset" "VDAC,Analog"
|
|
bitfld.long 0x00 24.--28. " STRB_RST1_SEL ,Select source either for VDAC strobe or analog-reset to discharge all caps" "Decimator0 half 0 analog,Decimator0 half 1 analog,2,3,4,5,6,7,Trigger 0,Trigger 1 input,Trigger 2 input,Trigger 3 input,Trigger 4 input,Trigger 5 input,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 13. " EARLY_Q1O ,OUT1 to VOUT1 switch timing" "Regular,Early"
|
|
bitfld.long 0x00 12. " EARLY_Q1S ,OUT to Sum1 switch timing" "Regular,Early"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SW_P1T ,OUT0 to cmp1.vminus" "Not switched,Switched"
|
|
bitfld.long 0x00 9. " SW_G1T ,Agnd1 to cmp1.vminus" "Not switched,Switched"
|
|
bitfld.long 0x00 8. " SW_R1T ,REF1 to cmp1.vminus" "Not switched,Switched"
|
|
bitfld.long 0x00 5. " SW_G1G ,Agnd1 to OA1.vplus" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SW_R1G ,REF1 to OA1.vplus" "Not switched,Switched"
|
|
bitfld.long 0x00 3. " SW_G13 ,VIN13 to OA1.vplus" "Not switched,Switched"
|
|
bitfld.long 0x00 2. " SW_G12 ,VIN12 to OA1.vplus" "Not switched,Switched"
|
|
bitfld.long 0x00 1. " SW_G11 ,VIN11 to OA1.vplus" "Not switched,Switched"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SW_G10 ,VIN10 to OA1.vplus" "Not switched,Switched"
|
|
line.long 0x04 "SW_MODBIT_SRC1,Select Source Of Modbit For A/B/C Branches Of Half 1"
|
|
bitfld.long 0x04 8.--12. " MODBIT1_SRC1_SEL ,Select source of modbit for C branch" "UAB0 half 0 comparator,UAB0 half 1 comparator,,,,,,,Trigger 0 input,Trigger 1 input,Trigger 2 input,Trigger 3 input,Trigger 4 input,Trigger 5 input,,,,,,,,,,,,,,,,,,SIGN1_VAL"
|
|
bitfld.long 0x04 0.--4. " MODBIT0_SRC1_SEL ,Select source of modbit for A & B branch" "UAB0 half 0 comparator,UAB0 half 1 comparator,,,,,,,Trigger 0 input,Trigger 1 input,Trigger 2 input,Trigger 3 input,Trigger 4 input,Trigger 5 input,,,,,,,,,,,,,,,,,,SIGN1_VAL"
|
|
group.long 0x340++0x0B
|
|
line.long 0x00 "SW_CA1_IN0,Cap A1 Input Switches Set 0"
|
|
bitfld.long 0x00 20.--23. " SW_A1Q ,OUT0 to cap A1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SW_A1P ,OUT1 to cap A1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " SW_A13_CMP ,VIN13 to cap A1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " SW_A12_CMP ,VIN12 to cap A1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SW_A11_CMP ,VIN11 to cap A1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " SW_A10_CMP ,VIN10 to cap A1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "SW_CA1_IN1,Cap A1 Input Switches Set 1"
|
|
bitfld.long 0x04 12.--15. " SW_A1V_CMP ,VSS to cap A1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " SW_A1G_CMP ,Agnd1 to cap A1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " SW_A1R_CMP ,REF1 to cap A1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SW_CA1_TOP,Cap A1 Top Plate Switches"
|
|
bitfld.long 0x08 16.--19. " SW_S1A ,Cap A1 top plate to SUM1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " SW_V1A_CMP ,Cap A1 top plate to VSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 4.--7. " SW_G1A_CMP ,Cap A1 top plate to Agnd1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " SW_R1A_CMP ,Cap A1 top plate to REF1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x350++0x0B
|
|
line.long 0x00 "SW_CB1_IN0,Cap B1 Input Switches Set 0"
|
|
bitfld.long 0x00 20.--23. " SW_B1Q ,OUT0 to cap B1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SW_B1P ,OUT1 to cap B1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " SW_B13_CMP ,VIN13 to cap B1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " SW_B12_CMP ,VIN12 to cap B1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SW_B11_CMP ,VIN11 to cap B1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " SW_B10_CMP ,VIN10 to cap B1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "SW_CB1_IN1,Cap B1 Input Switches Set 1"
|
|
bitfld.long 0x04 12.--15. " SW_B1V_CMP ,VSS to cap B1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " SW_B1G_CMP ,Agnd1 to cap B1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " SW_B1R_CMP ,REF1 to cap B1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SW_CB1_TOP,Cap A1 Top Plates Switches"
|
|
bitfld.long 0x08 16.--19. " SW_S1B ,Cap B1 top plate to SUM1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 12.--15. " SW_T1B ,Cap B1 top plate trim/attenuation bypass" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " SW_V1B_CMP ,Cap B1 top plate to VSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 4.--7. " SW_G1B_CMP ,Cap B1 top plate to Agnd1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " SW_R1B_CMP ,Cap B1 top plate to REF1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x360++0x1B
|
|
line.long 0x00 "SW_CC1_IN0,Cap C1 Input Switches Set 0"
|
|
bitfld.long 0x00 20.--23. " SW_C1Q ,OUT0 to cap C1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. " SW_C1P ,OUT1 to cap C1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " SW_C13_CMP ,VIN13 to cap C1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. " SW_C12_CMP ,VIN12 to cap C1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SW_C11_CMP ,VIN11 to cap C1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " SW_C10_CMP ,VIN10 to cap C1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "SW_CC1_IN1,Cap C1 Input Switches Set 1"
|
|
bitfld.long 0x04 12.--15. " SW_C1V_CMP ,VSS to cap C1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 8.--11. " SW_C1G_CMP ,Agnd1 to cap C1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 4.--7. " SW_C1R_CMP ,REF1 to cap C1 input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "SW_CC1_TOP,Cap A1 Top Plates Switches"
|
|
bitfld.long 0x08 20.--23. " SW_S01 ,Cap C1 top plate to SUM0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 16.--19. " SW_S1C ,Cap C1 top plate to SUM1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 12.--15. " SW_T1C ,Cap C1 top plate trim/attenuation bypass" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 8.--11. " SW_V1C_CMP ,Cap C1 top plate to VSS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " SW_G1C_CMP ,Cap C1 top plate to Agnd1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " SW_R1C_CMP ,Cap C1 top plate to REF1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "SW_CF1_BOT,CAP F1 Bottom Plate And Output Switches"
|
|
bitfld.long 0x0C 12.--15. " SW_Q1O ,OUT1 TO VOUT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 8.--11. " SW_Q1S ,Cap F bypass OUT1 to SUM1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 4.--7. " SW_Q1F ,Cap F1 bottom plate to OUT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0C 0.--3. " SW_G1F ,Cap F1 bottom plate to Agnd1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "SW_OTHER1,Other Clocked Controls"
|
|
bitfld.long 0x10 28.--31. " STROBE_RST1 ,Use the positive edge of the selected clocking waveform to synchronize" "Capacitor value,UAB analog-reset,2,3,4,5,6,7,8,9,10,11,12,13,14,?..."
|
|
bitfld.long 0x10 24.--27. " STROBE_SW1 ,Strobe for dsi_sw_ctrl update" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. " TRIG1_OUT ,Trigger output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 4.--7. " VALID1 ,Valid1 output flag to indicated that VOUT1 is valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 0.--3. " CMP1_FF ,Clock for Flip-Flop after comparator 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x14 "SW_BOOST_CTRL1,Bootstrap Clock Control"
|
|
bitfld.long 0x14 20.--23. " PUMP1_WAVE ,Clock for pump in half1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 16.--19. " SUM1_BOOST ,Clock for boot strap master in summing node branch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 12.--15. " CF1_BOOST ,Clock for boot strap master in F branch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 8.--11. " CC1_BOOST ,Clock for boot strap master in C branch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x14 4.--7. " CB1_BOOST ,Clock for boot strap master in B branch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x14 0.--3. " CA1_BOOST ,Clock for boot strap master in A branch" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
if (((per.l(ad:0x40340000+0x378))&0x20000000)==0x20000000)
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "SRAM1_CTRL,SRAM Programmed Size"
|
|
bitfld.long 0x00 31. " RUN ,Set to start executing the waveform" "Stop,Start"
|
|
bitfld.long 0x00 29. " TRIGGER_EN ,Enable input trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--28. " TRIG_SEL1 ,Input trigger select" "UAB0 half 0,UAB half 1,,,,,,,Trigger 0 input,Trigger 1 input,Trigger 2 input,Trigger 3 input,Trigger 4 input,Trigger 5 input,,,,,,,,,,,,,,,,,,SAR trigger"
|
|
bitfld.long 0x00 0.--3. " LAST_STEP ,Last step of wave programmed in the SRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x378++0x03
|
|
line.long 0x00 "SRAM1_CTRL,SRAM Programmed Size"
|
|
bitfld.long 0x00 31. " RUN ,Set to start executing the waveform" "Stop,Start"
|
|
bitfld.long 0x00 29. " TRIGGER_EN ,Enable input trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " LAST_STEP ,Last step of wave programmed in the SRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
rgroup.long 0x37C++0x03
|
|
line.long 0x00 "STAT1,Status Current SRAM Counter And Comparator"
|
|
hexmask.long.byte 0x00 24.--31. 1. " CURR_SUBSAMPLE ,Current value of the subsampling down counter"
|
|
bitfld.long 0x00 4. " COMP ,Current comparator status" "0,1"
|
|
bitfld.long 0x00 0.--3. " CURR_STEP ,Current step executed from the SRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "SRAM10,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "SRAM11,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "SRAM12,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "SRAM13,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "SRAM14,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "SRAM15,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "SRAM16,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "SRAM17,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "SRAM18,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "SRAM19,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "SRAM110,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "SRAM111,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "SRAM112,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "SRAM113,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "SRAM114,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "SRAM115,Waveform For Half 1 Of The UAB"
|
|
hexmask.long.word 0x00 0.--15. 1. " WAVE_STEP ,One step of the clocking waveform sequence"
|
|
group.long 0x400++0x0F
|
|
line.long 0x00 "DECM_CTRL,Global Decimator Control"
|
|
bitfld.long 0x00 31. " ENABLED ,Decimator enable" "Disabled,Enabled"
|
|
line.long 0x04 "DC0_CTRL,Decimator0 Control"
|
|
hexmask.long.word 0x04 16.--24. 1. " DC0_RATIO ,Decimation ratio"
|
|
bitfld.long 0x04 8.--12. " DC0_SHIFT ,Shift the result right by specified amount" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x04 6.--7. " DC0_TYPE ,Decimator type" "SINC1,SINC2,SINC3,?..."
|
|
bitfld.long 0x04 4.--5. " DC0_SEL ,Source select" "UAB_H0,UAB_H1,DSI0,DSI1"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DC0_MODE ,Operation mode" "Incremental,Continuous"
|
|
bitfld.long 0x04 0. " DC0_START ,Start decimator" "Not started,Started"
|
|
line.long 0x08 "DC0_TRIG,Decimator0 Trigger Control"
|
|
bitfld.long 0x08 29. " DC0_DSI_TRIG_EN ,Decimator DSI trigger input enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 24.--28. " DC0_TRIG_SEL ,Trigger select" "UAB0 half 0,UAB half 1,,,,,,,Trigger 0 input,Trigger 1 input,Trigger 2 input,Trigger 3 input,,,,,,,,,,,,,,,,,,,,SAR trigger"
|
|
line.long 0x0C "DC0_OVR,Decimator0 Overflow Control"
|
|
bitfld.long 0x0C 0.--4. " DC0_OVR_CORR_LOC ,Bit location for overflow correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x410++0x1B
|
|
line.long 0x00 "DC0_A0,Decimator0 Accumulator 0"
|
|
line.long 0x04 "DC0_A1,Decimator0 Accumulator 1"
|
|
line.long 0x08 "DC0_DEC_CNT,Decimator0 Decimation Counter"
|
|
bitfld.long 0x08 16.--17. " DIFF_CNT ,Differentiation down counter" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--8. 1. " INT_CNT ,Integration/decimation down counter"
|
|
line.long 0x0C "DC0_TMP,Decimator0 Temporary Value For Differentiation"
|
|
line.long 0x10 "DC0_D0,Decimator0 Differentiator 0"
|
|
line.long 0x14 "DC0_D1,Decimator0 Differentiator 1"
|
|
line.long 0x18 "DC0_RES,Decimator0 Result"
|
|
group.long 0x434++0x0B
|
|
line.long 0x00 "DC1_CTRL,Decimator1 Control"
|
|
hexmask.long.word 0x00 16.--24. 1. " DC1_RATIO ,Decimation ratio"
|
|
bitfld.long 0x00 8.--12. " DC1_SHIFT ,Shift the result right by specified amount" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 7. " DC01_CHAIN ,Chain decimator0 and decimator1" "Not chained,Chained"
|
|
bitfld.long 0x00 6. " DC1_TYPE ,Decimator type" "SINC1,SINC2"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " DC1_SEL ,Source select" "UAB_H0,UAB_H1,DSI0,DSI1"
|
|
bitfld.long 0x00 1. " DC1_MODE ,Operation mode" "Incremental,Continuous"
|
|
bitfld.long 0x00 0. " DC1_START ,Start decimator" "Not started,Started"
|
|
line.long 0x04 "DC1_TRIG,Decimator1 Trigger Control"
|
|
bitfld.long 0x04 29. " DC1_DSI_TRIG_EN ,Decimator DSI trigger input enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--28. " DC1_TRIG_SEL ,Trigger select" "UAB0 half 0,UAB half 1,,,,,,,Trigger 0 input,Trigger 1 input,Trigger 2 input,Trigger 3 input,,,,,,,,,,,,,,,,,,,,SAR trigger"
|
|
line.long 0x08 "DC1_OVR,Decimator 1 Overflow Control"
|
|
bitfld.long 0x08 0.--4. " DC1_OVR_CORR_LOC ,Bit location for overflow correction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x440++0x1B
|
|
line.long 0x00 "DC1_AO,Decimator1 Accumulator 0"
|
|
line.long 0x04 "DC1_A1,Decimator1 Accumulator 1"
|
|
line.long 0x08 "DC1_DEC_CNT,Decimator1 Decimation Counter"
|
|
bitfld.long 0x08 16.--17. " DIFF_CNT ,Differentiation down counter" "0,1,2,3"
|
|
hexmask.long.word 0x08 0.--8. 1. " INT_CNT ,Integration/decimation down counter"
|
|
line.long 0x0C "DC1_TMP,Decimator1 Temporary Value For Differentiator"
|
|
line.long 0x10 "DC1_D0,Decimator1 Differentiator 0"
|
|
line.long 0x14 "DC1_D1,Decimator1 Differentiator 1"
|
|
line.long 0x18 "DC1_RES,Decimator1 Result"
|
|
group.long 0xF00++0x0F
|
|
line.long 0x00 "CAP_TRIM0,Trim For Attenuation Cap Half0"
|
|
bitfld.long 0x00 8.--10. " CCTC0_VAL ,Cap C trim 0 value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " CTBC0_VAL ,Cap B trim 0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "CAP_TRIM1,Trim For Attenuation Cap Half1"
|
|
bitfld.long 0x04 8.--10. " CCTC1_VAL ,Cap C trim 1 value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 0.--4. " CTBC1_VAL ,Cap B trim 1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "OA_TRIM0,Trim For Opamp And Buffers Half0"
|
|
bitfld.long 0x08 16.--20. " AGND0_OFFSET ,Agnd0 buffer offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 8.--12. " REF0_OFFSET ,Reference buffer offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x08 0.--3. " OA0_OFFSET ,Opamp offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0C "OA_TRIM1,Trim For Opamp And Buffers Half1"
|
|
bitfld.long 0x0C 16.--20. " AGND1_OFFSET ,Agnd1 buffer offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 8.--12. " REF1_OFFSET ,Reference buffer offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x0C 0.--3. " OA1_OFFSET ,Opamp offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "UAB_CTRL,Global UAB Control"
|
|
bitfld.long 0x00 31. " ENABLED ,UAB enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "WCO (Watch Crystal Oscillator)"
|
|
base ad:0x40060000
|
|
width 17.
|
|
if (((per.l(ad:0x40060000))&0x80000000)==0x80000000)
|
|
if (((per.l(ad:0x40060000))&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG,WCO Configuration Register"
|
|
bitfld.long 0x00 31. " IP_ENABLE ,Master enable for IP" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DPLL_ENABLE ,Enable DPLL operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ENBUS[6] ,Enable both primary beta multipliers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ENBUS[3] ,Load resistor control 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ENBUS[2] ,Load resistor control 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENBUS[1] ,Load resistor control 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENBUS[0] ,Load resistor control 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EXT_INPUT_EN ,Disables the load resistor and allows external clock input for pad_xin" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " LPM_AUTO ,Automatically control low power mode" "No LPM in DeepSleep,LPM in DeepSleep"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LPM_EN ,Force block into low power mode" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CONFIG,WCO Configuration Register"
|
|
bitfld.long 0x00 31. " IP_ENABLE ,Master enable for IP" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " DPLL_ENABLE ,Enable DPLL operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ENBUS[6] ,Enable both primary beta multipliers" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ENBUS[3] ,Load resistor control 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ENBUS[2] ,Load resistor control 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ENBUS[1] ,Load resistor control 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ENBUS[0] ,Load resistor control 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EXT_INPUT_EN ,Disables the load resistor and allows external clock input for pad_xin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LPM_EN ,Force block into low power mode" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40060000))&0x40000000)==0x40000000)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DPLL,WCO DPLL Register"
|
|
hexmask.long.word 0x00 22.--29. 0x40 " DPLL_LF_LIMIT ,Maximum IMO offset allowed"
|
|
bitfld.long 0x00 19.--21. " DPLL_LF_PGAIN ,DPLL loop filter proportional gain setting" "0.0625,0.125,0.25,0.5,1.0,2.0,4.0,8.0"
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bitfld.long 0x00 16.--18. " DPLL_LF_IGAIN ,DPLL loop filter integral gain setting" "0.0625,0.125,0.25,0.5,1.0,2.0,4.0,8.0"
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hexmask.long.word 0x00 0.--10. 1. " DPLL_MULT ,11-bit multiplier to determinate IMO frequency in multiples of the WCO frequency"
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endif
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rgroup.long 0x200++0x07
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line.long 0x00 "WDT_CTRLOW,Watchdog Counters 0/1"
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hexmask.long.word 0x00 16.--31. 1. " WDT_CTR1 ,16-bit current value of WDT counter 1"
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hexmask.long.word 0x00 0.--15. 1. " WDT_CTR0 ,16-bit current value of WDT counter 0"
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line.long 0x04 "WDT_CTRHIGH,Watchdog Counter 2"
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group.long 0x208++0x0F
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line.long 0x00 "WDT_MATCH,Watchdog Counter Match Values"
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hexmask.long.word 0x00 16.--31. 1. " WDT_MATCH1 ,16-bit match value for watchdog counter 1"
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hexmask.long.word 0x00 0.--15. 1. " WDT_MATCH0 ,16-bit match value for watchdog counter 0"
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line.long 0x04 "WDT_CONFIG,Watchdog Counters Configuration"
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bitfld.long 0x04 30.--31. " LFCLK_SEL ,Select source for LFCLK" "ILO,WCO,?..."
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bitfld.long 0x04 24.--28. " WDT_BITS2 ,Bit to observe for WDT_INT2" "Bit0 of WDT_CTR2,Bit1 of WDT_CTR2,Bit2 of WDT_CTR2,Bit3 of WDT_CTR2,Bit4 of WDT_CTR2,Bit5 of WDT_CTR2,Bit6 of WDT_CTR2,Bit7 of WDT_CTR2,Bit8 of WDT_CTR2,Bit9 of WDT_CTR2,Bit10 of WDT_CTR2,Bit11 of WDT_CTR2,Bit12 of WDT_CTR2,Bit13 of WDT_CTR2,Bit14 of WDT_CTR2,Bit15 of WDT_CTR2,Bit16 of WDT_CTR2,Bit17 of WDT_CTR2,Bit18 of WDT_CTR2,Bit19of WDT_CTR2,Bit20 of WDT_CTR2,Bit21 of WDT_CTR2,Bit22 of WDT_CTR2,Bit23 of WDT_CTR2,Bit24 of WDT_CTR2,Bit25 of WDT_CTR2,Bit26 of WDT_CTR2,Bit27 of WDT_CTR2,Bit28 of WDT_CTR2,Bit29 of WDT_CTR2,Bit30 of WDT_CTR2,Bit31 of WDT_CTR2"
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bitfld.long 0x04 16. " WDT_MODE2 ,Watchdog counter 2 mode" "NOTHING,INT"
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bitfld.long 0x04 11. " WDT_CASCADE1_2 ,Cascade watchdog counters 1 2" "Independent,Cascade"
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textline " "
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bitfld.long 0x04 10. " WDT_CLEAR1 ,Clear watchdog counter when WDT_CTR1=WDT_MATCH1" "Free running counter,Clear on match"
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bitfld.long 0x04 8.--9. " WDT_MODE1 ,Watchdog counter action on match" "NOTHING,INT,RESET,INT_THEN_RESET"
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bitfld.long 0x04 3. " WDT_CASCADE0_1 ,Cascade watchdog counters 0 1" "Independent,Cascade"
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bitfld.long 0x04 2. " WDT_CLEAR0 ,Clear watchdog counter when WDT_CTR0=WDT_MATCH0" "Free running counter,Clear on match"
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textline " "
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bitfld.long 0x04 0.--1. " WDT_MODE0 ,Watchdog counter action on match" "NOTHING,INT,RESET,INT_THEN_RESET"
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line.long 0x08 "WDT_CONTROL,Watchdog Counters Control"
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bitfld.long 0x08 19. " WDT_RESET2 ,Resets counter 2 back to 0000_0000" "No reset,Reset"
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eventfld.long 0x08 18. " WDT_INT2 ,WDT interrupt request for counter 2" "No interrupt,Interrupt"
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rbitfld.long 0x08 17. " WDT_ENABLED2 ,Indicates actual state of counter 2" "Disabled,Enabled"
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bitfld.long 0x08 16. " WDT_ENABLE2 ,Enable counter 2" "Disabled,Enabled"
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textline " "
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bitfld.long 0x08 11. " WDT_RESET1 ,Resets counter 1 back to 0000_0000" "No reset,Reset"
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eventfld.long 0x08 10. " WDT_INT1 ,WDT interrupt request for counter 1" "No interrupt,Interrupt"
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rbitfld.long 0x08 9. " WDT_ENABLED1 ,Indicates actual state of counter 1" "Disabled,Enabled"
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bitfld.long 0x08 8. " WDT_ENABLE1 ,Enable counter 1" "Disabled,Enabled"
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textline " "
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bitfld.long 0x08 3. " WDT_RESET0 ,Resets counter 0 back to 0000_0000" "No reset,Reset"
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eventfld.long 0x08 2. " WDT_INT0 ,WDT interrupt request for counter 0" "No interrupt,Interrupt"
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rbitfld.long 0x08 1. " WDT_ENABLED0 ,Indicates actual state of counter 0" "Disabled,Enabled"
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bitfld.long 0x08 0. " WDT_ENABLE0 ,Enable counter 0" "Disabled,Enabled"
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line.long 0x0C "WDT_CLKEN,Watchdog Counters Clock Enable"
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bitfld.long 0x0C 1. " CLK_ILO_EN_FOR_WDT ,Enables the ILO clock for use by the WDT logic" "Disabled,Enabled"
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bitfld.long 0x0C 0. " CLK_WCO_EN_FOR_WDT ,Enable the WCO clock for use by the WDT logic" "Disabled,Enabled"
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if (((per.l(ad:0x40060000))&0x02)==0x02)
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hgroup.long 0xF00++0x03
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hide.long 0x00 "TRIM,WCO Trim Register"
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else
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group.long 0xF00++0x03
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|
line.long 0x00 "TRIM,WCO Trim Register"
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bitfld.long 0x00 4.--5. " LPM_GM ,GM setting for LPM" "0,1,2,3"
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bitfld.long 0x00 0.--2. " XGM ,Amplifier GM setting" "3370 nA,2620 nA,2250 nA,1500 nA,1870 nA,1120 nA,750 nA,0 nA"
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endif
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else
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group.long 0x00++0x03
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line.long 0x00 "CONFIG,WCO Configuration Register"
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bitfld.long 0x00 31. " IP_ENABLE ,Master enable for IP" "Disabled,Enabled"
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endif
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width 0x0B
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tree.end
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textline ""
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