37264 lines
2.6 MiB
37264 lines
2.6 MiB
; --------------------------------------------------------------------------------
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; @Title: OMAP3503, OMAP3515, OMAP3525, OMAP3530 On-Chip Peripherals
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; @Props: Released
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; @Author: ZUB
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; @Changelog: 2008-03-20 ZUB
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; @Manufacturer: TI - Texas Instruments
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; @Doc: spruf98.pdf Rev.2008-03; omap3503.pdf; sprufa0.pdf; sprufa1.pdf
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; sprufa2.pdf; sprufa3.pdf; sprufa4.pdf Rev.2008-02; sprufa5.pdf
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; sprufa6.pdf; sprufa7.pdf; sprufa8.pdf; sprufa9.pdf Rev.2008-02
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; sprufc5.pdf; sprufc6.pdf; sprufc9.pdf Rev.2008-02; sprufd0.pdf
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; sprufd1.pdf; sprufd2.pdf; sprufd4.pdf; sprufd5.pdf
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; sprufd6.pdf Rev.2008-02; spruff1.pdf; spruff2.pdf; spruff4.pdf
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; spruff5.pdf; spruff6.pdf; sprz278.pdf Rev.2008-02
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; @Core: Cortex-A8
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; @Chip: OMAP3503, OMAP3515, OMAP3525, OMAP3530
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peromap35xx.per 17441 2024-02-02 17:32:46Z kwisniewski $
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config 16. 8.
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width 0xB
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base ad:0x00000000
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tree "Core Registers (Cortex-A8)"
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width 0x8
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; --------------------------------------------------------------------------------
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; Identification registers
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; --------------------------------------------------------------------------------
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tree "ID Registers"
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rgroup c15:0x0--0x0
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line.long 0x0 "MIDR,Main ID Register"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
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bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
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textline " "
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hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
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bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x100--0x100
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line.long 0x0 "CTR,Cache Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
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bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
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textline " "
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bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
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rgroup c15:0x200--0x200
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line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register"
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bitfld.long 0x0 29.--31. " FORMAT ,Format" "ARMv6,ARMv6,ARMv6,ARMv6,ARMv7,ARMv6,ARMv6,ARMv6"
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bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rgroup c15:0x300--0x300
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line.long 0x0 "TLBTR,TLB Type Register"
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hexmask.long.byte 0x0 16.--23. 0x1 " ITLBLOCK ,Specifies the number of instruction TLB lockable entries"
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hexmask.long.byte 0x0 8.--15. 0x1 " DTLBLOCK ,Specifies the number of unified or data TLB lockable entries"
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bitfld.long 0x0 0. " S ,Unified or Separate TLBs" "Unified,Separate"
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rgroup c15:0x400--0x400
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line.long 0x0 "MPUTR,MPU type register"
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rgroup c15:0x500--0x500
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line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
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hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitniy Level 2"
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hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitniy Level 1"
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hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitniy Level 0"
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textline " "
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rgroup c15:0x0410++0x00
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line.long 0x00 "MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
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rgroup c15:0x0510++0x00
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line.long 0x00 "MMFR1,Memory Model Feature Register 1"
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bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
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bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
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rgroup c15:0x0610++0x00
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line.long 0x00 "MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
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bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
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rgroup c15:0x0710++0x00
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line.long 0x00 "MMFR3,Memory Model Feature Register 3"
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bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
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rgroup c15:0x0020++0x00
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line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
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bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
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bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
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bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0120++0x00
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line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
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bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0220++0x00
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line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
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bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0320++0x00
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line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
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bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
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rgroup c15:0x0420++0x00
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line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
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bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
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rgroup c15:0x0520++0x00
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line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
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rgroup c15:0x0620++0x00
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line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
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rgroup c15:0x0720++0x00
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line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
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rgroup c15:0x0010++0x00
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line.long 0x00 "PFR0,Processor Feature Register 0"
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bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
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textline " "
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bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
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rgroup c15:0x0110++0x00
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line.long 0x00 "PFR1,Processor Feature Register 1"
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bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
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bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
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bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
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textline " "
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rgroup c15:0x0210++0x00
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line.long 0x00 "DFR0,Debug Feature Register 0"
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bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
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bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
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bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
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textline " "
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bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
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bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
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bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
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rgroup c15:0x0310++0x00
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line.long 0x00 "AFR0,Auxiliary Feature Register 0"
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hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
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tree.end
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width 0x8
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tree "System Control and Configuration"
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group c15:0x1--0x1
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line.long 0x0 "SCTLR,Control Register"
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bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
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bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
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bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
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bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
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bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
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bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
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bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
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textline " "
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group c15:0x101--0x101
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line.long 0x0 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 31. " L2RD ,L2 hardware reset disable" "Enable,Disable"
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bitfld.long 0x00 30. " L1RD ,L1 hardware reset disable" "Enable,Disable"
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textline " "
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bitfld.long 0x00 18. " CPISEL ,CP14/CP15 instruction serialization" "No,Yes"
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bitfld.long 0x00 17. " CPWAI ,CP14/CP15 wait on idle" "No,Yes"
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bitfld.long 0x00 16. " CPFL ,CP14/CP15 pipeline flush" "No,Yes"
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textline " "
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bitfld.long 0x00 15. " FETMCLK ,Force ETM clock" "No,Yes"
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bitfld.long 0x00 14. " FNCLK ,Force NEON clock" "No,Yes"
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bitfld.long 0x00 13. " FMCLK ,Force main clock" "No,Yes"
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textline " "
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bitfld.long 0x00 12. " FNSI ,Force NEON single issue" "No,Yes"
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bitfld.long 0x00 11. " FLSSI ,Force load/store single issue" "No,Yes"
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bitfld.long 0x00 10. " FSI ,Force single issue" "No,Yes"
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textline " "
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bitfld.long 0x00 9. " PLDNOP ,PLD executes as NOP" "Execute,NOP"
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bitfld.long 0x00 8. " WFINOP ,WFI executes as NOP" "Execute,NOP"
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textline " "
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bitfld.long 0x00 7. " DBSM ,Disable branch size mispredicts" "Enable,Disable"
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bitfld.long 0x00 6. " IBE ,Invalidate BTB Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 5. " L1NEON ,NEON Data Caching Within the L1 Data Cache Enable" "Disable,Enable"
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bitfld.long 0x00 4. " ASA ,Speculative Accesses on AXI Enable" "Disable,Enable"
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textline " "
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bitfld.long 0x00 3. " L1PE ,L1 Cache Parity Detection Enable" "Disable,Enable"
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bitfld.long 0x00 1. " L2EN ,L2 Cache Enable" "Disable,Enable"
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bitfld.long 0x00 0. " L1ALIAS ,L1 Data Cache Hardware Alias Checks Enable" "Enable,Disable"
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group c15:0x201--0x201
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line.long 0x0 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
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bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
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textline " "
|
|
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
|
|
textline " "
|
|
group c15:0x11--0x11
|
|
line.long 0x0 "SCR,Secure Configuration Register"
|
|
bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
|
|
bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
|
|
bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
|
|
bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
|
|
group c15:0x111--0x111
|
|
line.long 0x0 "SDER,Secure Debug Enable Register"
|
|
bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
|
|
group c15:0x0211++0x00
|
|
line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 18. " PLE ,PLE Registers Access in Nonsecure World" "Denied,Permitted"
|
|
bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CL ,Lockdown Entries Allocation Within the L2 Cache in Nonsecure World" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CP13 ,Coprocessor 13 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 12. " CP12 ,Coprocessor 12 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CP9 ,Coprocessor 9 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 8. " CP8 ,Coprocessor 8 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CP7 ,Coprocessor 7 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 6. " CP6 ,Coprocessor 6 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CP5 ,Coprocessor 5 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 4. " CP4 ,Coprocessor 4 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CP3 ,Coprocessor 3 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 2. " CP2 ,Coprocessor 2 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CP1 ,Coprocessor 1 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
bitfld.long 0x00 0. " CP0 ,Coprocessor 0 in the Nonsecure World Access Permission" "Denied,Permitted"
|
|
textline " "
|
|
group c15:0x000c++0x00
|
|
line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register"
|
|
hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address"
|
|
group c15:0x10c--0x10c
|
|
line.long 0x0 "MVBAR,Monitor Vector Base Address Register"
|
|
hexmask.long.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address"
|
|
textline " "
|
|
rgroup c15:0x1C--0x1C
|
|
line.long 0x0 "ISR,Interrupt status Register"
|
|
bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending"
|
|
bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending"
|
|
bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending"
|
|
tree.end
|
|
width 0x0d
|
|
tree "Memory Management Unit"
|
|
width 8.
|
|
group c15:0x1--0x1
|
|
line.long 0x0 "SCTLR,Control Register"
|
|
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
|
|
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
|
|
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
|
|
bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
|
|
bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
|
|
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
|
|
textline " "
|
|
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
|
|
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
|
|
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
|
|
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
|
|
textline " "
|
|
group c15:0x0002++0x00
|
|
line.long 0x00 "TTBR0,Translation Table Base Register 0"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
|
|
group c15:0x0102++0x00
|
|
line.long 0x00 "TTBR1,Translation Table Base Register 1"
|
|
hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address"
|
|
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
|
|
textline " "
|
|
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
|
|
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
|
|
group c15:0x0202++0x00
|
|
line.long 0x00 "TTBCR,Translation Table Base Control Register"
|
|
bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable"
|
|
bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable"
|
|
bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000"
|
|
textline " "
|
|
group c15:0x3--0x3
|
|
line.long 0x0 "DACR,Domain Access Control Register"
|
|
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
|
|
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
|
|
textline " "
|
|
group c15:0x0005++0x00
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/decode,Reserved,Imprecise/parity/ECC,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/slave,?..."
|
|
group c15:0x0006++0x00
|
|
line.long 0x00 "DFAR,Data Fault Address Register"
|
|
group c15:0x0105++0x00
|
|
line.long 0x00 "IFSR,Instruction Fault Status Register"
|
|
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
|
|
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/parity,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,?..."
|
|
group c15:0x0206++0x00
|
|
line.long 0x00 "IFAR,Instruction Fault Address Register"
|
|
group c15:0x0015++0x00
|
|
line.long 0x00 "DAFSR,Data Auxiliary Fault Status Register"
|
|
group c15:0x0115++0x00
|
|
line.long 0x00 "IAFSR,Instruction Auxiliary Fault Status Register"
|
|
textline " "
|
|
group c15:0x002A--0x002A
|
|
line.long 0x00 "PMRRR,Primary Memory Region Remap Register"
|
|
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
|
|
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP"
|
|
group c15:0x012A--0x012A
|
|
line.long 0x00 "NMRR,Normal Memory Remap Register"
|
|
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
|
|
textline " "
|
|
group c15:0x000d++0x00
|
|
line.long 0x00 "FCSEPID,FCSE PID Register"
|
|
hexmask.long.byte 0x00 25.--31. 1. " FCSEPID ,Process for Fast Context Switch Identification and Specification"
|
|
group c15:0x10d--0x10d
|
|
line.long 0x0 "CONTEXT,Context ID Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID"
|
|
hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID"
|
|
group c15:0x020d++0x00
|
|
line.long 0x00 "URWTPID,User Read/Write Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " URWTPID ,User Read/Write Thread and Process ID"
|
|
group c15:0x030d++0x00
|
|
line.long 0x00 "UROTPID,User Read-Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " UROTPID ,User Read-Only Thread and Process ID"
|
|
group c15:0x040d++0x00
|
|
line.long 0x00 "POTPID,Privileged Only Thread and Process ID Register"
|
|
hexmask.long 0x00 0.--31. 1. " POTPID ,Privileged Only Thread and Process ID"
|
|
tree.end
|
|
width 0xC
|
|
tree "Cache Control and Configuration"
|
|
rgroup c15:0x1100--0x1100
|
|
line.long 0x0 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CTYPE8 ,Cache type for levels 8" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
|
|
rgroup c15:0x1000--0x1000
|
|
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
|
|
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
|
|
textline " "
|
|
hexmask.long.word 0x00 13.--27. 1. 1. " SETS ,Number of Sets"
|
|
hexmask.long.word 0x00 3.--12. 1. 1. " ASSOC ,Associativity"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words"
|
|
group c15:0x2000--0x2000
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
|
|
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/unified,Instruction"
|
|
tree.end
|
|
width 0x8
|
|
tree "L2 Cache Control and Configuration"
|
|
group c15:0x1009++0x00
|
|
line.long 0x00 "L2CLR,L2 Cache Lockdown Register"
|
|
bitfld.long 0x00 7. " LOCK_way_7 ,Way 7 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LOCK_way_6 ,Way 6 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LOCK_way_5 ,Way 5 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOCK_way_4 ,Way 4 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LOCK_way_3 ,Way 3 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LOCK_way_2 ,Way 2 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LOCK_way_1 ,Way 1 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LOCK_way_0 ,Way 0 of the L2 Cache Lockdown" "Not locked,Locked"
|
|
group c15:0x1209++0x00
|
|
line.long 0x00 "L2CACR,L2 Cache Auxiliary Control Register"
|
|
bitfld.long 0x00 28. " ECCP ,ECC/Parity Selection" "Parity,ECC"
|
|
bitfld.long 0x00 27. " PLDFD ,PLD Forwarding to LS Request Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " PLDD ,PLD Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " WCD ,Write Combining Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " WADD ,External Linefill When Storing an Entire Line With Write Allocate Permission Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 23. " WACD ,Combining of Data in the L2 Write Combining Buffers Disable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAD ,Allocate on Write Miss in L2 Disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 21. " PECCE ,Parity/ECC Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " L2I ,L2 Inner" "Outer,Inner"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " TRAML ,Program Tag RAM Latency" "2 cycles,2 cycles,3 cycles,4 cycles,4 cycles,4 cycles,4 cycles,4 cycles"
|
|
bitfld.long 0x00 0.--3. " DRAML ,Program Data RAM Latency" "3 cycles,3 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,13 cycles,13 cycles,13 cycles"
|
|
textline " "
|
|
rgroup c15:0x000b++0x00
|
|
line.long 0x00 "PLEISR0,PLE Identification and Status Register 0"
|
|
bitfld.long 0x00 1. " CH1P ,Channel 1 Present" "Not present,Present"
|
|
bitfld.long 0x00 0. " CH0P ,Channel 0 Present" "Not present,Present"
|
|
rgroup c15:0x010b++0x00
|
|
line.long 0x00 "PLEISR1,PLE Identification and Status Register 1"
|
|
bitfld.long 0x00 1. " CH1Q ,Channel 1 Queue" "Not queued,Queued"
|
|
bitfld.long 0x00 0. " CH0Q ,Channel 0 Queue" "Not queued,Queued"
|
|
rgroup c15:0x020b++0x00
|
|
line.long 0x00 "PLEISR2,PLE Identification and Status Register 2"
|
|
bitfld.long 0x00 1. " CH1R ,Channel 1 Run" "Not running,Running"
|
|
bitfld.long 0x00 0. " CH0R ,Channel 0 Run" "Not running,Running"
|
|
rgroup c15:0x030b++0x00
|
|
line.long 0x00 "PLEISR3,PLE Identification and Status Register 3"
|
|
bitfld.long 0x00 1. " CH1I ,Channel 1 Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " CH0I ,Channel 0 Interrupt" "No interrupt,Interrupt"
|
|
group c15:0x001b++0x00
|
|
line.long 0x00 "PLEUAR,PLE User Accessibility Register"
|
|
bitfld.long 0x00 1. " U1 ,User Mode Process Access Registers for Channel 1 Permission" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " U0 ,User Mode Process Access Registers for Channel 0 Permission" "Not permitted,Permitted"
|
|
group c15:0x002b++0x00
|
|
line.long 0x00 "PLECNR,PLE Channel Number Register"
|
|
bitfld.long 0x00 0. " CN ,PLE Channel Selection" "Channel 0,Channel 1"
|
|
wgroup c15:0x003b++0x00
|
|
line.long 0x00 "PLEER0,PLE Enable Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " PLEE_STOP ,PLE Enable Stop"
|
|
wgroup c15:0x013b++0x00
|
|
line.long 0x00 "PLEER1,PLE Enable Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " PLEE_START ,PLE Enable Start"
|
|
wgroup c15:0x023b++0x00
|
|
line.long 0x00 "PLEER2,PLE Enable Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " PLEES_CLEAR ,PLE Enable Clear"
|
|
group c15:0x004b++0x00
|
|
line.long 0x00 "PLECR,PLE Control Register"
|
|
bitfld.long 0x00 30. " DT ,Transfer Direction" "Memory->cache,Cache->memory"
|
|
bitfld.long 0x00 29. " IC ,Interrupt on Completion of the PLE Transfer" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 28. " IE ,Interrupt on an Error" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 26. " UM ,Permission Checks Type" "Privileged,User"
|
|
bitfld.long 0x00 0.--2. " Wy ,L2 Cache Way for Filling Data" "Way 0,Way 1,Way 2,Way 3,Way 4,Way 5,Way 6,Way 7"
|
|
textline " "
|
|
group c15:0x005b++0x00
|
|
line.long 0x00 "PLEISAR,PLE Internal Start Address Register"
|
|
hexmask.long 0x00 0.--31. 1. " PLEISA ,PLE Internal Start Address"
|
|
group c15:0x007b++0x00
|
|
line.long 0x00 "PLEIEAR,PLE Internal End Address Register"
|
|
hexmask.long.word 0x00 6.--17. 1. " Lines ,Number of Cache Lines Transferred"
|
|
rgroup c15:0x008b++0x00
|
|
line.long 0x00 "PLECSR,PLE Channel Status Register"
|
|
hexmask.long.byte 0x00 2.--8. 1. " EC ,External Address Error Status"
|
|
bitfld.long 0x00 0.--1. " Status ,PLE Channel Status" "Idle,Queued,Running,Complete/error"
|
|
group c15:0x00fb++0x00
|
|
line.long 0x00 "PLECIDR,PLE Context ID Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,ASID Extension to Form the Process ID and Current Process Identification"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ASID ,ASID of the Current Process and the Current ASID Identification"
|
|
tree.end
|
|
width 12.
|
|
tree "System Performance Monitor"
|
|
group c15:0xC9--0xC9
|
|
line.long 0x0 "PMCR,Performance Monitor Control Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
|
|
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
|
|
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
|
|
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
|
|
group c15:0x1C9--0x1C9
|
|
line.long 0x0 "CNTENS,Count Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x2C9--0x2C9
|
|
line.long 0x0 "CNTENC,Count Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
|
|
group c15:0x3C9--0x3C9
|
|
line.long 0x0 "FLAG,Overflow Flag Status Register"
|
|
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
|
|
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
|
|
group c15:0x4C9--0x4C9
|
|
line.long 0x0 "SWINCR,Software Increment Register"
|
|
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
|
|
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
|
|
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
|
|
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
|
|
group c15:0x5C9--0x5C9
|
|
line.long 0x0 "PMSELR,Performance Counter Selection Register"
|
|
bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,..."
|
|
group c15:0xD9--0xD9
|
|
line.long 0x0 "PMCCNTR,Cycle Count Register"
|
|
group c15:0x01d9++0x00
|
|
line.long 0x00 "PMXEVTYPER,Event Selection Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
|
|
group c15:0x02d9++0x00
|
|
line.long 0x00 "PMCNT,Performance Monitor Count Register"
|
|
group c15:0xE9--0xE9
|
|
line.long 0x0 "PMUSERENR,User Enable Register"
|
|
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
|
|
group c15:0x1E9--0x1E9
|
|
line.long 0x0 "INTENS,Interrupt Enable Set Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
group c15:0x2E9--0x2E9
|
|
line.long 0x0 "INTENC,Interrupt Enable Clear Register"
|
|
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
|
|
tree.end
|
|
width 8.
|
|
tree "Debug Registers"
|
|
width 10.
|
|
rgroup c14:0x000--0x000
|
|
line.long 0x0 "DBGDIDR,Debug ID Register"
|
|
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x0 20.--23. " CONTEXT ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..."
|
|
textline " "
|
|
bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Not implemented,Implemented"
|
|
bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented"
|
|
textline " "
|
|
bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
width 10.
|
|
group c14:0x22--0x22
|
|
line.long 0x0 "DBGDSCR,Debug Status and Control Register"
|
|
bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full"
|
|
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full"
|
|
bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full"
|
|
textline " "
|
|
bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired"
|
|
bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing"
|
|
textline " "
|
|
bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..."
|
|
bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded"
|
|
textline " "
|
|
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
|
|
bitfld.long 0x0 17. " nSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled"
|
|
bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled"
|
|
bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced"
|
|
bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception"
|
|
textline " "
|
|
bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted"
|
|
bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..."
|
|
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
|
|
textline " "
|
|
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
|
|
textline " "
|
|
width 10.
|
|
if (((data.long(c14:0x00))&0x01000)==0x00000)
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
else
|
|
group c14:0x007--0x007
|
|
line.long 0x0 "DBGVCR,Vector Catch Register"
|
|
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
|
|
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
|
|
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
|
|
endif
|
|
width 10.
|
|
hgroup c14:0x020--0x020
|
|
hide.long 0x0 "DBGDTRRX,Debug Receive Register (External View)"
|
|
in
|
|
group c14:0x023--0x023
|
|
line.long 0x0 "DBGDTRTX,Debug Transmit Register (External View)"
|
|
group c14:0x09++0x00
|
|
line.long 0x00 "DBGECR,Event Catch Register"
|
|
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
|
|
group c14:0x0a++0x00
|
|
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
|
|
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal"
|
|
bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal"
|
|
wgroup c14:0x21++0x00
|
|
line.long 0x00 "DBGITR,Instruction Transfer Register"
|
|
wgroup c14:0x24++0x00
|
|
line.long 0x00 "DBGDRCR,Debug Run Control Register"
|
|
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
|
|
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
|
|
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
|
|
wgroup c14:0xc0++0x00
|
|
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
|
|
rgroup c14:0xc1++0x00
|
|
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
|
|
bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required"
|
|
bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented"
|
|
group c14:0xc2++0x00
|
|
line.long 0x00 "DBGOSSRR,Operating System Save and Restore Register"
|
|
hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore"
|
|
group c14:0xc4++0x00
|
|
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
|
|
bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held"
|
|
bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high"
|
|
hgroup c14:0xc5++0x00
|
|
hide.long 0x00 "DBGPRSR,Device Power-Down and Reset Status Register"
|
|
in
|
|
width 11.
|
|
tree "Processor Identifier Registers"
|
|
rgroup c14:0x340--0x340
|
|
line.long 0x00 "CPUID,Main ID Register"
|
|
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
|
|
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture"
|
|
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
|
|
rgroup c14:0x341--0x341
|
|
line.long 0x00 "CACHETYPE,Cache Type Register"
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
|
|
rgroup c14:0x343--0x343
|
|
line.long 0x00 "TLBTYPE,TLB Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
|
|
hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
|
|
textline " "
|
|
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
|
|
rgroup c14:0x348--0x348
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x349--0x349
|
|
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x34a--0x34a
|
|
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
|
|
rgroup c14:0x34b--0x34b
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
|
|
rgroup c14:0x34c--0x34c
|
|
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x34d--0x34d
|
|
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
|
|
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
|
|
rgroup c14:0x34e--0x34e
|
|
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
|
|
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
|
|
rgroup c14:0x34f--0x34f
|
|
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
|
|
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x350--0x350
|
|
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
|
|
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x351--0x351
|
|
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
|
|
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x352--0x352
|
|
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
|
|
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x353--0x353
|
|
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
|
|
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
|
|
rgroup c14:0x354--0x354
|
|
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
|
|
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
|
|
rgroup c14:0x355--0x355
|
|
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
|
|
tree.end
|
|
width 0xC
|
|
tree "Coresight Management Registers"
|
|
width 17.
|
|
group c14:0x03bd++0x00
|
|
line.long 0x00 "DBGITCTRL_IOC,Integration Internal Output Control Register"
|
|
bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1"
|
|
bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " I_nPMUIRQ ,Internal nPMUIRQ" "0,1"
|
|
bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1"
|
|
group c14:0x03be++0x00
|
|
line.long 0x00 "DBGITCTRL_EOC,Integration External Output Control Register"
|
|
bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1"
|
|
bitfld.long 0x00 6. " nDMASIRQ ,External nDMASIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1"
|
|
bitfld.long 0x00 4. " nPMUIRQ ,External nPMUIRQ" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1"
|
|
bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1"
|
|
bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1"
|
|
rgroup c14:0x03bf++0x00
|
|
line.long 0x00 "DBGITCTRL_IS,Integration Input Status Register"
|
|
bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1"
|
|
bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1"
|
|
bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 2. " nFIQ ,nFIQ Input" "0,1"
|
|
bitfld.long 0x00 1. " nIRQ ,nIRQ Input" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1"
|
|
group c14:0x3c0--0x3c0
|
|
line.long 0x0 "DBGITCTRL,Integration Mode Control Register"
|
|
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
|
|
group c14:0x3e8--0x3e8
|
|
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
|
|
group c14:0x3e9--0x3e9
|
|
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
|
|
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
|
|
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
|
|
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
|
|
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
|
|
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
|
|
wgroup c14:0x3ec--0x3ec
|
|
line.long 0x0 "DBGLAR,Lock Access Register"
|
|
rgroup c14:0x3ed--0x3ed
|
|
line.long 0x0 "DBGLSR,Lock Status Register"
|
|
bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit"
|
|
bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented"
|
|
width 17.
|
|
rgroup c14:0x3ee--0x3ee
|
|
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented"
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled"
|
|
width 17.
|
|
hgroup c14:0x3f2--0x3f2
|
|
hide.long 0x0 "DBGDEVID,Device Identifier (RESERVED)"
|
|
rgroup c14:0x3f3--0x3f3
|
|
line.long 0x0 "DBGDEVTYPE,Device Type"
|
|
bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup c14:0x3f8--0x3f8
|
|
line.long 0x00 "DBGPID0,Debug Peripheral ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]"
|
|
rgroup c14:0x3f9--0x3f9
|
|
line.long 0x00 "DBGPID1,Debug Peripheral ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]"
|
|
rgroup c14:0x3fa--0x3fa
|
|
line.long 0x00 "DBGPID2,Debug Peripheral ID 2"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision"
|
|
bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]"
|
|
rgroup c14:0x3fb--0x3fb
|
|
line.long 0x00 "DBGPID3,Debug Peripheral ID 3"
|
|
hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision"
|
|
hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified"
|
|
rgroup c14:0x3f4--0x3f4
|
|
line.long 0x00 "DBGPID4,Debug Peripheral ID 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code"
|
|
rgroup c14:0x3fc--0x3fc
|
|
line.long 0x00 "DBGCID0,Debug Component ID 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0"
|
|
rgroup c14:0x3fd--0x3fd
|
|
line.long 0x00 "DBGCID1,Debug Component ID 1"
|
|
hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class"
|
|
hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1"
|
|
rgroup c14:0x3fe--0x3fe
|
|
line.long 0x00 "DBGCID2,Debug Component ID 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2"
|
|
rgroup c14:0x3ff--0x3ff
|
|
line.long 0x00 "DBGCID3,Debug Component ID 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3"
|
|
tree.end
|
|
tree.end
|
|
width 7.
|
|
tree "Breakpoint Registers"
|
|
group c14:0x40++0x00
|
|
line.long 0x00 "BVR0,Breakpoint Value Register 0"
|
|
group c14:0x50++0x00
|
|
line.long 0x00 "BCR0,Breakpoint Control Register 0"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x41++0x00
|
|
line.long 0x00 "BVR1,Breakpoint Value Register 1"
|
|
group c14:0x51++0x00
|
|
line.long 0x00 "BCR1,Breakpoint Control Register 1"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x42++0x00
|
|
line.long 0x00 "BVR2,Breakpoint Value Register 2"
|
|
group c14:0x52++0x00
|
|
line.long 0x00 "BCR2,Breakpoint Control Register 2"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x43++0x00
|
|
line.long 0x00 "BVR3,Breakpoint Value Register 3"
|
|
group c14:0x53++0x00
|
|
line.long 0x00 "BCR3,Breakpoint Control Register 3"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x44++0x00
|
|
line.long 0x00 "BVR4,Breakpoint Value Register 4"
|
|
group c14:0x54++0x00
|
|
line.long 0x00 "BCR4,Breakpoint Control Register 4"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
group c14:0x45++0x00
|
|
line.long 0x00 "BVR5,Breakpoint Value Register 5"
|
|
group c14:0x55++0x00
|
|
line.long 0x00 "BCR5,Breakpoint Control Register 5"
|
|
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
|
|
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
|
|
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
|
|
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 6.
|
|
tree "Watchpoint Control Registers"
|
|
group c14:0x60++0x00
|
|
line.long 0x00 "WVR0,Watchpoint Value Register 0"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
|
|
group c14:0x70--0x70
|
|
line.long 0x0 "WCR0,Watchpoint Control Register 0"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x61++0x00
|
|
line.long 0x00 "WVR1,Watchpoint Value Register 1"
|
|
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
|
|
group c14:0x71--0x71
|
|
line.long 0x0 "WCR1,Watchpoint Control Register 1"
|
|
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
|
|
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
|
|
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
|
|
textline " "
|
|
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
|
|
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
|
|
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
|
|
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
|
|
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
|
|
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
|
|
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
|
|
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
|
|
textline " "
|
|
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
|
|
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
|
|
group c14:0x006--0x006
|
|
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
|
|
hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
|
|
tree.end
|
|
tree.end
|
|
tree.open "Power Reset and Clock Management"
|
|
tree "Clock Management"
|
|
base ad:0x48004000
|
|
width 22.
|
|
group.long 0x00++0x7 "IVA2"
|
|
line.long 0x00 "CM_FCLKEN_IVA2,IVA2 Domain Functional Clock Activity Control"
|
|
bitfld.long 0x00 0. " EN_IVA2 ,IVA2 functional clock control" "Disabled,Enabled"
|
|
line.long 0x04 "CM_CLKEN_PLL_IVA2,DPLL2 Mode Control"
|
|
bitfld.long 0x04 10. " EN_IVA2_DPLL_LPMODE ,LP mode of the IVA2 DPLL control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " IVA2_DPLL_RAMPTIME ,Frequency ramp time total duration controll" "Disabled,4 us,20 us,40 us"
|
|
textline " "
|
|
hexmask.long 0x04 4.--7. 1. " IVA2_DPLL_FREQSEL ,Range of the DPLL2 internal frequency select"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EN_IVA2_DPLL_DRIFTGUARD ,Automatic recalibration feature of the DPLL2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " EN_IVA2_DPLL ,DPLL2 control" "Reserved,Low power stop,Reserved,Reserved,Reserved,Low power bypass,Reserved,Lock"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x00 "CM_IDLEST_IVA2,IVA2 Standby Status And Access Availability Monitoring"
|
|
bitfld.long 0x00 0. " ST_IVA2 ,IVA2 standby status" "Active,Standby"
|
|
line.long 0x04 "CM_IDLEST_PLL_IVA2,Master Clock Activity Monitoring"
|
|
bitfld.long 0x04 0. " ST_IVA2_CLK ,IVA2_CLK activity" "Bypassed,Locked"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "CM_AUTOIDLE_PLL_IVA2,Automatic Control Over The DPLL2 Activity"
|
|
bitfld.long 0x00 0.--2. " AUTO_IVA2_DPLL ,DPLL2 automatic control" "Disabled,Low power stop,?..."
|
|
group.long 0x40++0xb
|
|
line.long 0x00 "CM_CLKSEL1_PLL_IVA2,Over The DPLL2 Control"
|
|
bitfld.long 0x00 19.--21. " IVA2_CLK_SRC ,IVA2 DPLL bypass source clock" "Reserved,CORE_CLK/1,CORE_CLK/2,Reserved,CORE_CLK/4,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--18. 1. " IVA2_DPLL_MULT ,IVA2 DPLL multiplier factor"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " IVA2_DPLL_DIV ,IVA2 DPLL divider factor"
|
|
line.long 0x04 "CM_CLKSEL2_PLL_IVA2,Over The DPLL2 Control"
|
|
bitfld.long 0x04 0.--4. " IVA2_DPLL_CLKOUT_DIV ,IVA2 DPLL output clock divider factor" "Reserved,Clk/1,Clk/2,Clk/3,Clk/4,Clk/5,Clk/6,Clk/7,Clk/8,Clk/9,Clk/10,Clk/11,Clk/12,Clk/13,Clk/14,Clk/15,Clk/16,?..."
|
|
line.long 0x08 "CM_CLKSTCTRL_IVA2,Domain power state transition enables"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL_IVA2 ,Controls the clock state transition of the IVA2 clock domain" "Disabled,Supervised sleep,Supervised wake-up,Auto"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x00 "CM_CLKSTST_IVA2,Clock Activity In The Domain Status"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_IVA2 ,Clock Activity Status" "Not active,Active"
|
|
rgroup.long 0x800++0x3 "OCP System Registers"
|
|
line.long 0x00 "CM_REVISION,IP revision code for the CM part of the PRCM"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP revision"
|
|
group.long 0x810++0x3
|
|
line.long 0x00 "CM_SYSCONFIG,OCP Interface Parameters Control"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy" "Free-running,Auto gating strategy"
|
|
group.long 0x904++0x3 "MPU"
|
|
line.long 0x00 "CM_CLKEN_PLL_MPU,DPLL1 Modes Control"
|
|
bitfld.long 0x00 10. " EN_MPU_DPLL_LPMODE ,LP mode of the MPU DPLL control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MPU_DPLL_RAMPTIME ,Frequency ramp time total duration controlling" "Disabled,4 us,20 us,40 us"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " MPU_DPLL_FREQSEL ,Select proper range of the DPLL1 internal frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN_MPU_DPLL_DRIFTGUARD ,automatic recalibration feature of the DPLL1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EN_MPU_DPLL ,DPLL1 control" "Reserved,Reserved,Reserved,Reserved,Reserved,Low power bypass,Reserved,Lock"
|
|
rgroup.long 0x920++0x7
|
|
line.long 0x00 "CM_IDLEST_MPU,Modules Access Availability Monitoring"
|
|
bitfld.long 0x00 0. " ST_MPU ,MPU standby status" "Active,Standby"
|
|
line.long 0x04 "CM_IDLEST_PLL_MPU,Master Clock Activity Monitoring"
|
|
bitfld.long 0x04 0. " ST_MPU_CLK ,MPU_CLK activity" "Bypassed,Locked"
|
|
group.long 0x934++0x3
|
|
line.long 0x00 "CM_AUTOIDLE_PLL_MPU,Over The DPLL1 Activity Automatic Control"
|
|
bitfld.long 0x00 0.--2. " AUTO_MPU_DPLL ,DPLL1 automatic control" "Disabled,Auto low power stop,?..."
|
|
group.long 0x940++0xb
|
|
line.long 0x00 "CM_CLKSEL1_PLL_MPU,Over The DPLL1 Control"
|
|
bitfld.long 0x00 19.--21. " MPU_CLK_SRC ,DPLL1 bypass source clock" "Reserved,CORE.CLK/1,CORE.CLK/2,Reserved,CORE.CLK/4,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--18. 1. " MPU_DPLL_MULT ,DPLL1 multiplier factor"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " MPU_DPLL_DIV ,DPLL1 divider factor"
|
|
line.long 0x04 "CM_CLKSEL2_PLL_MPU,Over The DPLL1 Control"
|
|
bitfld.long 0x04 0.--4. " MPU_DPLL_CLKOUT_DIV ,DPLL1 output clock divider factor" "Reserved,Clk/1,Clk/2,Clk/3,Clk/4,Clk/5,Clk/6,Clk/7,Clk/8,Clk/9,Clk/10,Clk/11,Clk/12,Clk/13,Clk/14,Clk/15,Clk/16,?..."
|
|
line.long 0x08 "CM_CLKSTCTRL_MPU,Domain Power State Transition Enable"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL_MPU ,Clock state transition of the MPU clock domain control" "Disabled,Reserved,Supervised wake-up,Auto"
|
|
rgroup.long 0x94C++0x3
|
|
line.long 0x00 "CM_CLKSTST_MPU,Clock Activity In The Domain Status"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_MPU ,Clock activity status" "Not active,Active"
|
|
group.long 0xA00++0x3 "CORE"
|
|
line.long 0x00 "CM_FCLKEN1_CORE,Functional Clock Activity Control"
|
|
bitfld.long 0x00 30. " EN_MMC3 ,MMC3 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EN_MMC2 ,MMC SDIO 2 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EN_MMC1 ,MMC SDIO 1 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EN_MSPRO ,MSPRO functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " EN_HDQ ,HDQ-wire functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EN_MCSPI4 ,McSPI 4 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " EN_MCSPI3 ,McSPI 3 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EN_MCSPI2 ,McSPI 2 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EN_MCSPI1 ,McSPI 1 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EN_I2C3 ,I2C 3 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EN_I2C2 ,I2C 2 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_I2C1 ,I2C 1 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EN_UART2 ,UART 2 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EN_UART1 ,UART 1 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EN_GPT11 ,GPTIMER 11 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EN_GPT10 ,GPTIMER 10 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EN_MCBSP5 ,McBSP 5 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EN_MCBSP1 ,McBSP 1 functional clock control" "Disabled,Enabled"
|
|
group.long 0xA08++0x3
|
|
line.long 0x00 "CM_FCLKEN3_CORE,Controls The Module Functional Clock Activity"
|
|
bitfld.long 0x00 2. " EN_USBTLL ,USB TLL functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EN_TS ,Temperature Sensors functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_CPEFUSE ,CPEFUSE functional clock control" "Disabled,Enabled"
|
|
group.long 0xA10++0xB
|
|
line.long 0x00 "CM_ICLKEN1_CORE,Interface Clock Activity Control"
|
|
bitfld.long 0x00 30. " EN_MMC3 ,MMC SDIO 3 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " EN_ICR ,ICR interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " EN_AES2 ,AES 2 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " EN_SHA12 ,SHA1/MD5 2 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " EN_DES2 ,DES/3DES 2 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EN_MMC2 ,MMC SDIO 2 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EN_MMC1 ,MMC SDIO 1 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " EN_MSPRO ,MSPRO interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " EN_HDQ ,HDQ-wire interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EN_MCSPI4 ,McSPI 4 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " EN_MCSPI3 ,McSPI 3 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EN_MCSPI2 ,McSPI 2 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EN_MCSPI1 ,McSPI 1 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EN_I2C3 ,I2C 3 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EN_I2C2 ,I2C 2 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_I2C1 ,I2C 1 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EN_UART2 ,UART 2 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EN_UART1 ,UART 1 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EN_GPT11 ,GPTIMER 11 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EN_GPT10 ,GPTIMER 10 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EN_MCBSP5 ,McBSP 5 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EN_MCBSP1 ,McBSP 1 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EN_MAILBOXES ,Mailboxes interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EN_OMAPCTRL ,OMAP Control interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EN_HSOTGUSB ,HS OTG USB interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_SDRC ,SDRC interface clock control" "Disabled,Enabled"
|
|
line.long 0x04 "CM_ICLKEN2_CORE,Interface Clock Activity"
|
|
bitfld.long 0x04 4. " EN_PKA ,FPKA1 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " EN_AES1 ,AES 1 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EN_RNG ,RNG1 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " EN_SHA11 ,SHA1/MD5 1 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EN_DES1 ,DES/3DES 1 interface clock control" "Disabled,Enabled"
|
|
line.long 0x08 "CM_ICLKEN3_CORE,Interface Clock Activity"
|
|
bitfld.long 0x08 2. " EN_USBTLL ,USB TLL interface clock control" "Disabled,Enabled"
|
|
rgroup.long 0xA20++0xB
|
|
line.long 0x00 "CM_IDLEST1_CORE,CORE Modules Access Availability Monitoring"
|
|
bitfld.long 0x00 30. " ST_MMC3 ,MMC 3 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 29. " ST_ICR ,ICR idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 28. " ST_AES2 ,AES 2 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " ST_SHA12 ,SHA1/MD5 2 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 26. " ST_DES2 ,DES/3DES 2 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ST_MMC2 ,MMC SDIO 2 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 24. " ST_MMC1 ,MMC SDIO 1 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ST_MSPRO ,MSPRO idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 22. " ST_HDQ ,HDQ-wire idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ST_MCSPI4 ,McSPI 4 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 20. " ST_MCSPI3 ,McSPI 3 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ST_MCSPI2 ,McSPI 2 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 18. " ST_MCSPI1 ,McSPI 1 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ST_I2C3 ,I2C 3 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 16. " ST_I2C2 ,I2C 2 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ST_I2C1 ,I2C 1 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 14. " ST_UART2 ,UART 2 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ST_UART1 ,UART 1 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 12. " ST_GPT11 ,GPTIMER 11 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ST_GPT10 ,GPTIMER 10 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 10. " ST_MCBSP5 ,McBSP 5 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ST_MCBSP1 ,McBSP 1 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ST_MAILBOXES ,Mailboxes idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 6. " ST_OMAPCTRL ,OMAPCTRL idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ST_FSHOSTUSB ,FS HOST USB standby status" "Active,Standby"
|
|
bitfld.long 0x00 4. " ST_HSOTGUSB ,HS OTG USB standby status" "Active,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ST_SDMA ,System DMA standby status" "Active,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ST_SDRC ,SDRC idle status" "Accessed,Not accessed"
|
|
line.long 0x04 "CM_IDLEST2_CORE,CORE Modules Access Availability Monitoring"
|
|
bitfld.long 0x04 4. " ST_PKA ,FPKA1 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x04 3. " ST_AES1 ,AES 1 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ST_RNG ,RNG1 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x04 1. " ST_SHA11 ,SHA1/MD5 1 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ST_DES1 ,DES/3DES 1 idle status" "Accessed,Not accessed"
|
|
line.long 0x08 "CM_IDLEST3_CORE,CORE Modules Access Availability Monitoring"
|
|
bitfld.long 0x08 2. " ST_USBTLL ,USB TLL idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x08 0. " ST_CPEFUSE ,CPEFUSE idle status" "Accessed,Not accessed"
|
|
group.long 0xA30++0xB
|
|
line.long 0x00 "CM_AUTOIDLE1_CORE,Automatic Control Of The CORE Modules Interface Clock Activity"
|
|
bitfld.long 0x00 30. " AUTO_MMC3 ,MMC SDIO 3 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 29. " AUTO_ICR ,ICR auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 28. " AUTO_AES2 ,AES 2 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 27. " AUTO_SHA12 ,SHA1/MD5 2 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 26. " AUTO_DES2 ,DES/3DES 2 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 25. " AUTO_MMC2 ,MMC SDIO 2 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 24. " AUTO_MMC1 ,MMC SDIO 1 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AUTO_MSPRO ,MSPRO auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 22. " AUTO_HDQ ,HDQ-wire auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 21. " AUTO_MCSPI4 ,McSPI 4 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 20. " AUTO_MCSPI3 ,McSPI 3 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 19. " AUTO_MCSPI2 ,McSPI 2 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 18. " AUTO_MCSPI1 ,McSPI 1 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 17. " AUTO_I2C3 ,I2C 3 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 16. " AUTO_I2C2 ,I2C 2 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AUTO_I2C1 ,I2C 1 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 14. " AUTO_UART2 ,UART 2 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_UART1 ,UART 1 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 12. " AUTO_GPT11 ,GPTIMER 11 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AUTO_GPT10 ,GPTIMER 10 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 10. " AUTO_MCBSP5 ,McBSP 5 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AUTO_MCBSP1 ,McBSP 1 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AUTO_MAILBOXES ,Mailboxes auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 6. " AUTO_OMAPCTRL ,OMAP Control auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 4. " AUTO_HSOTGUSB ,HS OTG USB auto clock control" "Unrelated,Related"
|
|
line.long 0x04 "CM_AUTOIDLE2_CORE,Automatic Control Of The CORE Modules Interface Clock Activity"
|
|
bitfld.long 0x04 4. " AUTO_PKA ,FPKA1 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x04 3. " AUTO_AES1 ,AES 1 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x04 2. " AUTO_RNG ,RNG1 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x04 1. " AUTO_SHA11 ,SHA1/MD5 1 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x04 0. " AUTO_DES1 ,DES/3DES 1 auto clock control" "Unrelated,Related"
|
|
line.long 0x08 "CM_AUTOIDLE3_CORE,Automatic Control Of The CORE Modules Interface Clock Activity"
|
|
bitfld.long 0x08 2. " AUTO_USBTLL ,USB TLL auto clock control" "Unrelated,Related"
|
|
group.long 0xA40++0x3
|
|
line.long 0x00 "CM_CLKSEL_CORE,CORE Modules Clock Selection"
|
|
bitfld.long 0x00 8.--11. " CLKSEL_SSI ,Selects SSI functional source clock" "Reserved,COREX2_CLK/1,COREX2_CLK/2,COREX2_CLK/3,COREX2_CLK/4,Reserved,COREX2_CLK/6,Reserved,COREX2_CLK/8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " CLKSEL_GPT11 ,Selects GPTIMER 11 source clock" "CM_32K_CLK,CM_SYS_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKSEL_GPT10 ,Selects GPTIMER 10 source clock" "CM_32K_CLK,CM_SYS_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CLKSEL_L4 ,Selects Peripherals interconnect clock (L4_clk)" "Reserved,L3_ICLK/1,L3_ICLK/2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CLKSEL_L3 ,Selects L3 interconnect clock (L3_clk)" "Reserved,CORE_CLK/1,CORE_CLK/2,?..."
|
|
group.long 0xA48++0x3
|
|
line.long 0x00 "CM_CLKSTCTRL_CORE,Domain Power State Transition Enable"
|
|
bitfld.long 0x00 2.--3. " CLKTRCTRL_L4 ,Clock state transition of the L4 clock domain control" "Disabled,Reserved,Reserved,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL_L3 ,Clock state transition of the L3 clock domain control" "Disabled,Reserved,Reserved,Enabled"
|
|
rgroup.long 0xA4C++0x3
|
|
line.long 0x00 "CM_CLKSTST_CORE,Clock Activity In The Domain Status"
|
|
bitfld.long 0x00 1. " CLKACTIVITY_L4 ,L4 clock activity status" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKACTIVITY_L3 ,L3 clock activity status" "Not active,Active"
|
|
group.long 0xB00++0x3 "SGX"
|
|
line.long 0x00 "CM_FCLKEN_SGX,Controls The Graphics Engine Functional Clock Activity"
|
|
bitfld.long 0x00 1. " EN_SGX ,SGX functional clock enable" "Disabled,Enabled"
|
|
group.long 0xB10++0x3
|
|
line.long 0x00 "CM_ICLKEN_SGX,Controls The Graphics Engine Interface Clock Activity"
|
|
bitfld.long 0x00 0. " EN_SGX ,SGX interface clock control" "Disabled,Enabled"
|
|
rgroup.long 0xB20++0x3
|
|
line.long 0x00 "CM_IDLEST_SGX,SGX Standby Status"
|
|
bitfld.long 0x00 0. " ST_SGX ,SGX standby status" "Active,Standby"
|
|
group.long 0xB40++0xb
|
|
line.long 0x00 "CM_CLKSEL_SGX,SGX Clock Selection"
|
|
bitfld.long 0x00 0.--2. " CLKSEL_SGX ,Selects SGX functional clock" "CORE_CLK/3,CORE_CLK/4,CORE_CLK/6,CM_96M_FCLK,?..."
|
|
line.long 0x04 "CM_SLEEPDEP_SGX,Sleep Transition Dependency Of SGX Domain Enable"
|
|
bitfld.long 0x04 1. " EN_MPU ,Sleep dependency with MPU domain" "Disabled,Enabled"
|
|
line.long 0x08 "CM_CLKSTCTRL_SGX,Domain Power State Transition Enable"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL_SGX ,clock state transition of the SGX clock domain control" "Disabled,Supervised sleep,Supervised wake-up,Auto"
|
|
rgroup.long 0xB4C++0x3
|
|
line.long 0x00 "CM_CLKSTST_SGX,Clock Activity In The Domain Status"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_SGX ,Clock activity status" "Not active,Active"
|
|
group.long 0xC00++0x3 "WKUP"
|
|
line.long 0x00 "CM_FCLKEN_WKUP,Controls The Modules Functional Clock Activity"
|
|
bitfld.long 0x00 9. " EN_USIMOCP ,USIMOCP functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EN_SR2 ,Smart Refex 2 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EN_SR1 ,Smart Refex 1 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EN_WDT2 ,WDTIMER 2 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EN_GPIO1 ,GPIO 1 clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_GPT1 ,GPTIMER 1 clock control" "Disabled,Enabled"
|
|
group.long 0xC10++0x3
|
|
line.long 0x00 "CM_ICLKEN_WKUP,Controls The Modules Interface Clock Activity"
|
|
bitfld.long 0x00 9. " EN_USIMOCP ,USIMOCP interface clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EN_WDT2 ,WDTIMER 2 interface clock" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EN_WDT1 ,WDTIMER 1 (Secure) interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN_GPIO1 ,GPIO 1 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EN_32KSYNC ,32 kHz Sync Timer interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_GPT12 ,GPTIMER 12 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN_GPT1 ,GPTIMER 1 interface clock control" "Disabled,Enabled"
|
|
rgroup.long 0xC20++0x3
|
|
line.long 0x00 "CM_IDLEST_WKUP,WAKEUP Domain Modules Access Monitoring"
|
|
bitfld.long 0x00 9. " ST_USIMOCP ,USIMOCP idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ST_SR2 ,Smart Reflex 2 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 6. " ST_SR1 ,Smart Reflex 1 idle status" "Accessed,Not accessed"
|
|
textline " "
|
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bitfld.long 0x00 5. " ST_WDT2 ,WDT 2 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 4. " ST_WDT1 ,WDTIMER 1 (Secure) idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ST_GPIO1 ,GPIO 1 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 2. " ST_32KSYNC ,32 kHz Sync Timer idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ST_GPT12 ,GPTIMER 12 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 0. " ST_GPT1 ,GPTIMER 1 idle status" "Accessed,Not accessed"
|
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group.long 0xC30++0x3
|
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line.long 0x00 "CM_AUTOIDLE_WKUP,Automatic Control Of The WAKEUP Modules Interface Clock Activity"
|
|
bitfld.long 0x00 9. " AUTO_USIMOCP ,USIMOCP interface clock autoidle control" "Unrelated,Related"
|
|
textline " "
|
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bitfld.long 0x00 5. " AUTO_WDT2 ,WDTIMER 2 autoidle control" "Unrelated,Related"
|
|
bitfld.long 0x00 4. " AUTO_WDT1 ,WDTIMER 1 (Secure) auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AUTO_GPIO1 ,GPIO 1 autoidle control" "Unrelated,Related"
|
|
bitfld.long 0x00 2. " AUTO_32KSYNC ,32 kHz Sync Timer autoidle control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AUTO_GPT12 ,GPTIMER 12 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 0. " AUTO_GPT1 ,GPTIMER 1 autoidle control" "Unrelated,Related"
|
|
group.long 0xC40++0x3
|
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line.long 0x00 "CM_CLKSEL_WKUP,WAKEUP Domain Modules Source Clock Selection"
|
|
bitfld.long 0x00 3.--6. " CLKSEL_USIMOCP ,Selects the USIMOCP module functional clock" "Reserved,System clk/1,System clk/2,96 MHz clk/2,96 MHz clk/4,96 MHz clk/8,96 MHz clk/10,120 MHz clk/4,120 MHz clk/8,120 MHz clk/16,120 MHz clk/20,?..."
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textline " "
|
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bitfld.long 0x00 1.--2. " CLKSEL_RM ,Selects the Reset Manager clock" "Reserved,L4_ICLK/1,L4_ICLK/2,?..."
|
|
bitfld.long 0x00 0. " CLKSEL_GPT1 ,Selects GPTIMER 1 source clock" "32K_FCLK,SYS_CLK"
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group.long 0xD00++0x7 "Clock Control Registers"
|
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line.long 0x00 "CM_CLKEN_PLL,DLL3 And DPLL4 Modes Control"
|
|
bitfld.long 0x00 31. " PWRDN_EMU_PERIPH ,DPLL4_M6X2_CLK HSDIVIDER path power-down control" "Power-up,Power-down"
|
|
textline " "
|
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bitfld.long 0x00 30. " PWRDN_CAM ,DPLL4_M5X2_CLK HSDIVIDER path power-down control" "Power-up,Power-down"
|
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textline " "
|
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bitfld.long 0x00 29. " PWRDN_DSS1 ,DPLL4_M4X2_CLK HSDIVIDER path power-down control" "Power-up,Power-down"
|
|
textline " "
|
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bitfld.long 0x00 28. " PWRDN_TV ,DPLL4_M3X2_CLK HSDIVIDER path power-down control" "Power-up,Power-down"
|
|
textline " "
|
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bitfld.long 0x00 27. " PWRDN_96M ,DPLL4_M2X2_CLK path" "Power-up,Power-down"
|
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textline " "
|
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bitfld.long 0x00 26. " EN_PERIPH_DPLL_LPMODE ,LP mode of the DPLL4 enable" "Disabled,Enabled"
|
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textline " "
|
|
bitfld.long 0x00 24.--25. " PERIPH_DPLL_RAMPTIME ,frequency ramp time total duration control" "Disabled,4 us,20 us,40 us"
|
|
textline " "
|
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bitfld.long 0x00 20.--23. " PERIPH_DPLL_FREQSEL ,Select proper range of the DPLL4 internal frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
|
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bitfld.long 0x00 19. " EN_PERIPH_DPLL_DRIFTGUARD ,automatic recalibration feature of the DPLL4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " EN_PERIPH_DPLL ,DPLL4 control" "Reserved,Low power stop,Reserved,Reserved,Reserved,Reserved,Reserved,Lock"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PWRDN_EMU_CORE ,DPLL3_M3X2 HSDIVIDER path power-down control" "Power-up,Power-down"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EN_CORE_DPLL_LPMODE ,LP mode of the DPLL3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CORE_DPLL_RAMPTIME ,Frequency ramp time total duration" "Disabled,4 us,20 us,40 us"
|
|
textline " "
|
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bitfld.long 0x00 4.--7. " CORE_DPLL_FREQSEL ,Select range of the DPLL3 internal frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN_CORE_DPLL_DRIFTGUARD ,Automatic recalibration feature of the DPLL3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " EN_CORE_DPLL ,DPLL3 control" "Reserved,Reserved,Reserved,Reserved,Reserved,Low power bypass,Fast relock bypass,Lock"
|
|
line.long 0x04 "CM_CLKEN2_PLL,DPLL5 Modes Control"
|
|
bitfld.long 0x04 10. " EN_PERIPH2_DPLL_LPMODE ,LP mode of the DPLL5 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " PERIPH2_DPLL_RAMPTIME ,Frequency ramp time total duration control" "Disabled,4us,20us,40us"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " PERIPH2_DPLL_FREQSEL ,Proper range of the second PERIPHERAL DPLL internal frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 3. " EN_PERIPH2_DPLL_DRIFTGUARD ,Automatic recalibration feature of the DPLL5 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " EN_PERIPH2_DPLL ,DPLL5 control" "Reserved,Low power stop mode,Reserved,Reserved,Reserved,Reserved,Reserved,Lock mode enable"
|
|
rgroup.long 0xD20++0x7
|
|
line.long 0x00 "CM_IDLEST_CKGEN,Master Clock Activity Monitor"
|
|
bitfld.long 0x00 13. " ST_EMU_PERIPH_CLK ,Emulation clock activity at the output stage of the DPLL4" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ST_CAM_CLK ,CAMERA functional clock activity at the output stage of the DPLL4" "Not active,Active"
|
|
textline " "
|
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bitfld.long 0x00 11. " ST_DSS1_CLK ,DSS functional clock 1 activity at the output stage of the DPLL4" "Not active,Active"
|
|
textline " "
|
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bitfld.long 0x00 10. " ST_TV_CLK ,TV clock activity at the output stage of the DPLL4" "Not active,Active"
|
|
textline " "
|
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bitfld.long 0x00 9. " ST_FUNC96M_CLK ,96 MHz clock activity at the output stage of the DPLL4" "Not active,Active"
|
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textline " "
|
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bitfld.long 0x00 8. " ST_EMU_CORE_CLK ,Emulation clock activity at the output stage of the DPLL3" "Not active,Active"
|
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textline " "
|
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bitfld.long 0x00 5. " ST_54M_CLK ,Functional clock 54 MHz activity" "Not active,Active"
|
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textline " "
|
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bitfld.long 0x00 4. " ST_12M_CLK ,Functional clock 12 MHz activity" "Not active,Active"
|
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textline " "
|
|
bitfld.long 0x00 3. " ST_48M_CLK ,Functional clock 48 MHz activity" "Not active,Active"
|
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textline " "
|
|
bitfld.long 0x00 2. " ST_96M_CLK ,Functional clock 96 MHz activity" "Not active,Active"
|
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textline " "
|
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bitfld.long 0x00 1. " ST_PERIPH_CLK ,Peripheral_clk activity" "Bypassed,Locked"
|
|
textline " "
|
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bitfld.long 0x00 0. " ST_CORE_CLK ,Core_clk activity" "Bypassed,Locked"
|
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line.long 0x04 "CM_IDLEST2_CKGEN,Master Clock Activity Monitor"
|
|
bitfld.long 0x04 3. " ST_FUNC120M_CLK ,120 MHz clock activity at the output stage of the DPLL5" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ST_USIM_CLK ,USIM functional clock activity" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ST_120M_CLK ,Functional clock 120 MHz activity" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ST_PERIPH2_CLK ,DPLL5 clock activity" "Bypassed,Locked"
|
|
group.long 0xD30++0x7
|
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line.long 0x00 "CM_AUTOIDLE_PLL,Automatic Control Over The DPLL3 And DPLL4 Activity"
|
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bitfld.long 0x00 3.--5. " AUTO_PERIPH_DPLL ,DPLL4 automatic control" "Disabled,Low power stop,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_CORE_DPLL ,DPLL3 automatic control" "Disabled,Low power stop"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AUTO_CORE_DPLL[2] ,Idle bypass low power mode" "Disabled,Enabled"
|
|
line.long 0x04 "CM_AUTOIDLE2_PLL,Automatic Control Over The DPLL5 Activity"
|
|
bitfld.long 0x04 0.--2. " AUTO_PERIPH2_DPLL ,DPLL5 automatic control" "Disabled,Low power stop,?..."
|
|
group.long 0xD40++0x13
|
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line.long 0x00 "CM_CLKSEL1_PLL,Master Clock Frequencies Selection"
|
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bitfld.long 0x00 27.--31. " CORE_DPLL_CLKOUT_DIV ,DPLL3 output clock divider factor" "Reserved,clk/1,clk/2,clk/3,clk/4,clk/5,clk/6,clk/7,clk/8,clk/9,clk/10,clk/11,clk/12,clk/13,clk/14,clk/15,clk/16,clk/17,clk/18,clk/19,clk/20,clk/21,clk/22,clk/23,clk/24,clk/25,clk/26,clk/27,clk/28,clk/29,clk/30,clk/31"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--26. 1. " CORE_DPLL_MULT ,DPLL3 multiplier factor"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--14. 1. " CORE_DPLL_DIV ,DPLL3 divider factor"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SOURCE_96M ,Selection of 96M_FCLK source" "CM_96M_FCLK,CM_SYS_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SOURCE_54M ,Selection of 54MHz functional clock source" "DPLL4_M3X2_CLK,Sys_altclk"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SOURCE_48M ,Selection of 12M_FCLK and 48M_FCLK source" "CM_96M_FCLK,Sys_altclk"
|
|
line.long 0x04 "CM_CLKSEL2_PLL,This Register Controls The Selection Of The Master Clock Frequencies"
|
|
hexmask.long.word 0x04 8.--18. 1. " PERIPH_DPLL_MULT ,DPLL4 multiplier factor"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--6. 1. " PERIPH_DPLL_DIV ,DPLL4 divider factor"
|
|
line.long 0x08 "CM_CLKSEL3_PLL,Master Clock Frequencies Selection"
|
|
bitfld.long 0x08 0.--4. " DIV_96M ,96 MHz clock divider factor" "Reserved,DPLL4 clk/1,DPLL4 clk/2,DPLL4 clk/3,DPLL4 clk/4,DPLL4 clk/5,DPLL4 clk/6,DPLL4 clk/7,DPLL4 clk/8,DPLL4 clk/9,DPLL4 clk/10,DPLL4 clk/11,DPLL4 clk/12,DPLL4 clk/13,DPLL4 clk/14,DPLL4 clk/15,DPLL4 clk/16,?..."
|
|
line.long 0x0C "CM_CLKSEL4_PLL,Master Clock Frequencies Selection"
|
|
hexmask.long.word 0x0C 8.--18. 1. " PERIPH2_DPLL_MULT ,DPLL5 multiplier factor (0 to 2047)"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--6. 1. " PERIPH2_DPLL_DIV ,DPLL5 divider factor (0 to 127)"
|
|
line.long 0x10 "CM_CLKSEL5_PLL,Master Clock Frequencies Control Register"
|
|
bitfld.long 0x10 0.--4. " DIV_120M ,120 MHz clock divider factor M2" "Reserved,DPLL5 clk/1,DPLL5 clk/2,DPLL5 clk/3,DPLL5 clk/4,DPLL5 clk/5,DPLL5 clk/6,DPLL5 clk/7,DPLL5 clk/8,DPLL5 clk/9,DPLL5 clk/10,DPLL5 clk/11,DPLL5 clk/12,DPLL5 clk/13,DPLL5 clk/14,DPLL5 clk/15,DPLL5 clk/16,?..."
|
|
group.long 0xD70++0x3
|
|
line.long 0x00 "CM_CLKOUT_CTRL,SYS_CLKOUT2 Output Clock Control"
|
|
bitfld.long 0x00 7. " CLKOUT2_EN ,External output clock activity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CLKOUT2_DIV ,External output clock division control" "sys_clkout2/1,sys_clkout2/2,sys_clkout2/4,sys_clkout2/8,sys_clkout2/16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CLKOUT2SOURCE ,External output clock source" "DPLL3 output,System clock,96 MHz clock,54 MHz clock"
|
|
group.long 0xE00++0x3 "DSS"
|
|
line.long 0x00 "CM_FCLKEN_DSS,Controls The Modules Functional Clock Activity"
|
|
bitfld.long 0x00 2. " EN_TV ,TV OUT functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EN_DSS2 ,Display Sub-System functional clock 2 control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_DSS1 ,Display Sub-System functional clock 1 control" "Disabled,Enabled"
|
|
group.long 0xE10++0x3
|
|
line.long 0x00 "CM_ICLKEN_DSS,Modules Interface Clock Activity"
|
|
bitfld.long 0x00 0. " EN_DSS ,Display sub-system interface clock control" "Disabled,Enabled"
|
|
rgroup.long 0xE20++0x3
|
|
line.long 0x00 "CM_IDLEST_DSS,Modules Access Availability Monitoring"
|
|
bitfld.long 0x00 1. " ST_DSS_IDLE ,Display Sub-System idle status" "Active,Idle"
|
|
bitfld.long 0x00 0. " ST_DSS_STDBY ,Display Sub-System standby status" "Active,Standby"
|
|
group.long 0xE30++0x3
|
|
line.long 0x00 "CM_AUTOIDLE_DSS,Automatic Control Of The Modules Interface Clock Activity"
|
|
bitfld.long 0x00 0. " AUTO_DSS ,Display Sub-System auto clock control" "Unrelated,Related"
|
|
group.long 0xE40++0xb
|
|
line.long 0x00 "CM_CLKSEL_DSS,Modules Clock Selection"
|
|
bitfld.long 0x00 8.--12. " CLKSEL_TV ,TV functional clock divider factor" "Reserved,DPLL4 clk/1,DPLL4 clk/2,DPLL4 clk/3,DPLL4 clk/4,DPLL4 clk/5,DPLL4 clk/6,DPLL4 clk/7,DPLL4 clk/8,DPLL4 clk/9,DPLL4 clk/10,DPLL4 clk/11,DPLL4 clk/12,DPLL4 clk/13,DPLL4 clk/14,DPLL4 clk/15,DPLL4 clk/16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CLKSEL_DSS1 ,Display sub-system functional clock 1 divider factor" "Reserved,DPLL4 clk/1,DPLL4 clk/2,DPLL4 clk/3,DPLL4 clk/4,DPLL4 clk/5,DPLL4 clk/6,DPLL4 clk/7,DPLL4 clk/8,DPLL4 clk/9,DPLL4 clk/10,DPLL4 clk/11,DPLL4 clk/12,DPLL4 clk/13,DPLL4 clk/14,DPLL4 clk/15,DPLL4 clk/16,?..."
|
|
line.long 0x04 "CM_SLEEPDEP_DSS,Sleep Transition Dependency Of DSS Domain Enable"
|
|
bitfld.long 0x04 2. " EN_IVA2 ,IVA2 domain dependency" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " EN_MPU ,MPU domain dependency" "Disabled,Enabled"
|
|
line.long 0x08 "CM_CLKSTCTRL_DSS,Domain Power State Transition Enable"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL_DSS ,Clock state transition of the DSS clock domain" "Disabled,Supervised sleep,Supervised wake-up,Auto"
|
|
rgroup.long 0xE4C++0x3
|
|
line.long 0x00 "CM_CLKSTST_DSS,Status On The Clock Activity In The Domain"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_DSS ,Clock activity status" "Not active,Active"
|
|
group.long 0xF00++0x3 "CAM"
|
|
line.long 0x00 "CM_FCLKEN_CAM,Modules Functional Clock Activity"
|
|
bitfld.long 0x00 1. " EN_CSI2 ,CSI2 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN_CAM ,Camera functional clock control" "Disabled,Enabled"
|
|
group.long 0xF10++0x3
|
|
line.long 0x00 "CM_ICLKEN_CAM,Modules Interface Clock Activity"
|
|
bitfld.long 0x00 0. " EN_CAM ,Camera interface clock control" "Disabled,Enabled"
|
|
rgroup.long 0xF20++0x3
|
|
line.long 0x00 "CM_IDLEST_CAM,Modules Access Availability Monitoring"
|
|
bitfld.long 0x00 0. " ST_CAM ,Camera standby status" "Active,Standby"
|
|
group.long 0xF30++0x3
|
|
line.long 0x00 "CM_AUTOIDLE_CAM,Automatic Control Of The Modules Interface Clock Activity"
|
|
bitfld.long 0x00 0. " AUTO_CAM ,Camera auto clock control" "Unrelated,Related"
|
|
group.long 0xF40++0xb
|
|
line.long 0x00 "CM_CLKSEL_CAM,CAM Modules Clock Selection"
|
|
bitfld.long 0x00 0.--4. " CLKSEL_CAM ,Camera functional clock 1 divider factor" "Reserved,DPLL4 clk/1,DPLL4 clk/2,DPLL4 clk/3,DPLL4 clk/4,DPLL4 clk/5,DPLL4 clk/6,DPLL4 clk/7,DPLL4 clk/8,DPLL4 clk/9,DPLL4 clk/10,DPLL4 clk/11,DPLL4 clk/12,DPLL4 clk/13,DPLL4 clk/14,DPLL4 clk/15,DPLL4 clk/16,?..."
|
|
line.long 0x04 "CM_SLEEPDEP_CAM,Sleep Transition Dependency Of CAMERA Domain Enable"
|
|
bitfld.long 0x04 1. " EN_MPU ,MPU domain dependency" "Disabled,Enabled"
|
|
line.long 0x08 "CM_CLKSTCTRL_CAM,SW And HW Supervised Transition Enable"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL_CAM ,Clock state transition of the CAMERA clock domain" "Disabled,Supervised sleep,Supervised wake-up,Auto"
|
|
rgroup.long 0xF4C++0x3
|
|
line.long 0x00 "CM_CLKSTST_CAM,Status On The Clock Activity In The Domain"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_CAM ,Clock activity status" "Not active,Active"
|
|
group.long 0x1000++0x3 "PER"
|
|
line.long 0x00 "CM_FCLKEN_PER,Modules Functional Clock Activity"
|
|
bitfld.long 0x00 17. " EN_GPIO6 ,GPIO 6 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EN_GPIO5 ,GPIO 5 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_GPIO4 ,GPIO 4 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EN_GPIO3 ,GPIO 3 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EN_GPIO2 ,GPIO 2 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EN_WDT3 ,WDTIMER 3 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EN_UART3 ,UART3 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EN_GPT9 ,GPTIMER 9 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EN_GPT8 ,GPTIMER 8 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EN_GPT7 ,GPTIMER 7 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EN_GPT6 ,GPTIMER 6 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EN_GPT5 ,GPTIMER 5 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EN_GPT4 ,GPTIMER 4 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EN_GPT3 ,GPTIMER 3 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN_GPT2 ,GPTIMER 2 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EN_MCBSP4 ,McBSP 4 functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_MCBSP3 ,McBSP 3 functional clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN_MCBSP2 ,McBSP 2 functional clock control" "Disabled,Enabled"
|
|
group.long 0x1010++0x3
|
|
line.long 0x00 "CM_ICLKEN_PER,Modules Interface Clock Activity"
|
|
bitfld.long 0x00 17. " EN_GPIO6 ,GPIO 6 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EN_GPIO5 ,GPIO 5 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_GPIO4 ,GPIO 4 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EN_GPIO3 ,GPIO 3 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EN_GPIO2 ,GPIO 2 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EN_WDT3 ,WDTIMER 3 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EN_UART3 ,UART3 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EN_GPT9 ,GPTIMER 9 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EN_GPT8 ,GPTIMER 8 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " EN_GPT7 ,GPTIMER 7 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " EN_GPT6 ,GPTIMER 6 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " EN_GPT5 ,GPTIMER 5 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EN_GPT4 ,GPTIMER 4 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " EN_GPT3 ,GPTIMER 3 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EN_GPT2 ,GPTIMER 2 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EN_MCBSP4 ,McBSP 4 interface clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_MCBSP3 ,McBSP 3 interface clock control" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN_MCBSP2 ,McBSP 2 interface clock control" "Disabled,Enabled"
|
|
rgroup.long 0x1020++0x3
|
|
line.long 0x00 "CM_IDLEST_PER,Modules Access Availability Monitoring"
|
|
bitfld.long 0x00 17. " ST_GPIO6 ,GPIO 6 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 16. " ST_GPIO5 ,GPIO 5 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ST_GPIO4 ,GPIO 4 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 14. " ST_GPIO3 ,GPIO 3 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ST_GPIO2 ,GPIO 2 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 12. " ST_WDT3 ,WDTIMER 3 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ST_UART3 ,UART3 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 10. " ST_GPT9 ,GPTIMER 9 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ST_GPT8 ,GPTIMER 8 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 8. " ST_GPT7 ,GPTIMER 7 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ST_GPT6 ,GPTIMER 6 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 6. " ST_GPT5 ,GPTIMER 5 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ST_GPT4 ,GPTIMER 4 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 4. " ST_GPT3 ,GPTIMER 3 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ST_GPT2 ,GPTIMER 2 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 2. " ST_MCBSP4 ,McBSP 4 idle status" "Accessed,Not accessed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ST_MCBSP3 ,McBSP 3 idle status" "Accessed,Not accessed"
|
|
bitfld.long 0x00 0. " ST_MCBSP2 ,McBSP 2 idle status" "Accessed,Not accessed"
|
|
group.long 0x1030++0x3
|
|
line.long 0x00 "CM_AUTOIDLE_PER,Automatic Control Of The Modules Interface Clock Activity"
|
|
bitfld.long 0x00 17. " AUTO_GPIO6 ,GPIO 6 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 16. " AUTO_GPIO5 ,GPIO 5 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AUTO_GPIO4 ,GPIO 4 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 14. " AUTO_GPIO3 ,GPIO 3 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 13. " AUTO_GPIO2 ,GPIO 2 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 12. " AUTO_WDT3 ,WDTIMER 3 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 11. " AUTO_UART3 ,UART3 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 10. " AUTO_GPT9 ,GPTIMER 9 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AUTO_GPT8 ,GPTIMER 8 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 8. " AUTO_GPT7 ,GPTIMER 7 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AUTO_GPT6 ,GPTIMER 6 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 6. " AUTO_GPT5 ,GPTIMER 5 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AUTO_GPT4 ,GPTIMER 4 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 4. " AUTO_GPT3 ,GPTIMER 3 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AUTO_GPT2 ,GPTIMER 2 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 2. " AUTO_MCBSP4 ,McBSP 4 auto clock control" "Unrelated,Related"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AUTO_MCBSP3 ,McBSP 3 auto clock control" "Unrelated,Related"
|
|
bitfld.long 0x00 0. " AUTO_MCBSP2 ,McBSP 2 auto clock control" "Unrelated,Related"
|
|
group.long 0x1040++0xb
|
|
line.long 0x00 "CM_CLKSEL_PER,PER Modules Clock Selection"
|
|
bitfld.long 0x00 7. " CLKSEL_GPT9 ,Selects GPTIMER 9 source clock" "Func_32k_clk,Sys_clk"
|
|
bitfld.long 0x00 6. " CLKSEL_GPT8 ,Selects GPTIMER 8 source clock" "Func_32k_clk,Sys_clk"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLKSEL_GPT7 ,Selects GPTIMER 7 source clock" "Func_32k_clk,Sys_clk"
|
|
bitfld.long 0x00 4. " CLKSEL_GPT6 ,Selects GPTIMER 6 source clock" "Func_32k_clk,Sys_clk"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLKSEL_GPT5 ,Selects GPTIMER 5 source clock" "Func_32k_clk,Sys_clk"
|
|
bitfld.long 0x00 2. " CLKSEL_GPT4 ,Selects GPTIMER 4 source clock" "Func_32k_clk,Sys_clk"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CLKSEL_GPT3 ,Selects GPTIMER 3 source clock" "Func_32k_clk,Sys_clk"
|
|
bitfld.long 0x00 0. " CLKSEL_GPT2 ,Selects GPTIMER 2 source clock" "Func_32k_clk,Sys_clk"
|
|
line.long 0x04 "CM_SLEEPDEP_PER,Sleep Transition Dependency Of PERIPHERAL Domain Enable"
|
|
bitfld.long 0x04 2. " EN_IVA2 ,IVA2 domain dependency" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " EN_MPU ,MPU domain dependency" "Disabled,Enabled"
|
|
line.long 0x08 "CM_CLKSTCTRL_PER,HW Supervised Transition Enable"
|
|
bitfld.long 0x08 0.--1. " CLKTRCTRL_PER ,Clock state transition of the PERIPHERAL clock domain" "Disabled,Supervised sleep,Supervised wake-up,Auto"
|
|
rgroup.long 0x104C++0x3
|
|
line.long 0x00 "CM_CLKSTST_PER,Status On The Clock Activity In The Domain"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_PER ,Clock activity status" "Not active,Active"
|
|
group.long 0x1140++0x3 "EMU"
|
|
line.long 0x00 "CM_CLKSEL1_EMU,Modules Clock Selection"
|
|
bitfld.long 0x00 24.--28. " DIV_DPLL4 ,DPLL4_M6X2 clock divider factor" "Reserved,DPLL4 clk/1,DPLL4 clk/2,DPLL4 clk/3,DPLL4 clk/4,DPLL4 clk/5,DPLL4 clk/6,DPLL4 clk/7,DPLL4 clk/8,DPLL4 clk/9,DPLL4 clk/10,DPLL4 clk/11,DPLL4 clk/12,DPLL4 clk/13,DPLL4 clk/14,DPLL4 clk/15,DPLL4 clk/16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " DIV_DPLL3 ,DPLL3_M3X2 clock divider factor" "Reserved,DPLL4 clk/1,DPLL4 clk/2,DPLL4 clk/3,DPLL4 clk/4,DPLL4 clk/5,DPLL4 clk/6,DPLL4 clk/7,DPLL4 clk/8,DPLL4 clk/9,DPLL4 clk/10,DPLL4 clk/11,DPLL4 clk/12,DPLL4 clk/13,DPLL4 clk/14,DPLL4 clk/15,DPLL4 clk/16,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11.--13. " CLKSEL_TRACECLK ,Selects the TRACE clock" "Reserved,SCLK/1,SCLK/2,Reserved,SCLK/4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " CLKSEL_PCLK ,Selects the PCLK clock" "Reserved,Reserved,SCLK/2,SCLK/3,SCLK/4,Reserved,SCLK/6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CLKSEL_PCLKX2 ,Selects the PCLKx2 clock" "Reserved,SCLK/1,SCLK/2,SCLK/3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CLKSEL_ATCLK ,Selects the ATCLK clock" "Reserved,SCLK/1,SCLK/2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TRACE_MUX_CTRL ,Source clock selection" "sys.clk,EMU_CORE_ALWON,EMU_PER_ALWON,EMU_MPU_ALWON"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MUX_CTRL ,Source clock selection (ATCLK; PCLK and PCLKx2)" "sys.clk,EMU_CORE_ALWON,EMU_PER_ALWON,EMU_MPU_ALWON"
|
|
group.long 0x1148++0x3
|
|
line.long 0x00 "CM_CLKSTCTRL_EMU,SW and HW Supervised Transition Enable"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL_EMU ,clock state transition of the EMULATION clock domain" "Reserved,Supervised sleep,Supervised wake-up,Auto"
|
|
rgroup.long 0x114C++0x3
|
|
line.long 0x00 "CM_CLKSTST_EMU,Status on The Clock Activity In The Domain"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_EMU ,Clock activity status" "Not active,Active"
|
|
group.long 0x1150++0x7
|
|
line.long 0x00 "CM_CLKSEL2_EMU,Override Controls Over The DPLL3"
|
|
bitfld.long 0x00 19. " OVERRIDE_ENABLE ,Emulation override control enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--18. 1. " CORE_DPLL_EMU_MULT ,DPLL3 override multiplier factor"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " CORE_DPLL_EMU_DIV ,DPLL3 override divider factor"
|
|
line.long 0x04 "CM_CLKSEL3_EMU,Override Controls Over The DPLL4"
|
|
bitfld.long 0x04 19. " OVERRIDE_ENABLE ,Emulation override control enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 8.--18. 1. " PERIPH_DPLL_EMU_MULT ,DPLL3 override multiplier factor"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--6. 1. " PERIPH_DPLL_EMU_DIV ,DPLL3 override divider factor"
|
|
group.long 0x129C++0x3 "Global"
|
|
line.long 0x00 "CM_POLCTRL,Polarity Of Device Outputs Control Signals"
|
|
bitfld.long 0x00 0. " CLKOUT2_POL ,External output clock 2 polarity" "sys_clkout2 low,sys_clkout2 high"
|
|
rgroup.long 0x1320++0x3 "NEON"
|
|
line.long 0x00 "CM_IDLEST_NEON,Modules Access Availability Monitoring"
|
|
bitfld.long 0x00 0. " ST_NEON ,NEON standby status" "Active,Standby"
|
|
group.long 0x1348++0x3
|
|
line.long 0x00 "CM_CLKSTCTRL_NEON,HW Supervised Domain Power State Transition"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL_NEON ,Clock state transition of the NEON clock domain" "Disabled,Supervised sleep,Supervised wake-up,Auto"
|
|
group.long 0x1400++0x3 "USBHOST_CM"
|
|
line.long 0x00 "CM_FCLKEN_USBHOST,Controls The Modules Functional Clock Activity"
|
|
bitfld.long 0x00 1. " EN_USBHOST2 ,USB HOST 120-MHz functional clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_USBHOST1 ,USB HOST 48-MHz functional clock control" "Disabled,Enabled"
|
|
group.long 0x1410++0x3
|
|
line.long 0x00 "CM_ICLKEN_USBHOST,Controls The Modules Interface Clock Activity"
|
|
bitfld.long 0x00 0. " EN_USBHOST ,USB HOST Interface Clock Control" "Disabled,Enabled"
|
|
rgroup.long 0x1420++0x3
|
|
line.long 0x00 "CM_IDLEST_USBHOST,Modules Access Availability Monitoring"
|
|
bitfld.long 0x00 1. " ST_USBHOST_IDLE ,USB HOST idle status" "Active,Idle"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ST_USBHOST_STDBY ,USB HOST standby status" "Active,Standby"
|
|
group.long 0x1430++0x3
|
|
line.long 0x00 "CM_AUTOIDLE_USBHOST,Automatic Control Of The Modules Interface Clock Activity"
|
|
bitfld.long 0x00 0. " AUTO_USBHOST ,USB HOST auto clock control" "Unrelated,Auto enabled/disabled"
|
|
group.long 0x1444++0x3
|
|
line.long 0x00 "CM_SLEEPDEP_USBHOST,Sleep Transition Dependency Of USB HOST Domain Control"
|
|
bitfld.long 0x00 2. " EN_IVA2 ,IVA2 domain dependency" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Disabled,Enabled"
|
|
group.long 0x1448++0x3
|
|
line.long 0x00 "CM_CLKSTCTRL_USBHOST,Domain Power State Transition Control"
|
|
bitfld.long 0x00 0.--1. " CLKTRCTRL_USBHOST ,Controls the clock state transition of the USB HOST clock domain" "Disabled,Supervised sleep,Supervised wake-up,Auto enabled"
|
|
rgroup.long 0x144C++0x3
|
|
line.long 0x00 "CM_CLKSTST_USBHOST,Status On The Interface Clock Activity In The Domain"
|
|
bitfld.long 0x00 0. " CLKACTIVITY_USBHOST ,Interface clock activity status" "No domain,Domain"
|
|
width 0xb
|
|
tree.end
|
|
tree "Power Reset Management"
|
|
base ad:0x48306000
|
|
width 23.
|
|
group.long 0x50++0x3 "IVA2"
|
|
line.long 0x00 "RM_RSTCTRL_IVA2,Release Of The IVA2 Sub-system Reset Control"
|
|
bitfld.long 0x00 2. " RST3_IVA2 ,Video Sequencer reset control" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RST2_IVA2 ,IVA2 - MMU reset control and Video Hardware accelerator reset control" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RST1_IVA2 ,IVA2 - DSP reset control" "No reset,Reset"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "RM_RSTST_IVA2,Logs The Different Reset Sources Of The IVA2 Domain"
|
|
eventfld.long 0x00 13. " EMULATION_VSEQ_RST ,Emulation reset (Video SEQUENCER)" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 12. " EMULATION_VHWA_RST ,Emulation reset (Video Hardware accelerator)" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 11. " EMULATION_IVA2_RST ,Emulation reset IVA2 (DSP)" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 10. " IVA2_SW_RST3 ,Video Sequencer software reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IVA2_SW_RST2 ,IVA2-MMU software reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 8. " IVA2_SW_RST1 ,IVA2 - DSP software reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 3. " COREDOMAINWKUP_RST ,CORE domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DOMAINWKUP_RST ,Power domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "PM_WKDEP_IVA2,Wake-up Of The IVA2 Domain Enable"
|
|
bitfld.long 0x00 7. " EN_PER ,PERIPHERAL domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EN_DSS ,WAKEUP domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EN_WKUP ,WAKEUP domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_CORE ,CORE domain dependency" "Independent,Woken-up"
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "PM_PWSTCTRL_IVA2,IVA2 Domain Power State Transition Control"
|
|
bitfld.long 0x00 22.--23. " L2FLATMEMONSTATE ,L2 Flat memory state when domain is ON" "Reserved,Reserved,Reserved,Always on"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " SHAREDL2CACHEFLATONSTATE ,Shared L2 Cache and Flat memory state when domain is ON" "Off,Reserved,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " L1FLATMEMONSTATE ,L1 Flat memory state when domain is ON" "Reserved,Reserved,Reserved,Always on"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SHAREDL1CACHEFLATONSTATE ,Shared L1 Cache and Flat memory state when domain ON" "Reserved,Reserved,Reserved,Always on"
|
|
textline " "
|
|
bitfld.long 0x00 11. " L2FLATMEMRETSTATE ,L2 Flat memory state when domain is RETENTION" "Off,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SHAREDL2CACHEFLATRETSTATE ,Shared L2 Cache and Flat memory state when domain is RETENTION" "Off,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 9. " L1FLATMEMRETSTATE ,L1 Flat memory state when domain is RETENTION" "Off,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SHAREDL1CACHEFLATRETSTATE ,Shared L1 Cache and Flat memory state when domain is RETENTION" "Off,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MEMORYCHANGE ,Memory change control in ON state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when RETENTION" "Off,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "Off,Retention,Reserved,On"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x00 "PM_PWSTST_IVA2,Power State Transition Of The IVA2 Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " L2FLATMEMSTATEST ,L2 Flat memory state status" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " SHAREDL2CACHEFLATSTATEST ,Shared L2 Cache and Flat memory state status" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " L1FLATMEMSTATEST ,L1 Flat memory state status" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " SHAREDL1CACHEFLATSTATEST ,Shared L1 Cache and Flat memory state status" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Off,Retention,Inactive,On"
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "PM_PREPWSTST_IVA2,IVA2 Domain Previous Power State Status"
|
|
bitfld.long 0x00 10.--11. " LASTL2FLATMEMSTATEENTERED ,Last L2 Flat memory state entered" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LASTSHAREDL2CACHEFLATSTATEENTERED ,Shared L2 Cache and Flat memory last state entered" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " LASTL1FLATMEMSTATEENTERED ,Last L1 Flat memory state entered" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " LASTSHAREDL1CACHEFLATSTATEENTERED ,Shared L1 Cache and Flat memory last state entered" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LASTLOGICSTATEENTERED ,Last logic state entered" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " LASTPOWERSTATEENTERED ,Last power state entered" "Off,Retention,Inactive,On"
|
|
group.long 0xF8++0x7
|
|
line.long 0x00 "PRM_IRQSTATUS_IVA2,Interrupt Status Register"
|
|
eventfld.long 0x00 2. " IVA2_DPLL_ST ,DPLL2 recalibration event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " FORCEWKUP_ST ,Force wake-up IVA2 domain transition completed event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 0. " WKUP_ST ,IVA2 peripherals group (but FS USB) wake-up event status" "No interrupt,Interrupt"
|
|
line.long 0x04 "PRM_IRQENABLE_IVA2,Module Internal Sources Of Interrupt Enable"
|
|
bitfld.long 0x04 2. " IVA2_DPLL_RECAL_EN ,DPLL2 recalibration mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FORCEWKUP_EN ,Force wake-up IVA2 domain transition completed event mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " WKUP_EN ,IVA2 peripherals group (but FS USB) wake-up event mask" "Masked,Enabled"
|
|
rgroup.long 0x804++0x3 "OCP System Registers"
|
|
line.long 0x00 "PRM_REV,IP revision code"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP revision"
|
|
group.long 0x814++0xb
|
|
line.long 0x00 "PRM_SYSCONFIG,OCP Interface Various Parameters Control"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy" "Free-running,Auto"
|
|
line.long 0x04 "PRM_IRQSTATUS_MPU,Interrupt Status Register"
|
|
eventfld.long 0x04 25. " SND_PERIPH_DPLL_ST ,DPLL5 recalibration event status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 24. " VC_TIMEOUTERR_ST ,Voltage Controller timeout error event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 23. " VC_RAERR_ST ,Voltage Controller register address acknowledge error event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 22. " VC_SAERR_ST ,Voltage Controller slave address acknowledge error event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 21. " VP2_TRANXDONE_ST ,Voltage Processor 2 transaction completion status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 20. " VP2_EQVALUE_ST ,Voltage Processor 2 voltage value change event" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 19. " VP2_NOSMPSACK_ST ,Voltage Processor 2 timeout event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 18. " VP2_MAXVDD_ST ,Voltage Processor 2 voltage higher limit event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 17. " VP2_MINVDD_ST ,Voltage Processor 2 voltage lower limit event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 16. " VP2_OPPCHANGEDONE_ST ,Voltage Processor 2 OPP change done status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 15. " VP1_TRANXDONE_ST ,Voltage Processor 1 transaction completion status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 14. " VP1_EQVALUE_ST ,Voltage Processor 1 voltage value change event" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 13. " VP1_NOSMPSACK_ST ,Voltage Processor 1 timeout event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 12. " VP1_MAXVDD_ST ,Voltage Processor 1 voltage higher limit event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 11. " VP1_MINVDD_ST ,Voltage Processor 1 voltage lower limit event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 10. " VP1_OPPCHANGEDONE_ST ,Voltage Processor 1 OPP change done status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 9. " IO_ST ,IO pad event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 8. " IVA2_DPLL_ST ,DPLL2 recalibration event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 7. " MPU_DPLL_ST ,DPLL1 recalibration event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 6. " PERIPH_DPLL_ST ,DPLL4 recalibration event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 5. " CORE_DPLL_ST ,DPLL3 recalibration event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 4. " TRANSITION_ST ,Software supervised transition completed event status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 3. " EVGENOFF_ST ,Event Generator endOFFtime status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 2. " EVGENON_ST ,Event Generator endONtime status" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x04 0. " WKUP_ST ,MPU peripherals group wake-up event status" "No interrupt,Interrupt"
|
|
line.long 0x08 "PRM_IRQENABLE_MPU,Module Internal Sources Of Enabled Enable"
|
|
bitfld.long 0x08 25. " SND_PERIPH_DPLL_RECAL_EN ,DPLL5 recalibration mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " VC_TIMEOUTERR_EN ,Voltage Controller timeout error mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " VC_RAERR_EN ,Voltage Controller register address acknowledge error mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " VC_SAERR_EN ,Voltage Controller slave address acknowledge error mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " VP2_TRANXDONE_EN ,Voltage Processor 2 transaction completion mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " VP2_EQVALUE_EN ,Voltage Processor 2 voltage value change mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " VP2_NOSMPSACK_EN ,Voltage Processor 2 timeout mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " VP2_MAXVDD_EN ,Voltage Processor 2 voltage higher limit mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " VP2_MINVDD_EN ,Voltage Processor 2 voltage lower limit mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " VP2_OPPCHANGEDONE_EN ,Voltage Processor 2 OPP change done mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " VP1_TRANXDONE_EN ,Voltage Processor 1 transaction completion mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " VP1_EQVALUE_EN ,Voltage Processor 1 voltage value change mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " VP1_NOSMPSACK_EN ,Voltage Processor 1 timeout mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " VP1_MAXVDD_EN ,Voltage Processor 1 voltage higher limit mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " VP1_MINVDD_EN ,Voltage Processor 1 voltage lower limit mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " VP1_OPPCHANGEDONE_EN ,Voltage Processor 1 OPP change done mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " IO_EN ,IO pad mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " IVA2_DPLL_RECAL_EN ,DPLL2 recalibration mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MPU_DPLL_RECAL_EN ,DPLL1 recalibration mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " PERIPH_DPLL_RECAL_EN ,DPLL4 recalibration mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " CORE_DPLL_RECAL_EN ,DPLL3 recalibration mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " TRANSITION_EN ,Software supervised transition completed mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " EVGENOFF_EN ,Event Generator endOFFtime mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " EVGENON_EN ,Event Generator endONtime mask" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " WKUP_EN ,MPU peripherals group wake-up mask" "Masked,Enabled"
|
|
group.long 0x958++0x3 "MPU"
|
|
line.long 0x00 "RM_RSTST_MPU,Different Reset Sources Of The MPU Domain Log"
|
|
eventfld.long 0x00 11. " EMULATION_MPU_RST ,Emulation reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 3. " COREDOMAINWKUP_RST ,CORE domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DOMAINWKUP_RST ,Power domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0x9C8++0x3
|
|
line.long 0x00 "PM_WKDEP_MPU,Wake-up Of The MPU Domain Enable"
|
|
bitfld.long 0x00 7. " EN_PER ,PERIPHERAL domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EN_DSS ,DSS domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EN_IVA2 ,IVA2 domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_CORE ,CORE domain dependency" "Independent,Woken-up"
|
|
group.long 0x9D4++0xF
|
|
line.long 0x00 "PM_EVGENCTRL_MPU,Event Generator Control"
|
|
bitfld.long 0x00 3.--4. " OFFLOADMODE ,OFF load mode setting" "Update PM_EVGENOFFTIM_MPU,Reserved,MPU standby,Auto"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " ONLOADMODE ,ON load mode setting" "Update PM_EVGENOFFTIM_MPU,MPU standby,Reserved,Auto"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Event generator control" "Disabled,Enabled"
|
|
line.long 0x04 "PM_EVGENONTIM_MPU,ON Count Duration Of The Event Generator"
|
|
line.long 0x08 "PM_EVGENOFFTIM_MPU,OFF Count Duration Of The Event Generator"
|
|
line.long 0x0C "PM_PWSTCTRL_MPU,MPU Domain Power State Transition Control"
|
|
bitfld.long 0x0C 16.--17. " L2CACHEONSTATE ,L2 Cache memory state when domain is ON" "Off,Reserved,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " L2CACHERETSTATE ,L2 Cache memory state when domain is RETENTION" "Off,Retained"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " MEMORYCHANGE ,Memory change control in ON state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " LOGICL1CACHERETSTATE ,Logic and L1 Cache state when domain is RETENTION" "Off,Retained"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " POWERSTATE ,Power state control" "Off,Retention,Reserved,On"
|
|
rgroup.long 0x9E4++0x3
|
|
line.long 0x00 "PM_PWSTST_MPU,MPU Domain Power State Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " L2CACHESTATEST ,L2 Cache memory state status" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOGICL1CACHESTATEST ,Logic and L1 Cache state status" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Off,Retention,Inactive,On"
|
|
group.long 0x9E8++0x3
|
|
line.long 0x00 "PM_PREPWSTST_MPU,MPU Domain Previous Power State Status"
|
|
bitfld.long 0x00 6.--7. " LASTL2CACHESTATEENTERED ,Last L2 Cache memory state entered" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LASTLOGICL1CACHESTATEENTERED ,Last logic and L1 Cache state entered" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " LASTPOWERSTATEENTERED ,Last power state entered" "Off,Retention,Inactive,On"
|
|
group.long 0xA58++0x3 "CORE"
|
|
line.long 0x00 "RM_RSTST_CORE,Different Reset Sources Of The CORE Domain Log"
|
|
eventfld.long 0x00 2. " DOMAINWKUP_RST ,Power domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0xAA0++0xb
|
|
line.long 0x00 "PM_WKEN1_CORE,Modules Wake-up Events Enable"
|
|
bitfld.long 0x00 30. " EN_MMC3 ,MMC SDIO 3 wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EN_MMC2 ,MMC SDIO 2 wake-up is disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " EN_MMC1 ,MMC SDIO 1 wake-up is disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " EN_MCSPI4 ,McSPI 4 wake-up is disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " EN_MCSPI3 ,McSPI 3 wake-up is disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " EN_MCSPI2 ,McSPI 2 wake-up is disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " EN_MCSPI1 ,McSPI 1 wake-up is disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EN_I2C3 ,I2C 3 wake-up is disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EN_I2C2 ,I2C 2 wake-up is disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_I2C1 ,I2C 1 wake-up is disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EN_UART2 ,UART 2 wake-up is disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EN_UART1 ,UART 1 wake-up is disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " EN_GPT11 ,GPTIMER 11 wake-up is disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EN_GPT10 ,GPTIMER 10 wake-up is disabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " EN_MCBSP5 ,McBSP 5 wake-up is disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EN_MCBSP1 ,McBSP 1 wake-up is disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EN_HSOTGUSB ,HS OTG USB wake-up is disabled" "Disabled,Enabled"
|
|
line.long 0x04 "PM_MPUGRPSEL1_CORE,Group Of Modules That Wake-up The MPU"
|
|
bitfld.long 0x04 30. " GRPSEL_MMC3 , Select the MMC 3 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 25. " GRPSEL_MMC2 ,MMC 2 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 24. " GRPSEL_MMC1 ,MMC 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 21. " GRPSEL_MCSPI4 ,McSPI 4 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 20. " GRPSEL_MCSPI3 ,McSPI 3 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 19. " GRPSEL_MCSPI2 ,McSPI 2 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 18. " GRPSEL_MCSPI1 ,McSPI 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 17. " GRPSEL_I2C3 ,I2C 3 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 16. " GRPSEL_I2C2 ,I2C 2 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 15. " GRPSEL_I2C1 ,I2C 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 14. " GRPSEL_UART2 ,UART 2 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 13. " GRPSEL_UART1 ,UART 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 12. " GRPSEL_GPT11 ,GPTIMER 11 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 11. " GRPSEL_GPT10 ,GPTIMER 10 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 10. " GRPSEL_MCBSP5 ,McBSP 5 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 9. " GRPSEL_MCBSP1 ,McBSP 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 4. " GRPSEL_HSOTGUSB ,HS OTG USB in the MPU wake-up events group" "Not attached,Attached"
|
|
line.long 0x08 "IVA2GRPSEL1_CORE,Group Of Modules That Wake-up The IVA2"
|
|
bitfld.long 0x08 30. " GRPSEL_MMC3 ,Select the MMC 3 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 25. " GRPSEL_MMC2 ,MMC 2 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 24. " GRPSEL_MMC1 ,MMC 1 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 21. " GRPSEL_MCSPI4 ,McSPI 4 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 20. " GRPSEL_MCSPI3 ,McSPI 3 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 19. " GRPSEL_MCSPI2 ,McSPI 2 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 18. " GRPSEL_MCSPI1 ,McSPI 1 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 17. " GRPSEL_I2C3 ,I2C 3 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 16. " GRPSEL_I2C2 ,I2C 2 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 15. " GRPSEL_I2C1 ,I2C 1 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 14. " GRPSEL_UART2 ,UART 2 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 13. " GRPSEL_UART1 ,UART 1 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 12. " GRPSEL_GPT11 ,GPTIMER 11 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 11. " GRPSEL_GPT10 ,GPTIMER 10 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 10. " GRPSEL_MCBSP5 ,McBSP 5 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 9. " GRPSEL_MCBSP1 ,McBSP 1 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 4. " GRPSEL_HSOTGUSB ,HS OTG USB in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
group.long 0xAB0++0x3
|
|
line.long 0x00 "PM_WKST1_CORE,Modules Wake-up Events Log"
|
|
eventfld.long 0x00 30. " ST_MMC3 ,MMC 3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 25. " ST_MMC2 ,MMC 2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 24. " ST_MMC1 ,MMC 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 21. " ST_MCSPI4 ,McSPI 4 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 20. " ST_MCSPI3 ,McSPI 3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 19. " ST_MCSPI2 ,McSPI 2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 18. " ST_MCSPI1 ,McSPI 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 17. " ST_I2C3 ,I2C 3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ST_I2C2 ,I2C 2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 15. " ST_I2C1 ,I2C 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ST_UART2 ,UART 2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ST_UART1 ,UART 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 12. " ST_GPT11 ,GPTIMER 11 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ST_GPT10 ,GPTIMER 10 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ST_MCBSP5 ,McBSP 5 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ST_MCBSP1 ,McBSP 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ST_HSOTGUSB ,HS OTG USB Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
group.long 0xAB8++0x3
|
|
line.long 0x00 "PM_WKST3_CORE,Modules Wake-up Events Log"
|
|
bitfld.long 0x00 2. " ST_USBTLL ,USB TLL Wake-up status" "Not occurred,Occurred"
|
|
group.long 0xAE0++0x3
|
|
line.long 0x00 "PM_PWSTCTRL_CORE,CORE Domain Power State Transition Control"
|
|
bitfld.long 0x00 18.--19. " MEM2ONSTATE ,Memory block 2 state when domain is ON" "Off,Retention,Reserved,On"
|
|
bitfld.long 0x00 16.--17. " MEM1ONSTATE ,Memory block 1 state when domain is ON" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MEM2RETSTATE ,Memory block 2 state when domain is RETENTION" "Off,Retained"
|
|
bitfld.long 0x00 8. " MEM1RETSTATE ,Memory block 1 state when domain is RETENTION" "Off,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SAVEANDRESTORE ,Save And Restore mechanism for the USB TLL module" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MEMORYCHANGE ,Memory change control in ON state" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when domain is RETENTION" "Off,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "Off,Retention,Reserved,On"
|
|
rgroup.long 0xAE4++0x3
|
|
line.long 0x00 "PM_PWSTST_CORE,Power State Transition Of The CORE Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
bitfld.long 0x00 6.--7. " MEM2STATEST ,Memory block 2 state status" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MEM1STATEST ,Memory block 1 state status" "Off,Retention,Reserved,On"
|
|
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Off,Retention,Inactive,On"
|
|
group.long 0xAE8++0x3
|
|
line.long 0x00 "PM_PREPWSTST_CORE,CORE Domain Previous Power State Status"
|
|
bitfld.long 0x00 6.--7. " LASTMEM2STATEENTERED ,Last Memory block 2 state entered" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " LASTMEM1STATEENTERED ,Last Memory block 1 state entered" "Off,Retention,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LASTLOGICSTATEENTERED ,Last logic state entered" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " LASTPOWERSTATEENTERED ,Last power state entered" "Off,Retention,Inactive,On"
|
|
group.long 0xAF0++0xB
|
|
line.long 0x00 "PM_WKEN3_CORE,Enabling/Disabling Modules Wake-up Events"
|
|
bitfld.long 0x00 2. " EN_USBTLL ,USB TLL wake-up control" "Disabled,Enabled"
|
|
line.long 0x04 "PM_IVA2GRPSEL3_CORE,Selecting The Group Of Modules That Wake-up The IVA2"
|
|
bitfld.long 0x04 2. " GRPSEL_USBTLL ,Select the USB TLL in the IVA2 wake-up events group" "Not attached,Attached"
|
|
line.long 0x08 "PM_MPUGRPSEL3_CORE,Selecting The Group Of Modules That Wake-up The MPU"
|
|
bitfld.long 0x08 2. " GRPSEL_USBTLL ,Select the USB TLL in the MPU wake-up events group" "Not attached,Attached"
|
|
group.long 0xB58++0x3 "SGX"
|
|
line.long 0x00 "RM_RSTST_SGX,Different Reset Sources Of The SGX Domain Log"
|
|
eventfld.long 0x00 3. " COREDOMAINWKUP_RST ,CORE domain wake-up reset" "No Reset,Reset"
|
|
eventfld.long 0x00 2. " DOMAINWKUP_RST ,Power domain wake-up reset" "No Reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No Reset,Reset"
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No Reset,Reset"
|
|
group.long 0xBC8++0x3
|
|
line.long 0x00 "PM_WKDEP_SGX,Wake-up Of The SGX Domain Enable"
|
|
bitfld.long 0x00 4. " EN_WKUP ,WAKEUP domain dependency" "Independent,Woken-up"
|
|
bitfld.long 0x00 2. " EN_IVA2 ,IVA2 domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Independent,Woken-up"
|
|
group.long 0xBE0++0x3
|
|
line.long 0x00 "PM_PWSTCTRL_SSGX,SGX Domain Power State Transition Control"
|
|
bitfld.long 0x00 16.--17. " MEMONSTATE ,Memory state when ON" "Reserved,Reserved,Reserved,Always On"
|
|
bitfld.long 0x00 8. " MEMRETSTATE ,Memory state when RETENTION" "Reserved,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when RETENTION" "Off,Retained"
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "Off,Retention,Reserved,On"
|
|
rgroup.long 0xBE4++0x3
|
|
line.long 0x00 "PM_PWSTST_SGX,Power State Transition Of The SGX Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Off,Retention,Inactive,On"
|
|
group.long 0xBE8++0x3
|
|
line.long 0x00 "PM_PREPWSTST_SGX,SGX Domain Previous Power State Status"
|
|
bitfld.long 0x00 0.--1. " LASTPOWERSTATEENTERED ,Last power state entered" "Off,Retention,Inactive,On"
|
|
group.long 0xCA0++0xb "WKUP"
|
|
line.long 0x00 "PM_WKEN_WKUP,Modules Wake-up Events Enable"
|
|
bitfld.long 0x00 9. " EN_USIMOCP ,USIMOCP wake-up control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EN_IO ,IO pad wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EN_SR2 ,Smart Refex 2 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EN_SR1 ,Smart Refex 1 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EN_GPIO1 ,GPIO 1 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_GPT12 ,GPTIMER 12 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN_GPT1 ,GPTIMER 1 wake-up enable" "Disabled,Enabled"
|
|
line.long 0x04 "PM_MPUGRPSEL_WKUP,MPU Wake-up Events Group"
|
|
bitfld.long 0x04 9. " GRPSEL_USIMOCP ,Select the USIMOCP in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 8. " GRPSEL_IO ,IO pad in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 7. " GRPSEL_SR2 ,Smart Reflex 2 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 6. " GRPSEL_SR1 ,Smart Reflex 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 3. " GRPSEL_GPIO1 ,GPIO 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 1. " GRPSEL_GPT12 ,GPTIMER 12 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 0. " GRPSEL_GPT1 ,GPTIMER 1 in the MPU wake-up events group" "Not attached,Attached"
|
|
line.long 0x08 "PM_IVA2GRPSEL_WKUP,IVA2 Wake-up Events Group"
|
|
bitfld.long 0x08 9. " GRPSEL_USIMOCP ,Select the USIMOCP in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 8. " GRPSEL_IO ,IO pad in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 7. " GRPSEL_SR2 ,Smart Reflex 2 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 6. " GRPSEL_SR1 ,Smart Reflex 1 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 3. " GRPSEL_GPIO1 ,GPIO 1 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 1. " GRPSEL_GPT12 ,GPTIMER 12 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 0. " GRPSEL_GPT1 ,GPTIMER 1 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
group.long 0xCB0++0x3
|
|
line.long 0x00 "PM_WKST_WKUP,Modules Wake-up Events Log"
|
|
eventfld.long 0x00 9. " ST_USIMOCP ,USIMOCP Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ST_IO ,IO pad Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 7. " GRPSEL_SR2 ,Smart Reflex 2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ST_SR1 ,Smart Reflex 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ST_GPIO1 ,GPIO 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ST_GPT12 ,GPTIMER 12 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ST_GPT1 ,GPTIMER 1 Wake-up status" "Not occurred/masked,Occurred"
|
|
group.long 0xD40++0x3 "Clock Control Registers"
|
|
line.long 0x00 "PRM_CLKSEL,System Clock Frequency Selection"
|
|
bitfld.long 0x00 0.--2. " SYS_CLKIN_SEL ,System clock input selection (INCLK)" "12MHz,13MHz,19.2MHz,26MHz,38.4MHz,16.8MHz,?..."
|
|
group.long 0xD70++0x3
|
|
line.long 0x00 "PRM_CLKOUT_CTRL,SYS_CLKOUT1 Output Clock Control"
|
|
bitfld.long 0x00 7. " CLKOUT_EN ,External output clock activity (sys_clkout1)" "Disabled,Enabled"
|
|
group.long 0xE58++0x3 "DSS"
|
|
line.long 0x00 "RM_RSTST_DSS,Different Reset Sources Of The DSS Domain Log"
|
|
eventfld.long 0x00 3. " COREDOMAINWKUP_RST ,CORE domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DOMAINWKUP_RST ,Power domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0xEA0++0x3
|
|
line.long 0x00 "PM_WKEN_DSS,Modules Wake-up Events Enable"
|
|
bitfld.long 0x00 0. " EN_DSS ,DSS Wake-up enable" "Disabled,Enabled"
|
|
group.long 0xEC8++0x3
|
|
line.long 0x00 "PM_WKDEP_DSS,Wake-up Of The DISPLAY Domain Enable"
|
|
bitfld.long 0x00 4. " EN_WKUP ,WAKEUP domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EN_IVA2 ,IVA2 domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Independent,Woken-up"
|
|
group.long 0xEE0++0x3
|
|
line.long 0x00 "PM_PWSTCTRL_DSS,DISPLAY Domain Power State Transition Control"
|
|
bitfld.long 0x00 16.--17. " MEMONSTATE ,Memory state when ON" "Reserved,Reserved,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MEMRETSTATE ,Memory state when RETENTION" "Reserved,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when RETENTION" "Reserved,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "Off,Retention,Reserved,On"
|
|
rgroup.long 0xEE4++0x3
|
|
line.long 0x00 "PM_PWSTST_DSS,Power State Transition Of The DSS Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Off,Retention,Inactive,On"
|
|
group.long 0xEE8++0x3
|
|
line.long 0x00 "PM_PREPWSTST_DSS,DSS Domain Previous Power State Status"
|
|
bitfld.long 0x00 0.--1. " LASTPOWERSTATEENTERED ,Last power state entered" "Off,Retention,Inactive,On"
|
|
group.long 0xF58++0x3 "CAM"
|
|
line.long 0x00 "RM_RSTST_CAM,Different Reset Sources Of The CAMERA Domain Log"
|
|
eventfld.long 0x00 3. " COREDOMAINWKUP_RST ,CORE domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DOMAINWKUP_RST ,Power domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0xFC8++0x3
|
|
line.long 0x00 "PM_WKDEP_CAM,Wake-up Of The CAMERA Domain Enable"
|
|
bitfld.long 0x00 4. " EN_WKUP ,WAKEUP domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EN_IVA2 ,IVA2 domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Independent,Woken-up"
|
|
group.long 0xFE0++0x3
|
|
line.long 0x00 "PM_PWSTCTRL_CAM,CORE Domain Power State Transition Control"
|
|
bitfld.long 0x00 16.--17. " MEMONSTATE ,Memory state when ON" "Reserved,Reserved,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MEMRETSTATE ,Memory state when RETENTION" "Reserved,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when RETENTION" "Reserved,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "Off,Retention,Reserved,On"
|
|
rgroup.long 0xFE4++0x3
|
|
line.long 0x00 "PM_PWSTST_CAM,Power State Transition Of The CAMERA Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Off,Retention,Inactive,On"
|
|
group.long 0xFE8++0x3
|
|
line.long 0x00 "PM_PREPWSTST_CAM,CAMERA Domain Previous Power State Status"
|
|
bitfld.long 0x00 0.--1. " LASTPOWERSTATEENTERED ,Last power state entered" "Off,Retention,Inactive,On"
|
|
group.long 0x1058++0x3 "PER"
|
|
line.long 0x00 "RM_RSTST_PER,Different Reset Sources Of The PERIPHERAL Domain Log"
|
|
eventfld.long 0x00 3. " COREDOMAINWKUP_RST ,CORE domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DOMAINWKUP_RST ,Power domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0x10A0++0xb
|
|
line.long 0x00 "PM_WKEN_PER,Modules Wake-up Events Enable"
|
|
bitfld.long 0x00 17. " EN_GPIO6 ,GPIO6 Wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EN_GPIO5 ,GPIO5 Wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " EN_GPIO4 ,GPIO4 Wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " EN_GPIO3 ,GPIO3 Wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EN_GPIO2 ,GPIO2 Wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " EN_UART3 ,UART3 Wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " EN_GPT9 ,GPT9 Wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " EN_GPT8 ,GPT8 Wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " EN_GPT7 ,GPT7 Wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EN_GPT6 ,GPT6 Wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EN_GPT5 ,GPT5 Wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EN_GPT4 ,GPT4 Wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EN_GPT3 ,GPT3 Wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EN_GPT2 ,GPT2 Wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EN_MCBSP4 ,MCBSP4 Wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " EN_MCBSP3 ,MCBSP3 Wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_MCBSP2 ,MCBSP2 Wake-up enable" "Disabled,Enabled"
|
|
line.long 0x04 "PM_MPUGRPSEL_PER,Group Of Modules That Wake-up The MPU"
|
|
bitfld.long 0x04 17. " GRPSEL_GPIO6 ,GPIO6 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 16. " GRPSEL_GPIO5 ,GPIO5 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 15. " GRPSEL_GPIO4 ,GPIO4 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 14. " GRPSEL_GPIO3 ,GPIO3 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 13. " GRPSEL_GPIO2 ,GPIO2 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 11. " GRPSEL_UART3 ,UART3 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 10. " GRPSEL_GPT9 ,GPT9 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 9. " GRPSEL_GPT8 ,GPT8 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 8. " GRPSEL_GPT7 ,GPT7 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 7. " GRPSEL_GPT6 ,GPT6 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 6. " GRPSEL_GPT5 ,GPT5 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 5. " GRPSEL_GPT4 ,GPT4 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 4. " GRPSEL_GPT3 ,GPT3 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 3. " GRPSEL_GPT2 ,GPT2 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 2. " GRPSEL_MCBSP4 ,MCBSP4 in the MPU wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x04 1. " GRPSEL_MCBSP3 ,MCBSP3 in the MPU wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 0. " GRPSEL_MCBSP2 ,MCBSP2 in the MPU wake-up events group" "Not attached,Attached"
|
|
line.long 0x08 "PM_IVA2GRPSEL_PER,Group Of Modules That Wake-up The IVA2"
|
|
bitfld.long 0x08 17. " GRPSEL_GPIO6 ,GPIO6 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 16. " GRPSEL_GPIO5 ,GPIO5 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 15. " GRPSEL_GPIO4 ,GPIO4 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 14. " GRPSEL_GPIO3 ,GPIO3 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 13. " GRPSEL_GPIO2 ,GPIO2 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 11. " GRPSEL_UART3 ,UART3 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 10. " GRPSEL_GPT9 ,GPT9 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 9. " GRPSEL_GPT8 ,GPT8 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 8. " GRPSEL_GPT7 ,GPT7 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 7. " GRPSEL_GPT6 ,GPT6 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 6. " GRPSEL_GPT5 ,GPT5 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 5. " GRPSEL_GPT4 ,GPT4 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 4. " GRPSEL_GPT3 ,GPT3 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 3. " GRPSEL_GPT2 ,GPT2 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 2. " GRPSEL_MCBSP4 ,MCBSP4 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
bitfld.long 0x08 1. " GRPSEL_MCBSP3 ,MCBSP3 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
textline " "
|
|
bitfld.long 0x08 0. " GRPSEL_MCBSP2 ,MCBSP2 in the IVA2 wake-up events group" "Not attached,Attached"
|
|
group.long 0x10B0++0x3
|
|
line.long 0x00 "PM_WKST_PER,Modules Wake-up Events"
|
|
eventfld.long 0x00 17. " ST_GPIO6 ,GPIO6 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 16. " ST_GPIO5 ,GPIO5 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 15. " ST_GPIO4 ,GPIO4 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 14. " ST_GPIO3 ,GPIO3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 13. " ST_GPIO2 ,GPIO2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 11. " ST_UART3 ,UART3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 10. " ST_GPT9 ,GPT9 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 9. " ST_GPT8 ,GPT8 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ST_GPT7 ,GPT7 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 7. " ST_GPT6 ,GPT6 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " ST_GPT5 ,GPT5 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ST_GPT4 ,GPT4 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ST_GPT3 ,GPT3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ST_GPT2 ,GPT2 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ST_MCBSP4 ,MCBSP4 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ST_MCBSP3 ,MCBSP3 Wake-up status" "Not occurred/masked,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ST_MCBSP2 ,MCBSP2 Wake-up status" "Not occurred/masked,Occurred"
|
|
group.long 0x10C8++0x3
|
|
line.long 0x00 "PM_WKDEP_PER,Wake-up Of The PERIPHERAL Domain Enable"
|
|
bitfld.long 0x00 4. " EN_WKUP ,WAKEUP domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EN_IVA2 ,IVA2 domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_CORE ,CORE domain dependency" "Woken-up,Not woken-up"
|
|
group.long 0x10E0++0x3
|
|
line.long 0x00 "PM_PWSTCTRL_PER,PERIPHERAL Domain Power State Transition Control"
|
|
bitfld.long 0x00 16.--17. " MEMONSTATE ,Memory state when ON" "Reserved,Reserved,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MEMRETSTATE ,Memory state when RETENTION" "Reserved,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when RETENTION" "Reserved,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "Off,Retention,Reserved,On"
|
|
rgroup.long 0x10E4++0x3
|
|
line.long 0x00 "PM_PWSTST_PER,Power State Transition Of The PERIPHERAL Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOGICSTATEST , Logic state status" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Off,Retention,Inactive,On"
|
|
group.long 0x10E8++0x3
|
|
line.long 0x00 "PM_PREPWSTST_PER,PERIPHERAL Domain Previous Power State Status"
|
|
bitfld.long 0x00 2. " LASTLOGICSTATEENTERED ,Last logic state entered" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " LASTPOWERSTATEENTERED ,Last power state entered" "Off,Retention,Inactive,On"
|
|
group.long 0x1158++0x3 "EMU"
|
|
line.long 0x00 "RM_RSTST_EMU,Different Reset Sources Of The EMULATION Domain Log"
|
|
eventfld.long 0x00 2. " DOMAINWKUP_RST ,Power domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
rgroup.long 0x11E4++0x3
|
|
line.long 0x00 "PM_PWSTST_EMU,Power State Transition Of The EMULATION Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Off,Reserved,Reserved,On"
|
|
group.long 0x1220++0x1F "Global Registers"
|
|
line.long 0x00 "PRM_VC_SMPS_SA,I2C Slave Address Of The Power IC Device Set"
|
|
hexmask.long.byte 0x00 16.--22. 1. " SA1 ,I2C slave address value for the second Power IC device"
|
|
hexmask.long.byte 0x00 0.--6. 1. " SA0 ,I2C slave address value for the first Power IC device"
|
|
line.long 0x04 "PRM_VC_SMPS_VOL_RA,Voltage Configuration Register Address For The VDD Channels Set"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VOLRA1 ,Voltage configuration register address for the second VDD channel"
|
|
hexmask.long.byte 0x04 0.--7. 1. " VOLRA0 ,Voltage configuration register address for the first VDD channel"
|
|
line.long 0x08 "PRM_VC_SMPS_CMD_RA,ON/Retention/OFF Command Configuration Register Address For The VDD Channels Set"
|
|
hexmask.long.byte 0x08 16.--23. 1. " CMDRA1 ,ON/ON-LP/Retention/OFF command configuration register address for the second VDD channel"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CMDRA0 ,ON/ON-LP/Retention/OFF command configuration register address for the first VDD channel"
|
|
line.long 0x0C "PRM_VC_CMD_VAL_0,ON/Retention/OFF Voltage Level Values For The First VDD Channels Set"
|
|
hexmask.long.byte 0x0c 24.--31. 1. " ON ,ON voltage level value for the first VDD channel"
|
|
hexmask.long.byte 0x0c 16.--23. 1. " ONLP ,ON-LP voltage level value for the first VDD channel"
|
|
textline " "
|
|
hexmask.long.byte 0x0c 8.--15. 1. " RET ,RET voltage level value for the first VDD channel"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " OFF ,OFF voltage level value for the first VDD channel"
|
|
line.long 0x10 "PRM_VC_CMD_VAL_1,ON/Retention/OFF Voltage Level Values For The Second VDD Channel"
|
|
hexmask.long.byte 0x10 24.--31. 1. " ON ,ON voltage level value for the Second VDD channel"
|
|
hexmask.long.byte 0x10 16.--23. 1. " ONLP ,ON-LP voltage level value for the first VDD channel"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " RET ,RET voltage level value for the Second VDD channel"
|
|
hexmask.long.byte 0x10 0.--7. 1. " OFF ,OFF voltage level value for the Second VDD channel"
|
|
line.long 0x14 "PRM_VC_CH_CONF,Configuration Pointers For Both VDD Channels"
|
|
bitfld.long 0x14 20. " CMD1 ,ON/ON-LP/Retention/OFF voltage values" "Not select,Select"
|
|
bitfld.long 0x14 19. " RACEN1 ,Enable bit for usage of RAC1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 18. " RAC1 ,ON/ON-LP/Retention/OFF command configuration register address pointer" "Not set,Set"
|
|
bitfld.long 0x14 17. " RAV1 ,voltage configuration register address pointer" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x14 16. " SA1 ,Set the slave address pointer for the second VDD channel" "Not set,Set"
|
|
bitfld.long 0x14 4. " CMD0 ,ON/ON-LP/Retention/OFF voltage values" "Not select,Select"
|
|
textline " "
|
|
bitfld.long 0x14 3. " RACEN0 ,Enable bit for usage of RAC0" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " RAC0 ,ON/ON-LP/Retention/OFF command configuration register address pointer" "Not set,Set"
|
|
textline " "
|
|
bitfld.long 0x14 1. " RAV0 ,voltage configuration register address pointer" "Not set,Set"
|
|
bitfld.long 0x14 0. " SA0 ,slave address pointer for the first VDD channel" "Not set,Set"
|
|
line.long 0x18 "PRM_VC_I2C_CFG,Configuration Pointers For Both VDD Channels"
|
|
bitfld.long 0x18 5. " HSMASTER ,I2C pads in a low power mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 4. " SREN ,I2C repeated start operation mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 3. " HSEN ,I2C bus High Speed mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0.--2. " MCODE ,Master code value for I2C High Speed preamble transmission" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "PRM_VC_BYPASS_VAL,Power IC Device Using The Bypass Interface"
|
|
bitfld.long 0x1C 24. " VALID ,validates the bypass command" "Acknowledged,Pending"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " DATA ,Data to send to the Power IC device"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 8.--15. 1. " REGADDR ,address of Power IC device register"
|
|
hexmask.long.byte 0x1C 0.--6. 1. " SLAVEADDR ,I2C slave address value"
|
|
group.long 0x1250++0xb
|
|
line.long 0x00 "PRM_RSTCTRL,Global Software And DPLL3 Reset Control"
|
|
bitfld.long 0x00 2. " RST_DPLL3 ,DPLL3 software reset control" "Cleared,Asserted"
|
|
bitfld.long 0x00 1. " RST_GS ,Global software reset control" "Cleared,Asserted"
|
|
line.long 0x04 "PRM_RSTTIME,Reset Duration Control"
|
|
hexmask.long.byte 0x04 8.--12. 1. " RSTTIME2 ,reset duration 2"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RSTTIME1 ,reset duration 1"
|
|
line.long 0x08 "PRM_RSTST,Global Reset Sources Log"
|
|
eventfld.long 0x08 10. " ICECRUSHER_RST ,IceCrusher reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 9. " ICEPICK_RST ,IcePick reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 8. " VDD2_VOLTAGE_MANAGER_RST ,VDD2 voltage manager reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 7. " VDD1_VOLTAGE_MANAGER_RST ,VDD1 voltage manager reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 6. " EXTERNAL_WARM_RST ,External warm reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 5. " SECURE_WD_RST ,Secure watchdog reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 4. " MPU_WD_RST ,MPU watchdog reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 3. " SECURITY_VIOL_RST ,Security violation reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 1. " GLOBAL_SW_RST ,Global software reset event" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x08 0. " GLOBAL_COLD_RST ,Power-up (cold) reset event" "No reset,Reset"
|
|
group.long 0x1260++0x7
|
|
line.long 0x00 "PRM_VOLTCTRL,External Power IC Control"
|
|
bitfld.long 0x00 4. " SEL_VMODE ,select the mode used to control the Power IC (I2C or VMODE)" "I2C,VMODE"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SEL_OFF ,send the OFF command" "I2C interface,SYSOFF_MODE asserted"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AUTO_OFF ,OFF command" "Not send,Auto send"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AUTO_RET ,RETENTION command" "Not send,Auto send"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_SLEEP ,SLEEP command" "Not send,Auto send"
|
|
line.long 0x04 "PRM_SRAM_PCHARGE,Pre-charge Time Of The SRAM"
|
|
hexmask.long.byte 0x04 0.--7. 1. " PCHARGE_TIME ,Number of system clock cycles for the SRAM pre-charge duration"
|
|
group.long 0x1270++0x3
|
|
line.long 0x00 "PRM_CLKSRC_CTRL,Device Source Clock Control"
|
|
bitfld.long 0x00 6.--7. " SYSCLKDIV ,System clock input divider" "EXCLK/1,EXCLK/2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " AUTOEXTCLKMODE ,External clock request and oscillator control (CLKREQ voltages domains)" "Asserted/Osc active,Sleep/Retention/Off,Retention/Off,Off"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SYSCLKSEL ,Mode of the ocillator" "Bypass,Oscillator,Reserved,Unknow state"
|
|
rgroup.long 0x1280++0x3
|
|
line.long 0x00 "PRM_OBS,Observable Signals Log"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " OBS_BUS ,Indicates the current value on the observable bus"
|
|
group.long 0x1290++0xF
|
|
line.long 0x00 "PRM_VOLTSETUP1,Setup Time Of The VDD1 And VDD2 Regulators Set"
|
|
hexmask.long.word 0x00 16.--31. 1. " SETUP_TIME2 ,Duration of VDD2 regulator"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--15. 1. " SETUP_TIME1 ,Duration of VDD1 regulator"
|
|
line.long 0x04 "PRM_VOLTOFFSET,Set Offset-time"
|
|
hexmask.long.word 0x04 0.--15. 1. " OFFSET_TIME ,Number of 32kHz clock cycles for the OFF mode offset time"
|
|
line.long 0x08 "PRM_CLKSETUP,Setup Time Of The Oscillator System Clock"
|
|
hexmask.long.word 0x08 0.--15. 1. " SETUP_TIME ,Number of 32kHz clock cycles for the SETUP duration"
|
|
line.long 0x0C "PRM_POLCTRL,Polarity Of Device Outputs Control Signals"
|
|
bitfld.long 0x0C 3. " OFFMODE_POL ,Controls the polarity of the SYS_OFFMODE signal" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " CLKOUT_POL ,Controls the external output clock polarity when disabled" "Gated low,Gated high"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " CLKREQ_POL ,Controls the polarity of the SYS_CLKREQ signal" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " EXTVOL_POL ,Controls the polarity of VMODE signal" "Active low,Active high"
|
|
group.long 0x12A0++0x3
|
|
line.long 0x00 "PRM_VOLTSETUP2,Overall Setup Time Of VDD1 And VDD2 Regulators"
|
|
hexmask.long.word 0x00 0.--15. 1. " OFFMODESETUPTIME ,Number of 32kHz clock cycles for the overall setup time"
|
|
group.long 0x1358++0x3 "NEON"
|
|
line.long 0x00 "RM_RSTST_NEON,Different Reset Sources Of The NEON Domain Log"
|
|
eventfld.long 0x00 3. " COREDOMAINWKUP_RST ,CORE domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DOMAINWKUP_RST ,Power domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
textline " "
|
|
eventfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0x13C8++0x3
|
|
line.long 0x00 "PM_WKDEP_NEON,Wake-up Of The NEON Domain Enable"
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Independent,Woken-up"
|
|
group.long 0x13E0++0x3
|
|
line.long 0x00 "PM_PWSTCTRL_NEON,NEON Domain Power State Transition Control"
|
|
bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when RETENTION" "Reserved,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "Off,Retention,Reserved,On"
|
|
rgroup.long 0x13E4++0x3
|
|
line.long 0x00 "PM_PWSTST_NEON,Power State Transition Of The NEON Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,Transition"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Off,Retention,Inactive,On"
|
|
group.long 0x13E8++0x3
|
|
line.long 0x00 "PM_PREPWSTST_NEON,NEON Domain Previous Power State Status"
|
|
bitfld.long 0x00 0.--1. " LASTPOWERSTATEENTERED ,Last power state entered" "Off,Retention,Inactive,On"
|
|
group.long 0x1458++0x3 "USBHOST_PRM"
|
|
line.long 0x00 "RM_RSTST_USBHOST,Different Reset Sources Of The USB HOST Domain Log"
|
|
bitfld.long 0x00 3. " COREDOMAINWKUP_RST ,CORE domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DOMAINWKUP_RST ,Power domain wake-up reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GLOBALWARM_RST ,Global warm reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GLOBALCOLD_RST ,Global cold reset" "No reset,Reset"
|
|
group.long 0x14A0++0xB
|
|
line.long 0x00 "PM_WKEN_USBHOST,Modules Wake-up Events Control"
|
|
bitfld.long 0x00 0. " EN_USBHOST ,USB HOST Wake-up enable" "Disabled,Enabled"
|
|
line.long 0x04 "PM_MPUGRPSEL_USBHOST,Select The Group Of Modules That Wake-up The MPU"
|
|
bitfld.long 0x04 0. " GRPSEL_USBHOST ,Select the USBHOST in the MPU wake-up events" "Not attached,Attached"
|
|
line.long 0x08 "PM_IVA2GRPSEL_USBHOST,Select The Group Of Modules That Wake-up The IVA2"
|
|
bitfld.long 0x08 0. " GRPSEL_USBHOST ,Select the USBHOST in the IVA2 wake-up events" "Not attached,Attached"
|
|
group.long 0x14B0++0x3
|
|
line.long 0x00 "PM_WKST_USBHOST,Modules Wake-up Events Log"
|
|
bitfld.long 0x00 0. " ST_USBHOST ,USB HOST Wake-up status" "Not occurred,Occurred"
|
|
group.long 0x14C8++0x3
|
|
line.long 0x00 "PM_WKDEP_USBHOST,Wake-up Of The USB HOST Domain Control"
|
|
bitfld.long 0x00 4. " EN_WKUP ,WAKEUP domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EN_IVA2 ,IVA2 domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EN_MPU ,MPU domain dependency" "Independent,Woken-up"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN_CORE ,CORE domain dependency" "Independent,Woken-up"
|
|
group.long 0x14E0++0x3
|
|
line.long 0x00 "PM_PWSTCTRL_USBHOST,USB HOST Domain Power State Transition Control"
|
|
bitfld.long 0x00 16.--17. " MEMONSTATE ,Memory state when ON" "Reserved,Reserved,Reserved,On"
|
|
textline " "
|
|
bitfld.long 0x00 8. " MEMRETSTATE ,Memory state when RETENTION" "No effect,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SAVEANDRESTORE ,Save And Restore mechanism for the USB HOST module" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOGICRETSTATE ,Logic state when RETENTION" "No effect,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "Off,Retention,Reserved,On"
|
|
rgroup.long 0x14E4++0x3
|
|
line.long 0x00 "PM_PWSTST_USBHOST,Power State Transition Of The USB HOST Domain Status"
|
|
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current power state status" "Off,Retention,Inactive,On"
|
|
group.long 0x14E8++0x3
|
|
line.long 0x00 "PM_PREPWSTST_USBHOST,Status On The USBHOST Domain Previous Power State"
|
|
bitfld.long 0x00 0.--1. " LASTPOWERSTATEENTERED ,Last power state entered" "Off,Retention,Inactive,On"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "Interprocessor Communication"
|
|
base ad:0x48094000
|
|
width 22.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MAILBOX_SYSCONFIG,Various Parameters Of The L4-Core Interface Control"
|
|
bitfld.long 0x00 8. " CLOCKACTIVITY ,Clock activity during wake up mode period" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MAILBOX_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "On-going,Completed"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "MAILBOX_MESSAGE_0,The Message Register Stores The Next To Be Read Message Of The Mailbox 0"
|
|
line.long 0x04 "MAILBOX_MESSAGE_1,The Message Register Stores The Next To Be Read Message Of The Mailbox 1"
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x00 "MAILBOX_FIFOSTATUS_0,The FIFO Status Register Related To The Mailbox Internal FIFO"
|
|
bitfld.long 0x00 0. " FIFOFULLMB ,Full flag for Mailbox" "Not occurred,Occurred"
|
|
line.long 0x04 "MAILBOX_FIFOSTATUS_1,The FIFO Status Register Related To The Mailbox Internal FIFO"
|
|
bitfld.long 0x04 0. " FIFOFULLMB ,Full flag for Mailbox" "Not occurred,Occurred"
|
|
rgroup.long 0xC0++0x7
|
|
line.long 0x00 "MAILBOX_MSGSTATUS_0,Status Of The Messages In The Mailbox"
|
|
bitfld.long 0x00 0.--2. " NBOFMSGMB ,Number of Messages in Mailbox" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "MAILBOX_MSGSTATUS_1,Status Of The Messages In The Mailbox"
|
|
bitfld.long 0x04 0.--2. " NBOFMSGMB ,Number of Messages in Mailbox" "0,1,2,3,4,5,6,7"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_0,Events That May Be Responsible For The Generation Of An Interrupt Status"
|
|
eventfld.long 0x00 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u Mailbox 1" "Full,Not full"
|
|
textline " "
|
|
eventfld.long 0x00 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u Mailbox 1" "No action,New message"
|
|
textline " "
|
|
eventfld.long 0x00 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u Mailbox 0" "Full,Not full"
|
|
textline " "
|
|
eventfld.long 0x00 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u Mailbox 0" "No action,New message"
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "MAILBOX_IRQSTATUS_1,Events That May Be Responsible For The Generation Of An Interrupt Status"
|
|
eventfld.long 0x00 3. " NOTFULLSTATUSUUMB1 ,NotFull Status bit for User u Mailbox 1" "Full,Not full"
|
|
textline " "
|
|
eventfld.long 0x00 2. " NEWMSGSTATUSUUMB1 ,NewMessage Status bit for User u Mailbox 1" "No action,New message"
|
|
textline " "
|
|
eventfld.long 0x00 1. " NOTFULLSTATUSUUMB0 ,NotFull Status bit for User u Mailbox 0" "Full,Not full"
|
|
textline " "
|
|
eventfld.long 0x00 0. " NEWMSGSTATUSUUMB0 ,NewMessage Status bit for User u Mailbox 0" "No action,New message"
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "MAILBOX_IRQENABLE_0,The Interrupt Enable Register"
|
|
bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u Mailbox 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u Mailbox 0" "Disabled,Enabled"
|
|
group.long 0x10C++0x3
|
|
line.long 0x00 "MAILBOX_IRQENABLE_1,The Interrupt Enable Register"
|
|
bitfld.long 0x00 3. " NOTFULLENABLEUUMB1 ,NotFull Enable bit for User u Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NEWMSGENABLEUUMB1 ,NewMessage Enable bit for User u Mailbox 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NOTFULLENABLEUUMB0 ,NotFull Enable bit for User u Mailbox 0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NEWMSGENABLEUUMB0 ,NewMessage Enable bit for User u Mailbox 0" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.open "System Control Registers"
|
|
tree "INTERFACE"
|
|
base ad:0x48002000
|
|
width 19.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "CONTROL_REVISION,Control Module Revision Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVISION ,Revision number"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "CONTROL_SYSCONFIG,Set Various Parameters Relative To The Idle Mode Of The Control Module"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power Management" "Force-idle,Reserved,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Applied"
|
|
width 0xb
|
|
tree.end
|
|
tree "PADCONFS"
|
|
base ad:0x48002030
|
|
width 31.
|
|
group.long 0x00++0x3F
|
|
line.long 0x0 "CONTROL_PADCONF_SDRC_D0,Configuration Register For Pads sdrc_d0; sdrc_d1"
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for sdrc_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for sdrc_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d0" "Disabled,Enabled"
|
|
line.long 0x4 "CONTROL_PADCONF_SDRC_D2,Configuration Register For Pads sdrc_d2; sdrc_d3"
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for sdrc_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for sdrc_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d2" "Disabled,Enabled"
|
|
line.long 0x8 "CONTROL_PADCONF_SDRC_D4,Configuration Register For Pads sdrc_d4; sdrc_d5"
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for sdrc_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for sdrc_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d4" "Disabled,Enabled"
|
|
line.long 0xC "CONTROL_PADCONF_SDRC_D6,Configuration Register For Pads sdrc_d6; sdrc_d7"
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for sdrc_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for sdrc_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d6" "Disabled,Enabled"
|
|
line.long 0x10 "CONTROL_PADCONF_SDRC_D8,Configuration Register For Pads sdrc_d8; sdrc_d9"
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for sdrc_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for sdrc_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d8" "Disabled,Enabled"
|
|
line.long 0x14 "CONTROL_PADCONF_SDRC_D10,Configuration Register For Pads sdrc_d10; sdrc_d11"
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for sdrc_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for sdrc_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d10" "Disabled,Enabled"
|
|
line.long 0x18 "CONTROL_PADCONF_SDRC_D12,Configuration Register For Pads sdrc_d12; sdrc_d13"
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for sdrc_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for sdrc_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d12" "Disabled,Enabled"
|
|
line.long 0x1C "CONTROL_PADCONF_SDRC_D14,Configuration Register For Pads sdrc_d14; sdrc_d15"
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for sdrc_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for sdrc_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d14" "Disabled,Enabled"
|
|
line.long 0x20 "CONTROL_PADCONF_SDRC_D16,Configuration Register For Pads sdrc_d16; sdrc_d17"
|
|
bitfld.long 0x20 24. " INPUTENABLE1 ,Input enable for sdrc_d17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d17" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for sdrc_d16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d16" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d16" "Disabled,Enabled"
|
|
line.long 0x24 "CONTROL_PADCONF_SDRC_D18,Configuration Register For Pads sdrc_d18; sdrc_d19"
|
|
bitfld.long 0x24 24. " INPUTENABLE1 ,Input enable for sdrc_d19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 8. " INPUTENABLE0 ,Input enable for sdrc_d18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d18" "Disabled,Enabled"
|
|
line.long 0x28 "CONTROL_PADCONF_SDRC_D20,Configuration Register For Pads sdrc_d20; sdrc_d21"
|
|
bitfld.long 0x28 24. " INPUTENABLE1 ,Input enable for sdrc_d21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d21" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 8. " INPUTENABLE0 ,Input enable for sdrc_d20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d20" "Disabled,Enabled"
|
|
line.long 0x2C "CONTROL_PADCONF_SDRC_D22,Configuration Register For Pads sdrc_d22; sdrc_d23"
|
|
bitfld.long 0x2C 24. " INPUTENABLE1 ,Input enable for sdrc_d23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d23" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 8. " INPUTENABLE0 ,Input enable for sdrc_d22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d22" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d22" "Disabled,Enabled"
|
|
line.long 0x30 "CONTROL_PADCONF_SDRC_D24,Configuration Register For Pads sdrc_d24; sdrc_d25"
|
|
bitfld.long 0x30 24. " INPUTENABLE1 ,Input enable for sdrc_d25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d25" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 8. " INPUTENABLE0 ,Input enable for sdrc_d24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d24" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d24" "Disabled,Enabled"
|
|
line.long 0x34 "CONTROL_PADCONF_SDRC_D26,Configuration Register For Pads sdrc_d26; sdrc_d27"
|
|
bitfld.long 0x34 24. " INPUTENABLE1 ,Input enable for sdrc_d27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d27" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 8. " INPUTENABLE0 ,Input enable for sdrc_d26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d26" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d26" "Disabled,Enabled"
|
|
line.long 0x38 "CONTROL_PADCONF_SDRC_D28,Configuration Register For Pads sdrc_d28; sdrc_d29"
|
|
bitfld.long 0x38 24. " INPUTENABLE1 ,Input enable for sdrc_d29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d29" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 8. " INPUTENABLE0 ,Input enable for sdrc_d28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d28" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d28" "Disabled,Enabled"
|
|
line.long 0x3C "CONTROL_PADCONF_SDRC_D30,Configuration Register For Pads sdrc_d30; sdrc_d31"
|
|
bitfld.long 0x3C 24. " INPUTENABLE1 ,Input enable for sdrc_d31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_d31" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_d31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 8. " INPUTENABLE0 ,Input enable for sdrc_d30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_d30" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_d30" "Disabled,Enabled"
|
|
group.long 0x40++0xb
|
|
line.long 0x00 "CONTROL_PADCONF_SDRC_CLK,Configuration Register For Pads sdrc_clk; sdrc_dqs0"
|
|
bitfld.long 0x00 24. " INPUTENABLE1 ,Input enable for sdrc_dqs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_dqs0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_dqs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for sdrc_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_clk" "Disabled,Enabled"
|
|
line.long 0x04 "CONTROL_PADCONF_SDRC_DQS1,Configuration Register For Pads sdrc_dqs1; sdrc_dqs2"
|
|
bitfld.long 0x04 24. " INPUTENABLE1 ,Input enable for sdrc_dqs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_dqs2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_dqs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " INPUTENABLE0 ,Input enable for sdrc_dqs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_dqs1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_dqs1" "Disabled,Enabled"
|
|
line.long 0x08 "CONTROL_PADCONF_SDRC_DQS3,Configuration Register For Pads sdrc_dqs1; gpmc_a1"
|
|
bitfld.long 0x08 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_a1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x08 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_a1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_a1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_a1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_a1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_a1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OFFENABLE1 ,Off mode enable for gpmc_a1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " INPUTENABLE1 ,Input enable for gpmc_a1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_a1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_a1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_a1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 8. " INPUTENABLE0 ,Input enable for sdrc_dqs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_dqs3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_dqs3" "Disabled,Enabled"
|
|
group.long 0x4C++0xF
|
|
line.long 0x0 "CONTROL_PADCONF_GPMC_A2,Configuration Register For Pads gpmc_a2, gpmc_a3"
|
|
bitfld.long 0x0 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_a3" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_a3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_a3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_a3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_a3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_a3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " OFFENABLE1 ,Off mode enable for gpmc_a3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for gpmc_a3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_a3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_a3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_a3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 15. " WAKEUPEVENT0 ,Wake Up event for gpmc_a2" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 14. " WAKEUPENABLE0 ,Wake Up enable for gpmc_a2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_a2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_a2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_a2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_a2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " OFFENABLE0 ,Off mode enable for gpmc_a2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for gpmc_a2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_a2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_a2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_a2" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CONTROL_PADCONF_GPMC_A4,Configuration Register For Pads gpmc_a4, gpmc_a5"
|
|
bitfld.long 0x4 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_a5" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_a5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_a5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_a5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_a5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_a5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " OFFENABLE1 ,Off mode enable for gpmc_a5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for gpmc_a5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_a5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_a5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_a5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 15. " WAKEUPEVENT0 ,Wake Up event for gpmc_a4" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 14. " WAKEUPENABLE0 ,Wake Up enable for gpmc_a4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_a4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_a4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_a4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_a4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " OFFENABLE0 ,Off mode enable for gpmc_a4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for gpmc_a4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_a4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_a4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_a4" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CONTROL_PADCONF_GPMC_A6,Configuration Register For Pads gpmc_a6, gpmc_a7"
|
|
bitfld.long 0x8 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_a7" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_a7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_a7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_a7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_a7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_a7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 25. " OFFENABLE1 ,Off mode enable for gpmc_a7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for gpmc_a7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_a7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_a7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_a7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 15. " WAKEUPEVENT0 ,Wake Up event for gpmc_a6" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 14. " WAKEUPENABLE0 ,Wake Up enable for gpmc_a6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_a6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_a6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_a6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_a6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 9. " OFFENABLE0 ,Off mode enable for gpmc_a6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for gpmc_a6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_a6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_a6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_a6" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "CONTROL_PADCONF_GPMC_A8,Configuration Register For Pads gpmc_a8, gpmc_a9"
|
|
bitfld.long 0xC 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_a9" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_a9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_a9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_a9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_a9" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_a9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 25. " OFFENABLE1 ,Off mode enable for gpmc_a9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for gpmc_a9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_a9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_a9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_a9" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 15. " WAKEUPEVENT0 ,Wake Up event for gpmc_a8" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 14. " WAKEUPENABLE0 ,Wake Up enable for gpmc_a8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_a8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_a8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_a8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_a8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 9. " OFFENABLE0 ,Off mode enable for gpmc_a8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for gpmc_a8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_a8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_a8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_a8" "0,1,2,3,4,5,6,7"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "CONTROL_PADCONF_GPMC_A10,Configuration Register For Pads gpmc_a10; gpmc_d0"
|
|
bitfld.long 0x00 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_d0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_d0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OFFENABLE1 ,Off mode enable for gpmc_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " INPUTENABLE1 ,Input enable for gpmc_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAKEUPEVENT0 ,Wake Up event for gpmc_a$3" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 14. " WAKEUPENABLE0 ,Wake Up enable for gpmc_a$3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_a$3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_a$3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_a$3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_a$3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFFENABLE0 ,Off mode enable for gpmc_a$3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for gpmc_a$3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_a$3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_a$3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_a$3" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0xb
|
|
line.long 0x0 "CONTROL_PADCONF_GPMC_D1,Configuration Register For Pads gpmc_d1; gpmc_d2"
|
|
bitfld.long 0x0 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_d2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_d2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " OFFENABLE1 ,Off mode enable for gpmc_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for gpmc_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_d1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_d1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " OFFENABLE0 ,Off mode enable for gpmc_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for gpmc_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d1" "Disabled,Enabled"
|
|
line.long 0x4 "CONTROL_PADCONF_GPMC_D3,Configuration Register For Pads gpmc_d3; gpmc_d4"
|
|
bitfld.long 0x4 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_d4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_d4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " OFFENABLE1 ,Off mode enable for gpmc_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for gpmc_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_d3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_d3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " OFFENABLE0 ,Off mode enable for gpmc_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for gpmc_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d3" "Disabled,Enabled"
|
|
line.long 0x8 "CONTROL_PADCONF_GPMC_D5,Configuration Register For Pads gpmc_d5; gpmc_d6"
|
|
bitfld.long 0x8 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_d6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_d6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 25. " OFFENABLE1 ,Off mode enable for gpmc_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for gpmc_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_d5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_d5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 9. " OFFENABLE0 ,Off mode enable for gpmc_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for gpmc_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d5" "Disabled,Enabled"
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "CONTROL_PADCONF_GPMC_D7,Configuration Register For Pads gpmc_d7; gpmc_d8"
|
|
bitfld.long 0x00 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_d8" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_d8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_d8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OFFENABLE1 ,Off mode enable for gpmc_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " INPUTENABLE1 ,Input enable for gpmc_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_d8" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_d7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_d7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFFENABLE0 ,Off mode enable for gpmc_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for gpmc_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d7" "Disabled,Enabled"
|
|
group.long 0x70++0xb
|
|
line.long 0x0 "CONTROL_PADCONF_GPMC_D9,Configuration Register For Pads gpmc_d9, gpmc_d10"
|
|
bitfld.long 0x0 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_d10" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_d10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_d10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " OFFENABLE1 ,Off mode enable for gpmc_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for gpmc_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_d10" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_d9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_d9" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " OFFENABLE0 ,Off mode enable for gpmc_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for gpmc_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d9" "Disabled,Enabled"
|
|
line.long 0x4 "CONTROL_PADCONF_GPMC_D11,Configuration Register For Pads gpmc_d11, gpmc_d12"
|
|
bitfld.long 0x4 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_d12" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_d12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_d12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " OFFENABLE1 ,Off mode enable for gpmc_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for gpmc_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_d12" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_d11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_d11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " OFFENABLE0 ,Off mode enable for gpmc_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for gpmc_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d11" "Disabled,Enabled"
|
|
line.long 0x8 "CONTROL_PADCONF_GPMC_D13,Configuration Register For Pads gpmc_d13, gpmc_d14"
|
|
bitfld.long 0x8 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_d14" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_d14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_d14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 25. " OFFENABLE1 ,Off mode enable for gpmc_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for gpmc_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_d14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_d14" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_d13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_d13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 9. " OFFENABLE0 ,Off mode enable for gpmc_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for gpmc_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d13" "Disabled,Enabled"
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "CONTROL_PADCONF_GPMC_D15,Configuration Register For Pads gpmc_d15; gpmc_ncs0"
|
|
bitfld.long 0x00 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_ncs0" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_ncs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_ncs0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_ncs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_ncs0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_ncs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OFFENABLE1 ,Off mode enable for gpmc_ncs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " INPUTENABLE1 ,Input enable for gpmc_ncs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_ncs0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_ncs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_ncs0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_d15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_d15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFFENABLE0 ,Off mode enable for gpmc_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for gpmc_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_d15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_d15" "Disabled,Enabled"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "CONTROL_PADCONF_GPMC_NCS1,Configuration Register For Pads gpmc_ncs1; gpmc_ncs2"
|
|
bitfld.long 0x0 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_ncs2" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_ncs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_ncs2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_ncs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_ncs2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_ncs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " OFFENABLE1 ,Off mode enable for gpmc_ncs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for gpmc_ncs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_ncs2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_ncs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_ncs2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 15. " WAKEUPEVENT0 ,Wake Up event for gpmc_ncs1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 14. " WAKEUPENABLE0 ,Wake Up enable for gpmc_ncs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_ncs1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_ncs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_ncs1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_ncs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " OFFENABLE0 ,Off mode enable for gpmc_ncs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for gpmc_ncs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_ncs1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_ncs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_ncs1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CONTROL_PADCONF_GPMC_NCS3,Configuration Register For Pads gpmc_ncs3; gpmc_ncs4"
|
|
bitfld.long 0x4 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_ncs4" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_ncs4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_ncs4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_ncs4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_ncs4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_ncs4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " OFFENABLE1 ,Off mode enable for gpmc_ncs4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for gpmc_ncs4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_ncs4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_ncs4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_ncs4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 15. " WAKEUPEVENT0 ,Wake Up event for gpmc_ncs3" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 14. " WAKEUPENABLE0 ,Wake Up enable for gpmc_ncs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_ncs3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_ncs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_ncs3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_ncs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " OFFENABLE0 ,Off mode enable for gpmc_ncs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for gpmc_ncs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_ncs3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_ncs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_ncs3" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CONTROL_PADCONF_GPMC_NCS5,Configuration Register For Pads gpmc_ncs5; gpmc_ncs6"
|
|
bitfld.long 0x8 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_ncs6" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_ncs6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_ncs6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_ncs6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_ncs6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_ncs6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 25. " OFFENABLE1 ,Off mode enable for gpmc_ncs6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for gpmc_ncs6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_ncs6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_ncs6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_ncs6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 15. " WAKEUPEVENT0 ,Wake Up event for gpmc_ncs5" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 14. " WAKEUPENABLE0 ,Wake Up enable for gpmc_ncs5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_ncs5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_ncs5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_ncs5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_ncs5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 9. " OFFENABLE0 ,Off mode enable for gpmc_ncs5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for gpmc_ncs5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_ncs5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_ncs5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_ncs5" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "CONTROL_PADCONF_GPMC_NCS7,Configuration Register For Pads gpmc_ncs7; gpmc_clk"
|
|
bitfld.long 0x0C 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_clk" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0C 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_clk" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " OFFENABLE1 ,Off mode enable for gpmc_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " INPUTENABLE1 ,Input enable for gpmc_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_clk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " WAKEUPEVENT0 ,Wake Up event for gpmc_ncs7" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " WAKEUPENABLE0 ,Wake Up enable for gpmc_ncs7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_ncs7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_ncs7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_ncs7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_ncs7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " OFFENABLE0 ,Off mode enable for gpmc_ncs7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " INPUTENABLE0 ,Input enable for gpmc_ncs7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_ncs7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_ncs7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_ncs7" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90++0x1b
|
|
line.long 0x00 "CONTROL_PADCONF_GPMC_NADV_ALE,Configuration Register For Pads gpmc_nadv_ale; gpmc_noe"
|
|
bitfld.long 0x00 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_noe" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_noe" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OFFENABLE1 ,Off mode enable for gpmc_noe" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_nadv_ale" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_nadv_ale" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFFENABLE0 ,Off mode enable for gpmc_nadv_ale" "Disabled,Enabled"
|
|
line.long 0x04 "CONTROL_PADCONF_GPMC_NWE,Configuration Register For Pads gpmc_nwe; gpmc_nbe0_cle"
|
|
bitfld.long 0x04 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_nbe0_cle" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x04 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_nbe0_cle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_nbe0_cle" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_nbe0_cle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_nbe0_cle" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_nbe0_cle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " OFFENABLE1 ,Off mode enable for gpmc_nbe0_cle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " INPUTENABLE1 ,Input enable for gpmc_nbe0_cle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_nbe0_cle" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_nbe0_cle" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_nbe0_cle" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_nwe" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_nwe" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OFFENABLE0 ,Off mode enable for gpmc_nwe" "Disabled,Enabled"
|
|
line.long 0x08 "CONTROL_PADCONF_GPMC_NBE1,Configuration Register For Pads gpmc_nbe1; gpmc_nwp"
|
|
bitfld.long 0x08 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_nwp" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x08 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_nwp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_nwp" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_nwp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_nwp" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_nwp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OFFENABLE1 ,Off mode enable for gpmc_nwp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " INPUTENABLE1 ,Input enable for gpmc_nwp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_nwp" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_nwp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_nwp" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 15. " WAKEUPEVENT0 ,Wake Up event for gpmc_nbe1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x08 14. " WAKEUPENABLE0 ,Wake Up enable for gpmc_nbe1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_nbe1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_nbe1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_nbe1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_nbe1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OFFENABLE0 ,Off mode enable for gpmc_nbe1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " INPUTENABLE0 ,Input enable for gpmc_nbe1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_nbe1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_nbe1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_nbe1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "CONTROL_PADCONF_GPMC_WAIT0,Configuration Register For Pads gpmc_wait0; gpmc_wait1"
|
|
bitfld.long 0x0c 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_wait1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0c 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_wait1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_wait1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_wait1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_wait1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0c 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_wait1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " OFFENABLE1 ,Off mode enable for gpmc_wait1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 24. " INPUTENABLE1 ,Input enable for gpmc_wait1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_wait1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_wait1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_wait1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_wait0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_wait0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " OFFENABLE0 ,Off mode enable for gpmc_wait0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 8. " INPUTENABLE0 ,Input enable for gpmc_wait0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_wait0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_wait0" "Disabled,Enabled"
|
|
line.long 0x10 "CONTROL_PADCONF_GPMC_WAIT2,Configuration Register For Pads gpmc_wait2; gpmc_wait3"
|
|
bitfld.long 0x10 31. " WAKEUPEVENT1 ,Wake Up event for gpmc_wait3" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 30. " WAKEUPENABLE1 ,Wake Up enable for gpmc_wait3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for gpmc_wait3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for gpmc_wait3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " OFFOUTVALUE1 ,Off mode output value for gpmc_wait3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 26. " OFFOUTENABLE1 ,Off mode output enable for gpmc_wait3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " OFFENABLE1 ,Off mode enable for gpmc_wait3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for gpmc_wait3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for gpmc_wait3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for gpmc_wait3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for gpmc_wait3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 15. " WAKEUPEVENT0 ,Wake Up event for gpmc_wait2" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 14. " WAKEUPENABLE0 ,Wake Up enable for gpmc_wait2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for gpmc_wait2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for gpmc_wait2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " OFFOUTVALUE0 ,Off mode output value for gpmc_wait2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 10. " OFFOUTENABLE0 ,Off mode output enable for gpmc_wait2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " OFFENABLE0 ,Off mode enable for gpmc_wait2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for gpmc_wait2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for gpmc_wait2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for gpmc_wait2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for gpmc_wait2" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CONTROL_PADCONF_DSS_PCLK,Configuration Register For Pads dss_pclk; dss_hsync"
|
|
bitfld.long 0x14 31. " WAKEUPEVENT1 ,Wake Up event for dss_hsync" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 30. " WAKEUPENABLE1 ,Wake Up enable for dss_hsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_hsync" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_hsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " OFFOUTVALUE1 ,Off mode output value for dss_hsync" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 26. " OFFOUTENABLE1 ,Off mode output enable for dss_hsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " OFFENABLE1 ,Off mode enable for dss_hsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for dss_hsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_hsync" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_hsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_hsync" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 15. " WAKEUPEVENT0 ,Wake Up event for dss_pclk" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 14. " WAKEUPENABLE0 ,Wake Up enable for dss_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_pclk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " OFFOUTVALUE0 ,Off mode output value for dss_pclk" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 10. " OFFOUTENABLE0 ,Off mode output enable for dss_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " OFFENABLE0 ,Off mode enable for dss_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for dss_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_pclk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_pclk" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "CONTROL_PADCONF_DSS_VSYNC,Configuration Register For Pads dss_vsync, dss_acbias"
|
|
bitfld.long 0x18 31. " WAKEUPEVENT1 ,Wake Up event for dss_acbias" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 30. " WAKEUPENABLE1 ,Wake Up enable for dss_acbias" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_acbias" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_acbias" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 27. " OFFOUTVALUE1 ,Off mode output value for dss_acbias" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 26. " OFFOUTENABLE1 ,Off mode output enable for dss_acbias" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 25. " OFFENABLE1 ,Off mode enable for dss_acbias" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for dss_acbias" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_acbias" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_acbias" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_acbias" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 15. " WAKEUPEVENT0 ,Wake Up event for dss_vsync" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 14. " WAKEUPENABLE0 ,Wake Up enable for dss_vsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_vsync" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_vsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " OFFOUTVALUE0 ,Off mode output value for dss_vsync" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 10. " OFFOUTENABLE0 ,Off mode output enable for dss_vsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " OFFENABLE0 ,Off mode enable for dss_vsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for dss_vsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_vsync" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_vsync" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_vsync" "0,1,2,3,4,5,6,7"
|
|
group.long 0xAC++0x2F
|
|
line.long 0x0 "CONTROL_PADCONF_DSS_DATA0,Configuration Register For Pads dss_data0; dss_data1"
|
|
bitfld.long 0x0 31. " WAKEUPEVENT1 ,Wake Up event for dss_data1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " OFFOUTVALUE1 ,Off mode output value for dss_data1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " OFFENABLE1 ,Off mode enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 15. " WAKEUPEVENT0 ,Wake Up event for dss_data0" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " OFFOUTVALUE0 ,Off mode output value for dss_data0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " OFFENABLE0 ,Off mode enable for dss_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for dss_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CONTROL_PADCONF_DSS_DATA2,Configuration Register For Pads dss_data2; dss_data3"
|
|
bitfld.long 0x4 31. " WAKEUPEVENT1 ,Wake Up event for dss_data3" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 27. " OFFOUTVALUE1 ,Off mode output value for dss_data3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " OFFENABLE1 ,Off mode enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 15. " WAKEUPEVENT0 ,Wake Up event for dss_data2" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " OFFOUTVALUE0 ,Off mode output value for dss_data2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " OFFENABLE0 ,Off mode enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data2" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CONTROL_PADCONF_DSS_DATA4,Configuration Register For Pads dss_data4; dss_data5"
|
|
bitfld.long 0x8 31. " WAKEUPEVENT1 ,Wake Up event for dss_data5" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 27. " OFFOUTVALUE1 ,Off mode output value for dss_data5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 25. " OFFENABLE1 ,Off mode enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 15. " WAKEUPEVENT0 ,Wake Up event for dss_data4" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 11. " OFFOUTVALUE0 ,Off mode output value for dss_data4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 9. " OFFENABLE0 ,Off mode enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data4" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "CONTROL_PADCONF_DSS_DATA6,Configuration Register For Pads dss_data6; dss_data7"
|
|
bitfld.long 0xC 31. " WAKEUPEVENT1 ,Wake Up event for dss_data7" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 27. " OFFOUTVALUE1 ,Off mode output value for dss_data7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 25. " OFFENABLE1 ,Off mode enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 15. " WAKEUPEVENT0 ,Wake Up event for dss_data6" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 11. " OFFOUTVALUE0 ,Off mode output value for dss_data6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 9. " OFFENABLE0 ,Off mode enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data6" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "CONTROL_PADCONF_DSS_DATA8,Configuration Register For Pads dss_data8; dss_data9"
|
|
bitfld.long 0x10 31. " WAKEUPEVENT1 ,Wake Up event for dss_data9" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " OFFOUTVALUE1 ,Off mode output value for dss_data9" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " OFFENABLE1 ,Off mode enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data9" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 15. " WAKEUPEVENT0 ,Wake Up event for dss_data8" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " OFFOUTVALUE0 ,Off mode output value for dss_data8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " OFFENABLE0 ,Off mode enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data8" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CONTROL_PADCONF_DSS_DATA10,Configuration Register For Pads dss_data10; dss_data11"
|
|
bitfld.long 0x14 31. " WAKEUPEVENT1 ,Wake Up event for dss_data11" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " OFFOUTVALUE1 ,Off mode output value for dss_data11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " OFFENABLE1 ,Off mode enable for dss_data11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for dss_data11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data11" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 15. " WAKEUPEVENT0 ,Wake Up event for dss_data10" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " OFFOUTVALUE0 ,Off mode output value for dss_data10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " OFFENABLE0 ,Off mode enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data10" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "CONTROL_PADCONF_DSS_DATA12,Configuration Register For Pads dss_data12; dss_data13"
|
|
bitfld.long 0x18 31. " WAKEUPEVENT1 ,Wake Up event for dss_data13" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 27. " OFFOUTVALUE1 ,Off mode output value for dss_data13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 25. " OFFENABLE1 ,Off mode enable for dss_data13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for dss_data13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data13" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 15. " WAKEUPEVENT0 ,Wake Up event for dss_data12" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " OFFOUTVALUE0 ,Off mode output value for dss_data12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " OFFENABLE0 ,Off mode enable for dss_data12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for dss_data12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data12" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "CONTROL_PADCONF_DSS_DATA14,Configuration Register For Pads dss_data14; dss_data15"
|
|
bitfld.long 0x1C 31. " WAKEUPEVENT1 ,Wake Up event for dss_data15" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x1C 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " OFFOUTVALUE1 ,Off mode output value for dss_data15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " OFFENABLE1 ,Off mode enable for dss_data15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for dss_data15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data15" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " WAKEUPEVENT0 ,Wake Up event for dss_data14" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x1C 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " OFFOUTVALUE0 ,Off mode output value for dss_data14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " OFFENABLE0 ,Off mode enable for dss_data14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for dss_data14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data14" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "CONTROL_PADCONF_DSS_DATA16,Configuration Register For Pads dss_data16; dss_data17"
|
|
bitfld.long 0x20 31. " WAKEUPEVENT1 ,Wake Up event for dss_data17" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x20 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data17" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 27. " OFFOUTVALUE1 ,Off mode output value for dss_data17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x20 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 25. " OFFENABLE1 ,Off mode enable for dss_data17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 24. " INPUTENABLE1 ,Input enable for dss_data17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data17" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data17" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x20 15. " WAKEUPEVENT0 ,Wake Up event for dss_data16" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x20 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data16" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 11. " OFFOUTVALUE0 ,Off mode output value for dss_data16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x20 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 9. " OFFENABLE0 ,Off mode enable for dss_data16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for dss_data16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data16" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data16" "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "CONTROL_PADCONF_DSS_DATA18,Configuration Register For Pads dss_data18; dss_data19"
|
|
bitfld.long 0x24 31. " WAKEUPEVENT1 ,Wake Up event for dss_data19" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x24 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 27. " OFFOUTVALUE1 ,Off mode output value for dss_data19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 25. " OFFENABLE1 ,Off mode enable for dss_data19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 24. " INPUTENABLE1 ,Input enable for dss_data19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data19" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x24 15. " WAKEUPEVENT0 ,Wake Up event for dss_data18" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x24 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 11. " OFFOUTVALUE0 ,Off mode output value for dss_data18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 9. " OFFENABLE0 ,Off mode enable for dss_data18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 8. " INPUTENABLE0 ,Input enable for dss_data18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data18" "0,1,2,3,4,5,6,7"
|
|
line.long 0x28 "CONTROL_PADCONF_DSS_DATA20,Configuration Register For Pads dss_data20; dss_data21"
|
|
bitfld.long 0x28 31. " WAKEUPEVENT1 ,Wake Up event for dss_data21" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x28 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data21" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 27. " OFFOUTVALUE1 ,Off mode output value for dss_data21" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x28 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 25. " OFFENABLE1 ,Off mode enable for dss_data21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 24. " INPUTENABLE1 ,Input enable for dss_data21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data21" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data21" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x28 15. " WAKEUPEVENT0 ,Wake Up event for dss_data20" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x28 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 11. " OFFOUTVALUE0 ,Off mode output value for dss_data20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x28 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 9. " OFFENABLE0 ,Off mode enable for dss_data20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 8. " INPUTENABLE0 ,Input enable for dss_data20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data20" "0,1,2,3,4,5,6,7"
|
|
line.long 0x2C "CONTROL_PADCONF_DSS_DATA22,Configuration Register For Pads dss_data22; dss_data23"
|
|
bitfld.long 0x2C 31. " WAKEUPEVENT1 ,Wake Up event for dss_data23" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x2C 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data23" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 27. " OFFOUTVALUE1 ,Off mode output value for dss_data23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x2C 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 25. " OFFENABLE1 ,Off mode enable for dss_data23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 24. " INPUTENABLE1 ,Input enable for dss_data23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data23" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data23" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x2C 15. " WAKEUPEVENT0 ,Wake Up event for dss_data22" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x2C 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data22" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 11. " OFFOUTVALUE0 ,Off mode output value for dss_data22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x2C 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " OFFENABLE0 ,Off mode enable for dss_data22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 8. " INPUTENABLE0 ,Input enable for dss_data22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data22" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data22" "0,1,2,3,4,5,6,7"
|
|
group.long 0xDC++0xb
|
|
line.long 0x00 "CONTROL_PADCONF_CAM_HS,Configuration Register For Pads cam_hs; cam_vs"
|
|
bitfld.long 0x00 31. " WAKEUPEVENT1 ,Wake Up event for cam_vs" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WAKEUPENABLE1 ,Wake Up enable for cam_vs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for cam_vs" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for cam_vs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " OFFOUTVALUE1 ,Off mode output value for cam_vs" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OFFOUTENABLE1 ,Off mode output enable for cam_vs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OFFENABLE1 ,Off mode enable for cam_vs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " INPUTENABLE1 ,Input enable for cam_vs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for cam_vs" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for cam_vs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " MUXMODE1 ,Functional multiplexing selection for cam_vs" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAKEUPEVENT0 ,Wake Up event for cam_hs" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 14. " WAKEUPENABLE0 ,Wake Up enable for cam_hs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for cam_hs" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for cam_hs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFFOUTVALUE0 ,Off mode output value for cam_hs" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OFFOUTENABLE0 ,Off mode output enable for cam_hs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFFENABLE0 ,Off mode enable for cam_hs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for cam_hs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for cam_hs" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for cam_hs" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MUXMODE0 ,Functional multiplexing selection for cam_hs" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "CONTROL_PADCONF_CAM_XCLKA,Configuration Register For Pads cam_xclka; cam_pclk"
|
|
bitfld.long 0x04 31. " WAKEUPEVENT1 ,Wake Up event for cam_pclk" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x04 30. " WAKEUPENABLE1 ,Wake Up enable for cam_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for cam_pclk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for cam_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OFFOUTVALUE1 ,Off mode output value for cam_pclk" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 26. " OFFOUTENABLE1 ,Off mode output enable for cam_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " OFFENABLE1 ,Off mode enable for cam_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " INPUTENABLE1 ,Input enable for cam_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PULLTYPESELECT1 ,Pull-up/Down selection for cam_pclk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PULLUDENABLE1 ,Pull-up/Down enable for cam_pclk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " MUXMODE1 ,Functional multiplexing selection for cam_pclk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 15. " WAKEUPEVENT0 ,Wake Up event for cam_xclka" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x04 14. " WAKEUPENABLE0 ,Wake Up enable for cam_xclka" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for cam_xclka" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for cam_xclka" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OFFOUTVALUE0 ,Off mode output value for cam_xclka" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " OFFOUTENABLE0 ,Off mode output enable for cam_xclka" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OFFENABLE0 ,Off mode enable for cam_xclka" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " INPUTENABLE0 ,Input enable for cam_xclka" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PULLTYPESELECT0 ,Pull-up/Down selection for cam_xclka" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PULLUDENABLE0 ,Pull-up/Down enable for cam_xclka" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " MUXMODE0 ,Functional multiplexing selection for cam_xclka" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "CONTROL_PADCONF_CAM_FLD,Configuration Register For Pads cam_fld; cam_d0"
|
|
bitfld.long 0x08 31. " WAKEUPEVENT1 ,Wake Up event for cam_d0" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x08 30. " WAKEUPENABLE1 ,Wake Up enable for cam_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for cam_d0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for cam_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " OFFOUTVALUE1 ,Off mode output value for cam_d0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 26. " OFFOUTENABLE1 ,Off mode output enable for cam_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OFFENABLE1 ,Off mode enable for cam_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " INPUTENABLE1 ,Input enable for cam_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " PULLTYPESELECT1 ,Pull-up/Down selection for cam_d0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PULLUDENABLE1 ,Pull-up/Down enable for cam_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " MUXMODE1 ,Functional multiplexing selection for cam_d0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 15. " WAKEUPEVENT0 ,Wake Up event for cam_fld" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x08 14. " WAKEUPENABLE0 ,Wake Up enable for cam_fld" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for cam_fld" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for cam_fld" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OFFOUTVALUE0 ,Off mode output value for cam_fld" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 10. " OFFOUTENABLE0 ,Off mode output enable for cam_fld" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OFFENABLE0 ,Off mode enable for cam_fld" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " INPUTENABLE0 ,Input enable for cam_fld" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PULLTYPESELECT0 ,Pull-up/Down selection for cam_fld" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PULLUDENABLE0 ,Pull-up/Down enable for cam_fld" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " MUXMODE0 ,Functional multiplexing selection for cam_fld" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x13
|
|
line.long 0x0 "CONTROL_PADCONF_CAM_D1,Configuration Register For Pads cam_d1; cam_d2"
|
|
bitfld.long 0x0 31. " WAKEUPEVENT1 ,Wake Up event for dss_data2" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " OFFOUTVALUE1 ,Off mode output value for dss_data2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " OFFENABLE1 ,Off mode enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 15. " WAKEUPEVENT0 ,Wake Up event for dss_data1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " OFFOUTVALUE0 ,Off mode output value for dss_data1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " OFFENABLE0 ,Off mode enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CONTROL_PADCONF_CAM_D3,Configuration Register For Pads cam_d3; cam_d4"
|
|
bitfld.long 0x4 31. " WAKEUPEVENT1 ,Wake Up event for dss_data4" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 27. " OFFOUTVALUE1 ,Off mode output value for dss_data4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " OFFENABLE1 ,Off mode enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 15. " WAKEUPEVENT0 ,Wake Up event for dss_data3" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " OFFOUTVALUE0 ,Off mode output value for dss_data3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " OFFENABLE0 ,Off mode enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data3" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CONTROL_PADCONF_CAM_D5,Configuration Register For Pads cam_d5; cam_d6"
|
|
bitfld.long 0x8 31. " WAKEUPEVENT1 ,Wake Up event for dss_data6" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 27. " OFFOUTVALUE1 ,Off mode output value for dss_data6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 25. " OFFENABLE1 ,Off mode enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 15. " WAKEUPEVENT0 ,Wake Up event for dss_data5" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 11. " OFFOUTVALUE0 ,Off mode output value for dss_data5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 9. " OFFENABLE0 ,Off mode enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data5" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "CONTROL_PADCONF_CAM_D7,Configuration Register For Pads cam_d7; cam_d8"
|
|
bitfld.long 0xC 31. " WAKEUPEVENT1 ,Wake Up event for dss_data8" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 27. " OFFOUTVALUE1 ,Off mode output value for dss_data8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 25. " OFFENABLE1 ,Off mode enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data8" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 15. " WAKEUPEVENT0 ,Wake Up event for dss_data7" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 11. " OFFOUTVALUE0 ,Off mode output value for dss_data7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 9. " OFFENABLE0 ,Off mode enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data7" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "CONTROL_PADCONF_CAM_D9,Configuration Register For Pads cam_d9; cam_d10"
|
|
bitfld.long 0x10 31. " WAKEUPEVENT1 ,Wake Up event for dss_data10" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 30. " WAKEUPENABLE1 ,Wake Up enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for dss_data10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " OFFOUTVALUE1 ,Off mode output value for dss_data10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 26. " OFFOUTENABLE1 ,Off mode output enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " OFFENABLE1 ,Off mode enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for dss_data10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for dss_data10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for dss_data10" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 15. " WAKEUPEVENT0 ,Wake Up event for dss_data9" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 14. " WAKEUPENABLE0 ,Wake Up enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for dss_data9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " OFFOUTVALUE0 ,Off mode output value for dss_data9" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 10. " OFFOUTENABLE0 ,Off mode output enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " OFFENABLE0 ,Off mode enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for dss_data9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for dss_data9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for dss_data9" "0,1,2,3,4,5,6,7"
|
|
group.long 0xFC++0x1b
|
|
line.long 0x00 "CONTROL_PADCONF_CAM_D11,Configuration Register For Pads cam_d11; cam_xclkb"
|
|
bitfld.long 0x00 31. " WAKEUPEVENT1 ,Wake Up event for cam_xclkb" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WAKEUPENABLE1 ,Wake Up enable for cam_xclkb" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for cam_xclkb" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for cam_xclkb" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " OFFOUTVALUE1 ,Off mode output value for cam_xclkb" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OFFOUTENABLE1 ,Off mode output enable for cam_xclkb" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OFFENABLE1 ,Off mode enable for cam_xclkb" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " INPUTENABLE1 ,Input enable for cam_xclkb" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for cam_xclkb" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for cam_xclkb" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " MUXMODE1 ,Functional multiplexing selection for cam_xclkb" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAKEUPEVENT0 ,Wake Up event for cam_d11" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for cam_d11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for cam_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFFOUTVALUE0 ,Off mode output value for cam_d11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OFFOUTENABLE0 ,Off mode output enable for cam_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFFENABLE0 ,Off mode enable for cam_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for cam_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for cam_d11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for cam_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MUXMODE0 ,Functional multiplexing selection for cam_d11" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "CONTROL_PADCONF_CAM_WEN,Configuration Register For Pads cam_wen; cam_strobe"
|
|
bitfld.long 0x04 31. " WAKEUPEVENT1 ,Wake Up event for cam_strobe" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x04 30. " WAKEUPENABLE1 ,Wake Up enable for cam_strobe" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for cam_strobe" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OFFOUTVALUE1 ,Off mode output value for cam_strobe" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 26. " OFFOUTENABLE1 ,Off mode output enable for cam_strobe" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " OFFENABLE1 ,Off mode enable for cam_strobe" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " INPUTENABLE1 ,Input enable for cam_strobe" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PULLTYPESELECT1 ,Pull-up/Down selection for cam_strobe" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PULLUDENABLE1 ,Pull-up/Down enable for cam_strobe" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " MUXMODE1 ,Functional multiplexing selection for cam_strobe" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 15. " WAKEUPEVENT0 ,Wake Up event for cam_wen" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x04 14. " WAKEUPENABLE0 ,Wake Up enable for cam_wen" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for cam_wen" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for cam_wen" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OFFOUTVALUE0 ,Off mode output value for cam_wen" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " OFFOUTENABLE0 ,Off mode output enable for cam_wen" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OFFENABLE0 ,Off mode enable for cam_wen" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " INPUTENABLE0 ,Input enable for cam_wen" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PULLTYPESELECT0 ,Pull-up/Down selection for cam_wen" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PULLUDENABLE0 ,Pull-up/Down enable for cam_wen" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " MUXMODE0 ,Functional multiplexing selection for cam_wen" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "CONTROL_PADCONF_CSI2_DX0,Configuration Register For Pads csi2_dx0; csi2_dy0"
|
|
bitfld.long 0x08 31. " WAKEUPEVENT1 ,Wake Up event for csi2_dy0" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x08 30. " WAKEUPENABLE1 ,Wake Up enable for csi2_dy0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for csi2_dy0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for csi2_dy0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " OFFOUTVALUE1 ,Off mode output value for csi2_dy0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 26. " OFFOUTENABLE1 ,Off mode output enable for csi2_dy0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OFFENABLE1 ,Off mode enable for csi2_dy0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " INPUTENABLE1 ,Input enable for csi2_dy0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " PULLTYPESELECT1 ,Pull-up/Down selection for csi2_dy0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PULLUDENABLE1 ,Pull-up/Down enable for csi2_dy0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " MUXMODE1 ,Functional multiplexing selection for csi2_dy0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 15. " WAKEUPEVENT0 ,Wake Up event for csi2_dx0" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x08 14. " WAKEUPENABLE0 ,Wake Up enable for csi2_dx0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for csi2_dx0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for csi2_dx0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OFFOUTVALUE0 ,Off mode output value for csi2_dx0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 10. " OFFOUTENABLE0 ,Off mode output enable for csi2_dx0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OFFENABLE0 ,Off mode enable for csi2_dx0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " INPUTENABLE0 ,Input enable for csi2_dx0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PULLTYPESELECT0 ,Pull-up/Down selection for csi2_dx0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PULLUDENABLE0 ,Pull-up/Down enable for csi2_dx0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " MUXMODE0 ,Functional multiplexing selection for csi2_dx0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "CONTROL_PADCONF_CSI2_DX1,Configuration Register For Pads csi2_dx1; csi2_dy1"
|
|
bitfld.long 0x0C 31. " WAKEUPEVENT1 ,Wake Up event for csi2_dy1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0C 30. " WAKEUPENABLE1 ,Wake Up enable for csi2_dy1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for csi2_dy1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for csi2_dy1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " OFFOUTVALUE1 ,Off mode output value for csi2_dy1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " OFFOUTENABLE1 ,Off mode output enable for csi2_dy1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " OFFENABLE1 ,Off mode enable for csi2_dy1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " INPUTENABLE1 ,Input enable for csi2_dy1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for csi2_dy1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " PULLUDENABLE1 ,Pull-up/Down enable for csi2_dy1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--18. " MUXMODE1 ,Functional multiplexing selection for csi2_dy1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " WAKEUPEVENT0 ,Wake Up event for csi2_dx1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " WAKEUPENABLE0 ,Wake Up enable for csi2_dx1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for csi2_dx1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for csi2_dx1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " OFFOUTVALUE0 ,Off mode output value for csi2_dx1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " OFFOUTENABLE0 ,Off mode output enable for csi2_dx1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " OFFENABLE0 ,Off mode enable for csi2_dx1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " INPUTENABLE0 ,Input enable for csi2_dx1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for csi2_dx1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " PULLUDENABLE0 ,Pull-up/Down enable for csi2_dx1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " MUXMODE0 ,Functional multiplexing selection for csi2_dx1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "CONTROL_PADCONF_MCBSP2_FSX,Configuration Register For Pads pads mcbsp2_fsx; mcbsp2_clkx"
|
|
bitfld.long 0x10 31. " WAKEUPEVENT1 ,Wake Up event for mcbsp2_clkx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 30. " WAKEUPENABLE1 ,Wake Up enable for mcbsp2_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcbsp2_clkx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcbsp2_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " OFFOUTVALUE1 ,Off mode output value for mcbsp2_clkx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 26. " OFFOUTENABLE1 ,Off mode output enable for mcbsp2_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " OFFENABLE1 ,Off mode enable for mcbsp2_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for mcbsp2_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp2_clkx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp2_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp2_clkx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 15. " WAKEUPEVENT0 ,Wake Up event for mcbsp2_fsx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 14. " WAKEUPENABLE0 ,Wake Up enable for mcbsp2_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcbsp2_fsx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcbsp2_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " OFFOUTVALUE0 ,Off mode output value for mcbsp2_fsx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 9. " OFFENABLE0 ,Off mode enable for mcbsp2_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for mcbsp2_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp2_fsx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp2_fsx" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CONTROL_PADCONF_MCBSP2_DR,Configuration Register For Pads pads mcbsp2_dr; mcbsp2_dx"
|
|
bitfld.long 0x14 31. " WAKEUPEVENT1 ,Wake Up event for mcbsp2_dx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 30. " WAKEUPENABLE1 ,Wake Up enable for mcbsp2_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcbsp2_dx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcbsp2_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " OFFOUTVALUE1 ,Off mode output value for mcbsp2_dx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 26. " OFFOUTENABLE1 ,Off mode output enable for mcbsp2_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " OFFENABLE1 ,Off mode enable for mcbsp2_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for mcbsp2_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp2_dx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp2_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp2_dx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 15. " WAKEUPEVENT0 ,Wake Up event for mcbsp2_dr" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 14. " WAKEUPENABLE0 ,Wake Up enable for mcbsp2_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcbsp2_dr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcbsp2_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " OFFOUTVALUE0 ,Off mode output value for mcbsp2_dr" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 10. " OFFOUTENABLE0 ,Off mode output enable for mcbsp2_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " OFFENABLE0 ,Off mode enable for mcbsp2_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for mcbsp2_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp2_dr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp2_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp2_dr" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "CONTROL_PADCONF_MMC1_CLK,Configuration Register For Pads pads mmc1_clk; mmc1_cmd"
|
|
bitfld.long 0x18 31. " WAKEUPEVENT1 ,Wake Up event for mmc1_cmd" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 30. " WAKEUPENABLE1 ,Wake Up enable for mmc1_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mmc1_cmd" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mmc1_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 27. " OFFOUTVALUE1 ,Off mode output value for mmc1_cmd" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 26. " OFFOUTENABLE1 ,Off mode output enable for mmc1_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 25. " OFFENABLE1 ,Off mode enable for mmc1_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for mmc1_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc1_cmd" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc1_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc1_cmd" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 15. " WAKEUPEVENT0 ,Wake Up event for mmc1_clk" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 14. " WAKEUPENABLE0 ,Wake Up enable for mmc1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mmc1_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mmc1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " OFFOUTVALUE0 ,Off mode output value for mmc1_clk" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 10. " OFFOUTENABLE0 ,Off mode output enable for mmc1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " OFFENABLE0 ,Off mode enable for mmc1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for mmc1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc1_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc1_clk" "0,1,2,3,4,5,6,7"
|
|
group.long 0x118++0xF
|
|
line.long 0x0 "CONTROL_PADCONF_MMC1_DAT0,Configuration Register For Pads mmc1_dat0; mmc1_dat1"
|
|
bitfld.long 0x0 31. " WAKEUPEVENT1 ,Wake Up event for mmc1_dat1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 30. " WAKEUPENABLE1 ,Wake Up enable for mmc1_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mmc1_dat1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mmc1_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " OFFOUTVALUE1 ,Off mode output value for mmc1_dat1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " OFFOUTENABLE1 ,Off mode output enable for mmc1_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " OFFENABLE1 ,Off mode enable for mmc1_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for mmc1_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc1_dat1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc1_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc1_dat1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 15. " WAKEUPEVENT0 ,Wake Up event for mmc1_dat0" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 14. " WAKEUPENABLE0 ,Wake Up enable for mmc1_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mmc1_dat0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mmc1_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " OFFOUTVALUE0 ,Off mode output value for mmc1_dat0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " OFFOUTENABLE0 ,Off mode output enable for mmc1_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " OFFENABLE0 ,Off mode enable for mmc1_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for mmc1_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc1_dat0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc1_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc1_dat0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CONTROL_PADCONF_MMC1_DAT2,Configuration Register For Pads mmc1_dat2; mmc1_dat3"
|
|
bitfld.long 0x4 31. " WAKEUPEVENT1 ,Wake Up event for mmc1_dat3" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 30. " WAKEUPENABLE1 ,Wake Up enable for mmc1_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mmc1_dat3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mmc1_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 27. " OFFOUTVALUE1 ,Off mode output value for mmc1_dat3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 26. " OFFOUTENABLE1 ,Off mode output enable for mmc1_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " OFFENABLE1 ,Off mode enable for mmc1_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for mmc1_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc1_dat3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc1_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc1_dat3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 15. " WAKEUPEVENT0 ,Wake Up event for mmc1_dat2" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 14. " WAKEUPENABLE0 ,Wake Up enable for mmc1_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mmc1_dat2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mmc1_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " OFFOUTVALUE0 ,Off mode output value for mmc1_dat2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " OFFOUTENABLE0 ,Off mode output enable for mmc1_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " OFFENABLE0 ,Off mode enable for mmc1_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for mmc1_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc1_dat2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc1_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc1_dat2" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CONTROL_PADCONF_MMC1_DAT4,Configuration Register For Pads mmc1_dat4; mmc1_dat5"
|
|
bitfld.long 0x8 31. " WAKEUPEVENT1 ,Wake Up event for mmc1_dat5" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 30. " WAKEUPENABLE1 ,Wake Up enable for mmc1_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mmc1_dat5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mmc1_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 27. " OFFOUTVALUE1 ,Off mode output value for mmc1_dat5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 26. " OFFOUTENABLE1 ,Off mode output enable for mmc1_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 25. " OFFENABLE1 ,Off mode enable for mmc1_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for mmc1_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc1_dat5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc1_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc1_dat5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 15. " WAKEUPEVENT0 ,Wake Up event for mmc1_dat4" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 14. " WAKEUPENABLE0 ,Wake Up enable for mmc1_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mmc1_dat4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mmc1_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 11. " OFFOUTVALUE0 ,Off mode output value for mmc1_dat4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 10. " OFFOUTENABLE0 ,Off mode output enable for mmc1_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 9. " OFFENABLE0 ,Off mode enable for mmc1_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for mmc1_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc1_dat4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc1_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc1_dat4" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "CONTROL_PADCONF_MMC1_DAT6,Configuration Register For Pads mmc1_dat6; mmc1_dat7"
|
|
bitfld.long 0xC 31. " WAKEUPEVENT1 ,Wake Up event for mmc1_dat7" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 30. " WAKEUPENABLE1 ,Wake Up enable for mmc1_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mmc1_dat7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mmc1_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 27. " OFFOUTVALUE1 ,Off mode output value for mmc1_dat7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 26. " OFFOUTENABLE1 ,Off mode output enable for mmc1_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 25. " OFFENABLE1 ,Off mode enable for mmc1_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for mmc1_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc1_dat7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc1_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc1_dat7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 15. " WAKEUPEVENT0 ,Wake Up event for mmc1_dat6" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 14. " WAKEUPENABLE0 ,Wake Up enable for mmc1_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mmc1_dat6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mmc1_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 11. " OFFOUTVALUE0 ,Off mode output value for mmc1_dat6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 10. " OFFOUTENABLE0 ,Off mode output enable for mmc1_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 9. " OFFENABLE0 ,Off mode enable for mmc1_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for mmc1_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc1_dat6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc1_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc1_dat6" "0,1,2,3,4,5,6,7"
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "CONTROL_PADCONF_MMC2_CLK,Configuration Register For Pads mmc2_clk; mmc2_cmd"
|
|
bitfld.long 0x00 31. " WAKEUPEVENT1 ,Wake Up event for mmc2_cmd" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WAKEUPENABLE1 ,Wake Up enable for mmc2_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mmc2_cmd" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mmc2_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " OFFOUTVALUE1 ,Off mode output value for mmc2_cmd" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OFFOUTENABLE1 ,Off mode output enable for mmc2_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OFFENABLE1 ,Off mode enable for mmc2_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " INPUTENABLE1 ,Input enable for mmc2_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc2_cmd" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc2_cmd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc2_cmd" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAKEUPEVENT0 ,Wake Up event for mmc2_clk" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 14. " WAKEUPENABLE0 ,Wake Up enable for mmc2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mmc2_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mmc2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFFOUTVALUE0 ,Off mode output value for mmc2_clk" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OFFOUTENABLE0 ,Off mode output enable for mmc2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFFENABLE0 ,Off mode enable for mmc2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for mmc2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc2_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc2_clk" "0,1,2,3,4,5,6,7"
|
|
group.long 0x12C++0xF
|
|
line.long 0x0 "CONTROL_PADCONF_MMC2_DAT0,Configuration Register For Pads mmc2_dat0; mmc2_dat1"
|
|
bitfld.long 0x0 31. " WAKEUPEVENT1 ,Wake Up event for mmc2_dat1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 30. " WAKEUPENABLE1 ,Wake Up enable for mmc2_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mmc2_dat1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mmc2_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " OFFOUTVALUE1 ,Off mode output value for mmc2_dat1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " OFFOUTENABLE1 ,Off mode output enable for mmc2_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " OFFENABLE1 ,Off mode enable for mmc2_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for mmc2_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc2_dat1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc2_dat1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc2_dat1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 15. " WAKEUPEVENT0 ,Wake Up event for mmc2_dat0" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 14. " WAKEUPENABLE0 ,Wake Up enable for mmc2_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mmc2_dat0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mmc2_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " OFFOUTVALUE0 ,Off mode output value for mmc2_dat0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " OFFOUTENABLE0 ,Off mode output enable for mmc2_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " OFFENABLE0 ,Off mode enable for mmc2_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for mmc2_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc2_dat0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc2_dat0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc2_dat0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CONTROL_PADCONF_MMC2_DAT2,Configuration Register For Pads mmc2_dat2; mmc2_dat3"
|
|
bitfld.long 0x4 31. " WAKEUPEVENT1 ,Wake Up event for mmc2_dat3" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 30. " WAKEUPENABLE1 ,Wake Up enable for mmc2_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mmc2_dat3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mmc2_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 27. " OFFOUTVALUE1 ,Off mode output value for mmc2_dat3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 26. " OFFOUTENABLE1 ,Off mode output enable for mmc2_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " OFFENABLE1 ,Off mode enable for mmc2_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for mmc2_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc2_dat3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc2_dat3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc2_dat3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 15. " WAKEUPEVENT0 ,Wake Up event for mmc2_dat2" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 14. " WAKEUPENABLE0 ,Wake Up enable for mmc2_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mmc2_dat2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mmc2_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " OFFOUTVALUE0 ,Off mode output value for mmc2_dat2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " OFFOUTENABLE0 ,Off mode output enable for mmc2_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " OFFENABLE0 ,Off mode enable for mmc2_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for mmc2_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc2_dat2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc2_dat2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc2_dat2" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CONTROL_PADCONF_MMC2_DAT4,Configuration Register For Pads mmc2_dat4; mmc2_dat5"
|
|
bitfld.long 0x8 31. " WAKEUPEVENT1 ,Wake Up event for mmc2_dat5" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 30. " WAKEUPENABLE1 ,Wake Up enable for mmc2_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mmc2_dat5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mmc2_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 27. " OFFOUTVALUE1 ,Off mode output value for mmc2_dat5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 26. " OFFOUTENABLE1 ,Off mode output enable for mmc2_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 25. " OFFENABLE1 ,Off mode enable for mmc2_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for mmc2_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc2_dat5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc2_dat5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc2_dat5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 15. " WAKEUPEVENT0 ,Wake Up event for mmc2_dat4" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 14. " WAKEUPENABLE0 ,Wake Up enable for mmc2_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mmc2_dat4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mmc2_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 11. " OFFOUTVALUE0 ,Off mode output value for mmc2_dat4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 10. " OFFOUTENABLE0 ,Off mode output enable for mmc2_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 9. " OFFENABLE0 ,Off mode enable for mmc2_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for mmc2_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc2_dat4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc2_dat4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc2_dat4" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "CONTROL_PADCONF_MMC2_DAT6,Configuration Register For Pads mmc2_dat6; mmc2_dat7"
|
|
bitfld.long 0xC 31. " WAKEUPEVENT1 ,Wake Up event for mmc2_dat7" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 30. " WAKEUPENABLE1 ,Wake Up enable for mmc2_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mmc2_dat7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mmc2_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 27. " OFFOUTVALUE1 ,Off mode output value for mmc2_dat7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 26. " OFFOUTENABLE1 ,Off mode output enable for mmc2_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 25. " OFFENABLE1 ,Off mode enable for mmc2_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for mmc2_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mmc2_dat7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for mmc2_dat7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for mmc2_dat7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 15. " WAKEUPEVENT0 ,Wake Up event for mmc2_dat6" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 14. " WAKEUPENABLE0 ,Wake Up enable for mmc2_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mmc2_dat6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mmc2_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 11. " OFFOUTVALUE0 ,Off mode output value for mmc2_dat6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 10. " OFFOUTENABLE0 ,Off mode output enable for mmc2_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 9. " OFFENABLE0 ,Off mode enable for mmc2_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for mmc2_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mmc2_dat6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for mmc2_dat6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for mmc2_dat6" "0,1,2,3,4,5,6,7"
|
|
group.long 0x13C++0x3f
|
|
line.long 0x00 "CONTROL_PADCONF_MCBSP3_DX,Configuration Register For Pads mcbsp3_dx; mcbsp3_dr"
|
|
bitfld.long 0x00 31. " WAKEUPEVENT1 ,Wake Up event for mcbsp3_dr" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WAKEUPENABLE1 ,Wake Up enable for mcbsp3_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcbsp3_dr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcbsp3_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " OFFOUTVALUE1 ,Off mode output value for mcbsp3_dr" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OFFOUTENABLE1 ,Off mode output enable for mcbsp3_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OFFENABLE1 ,Off mode enable for mcbsp3_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " INPUTENABLE1 ,Input enable for mcbsp3_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp3_dr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp3_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp3_dr" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAKEUPEVENT0 ,Wake Up event for mcbsp3_dx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 14. " WAKEUPENABLE0 ,Wake Up enable for mcbsp3_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcbsp3_dx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcbsp3_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFFOUTVALUE0 ,Off mode output value for mcbsp3_dx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OFFOUTENABLE0 ,Off mode output enable for mcbsp3_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFFENABLE0 ,Off mode enable for mcbsp3_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for mcbsp3_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp3_dx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp3_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp3_dx" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "CONTROL_PADCONF_MCBSP3_CLKX,Configuration Register For Pads mcbsp3_clkx; mcbsp3_fsx"
|
|
bitfld.long 0x04 31. " WAKEUPEVENT1 ,Wake Up event for mcbsp3_fsx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x04 30. " WAKEUPENABLE1 ,Wake Up enable for mcbsp3_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcbsp3_fsx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcbsp3_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OFFOUTVALUE1 ,Off mode output value for mcbsp3_fsx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 26. " OFFOUTENABLE1 ,Off mode output enable for mcbsp3_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " OFFENABLE1 ,Off mode enable for mcbsp3_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " INPUTENABLE1 ,Input enable for mcbsp3_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp3_fsx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp3_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp3_fsx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 15. " WAKEUPEVENT0 ,Wake Up event for mcbsp3_clkx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x04 14. " WAKEUPENABLE0 ,Wake Up enable for mcbsp3_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcbsp3_clkx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcbsp3_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OFFOUTVALUE0 ,Off mode output value for mcbsp3_clkx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " OFFOUTENABLE0 ,Off mode output enable for mcbsp3_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OFFENABLE0 ,Off mode enable for mcbsp3_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " INPUTENABLE0 ,Input enable for mcbsp3_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp3_clkx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp3_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp3_clkx" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "CONTROL_PADCONF_UART2_CTS,Configuration Register For Pads uart2_cts; uart2_rts"
|
|
bitfld.long 0x08 31. " WAKEUPEVENT1 ,Wake Up event for uart2_rts" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x08 30. " WAKEUPENABLE1 ,Wake Up enable for uart2_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for uart2_rts" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for uart2_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " OFFOUTVALUE1 ,Off mode output value for uart2_rts" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 26. " OFFOUTENABLE1 ,Off mode output enable for uart2_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OFFENABLE1 ,Off mode enable for uart2_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " INPUTENABLE1 ,Input enable for uart2_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " PULLTYPESELECT1 ,Pull-up/Down selection for uart2_rts" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PULLUDENABLE1 ,Pull-up/Down enable for uart2_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " MUXMODE1 ,Functional multiplexing selection for uart2_rts" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 15. " WAKEUPEVENT0 ,Wake Up event for uart2_cts" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x08 14. " WAKEUPENABLE0 ,Wake Up enable for uart2_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for uart2_cts" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for uart2_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OFFOUTVALUE0 ,Off mode output value for uart2_cts" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 10. " OFFOUTENABLE0 ,Off mode output enable for uart2_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OFFENABLE0 ,Off mode enable for uart2_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " INPUTENABLE0 ,Input enable for uart2_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PULLTYPESELECT0 ,Pull-up/Down selection for uart2_cts" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PULLUDENABLE0 ,Pull-up/Down enable for uart2_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " MUXMODE0 ,Functional multiplexing selection for uart2_cts" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "CONTROL_PADCONF_UART2_TX,Configuration Register For Pads uart2_tx; uart2_rx"
|
|
bitfld.long 0x0C 31. " WAKEUPEVENT1 ,Wake Up event for uart2_rx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0C 30. " WAKEUPENABLE1 ,Wake Up enable for uart2_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for uart2_rx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for uart2_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " OFFOUTVALUE1 ,Off mode output value for uart2_rx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " OFFOUTENABLE1 ,Off mode output enable for uart2_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " OFFENABLE1 ,Off mode enable for uart2_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " INPUTENABLE1 ,Input enable for uart2_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for uart2_rx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " PULLUDENABLE1 ,Pull-up/Down enable for uart2_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--18. " MUXMODE1 ,Functional multiplexing selection for uart2_rx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " WAKEUPEVENT0 ,Wake Up event for uart2_tx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " WAKEUPENABLE0 ,Wake Up enable for uart2_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for uart2_tx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for uart2_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " OFFOUTVALUE0 ,Off mode output value for uart2_tx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " OFFOUTENABLE0 ,Off mode output enable for uart2_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " OFFENABLE0 ,Off mode enable for uart2_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " INPUTENABLE0 ,Input enable for uart2_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for uart2_tx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " PULLUDENABLE0 ,Pull-up/Down enable for uart2_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " MUXMODE0 ,Functional multiplexing selection for uart2_tx" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "CONTROL_PADCONF_UART1_TX,Configuration Register For Pads uart1_tx; uart1_rts"
|
|
bitfld.long 0x10 31. " WAKEUPEVENT1 ,Wake Up event for uart1_rts" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 30. " WAKEUPENABLE1 ,Wake Up enable for uart1_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for uart1_rts" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for uart1_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " OFFOUTVALUE1 ,Off mode output value for uart1_rts" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 26. " OFFOUTENABLE1 ,Off mode output enable for uart1_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " OFFENABLE1 ,Off mode enable for uart1_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for uart1_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for uart1_rts" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for uart1_rts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for uart1_rts" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 15. " WAKEUPEVENT0 ,Wake Up event for uart1_tx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 14. " WAKEUPENABLE0 ,Wake Up enable for uart1_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for uart1_tx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for uart1_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " OFFOUTVALUE0 ,Off mode output value for uart1_tx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 10. " OFFOUTENABLE0 ,Off mode output enable for uart1_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " OFFENABLE0 ,Off mode enable for uart1_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for uart1_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for uart1_tx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for uart1_tx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for uart1_tx" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CONTROL_PADCONF_UART1_CTS,Configuration Register For Pads uart1_cts; uart1_rx"
|
|
bitfld.long 0x14 31. " WAKEUPEVENT1 ,Wake Up event for uart1_rx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 30. " WAKEUPENABLE1 ,Wake Up enable for uart1_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for uart1_rx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for uart1_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " OFFOUTVALUE1 ,Off mode output value for uart1_rx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 26. " OFFOUTENABLE1 ,Off mode output enable for uart1_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " OFFENABLE1 ,Off mode enable for uart1_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for uart1_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for uart1_rx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for uart1_rx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for uart1_rx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 15. " WAKEUPEVENT0 ,Wake Up event for uart1_cts" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 14. " WAKEUPENABLE0 ,Wake Up enable for uart1_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for uart1_cts" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for uart1_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " OFFOUTVALUE0 ,Off mode output value for uart1_cts" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 10. " OFFOUTENABLE0 ,Off mode output enable for uart1_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " OFFENABLE0 ,Off mode enable for uart1_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for uart1_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for uart1_cts" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for uart1_cts" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for uart1_cts" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "CONTROL_PADCONF_MCBSP4_CLKX,Configuration Register For Pads mcbsp4_clkx; mcbsp4_dr"
|
|
bitfld.long 0x18 31. " WAKEUPEVENT1 ,Wake Up event for mcbsp4_dr" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 30. " WAKEUPENABLE1 ,Wake Up enable for mcbsp4_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcbsp4_dr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcbsp4_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 27. " OFFOUTVALUE1 ,Off mode output value for mcbsp4_dr" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 26. " OFFOUTENABLE1 ,Off mode output enable for mcbsp4_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 25. " OFFENABLE1 ,Off mode enable for mcbsp4_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for mcbsp4_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp4_dr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp4_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp4_dr" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 15. " WAKEUPEVENT0 ,Wake Up event for mcbsp4_clkx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 14. " WAKEUPENABLE0 ,Wake Up enable for mcbsp4_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcbsp4_clkx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcbsp4_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " OFFOUTVALUE0 ,Off mode output value for mcbsp4_clkx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 10. " OFFOUTENABLE0 ,Off mode output enable for mcbsp4_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " OFFENABLE0 ,Off mode enable for mcbsp4_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for mcbsp4_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp4_clkx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp4_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp4_clkx" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "CONTROL_PADCONF_MCBSP4_DX,Configuration Register For Pads mcbsp4_dx; mcbsp4_fsx"
|
|
bitfld.long 0x1C 31. " WAKEUPEVENT1 ,Wake Up event for mcbsp4_fsx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x1C 30. " WAKEUPENABLE1 ,Wake Up enable for mcbsp4_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcbsp4_fsx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcbsp4_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " OFFOUTVALUE1 ,Off mode output value for mcbsp4_fsx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 26. " OFFOUTENABLE1 ,Off mode output enable for mcbsp4_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " OFFENABLE1 ,Off mode enable for mcbsp4_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for mcbsp4_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp4_fsx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp4_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp4_fsx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " WAKEUPEVENT0 ,Wake Up event for mcbsp4_dx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x1C 14. " WAKEUPENABLE0 ,Wake Up enable for mcbsp4_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcbsp4_dx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcbsp4_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " OFFOUTVALUE0 ,Off mode output value for mcbsp4_dx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " OFFOUTENABLE0 ,Off mode output enable for mcbsp4_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " OFFENABLE0 ,Off mode enable for mcbsp4_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for mcbsp4_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp4_dx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp4_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp4_dx" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "CONTROL_PADCONF_MCBSP1_CLKR,Configuration Register For Pads mcbsp1_clkr; mcbsp1_fsr"
|
|
bitfld.long 0x20 31. " WAKEUPEVENT1 ,Wake Up event for mcbsp1_fsr" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x20 30. " WAKEUPENABLE1 ,Wake Up enable for mcbsp1_fsr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcbsp1_fsr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcbsp1_fsr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 27. " OFFOUTVALUE1 ,Off mode output value for mcbsp1_fsr" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x20 26. " OFFOUTENABLE1 ,Off mode output enable for mcbsp1_fsr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 25. " OFFENABLE1 ,Off mode enable for mcbsp1_fsr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 24. " INPUTENABLE1 ,Input enable for mcbsp1_fsr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp1_fsr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp1_fsr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp1_fsr" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x20 15. " WAKEUPEVENT0 ,Wake Up event for mcbsp1_clkr" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x20 14. " WAKEUPENABLE0 ,Wake Up enable for mcbsp1_clkr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcbsp1_clkr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcbsp1_clkr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 11. " OFFOUTVALUE0 ,Off mode output value for mcbsp1_clkr" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x20 10. " OFFOUTENABLE0 ,Off mode output enable for mcbsp1_clkr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 9. " OFFENABLE0 ,Off mode enable for mcbsp1_clkr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for mcbsp1_clkr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp1_clkr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp1_clkr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp1_clkr" "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "CONTROL_PADCONF_MCBSP1_DX,Configuration Register For Pads mcbsp1_dx; mcbsp1_dr"
|
|
bitfld.long 0x24 31. " WAKEUPEVENT1 ,Wake Up event for mcbsp1_dr" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x24 30. " WAKEUPENABLE1 ,Wake Up enable for mcbsp1_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcbsp1_dr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcbsp1_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 27. " OFFOUTVALUE1 ,Off mode output value for mcbsp1_dr" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 26. " OFFOUTENABLE1 ,Off mode output enable for mcbsp1_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 25. " OFFENABLE1 ,Off mode enable for mcbsp1_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 24. " INPUTENABLE1 ,Input enable for mcbsp1_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp1_dr" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp1_dr" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp1_dr" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x24 15. " WAKEUPEVENT0 ,Wake Up event for mcbsp1_dx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x24 14. " WAKEUPENABLE0 ,Wake Up enable for mcbsp1_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcbsp1_dx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcbsp1_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 11. " OFFOUTVALUE0 ,Off mode output value for mcbsp1_dx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 10. " OFFOUTENABLE0 ,Off mode output enable for mcbsp1_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 9. " OFFENABLE0 ,Off mode enable for mcbsp1_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 8. " INPUTENABLE0 ,Input enable for mcbsp1_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp1_dx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp1_dx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp1_dx" "0,1,2,3,4,5,6,7"
|
|
line.long 0x28 "CONTROL_PADCONF_MCBSP_CLKS,Configuration Register For Pads mcbsp_clks; mcbsp1_fsx"
|
|
bitfld.long 0x28 31. " WAKEUPEVENT1 ,Wake Up event for mcbsp1_fsx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x28 30. " WAKEUPENABLE1 ,Wake Up enable for mcbsp1_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcbsp1_fsx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcbsp1_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 27. " OFFOUTVALUE1 ,Off mode output value for mcbsp1_fsx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x28 26. " OFFOUTENABLE1 ,Off mode output enable for mcbsp1_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 25. " OFFENABLE1 ,Off mode enable for mcbsp1_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 24. " INPUTENABLE1 ,Input enable for mcbsp1_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcbsp1_fsx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcbsp1_fsx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcbsp1_fsx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x28 15. " WAKEUPEVENT0 ,Wake Up event for mcbsp_clks" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x28 14. " WAKEUPENABLE0 ,Wake Up enable for mcbsp_clks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcbsp_clks" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcbsp_clks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 11. " OFFOUTVALUE0 ,Off mode output value for mcbsp_clks" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x28 10. " OFFOUTENABLE0 ,Off mode output enable for mcbsp_clks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 9. " OFFENABLE0 ,Off mode enable for mcbsp_clks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 8. " INPUTENABLE0 ,Input enable for mcbsp_clks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp_clks" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp_clks" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp_clks" "0,1,2,3,4,5,6,7"
|
|
line.long 0x2C "CONTROL_PADCONF_MCBSP1_CLKX,Configuration Register For Pads mcbsp1_clkx; uart3_cts_rctx"
|
|
bitfld.long 0x2C 31. " WAKEUPEVENT1 ,Wake Up event for uart3_cts_rctx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x2C 30. " WAKEUPENABLE1 ,Wake Up enable for uart3_cts_rctx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for uart3_cts_rctx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for uart3_cts_rctx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 27. " OFFOUTVALUE1 ,Off mode output value for uart3_cts_rctx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x2C 26. " OFFOUTENABLE1 ,Off mode output enable for uart3_cts_rctx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 25. " OFFENABLE1 ,Off mode enable for uart3_cts_rctx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 24. " INPUTENABLE1 ,Input enable for uart3_cts_rctx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for uart3_cts_rctx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 19. " PULLUDENABLE1 ,Pull-up/Down enable for uart3_cts_rctx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 16.--18. " MUXMODE1 ,Functional multiplexing selection for uart3_cts_rctx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x2C 15. " WAKEUPEVENT0 ,Wake Up event for mcbsp1_clkx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x2C 14. " WAKEUPENABLE0 ,Wake Up enable for mcbsp1_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcbsp1_clkx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcbsp1_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 11. " OFFOUTVALUE0 ,Off mode output value for mcbsp1_clkx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x2C 10. " OFFOUTENABLE0 ,Off mode output enable for mcbsp1_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " OFFENABLE0 ,Off mode enable for mcbsp1_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 8. " INPUTENABLE0 ,Input enable for mcbsp1_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcbsp1_clkx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcbsp1_clkx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcbsp1_clkx" "0,1,2,3,4,5,6,7"
|
|
line.long 0x30 "CONTROL_PADCONF_UART3_RTS_SD,Configuration Register For Pads uart3_rts_sd; uart3_rx_irrx"
|
|
bitfld.long 0x30 31. " WAKEUPEVENT1 ,Wake Up event for uart3_rx_irrx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x30 30. " WAKEUPENABLE1 ,Wake Up enable for uart3_rx_irrx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for uart3_rx_irrx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for uart3_rx_irrx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 27. " OFFOUTVALUE1 ,Off mode output value for uart3_rx_irrx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x30 26. " OFFOUTENABLE1 ,Off mode output enable for uart3_rx_irrx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 25. " OFFENABLE1 ,Off mode enable for uart3_rx_irrx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 24. " INPUTENABLE1 ,Input enable for uart3_rx_irrx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 20. " PULLTYPESELECT1 ,Pull-up/Down selection for uart3_rx_irrx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 19. " PULLUDENABLE1 ,Pull-up/Down enable for uart3_rx_irrx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 16.--18. " MUXMODE1 ,Functional multiplexing selection for uart3_rx_irrx" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x30 15. " WAKEUPEVENT0 ,Wake Up event for uart3_rts_sd" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x30 14. " WAKEUPENABLE0 ,Wake Up enable for uart3_rts_sd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for uart3_rts_sd" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for uart3_rts_sd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 11. " OFFOUTVALUE0 ,Off mode output value for uart3_rts_sd" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x30 10. " OFFOUTENABLE0 ,Off mode output enable for uart3_rts_sd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 9. " OFFENABLE0 ,Off mode enable for uart3_rts_sd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 8. " INPUTENABLE0 ,Input enable for uart3_rts_sd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 4. " PULLTYPESELECT0 ,Pull-up/Down selection for uart3_rts_sd" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 3. " PULLUDENABLE0 ,Pull-up/Down enable for uart3_rts_sd" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 0.--2. " MUXMODE0 ,Functional multiplexing selection for uart3_rts_sd" "0,1,2,3,4,5,6,7"
|
|
line.long 0x34 "CONTROL_PADCONF_UART3_TX_IRTX,Configuration Register For Pads uart3_tx_irtx; hsusb0_clk"
|
|
bitfld.long 0x34 31. " WAKEUPEVENT1 ,Wake Up event for hsusb0_clk" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x34 30. " WAKEUPENABLE1 ,Wake Up enable for hsusb0_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for hsusb0_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for hsusb0_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 27. " OFFOUTVALUE1 ,Off mode output value for hsusb0_clk" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x34 26. " OFFOUTENABLE1 ,Off mode output enable for hsusb0_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 25. " OFFENABLE1 ,Off mode enable for hsusb0_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 24. " INPUTENABLE1 ,Input enable for hsusb0_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 20. " PULLTYPESELECT1 ,Pull-up/Down selection for hsusb0_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 19. " PULLUDENABLE1 ,Pull-up/Down enable for hsusb0_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 16.--18. " MUXMODE1 ,Functional multiplexing selection for hsusb0_clk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x34 15. " WAKEUPEVENT0 ,Wake Up event for uart3_tx_irtx" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x34 14. " WAKEUPENABLE0 ,Wake Up enable for uart3_tx_irtx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for uart3_tx_irtx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for uart3_tx_irtx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 11. " OFFOUTVALUE0 ,Off mode output value for uart3_tx_irtx" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x34 10. " OFFOUTENABLE0 ,Off mode output enable for uart3_tx_irtx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 9. " OFFENABLE0 ,Off mode enable for uart3_tx_irtx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 8. " INPUTENABLE0 ,Input enable for uart3_tx_irtx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 4. " PULLTYPESELECT0 ,Pull-up/Down selection for uart3_tx_irtx" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 3. " PULLUDENABLE0 ,Pull-up/Down enable for uart3_tx_irtx" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 0.--2. " MUXMODE0 ,Functional multiplexing selection for uart3_tx_irtx" "0,1,2,3,4,5,6,7"
|
|
line.long 0x38 "CONTROL_PADCONF_HSUSB0_STP,Configuration Register For Pads hsusb0_stp, hsusb0_dir"
|
|
bitfld.long 0x38 31. " WAKEUPEVENT1 ,Wake Up event for hsusb0_dir" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x38 30. " WAKEUPENABLE1 ,Wake Up enable for hsusb0_dir" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for hsusb0_dir" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for hsusb0_dir" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 27. " OFFOUTVALUE1 ,Off mode output value for hsusb0_dir" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x38 26. " OFFOUTENABLE1 ,Off mode output enable for hsusb0_dir" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 25. " OFFENABLE1 ,Off mode enable for hsusb0_dir" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 24. " INPUTENABLE1 ,Input enable for hsusb0_dir" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 20. " PULLTYPESELECT1 ,Pull-up/Down selection for hsusb0_dir" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 19. " PULLUDENABLE1 ,Pull-up/Down enable for hsusb0_dir" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 16.--18. " MUXMODE1 ,Functional multiplexing selection for hsusb0_dir" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x38 15. " WAKEUPEVENT0 ,Wake Up event for hsusb0_stp" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x38 14. " WAKEUPENABLE0 ,Wake Up enable for hsusb0_stp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for hsusb0_stp" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for hsusb0_stp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 11. " OFFOUTVALUE0 ,Off mode output value for hsusb0_stp" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x38 10. " OFFOUTENABLE0 ,Off mode output enable for hsusb0_stp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 9. " OFFENABLE0 ,Off mode enable for hsusb0_stp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 8. " INPUTENABLE0 ,Input enable for hsusb0_stp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 4. " PULLTYPESELECT0 ,Pull-up/Down selection for hsusb0_stp" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 3. " PULLUDENABLE0 ,Pull-up/Down enable for hsusb0_stp" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 0.--2. " MUXMODE0 ,Functional multiplexing selection for hsusb0_stp" "0,1,2,3,4,5,6,7"
|
|
line.long 0x3C "CONTROL_PADCONF_HSUSB0_NXT,Configuration Register For Pads hsusb0_nxt; hsusb0_data0"
|
|
bitfld.long 0x3C 31. " WAKEUPEVENT1 ,Wake Up event for hsusb0_data0" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x3C 30. " WAKEUPENABLE1 ,Wake Up enable for hsusb0_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for hsusb0_data0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for hsusb0_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 27. " OFFOUTVALUE1 ,Off mode output value for hsusb0_data0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x3C 26. " OFFOUTENABLE1 ,Off mode output enable for hsusb0_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 25. " OFFENABLE1 ,Off mode enable for hsusb0_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 24. " INPUTENABLE1 ,Input enable for hsusb0_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for hsusb0_data0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 19. " PULLUDENABLE1 ,Pull-up/Down enable for hsusb0_data0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 16.--18. " MUXMODE1 ,Functional multiplexing selection for hsusb0_data0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x3C 15. " WAKEUPEVENT0 ,Wake Up event for hsusb0_nxt" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x3C 14. " WAKEUPENABLE0 ,Wake Up enable for hsusb0_nxt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for hsusb0_nxt" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for hsusb0_nxt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 11. " OFFOUTVALUE0 ,Off mode output value for hsusb0_nxt" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x3C 10. " OFFOUTENABLE0 ,Off mode output enable for hsusb0_nxt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 9. " OFFENABLE0 ,Off mode enable for hsusb0_nxt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 8. " INPUTENABLE0 ,Input enable for hsusb0_nxt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for hsusb0_nxt" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 3. " PULLUDENABLE0 ,Pull-up/Down enable for hsusb0_nxt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 0.--2. " MUXMODE0 ,Functional multiplexing selection for hsusb0_nxt" "0,1,2,3,4,5,6,7"
|
|
group.long 0x17C++0xb
|
|
line.long 0x0 "CONTROL_PADCONF_HSUSB0_DATA1,Configuration Register For Pads hsusb0_data1; hsusb0_data2"
|
|
bitfld.long 0x0 31. " WAKEUPEVENT1 ,Wake Up event for hsusb0_data2" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 30. " WAKEUPENABLE1 ,Wake Up enable for hsusb0_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for hsusb0_data2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for hsusb0_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " OFFOUTVALUE1 ,Off mode output value for hsusb0_data2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " OFFOUTENABLE1 ,Off mode output enable for hsusb0_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " OFFENABLE1 ,Off mode enable for hsusb0_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for hsusb0_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for hsusb0_data2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for hsusb0_data2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for hsusb0_data2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 15. " WAKEUPEVENT0 ,Wake Up event for hsusb0_data1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 14. " WAKEUPENABLE0 ,Wake Up enable for hsusb0_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for hsusb0_data1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for hsusb0_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " OFFOUTVALUE0 ,Off mode output value for hsusb0_data1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " OFFOUTENABLE0 ,Off mode output enable for hsusb0_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " OFFENABLE0 ,Off mode enable for hsusb0_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for hsusb0_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for hsusb0_data1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for hsusb0_data1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MUXMODE0 ,Functional multiplexing selection for hsusb0_data1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CONTROL_PADCONF_HSUSB0_DATA3,Configuration Register For Pads hsusb0_data3; hsusb0_data4"
|
|
bitfld.long 0x4 31. " WAKEUPEVENT1 ,Wake Up event for hsusb0_data4" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 30. " WAKEUPENABLE1 ,Wake Up enable for hsusb0_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for hsusb0_data4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for hsusb0_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 27. " OFFOUTVALUE1 ,Off mode output value for hsusb0_data4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 26. " OFFOUTENABLE1 ,Off mode output enable for hsusb0_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " OFFENABLE1 ,Off mode enable for hsusb0_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for hsusb0_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for hsusb0_data4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for hsusb0_data4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for hsusb0_data4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 15. " WAKEUPEVENT0 ,Wake Up event for hsusb0_data3" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 14. " WAKEUPENABLE0 ,Wake Up enable for hsusb0_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for hsusb0_data3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for hsusb0_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " OFFOUTVALUE0 ,Off mode output value for hsusb0_data3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " OFFOUTENABLE0 ,Off mode output enable for hsusb0_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " OFFENABLE0 ,Off mode enable for hsusb0_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for hsusb0_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for hsusb0_data3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for hsusb0_data3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " MUXMODE0 ,Functional multiplexing selection for hsusb0_data3" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CONTROL_PADCONF_HSUSB0_DATA5,Configuration Register For Pads hsusb0_data5; hsusb0_data6"
|
|
bitfld.long 0x8 31. " WAKEUPEVENT1 ,Wake Up event for hsusb0_data6" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 30. " WAKEUPENABLE1 ,Wake Up enable for hsusb0_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for hsusb0_data6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for hsusb0_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 27. " OFFOUTVALUE1 ,Off mode output value for hsusb0_data6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 26. " OFFOUTENABLE1 ,Off mode output enable for hsusb0_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 25. " OFFENABLE1 ,Off mode enable for hsusb0_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for hsusb0_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for hsusb0_data6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for hsusb0_data6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for hsusb0_data6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 15. " WAKEUPEVENT0 ,Wake Up event for hsusb0_data5" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 14. " WAKEUPENABLE0 ,Wake Up enable for hsusb0_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for hsusb0_data5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for hsusb0_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 11. " OFFOUTVALUE0 ,Off mode output value for hsusb0_data5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 10. " OFFOUTENABLE0 ,Off mode output enable for hsusb0_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 9. " OFFENABLE0 ,Off mode enable for hsusb0_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for hsusb0_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for hsusb0_data5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for hsusb0_data5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for hsusb0_data5" "0,1,2,3,4,5,6,7"
|
|
group.long 0x188++0x2b
|
|
line.long 0x00 "CONTROL_PADCONF_HSUSB0_DATA7,Configuration Register For Pads hsusb0_data7; i2c1_scl"
|
|
bitfld.long 0x00 31. " WAKEUPEVENT1 ,Wake Up event for i2c1_scl" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WAKEUPENABLE1 ,Wake Up enable for i2c1_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for i2c1_scl" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for i2c1_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " OFFOUTVALUE1 ,Off mode output value for i2c1_scl" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OFFOUTENABLE1 ,Off mode output enable for i2c1_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OFFENABLE1 ,Off mode enable for i2c1_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " INPUTENABLE1 ,Input enable for i2c1_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for i2c1_scl" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for i2c1_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAKEUPEVENT0 ,Wake Up event for hsusb0_data7" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 14. " WAKEUPENABLE0 ,Wake Up enable for hsusb0_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for hsusb0_data7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for hsusb0_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFFOUTVALUE0 ,Off mode output value for hsusb0_data7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OFFOUTENABLE0 ,Off mode output enable for hsusb0_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFFENABLE0 ,Off mode enable for hsusb0_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for hsusb0_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for hsusb0_data7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for hsusb0_data7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MUXMODE0 ,Functional multiplexing selection for hsusb0_data7" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "CONTROL_PADCONF_I2C1_SDA,Configuration Register For Pads i2c1_sda; i2c2_scl"
|
|
bitfld.long 0x04 31. " WAKEUPEVENT1 ,Wake Up event for i2c2_scl" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x04 30. " WAKEUPENABLE1 ,Wake Up enable for i2c2_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for i2c2_scl" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for i2c2_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OFFOUTVALUE1 ,Off mode output value for i2c2_scl" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 26. " OFFOUTENABLE1 ,Off mode output enable for i2c2_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " OFFENABLE1 ,Off mode enable for i2c2_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " INPUTENABLE1 ,Input enable for i2c2_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PULLTYPESELECT1 ,Pull-up/Down selection for i2c2_scl" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PULLUDENABLE1 ,Pull-up/Down enable for i2c2_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " MUXMODE1 ,Functional multiplexing selection for i2c2_sci" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 15. " WAKEUPEVENT0 ,Wake Up event for i2c1_sda" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x04 14. " WAKEUPENABLE0 ,Wake Up enable for i2c1_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for i2c1_sda" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for i2c1_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OFFOUTVALUE0 ,Off mode output value for i2c1_sda" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " OFFOUTENABLE0 ,Off mode output enable for i2c1_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OFFENABLE0 ,Off mode enable for i2c1_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " INPUTENABLE0 ,Input enable for i2c1_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PULLTYPESELECT0 ,Pull-up/Down selection for i2c1_sda" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PULLUDENABLE0 ,Pull-up/Down enable for i2c1_sda" "Disabled,Enabled"
|
|
line.long 0x08 "CONTROL_PADCONF_I2C2_SDA,Configuration Register For Pads i2c2_sda; i2c3_scl"
|
|
bitfld.long 0x08 31. " WAKEUPEVENT1 ,Wake Up event for i2c3_scl" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x08 30. " WAKEUPENABLE1 ,Wake Up enable for i2c3_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for i2c3_scl" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for i2c3_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " OFFOUTVALUE1 ,Off mode output value for i2c3_scl" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 26. " OFFOUTENABLE1 ,Off mode output enable for i2c3_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OFFENABLE1 ,Off mode enable for i2c3_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " INPUTENABLE1 ,Input enable for i2c3_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " PULLTYPESELECT1 ,Pull-up/Down selection for i2c3_scl" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PULLUDENABLE1 ,Pull-up/Down enable for i2c3_scl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " MUXMODE1 ,Functional multiplexing selection for i2c3_scl" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 15. " WAKEUPEVENT0 ,Wake Up event for i2c2_sda" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x08 14. " WAKEUPENABLE0 ,Wake Up enable for i2c2_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for i2c2_sda" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for i2c2_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OFFOUTVALUE0 ,Off mode output value for i2c2_sda" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 10. " OFFOUTENABLE0 ,Off mode output enable for i2c2_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OFFENABLE0 ,Off mode enable for i2c2_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " INPUTENABLE0 ,Input enable for i2c2_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PULLTYPESELECT0 ,Pull-up/Down selection for i2c2_sda" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PULLUDENABLE0 ,Pull-up/Down enable for i2c2_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " MUXMODE0 ,Functional multiplexing selection for i2c2_sda" "0,1,2,3,4,5,6,7"
|
|
line.long 0x0C "CONTROL_PADCONF_I2C3_SDA,Configuration Register For Pads i2c3_sda; hdq_sio"
|
|
bitfld.long 0x0C 31. " WAKEUPEVENT1 ,Wake Up event for hdq_sio" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0C 30. " WAKEUPENABLE1 ,Wake Up enable for hdq_sio" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for hdq_sio" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for hdq_sio" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " OFFOUTVALUE1 ,Off mode output value for hdq_sio" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " OFFOUTENABLE1 ,Off mode output enable for hdq_sio" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " OFFENABLE1 ,Off mode enable for hdq_sio" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " INPUTENABLE1 ,Input enable for hdq_sio" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for hdq_sio" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " PULLUDENABLE1 ,Pull-up/Down enable for hdq_sio" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--18. " MUXMODE1 ,Functional multiplexing selection for hdq_sio" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " WAKEUPEVENT0 ,Wake Up event for i2c3_sda" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " WAKEUPENABLE0 ,Wake Up enable for i2c3_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for i2c3_sda" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for i2c3_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " OFFOUTVALUE0 ,Off mode output value for i2c3_sda" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " OFFOUTENABLE0 ,Off mode output enable for i2c3_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " OFFENABLE0 ,Off mode enable for i2c3_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " INPUTENABLE0 ,Input enable for i2c3_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for i2c3_sda" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " PULLUDENABLE0 ,Pull-up/Down enable for i2c3_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " MUXMODE0 ,Functional multiplexing selection for i2c3_sda" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "CONTROL_PADCONF_MCSPI1_CLK,Configuration Register For Pads mcspi1_clk; mcspi1_simo"
|
|
bitfld.long 0x10 31. " WAKEUPEVENT1 ,Wake Up event for mcspi1_simo" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 30. " WAKEUPENABLE1 ,Wake Up enable for mcspi1_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcspi1_simo" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcspi1_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " OFFOUTVALUE1 ,Off mode output value for mcspi1_simo" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 26. " OFFOUTENABLE1 ,Off mode output enable for mcspi1_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " OFFENABLE1 ,Off mode enable for mcspi1_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for mcspi1_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcspi1_simo" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcspi1_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcspi1_simo" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 15. " WAKEUPEVENT0 ,Wake Up event for mcspi1_clk" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 14. " WAKEUPENABLE0 ,Wake Up enable for mcspi1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcspi1_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcspi1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " OFFOUTVALUE0 ,Off mode output value for mcspi1_clk" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 10. " OFFOUTENABLE0 ,Off mode output enable for mcspi1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " OFFENABLE0 ,Off mode enable for mcspi1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for mcspi1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcspi1_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcspi1_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcspi1_clk" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CONTROL_PADCONF_MCSPI1_SOMI,Configuration Register For Pads mcspi1_somi; mcspi1_cs0"
|
|
bitfld.long 0x14 31. " WAKEUPEVENT1 ,Wake Up event for mcspi1_cs0" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 30. " WAKEUPENABLE1 ,Wake Up enable for mcspi1_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcspi1_cs0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcspi1_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " OFFOUTVALUE1 ,Off mode output value for mcspi1_cs0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 26. " OFFOUTENABLE1 ,Off mode output enable for mcspi1_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " OFFENABLE1 ,Off mode enable for mcspi1_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for mcspi1_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcspi1_cs0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcspi1_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcspi1_cs0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 15. " WAKEUPEVENT0 ,Wake Up event for mcspi1_somi" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 14. " WAKEUPENABLE0 ,Wake Up enable for mcspi1_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcspi1_somi" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcspi1_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " OFFOUTVALUE0 ,Off mode output value for mcspi1_somi" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 10. " OFFOUTENABLE0 ,Off mode output enable for mcspi1_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " OFFENABLE0 ,Off mode enable for mcspi1_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for mcspi1_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcspi1_somi" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcspi1_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcspi1_somi" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "CONTROL_PADCONF_MCSPI1_CS1,Configuration Register For Pads mcspi1_cs1; mcspi1_cs2"
|
|
bitfld.long 0x18 31. " WAKEUPEVENT1 ,Wake Up event for mcspi1_cs2" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 30. " WAKEUPENABLE1 ,Wake Up enable for mcspi1_cs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcspi1_cs2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcspi1_cs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 27. " OFFOUTVALUE1 ,Off mode output value for mcspi1_cs2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 26. " OFFOUTENABLE1 ,Off mode output enable for mcspi1_cs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 25. " OFFENABLE1 ,Off mode enable for mcspi1_cs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for mcspi1_cs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcspi1_cs2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcspi1_cs2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcspi1_cs2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 15. " WAKEUPEVENT0 ,Wake Up event for mcspi1_cs1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 14. " WAKEUPENABLE0 ,Wake Up enable for mcspi1_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcspi1_cs1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcspi1_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " OFFOUTVALUE0 ,Off mode output value for mcspi1_cs1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 10. " OFFOUTENABLE0 ,Off mode output enable for mcspi1_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " OFFENABLE0 ,Off mode enable for mcspi1_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for mcspi1_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcspi1_cs1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcspi1_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcspi1_cs1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "CONTROL_PADCONF_MCSPI1_CS3,Configuration Register For Pads mcspi1_cs3; mcspi2_clk"
|
|
bitfld.long 0x1C 31. " WAKEUPEVENT1 ,Wake Up event for mcspi2_clk" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x1C 30. " WAKEUPENABLE1 ,Wake Up enable for mcspi2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcspi2_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcspi2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " OFFOUTVALUE1 ,Off mode output value for mcspi2_clk" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 26. " OFFOUTENABLE1 ,Off mode output enable for mcspi2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " OFFENABLE1 ,Off mode enable for mcspi2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for mcspi2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcspi2_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcspi2_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcspi2_clk" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " WAKEUPEVENT0 ,Wake Up event for mcspi1_cs3" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x1C 14. " WAKEUPENABLE0 ,Wake Up enable for mcspi1_cs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcspi1_cs3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcspi1_cs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " OFFOUTVALUE0 ,Off mode output value for mcspi1_cs3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " OFFOUTENABLE0 ,Off mode output enable for mcspi1_cs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " OFFENABLE0 ,Off mode enable for mcspi1_cs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for mcspi1_cs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcspi1_cs3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcspi1_cs3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcspi1_cs3" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "CONTROL_PADCONF_MCSPI2_SIMO,Configuration Register For Pads mcspi2_simo; mcspi2_somi"
|
|
bitfld.long 0x20 31. " WAKEUPEVENT1 ,Wake Up event for mcspi2_somi" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x20 30. " WAKEUPENABLE1 ,Wake Up enable for mcspi2_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcspi2_somi" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcspi2_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 27. " OFFOUTVALUE1 ,Off mode output value for mcspi2_somi" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x20 26. " OFFOUTENABLE1 ,Off mode output enable for mcspi2_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 25. " OFFENABLE1 ,Off mode enable for mcspi2_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 24. " INPUTENABLE1 ,Input enable for mcspi2_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcspi2_somi" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcspi2_somi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcspi2_somi" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x20 15. " WAKEUPEVENT0 ,Wake Up event for mcspi2_simo" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x20 14. " WAKEUPENABLE0 ,Wake Up enable for mcspi2_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcspi2_simo" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcspi2_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 11. " OFFOUTVALUE0 ,Off mode output value for mcspi2_simo" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x20 10. " OFFOUTENABLE0 ,Off mode output enable for mcspi2_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 9. " OFFENABLE0 ,Off mode enable for mcspi2_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for mcspi2_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcspi2_simo" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcspi2_simo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcspi2_simo" "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "CONTROL_PADCONF_MCSPI2_CS0,Configuration Register For Pads mcspi2_cs0; mcspi2_cs1"
|
|
bitfld.long 0x24 31. " WAKEUPEVENT1 ,Wake Up event for mcspi2_cs1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x24 30. " WAKEUPENABLE1 ,Wake Up enable for mcspi2_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for mcspi2_cs1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for mcspi2_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 27. " OFFOUTVALUE1 ,Off mode output value for mcspi2_cs1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 26. " OFFOUTENABLE1 ,Off mode output enable for mcspi2_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 25. " OFFENABLE1 ,Off mode enable for mcspi2_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 24. " INPUTENABLE1 ,Input enable for mcspi2_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 20. " PULLTYPESELECT1 ,Pull-up/Down selection for mcspi2_cs1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 19. " PULLUDENABLE1 ,Pull-up/Down enable for mcspi2_cs1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 16.--18. " MUXMODE1 ,Functional multiplexing selection for mcspi2_cs1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x24 15. " WAKEUPEVENT0 ,Wake Up event for mcspi2_cs0" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x24 14. " WAKEUPENABLE0 ,Wake Up enable for mcspi2_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for mcspi2_cs0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for mcspi2_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 11. " OFFOUTVALUE0 ,Off mode output value for mcspi2_cs0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 10. " OFFOUTENABLE0 ,Off mode output enable for mcspi2_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 9. " OFFENABLE0 ,Off mode enable for mcspi2_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 8. " INPUTENABLE0 ,Input enable for mcspi2_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " PULLTYPESELECT0 ,Pull-up/Down selection for mcspi2_cs0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 3. " PULLUDENABLE0 ,Pull-up/Down enable for mcspi2_cs0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0.--2. " MUXMODE0 ,Functional multiplexing selection for mcspi2_cs0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x28 "CONTROL_PADCONF_SYS_NIRQ,Configuration Register For Pads sys_nirq; sys_clkout2"
|
|
bitfld.long 0x28 31. " WAKEUPEVENT1 ,Wake Up event for sys_clkout2" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x28 30. " WAKEUPENABLE1 ,Wake Up enable for sys_clkout2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sys_clkout2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sys_clkout2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 27. " OFFOUTVALUE1 ,Off mode output value for sys_clkout2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x28 26. " OFFOUTENABLE1 ,Off mode output enable for sys_clkout2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 25. " OFFENABLE1 ,Off mode enable for sys_clkout2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 24. " INPUTENABLE1 ,Input enable for sys_clkout2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_clkout2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_clkout2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_clkout2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x28 15. " WAKEUPEVENT0 ,Wake Up event for sys_nirq" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x28 14. " WAKEUPENABLE0 ,Wake Up enable for sys_nirq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sys_nirq" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sys_nirq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 11. " OFFOUTVALUE0 ,Off mode output value for sys_nirq" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x28 10. " OFFOUTENABLE0 ,Off mode output enable for sys_nirq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 9. " OFFENABLE0 ,Off mode enable for sys_nirq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 8. " INPUTENABLE0 ,Input enable for sys_nirq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sys_nirq" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 3. " PULLUDENABLE0 ,Pull-up/Down enable for sys_nirq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " MUXMODE0 ,Functional multiplexing selection for sys_nirq" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1B4++0x47
|
|
line.long 0x0 "CONTROL_PADCONF_SAD2D_MCAD0,Configuration Register For Pads sad2d_mcad0; sad2d_mcad1"
|
|
bitfld.long 0x0 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for sad2d_mcad1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for sad2d_mcad0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad0" "Disabled,Enabled"
|
|
line.long 0x4 "CONTROL_PADCONF_SAD2D_MCAD2,Configuration Register For Pads sad2d_mcad2; sad2d_mcad3"
|
|
bitfld.long 0x4 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for sad2d_mcad3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for sad2d_mcad2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad2" "Disabled,Enabled"
|
|
line.long 0x8 "CONTROL_PADCONF_SAD2D_MCAD4,Configuration Register For Pads sad2d_mcad4; sad2d_mcad5"
|
|
bitfld.long 0x8 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for sad2d_mcad5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for sad2d_mcad4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad4" "Disabled,Enabled"
|
|
line.long 0xC "CONTROL_PADCONF_SAD2D_MCAD6,Configuration Register For Pads sad2d_mcad6; sad2d_mcad7"
|
|
bitfld.long 0xC 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for sad2d_mcad7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for sad2d_mcad6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad6" "Disabled,Enabled"
|
|
line.long 0x10 "CONTROL_PADCONF_SAD2D_MCAD8,Configuration Register For Pads sad2d_mcad8; sad2d_mcad9"
|
|
bitfld.long 0x10 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad9" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for sad2d_mcad9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for sad2d_mcad8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad8" "Disabled,Enabled"
|
|
line.long 0x14 "CONTROL_PADCONF_SAD2D_MCAD10,Configuration Register For Pads sad2d_mcad10; sad2d_mcad11"
|
|
bitfld.long 0x14 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for sad2d_mcad11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for sad2d_mcad10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad10" "Disabled,Enabled"
|
|
line.long 0x18 "CONTROL_PADCONF_SAD2D_MCAD12,Configuration Register For Pads sad2d_mcad12; sad2d_mcad13"
|
|
bitfld.long 0x18 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for sad2d_mcad13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for sad2d_mcad12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad12" "Disabled,Enabled"
|
|
line.long 0x1C "CONTROL_PADCONF_SAD2D_MCAD14,Configuration Register For Pads sad2d_mcad14; sad2d_mcad15"
|
|
bitfld.long 0x1C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for sad2d_mcad15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for sad2d_mcad14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad14" "Disabled,Enabled"
|
|
line.long 0x20 "CONTROL_PADCONF_SAD2D_MCAD16,Configuration Register For Pads sad2d_mcad16; sad2d_mcad17"
|
|
bitfld.long 0x20 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad17" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad17" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x20 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 24. " INPUTENABLE1 ,Input enable for sad2d_mcad17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad17" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad17" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad16" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad16" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x20 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for sad2d_mcad16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad16" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad16" "Disabled,Enabled"
|
|
line.long 0x24 "CONTROL_PADCONF_SAD2D_MCAD18,Configuration Register For Pads sad2d_mcad18; sad2d_mcad19"
|
|
bitfld.long 0x24 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad19" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 24. " INPUTENABLE1 ,Input enable for sad2d_mcad19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad19" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad18" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 8. " INPUTENABLE0 ,Input enable for sad2d_mcad18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad18" "Disabled,Enabled"
|
|
line.long 0x28 "CONTROL_PADCONF_SAD2D_MCAD20,Configuration Register For Pads sad2d_mcad20; sad2d_mcad21"
|
|
bitfld.long 0x28 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad21" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad21" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x28 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 24. " INPUTENABLE1 ,Input enable for sad2d_mcad21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad21" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad21" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad20" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x28 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 8. " INPUTENABLE0 ,Input enable for sad2d_mcad20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x28 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x28 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad20" "Disabled,Enabled"
|
|
line.long 0x2C "CONTROL_PADCONF_SAD2D_MCAD22,Configuration Register For Pads sad2d_mcad22; sad2d_mcad23"
|
|
bitfld.long 0x2C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad23" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad23" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x2C 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 24. " INPUTENABLE1 ,Input enable for sad2d_mcad23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad23" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad22" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad22" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x2C 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 8. " INPUTENABLE0 ,Input enable for sad2d_mcad22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x2C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad22" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x2C 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad22" "Disabled,Enabled"
|
|
line.long 0x30 "CONTROL_PADCONF_SAD2D_MCAD24,Configuration Register For Pads sad2d_mcad24; sad2d_mcad25"
|
|
bitfld.long 0x30 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad25" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad25" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x30 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 24. " INPUTENABLE1 ,Input enable for sad2d_mcad25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad25" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad25" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad24" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad24" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x30 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 8. " INPUTENABLE0 ,Input enable for sad2d_mcad24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x30 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad24" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x30 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad24" "Disabled,Enabled"
|
|
line.long 0x34 "CONTROL_PADCONF_SAD2D_MCAD26,Configuration Register For Pads sad2d_mcad26; sad2d_mcad27"
|
|
bitfld.long 0x34 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad27" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad27" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x34 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 24. " INPUTENABLE1 ,Input enable for sad2d_mcad27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad27" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad27" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad26" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad26" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x34 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 8. " INPUTENABLE0 ,Input enable for sad2d_mcad26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x34 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad26" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x34 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad26" "Disabled,Enabled"
|
|
line.long 0x38 "CONTROL_PADCONF_SAD2D_MCAD28,Configuration Register For Pads sad2d_mcad28; sad2d_mcad29"
|
|
bitfld.long 0x38 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad29" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad29" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x38 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 24. " INPUTENABLE1 ,Input enable for sad2d_mcad29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad29" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad28" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad28" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x38 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 8. " INPUTENABLE0 ,Input enable for sad2d_mcad28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x38 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad28" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x38 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad28" "Disabled,Enabled"
|
|
line.long 0x3C "CONTROL_PADCONF_SAD2D_MCAD30,Configuration Register For Pads sad2d_mcad30; sad2d_mcad31"
|
|
bitfld.long 0x3C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad31" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad31" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x3C 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 24. " INPUTENABLE1 ,Input enable for sad2d_mcad31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad31" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad31" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad30" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad30" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x3C 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 8. " INPUTENABLE0 ,Input enable for sad2d_mcad30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x3C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad30" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x3C 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad30" "Disabled,Enabled"
|
|
line.long 0x40 "CONTROL_PADCONF_SAD2D_MCAD32,Configuration Register For Pads sad2d_mcad32; sad2d_mcad33"
|
|
bitfld.long 0x40 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad33" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x40 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad33" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x40 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 24. " INPUTENABLE1 ,Input enable for sad2d_mcad33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad33" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x40 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad33" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad32" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x40 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad32" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x40 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 8. " INPUTENABLE0 ,Input enable for sad2d_mcad32" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x40 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad32" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x40 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad32" "Disabled,Enabled"
|
|
line.long 0x44 "CONTROL_PADCONF_SAD2D_MCAD34,Configuration Register For Pads sad2d_mcad34; sad2d_mcad35"
|
|
bitfld.long 0x44 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mcad35" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x44 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mcad35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mcad35" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x44 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mcad35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 25. " OFFENABLE1 ,Off mode enable for sad2d_mcad35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 24. " INPUTENABLE1 ,Input enable for sad2d_mcad35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mcad35" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x44 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mcad35" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad34" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x44 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad34" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x44 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 8. " INPUTENABLE0 ,Input enable for sad2d_mcad34" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x44 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad34" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x44 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad34" "Disabled,Enabled"
|
|
group.long 0x1FC++0xF
|
|
line.long 0x00 "CONTROL_PADCONF_SAD2D_MCAD36,Configuration Register For Pads sad2d_mcad36; sad2d_clk26mi"
|
|
bitfld.long 0x00 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_clk26mi" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_clk26mi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OFFENABLE1 ,Off mode enable for sad2d_clk26mi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mcad36" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mcad36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_mcad36" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_mcad36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFFENABLE0 ,Off mode enable for sad2d_mcad36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for sad2d_mcad36" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mcad36" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mcad36" "Disabled,Enabled"
|
|
line.long 0x04 "CONTROL_PADCONF_SAD2D_NRESPWRON,Configuration Register For Pads sad2d_nrespwron; sad2d_nreswarm"
|
|
bitfld.long 0x04 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_nreswarm" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_nreswarm" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_nreswarm" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_nreswarm" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " OFFENABLE1 ,Off mode enable for sad2d_nreswarm" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_nreswarm" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_nreswarm" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_nrespwron" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_nrespwron" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OFFENABLE0 ,Off mode enable for sad2d_nrespwron" "Disabled,Enabled"
|
|
line.long 0x08 "CONTROL_PADCONF_SAD2D_ARMNIRQ,Configuration Register For Pads sasad2d_armnirq; sasad2d_umafiq"
|
|
bitfld.long 0x08 27. " OFFOUTVALUE1 ,Off mode output value for sasad2d_umafiq" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 26. " OFFOUTENABLE1 ,Off mode output enable for sasad2d_umafiq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OFFENABLE1 ,Off mode enable for sasad2d_umafiq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OFFOUTVALUE0 ,Off mode output value for sasad2d_armnirq" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 10. " OFFOUTENABLE0 ,Off mode output enable for sasad2d_armnirq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OFFENABLE0 ,Off mode enable for sasad2d_armnirq" "Disabled,Enabled"
|
|
line.long 0x0C "CONTROL_PADCONF_SAD2D_SPINT,Configuration Register For Pads sad2d_spint; sad2d_frint"
|
|
bitfld.long 0x0C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_frint" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_frint" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " OFFENABLE1 ,Off mode enable for sad2d_frint" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " INPUTENABLE1 ,Input enable for sad2d_frint" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_frint" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_frint" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--18. " MUXMODE1 ,Functional multiplexing selection for sad2d_frint" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_spint" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_spint" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " OFFENABLE0 ,Off mode enable for sad2d_spint" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " INPUTENABLE0 ,Input enable for sad2d_spint" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_spint" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_spint" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " MUXMODE0 ,Functional multiplexing selection for sad2d_spint" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20C++0x7
|
|
line.long 0x0 "CONTROL_PADCONF_SAD2D_DMAREQ0,Configuration Register For Pads sad2d_dmareq0; sad2d_dmareq1"
|
|
bitfld.long 0x0 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_dmareq1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_dmareq1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " OFFENABLE1 ,Off mode enable for sad2d_dmareq1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for sad2d_dmareq1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_dmareq0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_dmareq0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " OFFENABLE0 ,Off mode enable for sad2d_dmareq0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MUXMODE0 ,Functional multiplexing selection for sad2d_dmareq0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CONTROL_PADCONF_SAD2D_DMAREQ2,Configuration Register For Pads sad2d_dmareq2; sad2d_dmareq3"
|
|
bitfld.long 0x4 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_dmareq3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_dmareq3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " OFFENABLE1 ,Off mode enable for sad2d_dmareq3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for sad2d_dmareq3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_dmareq2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_dmareq2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " OFFENABLE0 ,Off mode enable for sad2d_dmareq2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " MUXMODE0 ,Functional multiplexing selection for sad2d_dmareq2" "0,1,2,3,4,5,6,7"
|
|
group.long 0x214++0x23
|
|
line.long 0x00 "CONTROL_PADCONF_SAD2D_NTRST,Configuration Register For Pads sad2d_ntrst; sad2d_tdi"
|
|
bitfld.long 0x00 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_tdi" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_tdi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OFFENABLE1 ,Off mode enable for sad2d_tdi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_ntrst" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_ntrst" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFFENABLE0 ,Off mode enable for sad2d_ntrst" "Disabled,Enabled"
|
|
line.long 0x04 "CONTROL_PADCONF_SAD2D_TDO,Configuration Register For Pads sad2d_tdo; sad2d_tms"
|
|
bitfld.long 0x04 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_tms" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_tms" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " OFFENABLE1 ,Off mode enable for sad2d_tms" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_tdo" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_tdo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OFFENABLE0 ,Off mode enable for sad2d_tdo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " INPUTENABLE0 ,Input enable for sad2d_tdo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_tdo" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_tdo" "Disabled,Enabled"
|
|
line.long 0x08 "CONTROL_PADCONF_SAD2D_TCK,Configuration Register For Pads sad2d_tck; sad2d_rtck"
|
|
bitfld.long 0x08 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_rtck" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_rtck" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OFFENABLE1 ,Off mode enable for sad2d_rtck" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " INPUTENABLE1 ,Input enable for sad2d_rtck" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_rtck" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_rtck" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_tck" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_tck" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " OFFENABLE0 ,Off mode enable for sad2d_tck" "Disabled,Enabled"
|
|
line.long 0x0C "CONTROL_PADCONF_SAD2D_MSTDBY,Configuration Register For Pads sad2d_mstdby; sad2d_idlereq"
|
|
bitfld.long 0x0C 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_idlereq" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_idlereq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " OFFENABLE1 ,Off mode enable for sad2d_idlereq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_mstdby" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_mstdby" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " OFFENABLE0 ,Off mode enable for sad2d_mstdby" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " INPUTENABLE0 ,Input enable for sad2d_mstdby" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_mstdby" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_mstdby" "Disabled,Enabled"
|
|
line.long 0x10 "CONTROL_PADCONF_SAD2D_IDLEACK,Configuration Register For Pads sad2d_idleack; sad2d_mwrite"
|
|
bitfld.long 0x10 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mwrite" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mwrite" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mwrite" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mwrite" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " OFFENABLE1 ,Off mode enable for sad2d_mwrite" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for sad2d_mwrite" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mwrite" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mwrite" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_idleack" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_idleack" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " OFFENABLE0 ,Off mode enable for sad2d_idleack" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for sad2d_idleack" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_idleack" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_idleack" "Disabled,Enabled"
|
|
line.long 0x14 "CONTROL_PADCONF_SAD2D_SWRITE,Configuration Register For Pads sad2d_swrite, sad2d_mread"
|
|
bitfld.long 0x14 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mread" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mread" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " OFFENABLE1 ,Off mode enable for sad2d_mread" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for sad2d_mread" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mread" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mread" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_swrite" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_swrite" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_swrite" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_swrite" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " OFFENABLE0 ,Off mode enable for sad2d_swrite" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for sad2d_swrite" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_swrite" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_swrite" "Disabled,Enabled"
|
|
line.long 0x18 "CONTROL_PADCONF_SAD2D_SREAD,Configuration Register For Pads sad2d_sread; sad2d_mbusflag"
|
|
bitfld.long 0x18 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for sad2d_mbusflag" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for sad2d_mbusflag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 27. " OFFOUTVALUE1 ,Off mode output value for sad2d_mbusflag" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 26. " OFFOUTENABLE1 ,Off mode output enable for sad2d_mbusflag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 25. " OFFENABLE1 ,Off mode enable for sad2d_mbusflag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for sad2d_mbusflag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sad2d_mbusflag" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for sad2d_mbusflag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for sad2d_sread" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for sad2d_sread" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_sread" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_sread" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " OFFENABLE0 ,Off mode enable for sad2d_sread" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for sad2d_sread" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_sread" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_sread" "Disabled,Enabled"
|
|
line.long 0x1C "CONTROL_PADCONF_SAD2D_SBUSFLAG,Configuration Register For Pad sad2d_sbusflag;sdrc_cke0"
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for sdrc_cke0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sdrc_cke0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for sdrc_cke0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--18. " MUXMODE1 ,Functional multiplexing selection for sdrc_cke0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " OFFOUTVALUE0 ,Off mode output value for sad2d_sbusflag" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " OFFOUTENABLE0 ,Off mode output enable for sad2d_sbusflag" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " OFFENABLE0 ,Off mode enable for sad2d_sbusflag" "Disabled,Enabled"
|
|
line.long 0x20 "CONTROL_PADCONF_SDRC_CKE1,Configuration Register For Pads sdrc_cke1"
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for sdrc_cke1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sdrc_cke1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for sdrc_cke1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 0.--2. " MUXMODE0 ,Functional multiplexing selection for sdrc_cke1" "0,1,2,3,4,5,6,7"
|
|
group.long 0x5A8++0x3
|
|
line.long 0x00 "CONTROL_PADCONF_ETK_CLK,Configuration Register For Pads etk_clk; etk_ctl"
|
|
bitfld.long 0x00 31. " WAKEUPEVENT1 ,Wake Up event for etk_ctl" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 30. " WAKEUPENABLE1 ,Wake Up enable for etk_ctl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for etk_ctl" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for etk_ctl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " OFFOUTVALUE1 ,Off mode output value for etk_ctl" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OFFOUTENABLE1 ,Off mode output enable for etk_ctl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OFFENABLE1 ,Off mode enable for etk_ctl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " INPUTENABLE1 ,Input enable for etk_ctl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_ctl" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_ctl" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_ctl" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WAKEUPEVENT0 ,Wake Up event for etk_clk" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x00 14. " WAKEUPENABLE0 ,Wake Up enable for etk_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for etk_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for etk_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OFFOUTVALUE0 ,Off mode output value for etk_clk" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OFFOUTENABLE0 ,Off mode output enable for etk_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " OFFENABLE0 ,Off mode enable for etk_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for etk_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_clk" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_clk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_clk" "0,1,2,3,4,5,6,7"
|
|
group.long 0x5AC++0x1F
|
|
line.long 0x0 "CONTROL_PADCONF_ETK_D0,Configuration Register For Pads etk_d0; etk_d1"
|
|
bitfld.long 0x0 31. " WAKEUPEVENT1 ,Wake Up event for etk_d1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 30. " WAKEUPENABLE1 ,Wake Up enable for etk_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for etk_d1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for etk_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 27. " OFFOUTVALUE1 ,Off mode output value for etk_d1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 26. " OFFOUTENABLE1 ,Off mode output enable for etk_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 25. " OFFENABLE1 ,Off mode enable for etk_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 24. " INPUTENABLE1 ,Input enable for etk_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x0 15. " WAKEUPEVENT0 ,Wake Up event for etk_d0" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x0 14. " WAKEUPENABLE0 ,Wake Up enable for etk_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for etk_d0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for etk_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 11. " OFFOUTVALUE0 ,Off mode output value for etk_d0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0 10. " OFFOUTENABLE0 ,Off mode output enable for etk_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " OFFENABLE0 ,Off mode enable for etk_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " INPUTENABLE0 ,Input enable for etk_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CONTROL_PADCONF_ETK_D2,Configuration Register For Pads etk_d2; etk_d3"
|
|
bitfld.long 0x4 31. " WAKEUPEVENT1 ,Wake Up event for etk_d3" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 30. " WAKEUPENABLE1 ,Wake Up enable for etk_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for etk_d3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for etk_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 27. " OFFOUTVALUE1 ,Off mode output value for etk_d3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 26. " OFFOUTENABLE1 ,Off mode output enable for etk_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 25. " OFFENABLE1 ,Off mode enable for etk_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 24. " INPUTENABLE1 ,Input enable for etk_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 15. " WAKEUPEVENT0 ,Wake Up event for etk_d2" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x4 14. " WAKEUPENABLE0 ,Wake Up enable for etk_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for etk_d2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for etk_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 11. " OFFOUTVALUE0 ,Off mode output value for etk_d2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x4 10. " OFFOUTENABLE0 ,Off mode output enable for etk_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 9. " OFFENABLE0 ,Off mode enable for etk_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 8. " INPUTENABLE0 ,Input enable for etk_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x4 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d2" "0,1,2,3,4,5,6,7"
|
|
line.long 0x8 "CONTROL_PADCONF_ETK_D4,Configuration Register For Pads etk_d4; etk_d5"
|
|
bitfld.long 0x8 31. " WAKEUPEVENT1 ,Wake Up event for etk_d5" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 30. " WAKEUPENABLE1 ,Wake Up enable for etk_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for etk_d5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for etk_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 27. " OFFOUTVALUE1 ,Off mode output value for etk_d5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 26. " OFFOUTENABLE1 ,Off mode output enable for etk_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 25. " OFFENABLE1 ,Off mode enable for etk_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 24. " INPUTENABLE1 ,Input enable for etk_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d5" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x8 15. " WAKEUPEVENT0 ,Wake Up event for etk_d4" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x8 14. " WAKEUPENABLE0 ,Wake Up enable for etk_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for etk_d4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for etk_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 11. " OFFOUTVALUE0 ,Off mode output value for etk_d4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x8 10. " OFFOUTENABLE0 ,Off mode output enable for etk_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 9. " OFFENABLE0 ,Off mode enable for etk_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 8. " INPUTENABLE0 ,Input enable for etk_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x8 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d4" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "CONTROL_PADCONF_ETK_D6,Configuration Register For Pads etk_d6; etk_d7"
|
|
bitfld.long 0xC 31. " WAKEUPEVENT1 ,Wake Up event for etk_d7" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 30. " WAKEUPENABLE1 ,Wake Up enable for etk_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for etk_d7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for etk_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 27. " OFFOUTVALUE1 ,Off mode output value for etk_d7" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 26. " OFFOUTENABLE1 ,Off mode output enable for etk_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 25. " OFFENABLE1 ,Off mode enable for etk_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for etk_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d7" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 15. " WAKEUPEVENT0 ,Wake Up event for etk_d6" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 14. " WAKEUPENABLE0 ,Wake Up enable for etk_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for etk_d6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for etk_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 11. " OFFOUTVALUE0 ,Off mode output value for etk_d6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 10. " OFFOUTENABLE0 ,Off mode output enable for etk_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 9. " OFFENABLE0 ,Off mode enable for etk_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for etk_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d6" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "CONTROL_PADCONF_ETK_D8,Configuration Register For Pads etk_d8; etk_d9"
|
|
bitfld.long 0x10 31. " WAKEUPEVENT1 ,Wake Up event for etk_d9" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 30. " WAKEUPENABLE1 ,Wake Up enable for etk_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for etk_d9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for etk_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " OFFOUTVALUE1 ,Off mode output value for etk_d9" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 26. " OFFOUTENABLE1 ,Off mode output enable for etk_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " OFFENABLE1 ,Off mode enable for etk_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for etk_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d9" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d9" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 15. " WAKEUPEVENT0 ,Wake Up event for etk_d8" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 14. " WAKEUPENABLE0 ,Wake Up enable for etk_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for etk_d8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for etk_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " OFFOUTVALUE0 ,Off mode output value for etk_d8" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 10. " OFFOUTENABLE0 ,Off mode output enable for etk_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " OFFENABLE0 ,Off mode enable for etk_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for etk_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d8" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CONTROL_PADCONF_ETK_D10,Configuration Register For Pads etk_d10; etk_d11"
|
|
bitfld.long 0x14 31. " WAKEUPEVENT1 ,Wake Up event for etk_d11" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 30. " WAKEUPENABLE1 ,Wake Up enable for etk_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for etk_d11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for etk_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " OFFOUTVALUE1 ,Off mode output value for etk_d11" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 26. " OFFOUTENABLE1 ,Off mode output enable for etk_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " OFFENABLE1 ,Off mode enable for etk_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for etk_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d11" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 15. " WAKEUPEVENT0 ,Wake Up event for etk_d10" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 14. " WAKEUPENABLE0 ,Wake Up enable for etk_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for etk_d10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for etk_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " OFFOUTVALUE0 ,Off mode output value for etk_d10" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 10. " OFFOUTENABLE0 ,Off mode output enable for etk_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " OFFENABLE0 ,Off mode enable for etk_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for etk_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d10" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "CONTROL_PADCONF_ETK_D12,Configuration Register For Pads etk_d12; etk_d13"
|
|
bitfld.long 0x18 31. " WAKEUPEVENT1 ,Wake Up event for etk_d13" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 30. " WAKEUPENABLE1 ,Wake Up enable for etk_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for etk_d13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for etk_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 27. " OFFOUTVALUE1 ,Off mode output value for etk_d13" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 26. " OFFOUTENABLE1 ,Off mode output enable for etk_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 25. " OFFENABLE1 ,Off mode enable for etk_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for etk_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d13" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d13" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 15. " WAKEUPEVENT0 ,Wake Up event for etk_d12" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 14. " WAKEUPENABLE0 ,Wake Up enable for etk_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for etk_d12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for etk_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " OFFOUTVALUE0 ,Off mode output value for etk_d12" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x18 10. " OFFOUTENABLE0 ,Off mode output enable for etk_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 9. " OFFENABLE0 ,Off mode enable for etk_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for etk_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d12" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "CONTROL_PADCONF_ETK_D14,Configuration Register For Pads etk_d14; etk_d15"
|
|
bitfld.long 0x1C 31. " WAKEUPEVENT1 ,Wake Up event for etk_d15" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x1C 30. " WAKEUPENABLE1 ,Wake Up enable for etk_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for etk_d15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for etk_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " OFFOUTVALUE1 ,Off mode output value for etk_d15" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 26. " OFFOUTENABLE1 ,Off mode output enable for etk_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " OFFENABLE1 ,Off mode enable for etk_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for etk_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for etk_d15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for etk_d15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--18. " MUXMODE1 ,Functional multiplexing selection for etk_d15" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " WAKEUPEVENT0 ,Wake Up event for etk_d14" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x1C 14. " WAKEUPENABLE0 ,Wake Up enable for etk_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for etk_d14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for etk_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " OFFOUTVALUE0 ,Off mode output value for etk_d14" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x1C 10. " OFFOUTENABLE0 ,Off mode output enable for etk_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " OFFENABLE0 ,Off mode enable for etk_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for etk_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for etk_d14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for etk_d14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0.--2. " MUXMODE0 ,Functional multiplexing selection for etk_d14" "0,1,2,3,4,5,6,7"
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width 0xb
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|
tree.end
|
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tree "GENERAL"
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|
base ad:0x48002270
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|
width 21.
|
|
group.long 0x00++0xF
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|
line.long 0x00 "CONTROL_PADCONF_OFF,Control register"
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|
bitfld.long 0x00 2. " WKUPCTRLCLOCKDIV ,Wkup_ctrl module clock divider" "Clk/4,Clk/2"
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textline " "
|
|
bitfld.long 0x00 1. " STARTSAVE ,Start pad configuration registers save mechanism" "Not started,Running"
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|
textline " "
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|
bitfld.long 0x00 0. " FORCEOFFMODEEN ,Force OFF mode active" "Not forced,Forced"
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line.long 0x04 "CONTROL_DEVCONF0,Static Device Configuration Register-0"
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|
bitfld.long 0x04 24. " MMCSDIO1ADPCLKISEL ,MMC/SDIO Module Input Clock selection" "External,Internal loop-back"
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|
textline " "
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|
bitfld.long 0x04 14. " ETMINTERFACEENABLE ,ETM interface control" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x04 6. " MCBSP2_CLKS ,Select the CLKS input for the module McBSP2" "PRCM clk,external McBSP_CLKS"
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|
textline " "
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bitfld.long 0x04 4. " MCBSP1_FSR ,Select the FSR input for the module McBSP1" "McBSP1_FSR,McBSP1_FSX"
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textline " "
|
|
bitfld.long 0x04 3. " MCBSP1_CLKR ,Select the CLKR input for the module McBSP1" "McBSP1_CLKR,McBSP1_CLKX"
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|
textline " "
|
|
bitfld.long 0x04 2. " MCBSP1_CLKS ,Select the CLKS input for the module McBSP1" "PRCM clk,external McBSP_CLKS"
|
|
textline " "
|
|
bitfld.long 0x04 1. " SENSDMAREQ1 ,Set sensitivity on SYS.DMAREQ1 input pin" "Level,Edge"
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|
textline " "
|
|
bitfld.long 0x04 0. " SENSDMAREQ0 ,Set sensitivity on SYS.DMAREQ0 input pin" "Level,Edge"
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|
line.long 0x08 "CONTROL_MEM_DFTRW0,DFT Read And Write Controls For Memory Blocks"
|
|
bitfld.long 0x08 15. " MEMORY4DFTGLXCTRL ,ETB memory DFT GLX ctrl" "0,1"
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|
textline " "
|
|
bitfld.long 0x08 14. " MEMORY3DFTGLXCTRL ,WKUP memory DFT GLX ctrl" "0,1"
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|
textline " "
|
|
bitfld.long 0x08 12.--13. " MEMORY2DFTWRITECTRL ,McBSP2 memory DFT write ctrl" "0,1,2,3"
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|
textline " "
|
|
bitfld.long 0x08 10.--11. " MEMORY2DFTREADCTRL ,McBSP2 memory DFT read ctrl" "0,1,2,3"
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|
textline " "
|
|
bitfld.long 0x08 7.--8. " MEMORY1DFTWRITECTRL ,IVA memory DFT write ctrl" "0,1,2,3"
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|
textline " "
|
|
bitfld.long 0x08 5.--6. " MEMORY1DFTREADCTRL ,IVA memory DFT read ctrl" "0,1,2,3"
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|
textline " "
|
|
bitfld.long 0x08 4. " MEMORY0DFTGLXCTRL ,SGX_ss memory DFT GLX ctrl" "0,1"
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|
textline " "
|
|
bitfld.long 0x08 2.--3. " MEMORY0DFTWRITECTRL ,SGX_ss memory DFT write ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " MEMORY0DFTREADCTRL ,SGX_ss memory DFT read ctrl" "0,1,2,3"
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line.long 0x0C "CONTROL_MEM_DFTRW1,DFT Read And Write Controls For Memory Blocks"
|
|
bitfld.long 0x0C 31. " DFTREADWRITEENABLE ,Control use of CONTROL_MEM_DFTRWx" "Test sub-system,CONTROL_MEM_DFTRWx"
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " MEMORY10DFTWRITECTRL ,DSI memory DFT write ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " MEMORY10DFTREADCTRL ,DSI memory DFT read ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 20.--21. " MEMORY9DFTWRITECTRL ,DISP_ss memory DFT write ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " MEMORY9DFTREADCTRL ,DISP_ss memory DFT read ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " MEMORY8DFTGLXCTRL ,ISP_ss memory DFT GLX ctrl" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 15.--16. " MEMORY8DFTWRITECTRL ,ISP_ss memory DFT write ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 13.--14. " MEMORY8DFTREADCTRL ,ISP_ss memory DFT read ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 11.--12. " MEMORY7DFTWRITECTRL ,MPU_ss memory DFT write ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 9.--10. " MEMORY7DFTREADCTRL ,MPU_ss memory DFT read ctrl" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " MEMORY6DFTGLXCTRL ,OCMRAM memory DFT GLX ctrl" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " MEMORY5DFTGLXCTRL ,USBHS memory DFT GLX ctrl" "0,1"
|
|
width 23.
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "CONTROL_MSUSPENDMUX_0,MSuspend Control Register"
|
|
bitfld.long 0x00 21.--23. " MCBSP2MSCTRL ,Control McBSP_2 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " MCBSP1MSCTRL ,Control McBSP_1 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " I2C2MSCTRL ,Control I2C_2 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " I2C1MSCTRL ,Control I2C_1 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " USIMOCPMSCTRL ,Control USIM OCP sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
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line.long 0x04 "CONTROL_MSUSPENDMUX_1,MSuspend Control Register"
|
|
bitfld.long 0x04 27.--29. " GPTM7MSCTRL ,Control General Purpose Timer 7 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x04 24.--26. " GPTM6MSCTRL ,Control General Purpose Timer 6 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x04 21.--23. " GPTM5MSCTRL ,Control General Purpose Timer 5 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x04 18.--20. " GPTM4MSCTRL ,Control General Purpose Timer 4 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " GPTM3MSCTRL ,Control General Purpose Timer 3 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " GPTM2MSCTRL ,Control General Purpose Timer 2 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " GPTM1MSCTRL ,Control General Purpose Timer 1 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
line.long 0x08 "CONTROL_MSUSPENDMUX_2,MSuspend Control Register"
|
|
bitfld.long 0x08 27.--29. " SYNCTMMSCTRL ,Control Sync Timer sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x08 21.--23. " WD3MSCTRL ,Control Watch Dog 4 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x08 18.--20. " WD2MSCTRL ,Control Watch Dog 2 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x08 15.--17. " WD1MSCTRL ,Control Watch Dog 1 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " GPTM12MSCTRL ,Control General Purpose Timer 12 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x08 9.--11. " GPTM11MSCTRL ,Control General Purpose Timer 11 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x08 6.--8. " GPTM10MSCTRL ,Control General Purpose Timer 10 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x08 3.--5. " GPTM9MSCTRL ,Control General Purpose Timer 9 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " GPTM8MSCTRL ,Control General Purpose Timer 8 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
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line.long 0x0C "CONTROL_MSUSPENDMUX_3,MSuspend Control Register"
|
|
bitfld.long 0x0C 27.--29. " SHA2MSCTRL ,Control SHA sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x0C 24.--26. " DES2MSCTRL ,Control DES3DES sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x0C 18.--20. " AES1MSCTRL ,Control AES sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x0C 15.--17. " RNGMSCTRL ,Control RNG sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--14. " SHA1MSCTRL ,Control SHA sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x0C 9.--11. " DES1MSCTRL ,Control DES3DES sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--2. " AES2MSCTRL ,Control AES sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
line.long 0x10 "CONTROL_MSUSPENDMUX_4,MSuspend Control Register"
|
|
bitfld.long 0x10 27.--29. " DMAMSCTRL ,Control DMA sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
line.long 0x14 "CONTROL_MSUSPENDMUX_5,MSuspend Control Register"
|
|
bitfld.long 0x14 21.--23. " I2C3MSCTRL ,Control I2C-3 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x14 6.--8. " MCBSP5MSCTRL ,Control McBSP-5 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x14 3.--5. " MCBSP4MSCTRL ,Control McBSP-4 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MCBSP3MSCTRL ,Control McBSP-3 sensitivity to MCU and/or DSP MSuspend signals" "No sensitivity,MCU,DSP,Logical ORed MCU/DSP,Logical ANDed MCU/DSP,No sensitivity,No sensitivity,No sensitivity"
|
|
width 22.
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "CONTROL_SEC_CTRL,Security Control Register"
|
|
bitfld.long 0x00 31. " SECCTRLWRDISABLE ,Security Control Register write disable control" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 30. " SECUREMODEINITDONE ,Used by SoftWare to indicate complete secure mode initialization" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x00 28.--29. " CORERAMSECURESAVE ,Used for indicating the nature of secure content save" "No content,Retention operation,Low Iddq operation,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " CPEFUSEDECODEDN ,Used for indicating the encoded state of the MSV and CEK" "Decoded,Not decoded"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CPEFUSEWRDISABLE ,Used to indicate if it is allowed to write in the SWEV" "Allowed,Not allowed"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CPEFUSEAUTOLOADDONE ,Used by SoftWare to indicate complete secure mode" "In progress,Done"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BSCDISABLED ,Control the use of BSC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMLEDSYSTEMENABLE ,Control the use of DMLED module" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " OBSERVABILITYDISABLE ,Control the observability feature" "Configured,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PADCONFACCDISABLE ,Control the write access to the pad configuration registers" "Unrestricted,Allowed in secure mode"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SECKEYACCENABLE ,Random Key and Customer Key and Test_key eFuse access control" "No access,Access"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WDREGENABLE ,Secure watchdog registers update access control" "Not allowed,Allowed in secure mode"
|
|
textline " "
|
|
bitfld.long 0x00 0. " WDOPDISABLE ,Secure Watchdog operation enable control" "Running,Frozen"
|
|
group.long 0x68++0x13
|
|
line.long 0x00 "CONTROL_DEVCONF1,Static Device Configuration Register 1"
|
|
bitfld.long 0x00 23. " SENSDMAREQ6 ,Set sensitivity on SYS.nDMAREQ6 input pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SENSDMAREQ5 ,Set sensitivity on SYS.nDMAREQ5 input pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SENSDMAREQ4 ,Set sensitivity on SYS.nDMAREQ4 input pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CARKITHSUSB0DATA1AUTOEN ,Enable force from HSUB0 DATA1 pad configuration MuxMode (MM) when CARKITEN is generated" "DATA1MM driven by DATA1CR,DATA1MM forced to 0x2"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CARKITHSUSB0DATA0AUTOEN ,Enable force from HSUB0 DATA0 pad configuration MuxMode when CARKITEN is generated" "DATA0MM driven by DATA1CR,DATA0MM forced to 0x2"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TVOUTBYPASS ,Active high enable Dual 10-bit video DAC TV out bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 14. " I2C3HSMASTER ,Active-high enable of I2C3 IO internal pull-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " I2C2HSMASTER ,Active-high enable of I2C2 IO internal pull-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " I2C1HSMASTER ,Active-high enable of I2C1 IO internal pull-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TVACEN ,TV AC coupled load enable for TV detection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MPUFORCEWRNP ,Force MPU writes to others to be non posted" "Posted,Not posted"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SENSDMAREQ3 ,Set sensitivity on SYS.nDMAREQ3 input pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SENSDMAREQ2 ,Set sensitivity on SYS.nDMAREQ2 input pin" "Level,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MMCSDIO2ADPCLKISEL ,MMC/SDIO2 Module Input Clock selection" "External,Internal loop-back"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MCBSP5_CLKS ,Select the CLKS input for the module McBSP5" "PRCM functional clk,external McBSP_CLKS"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MCBSP4_CLKS ,Select the CLKS input for the module McBSP4" "PRCM functional clk,external McBSP_CLKS"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCBSP3_CLKS ,Select the CLKS input for the module McBSP3" "PRCM functional clk,external McBSP_CLKS"
|
|
line.long 0x04 "CONTROL_CSIRXFE,CSIRXFE Cells Control Register"
|
|
bitfld.long 0x04 13. " CSIRXFE_RESETAZ2 ,Active Low asynchronous reset signal for CSIRXFE2" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 12. " CSIRXFE_PWRDNZ2 ,Power Down control for CSIRXFE2" "Normal,Power down"
|
|
textline " "
|
|
bitfld.long 0x04 10. " CSIRXFE_SELFORM2 ,CSI receiver transmission format selection for CSIRXFE2" "Transmission1,Transmission2"
|
|
textline " "
|
|
bitfld.long 0x04 8. " CSIRXFE_RESENABLE2 ,Enable resistor for CSIRXFE2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CSIRXFE_INV2 ,Strobe/Clock inversion control for CSIRXFE2" "Not inverted,Inverted"
|
|
line.long 0x08 "CONTROL_SEC_STATUS,Security Status Register"
|
|
bitfld.long 0x08 30. " MPUL2ISNOTACCESSIBLE ,L2 I;D$ accessible status" "Accessible,Not accessible"
|
|
textline " "
|
|
bitfld.long 0x08 28. " MPUL1ISNOTACCESSIBLE ,L1 I$ accessible status" "Accessible,Not accessible"
|
|
textline " "
|
|
bitfld.long 0x08 25. " COREBANK2ISNOTACCESSIBLE ,RAM Bank2 accessible status" "Accessible,Not accessible"
|
|
textline " "
|
|
bitfld.long 0x08 24. " COREBANK1ISNOTACCESSIBLE ,RAM Bank1 accessible status" "Accessible,Not accessible"
|
|
textline " "
|
|
bitfld.long 0x08 22. " MPUL2ISDESTROYED ,L2 I;D$ damage status" "Safe,Destroyed"
|
|
textline " "
|
|
bitfld.long 0x08 20. " MPUL1ISDESTROYED ,L1 I$ damage status" "Safe,Destroyed"
|
|
textline " "
|
|
bitfld.long 0x08 17. " COREBANK2ISDESTROYED ,RAM Bank2 damage status" "Safe,Destroyed"
|
|
textline " "
|
|
bitfld.long 0x08 16. " COREBANK1ISDESTROYED ,RAM Bank1 damage status" "Safe,Destroyed"
|
|
textline " "
|
|
bitfld.long 0x08 15. " USBHOSTWKUPRST ,USB Host Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 14. " NEONWKUPRST ,Neon Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 13. " STACKEDMODEMWKUPRST ,Stacked Modem Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 12. " IVA2WKUPRST ,IVA2 Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 11. " SGXWKUPRST ,SGX Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DISPWKUPRST ,Display Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CAMWKUPRST ,Camera Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 8. " PERWKUPRST ,Peripheral Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 7. " EMUWKUPRST ,Emulation Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 6. " COREWKUPRST ,Core Domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MPUWKUPRST ,MPU domain Reset Status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 4. " RAMBISTSTARTED ,RAM BIST Started status" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x08 3. " SECVIOLATIONRESET ,Security violation status" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SECWDRESET ,Secure watchdog reset status" "Not secure,Secure"
|
|
textline " "
|
|
bitfld.long 0x08 1. " GLOBALWARMRESET ,Global Warm Reset (GWR) status" "Not GWR,GWR"
|
|
textline " "
|
|
bitfld.long 0x08 0. " POWERONRESET ,Power On Reset status" "not PowerOn,PowerOn"
|
|
line.long 0x0C "CONTROL_SEC_ERR_STATUS,Security Error Status Register"
|
|
bitfld.long 0x0C 17. " L4EMUFWERROR ,L4 Emulation Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " L4PERIPHFWERROR ,L4 Peripheral Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " D2DFWERROR ,D2D Firewalll Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " SMXAPERTFWERROR ,L3 Register target Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " SECMODFWERROR ,Secure State Machine Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " DISPDMAACCERROR ,Disp Dma Access Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " CAMERADMAACCERROR ,Camera Dma Access Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " SYSDMAACCERROR ,sDma Access Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " L4COREFWERROR ,L4 Security Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " IVA2FWERROR ,IVA2 Security Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " MAD2DFWERROR ,MAD2D Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " SMSFWERROR ,SMS Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " SMSFUNCFWERROR ,SMS Functional Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " GPMCFWERROR ,GPMC Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " OCMRAMFWERROR ,On Chip Ram Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " OCMROMFWERROR ,On Chip Rom Firewall Error" "No error,Error"
|
|
width 30.
|
|
line.long 0x10 "CONTROL_SEC_ERR_STATUS_DEBUG,Security Error Status Debug Register"
|
|
bitfld.long 0x10 17. " L4EMUDBGFWERROR ,L4 Emulation Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x10 16. " L4PERIPHERALDBGFWERROR ,L4 Peripheral Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x10 12. " SMXAPERTDBGFWERROR ,L3 Register target Debug Firewall error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x10 7. " L4COREDBGFWERROR ,L4 Core Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x10 6. " IVA2DBGFWERROR ,IVA2 Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x10 5. " MAD2D2DBGFWERROR ,MAD2D Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x10 3. " SMSDBGFWERROR ,SMS Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x10 2. " GPMCDBGFWERROR ,GPMC Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x10 1. " OCMRAMDBGFWERROR ,On Chip Ram Debug Firewall Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x10 0. " OCMROMDBGFWERROR ,On Chip Rom Debug Firewall Error" "No error,Error"
|
|
rgroup.long 0x80++0x7
|
|
line.long 0x00 "CONTROL_STATUS,Control Module Status Register"
|
|
bitfld.long 0x00 8.--10. " DEVICETYPE ,Device Type captured at reset time" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SYSBOOT_5 ,Sys.Boot pin values sampled at power-on reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SYSBOOT_4 ,Sys.Boot pin values sampled at power-on reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYSBOOT_3 ,Sys.Boot pin values sampled at power-on reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYSBOOT_2 ,Sys.Boot pin values sampled at power-on reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SYSBOOT_1 ,Sys.Boot pin values sampled at power-on reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SYSBOOT_0 ,Sys.Boot pin values sampled at power-on reset" "No reset,Reset"
|
|
line.long 0x04 "CONTROL_GENERAL_PURPOSE_STATUS,Status bits reflecting chip internal states"
|
|
bitfld.long 0x04 31. " RNGIDLE ,RNGIdle output from the RNG module" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 0. " SAVEDONE ,Pad configuration save status" "Not saved,Saved"
|
|
width 24.
|
|
rgroup.long 0x90++0x13
|
|
line.long 0x00 "CONTROL_RPUB_KEY_H_0,Root Public Key Hash Bits[31:0] Fuse Keys [31:0]"
|
|
line.long 0x04 "CONTROL_RPUB_KEY_H_1,Root Public Key Hash Bits[63:32] Fuse Keys [62:32]"
|
|
line.long 0x08 "CONTROL_RPUB_KEY_H_2,Root Public Key Hash Bits[95:64] Fuse Keys [95:64]"
|
|
line.long 0x0c "CONTROL_RPUB_KEY_H_3,Root Public Key Hash Bits[127:96] Fuse Keys [127:96]"
|
|
line.long 0x10 "CONTROL_RPUB_KEY_H_4,Random Key bits[159:128] Fuse Keys [159:128]"
|
|
rgroup.long 0xA8++0x1F
|
|
line.long 0x00 "CONTROL_RAND_KEY_0,Random Key bits[31:0] Fuse Keys [223:192]"
|
|
line.long 0x04 "CONTROL_RAND_KEY_1,Random Key bits[63:32] Fuse Keys [255:224]"
|
|
line.long 0x08 "CONTROL_RAND_KEY_2,Random Key bits[95:64] Fuse Keys [287:256]"
|
|
line.long 0x0C "CONTROL_RAND_KEY_3,Random Key bits[127:96] Fuse Keys [319:288]"
|
|
line.long 0x10 "CONTROL_CUST_KEY_0,Customer Key bits[31:0] Fuse Keys [351:320]"
|
|
line.long 0x14 "CONTROL_CUST_KEY_1,Customer Key bits[63:32] Fuse Keys [383:352]"
|
|
line.long 0x18 "CONTROL_CUST_KEY_2,Customer Key bits[95:64] Fuse Keys [415:384]"
|
|
line.long 0x1C "CONTROL_CUST_KEY_3,Customer Key bits[127:96] Fuse Keys [447:416]"
|
|
rgroup.long 0x100++0x7
|
|
line.long 0x00 "CONTROL_USB_CONF_0,USB Fuse conf [31:0] USB Product ID [31:16] Vendor ID [15:0]"
|
|
line.long 0x04 "CONTROL_USB_CONF_1,USB Fuse conf [63:32] SEQ_DISADAPTCLK[1] USB PHY Detection Mode [0]"
|
|
rgroup.long 0x110++0x67
|
|
line.long 0x00 "CONTROL_FUSE_OPP1_VDD1,Fuse OPP [95:72]"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " FUSE_OPP_95_72 ,Fuse OPP [95:72]"
|
|
line.long 0x04 "CONTROL_FUSE_OPP2_VDD1,Fuse OPP [119:96]"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " FUSE_OPP_119_96 ,Fuse OPP [119:96]"
|
|
line.long 0x08 "CONTROL_FUSE_OPP3_VDD1,Fuse OPP [143:120]"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " FUSE_OPP_143_120 ,Fuse OPP [143:120]"
|
|
line.long 0x0C "CONTROL_FUSE_OPP4_VDD1,Fuse OPP [167:144]"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " FUSE_OPP_167_144 ,Fuse OPP [167:144]"
|
|
line.long 0x10 "CONTROL_FUSE_OPP5_VDD1,Fuse OPP [191:168]"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " FUSE_OPP_191_168 ,Fuse OPP [191:168]"
|
|
line.long 0x14 "CONTROL_FUSE_OPP1_VDD2,Fuse OPP [23:0]"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " FUSE_OPP_23_0 ,Fuse OPP [23:0]"
|
|
line.long 0x18 "CONTROL_FUSE_OPP2_VDD2,Fuse OPP [47:24]"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " FUSE_OPP_24_47 ,Fuse OPP [47:24]"
|
|
line.long 0x1C "CONTROL_FUSE_OPP3_VDD2,Fuse OPP [63:48]"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. " FUSE_OPP_63_48 ,Fuse OPP [63:48]"
|
|
line.long 0x20 "CONTROL_FUSE_SR,Fuse SR1 and SR2"
|
|
hexmask.long.byte 0x20 8.--15. 1. " FUSE_SR2 ,Fuse SR 2"
|
|
textline " "
|
|
hexmask.long.byte 0x20 0.--7. 1. " FUSE_SR1 ,Fuse SR 1"
|
|
line.long 0x24 "CONTROL_CEK_0,Customer Key [31:0]"
|
|
line.long 0x28 "CONTROL_CEK_1,Customer Key [63:32]"
|
|
line.long 0x2C "CONTROL_CEK_2,Customer Key [95:64]"
|
|
line.long 0x30 "CONTROL_CEK_3,Customer Key [127:96]"
|
|
line.long 0x34 "CONTROL_MSV_0,Model specific value [31:0]"
|
|
line.long 0x38 "CONTROL_CEK_BCH_0,Cpefuse CEK (BCH Decoded) [31:0]"
|
|
line.long 0x3C "CONTROL_CEK_BCH_1,Cpefuse CEK (BCH Decoded) [63:32]"
|
|
line.long 0x40 "CONTROL_CEK_BCH_2,Cpefuse CEK (BCH Decoded) [95:64]"
|
|
line.long 0x44 "CONTROL_CEK_BCH_3,Cpefuse CEK (BCH Decoded) [127:96]"
|
|
line.long 0x48 "CONTROL_CEK_BCH_4,Cpefuse CEK (BCH Decoded) [143:128]"
|
|
line.long 0x4C "CONTROL_MSV_BCH_0,Cpefuse MSV (BCH Decoded) [31:0]"
|
|
line.long 0x50 "CONTROL_MSV_BCH_1,Cpefuse MSV (BCH Decoded) [63:32]"
|
|
line.long 0x54 "CONTROL_SWRV_0,Software revision value [31:0]"
|
|
line.long 0x58 "CONTROL_SWRV_1,Software revision value [63:32]"
|
|
line.long 0x5C "CONTROL_SWRV_2,Software revision value [95:64]"
|
|
line.long 0x60 "CONTROL_SWRV_3,Software revision value [127:96]"
|
|
line.long 0x64 "CONTROL_SWRV_4,Software revision value [159:128]"
|
|
group.long 0x190++0x7
|
|
line.long 0x00 "CONTROL_IVA2_BOOTADDR,Physical Address Of The IVA2 Boot Loader"
|
|
hexmask.long 0x00 10.--31. 0x400 " BOOTLOADADDR ,Physical Address of the IVA2 boot loader"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " BOOTREVID ,IVA2 boot code revision ID"
|
|
line.long 0x04 "CONTROL_IVA2_BOOTMOD,Boot Mode Of The IVA2"
|
|
bitfld.long 0x04 0.--3. " BOOTMODE ,Boot mode of the IVA2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1B0++0x23
|
|
line.long 0x0 "CONTROL_DEBOBS_0,Set Of Signals To Be Observed For hw_dbg1 and hw_dbg0"
|
|
hexmask.long.byte 0x0 16.--22. 1. " OBSMUX1 ,Select the set of signals to be exported for WKUPOBSMUX1"
|
|
textline " "
|
|
hexmask.long.byte 0x0 0.--6. 1. " OBSMUX0 ,Select the set of signals to be exported for WKUPOBSMUX0"
|
|
line.long 0x4 "CONTROL_DEBOBS_1,Set Of Signals To Be Observed For hw_dbg3 and hw_dbg2"
|
|
hexmask.long.byte 0x4 16.--22. 1. " OBSMUX3 ,Select the set of signals to be exported for WKUPOBSMUX3"
|
|
textline " "
|
|
hexmask.long.byte 0x4 0.--6. 1. " OBSMUX2 ,Select the set of signals to be exported for WKUPOBSMUX2"
|
|
line.long 0x8 "CONTROL_DEBOBS_2,Set Of Signals To Be Observed For hw_dbg5 and hw_dbg4"
|
|
hexmask.long.byte 0x8 16.--22. 1. " OBSMUX5 ,Select the set of signals to be exported for WKUPOBSMUX5"
|
|
textline " "
|
|
hexmask.long.byte 0x8 0.--6. 1. " OBSMUX4 ,Select the set of signals to be exported for WKUPOBSMUX4"
|
|
line.long 0xC "CONTROL_DEBOBS_3,Set Of Signals To Be Observed For hw_dbg7 and hw_dbg6"
|
|
hexmask.long.byte 0xC 16.--22. 1. " OBSMUX7 ,Select the set of signals to be exported for WKUPOBSMUX7"
|
|
textline " "
|
|
hexmask.long.byte 0xC 0.--6. 1. " OBSMUX6 ,Select the set of signals to be exported for WKUPOBSMUX6"
|
|
line.long 0x10 "CONTROL_DEBOBS_4,Set Of Signals To Be Observed For hw_dbg9 and hw_dbg8"
|
|
hexmask.long.byte 0x10 16.--22. 1. " OBSMUX9 ,Select the set of signals to be exported for WKUPOBSMUX9"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--6. 1. " OBSMUX8 ,Select the set of signals to be exported for WKUPOBSMUX8"
|
|
line.long 0x14 "CONTROL_DEBOBS_5,Set Of Signals To Be Observed For hw_dbg11 and hw_dbg10"
|
|
hexmask.long.byte 0x14 16.--22. 1. " OBSMUX11 ,Select the set of signals to be exported for WKUPOBSMUX11"
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--6. 1. " OBSMUX10 ,Select the set of signals to be exported for WKUPOBSMUX10"
|
|
line.long 0x18 "CONTROL_DEBOBS_6,Set Of Signals To Be Observed For hw_dbg14 and hw_dbg13"
|
|
hexmask.long.byte 0x18 16.--22. 1. " OBSMUX14 ,Select the set of signals to be exported for WKUPOBSMUX14"
|
|
textline " "
|
|
hexmask.long.byte 0x18 0.--6. 1. " OBSMUX13 ,Select the set of signals to be exported for WKUPOBSMUX13"
|
|
line.long 0x1C "CONTROL_DEBOBS_7,Set Of Signals To Be Observed For hw_dbg16 and hw_dbg15"
|
|
hexmask.long.byte 0x1C 16.--22. 1. " OBSMUX16 ,Select the set of signals to be exported for WKUPOBSMUX16"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--6. 1. " OBSMUX15 ,Select the set of signals to be exported for WKUPOBSMUX15"
|
|
line.long 0x20 "CONTROL_DEBOBS_8,Set Of Signals To Be Observed For hw_dbg18 and hw_dbg17"
|
|
hexmask.long.byte 0x20 16.--22. 1. " OBSMUX18 ,Select the set of signals to be exported for WKUPOBSMUX18"
|
|
textline " "
|
|
hexmask.long.byte 0x20 0.--6. 1. " OBSMUX17 ,Select the set of signals to be exported for WKUPOBSMUX17"
|
|
group.long 0x1D4++0x7
|
|
line.long 0x00 "CONTROL_PROG_IO0,Configure Drive Strength Of IO Cells"
|
|
bitfld.long 0x00 31. " SDRC_LOWDATA ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 30. " SDRC_HIGHDATA ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 29. " SDRC_ADDRCTR ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 28. " SDRC_CS0 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SDRC_NCS1 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 26. " GPMC_A1 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 25. " GPMC_A2 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 24. " GPMC_A3 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 23. " GPMC_A4 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 22. " GPMC_A5 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 21. " GPMC_A6 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 20. " GPMC_A7 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GPMC_A8 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 18. " GPMC_A9 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 17. " GPMC_A10 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 16. " GPMC_MIN_CFG ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GPMC_D8_D15 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 14. " GPMC_NCS0 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GPMC_NCS1 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 12. " GPMC_NCS2 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 11. " GPMC_NCS3 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 10. " GPMC_NCS4 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GPMC_NCS5 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GPMC_NCS6 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GPMC_NCS7 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 6. " GPMC_CLK ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 5. " GPMC_NBE0_CLE ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GPMC_NBE1 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 3. " GPMC_NWP ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 2. " GPMC_WAIT1 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 1. " GPMC_WAIT2 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GPMC_WAIT3 ,Drive strength for output load" "Low 2-6 pF,High 6-12 pF"
|
|
line.long 0x04 "CONTROL_PROG_IO1,Configure Drive Strength Of IO Cells"
|
|
bitfld.long 0x04 16.--17. " DSS_MIN_CTL ,Drive strength for impedance and current output" "20 Ohm/8 mA,25 Ohm/6 mA,40 Ohm/4 mA,65 Ohm/2 mA"
|
|
textline " "
|
|
bitfld.long 0x04 14.--15. " DSS_D8 ,Drive strength for impedance and current output" "20 Ohm/8 mA,25 Ohm/6 mA,40 Ohm/4 mA,65 Ohm/2 mA"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " DSS_D9 ,Drive strength for impedance and current output" "20 Ohm/8 mA,25 Ohm/6 mA,40 Ohm/4 mA,65 Ohm/2 mA"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " DSS_D16_D17 ,Drive strength for impedance and current output" "20 Ohm/8 mA,25 Ohm/6 mA,40 Ohm/4 mA,65 Ohm/2 mA"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " DSS_D18_D21 ,Drive strength for impedance and current output" "20 Ohm/8 mA,25 Ohm/6 mA,40 Ohm/4 mA,65 Ohm/2 mA"
|
|
textline " "
|
|
bitfld.long 0x04 6.--7. " MCBSP2_CONF ,Drive strength for impedance and current output" "20 Ohm/8 mA,25 Ohm/6 mA,40 Ohm/4 mA,65 Ohm/2 mA"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " MCSPI1_MIN_CTRL ,Drive strength for impedance and current output" "20 Ohm/8 mA,25 Ohm/6 mA,40 Ohm/4 mA,65 Ohm/2 mA"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " MCSP1_CS1 ,Drive strength for impedance and current output" "20 Ohm/8 mA,25 Ohm/6 mA,40 Ohm/4 mA,65 Ohm/2 mA"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " MCSP1_CS2 ,Drive strength for impedance and current output" "20 Ohm/8 mA,25 Ohm/6 mA,40 Ohm/4 mA,65 Ohm/2 mA"
|
|
width 32.
|
|
group.long 0x1E0++0x3
|
|
line.long 0x00 "CONTROL_DSS_DPLL_SPREADING,EMI Reduction Feature For Display_SS/DSI DPLL Control"
|
|
bitfld.long 0x00 7. " DSS_SPREADING_ENABLE_STATUS ,Indicates the status of the SSC feature" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DSS_SPREADING_ENABLE ,Enables/disables EMI Reduction feature (Spreading)" "Stops at end,Started"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " DSS_SPREADING_AMPLITUDE ,Controls the modulation index" "K=4,K=6,K=8,K=10"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " DSS_SPREADING_RATE ,Controls the rate of frequency modulation" "62.5-125 KHz,125-250 KHz,250-500 KHz,500-1000 KHz"
|
|
group.long 0x454++0xB
|
|
line.long 0x00 "CONTROL_CORE_DPLL_SPREADING,EMI Reduction Feature For Display_SS/DSI DPLL Control"
|
|
bitfld.long 0x00 7. " CORE_SPREADING_ENABLE_STATUS ,Indicates the status of the SSC feature" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CORE_SPREADING_ENABLE ,Enables/disables EMI Reduction feature (Spreading)" "Stops at end,Started"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CORE_SPREADING_AMPLITUDE ,Controls the modulation index" "K=4,K=6,K=8,K=10"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CORE_SPREADING_RATE ,Controls the rate of frequency modulation" "62.5-125 KHz,125-250 KHz,250-500 KHz,500-1000 KHz"
|
|
line.long 0x04 "CONTROL_PER_DPLL_SPREADING,EMI Reduction Feature For Display_SS/DSI DPLL Control"
|
|
bitfld.long 0x04 7. " PER_SPREADING_ENABLE_STATUS ,Indicates the status of the SSC feature" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PER_SPREADING_ENABLE ,Enables/disables EMI Reduction feature (Spreading)" "Stops at end,Started"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " PER_SPREADING_AMPLITUDE ,Controls the modulation index" "K=4,K=6,K=8,K=10"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " PER_SPREADING_RATE ,Controls the rate of frequency modulation" "62.5-125 KHz,125-250 KHz,250-500 KHz,500-1000 KHz"
|
|
line.long 0x08 "CONTROL_USBHOST_DPLL_SPREADING,EMI Reduction Feature For Display_SS/DSI DPLL Control"
|
|
bitfld.long 0x08 7. " USBHOST_SPREADING_ENABLE_STATUS ,Indicates the status of the SSC feature" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 4. " USBHOST_SPREADING_ENABLE ,Enables/disables EMI Reduction feature (Spreading)" "Stops at end,Started"
|
|
textline " "
|
|
bitfld.long 0x08 2.--3. " USBHOST_SPREADING_AMPLITUDE ,Controls the modulation index" "K=4,K=6,K=8,K=10"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " USBHOST_SPREADING_RATE ,Controls the rate of frequency modulation" "62.5-125 KHz,125-250 KHz,250-500 KHz,500-1000 KHz"
|
|
group.long 0x1F0++0x33
|
|
line.long 0x00 "CONTROL_SECURE_SDRC_SHARING,SDRC Sharing Configuration Register"
|
|
bitfld.long 0x00 31. " SECURESDRCSHARINGWRDISABLE ,SecureSdrcSharingWrDisable Register write disable control" "Allowed,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 30. " SECURESDRCSHARINGLOCK ,Exported value to SDRC.SDRC_SHARING[30]" "Low,High"
|
|
textline " "
|
|
hexmask.long 0x00 0.--29. 1. " SECURESDRCSHARING ,Exported value to SDRC.SDRC_SHARING[29:0]"
|
|
line.long 0x04 "CONTROL_SECURE_SDRC_MCFG0,SDRC MCFG Configuration Register 0"
|
|
bitfld.long 0x04 31. " SECURESDRCMCFG0WRDISABLE ,SECURE_SDRC_MCFG0 Register write disable control" "Allowed,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x04 30. " SECURESDRCMCFG0LOCK ,Exported value to SDRC.SDRC_MCFG_0[30]" "Low,High"
|
|
textline " "
|
|
hexmask.long 0x04 0.--29. 1. " SECURESDRCMCFG0 ,Exported value to SDRC.SDRC_MCFG_0[29:0]"
|
|
line.long 0x08 "CONTROL_SECURE_SDRC_MCFG1,SDRC MCFG Configuration Register 1"
|
|
bitfld.long 0x08 31. " SECURESDRCMCFG1WRDISABLE ,SECURE_SDRC_MCFG1 Register write disable control" "Allowed,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x08 30. " SECURESDRCMCFG1LOCK ,Exported value to SDRC.SDRC_MCFG_1[30]" "Low,High"
|
|
textline " "
|
|
hexmask.long 0x08 0.--29. 1. " SECURESDRCMCFG1 ,Exported value to SDRC.SDRC_MCFG_1[29:0]"
|
|
width 40.
|
|
line.long 0x0C "CONTROL_MODEM_FW_CONFIGURATION_LOCK,Locking The Configuration Of All The Firewall Configuration Registers"
|
|
bitfld.long 0x0C 0. " FWCONFIGURATIONLOCK ,FW configuration" "Not accessed,Accessed"
|
|
line.long 0x10 "CONTROL_MODEM_MEMORY_RESOURCES_CONF,Modem Memory Resources Conf"
|
|
bitfld.long 0x10 31. " CMDWTOCMRAMSWITCH ,Select if CMDWT or OCMRAM is accessible by the Modem" "CMDWT,OCMRAM"
|
|
textline " "
|
|
hexmask.long.byte 0x10 27.--30. 1. " MODEMSTACKMEMORYSIZE ,Configuration of the modem stack memory size"
|
|
textline " "
|
|
hexmask.long.byte 0x10 22.--26. 1. " MODEMSMSMEMORYSIZE ,Configuration of the SMS modem memory section size"
|
|
textline " "
|
|
hexmask.long.byte 0x10 17.--21. 1. " MODEMGPMCRESERVEDS2SIZE ,Configuration of the GPMC modem shared section size"
|
|
textline " "
|
|
hexmask.long.byte 0x10 12.--16. 1. " MODEMGPMCRESERVEDS1SIZE ,Configuration of the GPMC modem reserved section size"
|
|
textline " "
|
|
hexmask.long.word 0x10 0.--11. 1. " MODEMGPMCRESERVEDBASEADDR ,Configuration of the GPMC base address"
|
|
line.long 0x14 "CONTROL_MODEM_GPMC_DT_FW_REQ_INFO,Modem GPMC Default Firewall Request Info Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " MODEMGPMCDTFWREQINFO ,Exported values to the GPMC firewall region1 REQ_INFO_PERMISSION field"
|
|
line.long 0x18 "CONTROL_MODEM_GPMC_DT_FW_RD,Modem GPMC Default Firewall Control Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " MODEMGPMCDTFWRD ,Exported values to the GPMC firewall region1 READ_PERMISSION field"
|
|
line.long 0x1c "CONTROL_MODEM_GPMC_DT_FW_WR,Modem GPMC Default Firewall Control Register"
|
|
hexmask.long.word 0x1c 0.--15. 1. " MODEMGPMCDTFWWR ,Exported values to the GPMC firewall region1 WRITE_PERMISSION field"
|
|
line.long 0x20 "CONTROL_MODEM_GPMC_BOOT_CODE,GPMC Flash Boot Code Protection Register"
|
|
bitfld.long 0x20 5. " GPMCBOOTCODEWRITEPROTECTED ,Flash Boot Code area write protection" "Not protected,Protected"
|
|
textline " "
|
|
hexmask.long.byte 0x20 0.--4. 1. " GPMCBOOTCODESIZE ,Size of the Flash boot code to protect"
|
|
line.long 0x24 "CONTROL_MODEM_SMS_RG_ATT1,Exported Values To The SMS Firewall Region1 SMS_RG_ATT1 Field"
|
|
line.long 0x28 "CONTROL_MODEM_SMS_RG_RDPERM1,Modem SMS Control Register"
|
|
hexmask.long.word 0x28 0.--15. 1. " SMSRGRDPERM1 ,Exported values to the SMS firewall region1 SMS_RG_RDPERM1 field"
|
|
line.long 0x2c "CONTROL_MODEM_SMS_RG_WRPERM1,Modem SMS Control Register"
|
|
hexmask.long.word 0x2c 0.--15. 1. " SMSRGWRPERM1 ,Exported values to the SMS firewall region1 SMS_RG_WRPERM1 field"
|
|
line.long 0x30 "CONTROL_MODEM_D2D_FW_DEBUG_MODE,Modem D2D Control Register"
|
|
bitfld.long 0x30 0. " D2DFWDEBUGMODE ,SMX-D2D FW debug mode" "No debug,Debug"
|
|
group.long 0x228++0xB
|
|
line.long 0x00 "CONTROL_DPF_OCM_RAM_FW_ADDR_MATCH,OCM RAM Dynamic Power Framework Handing"
|
|
hexmask.long.tbyte 0x00 0.--19. 1. " REGIONOCMRAMFWADDRMATCH ,Refer to SMX FW addr_match field"
|
|
line.long 0x04 "CONTROL_DPF_OCM_RAM_FW_REQINFO,OCM RAM Dynamic Power Framework Handing"
|
|
hexmask.long.word 0x04 0.--15. 1. " REGIONOCMRAMFWREQINFO ,Refer to SMX FW REQINFO permission field"
|
|
line.long 0x08 "CONTROL_DPF_OCM_RAM_FW_WR,OCM RAM Dynamic Power Framework Handing"
|
|
hexmask.long.word 0x08 0.--15. 1. " REGIONOCMRAMFWWR ,Refer to SMX FW WR permission field"
|
|
group.long 0x234++0x17
|
|
line.long 0x00 "CONTROL_DPF_REGION4_GPMC_FW_ADDR_MATCH,Dfp Region4 Control Register"
|
|
hexmask.long 0x00 0.--29. 1. " REGION4GPMCFWADDRMATCH ,Exported value to SMX FW region 4"
|
|
line.long 0x04 "CONTROL_DPF_REGION4_GPMC_FW_REQINFO,Dfp Region4 Control Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " REGION4GPMCFWREQINFO ,Exported value to SMX FW region 4 GPMC REQINFO_PERMISSION_4 field"
|
|
line.long 0x08 "CONTROL_DPF_REGION4_GPMC_FW_WR,Dfp Region4 Control Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " REGION4GPMCFWWR ,Exported value to SMX FW region 4 GPMC WRITE_PERMISSION_4 field"
|
|
line.long 0x0c "CONTROL_DPF_REGION1_IVA2_FW_ADDR_MATCH,Dpf Region 1 IVA2 Control Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " REGION1IVA2FWADDRMATCH ,Exported value to SMX FW region 1"
|
|
line.long 0x10 "CONTROL_DPF_REGION1_IVA2_FW_REQINFO,Dpf Region 1 IVA2 Control Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " REGION1IVA2FWREQINFO ,Exported value to SMX FW region 1 IVA2 REQINFO_PERMISSION_1 field"
|
|
line.long 0x14 "CONTROL_DPF_REGION1_IVA2_FW_WR,Dpf Region 1 IVA2 Control Register"
|
|
hexmask.long.word 0x14 0.--12. 1. " REGION1IVA2FWWR ,Exported value to SMX FW region 1 IVA2 WRITE_PERMISSION_1 field"
|
|
group.long 0x2C8++0xB
|
|
line.long 0x00 "CONTROL_DPF_MAD2D_FW_ADDR_MATCH,MAD2D Dynamic Power Framework Handing"
|
|
hexmask.long.word 0x00 0.--15. 1. " REGIONMAD2DFWWR ,Refer to SMX FW WR permission field"
|
|
line.long 0x04 "CONTROL_DPF_MAD2D_FW_REQINFO,MAD2D Dynamic Power Framework Handing"
|
|
hexmask.long.word 0x04 0.--15. 1. " MAD2DFWREQINFO ,Refer to SMX FW REQINFO permission field"
|
|
line.long 0x08 "CONTROL_DPF_MAD2D_FW_WR,MAD2D Dynamic Power Framework Handing"
|
|
hexmask.long.word 0x08 0.--15. 1. " REGIONMAD2DFWWR ,Refer to SMX FW WR permission field"
|
|
group.long 0x24C++0xB
|
|
line.long 0x00 "CONTROL_APE_FW_DEFAULT_SECURE_LOCK,Firewall Security Lock Features Control Register"
|
|
bitfld.long 0x00 28. " L4TIMERDEFAULTDEBUGLOCK ,TIMER12 debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 27. " L4CAMDEFAULTDEBUGLOCK ,CAMERA debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 26. " L4DISPDEFAULTDEBUGLOCK ,DISPLAY debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 25. " L4CRYPTODEFAULTDEBUGLOCK ,CRYPTO debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 24. " L4COREAPDEFAULTDEBUGLOCK ,L4 CORE AP debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 20. " L4TIMERDEFAULTSECURELOCK ,TIMER12 secure" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 19. " L4CAMDEFAULTSECURELOCK ,CAMERA secure" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 18. " L4DISPDEFAULTSECURELOCK ,DISPLAY secure" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 17. " L4CRYPTODEFAULTSECURELOCK ,CRYPTO secure" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 16. " L4COREAPDEFAULTSECURELOCK ,L4 CORE AP secure" "Not secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 12. " MAD2DDEFAULTDEBUGLOCK ,MAD2D debug after next SMX-APE reset" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SMSDEFAULTDEBUGLOCK ,SMS debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OCMRAMDEFAULTDEBUGLOCK ,OCM-RAM debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IVA2DEFAULTDEBUGLOCK ,IVA2 debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 8. " GPMCDEFAULTDEBUGLOCK ,GPMC debug" "No debug,Debug"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MAD2DDEFAULTSECURELOCK ,MAD2D public" "Not public,Public"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SMSDEFAULTSECURELOCK ,SMS public" "Not public,Public"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OCMRAMDEFAULTSECURELOCK ,OCM-RAM public" "Not public,Public"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IVA2DEFAULTSECURELOCK ,IVA2 public" "Not public,Public"
|
|
textline " "
|
|
bitfld.long 0x00 0. " GPMCDEFAULTSECURELOCK ,GPMC public" "Not public,Public"
|
|
line.long 0x04 "CONTROL_OCMROM_SECURE_DEBUG,Secure ROM Code Debug Configuration Register"
|
|
bitfld.long 0x04 0. " OCMROMSECUREDEBUG ,Secure ROM access for debug puproses" "Not granted,Granted"
|
|
line.long 0x08 "CONTROL_D2D_FW_STACKED_DEVICE_SEC_DEBUG,D2D Stacked Device Debug Control Register"
|
|
eventfld.long 0x08 1. " D2DDSPIRQ ,IRQ is sent to the D2D Stacked Device DSP component" "Not sent,Sent"
|
|
textline " "
|
|
eventfld.long 0x08 0. " D2DMPUIRQ ,IRQ is sent to the D2D Stacked Device MPU component" "Not sent,Sent"
|
|
group.long 0x264++0x7
|
|
line.long 0x00 "CONTROL_EXT_SEC_CONTROL,EXT SEC Control Register"
|
|
bitfld.long 0x00 2. " I2CSENABLE ,I2C module access control" "Unrestricted,Allowed in Secure Mode"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CCSECURITYDISABLE ,Companion Chip Security Control" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SECUREEXECINDICATOR ,Secure Execution Indicator" "Reset,Set"
|
|
line.long 0x04 "CONTROL_D2D_FW_STACKED_DEVICE_SECURITY,D2D Stacked Device Security Control Register"
|
|
eventfld.long 0x04 1. " SD2DRESETD2DDEVICERELEASE ,SD2D reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 0. " D2DAPEMPUIRQ , To ARM11 component IRQ sent" "Not sent,Sent"
|
|
width 21.
|
|
group.long 0x2B0++0x13
|
|
line.long 0x00 "CONTROL_PBIAS_LITE,Settings For PBIAS LITE/MMC/SD/SDIO1 Pins Control"
|
|
bitfld.long 0x00 15. " PBIASLITESUPPLYHIGH1 ,USIMPBIAS supplied by 1.8V or 3.0V VDDS" "1.8V,3.0V"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PBIASLITEVMODEERROR1 ,VMODE level matches with SUPPLY_HI output signal" "Match,Not match"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PBIASSPEEDCTRL1 ,Speed Control for MMC I/O" "26 MHz,52 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PBIASLITEPWRDNZ1 ,Input Signal Referenced to VDD" "Ramping up,Stable"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PBIASLITEVMODE1 ,VDDS voltage level information control from software" "1.8V,3.0V"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PBIASLITESUPPLYHIGH0 ,Status indicating if MMC/SD/SDIO1 PBIAS is supplied by 1.8 V or 3.0 V VDDS" "1.8V,3.0V"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PBIASLITEVMODEERROR0 ,VMODE level matches with SUPPLY_HI output signal" "Match,Not match"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBIASSPEEDCTRL0 ,Speed Control for MMC I/O" "26 MHz,52 MHz"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PBIASLITEPWRDNZ0 ,Input Signal Referenced to VDD" "VDDS ramping up,VDDS stable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PBIASLITEVMODE0 ,VDDS voltage level information control from software" "1.8V,3.0V"
|
|
line.long 0x04 "CONTROL_TEMP_SENSOR,Temp Sensor Control Register"
|
|
bitfld.long 0x04 9. " CONTCONV ,VDD level digital inputs (ADC Converion Mode)" "Single,Continuous"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SOC ,ADC Start of Conversion" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x04 7. " EOCZ ,ADC End of Conversion" "Valid,End"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--6. 1. " TEMP ,Temperature data from the ADC"
|
|
line.long 0x08 "CONTROL_SRAMLDO4,Control SRAMLDO4 Voltage Setting"
|
|
bitfld.long 0x08 31. " RET_MUX_CTRL ,Override Retention Mode VSET Fuse" "No override,Override"
|
|
textline " "
|
|
hexmask.long.byte 0x08 24.--28. 1. " RET_VSET_EFUSE ,Retention mode Fuse value"
|
|
textline " "
|
|
hexmask.long.byte 0x08 16.--20. 1. " RET_VSET_OUT ,Retention Mode voltage control"
|
|
line.long 0x0C "CONTROL_SRAMLDO5,Control SRAMLDO5 Voltage Setting"
|
|
bitfld.long 0x0c 31. " RET_MUX_CTRL ,Override Retention Mode VSET Fuse" "No override,Override"
|
|
textline " "
|
|
hexmask.long.byte 0x0c 24.--28. 1. " RET_VSET_EFUSE ,Retention mode Fuse value"
|
|
textline " "
|
|
hexmask.long.byte 0x0c 16.--20. 1. " RET_VSET_OUT ,Retention Mode voltage control"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " ACT_MUX_CTRL ,Override VSET Fuse setting" "No override,Override"
|
|
textline " "
|
|
hexmask.long.byte 0x0c 8.--12. 1. " ACT_VSET_EFUSE ,Active mode Fuse value"
|
|
textline " "
|
|
hexmask.long.byte 0x0c 0.--4. 1. " ACT_VSET_OUT ,Active Mode Voltage Control"
|
|
line.long 0x10 "CONTROL_CSI,Control CSIa And CSIb Receiver Trimming Setting"
|
|
bitfld.long 0x10 31. " CSI_B_MUX_CTRL ,Override CSIb receiver trimming Fuse" "No override,Override"
|
|
textline " "
|
|
hexmask.long.byte 0x10 21.--25. 1. " CSI_B_TRIM_FUSE ,CSIb receiver trimming Fuse value"
|
|
textline " "
|
|
hexmask.long.byte 0x10 16.--20. 1. " CSI_B_TRIM_REG ,CSIb receiver trimming Register control"
|
|
textline " "
|
|
bitfld.long 0x10 15. " CSI_A_MUX_CTRL ,Override CSIa receiver trimming Fuse" "No override,Override"
|
|
textline " "
|
|
hexmask.long.byte 0x10 5.--9. 1. " CSI_A_TRIM_FUSE ,CSIa receiver trimming Fuse value"
|
|
textline " "
|
|
hexmask.long.byte 0x10 0.--4. 1. " CSI_A_TRIM_REG ,CSIa receiver trimming Register control"
|
|
base ad:0x48002540
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "CONTROL_IDCODE,Device IDCODE"
|
|
hexmask.long.byte 0x00 28.--31. 1. " VERSION ,Revision number"
|
|
textline " "
|
|
hexmask.long.word 0x00 12.--27. 1. " HAWKEYE ,Hawkeye number"
|
|
textline " "
|
|
hexmask.long.word 0x00 1.--11. 1. " TI_IDM ,Manufacturer identity (TI)"
|
|
width 0xb
|
|
tree.end
|
|
tree "PADCONFS_WKUP"
|
|
base ad:0x48002A00
|
|
width 30.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "CONTROL_PADCONF_I2C4_SCL,Configuration Register For Pads i2c4_scl; i2c4_sda"
|
|
bitfld.long 0x00 24. " INPUTENABLE1 ,Input enable for i2c4_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PULLTYPESELECT1 ,Pull-up/Down selection for i2c4_sda" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PULLUDENABLE1 ,Pull-up/Down enable for i2c4_sda" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " MUXMODE1 ,Functional multiplexing selection for i2c4_sda" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for i2c4_sci" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for i2c4_sci" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for i2c4_sci" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " MUXMODE0 ,Functional multiplexing selection for i2c4_sci" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "CONTROL_PADCONF_SYS_32K,Configuration Register For Pads sys_32k; sys_clkreq"
|
|
bitfld.long 0x04 31. " WAKEUPEVENT1 ,Wake Up event for sys_clkreq" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x04 30. " WAKEUPENABLE1 ,Wake Up enable for sys_clkreq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 24. " INPUTENABLE1 ,Input enable for sys_clkreq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_clkreq" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_clkreq" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_clkreq" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8. " INPUTENABLE0 ,Off mode enable for sys_32k" "Disabled,Enabled"
|
|
line.long 0x08 "CONTROL_PADCONF_SYS_NRESWARM,Configuration Register For Pads sys_nreswarm; sys_boot0"
|
|
bitfld.long 0x08 31. " WAKEUPEVENT1 ,Wake Up event for sys_boot0" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x08 30. " WAKEUPENABLE1 ,Wake Up enable for sys_boot0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " OFFOUTVALUE1 ,Off mode output value for sys_boot0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 26. " OFFOUTENABLE1 ,Off mode output enable for sys_boot0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OFFENABLE1 ,Off mode enable for sys_boot0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " INPUTENABLE1 ,Input enable for sys_boot0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_boot0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_boot0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_boot0" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 15. " WAKEUPEVENT0 ,Wake Up event for sys_nreswarm" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x08 14. " WAKEUPENABLE0 ,Wake Up enable for sys_nreswarm" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " INPUTENABLE0 ,Off mode enable for sys_32k" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sys_nreswarm" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 3. " PULLUDENABLE0 ,Pull-up/Down enable for sys_nreswarm" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " MUXMODE0 ,Functional multiplexing selection for sys_nreswarm" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "CONTROL_PADCONF_SYS_BOOT1,Configuration Register For Pads sys_boot1; sys_boot2"
|
|
bitfld.long 0xC 31. " WAKEUPEVENT1 ,Wake Up event for sys_boot2" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 30. " WAKEUPENABLE1 ,Wake Up enable for sys_boot2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 27. " OFFOUTVALUE1 ,Off mode output value for sys_boot2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 26. " OFFOUTENABLE1 ,Off mode output enable for sys_boot2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 25. " OFFENABLE1 ,Off mode enable for sys_boot2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 24. " INPUTENABLE1 ,Input enable for sys_boot2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_boot2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_boot2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_boot2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0xC 15. " WAKEUPEVENT0 ,Wake Up event for sys_boot1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0xC 14. " WAKEUPENABLE0 ,Wake Up enable for sys_boot1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 11. " OFFOUTVALUE0 ,Off mode output value for sys_boot1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0xC 10. " OFFOUTENABLE0 ,Off mode output enable for sys_boot1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 9. " OFFENABLE0 ,Off mode enable for sys_boot1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 8. " INPUTENABLE0 ,Input enable for sys_boot1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sys_boot1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0xC 3. " PULLUDENABLE0 ,Pull-up/Down enable for sys_boot1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 0.--2. " MUXMODE0 ,Functional multiplexing selection for sys_boot1" "0,1,2,3,4,5,6,7"
|
|
line.long 0x10 "CONTROL_PADCONF_SYS_BOOT3,Configuration Register For Pads sys_boot3; sys_boot4"
|
|
bitfld.long 0x10 31. " WAKEUPEVENT1 ,Wake Up event for sys_boot4" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 30. " WAKEUPENABLE1 ,Wake Up enable for sys_boot4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " OFFOUTVALUE1 ,Off mode output value for sys_boot4" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 26. " OFFOUTENABLE1 ,Off mode output enable for sys_boot4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " OFFENABLE1 ,Off mode enable for sys_boot4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " INPUTENABLE1 ,Input enable for sys_boot4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_boot4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_boot4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_boot4" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x10 15. " WAKEUPEVENT0 ,Wake Up event for sys_boot3" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x10 14. " WAKEUPENABLE0 ,Wake Up enable for sys_boot3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " OFFOUTVALUE0 ,Off mode output value for sys_boot3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 10. " OFFOUTENABLE0 ,Off mode output enable for sys_boot3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " OFFENABLE0 ,Off mode enable for sys_boot3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " INPUTENABLE0 ,Input enable for sys_boot3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sys_boot3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " PULLUDENABLE0 ,Pull-up/Down enable for sys_boot3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0.--2. " MUXMODE0 ,Functional multiplexing selection for sys_boot3" "0,1,2,3,4,5,6,7"
|
|
line.long 0x14 "CONTROL_PADCONF_SYS_BOOT5,Configuration Register For Pads sys_boot5; sys_boot6"
|
|
bitfld.long 0x14 31. " WAKEUPEVENT1 ,Wake Up event for sys_boot6" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 30. " WAKEUPENABLE1 ,Wake Up enable for sys_boot6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " OFFOUTVALUE1 ,Off mode output value for sys_boot6" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 26. " OFFOUTENABLE1 ,Off mode output enable for sys_boot6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " OFFENABLE1 ,Off mode enable for sys_boot6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 24. " INPUTENABLE1 ,Input enable for sys_boot6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_boot6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_boot6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_boot6" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x14 15. " WAKEUPEVENT0 ,Wake Up event for sys_boot5" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x14 14. " WAKEUPENABLE0 ,Wake Up enable for sys_boot5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " OFFOUTVALUE0 ,Off mode output value for sys_boot5" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x14 10. " OFFOUTENABLE0 ,Off mode output enable for sys_boot5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " OFFENABLE0 ,Off mode enable for sys_boot5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 8. " INPUTENABLE0 ,Input enable for sys_boot5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sys_boot5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x14 3. " PULLUDENABLE0 ,Pull-up/Down enable for sys_boot5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0.--2. " MUXMODE0 ,Functional multiplexing selection for sys_boot5" "0,1,2,3,4,5,6,7"
|
|
line.long 0x18 "CONTROL_PADCONF_SYS_OFF_MODE,Configuration Register For Pads sys_off_mode; sys_clkout1"
|
|
bitfld.long 0x18 31. " WAKEUPEVENT1 ,Wake Up event for sys_clkout1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 30. " WAKEUPENABLE1 ,Wake Up enable for sys_clkout1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 24. " INPUTENABLE1 ,Input enable for sys_clkout1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 20. " PULLTYPESELECT1 ,Pull-up/Down selection for sys_clkout1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 19. " PULLUDENABLE1 ,Pull-up/Down enable for sys_clkout1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16.--18. " MUXMODE1 ,Functional multiplexing selection for sys_clkout1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x18 15. " WAKEUPEVENT0 ,Wake Up event for sys_off_mode" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x18 14. " WAKEUPENABLE0 ,Wake Up enable for sys_off_mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 8. " INPUTENABLE0 ,Input enable for sys_off_mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sys_off_mode" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x18 3. " PULLUDENABLE0 ,Pull-up/Down enable for sys_off_mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " MUXMODE0 ,Functional multiplexing selection for sys_off_mode" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1C "CONTROL_PADCONF_JTAG_NTRST,Configuration Register For Pads jtag_ntrst; jtag_tck"
|
|
bitfld.long 0x1C 24. " INPUTENABLE1 ,Input enable for jtag_tck" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 20. " PULLTYPESELECT1 ,Pull-up/Down selection for jtag_tck" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " PULLUDENABLE1 ,Pull-up/Down enable for jtag_tck" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 8. " INPUTENABLE0 ,Input enable for jtag_ntrst" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 4. " PULLTYPESELECT0 ,Pull-up/Down selection for jtag_ntrst" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " PULLUDENABLE0 ,Pull-up/Down enable for jtag_ntrst" "Disabled,Enabled"
|
|
line.long 0x20 "CONTROL_PADCONF_JTAG_TMS_TMSC,Configuration Register For Pads jtag_tms_tmsc; jtag_tdi"
|
|
bitfld.long 0x20 24. " INPUTENABLE1 ,Input enable for jtag_tdi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 20. " PULLTYPESELECT1 ,Pull-up/Down selection for jtag_tdi" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 19. " PULLUDENABLE1 ,Pull-up/Down enable for jtag_tdi" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8. " INPUTENABLE0 ,Input enable for jtag_tms_tmsc" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 4. " PULLTYPESELECT0 ,Pull-up/Down selection for jtag_tms_tmsc" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x20 3. " PULLUDENABLE0 ,Pull-up/Down enable for jtag_tms_tmsc" "Disabled,Enabled"
|
|
line.long 0x24 "CONTROL_PADCONF_JTAG_EMU0,Configuration Register For Pads jtag_emu0; jtag_emu1"
|
|
bitfld.long 0x24 31. " WAKEUPEVENT1 ,Wake Up event for jtag_emu1" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x24 30. " WAKEUPENABLE1 ,Wake Up enable for jtag_emu1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 29. " OFFPULLTYPESELECT1 ,Off mode Pull-up/Down selection for jtag_emu1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 28. " OFFPULLUDENABLE1 ,Off mode Pull-up/Down enable for jtag_emu1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 27. " OFFOUTVALUE1 ,Off mode output value for jtag_emu1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 26. " OFFOUTENABLE1 ,Off mode output enable for jtag_emu1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 25. " OFFENABLE1 ,Off mode enable for jtag_emu1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 24. " INPUTENABLE1 ,Input enable for jtag_emu1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 20. " PULLTYPESELECT1 ,Pull-up/Down selection for jtag_emu1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 19. " PULLUDENABLE1 ,Pull-up/Down enable for jtag_emu1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 16.--18. " MUXMODE1 ,Functional multiplexing selection for jtag_emu1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x24 15. " WAKEUPEVENT0 ,Wake Up event for jtag_emu0" "No event,Event"
|
|
textline " "
|
|
bitfld.long 0x24 14. " WAKEUPENABLE0 ,Wake Up enable for jtag_emu0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 13. " OFFPULLTYPESELECT0 ,Off mode Pull-up/Down selection for jtag_emu0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 12. " OFFPULLUDENABLE0 ,Off mode Pull-up/Down enable for jtag_emu0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 11. " OFFOUTVALUE0 ,Off mode output value for jtag_emu0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x24 10. " OFFOUTENABLE0 ,Off mode output enable for jtag_emu0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 9. " OFFENABLE0 ,Off mode enable for jtag_emu0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 8. " INPUTENABLE0 ,Input enable for jtag_emu0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 4. " PULLTYPESELECT0 ,Pull-up/Down selection for jtag_emu0" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x24 3. " PULLUDENABLE0 ,Pull-up/Down enable for jtag_emu0" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 0.--2. " MUXMODE0 ,Functional multiplexing selection for jtag_emu0" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4C++0x7
|
|
line.long 0x00 "CONTROL_PADCONF_SAD2D_SWAKEUP,Configuration register for pads sad2d_swakeup; jtag_rtck"
|
|
bitfld.long 0x00 27. " OFFOUTVALUE1 ,Off mode output value for jtag_rtck" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 26. " OFFOUTENABLE1 ,Off mode output enable for jtag_rtck" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OFFENABLE1 ,Off mode enable for jtag_rtck" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " INPUTENABLE0 ,Input enable for sad2d_swakeup" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PULLTYPESELECT0 ,Pull-up/Down selection for sad2d_swakeup" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PULLUDENABLE0 ,Pull-up/Down enable for sad2d_swakeup" "Disabled,Enabled"
|
|
line.long 0x04 "CONTROL_PADCONF_TDO,Configuration Register For Pads jtag_tdo"
|
|
bitfld.long 0x04 11. " OFFOUTVALUE0 ,Off mode output value for jtag_tdo" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 10. " OFFOUTENABLE0 ,Off mode output enable for jtag_tdo" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OFFENABLE0 ,Off mode enable for jtag_tdo" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "GENERAL_WKUP"
|
|
base ad:0x48002A60
|
|
width 25.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "CONTROL_SEC_TAP,Security TAP Controllers Register"
|
|
bitfld.long 0x00 31. " SECTAPWRDISABLE ,Security TAP controller register write disable control" "Allowed,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x00 14. " SR2TAPENABLE ,Smart Reflex2 TAP control" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("AM3517*"))
|
|
bitfld.long 0x00 13. " SR1TAPENABLE ,Smart Reflex1 TAP control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " OCTTAPENABLE ,OCT TAP Control" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("AM3517*"))
|
|
bitfld.long 0x00 9. " SEQTAPENABLE ,SEQ TAP Control" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " SUBTAPCTRLDISABLE ,Restrict writable register list accessible through the Chip Level" "Unrestricted,Restricted"
|
|
textline " "
|
|
sif (!cpuis("AM3517*"))
|
|
bitfld.long 0x00 7. " IVA2ACCTAPENABLE ,IVA2 Video Accelerator TAP controls" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IVA2TAPENABLE ,IVA2 Tap Enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " SDTITAPENABLE ,SDTI TAP control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EFUSETAPENABLE ,E-Fuse TAP control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CHIPLEVELTAPENABLE ,Chip Level TAP control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ETBTAPENABLE ,ETB TAP control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CPEFUSETAPENABLE ,CP Efuse TAP control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MPUTAPENABLE ,MPU/ICECrusher/ETM/PSA TAP control" "Disabled,Enabled"
|
|
line.long 0x04 "CONTROL_SEC_EMU,Security Emulation Register"
|
|
bitfld.long 0x04 31. " SECEMUWRDISABLE ,Security EMULATION register write disable control" "Allowed,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x04 3. " ICESECPRIVDBGENABLE ,ICE Secure Privilege debug control (MPU trace data)" "Not captured,Captured"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ETMSECPRIVDBGENABLE ,ETM Secure Privilege Control (MPU trace data)" "Not captured,Captured"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " GENDBGENABLE ,Generic Debug Control" "Disabled,Strict Public,Public,Secure"
|
|
line.long 0x8 "CONTROL_WKUP_DEBOBS_0,WKUP Domain Set Of Signals To Be Observed For hw_dbg[3-0]"
|
|
hexmask.long.byte 0x8 24.--28. 1. " OBSMUX3 ,Select the set of signals to be observed for hw_dbg3"
|
|
hexmask.long.byte 0x8 16.--20. 1. " OBSMUX2 ,Select the set of signals to be observed for hw_dbg2"
|
|
textline " "
|
|
hexmask.long.byte 0x8 8.--12. 1. " OBSMUX1 ,Select the set of signals to be observed for hw_dbg1"
|
|
hexmask.long.byte 0x8 0.--4. 1. " OBSMUX0 ,Select the set of signals to be observed for hw_dbg0"
|
|
line.long 0xC "CONTROL_WKUP_DEBOBS_1,WKUP Domain Set Of Signals To Be Observed For hw_dbg[7-4]"
|
|
hexmask.long.byte 0xC 24.--28. 1. " OBSMUX7 ,Select the set of signals to be observed for hw_dbg7"
|
|
hexmask.long.byte 0xC 16.--20. 1. " OBSMUX6 ,Select the set of signals to be observed for hw_dbg6"
|
|
textline " "
|
|
hexmask.long.byte 0xC 8.--12. 1. " OBSMUX5 ,Select the set of signals to be observed for hw_dbg5"
|
|
hexmask.long.byte 0xC 0.--4. 1. " OBSMUX4 ,Select the set of signals to be observed for hw_dbg4"
|
|
line.long 0x10 "CONTROL_WKUP_DEBOBS_2,WKUP Domain Set Of Signals To Be Observed For hw_dbg[11-8]"
|
|
hexmask.long.byte 0x10 24.--28. 1. " OBSMUX11 ,Select the set of signals to be observed for hw_dbg11"
|
|
hexmask.long.byte 0x10 16.--20. 1. " OBSMUX10 ,Select the set of signals to be observed for hw_dbg10"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--12. 1. " OBSMUX9 ,Select the set of signals to be observed for hw_dbg9"
|
|
hexmask.long.byte 0x10 0.--4. 1. " OBSMUX8 ,Select the set of signals to be observed for hw_dbg8"
|
|
line.long 0x14 "CONTROL_WKUP_DEBOBS_3,WKUP Domain Set Of Signals To Be Observed For hw_dbg[15-12]"
|
|
hexmask.long.byte 0x14 24.--28. 1. " OBSMUX15 ,Select the set of signals to be observed for hw_dbg15"
|
|
hexmask.long.byte 0x14 16.--20. 1. " OBSMUX14 ,Select the set of signals to be observed for hw_dbg14"
|
|
textline " "
|
|
hexmask.long.byte 0x14 8.--12. 1. " OBSMUX13 ,Select the set of signals to be observed for hw_dbg13"
|
|
hexmask.long.byte 0x14 0.--4. 1. " OBSMUX12 ,Select the set of signals to be observed for hw_dbg12"
|
|
line.long 0x18 "CONTROL_WKUP_DEBOBS_4,WKUP Domain Set Of Signals To Be Observed For hw_dbg[17-16]"
|
|
bitfld.long 0x18 31. " WKUPOBSERVABILITYDISABLE ,Control the observability feature" "Enabled,Disabled"
|
|
textline " "
|
|
hexmask.long.byte 0x18 8.--12. 1. " OBSMUX17 ,Select the set of signals to be observed for hw_dbg17"
|
|
hexmask.long.byte 0x18 0.--4. 1. " OBSMUX16 ,Select the set of signals to be observed for hw_dbg16"
|
|
line.long 0x1C "CONTROL_SEC_DAP,DAP Qualifiers Generated Using This Register"
|
|
bitfld.long 0x1C 31. " SECDAPWRDISABLE ,Security DAP Register write disable control" "Allowed,Forbidden"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " FORCEDAPSECUSERDEBUGEN ,Force MreqSupervisor to 0 for secure DAP accesses" "Unchanged,Forced"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " FORCEDAPSECPUBLICDEBUGEN ,Force MreqSecure to 0 for secure DAP accesses" "Unchanged,Forced"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " FORCEDAPPUBUSERDEBUGEN ,Force MreqSupervisor to 0 for public DAP accesses" "Unchanged,Forced"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "Memory Management Unit"
|
|
tree "Camera MMU"
|
|
base ad:0x480BD400
|
|
width 18.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MMU_SYSCONFIG,Various Parameters Of The Interconnect Interface"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "Switched off,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode" "Force,No idle,Smart,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Always,Never"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interconnect clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MMU_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "MMU_IRQSTATUS,Interrupt Status Register"
|
|
eventfld.long 0x00 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB (MultiHitFault)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " TABLEWALKFAULT ,Error response received during a table walk (TableWalkFault)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 2. " EMUMISS ,Unrecoverable TLB miss during debug (EMUMiss)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (TranslationFault)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TLBMISS ,Unrecoverable TLB miss" "False,Pending"
|
|
line.long 0x04 "MMU_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "Masked,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TABLEWALKFAULT ,Error response received during a table walk" "Masked,Error"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EMUMISS ,Unrecoverable TLB miss during debug" "Masked,Error"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables" "Masked,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TLBMISS ,Unrecoverable TLB miss" "Masked,Error"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "MMU_WALKING_ST,Status Information About The Table Walking Logic"
|
|
bitfld.long 0x00 0. " TWLRUNNING ,Table walking logic is running" "Completed,Running"
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "MMU_CNTL,MMU Features"
|
|
bitfld.long 0x00 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TWLENABLE ,Table walking logic enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MMUENABLE ,MMU enable" "Disabled,Enabled"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x00 "MMU_FAULT_AD,Virtual Address That Generated The Interrupt"
|
|
group.long 0x4C++0x7
|
|
line.long 0x00 "MMU_TTB,Resolution Table Base Address"
|
|
hexmask.long 0x00 7.--31. 0x80 " TTBADDRESS ,Translation table base address"
|
|
line.long 0x04 "MMU_LOCK,Lock the TLB entries to be read"
|
|
bitfld.long 0x04 10.--12. " BASEVALUE ,Locked entries base value" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 4.--6. " CURRENTVICTIM ,Eentry updated by the TWL/by the software/TLB entry read" "0,1,2,3,4,5,6,7"
|
|
group.long 0x54++0x13
|
|
line.long 0x00 "MMU_LD_TLB,Loads A TLB Entry"
|
|
bitfld.long 0x00 0. " LDTLBITEM ,Write (load) data in the TLB" "No effect,Load"
|
|
line.long 0x04 "MMU_CAM,CAM Entry"
|
|
hexmask.long 0x04 12.--31. 0x1000 " VATAG ,Virtual address tag"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P ,Preserved bit (TLB entry flushed)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 2. " V ,Valid bit (TLB entry)" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " PAGESIZE ,Page size" "1MB,64KB,4KB,16MB"
|
|
line.long 0x08 "MMU_RAM,RAM Entry"
|
|
hexmask.long 0x08 12.--31. 0x1000 " PHYSICALADDRESS ,Physical address of the page"
|
|
textline " "
|
|
bitfld.long 0x08 9. " ENDIANNESS ,Endianness of the page" "Little endian,Big endian"
|
|
textline " "
|
|
bitfld.long 0x08 7.--8. " ELEMENTSIZE ,Element size of the page" "8 bits,16 bits,32 bits,No translation"
|
|
textline " "
|
|
bitfld.long 0x08 6. " MIXED ,Mixed page attribute (use CPU element size)" "TLB,CPU"
|
|
line.long 0x0C "MMU_GFLUSH,Flushes All The Non-protected TLB Entries"
|
|
bitfld.long 0x0C 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries" "No effect,Flush"
|
|
line.long 0x10 "MMU_FLUSH_ENTRY,Flushes The Entry Pointed To By The CAM Virtual Address"
|
|
bitfld.long 0x10 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address" "No effect,Flush"
|
|
rgroup.long 0x68++0xB
|
|
line.long 0x00 "MMU_READ_CAM,Reads CAM Data From A CAM Entry"
|
|
hexmask.long 0x00 12.--31. 0x1000 " VATAG ,Virtual address tag"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P ,Preserved bit (TLB entry flushed)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " V ,Valid bit (TLB entry)" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PAGESIZE ,Page size" "1MB,64KB,4KB,16MB"
|
|
line.long 0x04 "MMU_READ_RAM,Reads RAM Data From A RAM Entry"
|
|
hexmask.long 0x04 12.--31. 0x1000 " PHYSICALADDRESS ,Physical address of the page"
|
|
textline " "
|
|
bitfld.long 0x04 9. " ENDIANNESS ,Endianness of the page" "Little endian,Big endian"
|
|
textline " "
|
|
bitfld.long 0x04 7.--8. " ELEMENTSIZE ,Element size of the page" "8 bits,16 bits,32 bits,No translation"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MIXED ,Mixed page attribute (use CPU element size)" "TLB,CPU"
|
|
line.long 0x08 "MMU_EMU_FAULT_AD,Last Virtual Address Of A Fault Caused By The Debugger"
|
|
width 0xb
|
|
tree.end
|
|
sif ((cpu()=="OMAP3530")||(cpu()=="OMAP3525"))
|
|
tree "IVA2.2 MMU"
|
|
base ad:0x5D000000
|
|
width 18.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MMU_SYSCONFIG,Various Parameters Of The Interconnect Interface"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "Switched off,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode" "Force,No idle,Smart,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Always,Never"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interconnect clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MMU_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "MMU_IRQSTATUS,Interrupt Status Register"
|
|
eventfld.long 0x00 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB (MultiHitFault)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " TABLEWALKFAULT ,Error response received during a table walk (TableWalkFault)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 2. " EMUMISS ,Unrecoverable TLB miss during debug (EMUMiss)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (TranslationFault)" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TLBMISS ,Unrecoverable TLB miss" "False,Pending"
|
|
line.long 0x04 "MMU_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "Masked,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " TABLEWALKFAULT ,Error response received during a table walk" "Masked,Error"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EMUMISS ,Unrecoverable TLB miss during debug" "Masked,Error"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables" "Masked,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " TLBMISS ,Unrecoverable TLB miss" "Masked,Error"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "MMU_WALKING_ST,Status Information About The Table Walking Logic"
|
|
bitfld.long 0x00 0. " TWLRUNNING ,Table walking logic is running" "Completed,Running"
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "MMU_CNTL,MMU Features"
|
|
bitfld.long 0x00 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TWLENABLE ,Table walking logic enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MMUENABLE ,MMU enable" "Disabled,Enabled"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x00 "MMU_FAULT_AD,Virtual Address That Generated The Interrupt"
|
|
group.long 0x4C++0x7
|
|
line.long 0x00 "MMU_TTB,Resolution Table Base Address"
|
|
hexmask.long 0x00 7.--31. 0x80 " TTBADDRESS ,Translation table base address"
|
|
line.long 0x04 "MMU_LOCK,Lock the TLB entries to be read"
|
|
hexmask.long.byte 0x04 10.--14. 1. " BASEVALUE ,Locked entries base value"
|
|
textline " "
|
|
hexmask.long.byte 0x04 4.--8. 1. " CURRENTVICTIM ,Eentry updated by the TWL/by the software/TLB entry read"
|
|
group.long 0x54++0x13
|
|
line.long 0x00 "MMU_LD_TLB,Loads A TLB Entry"
|
|
bitfld.long 0x00 0. " LDTLBITEM ,Write (load) data in the TLB" "No effect,Load"
|
|
line.long 0x04 "MMU_CAM,CAM Entry"
|
|
hexmask.long 0x04 12.--31. 0x1000 " VATAG ,Virtual address tag"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P ,Preserved bit (TLB entry flushed)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x04 2. " V ,Valid bit (TLB entry)" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " PAGESIZE ,Page size" "1MB,64KB,4KB,16MB"
|
|
line.long 0x08 "MMU_RAM,RAM Entry"
|
|
hexmask.long 0x08 12.--31. 0x1000 " PHYSICALADDRESS ,Physical address of the page"
|
|
textline " "
|
|
bitfld.long 0x08 9. " ENDIANNESS ,Endianness of the page" "Little endian,Big endian"
|
|
textline " "
|
|
bitfld.long 0x08 7.--8. " ELEMENTSIZE ,Element size of the page" "8 bits,16 bits,32 bits,No translation"
|
|
textline " "
|
|
bitfld.long 0x08 6. " MIXED ,Mixed page attribute (use CPU element size)" "TLB,CPU"
|
|
line.long 0x0C "MMU_GFLUSH,Flushes All The Non-protected TLB Entries"
|
|
bitfld.long 0x0C 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries" "No effect,Flush"
|
|
line.long 0x10 "MMU_FLUSH_ENTRY,Flushes The Entry Pointed To By The CAM Virtual Address"
|
|
bitfld.long 0x10 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address" "No effect,Flush"
|
|
rgroup.long 0x68++0xB
|
|
line.long 0x00 "MMU_READ_CAM,Reads CAM Data From A CAM Entry"
|
|
hexmask.long 0x00 12.--31. 0x1000 " VATAG ,Virtual address tag"
|
|
textline " "
|
|
bitfld.long 0x00 3. " P ,Preserved bit (TLB entry flushed)" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " V ,Valid bit (TLB entry)" "Invalid,Valid"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PAGESIZE ,Page size" "1MB,64KB,4KB,16MB"
|
|
line.long 0x04 "MMU_READ_RAM,Reads RAM Data From A RAM Entry"
|
|
hexmask.long 0x04 12.--31. 0x1000 " PHYSICALADDRESS ,Physical address of the page"
|
|
textline " "
|
|
bitfld.long 0x04 9. " ENDIANNESS ,Endianness of the page" "Little endian,Big endian"
|
|
textline " "
|
|
bitfld.long 0x04 7.--8. " ELEMENTSIZE ,Element size of the page" "8 bits,16 bits,32 bits,No translation"
|
|
textline " "
|
|
bitfld.long 0x04 6. " MIXED ,Mixed page attribute (use CPU element size)" "TLB,CPU"
|
|
line.long 0x08 "MMU_EMU_FAULT_AD,Last Virtual Address Of A Fault Caused By The Debugger"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "DMA"
|
|
tree "Common Registers"
|
|
base ad:0x48056000
|
|
width 19.
|
|
group.long 0x08++0x27
|
|
line.long 0x0 "DMA4_IRQSTATUS_L0,Interrupt Status Over Line L0 Register"
|
|
eventfld.long 0x0 31. " IRQSTATUS31 ,Interrupt Status For Channell 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 30. " IRQSTATUS30 ,Interrupt Status For Channell 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 29. " IRQSTATUS29 ,Interrupt Status For Channell 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 28. " IRQSTATUS28 ,Interrupt Status For Channell 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 27. " IRQSTATUS27 ,Interrupt Status For Channell 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 26. " IRQSTATUS26 ,Interrupt Status For Channell 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 25. " IRQSTATUS25 ,Interrupt Status For Channell 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 24. " IRQSTATUS24 ,Interrupt Status For Channell 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 23. " IRQSTATUS23 ,Interrupt Status For Channell 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 22. " IRQSTATUS22 ,Interrupt Status For Channell 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 21. " IRQSTATUS21 ,Interrupt Status For Channell 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 20. " IRQSTATUS20 ,Interrupt Status For Channell 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 19. " IRQSTATUS19 ,Interrupt Status For Channell 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 18. " IRQSTATUS18 ,Interrupt Status For Channell 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 17. " IRQSTATUS17 ,Interrupt Status For Channell 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 16. " IRQSTATUS16 ,Interrupt Status For Channell 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 15. " IRQSTATUS15 ,Interrupt Status For Channell 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 14. " IRQSTATUS14 ,Interrupt Status For Channell 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 13. " IRQSTATUS13 ,Interrupt Status For Channell 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 12. " IRQSTATUS12 ,Interrupt Status For Channell 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 11. " IRQSTATUS11 ,Interrupt Status For Channell 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 10. " IRQSTATUS10 ,Interrupt Status For Channell 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 9. " IRQSTATUS9 ,Interrupt Status For Channell 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 8. " IRQSTATUS8 ,Interrupt Status For Channell 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 7. " IRQSTATUS7 ,Interrupt Status For Channell 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 6. " IRQSTATUS6 ,Interrupt Status For Channell 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 5. " IRQSTATUS5 ,Interrupt Status For Channell 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 4. " IRQSTATUS4 ,Interrupt Status For Channell 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 3. " IRQSTATUS3 ,Interrupt Status For Channell 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 2. " IRQSTATUS2 ,Interrupt Status For Channell 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x0 1. " IRQSTATUS1 ,Interrupt Status For Channell 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x0 0. " IRQSTATUS0 ,Interrupt Status For Channell 0" "No interrupt,Interrupt"
|
|
line.long 0x4 "DMA4_IRQSTATUS_L1,Interrupt Status Over Line L1 Register"
|
|
eventfld.long 0x4 31. " IRQSTATUS31 ,Interrupt Status For Channell 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 30. " IRQSTATUS30 ,Interrupt Status For Channell 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 29. " IRQSTATUS29 ,Interrupt Status For Channell 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 28. " IRQSTATUS28 ,Interrupt Status For Channell 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 27. " IRQSTATUS27 ,Interrupt Status For Channell 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 26. " IRQSTATUS26 ,Interrupt Status For Channell 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 25. " IRQSTATUS25 ,Interrupt Status For Channell 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 24. " IRQSTATUS24 ,Interrupt Status For Channell 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 23. " IRQSTATUS23 ,Interrupt Status For Channell 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 22. " IRQSTATUS22 ,Interrupt Status For Channell 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 21. " IRQSTATUS21 ,Interrupt Status For Channell 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 20. " IRQSTATUS20 ,Interrupt Status For Channell 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 19. " IRQSTATUS19 ,Interrupt Status For Channell 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 18. " IRQSTATUS18 ,Interrupt Status For Channell 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 17. " IRQSTATUS17 ,Interrupt Status For Channell 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 16. " IRQSTATUS16 ,Interrupt Status For Channell 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 15. " IRQSTATUS15 ,Interrupt Status For Channell 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 14. " IRQSTATUS14 ,Interrupt Status For Channell 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 13. " IRQSTATUS13 ,Interrupt Status For Channell 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 12. " IRQSTATUS12 ,Interrupt Status For Channell 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 11. " IRQSTATUS11 ,Interrupt Status For Channell 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 10. " IRQSTATUS10 ,Interrupt Status For Channell 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 9. " IRQSTATUS9 ,Interrupt Status For Channell 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 8. " IRQSTATUS8 ,Interrupt Status For Channell 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 7. " IRQSTATUS7 ,Interrupt Status For Channell 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 6. " IRQSTATUS6 ,Interrupt Status For Channell 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 5. " IRQSTATUS5 ,Interrupt Status For Channell 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 4. " IRQSTATUS4 ,Interrupt Status For Channell 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 3. " IRQSTATUS3 ,Interrupt Status For Channell 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 2. " IRQSTATUS2 ,Interrupt Status For Channell 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x4 1. " IRQSTATUS1 ,Interrupt Status For Channell 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x4 0. " IRQSTATUS0 ,Interrupt Status For Channell 0" "No interrupt,Interrupt"
|
|
line.long 0x8 "DMA4_IRQSTATUS_L2,Interrupt Status Over Line L2 Register"
|
|
eventfld.long 0x8 31. " IRQSTATUS31 ,Interrupt Status For Channell 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 30. " IRQSTATUS30 ,Interrupt Status For Channell 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 29. " IRQSTATUS29 ,Interrupt Status For Channell 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 28. " IRQSTATUS28 ,Interrupt Status For Channell 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 27. " IRQSTATUS27 ,Interrupt Status For Channell 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 26. " IRQSTATUS26 ,Interrupt Status For Channell 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 25. " IRQSTATUS25 ,Interrupt Status For Channell 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 24. " IRQSTATUS24 ,Interrupt Status For Channell 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 23. " IRQSTATUS23 ,Interrupt Status For Channell 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 22. " IRQSTATUS22 ,Interrupt Status For Channell 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 21. " IRQSTATUS21 ,Interrupt Status For Channell 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 20. " IRQSTATUS20 ,Interrupt Status For Channell 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 19. " IRQSTATUS19 ,Interrupt Status For Channell 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 18. " IRQSTATUS18 ,Interrupt Status For Channell 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 17. " IRQSTATUS17 ,Interrupt Status For Channell 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 16. " IRQSTATUS16 ,Interrupt Status For Channell 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 15. " IRQSTATUS15 ,Interrupt Status For Channell 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 14. " IRQSTATUS14 ,Interrupt Status For Channell 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 13. " IRQSTATUS13 ,Interrupt Status For Channell 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 12. " IRQSTATUS12 ,Interrupt Status For Channell 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 11. " IRQSTATUS11 ,Interrupt Status For Channell 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 10. " IRQSTATUS10 ,Interrupt Status For Channell 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 9. " IRQSTATUS9 ,Interrupt Status For Channell 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 8. " IRQSTATUS8 ,Interrupt Status For Channell 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 7. " IRQSTATUS7 ,Interrupt Status For Channell 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 6. " IRQSTATUS6 ,Interrupt Status For Channell 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 5. " IRQSTATUS5 ,Interrupt Status For Channell 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 4. " IRQSTATUS4 ,Interrupt Status For Channell 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 3. " IRQSTATUS3 ,Interrupt Status For Channell 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 2. " IRQSTATUS2 ,Interrupt Status For Channell 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x8 1. " IRQSTATUS1 ,Interrupt Status For Channell 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x8 0. " IRQSTATUS0 ,Interrupt Status For Channell 0" "No interrupt,Interrupt"
|
|
line.long 0xC "DMA4_IRQSTATUS_L3,Interrupt Status Over Line L3 Register"
|
|
eventfld.long 0xC 31. " IRQSTATUS31 ,Interrupt Status For Channell 31" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 30. " IRQSTATUS30 ,Interrupt Status For Channell 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 29. " IRQSTATUS29 ,Interrupt Status For Channell 29" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 28. " IRQSTATUS28 ,Interrupt Status For Channell 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 27. " IRQSTATUS27 ,Interrupt Status For Channell 27" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 26. " IRQSTATUS26 ,Interrupt Status For Channell 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 25. " IRQSTATUS25 ,Interrupt Status For Channell 25" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 24. " IRQSTATUS24 ,Interrupt Status For Channell 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 23. " IRQSTATUS23 ,Interrupt Status For Channell 23" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 22. " IRQSTATUS22 ,Interrupt Status For Channell 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 21. " IRQSTATUS21 ,Interrupt Status For Channell 21" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 20. " IRQSTATUS20 ,Interrupt Status For Channell 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 19. " IRQSTATUS19 ,Interrupt Status For Channell 19" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 18. " IRQSTATUS18 ,Interrupt Status For Channell 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 17. " IRQSTATUS17 ,Interrupt Status For Channell 17" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 16. " IRQSTATUS16 ,Interrupt Status For Channell 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 15. " IRQSTATUS15 ,Interrupt Status For Channell 15" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 14. " IRQSTATUS14 ,Interrupt Status For Channell 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 13. " IRQSTATUS13 ,Interrupt Status For Channell 13" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 12. " IRQSTATUS12 ,Interrupt Status For Channell 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 11. " IRQSTATUS11 ,Interrupt Status For Channell 11" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 10. " IRQSTATUS10 ,Interrupt Status For Channell 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 9. " IRQSTATUS9 ,Interrupt Status For Channell 9" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 8. " IRQSTATUS8 ,Interrupt Status For Channell 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 7. " IRQSTATUS7 ,Interrupt Status For Channell 7" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 6. " IRQSTATUS6 ,Interrupt Status For Channell 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 5. " IRQSTATUS5 ,Interrupt Status For Channell 5" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 4. " IRQSTATUS4 ,Interrupt Status For Channell 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 3. " IRQSTATUS3 ,Interrupt Status For Channell 3" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 2. " IRQSTATUS2 ,Interrupt Status For Channell 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0xC 1. " IRQSTATUS1 ,Interrupt Status For Channell 1" "No interrupt,Interrupt"
|
|
eventfld.long 0xC 0. " IRQSTATUS0 ,Interrupt Status For Channell 0" "No interrupt,Interrupt"
|
|
line.long 0x10 "DMA4_IRQENABLE_L0,Interrupt Over Line L0 Enable Register"
|
|
eventfld.long 0x10 31. " IRQENABLE31 ,Interrupt Enable For Channell 31" "Disabled,Enabled"
|
|
eventfld.long 0x10 30. " IRQENABLE30 ,Interrupt Enable For Channell 30" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 29. " IRQENABLE29 ,Interrupt Enable For Channell 29" "Disabled,Enabled"
|
|
eventfld.long 0x10 28. " IRQENABLE28 ,Interrupt Enable For Channell 28" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 27. " IRQENABLE27 ,Interrupt Enable For Channell 27" "Disabled,Enabled"
|
|
eventfld.long 0x10 26. " IRQENABLE26 ,Interrupt Enable For Channell 26" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 25. " IRQENABLE25 ,Interrupt Enable For Channell 25" "Disabled,Enabled"
|
|
eventfld.long 0x10 24. " IRQENABLE24 ,Interrupt Enable For Channell 24" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 23. " IRQENABLE23 ,Interrupt Enable For Channell 23" "Disabled,Enabled"
|
|
eventfld.long 0x10 22. " IRQENABLE22 ,Interrupt Enable For Channell 22" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 21. " IRQENABLE21 ,Interrupt Enable For Channell 21" "Disabled,Enabled"
|
|
eventfld.long 0x10 20. " IRQENABLE20 ,Interrupt Enable For Channell 20" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 19. " IRQENABLE19 ,Interrupt Enable For Channell 19" "Disabled,Enabled"
|
|
eventfld.long 0x10 18. " IRQENABLE18 ,Interrupt Enable For Channell 18" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 17. " IRQENABLE17 ,Interrupt Enable For Channell 17" "Disabled,Enabled"
|
|
eventfld.long 0x10 16. " IRQENABLE16 ,Interrupt Enable For Channell 16" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 15. " IRQENABLE15 ,Interrupt Enable For Channell 15" "Disabled,Enabled"
|
|
eventfld.long 0x10 14. " IRQENABLE14 ,Interrupt Enable For Channell 14" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 13. " IRQENABLE13 ,Interrupt Enable For Channell 13" "Disabled,Enabled"
|
|
eventfld.long 0x10 12. " IRQENABLE12 ,Interrupt Enable For Channell 12" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 11. " IRQENABLE11 ,Interrupt Enable For Channell 11" "Disabled,Enabled"
|
|
eventfld.long 0x10 10. " IRQENABLE10 ,Interrupt Enable For Channell 10" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 9. " IRQENABLE9 ,Interrupt Enable For Channell 9" "Disabled,Enabled"
|
|
eventfld.long 0x10 8. " IRQENABLE8 ,Interrupt Enable For Channell 8" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 7. " IRQENABLE7 ,Interrupt Enable For Channell 7" "Disabled,Enabled"
|
|
eventfld.long 0x10 6. " IRQENABLE6 ,Interrupt Enable For Channell 6" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 5. " IRQENABLE5 ,Interrupt Enable For Channell 5" "Disabled,Enabled"
|
|
eventfld.long 0x10 4. " IRQENABLE4 ,Interrupt Enable For Channell 4" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 3. " IRQENABLE3 ,Interrupt Enable For Channell 3" "Disabled,Enabled"
|
|
eventfld.long 0x10 2. " IRQENABLE2 ,Interrupt Enable For Channell 2" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x10 1. " IRQENABLE1 ,Interrupt Enable For Channell 1" "Disabled,Enabled"
|
|
eventfld.long 0x10 0. " IRQENABLE0 ,Interrupt Enable For Channell 0" "Disabled,Enabled"
|
|
line.long 0x14 "DMA4_IRQENABLE_L1,Interrupt Over Line L1 Enable Register"
|
|
eventfld.long 0x14 31. " IRQENABLE31 ,Interrupt Enable For Channell 31" "Disabled,Enabled"
|
|
eventfld.long 0x14 30. " IRQENABLE30 ,Interrupt Enable For Channell 30" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 29. " IRQENABLE29 ,Interrupt Enable For Channell 29" "Disabled,Enabled"
|
|
eventfld.long 0x14 28. " IRQENABLE28 ,Interrupt Enable For Channell 28" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 27. " IRQENABLE27 ,Interrupt Enable For Channell 27" "Disabled,Enabled"
|
|
eventfld.long 0x14 26. " IRQENABLE26 ,Interrupt Enable For Channell 26" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 25. " IRQENABLE25 ,Interrupt Enable For Channell 25" "Disabled,Enabled"
|
|
eventfld.long 0x14 24. " IRQENABLE24 ,Interrupt Enable For Channell 24" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 23. " IRQENABLE23 ,Interrupt Enable For Channell 23" "Disabled,Enabled"
|
|
eventfld.long 0x14 22. " IRQENABLE22 ,Interrupt Enable For Channell 22" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 21. " IRQENABLE21 ,Interrupt Enable For Channell 21" "Disabled,Enabled"
|
|
eventfld.long 0x14 20. " IRQENABLE20 ,Interrupt Enable For Channell 20" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 19. " IRQENABLE19 ,Interrupt Enable For Channell 19" "Disabled,Enabled"
|
|
eventfld.long 0x14 18. " IRQENABLE18 ,Interrupt Enable For Channell 18" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 17. " IRQENABLE17 ,Interrupt Enable For Channell 17" "Disabled,Enabled"
|
|
eventfld.long 0x14 16. " IRQENABLE16 ,Interrupt Enable For Channell 16" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 15. " IRQENABLE15 ,Interrupt Enable For Channell 15" "Disabled,Enabled"
|
|
eventfld.long 0x14 14. " IRQENABLE14 ,Interrupt Enable For Channell 14" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 13. " IRQENABLE13 ,Interrupt Enable For Channell 13" "Disabled,Enabled"
|
|
eventfld.long 0x14 12. " IRQENABLE12 ,Interrupt Enable For Channell 12" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 11. " IRQENABLE11 ,Interrupt Enable For Channell 11" "Disabled,Enabled"
|
|
eventfld.long 0x14 10. " IRQENABLE10 ,Interrupt Enable For Channell 10" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 9. " IRQENABLE9 ,Interrupt Enable For Channell 9" "Disabled,Enabled"
|
|
eventfld.long 0x14 8. " IRQENABLE8 ,Interrupt Enable For Channell 8" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 7. " IRQENABLE7 ,Interrupt Enable For Channell 7" "Disabled,Enabled"
|
|
eventfld.long 0x14 6. " IRQENABLE6 ,Interrupt Enable For Channell 6" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 5. " IRQENABLE5 ,Interrupt Enable For Channell 5" "Disabled,Enabled"
|
|
eventfld.long 0x14 4. " IRQENABLE4 ,Interrupt Enable For Channell 4" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 3. " IRQENABLE3 ,Interrupt Enable For Channell 3" "Disabled,Enabled"
|
|
eventfld.long 0x14 2. " IRQENABLE2 ,Interrupt Enable For Channell 2" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x14 1. " IRQENABLE1 ,Interrupt Enable For Channell 1" "Disabled,Enabled"
|
|
eventfld.long 0x14 0. " IRQENABLE0 ,Interrupt Enable For Channell 0" "Disabled,Enabled"
|
|
line.long 0x18 "DMA4_IRQENABLE_L2,Interrupt Over Line L2 Enable Register"
|
|
eventfld.long 0x18 31. " IRQENABLE31 ,Interrupt Enable For Channell 31" "Disabled,Enabled"
|
|
eventfld.long 0x18 30. " IRQENABLE30 ,Interrupt Enable For Channell 30" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 29. " IRQENABLE29 ,Interrupt Enable For Channell 29" "Disabled,Enabled"
|
|
eventfld.long 0x18 28. " IRQENABLE28 ,Interrupt Enable For Channell 28" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 27. " IRQENABLE27 ,Interrupt Enable For Channell 27" "Disabled,Enabled"
|
|
eventfld.long 0x18 26. " IRQENABLE26 ,Interrupt Enable For Channell 26" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 25. " IRQENABLE25 ,Interrupt Enable For Channell 25" "Disabled,Enabled"
|
|
eventfld.long 0x18 24. " IRQENABLE24 ,Interrupt Enable For Channell 24" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 23. " IRQENABLE23 ,Interrupt Enable For Channell 23" "Disabled,Enabled"
|
|
eventfld.long 0x18 22. " IRQENABLE22 ,Interrupt Enable For Channell 22" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 21. " IRQENABLE21 ,Interrupt Enable For Channell 21" "Disabled,Enabled"
|
|
eventfld.long 0x18 20. " IRQENABLE20 ,Interrupt Enable For Channell 20" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 19. " IRQENABLE19 ,Interrupt Enable For Channell 19" "Disabled,Enabled"
|
|
eventfld.long 0x18 18. " IRQENABLE18 ,Interrupt Enable For Channell 18" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 17. " IRQENABLE17 ,Interrupt Enable For Channell 17" "Disabled,Enabled"
|
|
eventfld.long 0x18 16. " IRQENABLE16 ,Interrupt Enable For Channell 16" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 15. " IRQENABLE15 ,Interrupt Enable For Channell 15" "Disabled,Enabled"
|
|
eventfld.long 0x18 14. " IRQENABLE14 ,Interrupt Enable For Channell 14" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 13. " IRQENABLE13 ,Interrupt Enable For Channell 13" "Disabled,Enabled"
|
|
eventfld.long 0x18 12. " IRQENABLE12 ,Interrupt Enable For Channell 12" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 11. " IRQENABLE11 ,Interrupt Enable For Channell 11" "Disabled,Enabled"
|
|
eventfld.long 0x18 10. " IRQENABLE10 ,Interrupt Enable For Channell 10" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 9. " IRQENABLE9 ,Interrupt Enable For Channell 9" "Disabled,Enabled"
|
|
eventfld.long 0x18 8. " IRQENABLE8 ,Interrupt Enable For Channell 8" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 7. " IRQENABLE7 ,Interrupt Enable For Channell 7" "Disabled,Enabled"
|
|
eventfld.long 0x18 6. " IRQENABLE6 ,Interrupt Enable For Channell 6" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 5. " IRQENABLE5 ,Interrupt Enable For Channell 5" "Disabled,Enabled"
|
|
eventfld.long 0x18 4. " IRQENABLE4 ,Interrupt Enable For Channell 4" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 3. " IRQENABLE3 ,Interrupt Enable For Channell 3" "Disabled,Enabled"
|
|
eventfld.long 0x18 2. " IRQENABLE2 ,Interrupt Enable For Channell 2" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x18 1. " IRQENABLE1 ,Interrupt Enable For Channell 1" "Disabled,Enabled"
|
|
eventfld.long 0x18 0. " IRQENABLE0 ,Interrupt Enable For Channell 0" "Disabled,Enabled"
|
|
line.long 0x1C "DMA4_IRQENABLE_L3,Interrupt Over Line L3 Enable Register"
|
|
eventfld.long 0x1C 31. " IRQENABLE31 ,Interrupt Enable For Channell 31" "Disabled,Enabled"
|
|
eventfld.long 0x1C 30. " IRQENABLE30 ,Interrupt Enable For Channell 30" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 29. " IRQENABLE29 ,Interrupt Enable For Channell 29" "Disabled,Enabled"
|
|
eventfld.long 0x1C 28. " IRQENABLE28 ,Interrupt Enable For Channell 28" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 27. " IRQENABLE27 ,Interrupt Enable For Channell 27" "Disabled,Enabled"
|
|
eventfld.long 0x1C 26. " IRQENABLE26 ,Interrupt Enable For Channell 26" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 25. " IRQENABLE25 ,Interrupt Enable For Channell 25" "Disabled,Enabled"
|
|
eventfld.long 0x1C 24. " IRQENABLE24 ,Interrupt Enable For Channell 24" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 23. " IRQENABLE23 ,Interrupt Enable For Channell 23" "Disabled,Enabled"
|
|
eventfld.long 0x1C 22. " IRQENABLE22 ,Interrupt Enable For Channell 22" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 21. " IRQENABLE21 ,Interrupt Enable For Channell 21" "Disabled,Enabled"
|
|
eventfld.long 0x1C 20. " IRQENABLE20 ,Interrupt Enable For Channell 20" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 19. " IRQENABLE19 ,Interrupt Enable For Channell 19" "Disabled,Enabled"
|
|
eventfld.long 0x1C 18. " IRQENABLE18 ,Interrupt Enable For Channell 18" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 17. " IRQENABLE17 ,Interrupt Enable For Channell 17" "Disabled,Enabled"
|
|
eventfld.long 0x1C 16. " IRQENABLE16 ,Interrupt Enable For Channell 16" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 15. " IRQENABLE15 ,Interrupt Enable For Channell 15" "Disabled,Enabled"
|
|
eventfld.long 0x1C 14. " IRQENABLE14 ,Interrupt Enable For Channell 14" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 13. " IRQENABLE13 ,Interrupt Enable For Channell 13" "Disabled,Enabled"
|
|
eventfld.long 0x1C 12. " IRQENABLE12 ,Interrupt Enable For Channell 12" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 11. " IRQENABLE11 ,Interrupt Enable For Channell 11" "Disabled,Enabled"
|
|
eventfld.long 0x1C 10. " IRQENABLE10 ,Interrupt Enable For Channell 10" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 9. " IRQENABLE9 ,Interrupt Enable For Channell 9" "Disabled,Enabled"
|
|
eventfld.long 0x1C 8. " IRQENABLE8 ,Interrupt Enable For Channell 8" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 7. " IRQENABLE7 ,Interrupt Enable For Channell 7" "Disabled,Enabled"
|
|
eventfld.long 0x1C 6. " IRQENABLE6 ,Interrupt Enable For Channell 6" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 5. " IRQENABLE5 ,Interrupt Enable For Channell 5" "Disabled,Enabled"
|
|
eventfld.long 0x1C 4. " IRQENABLE4 ,Interrupt Enable For Channell 4" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 3. " IRQENABLE3 ,Interrupt Enable For Channell 3" "Disabled,Enabled"
|
|
eventfld.long 0x1C 2. " IRQENABLE2 ,Interrupt Enable For Channell 2" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x1C 1. " IRQENABLE1 ,Interrupt Enable For Channell 1" "Disabled,Enabled"
|
|
eventfld.long 0x1C 0. " IRQENABLE0 ,Interrupt Enable For Channell 0" "Disabled,Enabled"
|
|
line.long 0x20 "DMA4_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x20 0. " RESETDONE ,Internal reset monitoring" "On-going,Completed"
|
|
line.long 0x24 "DMA4_OCP_SYSCONFIG,Various Parameters Of The OCP Interface Control Register"
|
|
bitfld.long 0x24 12.--13. " MIDLEMODE ,Read power management standby control" "Forced-standby,No-standby,Smart-standby,?..."
|
|
textline " "
|
|
bitfld.long 0x24 9. " CLOCKACTIVITY1 ,Clocks activities during wake-up (Functional clock)" "Switched-off,Switched-on"
|
|
textline " "
|
|
bitfld.long 0x24 8. " CLOCKACTIVITY2 ,Clocks activities during wake-up (OCP interface clock)" "Switched-off,Switched-on"
|
|
textline " "
|
|
bitfld.long 0x24 5. " EMUFREE ,Enable sensitivity to MSuspend" "Frozen,Ignored"
|
|
textline " "
|
|
bitfld.long 0x24 3.--4. " SIDLEMODE ,Configuration port power management (idle control)" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x24 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x24 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Free running,Applied"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "DMA4_CAPS_0,DMA Capabilities Register 0 LSW"
|
|
bitfld.long 0x00 19. " CONST_FILL_CPBLTY ,Constant_Fill_Capability" "No LCH,Any LCH"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TRANSPARENT_BLT_CPBLTY ,Transparent_BLT_Capability" "No LCH,Any LCH"
|
|
group.long 0x6C++0xF
|
|
line.long 0x00 "DMA4_CAPS_2,DMA Capabilities Register 2"
|
|
bitfld.long 0x00 8. " SEPARATE_SRC_AND_DST_INDEX_CPBLTY ,Separate source/destination index capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DST_DOUBLE_INDEX_ADRS_CPBLTY ,Destination double index address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DST_SINGLE_INDEX_ADRS_CPBLTY ,Destination single index address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DST_POST_INCRMNT_ADRS_CPBLTY ,Destination post increment address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DST_CONST_ADRS_CPBLTY ,Destination constant address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SRC_DOUBLE_INDEX_ADRS_CPBLTY ,Source double index address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SRC_SINGLE_INDEX_ADRS_CPBLTY ,Source single index address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRC_POST_INCREMENT_ADRS_CPBLTY ,Source post increment address capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SRC_CONST_ADRS_CPBLTY ,Source constant address capability" "Not supported,Supported"
|
|
line.long 0x04 "DMA4_CAPS_3,DMA Capabilities Register 3"
|
|
bitfld.long 0x04 7. " BLOCK_SYNCHR_CPBLTY ,Block_synchronization_capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 6. " PKT_SYNCHR_CPBLTY ,Packet_synchronization_capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CHANNEL_CHAINING_CPBLTY ,Channel_chaining_capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 4. " LCH_INTERLEAVE_CPBLTY ,LCh_interleave_capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FRAME_SYNCHR_CPBLTY ,Frame_synchronization_capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ELMNT_SYNCHR_CPBLTY ,Element_synchronization_capability" "Not supported,Supported"
|
|
line.long 0x08 "DMA4_CAPS_4,DMA Capabilities Register 4"
|
|
bitfld.long 0x08 7. " PKT_INTERRUPT_CPBLTY ,End of Packet detection capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 6. " SYNC_STATUS_CPBLTY ,Sync_status_capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 5. " BLOCK_INTERRUPT_CPBLTY ,End of block detection capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 4. " LAST_FRAME_INTERRUPT_CPBLTY ,Start of last frame detection capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 3. " FRAME_INTERRUPT_CPBLTY ,End of frame detection capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 2. " HALF_FRAME_INTERRUPT_CPBLTY ,Detection capability of the half of frame end" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x08 1. " EVENT_DROP_INTERRUPT_CPBLTY ,Request collision detection capability" "Not supported,Supported"
|
|
line.long 0x0C "DMA4_GCR,FIFO Sharing Between High And Low Priority Channel"
|
|
hexmask.long.byte 0x0C 16.--23. 1. " ARBITRATION_RATE ,Arbitration switching rate between prioritized and regular channel queues"
|
|
textline " "
|
|
bitfld.long 0x0C 14.--15. " HI_LO_FIFO_BUDGET ,Separate gloabal FIFO budget for high and low priority channels" "No budget,75% low/25% high,25% low/75% high,50% low/50% high"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " HI_THREAD_RESERVED ,Thread reservation for high priority channel on r/w ports" "No reservation,Port0,Port0/Port1,Port0/Port1/Port2"
|
|
textline " "
|
|
hexmask.long.byte 0x0C 0.--7. 1. " MAX_CHANNEL_FIFO_DEPTH ,Maximum FIFO depth allocated to one logical channel"
|
|
width 0xb
|
|
tree.end
|
|
tree "Channels Registers"
|
|
width 19.
|
|
tree "Channel 0"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "DMA4_CCR_0,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x80+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_0,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x80+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_0,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x80+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_0,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x80+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_0,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x80+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_0,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x80+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_0,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x80+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_0,Channel Source Start Address"
|
|
group.long (0x80+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_0,Channel Destination Start Address"
|
|
group.long (0x80+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_0,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x80+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_0,Channel Source Frame Index"
|
|
group.long (0x80+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_0,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x80+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_0,Channel Destination Frame Index"
|
|
group.long (0x80+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_0,Channel Source Address Value"
|
|
group.long (0x80+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_0,Channel Destination Address Value"
|
|
group.long (0x80+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_0,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x80+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_0,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x80+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_0,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 1"
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "DMA4_CCR_1,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xE0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_1,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xE0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_1,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xE0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_1,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xE0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_1,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xE0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_1,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xE0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_1,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xE0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_1,Channel Source Start Address"
|
|
group.long (0xE0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_1,Channel Destination Start Address"
|
|
group.long (0xE0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_1,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xE0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_1,Channel Source Frame Index"
|
|
group.long (0xE0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_1,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xE0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_1,Channel Destination Frame Index"
|
|
group.long (0xE0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_1,Channel Source Address Value"
|
|
group.long (0xE0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_1,Channel Destination Address Value"
|
|
group.long (0xE0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_1,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xE0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_1,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xE0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_1,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 2"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "DMA4_CCR_2,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x140+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_2,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x140+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_2,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x140+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_2,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x140+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_2,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x140+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_2,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x140+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_2,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x140+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_2,Channel Source Start Address"
|
|
group.long (0x140+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_2,Channel Destination Start Address"
|
|
group.long (0x140+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_2,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x140+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_2,Channel Source Frame Index"
|
|
group.long (0x140+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_2,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x140+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_2,Channel Destination Frame Index"
|
|
group.long (0x140+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_2,Channel Source Address Value"
|
|
group.long (0x140+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_2,Channel Destination Address Value"
|
|
group.long (0x140+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_2,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x140+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_2,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x140+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_2,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 3"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x00 "DMA4_CCR_3,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x1A0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_3,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x1A0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_3,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x1A0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_3,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x1A0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_3,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x1A0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_3,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x1A0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_3,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x1A0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_3,Channel Source Start Address"
|
|
group.long (0x1A0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_3,Channel Destination Start Address"
|
|
group.long (0x1A0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_3,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x1A0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_3,Channel Source Frame Index"
|
|
group.long (0x1A0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_3,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x1A0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_3,Channel Destination Frame Index"
|
|
group.long (0x1A0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_3,Channel Source Address Value"
|
|
group.long (0x1A0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_3,Channel Destination Address Value"
|
|
group.long (0x1A0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_3,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x1A0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_3,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x1A0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_3,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 4"
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "DMA4_CCR_4,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x200+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_4,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x200+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_4,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x200+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_4,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x200+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_4,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x200+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_4,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x200+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_4,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x200+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_4,Channel Source Start Address"
|
|
group.long (0x200+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_4,Channel Destination Start Address"
|
|
group.long (0x200+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_4,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x200+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_4,Channel Source Frame Index"
|
|
group.long (0x200+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_4,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x200+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_4,Channel Destination Frame Index"
|
|
group.long (0x200+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_4,Channel Source Address Value"
|
|
group.long (0x200+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_4,Channel Destination Address Value"
|
|
group.long (0x200+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_4,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x200+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_4,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x200+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_4,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 5"
|
|
group.long 0x260++0x3
|
|
line.long 0x00 "DMA4_CCR_5,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x260+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_5,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x260+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_5,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x260+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_5,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x260+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_5,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x260+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_5,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x260+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_5,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x260+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_5,Channel Source Start Address"
|
|
group.long (0x260+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_5,Channel Destination Start Address"
|
|
group.long (0x260+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_5,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x260+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_5,Channel Source Frame Index"
|
|
group.long (0x260+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_5,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x260+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_5,Channel Destination Frame Index"
|
|
group.long (0x260+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_5,Channel Source Address Value"
|
|
group.long (0x260+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_5,Channel Destination Address Value"
|
|
group.long (0x260+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_5,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x260+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_5,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x260+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_5,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 6"
|
|
group.long 0x2C0++0x3
|
|
line.long 0x00 "DMA4_CCR_6,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x2C0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_6,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x2C0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_6,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x2C0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_6,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x2C0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_6,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x2C0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_6,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x2C0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_6,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x2C0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_6,Channel Source Start Address"
|
|
group.long (0x2C0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_6,Channel Destination Start Address"
|
|
group.long (0x2C0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_6,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x2C0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_6,Channel Source Frame Index"
|
|
group.long (0x2C0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_6,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x2C0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_6,Channel Destination Frame Index"
|
|
group.long (0x2C0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_6,Channel Source Address Value"
|
|
group.long (0x2C0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_6,Channel Destination Address Value"
|
|
group.long (0x2C0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_6,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x2C0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_6,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x2C0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_6,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 7"
|
|
group.long 0x320++0x3
|
|
line.long 0x00 "DMA4_CCR_7,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x320+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_7,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x320+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_7,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x320+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_7,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x320+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_7,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x320+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_7,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x320+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_7,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x320+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_7,Channel Source Start Address"
|
|
group.long (0x320+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_7,Channel Destination Start Address"
|
|
group.long (0x320+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_7,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x320+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_7,Channel Source Frame Index"
|
|
group.long (0x320+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_7,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x320+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_7,Channel Destination Frame Index"
|
|
group.long (0x320+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_7,Channel Source Address Value"
|
|
group.long (0x320+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_7,Channel Destination Address Value"
|
|
group.long (0x320+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_7,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x320+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_7,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x320+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_7,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 8"
|
|
group.long 0x380++0x3
|
|
line.long 0x00 "DMA4_CCR_8,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x380+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_8,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x380+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_8,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x380+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_8,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x380+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_8,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x380+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_8,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x380+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_8,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x380+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_8,Channel Source Start Address"
|
|
group.long (0x380+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_8,Channel Destination Start Address"
|
|
group.long (0x380+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_8,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x380+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_8,Channel Source Frame Index"
|
|
group.long (0x380+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_8,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x380+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_8,Channel Destination Frame Index"
|
|
group.long (0x380+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_8,Channel Source Address Value"
|
|
group.long (0x380+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_8,Channel Destination Address Value"
|
|
group.long (0x380+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_8,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x380+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_8,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x380+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_8,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 9"
|
|
group.long 0x3E0++0x3
|
|
line.long 0x00 "DMA4_CCR_9,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x3E0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_9,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x3E0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_9,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x3E0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_9,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x3E0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_9,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x3E0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_9,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x3E0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_9,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x3E0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_9,Channel Source Start Address"
|
|
group.long (0x3E0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_9,Channel Destination Start Address"
|
|
group.long (0x3E0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_9,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x3E0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_9,Channel Source Frame Index"
|
|
group.long (0x3E0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_9,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x3E0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_9,Channel Destination Frame Index"
|
|
group.long (0x3E0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_9,Channel Source Address Value"
|
|
group.long (0x3E0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_9,Channel Destination Address Value"
|
|
group.long (0x3E0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_9,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x3E0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_9,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x3E0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_9,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 10"
|
|
group.long 0x440++0x3
|
|
line.long 0x00 "DMA4_CCR_10,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x440+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_10,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x440+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_10,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x440+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_10,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x440+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_10,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x440+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_10,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x440+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_10,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x440+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_10,Channel Source Start Address"
|
|
group.long (0x440+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_10,Channel Destination Start Address"
|
|
group.long (0x440+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_10,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x440+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_10,Channel Source Frame Index"
|
|
group.long (0x440+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_10,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x440+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_10,Channel Destination Frame Index"
|
|
group.long (0x440+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_10,Channel Source Address Value"
|
|
group.long (0x440+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_10,Channel Destination Address Value"
|
|
group.long (0x440+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_10,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x440+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_10,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x440+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_10,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 11"
|
|
group.long 0x4A0++0x3
|
|
line.long 0x00 "DMA4_CCR_11,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x4A0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_11,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x4A0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_11,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x4A0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_11,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x4A0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_11,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x4A0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_11,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x4A0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_11,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x4A0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_11,Channel Source Start Address"
|
|
group.long (0x4A0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_11,Channel Destination Start Address"
|
|
group.long (0x4A0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_11,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x4A0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_11,Channel Source Frame Index"
|
|
group.long (0x4A0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_11,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x4A0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_11,Channel Destination Frame Index"
|
|
group.long (0x4A0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_11,Channel Source Address Value"
|
|
group.long (0x4A0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_11,Channel Destination Address Value"
|
|
group.long (0x4A0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_11,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x4A0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_11,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x4A0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_11,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 12"
|
|
group.long 0x500++0x3
|
|
line.long 0x00 "DMA4_CCR_12,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x500+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_12,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x500+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_12,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x500+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_12,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x500+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_12,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x500+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_12,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x500+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_12,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x500+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_12,Channel Source Start Address"
|
|
group.long (0x500+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_12,Channel Destination Start Address"
|
|
group.long (0x500+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_12,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x500+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_12,Channel Source Frame Index"
|
|
group.long (0x500+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_12,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x500+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_12,Channel Destination Frame Index"
|
|
group.long (0x500+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_12,Channel Source Address Value"
|
|
group.long (0x500+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_12,Channel Destination Address Value"
|
|
group.long (0x500+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_12,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x500+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_12,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x500+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_12,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 13"
|
|
group.long 0x560++0x3
|
|
line.long 0x00 "DMA4_CCR_13,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x560+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_13,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x560+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_13,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x560+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_13,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x560+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_13,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x560+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_13,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x560+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_13,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x560+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_13,Channel Source Start Address"
|
|
group.long (0x560+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_13,Channel Destination Start Address"
|
|
group.long (0x560+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_13,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x560+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_13,Channel Source Frame Index"
|
|
group.long (0x560+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_13,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x560+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_13,Channel Destination Frame Index"
|
|
group.long (0x560+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_13,Channel Source Address Value"
|
|
group.long (0x560+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_13,Channel Destination Address Value"
|
|
group.long (0x560+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_13,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x560+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_13,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x560+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_13,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 14"
|
|
group.long 0x5C0++0x3
|
|
line.long 0x00 "DMA4_CCR_14,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x5C0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_14,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x5C0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_14,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x5C0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_14,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x5C0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_14,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x5C0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_14,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x5C0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_14,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x5C0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_14,Channel Source Start Address"
|
|
group.long (0x5C0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_14,Channel Destination Start Address"
|
|
group.long (0x5C0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_14,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x5C0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_14,Channel Source Frame Index"
|
|
group.long (0x5C0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_14,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x5C0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_14,Channel Destination Frame Index"
|
|
group.long (0x5C0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_14,Channel Source Address Value"
|
|
group.long (0x5C0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_14,Channel Destination Address Value"
|
|
group.long (0x5C0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_14,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x5C0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_14,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x5C0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_14,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 15"
|
|
group.long 0x620++0x3
|
|
line.long 0x00 "DMA4_CCR_15,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x620+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_15,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x620+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_15,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x620+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_15,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x620+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_15,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x620+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_15,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x620+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_15,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x620+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_15,Channel Source Start Address"
|
|
group.long (0x620+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_15,Channel Destination Start Address"
|
|
group.long (0x620+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_15,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x620+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_15,Channel Source Frame Index"
|
|
group.long (0x620+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_15,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x620+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_15,Channel Destination Frame Index"
|
|
group.long (0x620+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_15,Channel Source Address Value"
|
|
group.long (0x620+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_15,Channel Destination Address Value"
|
|
group.long (0x620+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_15,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x620+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_15,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x620+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_15,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 16"
|
|
group.long 0x680++0x3
|
|
line.long 0x00 "DMA4_CCR_16,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x680+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_16,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x680+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_16,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x680+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_16,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x680+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_16,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x680+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_16,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x680+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_16,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x680+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_16,Channel Source Start Address"
|
|
group.long (0x680+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_16,Channel Destination Start Address"
|
|
group.long (0x680+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_16,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x680+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_16,Channel Source Frame Index"
|
|
group.long (0x680+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_16,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x680+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_16,Channel Destination Frame Index"
|
|
group.long (0x680+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_16,Channel Source Address Value"
|
|
group.long (0x680+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_16,Channel Destination Address Value"
|
|
group.long (0x680+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_16,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x680+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_16,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x680+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_16,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 17"
|
|
group.long 0x6E0++0x3
|
|
line.long 0x00 "DMA4_CCR_17,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x6E0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_17,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x6E0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_17,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x6E0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_17,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x6E0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_17,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x6E0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_17,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x6E0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_17,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x6E0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_17,Channel Source Start Address"
|
|
group.long (0x6E0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_17,Channel Destination Start Address"
|
|
group.long (0x6E0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_17,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x6E0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_17,Channel Source Frame Index"
|
|
group.long (0x6E0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_17,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x6E0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_17,Channel Destination Frame Index"
|
|
group.long (0x6E0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_17,Channel Source Address Value"
|
|
group.long (0x6E0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_17,Channel Destination Address Value"
|
|
group.long (0x6E0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_17,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x6E0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_17,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x6E0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_17,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 18"
|
|
group.long 0x740++0x3
|
|
line.long 0x00 "DMA4_CCR_18,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x740+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_18,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x740+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_18,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x740+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_18,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x740+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_18,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x740+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_18,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x740+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_18,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x740+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_18,Channel Source Start Address"
|
|
group.long (0x740+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_18,Channel Destination Start Address"
|
|
group.long (0x740+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_18,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x740+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_18,Channel Source Frame Index"
|
|
group.long (0x740+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_18,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x740+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_18,Channel Destination Frame Index"
|
|
group.long (0x740+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_18,Channel Source Address Value"
|
|
group.long (0x740+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_18,Channel Destination Address Value"
|
|
group.long (0x740+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_18,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x740+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_18,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x740+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_18,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 19"
|
|
group.long 0x7A0++0x3
|
|
line.long 0x00 "DMA4_CCR_19,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x7A0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_19,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x7A0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_19,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x7A0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_19,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x7A0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_19,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x7A0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_19,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x7A0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_19,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x7A0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_19,Channel Source Start Address"
|
|
group.long (0x7A0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_19,Channel Destination Start Address"
|
|
group.long (0x7A0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_19,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x7A0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_19,Channel Source Frame Index"
|
|
group.long (0x7A0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_19,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x7A0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_19,Channel Destination Frame Index"
|
|
group.long (0x7A0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_19,Channel Source Address Value"
|
|
group.long (0x7A0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_19,Channel Destination Address Value"
|
|
group.long (0x7A0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_19,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x7A0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_19,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x7A0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_19,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 20"
|
|
group.long 0x800++0x3
|
|
line.long 0x00 "DMA4_CCR_20,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x800+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_20,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x800+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_20,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x800+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_20,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x800+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_20,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x800+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_20,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x800+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_20,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x800+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_20,Channel Source Start Address"
|
|
group.long (0x800+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_20,Channel Destination Start Address"
|
|
group.long (0x800+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_20,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x800+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_20,Channel Source Frame Index"
|
|
group.long (0x800+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_20,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x800+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_20,Channel Destination Frame Index"
|
|
group.long (0x800+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_20,Channel Source Address Value"
|
|
group.long (0x800+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_20,Channel Destination Address Value"
|
|
group.long (0x800+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_20,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x800+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_20,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x800+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_20,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 21"
|
|
group.long 0x860++0x3
|
|
line.long 0x00 "DMA4_CCR_21,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x860+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_21,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x860+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_21,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x860+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_21,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x860+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_21,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x860+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_21,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x860+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_21,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x860+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_21,Channel Source Start Address"
|
|
group.long (0x860+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_21,Channel Destination Start Address"
|
|
group.long (0x860+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_21,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x860+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_21,Channel Source Frame Index"
|
|
group.long (0x860+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_21,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x860+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_21,Channel Destination Frame Index"
|
|
group.long (0x860+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_21,Channel Source Address Value"
|
|
group.long (0x860+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_21,Channel Destination Address Value"
|
|
group.long (0x860+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_21,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x860+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_21,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x860+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_21,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 22"
|
|
group.long 0x8C0++0x3
|
|
line.long 0x00 "DMA4_CCR_22,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x8C0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_22,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x8C0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_22,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x8C0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_22,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x8C0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_22,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x8C0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_22,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x8C0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_22,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x8C0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_22,Channel Source Start Address"
|
|
group.long (0x8C0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_22,Channel Destination Start Address"
|
|
group.long (0x8C0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_22,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x8C0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_22,Channel Source Frame Index"
|
|
group.long (0x8C0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_22,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x8C0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_22,Channel Destination Frame Index"
|
|
group.long (0x8C0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_22,Channel Source Address Value"
|
|
group.long (0x8C0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_22,Channel Destination Address Value"
|
|
group.long (0x8C0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_22,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x8C0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_22,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x8C0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_22,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 23"
|
|
group.long 0x920++0x3
|
|
line.long 0x00 "DMA4_CCR_23,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x920+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_23,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x920+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_23,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x920+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_23,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x920+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_23,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x920+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_23,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x920+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_23,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x920+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_23,Channel Source Start Address"
|
|
group.long (0x920+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_23,Channel Destination Start Address"
|
|
group.long (0x920+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_23,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x920+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_23,Channel Source Frame Index"
|
|
group.long (0x920+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_23,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x920+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_23,Channel Destination Frame Index"
|
|
group.long (0x920+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_23,Channel Source Address Value"
|
|
group.long (0x920+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_23,Channel Destination Address Value"
|
|
group.long (0x920+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_23,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x920+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_23,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x920+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_23,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 24"
|
|
group.long 0x980++0x3
|
|
line.long 0x00 "DMA4_CCR_24,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x980+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_24,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x980+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_24,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x980+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_24,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x980+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_24,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x980+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_24,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x980+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_24,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x980+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_24,Channel Source Start Address"
|
|
group.long (0x980+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_24,Channel Destination Start Address"
|
|
group.long (0x980+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_24,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x980+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_24,Channel Source Frame Index"
|
|
group.long (0x980+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_24,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x980+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_24,Channel Destination Frame Index"
|
|
group.long (0x980+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_24,Channel Source Address Value"
|
|
group.long (0x980+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_24,Channel Destination Address Value"
|
|
group.long (0x980+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_24,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x980+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_24,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x980+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_24,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 25"
|
|
group.long 0x9E0++0x3
|
|
line.long 0x00 "DMA4_CCR_25,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x9E0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_25,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x9E0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_25,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0x9E0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_25,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0x9E0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_25,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0x9E0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_25,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0x9E0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_25,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0x9E0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_25,Channel Source Start Address"
|
|
group.long (0x9E0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_25,Channel Destination Start Address"
|
|
group.long (0x9E0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_25,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0x9E0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_25,Channel Source Frame Index"
|
|
group.long (0x9E0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_25,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0x9E0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_25,Channel Destination Frame Index"
|
|
group.long (0x9E0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_25,Channel Source Address Value"
|
|
group.long (0x9E0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_25,Channel Destination Address Value"
|
|
group.long (0x9E0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_25,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0x9E0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_25,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0x9E0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_25,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 26"
|
|
group.long 0xA40++0x3
|
|
line.long 0x00 "DMA4_CCR_26,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xA40+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_26,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xA40+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_26,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xA40+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_26,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xA40+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_26,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xA40+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_26,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xA40+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_26,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xA40+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_26,Channel Source Start Address"
|
|
group.long (0xA40+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_26,Channel Destination Start Address"
|
|
group.long (0xA40+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_26,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xA40+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_26,Channel Source Frame Index"
|
|
group.long (0xA40+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_26,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xA40+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_26,Channel Destination Frame Index"
|
|
group.long (0xA40+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_26,Channel Source Address Value"
|
|
group.long (0xA40+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_26,Channel Destination Address Value"
|
|
group.long (0xA40+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_26,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xA40+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_26,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xA40+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_26,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 27"
|
|
group.long 0xAA0++0x3
|
|
line.long 0x00 "DMA4_CCR_27,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xAA0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_27,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xAA0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_27,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xAA0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_27,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xAA0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_27,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xAA0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_27,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xAA0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_27,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xAA0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_27,Channel Source Start Address"
|
|
group.long (0xAA0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_27,Channel Destination Start Address"
|
|
group.long (0xAA0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_27,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xAA0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_27,Channel Source Frame Index"
|
|
group.long (0xAA0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_27,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xAA0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_27,Channel Destination Frame Index"
|
|
group.long (0xAA0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_27,Channel Source Address Value"
|
|
group.long (0xAA0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_27,Channel Destination Address Value"
|
|
group.long (0xAA0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_27,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xAA0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_27,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xAA0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_27,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 28"
|
|
group.long 0xB00++0x3
|
|
line.long 0x00 "DMA4_CCR_28,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xB00+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_28,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xB00+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_28,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xB00+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_28,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xB00+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_28,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xB00+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_28,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xB00+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_28,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xB00+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_28,Channel Source Start Address"
|
|
group.long (0xB00+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_28,Channel Destination Start Address"
|
|
group.long (0xB00+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_28,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xB00+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_28,Channel Source Frame Index"
|
|
group.long (0xB00+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_28,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xB00+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_28,Channel Destination Frame Index"
|
|
group.long (0xB00+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_28,Channel Source Address Value"
|
|
group.long (0xB00+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_28,Channel Destination Address Value"
|
|
group.long (0xB00+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_28,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xB00+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_28,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xB00+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_28,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 29"
|
|
group.long 0xB60++0x3
|
|
line.long 0x00 "DMA4_CCR_29,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xB60+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_29,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xB60+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_29,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xB60+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_29,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xB60+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_29,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xB60+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_29,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xB60+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_29,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xB60+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_29,Channel Source Start Address"
|
|
group.long (0xB60+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_29,Channel Destination Start Address"
|
|
group.long (0xB60+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_29,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xB60+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_29,Channel Source Frame Index"
|
|
group.long (0xB60+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_29,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xB60+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_29,Channel Destination Frame Index"
|
|
group.long (0xB60+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_29,Channel Source Address Value"
|
|
group.long (0xB60+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_29,Channel Destination Address Value"
|
|
group.long (0xB60+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_29,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xB60+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_29,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xB60+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_29,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 30"
|
|
group.long 0xBC0++0x3
|
|
line.long 0x00 "DMA4_CCR_30,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xBC0+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_30,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xBC0+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_30,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xBC0+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_30,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xBC0+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_30,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xBC0+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_30,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xBC0+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_30,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xBC0+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_30,Channel Source Start Address"
|
|
group.long (0xBC0+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_30,Channel Destination Start Address"
|
|
group.long (0xBC0+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_30,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xBC0+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_30,Channel Source Frame Index"
|
|
group.long (0xBC0+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_30,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xBC0+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_30,Channel Destination Frame Index"
|
|
group.long (0xBC0+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_30,Channel Source Address Value"
|
|
group.long (0xBC0+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_30,Channel Destination Address Value"
|
|
group.long (0xBC0+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_30,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xBC0+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_30,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xBC0+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_30,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
tree "Channel 31"
|
|
group.long 0xC20++0x3
|
|
line.long 0x00 "DMA4_CCR_31,Channel Control Register"
|
|
bitfld.long 0x00 26. " WRITE_PRIORITY ,Channel priority on the Write side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " BUFFERING_DISABLE ,Disable buffering functionality when transfer is source synchronized" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " SEL_SRC_DST_SYNC ,Triggered by source or the destination on the DMA request" "Destination,Source"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PREFETCH ,Enables the prefetch mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " SUPERVISOR ,Enables the supervisor mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SECURE ,Secure transaction over the channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19.--20. " SYNCHRO_CONTROL_UPPER ,Channel Synchronization control upper" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TRANSPARENT_COPY_ENABLE ,Transparent copy enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONST_FILL_ENABLE ,Constant fill enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_AMODE ,Addressing mode on the Write Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SRC_AMODE ,Addressing mode on the Read Port" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WR_ACTIVE ,Channel write context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RD_ACTIVE ,Channel read context active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SUSPEND_SENSITIVE ,Logical channel suspend enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ENABLE ,Logical channel enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " READ_PRIORITY ,Channel priority on the read side" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. 18. " FS_BS ,Frame/Block synchronization" "Element,Block,Frame,Packet"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " SYNCHRO_CONTROL ,Channel synchronization control" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xC20+0x4)++0x3
|
|
line.long 0x00 "DMA4_CLNK_CTRL_31,Channel Link Control Register"
|
|
bitfld.long 0x00 15. " ENABLE_LNK ,Channel linking enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " NEXTLCH_ID ,Defines the NextLCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xC20+0x8)++0x3
|
|
line.long 0x00 "DMA4_CICR_31,Channel Interrupt Control Register"
|
|
bitfld.long 0x00 12. " DRAIN_IE ,Enables the end of draining interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MISALIGNED_ERR_IE ,Enables the address misaligned error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SUPERVISOR_ERR_IE ,Enables the supervisor transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " SECURE_ERR_IE ,Enables the secure transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TRANS_ERR_IE ,Enables the transaction error event interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PKT_IE ,Enables the end of Packet interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLOCK_IE ,Enables the end of block interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LAST_IE ,Last frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FRAME_IE ,Frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " HALF_IE ,Half frame interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable" "Disabled,Enabled"
|
|
group.long (0xC20+0xC)++0x3
|
|
line.long 0x00 "DMA4_CSR_31,Channel Status Register"
|
|
eventfld.long 0x00 12. " DRAIN_END ,End of channel drainiing" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 11. " MISALIGNED_ADRS_ERR ,Misaligned address error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 10. " SUPERVISOR_ERR ,Supervisor transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 9. " SECURE_ERR ,Secure transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TRANS_ERR ,Transaction error event" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 7. " PKT ,End of Packet transfer" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " SYNC ,Synchronization status of a channel" "Not synchronized,Synchronized"
|
|
textline " "
|
|
eventfld.long 0x00 5. " BLOCK ,End of block" "Not finished,Transferred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " LAST ,Last frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 3. " FRAME ,End of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " HALF ,Half of frame event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 1. " DROP ,Synchronization event drop occured during the transfer" "No colision,Reset"
|
|
group.long (0xC20+0x10)++0x3
|
|
line.long 0x00 "DMA4_CSDP_31,Channel Source Destination Parameters"
|
|
bitfld.long 0x00 21. " SRC_ENDIAN ,Channel source endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SRC_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DST_ENDIAN ,Channel Destination endianness control" "Little Endian,Big Endian"
|
|
textline " "
|
|
bitfld.long 0x00 18. " DST_ENDIAN_LOCK ,Endianness Lock" "Adapted,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WRITE_MODE ,Used to enable writing mode without posting or with posting" "Not posted,Posted,All posted except last,?..."
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DST_BURST_EN ,Used to enable bursting on the Write Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DST_PACKED ,Destination receives packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 9.--12. " WR_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the write port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7.--8. " SRC_BURST_EN ,Used to enable bursting on the Read Port" "Single access,16 bytes or 4x32/2x64-bit,32 bytes or 8x32/4x64-bit,64 bytes or 16x32/8x64-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRC_PACKED ,Source provides packed data" "Non packed,Packed"
|
|
textline " "
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 2.--5. " RD_ADD_TRSLT ,Enables the MReqAddressTranslate sideband signal in the read port side" "Reserved,Reserved,Reserved,Enabled,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel (scalar)" "8 bits,16 bits,32 bits,?..."
|
|
group.long (0xC20+0x14)++0x3
|
|
line.long 0x00 "DMA4_CEN_31,Channel Element Number"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CHANNEL_ELMNT_NBR ,Number of elements within a frame (unsigned) to transfer"
|
|
group.long (0xC20+0x18)++0x3
|
|
line.long 0x00 "DMA4_CFN_31,Channel Frame Number"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_FRAME_NBR ,Number of frames within the block to be transferred"
|
|
group.long (0xC20+0x1C)++0x3
|
|
line.long 0x00 "DMA4_CSSA_31,Channel Source Start Address"
|
|
group.long (0xC20+0x20)++0x3
|
|
line.long 0x00 "DMA4_CDSA_31,Channel Destination Start Address"
|
|
group.long (0xC20+0x24)++0x3
|
|
line.long 0x00 "DMA4_CSEI_31,Channel Source Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_SRC_ELMNT_INDEX ,Channel source element index"
|
|
group.long (0xC20+0x28)++0x3
|
|
line.long 0x00 "DMA4_CSFI_31,Channel Source Frame Index"
|
|
group.long (0xC20+0x2C)++0x3
|
|
line.long 0x00 "DMA4_CDEI_31,Channel Destination Element Index"
|
|
hexmask.long.word 0x00 0.--15. 1. " CHANNEL_DST_ELMNT_INDEX ,Channel destination element index"
|
|
group.long (0xC20+0x30)++0x3
|
|
line.long 0x00 "DMA4_CDFI_31,Channel Destination Frame Index"
|
|
group.long (0xC20+0x34)++0x3
|
|
line.long 0x00 "DMA4_CSAC_31,Channel Source Address Value"
|
|
group.long (0xC20+0x38)++0x3
|
|
line.long 0x00 "DMA4_CDAC_31,Channel Destination Address Value"
|
|
group.long (0xC20+0x3C)++0x3
|
|
line.long 0x00 "DMA4_CCEN_31,Channel Current Transferred Element Number In The Current Frame"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CURRENT_ELMNT_NBR ,Channel current transferred element number in the current frame"
|
|
group.long (0xC20+0x40)++0x3
|
|
line.long 0x00 "DMA4_CCFN_31,Channel Current Transferred Frame Number In The Current Transfer"
|
|
hexmask.long.word 0x00 0.--15. 1. " CURRENT_FRAME_NBR ,Channel current transferred frame number in the current transfer"
|
|
group.long (0xC20+0x44)++0x3
|
|
line.long 0x00 "DMA4_COLOR_31,Channel DMA COLOR KEY /SOLID COLOR"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " CH_BLT_FRGRND_COLOR_OR_SOLIDCOLORPTRN ,Color key or solid color pattern"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "Interrupt Controller Registers"
|
|
tree "MPU subsystem INTC"
|
|
base ad:0x48200000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "INTCPS_SYSCONFIG,Various Parameters Of The Module Interface Control"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "INTCPS_SYSSTATUS,Module Status Information"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x00 "INTCPS_SIR_IRQ,Currently Active IRQ Interrupt Number"
|
|
hexmask.long 0x00 7.--31. 1. " SPURIOUSIRQFLAG ,Spurious IRQ flag"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " ACTIVEIRQ ,Active IRQ number"
|
|
line.long 0x04 "INTCPS_SIR_FIQ,Currently Active FIQ Interrupt Number"
|
|
hexmask.long 0x04 7.--31. 1. " SPURIOUSIRQFLAG ,Spurious FIQ flag"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--6. 1. " ACTIVEIRQ ,Active FIQ number"
|
|
group.long 0x48++0xb
|
|
line.long 0x00 "INTCPS_CONTROL,New Interrupt Agreement Bits"
|
|
bitfld.long 0x00 1. " NEWFIQAGR ,Reset FIQ output and enable new FIQ generation" "No effect,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NEWIRQAGR ,New IRQ generation" "No effect,Enabled"
|
|
line.long 0x04 "INTCPS_PROTECTION,Protection Of The Other Registers Control"
|
|
bitfld.long 0x04 0. " PROTECTION ,Protection mode" "Disabled,Enabled"
|
|
line.long 0x08 "INTCPS_IDLE,Functional Clock Auto-idle And The Synchronizer Clock Auto-gating Control"
|
|
bitfld.long 0x08 1. " TURBO ,Input synchronizer clock auto-gating" "Free-running,Auto-gated"
|
|
textline " "
|
|
bitfld.long 0x08 0. " FUNCIDLE ,Functional clock idle mode" "Applied,Free-running"
|
|
rgroup.long 0x60++0xb
|
|
line.long 0x00 "INTCPS_IRQ_PRIORITY,Currently Active IRQ Priority Level"
|
|
hexmask.long 0x00 6.--31. 1. " SPURIOUSIRQFLAG ,Spurious IRQ flag"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " IRQPRIORITY ,Current IRQ priority"
|
|
line.long 0x04 "INTCPS_FIQ_PRIORITY,Currently Active FIQ Priority Level"
|
|
hexmask.long 0x04 6.--31. 1. " SPURIOUSFIQFLAG ,Spurious FIQ flag"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--5. 1. " FIQPRIORITY ,Current FIQ priority"
|
|
line.long 0x08 "INTCPS_THRESHOLD,Priority Threshold Set"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRIORITYTHRESHOLD ,Priority threshold"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "INTCPS_ITR0,Raw Interrupt Input Status Before Masking"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x14 31. " M_IRQ_31_set/clr ,GPIO module 3 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x14 30. " M_IRQ_30_set/clr ,GPIO module 2 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x14 29. " M_IRQ_29_set/clr ,GPIO module 1 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x14 28. " M_IRQ_28_set/clr ,IVA2 MMU interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x14 27. " M_IRQ_27_set/clr ,McBSP module 5 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x14 26. " M_IRQ_26_set/clr ,Mailbox user 0 request interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x14 25. " M_IRQ_25_set/clr ,Display subsystem module interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x14 24. " M_IRQ_24_set/clr ,Camera interface request 0 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x14 23. " M_IRQ_23_set/clr ,McBSP module 4 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x14 22. " M_IRQ_22_set/clr ,McBSP module 3 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x14 21. " M_IRQ_21_set/clr ,SGX graphics module interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x14 20. " M_IRQ_20_set/clr ,General-purpose memory controller module interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x14 19. " M_IRQ_19_set/clr ,SmartReflex 2 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x14 18. " M_IRQ_18_set/clr ,SmartReflex 1 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x14 17. " M_IRQ_17_set/clr ,McBSP module 2 IRQ interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x14 16. " M_IRQ_16_set/clr ,McBSP module 1 IRQ interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x14 15. " M_IRQ_15_set/clr ,System DMA request 3 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x14 14. " M_IRQ_14_set/clr ,System DMA request 2 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x14 13. " M_IRQ_13_set/clr ,System DMA request 1 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x14 12. " M_IRQ_12_set/clr ,System DMA request 0 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x14 11. " M_IRQ_11_set/clr ,PRCM module IRQ interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x14 10. " M_IRQ_10_set/clr ,SMX error for application interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x14 9. " M_IRQ_9_set/clr ,SMX error for debug interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x14 8. " M_IRQ_8_set/clr ,Modem security violation interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x14 7. " M_IRQ_7_set/clr ,External source interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x14 6. " M_IRQ_6_set/clr ,MPU subsystem secure state-machine abort interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x14 5. " M_IRQ_5_set/clr ,Sidetone MCBSP3 overflow interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x14 4. " M_IRQ_4_set/clr ,Sidetone MCBSP2 overflow interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x14 3. " M_IRQ_3_set/clr ,BENCH MPU emulation interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x14 2. " M_IRQ_2_set/clr ,COMMRX MPU emulation interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x14 1. " M_IRQ_1_set/clr ,COMMTX MPU emulation interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x14 0. " M_IRQ_0_set/clr ,EMUINT MPU emulation interrupt status" "Interrupt,No interrupt"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "INTCPS_ITR1,Raw Interrupt Input Status Before Masking"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x14 31. " M_IRQ_63_set/clr ,McBSP module 2 receive interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 30. 0x10 30. 0x14 30. " M_IRQ_62_set/clr ,McBSP module 2 transmit interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x10 29. 0x14 29. " M_IRQ_61_set/clr ,I2C module 3 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 28. 0x10 28. 0x14 28. " M_IRQ_60_set/clr ,McBSP module 1 receive interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x10 27. 0x14 27. " M_IRQ_59_set/clr ,McBSP module 1 transmit interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 26. 0x10 26. 0x14 26. " M_IRQ_58_set/clr ,HDQ/One-wire interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x10 25. 0x14 25. " M_IRQ_57_set/clr ,I2C module 2 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 24. 0x10 24. 0x14 24. " M_IRQ_56_set/clr ,I2C module 1 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x10 23. 0x14 23. " M_IRQ_55_set/clr ,McBSP module 4 receive interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 22. 0x10 22. 0x14 22. " M_IRQ_54_set/clr ,McBSP module 4 transmit interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x10 21. 0x14 21. " M_IRQ_53_set/clr ,MG function interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 20. 0x10 20. 0x14 20. " M_IRQ_52_set/clr ,RNG module interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x10 19. 0x14 19. " M_IRQ_51_set/clr ,SHA-2/MD5 crypto-accelerator 1 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 18. 0x10 18. 0x14 18. " M_IRQ_50_set/clr ,PKA crypto-accelerator interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x10 17. 0x14 17. " M_IRQ_49_set/clr ,SHA-1/MD5 crypto-accelerator 2 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 16. 0x10 16. 0x14 16. " M_IRQ_48_set/clr ,McSPI module 4 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x14 15. " M_IRQ_47_set/clr ,General-purpose timer module 11 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 14. 0x10 14. 0x14 14. " M_IRQ_46_set/clr ,General-purpose timer module 10 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x10 13. 0x14 13. " M_IRQ_45_set/clr ,General-purpose timer module 9 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 12. 0x10 12. 0x14 12. " M_IRQ_44_set/clr ,General-purpose timer module 8 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x10 11. 0x14 11. " M_IRQ_43_set/clr ,General-purpose timer module 7 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 10. 0x10 10. 0x14 10. " M_IRQ_42_set/clr ,General-purpose timer module 6 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x10 9. 0x14 9. " M_IRQ_41_set/clr ,General-purpose timer module 5 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 8. 0x10 8. 0x14 8. " M_IRQ_40_set/clr ,General-purpose timer module 4 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x10 7. 0x14 7. " M_IRQ_39_set/clr ,General-purpose timer module 3 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 6. 0x10 6. 0x14 6. " M_IRQ_38_set/clr ,General-purpose timer module 2 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x10 5. 0x14 5. " M_IRQ_37_set/clr ,General-purpose timer module 1 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 4. 0x10 4. 0x14 4. " M_IRQ_36_set/clr ,Watchdog timer module 3 overflow interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x10 3. 0x14 3. " M_IRQ_35set/clr ,USIM interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 2. 0x10 2. 0x14 2. " M_IRQ_34set/clr ,GPIO module 6 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x10 1. 0x14 1. " M_IRQ_33set/clr ,GPIO module 5 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 0. 0x10 0. 0x14 0. " M_IRQ_32_set/clr ,GPIO module 4 interrupt status" "Interrupt,No interrupt"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "INTCPS_ITR2,Raw Interrupt Input Status Before Masking"
|
|
setclrfld.long 0x00 31. 0x10 31. 0x14 31. " M_IRQ_95_set/clr ,General-purpose timer module 12 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x10 30. 0x14 30. " M_IRQ_94_set/clr ,MMC/SD module 3" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 29. 0x10 29. 0x14 29. " M_IRQ_93_set/clr ,High-Speed USB OTG DMA controller interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x10 28. 0x14 28. " M_IRQ_92_set/clr ,High-Speed USB OTG controller interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 27. 0x10 27. 0x14 27. " M_IRQ_91_set/clr ,McSPI module 3 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x10 26. 0x14 26. " M_IRQ_90_set/clr ,McBSP module 3 receive interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 25. 0x10 25. 0x14 25. " M_IRQ_89_set/clr ,McBSP module 3 transmit interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x10 24. 0x14 24. " M_IRQ_88_set/clr ,From 3G coprocessor hardware interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 23. 0x10 23. 0x14 23. " M_IRQ_87_set/clr ,MPU ICR interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x10 22. 0x14 22. " M_IRQ_86_set/clr ,MMC/SD module 2 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x10 20. 0x14 20. " M_IRQ_84_set/clr ,MS-PRO module interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 19. 0x10 19. 0x14 19. " M_IRQ_83_set/clr ,MMC/SD module 1 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x10 18. 0x14 18. " M_IRQ_82_set/clr ,McBSP module 5 receive interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 17. 0x10 17. 0x14 17. " M_IRQ_81_set/clr ,McBSP module 5 transmit interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x10 15. 0x14 15. " M_IRQ_79_set/clr ,SHA2/MD5 crypto-accelerator 1" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x10 14. 0x14 14. " M_IRQ_78_set/clr ,HSUSB MP TLL Interrupt" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 13. 0x10 13. 0x14 13. " M_IRQ_77_set/clr ,EHCI controller HSUSB MP Host Interrupt" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x10 12. 0x14 12. " M_IRQ_76_set/clr ,OHCI controller HSUSB MP Host Interrupt" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 11. 0x10 11. 0x14 11. " M_IRQ_75_set/clr ,Merged interrupt for PBIASlite1 and 2" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x10 10. 0x14 10. " M_IRQ_74_set/clr ,UART module 3 (also infrared) interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 9. 0x10 9. 0x14 9. " M_IRQ_73_set/clr ,UART module 2 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x10 8. 0x14 8. " M_IRQ_72_set/clr ,UART module 1 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 7. 0x10 7. 0x14 7. " M_IRQ_71_set/clr ,Dual SSI GDD interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x10 6. 0x14 6. " M_IRQ_70_set/clr ,Dual SSI port 2 request 1 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 5. 0x10 5. 0x14 5. " M_IRQ_69_set/clr ,Dual SSI port 2 request 0 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x10 4. 0x14 4. " M_IRQ_68_set/clr ,Dual SSI port 1 request 1 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 3. 0x10 3. 0x14 3. " M_IRQ_67_set/clr ,Dual SSI port 1 request 0 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x10 2. 0x14 2. " M_IRQ_66_set/clr ,McSPI module 2 interrupt status" "Interrupt,No interrupt"
|
|
setclrfld.long 0x00 1. 0x10 1. 0x14 1. " M_IRQ_65_set/clr ,McSPI module 1 interrupt status" "Interrupt,No interrupt"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x10 0. 0x14 0. " M_IRQ_64_set/clr ,PKA crypto-accelerator interrupt status" "Interrupt,No interrupt"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "INTCPS_MIR0,Interrupt Mask"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x04 31. " M_IRQ_31_set/clr ,GPIO module 3 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x04 30. " M_IRQ_30_set/clr ,GPIO module 2 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x08 29. 0x04 29. " M_IRQ_29_set/clr ,GPIO module 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " M_IRQ_28_set/clr ,IVA2 MMU interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " M_IRQ_27_set/clr ,McBSP module 5 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x04 26. " M_IRQ_26_set/clr ,Mailbox user 0 request interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " M_IRQ_25_set/clr ,Display subsystem module interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x04 24. " M_IRQ_24_set/clr ,Camera interface request 0 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x08 23. 0x04 23. " M_IRQ_23_set/clr ,McBSP module 4 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 22. 0x08 22. 0x04 22. " M_IRQ_22_set/clr ,McBSP module 3 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x08 21. 0x04 21. " M_IRQ_21_set/clr ,SGX graphics module interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " M_IRQ_20_set/clr ,General-purpose memory controller module interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " M_IRQ_19_set/clr ,SmartReflex 2 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " M_IRQ_18_set/clr ,SmartReflex 1 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " M_IRQ_17_set/clr ,McBSP module 2 IRQ interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " M_IRQ_16_set/clr ,McBSP module 1 IRQ interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x08 15. 0x04 15. " M_IRQ_15_set/clr ,System DMA request 3 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " M_IRQ_14_set/clr ,System DMA request 2 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " M_IRQ_13_set/clr ,System DMA request 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " M_IRQ_12_set/clr ,System DMA request 0 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " M_IRQ_11_set/clr ,PRCM module IRQ interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " M_IRQ_10_set/clr ,SMX error for application interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " M_IRQ_9_set/clr ,SMX error for debug interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " M_IRQ_8_set/clr ,Modem security violation interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " M_IRQ_7_set/clr ,External source interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " M_IRQ_6_set/clr ,MPU subsystem secure state-machine abort interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " M_IRQ_5_set/clr ,Sidetone MCBSP3 overflow interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " M_IRQ_4_set/clr ,Sidetone MCBSP2 overflow interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " M_IRQ_3_set/clr ,BENCH MPU emulation interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " M_IRQ_2_set/clr ,COMMRX MPU emulation interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " M_IRQ_1_set/clr ,COMMTX MPU emulation interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " M_IRQ_0_set/clr ,EMUINT MPU emulation interrupt mask" "Not masked,Masked"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "INTCPS_MIR1,Interrupt Mask"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x04 31. " M_IRQ_63_set/clr ,McBSP module 2 receive interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 30. 0x08 30. 0x04 30. " M_IRQ_62_set/clr ,McBSP module 2 transmit interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x08 29. 0x04 29. " M_IRQ_61_set/clr ,I2C module 3 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " M_IRQ_60_set/clr ,McBSP module 1 receive interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " M_IRQ_59_set/clr ,McBSP module 1 transmit interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 26. 0x08 26. 0x04 26. " M_IRQ_58_set/clr ,HDQ/One-wire interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " M_IRQ_57_set/clr ,I2C module 2 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 24. 0x08 24. 0x04 24. " M_IRQ_56_set/clr ,I2C module 1 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x08 23. 0x04 23. " M_IRQ_55_set/clr ,McBSP module 4 receive interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 22. 0x08 22. 0x04 22. " M_IRQ_54_set/clr ,McBSP module 4 transmit interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x08 21. 0x04 21. " M_IRQ_53_set/clr ,MG function interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " M_IRQ_52_set/clr ,RNG module interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " M_IRQ_51_set/clr ,SHA-2/MD5 crypto-accelerator 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " M_IRQ_50_set/clr ,PKA crypto-accelerator interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " M_IRQ_49_set/clr ,SHA-1/MD5 crypto-accelerator 2 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " M_IRQ_48_set/clr ,McSPI module 4 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x08 15. 0x04 15. " M_IRQ_47_set/clr ,General-purpose timer module 11 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " M_IRQ_46_set/clr ,General-purpose timer module 10 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " M_IRQ_45_set/clr ,General-purpose timer module 9 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " M_IRQ_44_set/clr ,General-purpose timer module 8 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " M_IRQ_43_set/clr ,General-purpose timer module 7 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " M_IRQ_42_set/clr ,General-purpose timer module 6 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " M_IRQ_41_set/clr ,General-purpose timer module 5 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " M_IRQ_40_set/clr ,General-purpose timer module 4 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " M_IRQ_39_set/clr ,General-purpose timer module 3 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " M_IRQ_38_set/clr ,General-purpose timer module 2 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " M_IRQ_37_set/clr ,General-purpose timer module 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " M_IRQ_36_set/clr ,Watchdog timer module 3 overflow interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " M_IRQ_35_set/clr ,USIM interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " M_IRQ_34_set/clr ,GPIO module 6 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " M_IRQ_33set/clr ,GPIO module 5 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " M_IRQ_32_set/clr ,GPIO module 4 interrupt mask" "Not masked,Masked"
|
|
group.long 0xC4++0x3
|
|
line.long 0x00 "INTCPS_MIR2,Interrupt Mask"
|
|
setclrfld.long 0x00 31. 0x08 31. 0x04 31. " M_IRQ_95_set/clr ,General-purpose timer module 12 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 30. 0x08 30. 0x04 30. " M_IRQ_94_set/clr ,MMC/SD module 3 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 29. 0x08 29. 0x04 29. " M_IRQ_93_set/clr ,High-Speed USB OTG DMA controller interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " M_IRQ_92_set/clr ,High-Speed USB OTG controller interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " M_IRQ_91_set/clr ,McSPI module 3 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 26. 0x08 26. 0x04 26. " M_IRQ_90_set/clr ,McBSP module 3 receive interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " M_IRQ_89_set/clr ,McBSP module 3 transmit interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 24. 0x08 24. 0x04 24. " M_IRQ_88_set/clr ,From 3G coprocessor hardware interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 23. 0x08 23. 0x04 23. " M_IRQ_87_set/clr ,MPU ICR interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x08 22. 0x04 22. " M_IRQ_86_set/clr ,MMC/SD module 2 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " M_IRQ_84_set/clr ,MS-PRO module interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " M_IRQ_83_set/clr ,MMC/SD module 1 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " M_IRQ_82_set/clr ,McBSP module 5 receive interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " M_IRQ_81_set/clr ,McBSP module 5 transmit interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x08 15. 0x04 15. " M_IRQ_79_set/clr ,SHA2/MD5 crypto-accelerator 1 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " M_IRQ_78_set/clr ,HSUSB MP TLL interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " M_IRQ_77_set/clr ,EHCI controller HSUSB MP Host interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " M_IRQ_76_set/clr ,OHCI controller HSUSB MP Host interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " M_IRQ_75_set/clr ,Merged interrupt for PBIASlite1 and 2 mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " M_IRQ_74_set/clr ,UART module 3 (also infrared) interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " M_IRQ_73_set/clr ,UART module 2 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " M_IRQ_72_set/clr ,UART module 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " M_IRQ_71_set/clr ,Dual SSI GDD interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " M_IRQ_70_set/clr ,Dual SSI port 2 request 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " M_IRQ_69_set/clr ,Dual SSI port 2 request 0 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " M_IRQ_68_set/clr ,Dual SSI port 1 request 1 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " M_IRQ_67_set/clr ,Dual SSI port 1 request 0 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " M_IRQ_66_set/clr ,McSPI module 2 interrupt mask" "Not masked,Masked"
|
|
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " M_IRQ_65_set/clr ,McSPI module 1 interrupt mask" "Not masked,Masked"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " M_IRQ_64_set/clr ,PKA crypto-accelerator interrupt mask" "Not masked,Masked"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x00 "INTCPS_PENDING_IRQ0,IRQ Status After Masking"
|
|
bitfld.long 0x00 31. " PENDINGIRQ31 ,IRQ status after masking 31" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PENDINGIRQ30 ,IRQ status after masking 30" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PENDINGIRQ29 ,IRQ status after masking 29" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " PENDINGIRQ28 ,IRQ status after masking 28" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGIRQ27 ,IRQ status after masking 27" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " PENDINGIRQ26 ,IRQ status after masking 26" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDINGIRQ25 ,IRQ status after masking 25" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " PENDINGIRQ24 ,IRQ status after masking 24" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGIRQ23 ,IRQ status after masking 23" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " PENDINGIRQ22 ,IRQ status after masking 22" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PENDINGIRQ21 ,IRQ status after masking 21" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PENDINGIRQ20 ,IRQ status after masking 20" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PENDINGIRQ19 ,IRQ status after masking 19" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PENDINGIRQ18 ,IRQ status after masking 18" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PENDINGIRQ17 ,IRQ status after masking 17" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " PENDINGIRQ16 ,IRQ status after masking 16" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGIRQ15 ,IRQ status after masking 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PENDINGIRQ14 ,IRQ status after masking 14" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PENDINGIRQ13 ,IRQ status after masking 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " PENDINGIRQ12 ,IRQ status after masking 12" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGIRQ11 ,IRQ status after masking 11" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " PENDINGIRQ10 ,IRQ status after masking 10" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PENDINGIRQ9 ,IRQ status after masking 9" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " PENDINGIRQ8 ,IRQ status after masking 8" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PENDINGIRQ7 ,IRQ status after masking 7" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " PENDINGIRQ6 ,IRQ status after masking 6" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGIRQ5 ,IRQ status after masking 5" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " PENDINGIRQ4 ,IRQ status after masking 4" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PENDINGIRQ3 ,IRQ status after masking 3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PENDINGIRQ2 ,IRQ status after masking 2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PENDINGIRQ1 ,IRQ status after masking 1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " PENDINGIRQ0 ,IRQ status after masking 0" "Not pending,Pending"
|
|
rgroup.long 0xB8++0x3
|
|
line.long 0x00 "INTCPS_PENDING_IRQ1,IRQ Status After Masking"
|
|
bitfld.long 0x00 31. " PENDINGIRQ63 ,IRQ status after masking 63" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PENDINGIRQ62 ,IRQ status after masking 62" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PENDINGIRQ61 ,IRQ status after masking 61" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " PENDINGIRQ60 ,IRQ status after masking 60" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGIRQ59 ,IRQ status after masking 59" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " PENDINGIRQ58 ,IRQ status after masking 58" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDINGIRQ57 ,IRQ status after masking 57" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " PENDINGIRQ56 ,IRQ status after masking 56" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGIRQ55 ,IRQ status after masking 55" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " PENDINGIRQ54 ,IRQ status after masking 54" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PENDINGIRQ53 ,IRQ status after masking 53" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PENDINGIRQ52 ,IRQ status after masking 52" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PENDINGIRQ51 ,IRQ status after masking 51" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PENDINGIRQ50 ,IRQ status after masking 50" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PENDINGIRQ49 ,IRQ status after masking 49" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " PENDINGIRQ48 ,IRQ status after masking 48" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGIRQ47 ,IRQ status after masking 47" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PENDINGIRQ46 ,IRQ status after masking 46" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PENDINGIRQ45 ,IRQ status after masking 45" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " PENDINGIRQ44 ,IRQ status after masking 44" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGIRQ43 ,IRQ status after masking 43" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " PENDINGIRQ42 ,IRQ status after masking 42" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PENDINGIRQ41 ,IRQ status after masking 41" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " PENDINGIRQ40 ,IRQ status after masking 40" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PENDINGIRQ39 ,IRQ status after masking 39" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " PENDINGIRQ38 ,IRQ status after masking 38" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGIRQ37 ,IRQ status after masking 37" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " PENDINGIRQ36 ,IRQ status after masking 36" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PENDINGIRQ34 ,IRQ status after masking 34" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " PENDINGIRQ33 ,IRQ status after masking 33" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PENDINGIRQ32 ,IRQ status after masking 32" "Not pending,Pending"
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x00 "INTCPS_PENDING_IRQ2,IRQ Status After Masking"
|
|
bitfld.long 0x00 31. " PENDINGIRQ95 ,IRQ status after masking 95" "Not pending,Pending"
|
|
bitfld.long 0x00 29. " PENDINGIRQ93 ,IRQ status after masking 93" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PENDINGIRQ92 ,IRQ status after masking 92" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " PENDINGIRQ91 ,IRQ status after masking 91" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PENDINGIRQ90 ,IRQ status after masking 90" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " PENDINGIRQ89 ,IRQ status after masking 89" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 24. " PENDINGIRQ88 ,IRQ status after masking 88" "Not pending,Pending"
|
|
bitfld.long 0x00 23. " PENDINGIRQ87 ,IRQ status after masking 87" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 22. " PENDINGIRQ86 ,IRQ status after masking 86" "Not pending,Pending"
|
|
bitfld.long 0x00 21. " PENDINGIRQ85 ,IRQ status after masking 85" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 20. " PENDINGIRQ84 ,IRQ status after masking 84" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " PENDINGIRQ83 ,IRQ status after masking 83" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 18. " PENDINGIRQ82 ,IRQ status after masking 82" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " PENDINGIRQ81 ,IRQ status after masking 81" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PENDINGIRQ80 ,IRQ status after masking 80" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " PENDINGIRQ79 ,IRQ status after masking 79" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PENDINGIRQ78 ,IRQ status after masking 78" "Not pending,Pending"
|
|
bitfld.long 0x00 13. " PENDINGIRQ77 ,IRQ status after masking 77" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PENDINGIRQ76 ,IRQ status after masking 76" "Not pending,Pending"
|
|
bitfld.long 0x00 11. " PENDINGIRQ75 ,IRQ status after masking 75" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PENDINGIRQ74 ,IRQ status after masking 74" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " PENDINGIRQ73 ,IRQ status after masking 73" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PENDINGIRQ72 ,IRQ status after masking 72" "Not pending,Pending"
|
|
bitfld.long 0x00 7. " PENDINGIRQ71 ,IRQ status after masking 71" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PENDINGIRQ70 ,IRQ status after masking 70" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " PENDINGIRQ69 ,IRQ status after masking 69" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PENDINGIRQ68 ,IRQ status after masking 68" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " PENDINGIRQ67 ,IRQ status after masking 67" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PENDINGIRQ66 ,IRQ status after masking 66" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " PENDINGIRQ65 ,IRQ status after masking 65" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PENDINGIRQ64 ,IRQ status after masking 64" "Not pending,Pending"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x00 "INTCPS_PENDING_FIQ0,FIQ Status After Masking"
|
|
bitfld.long 0x00 31. " PENDINGFIQ31 ,FIQ status after masking 31" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PENDINGFIQ30 ,FIQ status after masking 30" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PENDINGFIQ29 ,FIQ status after masking 29" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " PENDINGFIQ28 ,FIQ status after masking 28" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGFIQ27 ,FIQ status after masking 27" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " PENDINGFIQ26 ,FIQ status after masking 26" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDINGFIQ25 ,FIQ status after masking 25" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " PENDINGFIQ24 ,FIQ status after masking 24" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGFIQ23 ,FIQ status after masking 23" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " PENDINGFIQ22 ,FIQ status after masking 22" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PENDINGFIQ21 ,FIQ status after masking 21" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PENDINGFIQ20 ,FIQ status after masking 20" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PENDINGFIQ19 ,FIQ status after masking 19" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PENDINGFIQ18 ,FIQ status after masking 18" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PENDINGFIQ17 ,FIQ status after masking 17" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " PENDINGFIQ16 ,FIQ status after masking 16" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGFIQ15 ,FIQ status after masking 15" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PENDINGFIQ14 ,FIQ status after masking 14" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PENDINGFIQ13 ,FIQ status after masking 13" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " PENDINGFIQ12 ,FIQ status after masking 12" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGFIQ11 ,FIQ status after masking 11" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " PENDINGFIQ10 ,FIQ status after masking 10" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PENDINGFIQ9 ,FIQ status after masking 9" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " PENDINGFIQ8 ,FIQ status after masking 8" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PENDINGFIQ7 ,FIQ status after masking 7" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " PENDINGFIQ6 ,FIQ status after masking 6" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGFIQ5 ,FIQ status after masking 5" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " PENDINGFIQ4 ,FIQ status after masking 4" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PENDINGFIQ3 ,FIQ status after masking 3" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PENDINGFIQ2 ,FIQ status after masking 2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PENDINGFIQ1 ,FIQ status after masking 1" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " PENDINGFIQ0 ,FIQ status after masking 0" "Not pending,Pending"
|
|
rgroup.long 0xB8++0x3
|
|
line.long 0x00 "INTCPS_PENDING_FIQ1,FIQ Status After Masking"
|
|
bitfld.long 0x00 31. " PENDINGFIQ63 ,FIQ status after masking 63" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PENDINGFIQ62 ,FIQ status after masking 62" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PENDINGFIQ61 ,FIQ status after masking 61" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " PENDINGFIQ60 ,FIQ status after masking 60" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGFIQ59 ,FIQ status after masking 59" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " PENDINGFIQ58 ,FIQ status after masking 58" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDINGFIQ57 ,FIQ status after masking 57" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " PENDINGFIQ56 ,FIQ status after masking 56" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGFIQ55 ,FIQ status after masking 55" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " PENDINGFIQ54 ,FIQ status after masking 54" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PENDINGFIQ53 ,FIQ status after masking 53" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PENDINGFIQ52 ,FIQ status after masking 52" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PENDINGFIQ51 ,FIQ status after masking 51" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PENDINGFIQ50 ,FIQ status after masking 50" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PENDINGFIQ49 ,FIQ status after masking 49" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " PENDINGFIQ48 ,FIQ status after masking 48" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGFIQ47 ,FIQ status after masking 47" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PENDINGFIQ46 ,FIQ status after masking 46" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PENDINGFIQ45 ,FIQ status after masking 45" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " PENDINGFIQ44 ,FIQ status after masking 44" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGFIQ43 ,FIQ status after masking 43" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " PENDINGFIQ42 ,FIQ status after masking 42" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PENDINGFIQ41 ,FIQ status after masking 41" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " PENDINGFIQ40 ,FIQ status after masking 40" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PENDINGFIQ39 ,FIQ status after masking 39" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " PENDINGFIQ38 ,FIQ status after masking 38" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGFIQ37 ,FIQ status after masking 37" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " PENDINGFIQ36 ,FIQ status after masking 36" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PENDINGFIQ35 ,FIQ status after masking 35" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PENDINGFIQ34 ,FIQ status after masking 34" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PENDINGFIQ33 ,FIQ status after masking 33" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " PENDINGFIQ32 ,FIQ status after masking 32" "Not pending,Pending"
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x00 "INTCPS_PENDING_FIQ2,FIQ Status After Masking"
|
|
bitfld.long 0x00 31. " PENDINGFIQ95 ,FIQ status after masking 95" "Not pending,Pending"
|
|
bitfld.long 0x00 30. " PENDINGFIQ94 ,FIQ status after masking 94" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 29. " PENDINGFIQ93 ,FIQ status after masking 93" "Not pending,Pending"
|
|
bitfld.long 0x00 28. " PENDINGFIQ92 ,FIQ status after masking 92" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDINGFIQ91 ,FIQ status after masking 91" "Not pending,Pending"
|
|
bitfld.long 0x00 26. " PENDINGFIQ90 ,FIQ status after masking 90" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDINGFIQ89 ,FIQ status after masking 89" "Not pending,Pending"
|
|
bitfld.long 0x00 24. " PENDINGFIQ88 ,FIQ status after masking 88" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 23. " PENDINGFIQ87 ,FIQ status after masking 87" "Not pending,Pending"
|
|
bitfld.long 0x00 22. " PENDINGFIQ86 ,FIQ status after masking 86" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 21. " PENDINGFIQ85 ,FIQ status after masking 85" "Not pending,Pending"
|
|
bitfld.long 0x00 20. " PENDINGFIQ84 ,FIQ status after masking 84" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PENDINGFIQ83 ,FIQ status after masking 83" "Not pending,Pending"
|
|
bitfld.long 0x00 18. " PENDINGFIQ82 ,FIQ status after masking 82" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 17. " PENDINGFIQ81 ,FIQ status after masking 81" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " PENDINGFIQ80 ,FIQ status after masking 80" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 15. " PENDINGFIQ79 ,FIQ status after masking 79" "Not pending,Pending"
|
|
bitfld.long 0x00 14. " PENDINGFIQ78 ,FIQ status after masking 78" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PENDINGFIQ77 ,FIQ status after masking 77" "Not pending,Pending"
|
|
bitfld.long 0x00 12. " PENDINGFIQ76 ,FIQ status after masking 76" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PENDINGFIQ75 ,FIQ status after masking 75" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " PENDINGFIQ74 ,FIQ status after masking 74" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PENDINGFIQ73 ,FIQ status after masking 73" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " PENDINGFIQ72 ,FIQ status after masking 72" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PENDINGFIQ71 ,FIQ status after masking 71" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " PENDINGFIQ70 ,FIQ status after masking 70" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PENDINGFIQ69 ,FIQ status after masking 69" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " PENDINGFIQ68 ,FIQ status after masking 68" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PENDINGFIQ67 ,FIQ status after masking 67" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PENDINGFIQ66 ,FIQ status after masking 66" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PENDINGFIQ65 ,FIQ status after masking 65" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " PENDINGFIQ64 ,FIQ status after masking 64" "Not pending,Pending"
|
|
group.long 0x100++0x17F
|
|
line.long 0x0 "INTCPS_ILR0,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x4 "INTCPS_ILR1,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x8 "INTCPS_ILR2,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xC "INTCPS_ILR3,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x10 "INTCPS_ILR4,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x10 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x10 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x14 "INTCPS_ILR5,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x14 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x14 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x18 "INTCPS_ILR6,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x18 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x18 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x1C "INTCPS_ILR7,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x1C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x1C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x20 "INTCPS_ILR8,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x20 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x20 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x24 "INTCPS_ILR9,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x24 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x24 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x28 "INTCPS_ILR10,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x28 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x28 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x2C "INTCPS_ILR11,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x2C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x2C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x30 "INTCPS_ILR12,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x30 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x30 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x34 "INTCPS_ILR13,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x34 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x34 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x38 "INTCPS_ILR14,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x38 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x38 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x3C "INTCPS_ILR15,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x3C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x3C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x40 "INTCPS_ILR16,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x40 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x40 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x44 "INTCPS_ILR17,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x44 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x44 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x48 "INTCPS_ILR18,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x48 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x48 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x4C "INTCPS_ILR19,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x4C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x4C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x50 "INTCPS_ILR20,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x50 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x50 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x54 "INTCPS_ILR21,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x54 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x54 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x58 "INTCPS_ILR22,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x58 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x58 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x5C "INTCPS_ILR23,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x5C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x5C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x60 "INTCPS_ILR24,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x60 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x60 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x64 "INTCPS_ILR25,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x64 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x64 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x68 "INTCPS_ILR26,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x68 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x68 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x6C "INTCPS_ILR27,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x6C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x6C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x70 "INTCPS_ILR28,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x70 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x70 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x74 "INTCPS_ILR29,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x74 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x74 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x78 "INTCPS_ILR30,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x78 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x78 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x7C "INTCPS_ILR31,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x7C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x7C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x80 "INTCPS_ILR32,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x80 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x80 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x84 "INTCPS_ILR33,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x84 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x84 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x88 "INTCPS_ILR34,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x88 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x88 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x90 "INTCPS_ILR36,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x90 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x90 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x94 "INTCPS_ILR37,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x94 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x94 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x98 "INTCPS_ILR38,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x98 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x98 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x9C "INTCPS_ILR39,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x9C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x9C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xA0 "INTCPS_ILR40,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xA0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xA0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xA4 "INTCPS_ILR41,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xA4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xA4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xA8 "INTCPS_ILR42,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xA8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xA8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xAC "INTCPS_ILR43,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xAC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xAC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xB0 "INTCPS_ILR44,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xB0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xB0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xB4 "INTCPS_ILR45,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xB4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xB4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xB8 "INTCPS_ILR46,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xB8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xB8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xBC "INTCPS_ILR47,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xBC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xBC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xC0 "INTCPS_ILR48,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xC0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xC0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xC4 "INTCPS_ILR49,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xC4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xC4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xC8 "INTCPS_ILR50,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xC8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xC8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xCC "INTCPS_ILR51,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xCC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xCC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xD0 "INTCPS_ILR52,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xD0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xD0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xD4 "INTCPS_ILR53,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xD4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xD4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xD8 "INTCPS_ILR54,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xD8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xD8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xDC "INTCPS_ILR55,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xDC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xDC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xE0 "INTCPS_ILR56,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xE0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xE0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xE4 "INTCPS_ILR57,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xE4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xE4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xE8 "INTCPS_ILR58,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xE8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xE8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xEC "INTCPS_ILR59,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xEC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xEC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xF0 "INTCPS_ILR60,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xF0 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xF0 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xF4 "INTCPS_ILR61,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xF4 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xF4 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xF8 "INTCPS_ILR62,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xF8 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xF8 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0xFC "INTCPS_ILR63,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0xFC 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0xFC 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x100 "INTCPS_ILR64,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x100 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x100 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x104 "INTCPS_ILR65,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x104 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x104 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x108 "INTCPS_ILR66,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x108 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x108 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x10C "INTCPS_ILR67,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x10C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x10C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x110 "INTCPS_ILR68,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x110 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x110 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x114 "INTCPS_ILR69,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x114 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x114 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x118 "INTCPS_ILR70,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x118 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x118 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x11C "INTCPS_ILR71,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x11C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x11C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x120 "INTCPS_ILR72,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x120 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x120 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x124 "INTCPS_ILR73,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x124 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x124 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x128 "INTCPS_ILR74,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x128 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x128 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x12C "INTCPS_ILR75,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x12C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x12C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x130 "INTCPS_ILR76,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x130 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x130 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x134 "INTCPS_ILR77,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x134 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x134 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x138 "INTCPS_ILR78,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x138 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x138 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x13C "INTCPS_ILR79,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x13C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x13C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x140 "INTCPS_ILR80,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x140 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x140 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x144 "INTCPS_ILR81,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x144 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x144 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x148 "INTCPS_ILR82,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x148 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x148 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x14C "INTCPS_ILR83,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x14C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x14C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x150 "INTCPS_ILR84,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x150 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x150 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x154 "INTCPS_ILR85,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x154 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x154 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x158 "INTCPS_ILR86,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x158 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x158 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x15C "INTCPS_ILR87,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x15C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x15C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x160 "INTCPS_ILR88,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x160 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x160 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x164 "INTCPS_ILR89,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x164 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x164 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x168 "INTCPS_ILR90,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x168 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x168 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x16C "INTCPS_ILR91,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x16C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x16C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x170 "INTCPS_ILR92,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x170 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x170 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x174 "INTCPS_ILR93,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x174 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x174 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
line.long 0x17C "INTCPS_ILR95,Priority For The Interrupts And The FIQ/IRQ Steering"
|
|
hexmask.long.byte 0x17C 2.--7. 1. " PRIORITY ,Interrupt priority"
|
|
bitfld.long 0x17C 0. " FIQNIRQ ,Interrupt IRQ FIQ mapping" "IRQ,FIQ"
|
|
width 0xb
|
|
tree.end
|
|
tree "Device INTC"
|
|
base ad:0x470C8000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "INTC_INIT_REGISTER1,Power Optimization Enable Register"
|
|
bitfld.long 0x00 0. " INIT1 ,Lowest power configuration" "Disabled,Enabled"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "INTC_INIT_REGISTER2,Power Optimization Enable Register"
|
|
bitfld.long 0x00 1. " INIT2 ,Optimal power consumption" "Disabled,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "Memory Subsystem"
|
|
tree "General Purpose Memory Controller (GPMC)"
|
|
base ad:0x6E000000
|
|
width 22.
|
|
tree "Miscellaneous Registers"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPMC_SYSCONFIG,Various Parameters Of The Interconnect Control"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPMC_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "GPMC_IRQSTATUS,Interrupt Status Register"
|
|
eventfld.long 0x00 11. " WAIT3EDGEDETECTIONSTATUS ,Status of the Wait3 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 10. " WAIT2EDGEDETECTIONSTATUS ,Status of the Wait2 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 9. " WAIT1EDGEDETECTIONSTATUS ,Status of the Wait1 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 8. " WAIT0EDGEDETECTIONSTATUS ,Status of the Wait0 Edge Detection interrupt" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TERMINALCOUNTSTATUS ,Status of the TerminalCountEvent interrupt (COUNTVALUE)" ">0,=0"
|
|
textline " "
|
|
eventfld.long 0x00 0. " FIFOEVENTSTATUS ,Status of the FIFOEvent interrupt" "<FIFOTHRESHOLD,=FIFOTHRESHOLD"
|
|
line.long 0x04 "GPMC_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 11. " WAIT3EDGEDETECTIONENABLE ,Enables the Wait3 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " WAIT2EDGEDETECTIONENABLE ,Enables the Wait2 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT1EDGEDETECTIONENABLE ,Enables the Wait1 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT0EDGEDETECTIONENABLE ,Enables the Wait0 Edge Detection interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TERMINALCOUNTEVENTENABLE ,Enables TerminalCountEvent interrupt" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FIFOEVENTENABLE ,Enables the FIFOEvent interrupt" "Masked,Enabled"
|
|
group.long 0x40++0xb
|
|
line.long 0x00 "GPMC_TIMEOUT_CONTROL,Start Value Of The Timeout Counter Set Register"
|
|
hexmask.long.word 0x00 4.--12. 1. " TIMEOUTSTARTVALUE ,Start value of the time-out counter"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TIMEOUTENABLE ,Enable bit of the TimeOut feature" "Disabled,Enabled"
|
|
line.long 0x04 "GPMC_ERR_ADDRESS,Stores The Address Of The Illegal Access"
|
|
hexmask.long 0x04 0.--30. 1. " ILLEGALADD ,Address of illegal access"
|
|
line.long 0x08 "GPMC_ERR_TYPE,Stores The Type Of Error"
|
|
bitfld.long 0x08 8.--10. " ILLEGALMCMD ,System Command of the transaction that caused the error" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x08 4. " ERRORNOTSUPPADD ,Not supported Address error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 3. " ERRORNOTSUPPMCMD ,Not supported Command error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ERRORTIMEOUT ,Time-out error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ERRORVALID ,Error validity status" "Not valid,Valid"
|
|
group.long 0x50++0x7
|
|
line.long 0x00 "GPMC_CONFIG,Global Configuration Of The GPMC Module"
|
|
bitfld.long 0x00 11. " WAIT3PINPOLARITY ,Selects the polarity of input pin WAIT3" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WAIT2PINPOLARITY ,Selects the polarity of input pin WAIT2" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " WAIT1PINPOLARITY ,Selects the polarity of input pin WAIT1" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WAIT0PINPOLARITY ,Selects the polarity of input pin WAIT0" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WRITEPROTECT ,Controls the WP output pin level" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LIMITEDADDRESS ,Limited Address device support" "No effect,A26-A11 not modified"
|
|
textline " "
|
|
bitfld.long 0x00 0. " NANDFORCEPOSTEDWRITE ,Enables the Force Posted Write feature to NAND Cmd/Add/Data location" "Disabled,Enabled"
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|
line.long 0x04 "GPMC_STATUS,Global Status Bits Of The GPMC Module"
|
|
bitfld.long 0x04 11. " WAIT3STATUS ,Copy of input pin WAIT3" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x04 10. " WAIT2STATUS ,Copy of input pin WAIT2" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x04 9. " WAIT1STATUS ,Copy of input pin WAIT1" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x04 8. " WAIT0STATUS ,Copy of input pin WAIT0" "Asserted,De-asserted"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EMPTYWRITEBUFFERSTATUS ,Stores the empty status of the write buffer" "Not empty,Empty"
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|
group.long 0x1E0++0x7
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line.long 0x00 "GPMC_PREFETCH_CONFIG1,Prefetch Engine Configuration 1"
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|
bitfld.long 0x00 28.--30. " CYCLEOPTIMIZATION ,Defines the number of GPMC_FCLK cycles to be subtracted" "0,1,2,3,4,5,6,7"
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|
textline " "
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bitfld.long 0x00 27. " ENABLEOPTIMIZEDACCESS ,Enables access cycle optimization" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x00 24.--26. " ENGINECSSELECTOR ,CS where Prefetch Postwrite engine is active" "CS0,CS1,CS2,CS3,CS4,CS5,CS6,CS7"
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|
textline " "
|
|
bitfld.long 0x00 23. " PFPWENROUNDROBIN ,PFPW RoundRobin arbitration enable" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x00 16.--19. " PFPWWEIGHTEDPRIO ,Arbitration between a direct memory access and a PFPW engine access (next access is granted to the PFPW engine)" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
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|
textline " "
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|
hexmask.long.byte 0x00 8.--14. 1. " FIFOTHRESHOLD ,Maximum number of bytes read/write from the FIFO"
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|
textline " "
|
|
bitfld.long 0x00 7. " ENABLEENGINE ,Prefetch Postwite engine enable" "Disabled,Enabled"
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|
textline " "
|
|
bitfld.long 0x00 4.--5. " WAITPINSELECTOR ,Selects which wait pin edge detector should start the engine in synchronized mode" "Wait0EdgeDetection,Wait1EdgeDetection,Wait2EdgeDetection,Wait3EdgeDetection"
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|
textline " "
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|
bitfld.long 0x00 3. " SYNCHROMODE ,Selects when the engine starts the access to CS" "StartEngine set,StartEngine set/wait to nonwait edge"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DMAMODE ,Selects interrupt synchronization or DMA request synchronization" "Interrupt,DMA request"
|
|
textline " "
|
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bitfld.long 0x00 0. " ACCESSMODE ,Selects prefetch read or write-posting accesses" "Prefetch read,Write-posting"
|
|
line.long 0x04 "GPMC_PREFETCH_CONFIG2,Prefetch Engine Configuration 2"
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|
hexmask.long.word 0x04 0.--13. 1. " TRANSFERCOUNT ,Number of bytes to be read/write by the engine to the selected CS"
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|
group.long 0x1EC++0x13
|
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line.long 0x00 "GPMC_PREFETCH_CONTROL,Prefetch Engine Control"
|
|
bitfld.long 0x00 0. " STARTENGINE ,Reset FIFO pointer and start the engine" "Stopped,Running"
|
|
line.long 0x04 "GPMC_PREFETCH_STATUS,Prefetch Engine Status"
|
|
hexmask.long.byte 0x04 24.--30. 1. " FIFOPOINTER ,Number of available bytes to be read/write"
|
|
textline " "
|
|
bitfld.long 0x04 16. " FIFOTHRESHOLDSTATUS ,Set when FIFOPOINTER exceeds FIFOTHRESHOLD value" "<=FIFOTHRESHOLD,>FIFOTHRESHOLD"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--13. 1. " COUNTVALUE ,Number of remaining bytes to be read/write"
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|
line.long 0x08 "GPMC_ECC_CONFIG,ECC Configuration"
|
|
bitfld.long 0x08 16. " ECCALGORITHM ,ECC algorithm used" "Hamming,BCH"
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|
textline " "
|
|
bitfld.long 0x08 12. " ECCBCHT8 ,Error correction capability used for BCH" "t=4,t=8"
|
|
textline " "
|
|
bitfld.long 0x08 8.--11. " ECCWRAPMODE ,Spare area organization definition for the BCH algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ECC16B ,Selects an ECC calculated on 16 columns" "8 columns,16 columns"
|
|
textline " "
|
|
bitfld.long 0x08 4.--6. " ECCTOPSECTOR ,Number of sectors to process with the BCH algorithm" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x08 1.--3. " ECCCS ,Selects the CS where ECC is computed" "Chip-select 0,Chip-select 1,Chip-select 2,Chip-select 3,Chip-select 4,Chip-select 5,Chip-select 6,Chip-select 7"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ECCENABLE ,Enables the ECC feature" "Disabled,Enabled"
|
|
line.long 0x0C "GPMC_ECC_CONTROL,ECC Control"
|
|
eventfld.long 0x0C 8. " ECCCLEAR ,Clear all ECC result registers" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " ECCPOINTER ,ECC result register" "ECC engine disabled,ECC result register 1,ECC result register 2,ECC result register 3,ECC result register 4,ECC result register 5,ECC result register 6,ECC result register 7,ECC result register 8,ECC result register 9,?..."
|
|
line.long 0x10 "GPMC_ECC_SIZE_CONFIG,ECC Size"
|
|
hexmask.long.byte 0x10 22.--29. 1. " ECCSIZE1 ,Defines ECC size 1"
|
|
hexmask.long.byte 0x10 12.--19. 1. " ECCSIZE0 ,Defines ECC size 0"
|
|
textline " "
|
|
bitfld.long 0x10 8. " ECC9RESULTSIZE ,Selects ECC size for ECC 9 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x10 7. " ECC8RESULTSIZE ,Selects ECC size for ECC 8 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x10 6. " ECC7RESULTSIZE ,Selects ECC size for ECC 7 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x10 5. " ECC6RESULTSIZE ,Selects ECC size for ECC 6 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x10 4. " ECC5RESULTSIZE ,Selects ECC size for ECC 5 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x10 3. " ECC4RESULTSIZE ,Selects ECC size for ECC 4 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x10 2. " ECC3RESULTSIZE ,Selects ECC size for ECC 3 result register" "ECCSize0,ECCSize1"
|
|
bitfld.long 0x10 1. " ECC2RESULTSIZE ,Selects ECC size for ECC 2 result register" "ECCSize0,ECCSize1"
|
|
textline " "
|
|
bitfld.long 0x10 0. " ECC1RESULTSIZE ,Selects ECC size for ECC 1 result register" "ECCSize0,ECCSize1"
|
|
group.long 0x2D0++0x3
|
|
line.long 0x00 "GPMC_BCH_SWDATA,Pass Data To The BCH ECC Calculator"
|
|
hexmask.long.word 0x00 0.--15. 1. " BCH_DATA ,Data to be included in the BCH calculation"
|
|
tree.end
|
|
tree "Chip Select #0"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_0,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0x60+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_0,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,0CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,0CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,0CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,0CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_0,0ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,0ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,0ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,0ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,0ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_0,0WE and 0OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,0WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,0WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,0WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,0OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,0OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,0OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x60+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_0,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x60+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_0,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long (0x60+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_0,Address Location"
|
|
hgroup.long (0x60+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_0,Address Location"
|
|
hgroup.long (0x60+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_0,Address Location"
|
|
group.long (0x60+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_0,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Chip Select #1"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_1,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0x90+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_1,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,1CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,1CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,1CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,1CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_1,1ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,1ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,1ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,1ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,1ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_1,1WE and 1OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,1WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,1WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,1WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,1OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,1OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,1OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x90+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_1,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x90+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_1,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long (0x90+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_1,Address Location"
|
|
hgroup.long (0x90+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_1,Address Location"
|
|
hgroup.long (0x90+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_1,Address Location"
|
|
group.long (0x90+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_1,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Chip Select #2"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_2,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0xC0+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_2,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,2CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,2CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,2CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,2CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_2,2ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,2ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,2ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,2ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,2ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_2,2WE and 2OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,2WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,2WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,2WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,2OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,2OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,2OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xC0+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_2,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0xC0+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_2,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long (0xC0+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_2,Address Location"
|
|
hgroup.long (0xC0+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_2,Address Location"
|
|
hgroup.long (0xC0+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_2,Address Location"
|
|
group.long (0xC0+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_2,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Chip Select #3"
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_3,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0xF0+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_3,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,3CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,3CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,3CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,3CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_3,3ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,3ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,3ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,3ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,3ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_3,3WE and 3OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,3WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,3WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,3WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,3OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,3OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,3OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0xF0+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_3,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long (0xF0+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_3,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
hgroup.long (0xF0+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_3,Address Location"
|
|
hgroup.long (0xF0+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_3,Address Location"
|
|
hgroup.long (0xF0+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_3,Address Location"
|
|
group.long (0xF0+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_3,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
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|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Chip Select #4"
|
|
group.long 0x120++0x3
|
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line.long 0x00 "GPMC_CONFIG1_4,Signal Control Parameters Per Chip-select"
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|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
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|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0x120+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_4,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,4CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,4CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,4CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,4CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_4,4ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,4ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,4ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,4ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,4ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_4,4WE and 4OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,4WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,4WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,4WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,4OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,4OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,4OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x120+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_4,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x120+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_4,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long (0x120+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_4,Address Location"
|
|
hgroup.long (0x120+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_4,Address Location"
|
|
hgroup.long (0x120+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_4,Address Location"
|
|
group.long (0x120+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_4,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Chip Select #5"
|
|
group.long 0x150++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_5,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0x150+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_5,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,5CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,5CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,5CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,5CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_5,5ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,5ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,5ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,5ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,5ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_5,5WE and 5OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,5WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,5WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,5WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,5OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,5OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,5OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x150+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_5,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
group.long (0x150+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_5,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
hgroup.long (0x150+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_5,Address Location"
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|
hgroup.long (0x150+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_5,Address Location"
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|
hgroup.long (0x150+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_5,Address Location"
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|
group.long (0x150+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_5,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
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|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
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|
tree.end
|
|
tree "Chip Select #6"
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|
group.long 0x180++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_6,Signal Control Parameters Per Chip-select"
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|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
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|
textline " "
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|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
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|
textline " "
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|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
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|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
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|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
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|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
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|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
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|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
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|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
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|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
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|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0x180+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_6,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,6CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,6CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,6CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,6CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x180+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_6,6ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,6ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,6ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,6ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,6ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x180+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_6,6WE and 6OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,6WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,6WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,6WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,6OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,6OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,6OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x180+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_6,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x180+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_6,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long (0x180+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_6,Address Location"
|
|
hgroup.long (0x180+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_6,Address Location"
|
|
hgroup.long (0x180+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_6,Address Location"
|
|
group.long (0x180+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_6,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Chip Select #7"
|
|
group.long 0x1B0++0x3
|
|
line.long 0x00 "GPMC_CONFIG1_7,Signal Control Parameters Per Chip-select"
|
|
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
|
|
textline " "
|
|
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
|
|
group.long (0x1B0+0x04)++0x3
|
|
line.long 0x00 "GPMC_CONFIG2_7,Chip-select Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " CSWROFFTIME ,7CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,7CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSEXTRADELAY ,7CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,7CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x1B0+0x08)++0x3
|
|
line.long 0x00 "GPMC_CONFIG3_7,7ADV Signal Timing Parameter Configuration"
|
|
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,7ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,7ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ADVEXTRADELAY ,7ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " ADVONTIME ,7ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x1B0+0x0C)++0x3
|
|
line.long 0x00 "GPMC_CONFIG4_7,7WE and 7OE signals timing parameter configuration"
|
|
bitfld.long 0x00 24.--28. " WEOFFTIME ,7WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 23. " WEEXTRADELAY ,7WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WEONTIME ,7WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " OEOFFTIME ,7OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OEEXTRADELAY ,7OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " OEONTIME ,7OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x1B0+0x10)++0x3
|
|
line.long 0x00 "GPMC_CONFIG5_7,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
|
|
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--20. " ACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long (0x1B0+0x14)++0x3
|
|
line.long 0x00 "GPMC_CONFIG6_7,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
|
|
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hgroup.long (0x1B0+0x1C)++0x3
|
|
hide.long 0x00 "GPMC_NAND_COMMAND_7,Address Location"
|
|
hgroup.long (0x1B0+0x20)++0x3
|
|
hide.long 0x00 "GPMC_NAND_ADDRESS_7,Address Location"
|
|
hgroup.long (0x1B0+0x24)++0x3
|
|
hide.long 0x00 "GPMC_NAND_DATA_7,Address Location"
|
|
group.long (0x1B0+0x18)++0x3
|
|
line.long 0x00 "GPMC_CONFIG7_7,Chip-select Address Mapping Configuration"
|
|
hexmask.long.byte 0x00 8.--11. 1. " MASKADDRESS ,Chip-select mask address"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
|
|
tree.end
|
|
tree "Result Registers"
|
|
width 19.
|
|
group.long 0x200++0x23
|
|
line.long 0x0 "GPMC_ECC1_RESULT,ECC1 Result Register"
|
|
bitfld.long 0x0 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x0 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x0 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x0 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x0 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x0 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x0 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x0 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x0 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x0 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x0 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x0 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x0 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x0 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x0 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x0 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x4 "GPMC_ECC2_RESULT,ECC2 Result Register"
|
|
bitfld.long 0x4 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x4 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x4 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x4 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x4 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x4 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x4 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x4 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x4 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x4 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x4 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x4 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x4 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x4 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x4 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x4 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x4 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x4 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x4 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x8 "GPMC_ECC3_RESULT,ECC3 Result Register"
|
|
bitfld.long 0x8 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x8 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x8 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x8 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x8 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x8 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x8 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x8 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x8 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x8 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x8 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x8 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x8 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x8 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x8 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x8 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x8 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x8 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x8 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0xC "GPMC_ECC4_RESULT,ECC4 Result Register"
|
|
bitfld.long 0xC 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0xC 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0xC 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0xC 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0xC 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0xC 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0xC 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0xC 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0xC 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0xC 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0xC 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0xC 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0xC 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0xC 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0xC 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0xC 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0xC 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0xC 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0xC 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x10 "GPMC_ECC5_RESULT,ECC5 Result Register"
|
|
bitfld.long 0x10 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x10 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x10 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x10 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x10 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x10 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x10 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x10 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x10 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x10 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x10 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x10 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x10 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x10 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x10 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x10 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x10 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x10 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x10 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x14 "GPMC_ECC6_RESULT,ECC6 Result Register"
|
|
bitfld.long 0x14 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x14 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x14 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x14 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x14 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x14 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x14 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x14 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x14 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x14 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x14 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x14 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x14 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x14 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x14 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x14 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x14 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x14 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x14 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x18 "GPMC_ECC7_RESULT,ECC7 Result Register"
|
|
bitfld.long 0x18 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x18 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x18 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x18 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x18 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x18 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x18 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x18 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x18 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x18 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x18 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x18 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x18 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x18 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x18 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x18 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x18 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x18 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x18 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x1C "GPMC_ECC8_RESULT,ECC8 Result Register"
|
|
bitfld.long 0x1C 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x1C 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x1C 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x1C 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x1C 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x1C 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x1C 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x1C 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x1C 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x1C 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x1C 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x1C 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x1C 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x1C 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x1C 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x1C 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x1C 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x1C 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x1C 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
line.long 0x20 "GPMC_ECC9_RESULT,ECC9 Result Register"
|
|
bitfld.long 0x20 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x20 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x20 25. " P512O ,Odd Row Parity bit 512" "0,1"
|
|
bitfld.long 0x20 24. " P256O ,Odd Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 23. " P128O ,Odd Row Parity bit 128" "0,1"
|
|
bitfld.long 0x20 22. " P64O ,Odd Row Parity bit 64" "0,1"
|
|
bitfld.long 0x20 21. " P32O ,Odd Row Parity bit 32" "0,1"
|
|
bitfld.long 0x20 20. " P16O ,Odd Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 19. " P8O ,Odd Row Parity bit 8" "0,1"
|
|
bitfld.long 0x20 18. " P4O ,Odd Column Parity bit 4" "0,1"
|
|
bitfld.long 0x20 17. " P2O ,Odd Column Parity bit 2" "0,1"
|
|
bitfld.long 0x20 16. " P1O ,Odd Column Parity bit 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 11. " P2048E ,Even Row Parity bit 2048" "0,1"
|
|
bitfld.long 0x20 10. " P1024E ,Even Row Parity bit 1024" "0,1"
|
|
bitfld.long 0x20 9. " P512E ,Even Row Parity bit 512" "0,1"
|
|
bitfld.long 0x20 8. " P256E ,Even Row Parity bit 256" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 7. " P128E ,Even Row Parity bit 128" "0,1"
|
|
bitfld.long 0x20 6. " P64E ,Even Row Parity bit 64" "0,1"
|
|
bitfld.long 0x20 5. " P32E ,Even Row Parity bit 32" "0,1"
|
|
bitfld.long 0x20 4. " P16E ,Even Row Parity bit 16" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 3. " P8E ,Even Row Parity bit 8" "0,1"
|
|
bitfld.long 0x20 2. " P4E ,Even Column Parity bit 4" "0,1"
|
|
bitfld.long 0x20 1. " P2E ,Even Column Parity bit 2" "0,1"
|
|
bitfld.long 0x20 0. " P1E ,Even Column Parity bit 1" "0,1"
|
|
group.long 0x240++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_0,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_0,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_0,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_0,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x250++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_1,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_1,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_1,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_1,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x260++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_2,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_2,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_2,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_2,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x270++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_3,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_3,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_3,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_3,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x280++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_4,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_4,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_4,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_4,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x290++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_5,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_5,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_5,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_5,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x2A0++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_6,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_6,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_6,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_6,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
group.long 0x2B0++0xF
|
|
line.long 0x00 "GPMC_BCH_RESULT0_7,BCH ECC result (bits 0 to 31)"
|
|
line.long 0x04 "GPMC_BCH_RESULT1_7,BCH ECC result (bits 32 to 63)"
|
|
line.long 0x08 "GPMC_BCH_RESULT2_7,BCH ECC result (bits 64 to 95)"
|
|
line.long 0x0C "GPMC_BCH_RESULT3_7,BCH ECC result (bits 96 to 103)"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
tree "SDRAM Controller Subsystem"
|
|
tree "SMS"
|
|
base ad:0x6C000000
|
|
width 17.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SMS_SYSCONFIG,Various Parameters Of The Interconnect"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management req/ack control" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "SMS_SYSSTATUS,Module Status Information"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "SMS_RG_ATT0,Request Information Permission"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "SMS_RG_ATT1,Request Information Permission"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "SMS_RG_ATT2,Request Information Permission"
|
|
group.long 0xA8++0x3
|
|
line.long 0x00 "SMS_RG_ATT3,Request Information Permission"
|
|
group.long 0xC8++0x3
|
|
line.long 0x00 "SMS_RG_ATT4,Request Information Permission"
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "SMS_RG_ATT5,Request Information Permission"
|
|
group.long 0x108++0x3
|
|
line.long 0x00 "SMS_RG_ATT6,Request Information Permission"
|
|
group.long 0x128++0x3
|
|
line.long 0x00 "SMS_RG_ATT7,Request Information Permission"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM0,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM1,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x90++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM2,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM3,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0xD0++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM4,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0xF0++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM5,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM6,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x130++0x3
|
|
line.long 0x00 "SMS_RG_RDPERM7,List Of All Initiators That Have Permission For Reading From That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM0,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM1,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x98++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM2,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM3,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0xD8++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM4,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0xF8++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM5,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x118++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM6,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x138++0x3
|
|
line.long 0x00 "SMS_RG_WRPERM7,List Of All Initiators That Have Permission To Write To That Memory Region"
|
|
hexmask.long.word 0x00 0.--15. 1. " CONNIDVECTOR ,One bit per initiator group"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "SMS_RG_START1,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "SMS_RG_START2,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "SMS_RG_START3,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "SMS_RG_START4,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0xE0++0x3
|
|
line.long 0x00 "SMS_RG_START5,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "SMS_RG_START6,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "SMS_RG_START7,Region Start Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " STARTADDRESS ,Region start address"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "SMS_RG_END1,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "SMS_RG_END2,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "SMS_RG_END3,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
group.long 0xC4++0x3
|
|
line.long 0x00 "SMS_RG_END4,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
group.long 0xE4++0x3
|
|
line.long 0x00 "SMS_RG_END5,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
group.long 0x104++0x3
|
|
line.long 0x00 "SMS_RG_END6,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
group.long 0x124++0x3
|
|
line.long 0x00 "SMS_RG_END7,Region End Address"
|
|
hexmask.long.word 0x00 16.--30. 1. " ENDADDRESS ,Region end address"
|
|
width 22.
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "SMS_SECURITY_CONTROL,Security Level Required To Access All SMS Registers"
|
|
bitfld.long 0x00 27. " ROTCTXT11LOCK ,Security level to program rotation context 11 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 26. " ROTCTXT10LOCK ,Security level to program rotation context 10 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ROTCTXT9LOCK ,Security level to program rotation context 9 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 24. " ROTCTXT8LOCK ,Security level to program rotation context 8 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 23. " ROTCTXT7LOCK ,Security level to program rotation context 7 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ROTCTXT6LOCK ,Security level to program rotation context 6 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 21. " ROTCTXT5LOCK ,Security level to program rotation context 5 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 20. " ROTCTXT4LOCK ,Security level to program rotation context 4 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ROTCTXT3LOCK ,Security level to program rotation context 3 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 18. " ROTCTXT2LOCK ,Security level to program rotation context 2 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 17. " ROTCTXT1LOCK ,Security level to program rotation context 1 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ROTCTXT0LOCK ,Security level to program rotation context 0 (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ARBITRATIONREGSLOCK ,Security level to program arbitration control registers (transaction)" "Any,Secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " REGION1REGSLOCK ,Region1 security firewall registers lock bit" "Secure/Nonsecure,Only secure"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SOFTRESETLOCK ,Soft reset lock bit (triggered with access)" "Secure/Nonsecure,Only secure"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ERRORREGSLOCK ,Error registers lock bit" "Secure/Nonsecure,Only secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FIREWALLLOCK ,All security firewall registers lock bit" "Secure/Nonsecure,Only secure"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SECURITYCONTROLREGLOCK ,SMS_SECURITY_CONTROL register configuration lock bit" "Unlocked,Locked"
|
|
group.long 0x150++0xb
|
|
line.long 0x00 "SMS_CLASS_ARBITER0,Arbitration Parameters Between The Class 0 Request Groups"
|
|
bitfld.long 0x00 31. " BURSTCOMPLETE7 ,Delayed service until burst request complete BurstComplete for group 7" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 30. " BURSTCOMPLETE6 ,Delayed service until burst request complete BurstComplete for group 6" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " EXTENDEDGRANT7 ,Extended grant service inside a class (service for group 7 when granted)" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " EXTENDEDGRANT6 ,Extended grant service inside a class (service for group 6 when granted)" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 7. " HIGHPRIOVECTOR7 ,High priority attribute inside a class for group 7" "Standard,Highest"
|
|
textline " "
|
|
bitfld.long 0x00 6. " HIGHPRIOVECTOR6 ,High priority attribute inside a class for group 6" "Standard,Highest"
|
|
line.long 0x04 "SMS_CLASS_ARBITER1,Arbitration Parameters Between The Class 1 Request Groups"
|
|
bitfld.long 0x04 25. " BURSTCOMPLETE1 ,Delayed service until burst request complete BurstComplete for group 1" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x04 24. " BURSTCOMPLETE0 ,Delayed service until burst request complete BurstComplete for group 0" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " EXTENDEDGRANT1 ,Extended grant service inside a class (service for group 1 when granted)" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " EXTENDEDGRANT0 ,Extended grant service inside a class (service for group 0 when granted)" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x04 1. " HIGHPRIOVECTOR1 ,High priority attribute inside a class for group 1" "Standard,Highest"
|
|
textline " "
|
|
bitfld.long 0x04 0. " HIGHPRIOVECTOR0 ,High priority attribute inside a class for group 0" "Standard,Highest"
|
|
line.long 0x08 "SMS_CLASS_ARBITER2,Arbitration Parameters Between The Class 2 Request Groups"
|
|
bitfld.long 0x08 29. " BURSTCOMPLETE5 ,Delayed service until burst request complete BurstComplete for group 5" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x08 28. " BURSTCOMPLETE4 ,Delayed service until burst request complete BurstComplete for group 4" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x08 27. " BURSTCOMPLETE3 ,Delayed service until burst request complete BurstComplete for group 3" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x08 26. " BURSTCOMPLETE2 ,Delayed service until burst request complete BurstComplete for group 2" "Issued,Delayed"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " EXTENDEDGRANT5 ,Number of consecutive services" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 16.--17. " EXTENDEDGRANT4 ,Number of consecutive services" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 14.--15. " EXTENDEDGRANT3 ,Number of consecutive services" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " EXTENDEDGRANT2 ,Number of consecutive services" "Reserved,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIGHPRIOVECTOR5 ,High priority attribute inside a class for group 5" "Standard,Highest"
|
|
textline " "
|
|
bitfld.long 0x08 4. " HIGHPRIOVECTOR4 ,High priority attribute inside a class for group 4" "Standard,Highest"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHPRIOVECTOR3 ,High priority attribute inside a class for group 3" "Standard,Highest"
|
|
textline " "
|
|
bitfld.long 0x08 2. " HIGHPRIOVECTOR2 ,High priority attribute inside a class for group 2" "Standard,Highest"
|
|
group.long 0x160++0xF
|
|
line.long 0x00 "SMS_INTERCLASS_ARBITER,Priority Alternance Between Class 1/Class 2 Control Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CLASS2PRIO ,Class 2 high priority window width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLASS1PRIO ,Class 1 high priority window width"
|
|
line.long 0x4 "SMS_CLASS_ROTATION0,Number Of Consecutive Services Control Register"
|
|
hexmask.long.byte 0x4 0.--4. 1. " NOFSERVICES ,Number of RE split transactions serviced consecutively"
|
|
line.long 0x8 "SMS_CLASS_ROTATION1,Number Of Consecutive Services Control Register"
|
|
hexmask.long.byte 0x8 0.--4. 1. " NOFSERVICES ,Number of RE split transactions serviced consecutively"
|
|
line.long 0xC "SMS_CLASS_ROTATION2,Number Of Consecutive Services Control Register"
|
|
hexmask.long.byte 0xC 0.--4. 1. " NOFSERVICES ,Number of RE split transactions serviced consecutively"
|
|
rgroup.long 0x170++0x3
|
|
line.long 0x00 "SMS_ERR_ADDR,Address Of An Access That Has Generated An Error"
|
|
group.long 0x174++0x7
|
|
line.long 0x00 "SMS_ERR_TYPE,Additional Information About The Access That Has Generated The Error"
|
|
bitfld.long 0x00 24.--26. " ERRORREGIONID ,Region ID of the region that has been illegally accessed" "Region0,Region1,Region2,Region3,Region4,Region5,Region6,Region7"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " ERRORMCMD ,Interconnect command that caused the error" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " ERRORCONNID ,Identifies the illegal access initiator interconnect ConnID of the illegal access initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
eventfld.long 0x00 10. " UNEXPECTEDADD ,Unexpected request targeting nondefined rotation contexts" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 9. " UNEXPECTEDREQ ,Unexpected request received during SMS idle state" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 8. " ILLEGALCMD ,Illegal command on the L3 interface" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 3. " ERRORSECOVERLAP ,Protection region overlapping error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 2. " ERRORSECREG ,SMS security register accessed by nonsecure write transaction" "No violation,Detected"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ERRORSECURITY ,Security violation error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 0. " ERRORVALID ,Error validity status" "Not valid,Valid"
|
|
line.long 0x04 "SMS_POW_CTRL,SMS Power Management"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDLEDELAY ,Delay before autoidle"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL0,Virtual Rotated Frame Buffer Module For Context 0 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL1,Virtual Rotated Frame Buffer Module For Context 1 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL2,Virtual Rotated Frame Buffer Module For Context 2 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL3,Virtual Rotated Frame Buffer Module For Context 3 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL4,Virtual Rotated Frame Buffer Module For Context 4 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL5,Virtual Rotated Frame Buffer Module For Context 5 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x1E0++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL6,Virtual Rotated Frame Buffer Module For Context 6 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL7,Virtual Rotated Frame Buffer Module For Context 7 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL8,Virtual Rotated Frame Buffer Module For Context 8 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL9,Virtual Rotated Frame Buffer Module For Context 9 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL10,Virtual Rotated Frame Buffer Module For Context 10 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "SMS_ROT_CONTROL11,Virtual Rotated Frame Buffer Module For Context 11 Control Register"
|
|
bitfld.long 0x00 8.--10. " PH ,Indicates the page height in bytes" "0,1,2,3,?..."
|
|
bitfld.long 0x00 4.--6. " PW ,Indicates the page width in bytes" "0,1,2,3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PS ,Indicates the pixel size in bytes" "0,1,2,3"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE0,Bank Organization For Context 0 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 0"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 0"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE1,Bank Organization For Context 1 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 1"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 1"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE2,Bank Organization For Context 2 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 2"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 2"
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE3,Bank Organization For Context 3 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 3"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 3"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE4,Bank Organization For Context 4 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 4"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 4"
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE5,Bank Organization For Context 5 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 5"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 5"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE6,Bank Organization For Context 6 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 6"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 6"
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE7,Bank Organization For Context 7 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 7"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 7"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE8,Bank Organization For Context 8 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 8"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 8"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE9,Bank Organization For Context 9 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 9"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 9"
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE10,Bank Organization For Context 10 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 10"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 10"
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "SMS_ROT_SIZE11,Bank Organization For Context 11 Control Register"
|
|
hexmask.long.word 0x00 16.--26. 1. " IMAGEHEIGHT ,Image height in pixels for context 11"
|
|
hexmask.long.word 0x00 0.--10. 1. " IMAGEWIDTH ,Image width in pixels for context 11"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA0,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 0"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA1,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 1"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA2,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 2"
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA3,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 3"
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA4,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 4"
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA5,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 5"
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA6,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 6"
|
|
group.long 0x1F8++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA7,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 7"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA8,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 8"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA9,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 9"
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA10,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 10"
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "SMS_ROT_PHYSICAL_BA11,Physical Base Address For Context Control Register"
|
|
hexmask.long 0x00 0.--30. 1. " PHYSICALBA ,Physical base address of the frame buffer for context 11"
|
|
width 0xb
|
|
tree.end
|
|
tree "SDRC"
|
|
base ad:0x6D000000
|
|
width 18.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "SDRC_SYSCONFIG,Various Parameters Of The Interconnect"
|
|
bitfld.long 0x00 8. " NOMEMORYMRS ,No external Memory MRS command (MR/EMR1/EMR2 commands are performed to the external SDRAM)" "Performed,Not performed"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management req/ack control" "Reserved,Reserved,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "SDRC_SYSSTATUS,Module Status Information"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "SDRC_CS_CFG,Start Address Of The CS1 Address Space"
|
|
hexmask.long.byte 0x00 8.--9. 1. " CS1STARTLOW ,CS1 address space start address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--3. 1. " CS1STARTHIGH ,CS1 address space start address"
|
|
line.long 0x04 "SDRC_SHARING,SDRC Module Attached Memory Size And Position On The SDRC Module I/Os"
|
|
bitfld.long 0x04 30. " LOCK ,Read only access lock bit" "Fully writable,Set until next reset"
|
|
textline " "
|
|
bitfld.long 0x04 12.--14. " CS1MUXCFG ,Identifies the SDRC module pins used by CS1" "32-bit SDRAM on Datalane[31:0],32-bit SDRAM on Datalane[31:0],16-bit SDRAM on Datalane[31:16],16-bit SDRAM on Datalane[16:0],Reserved,Reserved,Reserved,16-bit SDRAM on Datalane[31:16]"
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " CS0MUXCFG ,Identifies the SDRC module pins used by CS0" "32-bit SDRAM on Datalane[31:0],32-bit SDRAM on Datalane[31:0],16-bit SDRAM on Datalane[31:16],16-bit SDRAM on Datalane[16:0],Reserved,Reserved,Reserved,16-bit SDRAM on Datalane[31:16]"
|
|
textline " "
|
|
bitfld.long 0x04 8. " SDRCTRISTATE ,Static tri-state command for the SDRC moduleI/O pads" "All SDRC tri-stated,Normal"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x00 "SDRC_ERR_ADDR,Captures The Address Of The Last Illegal Access Received On The Interconnect"
|
|
group.long 0x4C++0x3
|
|
line.long 0x00 "SDRC_ERR_TYPE,Additional Information About The Last Illegal Access"
|
|
bitfld.long 0x00 8.--11. " ERRORCONNID ,Identifies the illegal access initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " ERRORMCMD ,System command of the transaction that caused the error" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " ERRORADD ,Flag that indicates access to an illegal address" "Memory space,Register space,No Err Add,No Err Add"
|
|
textline " "
|
|
eventfld.long 0x00 1. " ERRORDPD ,Transaction error while the memory is in deep power-down mode" "Not in deep power-down,In deep power-down"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ERRORVALID ,Error validity status" "Not valid,Valid"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "SDRC_DLLA_CTRL,SDRC Module DLL Control"
|
|
hexmask.long.byte 0x00 24.--31. 1. " FIXEDDELAY ,Phase offset value in ModeFixedDelay mode"
|
|
textline " "
|
|
hexmask.long.byte 0x00 16.--23. 1. " MODEFIXEDDELAYINITLAT ,Initial latency before first request to be processed in ModeFixedDelay mode"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WRITEDDRCLKX2DIS ,Disable the MDDR write path using the double frequency input clk" "Double frequency clk,DLL/CDL write path"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " DLLMODEONIDLEREQ ,Selects the DLL mode upon hardware idle request" "Power-down,Idle,No action,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " DLLIDLE ,Enables the CQ0040v1 DLL Idle mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ENADLL ,Enable DLL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LOCKDLL ,Selects lock or unlock mode for DLL functionality" "TrackingDelay,FixedDelay"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DLLPHASE ,Nominal digitally controlled delay when DLL is enabled" "72 degrees,90 degrees"
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x00 "SDRC_DLLA_STATUS,Current Status Of The DLL A"
|
|
bitfld.long 0x00 2. " LOCKSTATUS ,DLL lock status" "Not locked,Locked"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "SDRC_POWER,The SDRC Power Management Register"
|
|
bitfld.long 0x00 26. " WAKEUPPROC ,SDRC wakeup in DDR mode (first request is stalled)" "500 latency cycles,DLL/CDL analog cell asserted"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--23. 1. " AUTOCOUNT ,16-bit programmable count value"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SRFRONRESET ,Enter self-refresh when a warm reset is applied" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SRFRONIDLEREQ ,Enter self-refresh when a hardware idle request is applied" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CLKCTRL ,Clock control feature defines clock gating and self-refresh" "No autolock,Internal clk gating,Self-refresh,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " EXTCLKDIS ,Disable the clock provided to the external memories" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PWDENA ,Activate the power-down mode of the target memory" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PAGEPOLICY ,Page/segment closure policy with respect to power versus bandwidth tradeoff" "Reserved,High power/high"
|
|
width 20.
|
|
if (((d.l((ad:0x6D000000+0x80)))&0x80000)==0x80000)
|
|
;The SDRC_MCFG_0 register has two distinct register descriptions. Bit no. 19. ADDRMUXLEGACY= Fixed or Flexible
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "SDRC_MCFG_0,Memory Configuration Register"
|
|
bitfld.long 0x00 30. " LOCKSTATUS ,Read only access lock bit" "Fully writable,Set until next reset"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " RASWIDTH ,RAS address width" "11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CASWIDTH ,CAS address width" "5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ADDRMUXLEGACY ,Fixed/Flexible address muxing scheme" "Fixed,Flexible"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--17. 1. " RAMSIZE ,RAM address space size"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BANKALLOCATION ,SDRAM bank mapping" "Bank-Row-Column,Bank1-Row-Bank0-Column,Row-Bank-Column,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " B32NOT16 ,External SDRAM bus width" "x16 bit,x32 bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DEEPPD ,Deep power-down mode" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DDRTYPE ,DDR memory type" "Mobile DDR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " RAMTYPE ,Memory type" "SDR-SDRAM,DDR-SDRAM,?..."
|
|
else
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "SDRC_MCFG_0,Memory Configuration Register"
|
|
bitfld.long 0x00 30. " LOCKSTATUS ,Read only access lock bit" "Fully writable,Set until next reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 20.--24. " ADDRMUX ,Address multiplexing scheme" "Address Mux Scheme 1,Address Mux Scheme 2,Address Mux Scheme 3,Address Mux Scheme 4,Address Mux Scheme 5,Address Mux Scheme 6,Address Mux Scheme 7,Address Mux Scheme 8,Address Mux Scheme 9,Address Mux Scheme 10,Address Mux Scheme 11,Address Mux Scheme 12,Address Mux Scheme 13,Address Mux Scheme 14,Address Mux Scheme 15,Address Mux Scheme 16,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Address Mux Scheme 23,Address Mux Scheme 24,Address Mux Scheme 25,Address Mux Scheme 26,Address Mux Scheme 27,Address Mux Scheme 28,Address Mux Scheme 29,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " ADDRMUXLEGACY ,Fixed/Flexible address muxing scheme" "Fixed,Flexible"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--17. 1. " RAMSIZE ,RAM address space size"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BANKALLOCATION ,SDRAM bank mapping" "Bank-Row-Column,Bank1-Row-Bank0-Column,Row-Bank-Column,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " B32NOT16 ,External SDRAM bus width" "x16 bit,x32 bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DEEPPD ,Deep power-down mode" "No deep power-down,deep power-down"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DDRTYPE ,DDR memory type" "Mobile DDR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " RAMTYPE ,Memory type" "SDR-SDRAM,DDR-SDRAM,?..."
|
|
endif
|
|
group.long (0x80+0x04)++0x3
|
|
line.long 0x00 "SDRC_MR_0,Corresponds To The JEDEC SDRAM MR Register"
|
|
bitfld.long 0x00 10.--11. " ZERO_1 ,Write 0s" "0,1,2,3"
|
|
bitfld.long 0x00 9. " WBST ,Write burst support" "Equals read burst,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " ZERO_0 ,Write 0s" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. " CASL ,CAS latency" "Reserved,1,2,3,4,5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " SIL ,Serial or interleaved mode" "Serial,Interleaved"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " BL ,Memory burst length" "1,2,4,8,Reserved,Reserved,Reserved,Full page"
|
|
group.long (0x80+0x08)++0x3
|
|
line.long 0x00 "SDRC_EMR2_0,Corresponds To The DDR1 EMR Register"
|
|
hexmask.long.byte 0x00 7.--11. 1. " ZERO ,Write 0s"
|
|
bitfld.long 0x00 5.--6. " DS ,Driver strength" "Full,Weak,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " TCSR ,Temperature compensated self-refresh" "70 degrees,45 degrees,15 degrees,85 degrees"
|
|
bitfld.long 0x00 0.--2. " PASR ,Partial array self-refresh" "All banks,1/2 array,1/4 array,Reserved,Reserved,1/8 array,1/16 array,?..."
|
|
group.long (0x80+0x1C)++0xF
|
|
line.long 0x00 "SDRC_ACTIM_CTRLA_0,The AC Timing Control Register A Sets The AC Parameter Values In The Clock Cycle Unit"
|
|
bitfld.long 0x00 27.--31. " TRFC ,Autorefresh to active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 22.--26. " TRC ,Row cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 18.--21. " TRAS ,Row active time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15.--17. " TRP ,Row precharge time" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " TRCD ,Row to column delay time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. " TRRD ,Active to active command period" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " TDPL ,Data-in to precharge command" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " TDAL ,Data-in to active command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "SDRC_ACTIM_CTRLB_0,The AC Timing Control Register B Sets The AC Parameter Values In The Clock Cycle Unit"
|
|
bitfld.long 0x04 16.--17. " TWTR ,Internal write to read command delay" "1 before,1,2,3"
|
|
bitfld.long 0x04 12.--14. " TCKE ,CKE minimum pulse width" "1,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " TXP ,Exit power-down to next valid command delay" "1 before,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXSR ,Self Refresh Exit to Active period"
|
|
line.long 0x08 "SDRC_RFR_CTRL_0,SDRAM Memory Autorefresh Control"
|
|
hexmask.long.word 0x08 8.--23. 1. " ARCV ,Autorefresh counter value"
|
|
bitfld.long 0x08 0.--1. " ARE ,Autorefresh enable" "Disabled,Loaded Arcv,Loaded 4xArcv,Loaded 8xArcv"
|
|
line.long 0x0C "SDRC_MANUAL_0,Allows To Send Specific Commands To The External Memory Devices Under Software Control"
|
|
hexmask.long.word 0x0C 16.--31. 1. " CMDPARAM ,Manual command parameter"
|
|
bitfld.long 0x0C 0.--3. " CMDCODE ,Memory command opcode" "NOP,Precharge all,Autorefresh,Enter deep power-down,Exit deep power-down,Enter self-refresh,Exit self-refresh,Set CKE signal high,Set CKE low,?..."
|
|
if (((d.l((ad:0x6D000000+0xB0)))&0x80000)==0x80000)
|
|
;The SDRC_MCFG_0 register has two distinct register descriptions. Bit no. 19. ADDRMUXLEGACY= Fixed or Flexible
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "SDRC_MCFG_1,Memory Configuration Register"
|
|
bitfld.long 0x00 30. " LOCKSTATUS ,Read only access lock bit" "Fully writable,Set until next reset"
|
|
textline " "
|
|
bitfld.long 0x00 24.--26. " RASWIDTH ,RAS address width" "11 bits,12 bits,13 bits,14 bits,15 bits,16 bits,17 bits,18 bits"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " CASWIDTH ,CAS address width" "5 bits,6 bits,7 bits,8 bits,9 bits,10 bits,11 bits,12 bits"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ADDRMUXLEGACY ,Fixed/Flexible address muxing scheme" "Fixed,Flexible"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--17. 1. " RAMSIZE ,RAM address space size"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BANKALLOCATION ,SDRAM bank mapping" "Bank-Row-Column,Bank1-Row-Bank0-Column,Row-Bank-Column,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " B32NOT16 ,External SDRAM bus width" "x16 bit,x32 bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DEEPPD ,Deep power-down mode" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DDRTYPE ,DDR memory type" "Mobile DDR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " RAMTYPE ,Memory type" "SDR-SDRAM,DDR-SDRAM,?..."
|
|
else
|
|
group.long 0xB0++0x3
|
|
line.long 0x00 "SDRC_MCFG_1,Memory Configuration Register"
|
|
bitfld.long 0x00 30. " LOCKSTATUS ,Read only access lock bit" "Fully writable,Set until next reset"
|
|
textline " "
|
|
textline " "
|
|
bitfld.long 0x00 20.--24. " ADDRMUX ,Address multiplexing scheme" "Address Mux Scheme 1,Address Mux Scheme 2,Address Mux Scheme 3,Address Mux Scheme 4,Address Mux Scheme 5,Address Mux Scheme 6,Address Mux Scheme 7,Address Mux Scheme 8,Address Mux Scheme 9,Address Mux Scheme 10,Address Mux Scheme 11,Address Mux Scheme 12,Address Mux Scheme 13,Address Mux Scheme 14,Address Mux Scheme 15,Address Mux Scheme 16,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Address Mux Scheme 23,Address Mux Scheme 24,Address Mux Scheme 25,Address Mux Scheme 26,Address Mux Scheme 27,Address Mux Scheme 28,Address Mux Scheme 29,?..."
|
|
textline " "
|
|
bitfld.long 0x00 19. " ADDRMUXLEGACY ,Fixed/Flexible address muxing scheme" "Fixed,Flexible"
|
|
textline " "
|
|
hexmask.long.word 0x00 8.--17. 1. " RAMSIZE ,RAM address space size"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " BANKALLOCATION ,SDRAM bank mapping" "Bank-Row-Column,Bank1-Row-Bank0-Column,Row-Bank-Column,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4. " B32NOT16 ,External SDRAM bus width" "x16 bit,x32 bit"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DEEPPD ,Deep power-down mode" "No deep power-down,deep power-down"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DDRTYPE ,DDR memory type" "Mobile DDR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " RAMTYPE ,Memory type" "SDR-SDRAM,DDR-SDRAM,?..."
|
|
endif
|
|
group.long (0xB0+0x04)++0x3
|
|
line.long 0x00 "SDRC_MR_1,Corresponds To The JEDEC SDRAM MR Register"
|
|
bitfld.long 0x00 10.--11. " ZERO_1 ,Write 0s" "0,1,2,3"
|
|
bitfld.long 0x00 9. " WBST ,Write burst support" "Equals read burst,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " ZERO_0 ,Write 0s" "0,1,2,3"
|
|
bitfld.long 0x00 4.--6. " CASL ,CAS latency" "Reserved,1,2,3,4,5,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " SIL ,Serial or interleaved mode" "Serial,Interleaved"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " BL ,Memory burst length" "1,2,4,8,Reserved,Reserved,Reserved,Full page"
|
|
group.long (0xB0+0x08)++0x3
|
|
line.long 0x00 "SDRC_EMR2_1,Corresponds To The DDR1 EMR Register"
|
|
hexmask.long.byte 0x00 7.--11. 1. " ZERO ,Write 0s"
|
|
bitfld.long 0x00 5.--6. " DS ,Driver strength" "Full,Weak,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " TCSR ,Temperature compensated self-refresh" "70 degrees,45 degrees,15 degrees,85 degrees"
|
|
bitfld.long 0x00 0.--2. " PASR ,Partial array self-refresh" "All banks,1/2 array,1/4 array,Reserved,Reserved,1/8 array,1/16 array,?..."
|
|
group.long (0xB0+0x1C)++0xF
|
|
line.long 0x00 "SDRC_ACTIM_CTRLA_1,The AC Timing Control Register A Sets The AC Parameter Values In The Clock Cycle Unit"
|
|
bitfld.long 0x00 27.--31. " TRFC ,Autorefresh to active" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 22.--26. " TRC ,Row cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 18.--21. " TRAS ,Row active time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15.--17. " TRP ,Row precharge time" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 12.--14. " TRCD ,Row to column delay time" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 9.--11. " TRRD ,Active to active command period" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 6.--8. " TDPL ,Data-in to precharge command" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--4. " TDAL ,Data-in to active command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "SDRC_ACTIM_CTRLB_1,The AC Timing Control Register B Sets The AC Parameter Values In The Clock Cycle Unit"
|
|
bitfld.long 0x04 16.--17. " TWTR ,Internal write to read command delay" "1 before,1,2,3"
|
|
bitfld.long 0x04 12.--14. " TCKE ,CKE minimum pulse width" "1,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " TXP ,Exit power-down to next valid command delay" "1 before,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x04 0.--7. 1. " TXSR ,Self Refresh Exit to Active period"
|
|
line.long 0x08 "SDRC_RFR_CTRL_1,SDRAM Memory Autorefresh Control"
|
|
hexmask.long.word 0x08 8.--23. 1. " ARCV ,Autorefresh counter value"
|
|
bitfld.long 0x08 0.--1. " ARE ,Autorefresh enable" "Disabled,Loaded Arcv,Loaded 4xArcv,Loaded 8xArcv"
|
|
line.long 0x0C "SDRC_MANUAL_1,Allows To Send Specific Commands To The External Memory Devices Under Software Control"
|
|
hexmask.long.word 0x0C 16.--31. 1. " CMDPARAM ,Manual command parameter"
|
|
bitfld.long 0x0C 0.--3. " CMDCODE ,Memory command opcode" "NOP,Precharge all,Autorefresh,Enter deep power-down,Exit deep power-down,Enter self-refresh,Exit self-refresh,Set CKE signal high,Set CKE low,?..."
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.open "Camera ISP"
|
|
tree "ISP"
|
|
base ad:0x480BC000
|
|
width 20.
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "ISP_SYSCONFIG,ISP System Configuration Register"
|
|
bitfld.long 0x00 12.--13. " MIDLE_MODE ,Master interface power management" "Force-standby,No-standby,Smart-standby,?..."
|
|
bitfld.long 0x00 1. " SOFT_RESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_IDLE ,Internal interface clock gating strategy" "Free running,Applied"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "ISP_SYSSTATUS,ISP System Status Register"
|
|
bitfld.long 0x00 0. " RESET_DONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x0C++0xF
|
|
line.long 0x00 "ISP_IRQ0ENABLE,Interrupt Enable Register To MCU"
|
|
bitfld.long 0x00 31. " HS_VS_IRQ ,HS or VS synchro event" "Masked,Enabled"
|
|
bitfld.long 0x00 30. " SEC_ERR_IRQ ,Security error event" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " OCP_ERR_IRQ ,ISP Interconnect error" "Masked,Enabled"
|
|
bitfld.long 0x00 28. " MMU_ERR_IRQ ,MMU error" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OVF_IRQ ,Central Resource SBL overflow" "Masked,Enabled"
|
|
bitfld.long 0x00 24. " RSZ_DONE_IRQ ,Resizer processing done event" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CBUFF_IRQ ,Circular buffer interrupt" "Masked,Enabled"
|
|
bitfld.long 0x00 20. " PRV_DONE_IRQ ,PREVIEW module - processing done event" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CCDC_LSC_PREFETCH_EROR ,The prefetch error indicates when the gain table was read to slowly from SDRAM" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " CCDC_LSC_PREFETCH_COMPLETED ,Indicates current state of the prefetch buffer" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CCDC_LSC_DONE ,The event is triggered when the internal state of LSC" "Masked,Enabled"
|
|
bitfld.long 0x00 16. " HIST_DONE_IRQ ,HIST module - processing done event" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " H3A_AWB_DONE_IRQ ,H3A module - auto exposure and auto white balance processing done event" "Masked,Enabled"
|
|
bitfld.long 0x00 12. " H3A_AF_DONE_IRQ ,H3A module - autofocus processing done event" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CCDC_ERR_IRQ ,CCDC module - faulty pixel correction memory underflow" "Masked,Enabled"
|
|
bitfld.long 0x00 10. " CCDC_VD2_IRQ ,CCDC module - programmable event 2" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CCDC_VD1_IRQ ,CCDC module - programmable event 1" "Masked,Enabled"
|
|
bitfld.long 0x00 8. " CCDC_VD0_IRQ ,CCDC module - programmable event 0" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CSIB_IRQ ,CSIB RECEIVER module event" "Masked,Enabled"
|
|
bitfld.long 0x00 3. " CSIB_LCM_IRQ ,CSIB RECEIVER module event on memory channel" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSIA_IRQ ,CSI2A RECEIVER module event" "Masked,Enabled"
|
|
line.long 0x04 "ISP_IRQ0STATUS,Interrupt Status Register"
|
|
eventfld.long 0x04 31. " HS_VS_IRQ ,HS or VS synchro event" "Not occurred,Occurred"
|
|
eventfld.long 0x04 30. " SEC_ERR_IRQ ,Security error event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 29. " OCP_ERR_IRQ ,ISP Interconnect error" "Not occurred,Occurred"
|
|
eventfld.long 0x04 28. " MMU_ERR_IRQ ,MMU error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 25. " OVF_IRQ ,Central Resource SBL overflow" "Not occurred,Occurred"
|
|
eventfld.long 0x04 24. " RSZ_DONE_IRQ ,Resizer processing done event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 21. " CBUFF_IRQ ,A circular buffer event is pending" "Not occurred,Occurred"
|
|
eventfld.long 0x04 20. " PRV_DONE_IRQ ,PREVIEW module - processing done event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 19. " CCDC_LSC_PREFETCH_ERROR ,The prefetch error indicates when the gain table was read to slowly from SDRAM" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 18. " CCDC_LSC_PREFETCH_COMPLETED ,Indicates current state of the prefetch buffer" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 17. " CCDC_LSC_DONE ,The event is triggered when the internal state of LSC toggles from BUSY to IDLE" "Not occurred,Occurred"
|
|
eventfld.long 0x04 16. " HIST_DONE_IRQ ,HIST module - processing done event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 13. " H3A_AWB_DONE_IRQ ,H3A module - auto exposure and auto white balance processing done event" "Not occurred,Occurred"
|
|
eventfld.long 0x04 12. " H3A_AF_DONE_IRQ ,H3A module - autofocus processing done event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 11. " CCDC_ERR_IRQ ,CCDC module - faulty pixel correction memory underflow" "Not occurred,Occurred"
|
|
eventfld.long 0x04 10. " CCDC_VD2_IRQ ,CCDC module - programmable event 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 9. " CCDC_VD1_IRQ ,CCDC module - programmable event 1" "Not occurred,Occurred"
|
|
eventfld.long 0x04 8. " CCDC_VD0_IRQ ,CCDC module - programmable event 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 4. " CSIB_IRQ ,CSIB RECEIVER module event" "Not occurred,Occurred"
|
|
eventfld.long 0x04 3. " CSIB_LCM_IRQ ,CSI1 RECEIVER module event on memory channel" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x04 0. " CSIA_IRQ ,CSIA RECEIVER module event" "Not occurred,Occurred"
|
|
line.long 0x08 "ISP_IRQ1ENABLE,Interrupt Enable Register To MCU"
|
|
bitfld.long 0x08 31. " HS_VS_IRQ ,HS or VS synchro event" "Masked,Enabled"
|
|
bitfld.long 0x08 30. " SEC_ERR_IRQ ,Security error event" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " OCP_ERR_IRQ ,ISP Interconnect error" "Masked,Enabled"
|
|
bitfld.long 0x08 28. " MMU_ERR_IRQ ,MMU error" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " OVF_IRQ ,Central Resource SBL overflow" "Masked,Enabled"
|
|
bitfld.long 0x08 24. " RSZ_DONE_IRQ ,Resizer processing done event" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " CBUFF_IRQ ,Circular buffer interrupt" "Masked,Enabled"
|
|
bitfld.long 0x08 20. " PRV_DONE_IRQ ,PREVIEW module - processing done event" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " CCDC_LSC_PREFETCH_EROR ,The prefetch error indicates when the gain table was read to slowly from SDRAM" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " CCDC_LSC_PREFETCH_COMPLETED ,Indicates current state of the prefetch buffer" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " CCDC_LSC_DONE ,The event is triggered when the internal state of LSC" "Masked,Enabled"
|
|
bitfld.long 0x08 16. " HIST_DONE_IRQ ,HIST module - processing done event" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " H3A_AWB_DONE_IRQ ,H3A module - auto exposure and auto white balance processing done event" "Masked,Enabled"
|
|
bitfld.long 0x08 12. " H3A_AF_DONE_IRQ ,H3A module - autofocus processing done event" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " CCDC_ERR_IRQ ,CCDC module - faulty pixel correction memory underflow" "Masked,Enabled"
|
|
bitfld.long 0x08 10. " CCDC_VD2_IRQ ,CCDC module - programmable event 2" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CCDC_VD1_IRQ ,CCDC module - programmable event 1" "Masked,Enabled"
|
|
bitfld.long 0x08 8. " CCDC_VD0_IRQ ,CCDC module - programmable event 0" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CSIB_IRQ ,CSIB RECEIVER module event" "Masked,Enabled"
|
|
bitfld.long 0x08 3. " CSIB_LCM_IRQ ,CSIB RECEIVER module event on memory channel" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " CSIA_IRQ ,CSI2A RECEIVER module event" "Masked,Enabled"
|
|
line.long 0x0C "ISP_IRQ1STATUS,Interrupt Status Register"
|
|
eventfld.long 0x0C 31. " HS_VS_IRQ ,HS or VS synchro event" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 30. " SEC_ERR_IRQ ,Security error event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0C 29. " OCP_ERR_IRQ ,ISP Interconnect error" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 28. " MMU_ERR_IRQ ,MMU error" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0C 25. " OVF_IRQ ,Central Resource SBL overflow" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 24. " RSZ_DONE_IRQ ,Resizer processing done event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0C 21. " CBUFF_IRQ ,A circular buffer event is pending" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 20. " PRV_DONE_IRQ ,PREVIEW module - processing done event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0C 19. " CCDC_LSC_PREFETCH_ERROR ,The prefetch error indicates when the gain table was read to slowly from SDRAM" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0C 18. " CCDC_LSC_PREFETCH_COMPLETED ,Indicates current state of the prefetch buffer" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0C 17. " CCDC_LSC_DONE ,The event is triggered when the internal state of LSC toggles from BUSY to IDLE" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 16. " HIST_DONE_IRQ ,HIST module - processing done event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0C 13. " H3A_AWB_DONE_IRQ ,H3A module - auto exposure and auto white balance processing done event" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 12. " H3A_AF_DONE_IRQ ,H3A module - autofocus processing done event" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0C 11. " CCDC_ERR_IRQ ,CCDC module - faulty pixel correction memory underflow" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 10. " CCDC_VD2_IRQ ,CCDC module - programmable event 2" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0C 9. " CCDC_VD1_IRQ ,CCDC module - programmable event 1" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 8. " CCDC_VD0_IRQ ,CCDC module - programmable event 0" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0C 4. " CSIB_IRQ ,CSIB RECEIVER module event" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 3. " CSIB_LCM_IRQ ,CSI1 RECEIVER module event on memory channel" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x0C 0. " CSIA_IRQ ,CSIA RECEIVER module event" "Not occurred,Occurred"
|
|
group.long 0x30++0x7
|
|
line.long 0x00 "TCTRL_GRESET_LENGTH,Timing Control - Global Shutter Length Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " LENGTH ,Sets the length of the cam_global_reset signal assertion"
|
|
line.long 0x04 "TCTRL_PSTRB_REPLAY,Timing Control - Prestrobe Replay Register"
|
|
hexmask.long.byte 0x04 25.--31. 1. " COUNTER ,Sets the number of PRESTROBE pulses after the original pulse"
|
|
hexmask.long 0x04 0.--24. 1. " DELAY ,Sets the delay for the PRESTROBE signal re-assertion"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "ISP_CTRL,Control Register After Reset"
|
|
bitfld.long 0x00 31. " FLUSH ,CCDC memory flush" "Not flushed,Flushed"
|
|
bitfld.long 0x00 30. " JPEG_FLUSH ,JPEG flush" "Not flushed,Flushed"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CCDC_WEN_POL ,Sets the polarity of the CCDC WEN bit" "Low,High"
|
|
bitfld.long 0x00 28. " SBL_SHARED_RPORTB ,Controls SBL shared read port B access" "Preview dark frame,CCDC lensshading"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SBL_SHARED_RPORTA ,Controls SBL shared read port A access" "Preview,CSI1"
|
|
bitfld.long 0x00 24.--25. " CBUFF1_BCF_CTRL ,Band width control feedback loop configuration register" "Disabled,Stalls response,Stalls request,Stalls response/request"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " CBUFF0_BCF_CTRL ,Controls SBL shared read port A access" "Disabled,Stalls response,Stalls request,Stalls response/request"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SBL_AUTOIDLE ,Sets the SBL autoidle mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SBL_WR0_RAM_EN ,SBL module WRITE0 RAM control" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SBL_WR1_RAM_EN ,SBL module WRITE1 RAM control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SBL_RD_RAM_EN ,SBL module READ RAM control" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PREV_RAM_EN ,PREVIEW module RAM control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CCDC_RAM_EN ,CCDC module RAM control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " SYNC_DETECT ,HS or VS synchronization signal detection" "HS falling edge,HS rising edge,VS falling edge,VS rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSZ_CLK_EN ,RSZ module clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PRV_CLK_EN ,PRV module clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " HIST_CLK_EN ,HIST module clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " H3A_CLK_EN ,H3A module clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CBUFF_AUTOGATING ,CBUFF module autogating feature control" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CCDC_CLK_EN ,CCDC module clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " SHIFT ,Data lane shifter" "No shift,Shift by 2,Shift by 4,Shift by 6"
|
|
bitfld.long 0x00 4. " PAR_CLK_POL ,Pixel clock polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " PAR_BRIDGE ,8 to 16-bit bridge at the input of the CCDC module" "Disabled,Reserved,Enabled [7:0]-[15:8],Enabled [15:8]-[7:0]"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PAR_SER_CLK_SEL ,Serial or parallel interface as the input to the preview hardware" "12-bit parallel,CSIA serial,CSIB serial,?..."
|
|
line.long 0x04 "ISP_SECURE,Security Control Register"
|
|
bitfld.long 0x04 0. " SECURE ,Secure mode" "Non secure,Secure"
|
|
group.long 0x50++0x2b
|
|
line.long 0x00 "TCTRL_CTRL,Timing Control Register"
|
|
bitfld.long 0x00 31. " GRESETDIR ,Sets the direction of the cam_global_reset signal" "Input,Output"
|
|
bitfld.long 0x00 30. " GRESETPOL ,Sets the polarity of the global reset signal" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 29. " GRESETEN ,Triggers the generation of the cam_global_reset signal" "No effect,Reset"
|
|
bitfld.long 0x00 27.--28. " INSEL ,Sets the mode that will trigger the SHUTTER/PRESTROBE/STROBE signals" "Parallel,CSIA,CSIB,GRESET"
|
|
textline " "
|
|
bitfld.long 0x00 26. " STRBPSTRBPOL ,Sets the polarity of the strobe and prestrobe signals" "Active high,Active low"
|
|
bitfld.long 0x00 24. " SHUTPOL ,Sets the polarity of the mechanical shutter signal" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 23. " STRBEN ,Flash strobe signal enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " PSTRBEN ,Flash prestrobe signal enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SHUTEN ,Mechanical shutter signal enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 10.--18. 1. " DIVC ,Sets the clock divisor value for CNTCLK clock"
|
|
textline " "
|
|
hexmask.long.byte 0x00 5.--9. 1. " DIVB ,Sets the clock divisor value for cam_xclkb clock"
|
|
hexmask.long.byte 0x00 0.--4. 1. " DIVA ,Sets the clock divisor value for cam_xclka clock"
|
|
line.long 0x04 "TCTRL_FRAME,Timing Control Frame Register"
|
|
bitfld.long 0x04 12.--17. " STRB ,Frame counter for the STROBE signal generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 6.--11. " PSTRB ,Frame counter for the PRESTROBE signal generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " SHUT ,Frame counter for the SHUTTER signal generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.long 0x08 "TCTRL_PSTRB_DELAY,Timing Control Pre Strobe Delay Register"
|
|
hexmask.long 0x08 0.--24. 1. " DELAY ,Sets the delay for the PRESTROBE signal assertion in cycles of the CNTCLK clock"
|
|
line.long 0x0C "TCTRL_STRB_DELAY,Timing Control Strobe Delay Register"
|
|
hexmask.long 0x0C 0.--24. 1. " DELAY ,Sets the delay for the cam_strobe signal assertion in cycles of the CNTCLK clock"
|
|
line.long 0x10 "TCTRL_SHUT_DELAY,Timing Control Shutter Delay Register"
|
|
hexmask.long 0x10 0.--24. 1. " DELAY ,Sets the delay for the cam_shutter signal assertion in cycles of the CNTCLK clock"
|
|
line.long 0x14 "TCTRL_PSTRB_LENGTH,Timing Control Prestrobe Length Register"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. " LENGTH ,Sets the length of the PRESTROBE signal assertion in cycles of the CNTCLK clock"
|
|
line.long 0x18 "TCTRL_STRB_LENGTH,Timing Control Strobe Length Register"
|
|
hexmask.long.tbyte 0x18 0.--23. 1. " LENGTH ,Sets the length of the cam_strobe signal assertion in cycles of the CNTCLK clock"
|
|
line.long 0x1C "TCTRL_SHUT_LENGTH,Timing Control Shutter Length Register"
|
|
hexmask.long.tbyte 0x1C 0.--23. 1. " LENGTH ,Sets the length of the cam_shutter signal assertion in cycles of the CNTCLK clock"
|
|
; line.long 0x20 "PING_PONG_ADDR,Ping Pong Address"
|
|
;
|
|
; line.long 0x24 "PING_PONG_MEM_RANGE,Ping Pong Memory Range"
|
|
; hexmask.long 0x24 0.--24. 1. " MEM_RANGE ,Sets the memory range used for ping ponging"
|
|
;
|
|
; line.long 0x28 "PING_PONG_BUF_SIZE,Ping Pong Buffer Size"
|
|
; hexmask.long.tbyte 0x28 0.--20. 1. " BUF_SIZE ,Sets the PING and PONG buffer sizes"
|
|
width 0xb
|
|
tree.end
|
|
tree "CSI1_RECEIVER"
|
|
tree "ISP_CBUFF"
|
|
base ad:0x480BC100
|
|
width 19.
|
|
group.long 0x18++0xF
|
|
line.long 0x00 "CBUFF_IRQSTATUS,Status Information About The Module Internal Events"
|
|
bitfld.long 0x00 5. " IRQ_CBUFF1_OVR ,Buffer overflow event" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " IRQ_CBUFF1_INVALID ,Invalid access" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQ_CBUFF1_READY ,The CPUW1 physical buffer is ready to be accessed by the CPU" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " IRQ_CBUFF0_OVR ,Buffer overflow event" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQ_CBUFF0_INVALID ,Invalid access" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " IRQ_CBUFF0_READY ,The CPUW0 physical buffer is ready to be accessed by the CPU" "No interrupt,Interrupt"
|
|
line.long 0x04 "CBUFF_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 5. " IRQ_CBUFF1_OVR ,Buffer overflow event" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " IRQ_CBUFF1_INVALID ,Invalid access" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " IRQ_CBUFF1_READY ,The CPUW1 physical buffer is ready to be accessed by the CPU" "Masked,Enabled"
|
|
bitfld.long 0x04 2. " IRQ_CBUFF0_OVR ,Buffer overflow event" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IRQ_CBUFF0_INVALID ,Invalid access" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " IRQ_CBUFF0_READY ,The CPUW0 physical buffer is ready to be accessed by the CPU" "Masked,Enabled"
|
|
line.long 0x8 "CBUFF0_CTRL,Circular Buffer 0 Control Register"
|
|
bitfld.long 0x8 8.--9. " WCOUNT ,Window count" "2 windows,4 windows,8 windows,16 windows"
|
|
bitfld.long 0x8 4.--7. " BCF ,Bandwidth control feedback loop output control" "Disabled,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x8 3. " ALLOW_NW_EQ_CPUW ,Allow NW=CPUW" "CPUW and NW,CPUW and CW"
|
|
bitfld.long 0x8 2. " DONE ,Indicate the CPU has finished processing its physical buffer" "No effect,Finished"
|
|
textline " "
|
|
bitfld.long 0x8 1. " RWMODE ,Selects read or write mode" "Write,Read"
|
|
bitfld.long 0x8 0. " ENABLE ,Enable/disable" "Disabled,Enabled"
|
|
line.long 0xC "CBUFF1_CTRL,Circular Buffer 1 Control Register"
|
|
bitfld.long 0xC 8.--9. " WCOUNT ,Window count" "2 windows,4 windows,8 windows,16 windows"
|
|
bitfld.long 0xC 4.--7. " BCF ,Bandwidth control feedback loop output control" "Disabled,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0xC 3. " ALLOW_NW_EQ_CPUW ,Allow NW=CPUW" "CPUW and NW,CPUW and CW"
|
|
bitfld.long 0xC 2. " DONE ,Indicate the CPU has finished processing its physical buffer" "No effect,Finished"
|
|
textline " "
|
|
bitfld.long 0xC 1. " RWMODE ,Selects read or write mode" "Write,Read"
|
|
bitfld.long 0xC 0. " ENABLE ,Enable/disable" "Disabled,Enabled"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "CBUFF0_STATUS,Threshold Value Used To Check If The CW Or NW Windows Are Full"
|
|
bitfld.long 0x0 16.--19. " NW ,Next window number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0 8.--11. " CW ,Current window number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x0 0.--3. " CPUW ,Current CPU window number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x4 "CBUFF1_STATUS,Threshold Value Used To Check If The CW Or NW Windows Are Full"
|
|
bitfld.long 0x4 16.--19. " NW ,Next window number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " CW ,Current window number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 0.--3. " CPUW ,Current CPU window number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "CBUFF0_START,Start address of the virtual space managed by circular buffer 0"
|
|
hexmask.long 0x0 3.--31. 0x8 " ADDR ,Address"
|
|
line.long 0x4 "CBUFF1_START,Start address of the virtual space managed by circular buffer 1"
|
|
hexmask.long 0x4 3.--31. 0x8 " ADDR ,Address"
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "CBUFF0_END,End address of the virtual space managed by circular buffer 0"
|
|
hexmask.long 0x0 3.--31. 0x8 " ADDR ,Address"
|
|
line.long 0x4 "CBUFF1_END,End address of the virtual space managed by circular buffer 1"
|
|
hexmask.long 0x4 3.--31. 0x8 " ADDR ,Address"
|
|
group.long 0x60++0x7
|
|
line.long 0x0 "CBUFF0_WINDOWSIZE,Defines The Window Size"
|
|
hexmask.long.tbyte 0x0 3.--23. 1. " SIZE ,Size"
|
|
line.long 0x4 "CBUFF1_WINDOWSIZE,Defines The Window Size"
|
|
hexmask.long.tbyte 0x4 3.--23. 1. " SIZE ,Size"
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "CBUFF0_THRESHOLD,Threshold Value Used To Check If A Write Window Is Full"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. " THRESHOLD ,Threshold value"
|
|
line.long 0x4 "CBUFF1_THRESHOLD,Threshold Value Used To Check If A Write Window Is Full"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " THRESHOLD ,Threshold value"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "ISP_CCDC"
|
|
base ad:0x480BC600
|
|
width 21.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "CCDC_PID,Peripherial ID Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TID ,Peripheral identification"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CID ,Class identification"
|
|
group.long 0x04++0xA3
|
|
line.long 0x00 "CCDC_PCR,Peripherial Control Register"
|
|
bitfld.long 0x00 1. " BUSY ,CCDC module busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " ENABLE ,CCDC module enable" "Disabled,Enabled"
|
|
line.long 0x04 "CCDC_SYN_MODE,SYNC And Mode Set Register"
|
|
bitfld.long 0x04 19. " SDR2RSZ ,Memory port output into the RESIZER input" "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " VP2SDR ,Video port output enable to the output formatter" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " WEN ,Data write enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " VDHDEN ,Timing generator enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FLDSTAT ,cam_fld signal status" "Odd,Even"
|
|
bitfld.long 0x04 14. " LPF ,Three-tap low pass filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " INPMOD ,cam_d format in SYNC mode" "Raw,YCbCr 16bit,YCbCr 8bit,?..."
|
|
bitfld.long 0x04 11. " PACK8 ,Data packing" "Normal,Pack"
|
|
textline " "
|
|
bitfld.long 0x04 8.--10. " DATSIZ ,cam_d signal width in SYNC mode" "8 bit,Reserved,Reserved,Reserved,12 bits,11 bits,10 bits,8 bits"
|
|
bitfld.long 0x04 7. " FLDMODE ,cam_fld signal mode" "Progressive,Interlaced"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DATAPOL ,cam_d signal polarity" "Normal,Ones complement"
|
|
bitfld.long 0x04 5. " EXWEN ,External write enable selection" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x04 4. " FLDPOL ,cam_fld signal polarity" "Positive,Negative"
|
|
bitfld.long 0x04 3. " HDPOL ,Sets the cam_hs signal polarity" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x04 2. " VDPOL ,cam_vs signal polarity" "Positive,Negative"
|
|
bitfld.long 0x04 1. " FLDOUT ,cam_fld signal direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VDHDOUT ,cam_hs and cam_vs signal directions" "Input,Output"
|
|
line.long 0x08 "CCDC_HD_VD_WID,Sync Width Control Register"
|
|
hexmask.long.word 0x08 16.--27. 1. " HDW ,Width of the HS sync pulse if set as output"
|
|
hexmask.long.word 0x08 0.--11. 1. " VDW ,Width of the VS sync pulse is set as output"
|
|
line.long 0x0C "CCDC_PIX_LINES,Size Control Register"
|
|
hexmask.long.byte 0x0C 16.--31. 1. " PPLN ,Pixels per line"
|
|
hexmask.long.byte 0x0C 0.--15. 1. " HLPRF ,Half line per field or frame"
|
|
line.long 0x10 "CCDC_HORZ_INFO,Horizontal Pixel Info Register"
|
|
hexmask.long.byte 0x10 16.--30. 1. " SPH ,Start pixel horizontal"
|
|
hexmask.long.byte 0x10 0.--14. 1. " NPH ,Number of pixels horizontal"
|
|
line.long 0x14 "CCDC_VERT_START,Vertical Line Start Register"
|
|
hexmask.long.byte 0x14 16.--30. 1. " SLV0 ,Start line vertical - field0"
|
|
hexmask.long.byte 0x14 0.--14. 1. " SLV1 ,Start line vertical - field1"
|
|
line.long 0x18 "CCDC_VERT_LINES,Vertical Line Number Register"
|
|
hexmask.long.byte 0x18 0.--14. 1. " NLV ,Number of lines - vertical direction"
|
|
line.long 0x1C "CCDC_CULLING,Cull Control Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " CULHEVN ,Horizontal culling patterns for even lines"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " CULHODD ,Horizontal culling patterns for odd lines"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " CULV ,Vertical culling pattern"
|
|
line.long 0x20 "CCDC_HSIZE_OFF,Horizontal Size Register"
|
|
hexmask.long.word 0x20 0.--15. 1. " LMOFST , Line offset"
|
|
line.long 0x24 "CCDC_SDOFST,Memory Offset Register"
|
|
bitfld.long 0x24 14. " FIINV ,Field identification signal inverse" "Non Inverse,Inverse"
|
|
bitfld.long 0x24 12.--13. " FOFST ,Line offset value" "+1 line,+2 line,+3 line,+4 line"
|
|
textline " "
|
|
bitfld.long 0x24 9.--11. " LOFST0 ,Line offset values of even lines and even fields" "+1 line,+2 line,+3 line,+4 line,-1 line,-2 line,-3 line,-4 line"
|
|
bitfld.long 0x24 6.--8. " LOFST1 ,Line offset values of odd lines and even fields" "+1 line,+2 line,+3 line,+4 line,-1 line,-2 line,-3 line,-4 line"
|
|
textline " "
|
|
bitfld.long 0x24 3.--5. " LOFST2 ,Line offset values of even lines and odd fields" "+1 line,+2 line,+3 line,+4 line,-1 line,-2 line,-3 line,-4 line"
|
|
bitfld.long 0x24 0.--2. " LOFST3 ,Line offset values of odd lines and odd fields" "+1 line,+2 line,+3 line,+4 line,-1 line,-2 line,-3 line,-4 line"
|
|
line.long 0x28 "CCDC_SDR_ADDR,Memory Address Register"
|
|
line.long 0x2C "CCDC_CLAMP,Clamp Control Register"
|
|
bitfld.long 0x2C 31. " CLAMPEN ,Clamp enable" "Disabled,Enable"
|
|
bitfld.long 0x2C 28.--30. " OBSLEN ,Optical black sample length" "1 pixel,2 pixels,4 pixels,8 pixels,16 pixels,?..."
|
|
textline " "
|
|
bitfld.long 0x2C 25.--27. " OBSLN ,Optical black sample lines" "1 line,2 lines,4 lines,8 lines,16 lines,?..."
|
|
hexmask.long.word 0x2C 10.--24. 1. " OBST ,Start pixel of optical black samples"
|
|
textline " "
|
|
hexmask.long.byte 0x2C 0.--4. 1. " OBGAIN ,Gain to apply to the optical black average"
|
|
line.long 0x30 "CCDC_DCSUB,DC Clamp Register"
|
|
hexmask.long.word 0x30 0.--13. 1. " DCSUB ,DC value to subtract from the data"
|
|
line.long 0x34 "CCDC_COLPTN,Color Pattern Register"
|
|
bitfld.long 0x34 30.--31. " CP3LPC3 ,Collor pattern 3rd line pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x34 28.--29. " CP3LPC2 ,Collor pattern 3rd line pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x34 26.--27. " CP3LPC1 ,Collor pattern 3rd line pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x34 24.--25. " CP3LPC0 ,Collor pattern 3rd line pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x34 22.--23. " CP2PLC3 ,Collor pattern 2nd line pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x34 20.--21. " CP2PLC2 ,Collor pattern 2nd line pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x34 18.--19. " CP2PLC1 ,Collor pattern 2nd line pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x34 16.--17. " CP2PLC0 ,Collor pattern 2nd line pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x34 14.--15. " CP1PLC3 ,Collor pattern 1st line pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x34 12.--13. " CP1PLC2 ,Collor pattern 1st line pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x34 10.--11. " CP1PLC1 ,Collor pattern 1st line pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x34 8.--9. " CP1PLC0 ,Collor pattern 1st line pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x34 6.--7. " CP0PLC3 ,Collor pattern 0th line pixel counter = 3" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x34 4.--5. " CP0PLC2 ,Collor pattern 0th line pixel counter = 2" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
textline " "
|
|
bitfld.long 0x34 2.--3. " CP0PLC1 ,Collor pattern 0th line pixel counter = 1" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
bitfld.long 0x34 0.--1. " CP0PLC0 ,Collor pattern 0th line pixel counter = 0" "R/Ye,Gr/Cy,Gb/G,B/Mg"
|
|
line.long 0x38 "CCDC_BLKCMP,Black Compensation Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " R_YE ,Black level compensation R/Ye pixels"
|
|
hexmask.long.byte 0x38 16.--23. 1. " GR_CY ,Black level compensation Gr/Cy pixels"
|
|
textline " "
|
|
hexmask.long.byte 0x38 8.--15. 1. " GB_G ,Black level compensation Gb/G pixels"
|
|
hexmask.long.byte 0x38 0.--7. 1. " B_MG ,Black level compensation B/Mg pixels"
|
|
line.long 0x3C "CCDC_FPC,Fault Pixel Correction Register"
|
|
bitfld.long 0x3C 16. " FPERR ,Fault pixel correction error" "No error,Error"
|
|
bitfld.long 0x3C 15. " FPCEN ,Fault pixel correction enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x3C 0.--14. 1. " FPNUM ,Number of fault pixels to be corrected in the frame"
|
|
line.long 0x40 "CCDC_FPC_ADDR,Fault Pixel Correction Memory Address"
|
|
line.long 0x44 "CCDC_VDINT,VD Interrupt Register"
|
|
hexmask.long.word 0x44 16.--30. 1. " VDINT0 ,VD0 interrupt timing"
|
|
hexmask.long.word 0x44 0.--14. 1. " VDINT1 ,VD1 interrupt timing"
|
|
line.long 0x48 "CCDC_ALAW,Alaw Settings Register"
|
|
bitfld.long 0x48 3. " CCDTBL ,Apply A-Law compression to data saved to memory" "Disabled,Enabled"
|
|
bitfld.long 0x48 0.--2. " GWDI ,A-Law input width" "Reserved,Reserved,Reserved,Bits 12 to 3,Bits 11 to 2,Bits 10 to 1,Bits 9 to 0,?..."
|
|
line.long 0x4C "CCDC_REC656IF,ITU-R BT.656 Configuration Register"
|
|
bitfld.long 0x4C 1. " ECCFVH ,FVH error correction enable" "Disabled,Enabled"
|
|
bitfld.long 0x4C 0. " R656ON ,ITU-R BT656 interface enable" "Disabled,Enabled"
|
|
line.long 0x50 "CCDC_CFG,Configuration Register"
|
|
bitfld.long 0x50 15. " VDLC ,Enable latching function registers on the internal VS sync pulse" "Latched,Not latched"
|
|
bitfld.long 0x50 13. " MSBINVI ,MSB of chroma input signal stored to memory inverted" "Normal,MSB inverted"
|
|
textline " "
|
|
bitfld.long 0x50 12. " BSWD ,Byte swap data stored to memory" "Normal,Swap bytes"
|
|
bitfld.long 0x50 11. " Y8POS ,Location of Y color component when YCbCr 8-bit data is input" "Even pixel,Odd pixel"
|
|
textline " "
|
|
bitfld.long 0x50 8. " WENLOG ,Valid area settings" "ANDed,ORed"
|
|
bitfld.long 0x50 6.--7. " FIDMD ,Settings of field identification detection function (FLD signal at the VS timing)" "Latched,Not latched,Latched at edge,Latched on phase VS/HS"
|
|
textline " "
|
|
bitfld.long 0x50 5. " BW656 ,The data width in ITU-R BT656 input mode" "8 bits,10 bits"
|
|
line.long 0x54 "CCDC_FMTCFG,Data Reformatter/Video IF Config Register"
|
|
bitfld.long 0x54 16.--18. " VPIF_FRQ ,Video port data ready frequency" "1/2,1/3.5,1/4.5,1/5.5,1/6.5,?..."
|
|
bitfld.long 0x54 15. " VPEN ,Video port enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x54 12.--14. " VPIN ,10-bit input select for video port" "Reserved,Reserved,Reserved,Bits 12-3,Bits 11-2,Bits 10-1,Bits 9-0,?..."
|
|
bitfld.long 0x54 8.--11. " PLEN_EVEN ,Number of program entries in even line minus 1" "1,2,3,4,5,6,7,8,?..."
|
|
textline " "
|
|
bitfld.long 0x54 4.--7. " PLEN_ODD ,Number of program entries in odd line minus 1" "1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x54 2.--3. " LNUM ,Number of output lines from 1 input line" "1 line,2 lines,3 lines,4 lines"
|
|
textline " "
|
|
bitfld.long 0x54 1. " LNALT ,Line alternating mode enable" "Enabled,Disabled"
|
|
bitfld.long 0x54 0. " FMTEN ,Formatter enable" "Disabled,Enabled"
|
|
line.long 0x58 "CCDC_FMT_HORZ,Data Reformatter Horiz Info Register"
|
|
hexmask.long.word 0x58 16.--28. 1. " FMTSPH ,Start pixel horizontal from start of the HS sync pulse"
|
|
hexmask.long.word 0x58 0.--12. 1. " FMTLNH ,Number of pixels in horizontal direction to use for the data reformatter"
|
|
line.long 0x5C "CCDC_FMT_VERT,Data Reformatter Vert Info Register"
|
|
hexmask.long.word 0x5C 16.--28. 1. " FMTSLV ,Start line from start of VS sync pulse for the data reformatter"
|
|
hexmask.long.word 0x5C 0.--12. 1. " FMTLNV ,Number of lines in vertical direction for the data reformatter"
|
|
line.long 0x60 "CCDC_FMT_ADDR0,Data Reformatter Addr PTR 0 Setup Register"
|
|
bitfld.long 0x60 24.--25. " LINE ,The output line the address belongs to" "1st,2nd,3rd,4th"
|
|
hexmask.long.word 0x60 0.--12. 1. " INIT ,Initial address value"
|
|
line.long 0x64 "CCDC_FMT_ADDR1,Data Reformatter Addr PTR 1 Setup Register"
|
|
bitfld.long 0x64 24.--25. " LINE ,The output line the address belongs to" "1st,2nd,3rd,4th"
|
|
hexmask.long.word 0x64 0.--12. 1. " INIT ,Initial address value"
|
|
line.long 0x68 "CCDC_FMT_ADDR2,Data Reformatter Addr PTR 2 Setup Register"
|
|
bitfld.long 0x68 24.--25. " LINE ,The output line the address belongs to" "1st,2nd,3rd,4th"
|
|
hexmask.long.word 0x68 0.--12. 1. " INIT ,Initial address value"
|
|
line.long 0x6C "CCDC_FMT_ADDR3,Data Reformatter Addr PTR 3 Setup Register"
|
|
bitfld.long 0x6C 24.--25. " LINE ,The output line the address belongs to" "1st,2nd,3rd,4th"
|
|
hexmask.long.word 0x6C 0.--12. 1. " INIT ,Initial address value"
|
|
line.long 0x70 "CCDC_FMT_ADDR4,Data Reformatter Addr PTR 4 Setup Register"
|
|
bitfld.long 0x70 24.--25. " LINE ,The output line the address belongs to" "1st,2nd,3rd,4th"
|
|
hexmask.long.word 0x70 0.--12. 1. " INIT ,Initial address value"
|
|
line.long 0x74 "CCDC_FMT_ADDR5,Data Reformatter Addr PTR 5 Setup Register"
|
|
bitfld.long 0x74 24.--25. " LINE ,The output line the address belongs to" "1st,2nd,3rd,4th"
|
|
hexmask.long.word 0x74 0.--12. 1. " INIT ,Initial address value"
|
|
line.long 0x78 "CCDC_FMT_ADDR6,Data Reformatter Addr PTR 6 Setup Register"
|
|
bitfld.long 0x78 24.--25. " LINE ,The output line the address belongs to" "1st,2nd,3rd,4th"
|
|
hexmask.long.word 0x78 0.--12. 1. " INIT ,Initial address value"
|
|
line.long 0x7C "CCDC_FMT_ADDR7,Data Reformatter Addr PTR 7 Setup Register"
|
|
bitfld.long 0x7C 24.--25. " LINE ,The output line the address belongs to" "1st,2nd,3rd,4th"
|
|
hexmask.long.word 0x7C 0.--12. 1. " INIT ,Initial address value"
|
|
line.long 0x80 "CCDC_PRGEVEN0,Program Entries 0-7 For Even Lines Register"
|
|
bitfld.long 0x80 29.--31. " EVEN7[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x80 28. " EVEN7[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x80 25.--27. " EVEN6[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x80 24. " EVEN6[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x80 21.--23. " EVEN5[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x80 20. " EVEN5[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x80 17.--19. " EVEN4[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x80 16. " EVEN4[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x80 13.--15. " EVEN3[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x80 12. " EVEN3[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x80 9.--11. " EVEN2[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x80 8. " EVEN2[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x80 5.--7. " EVEN1[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x80 4. " EVEN1[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x80 1.--3. " EVEN0[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x80 0. " EVEN0[0] ,Address update" "Increment,Decrment"
|
|
line.long 0x84 "CCDC_PRGEVEN1,Program Entries 8-15 For Even Lines Register"
|
|
bitfld.long 0x84 29.--31. " EVEN15[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x84 28. " EVEN15[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x84 25.--27. " EVEN14[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x84 24. " EVEN14[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x84 21.--23. " EVEN13[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x84 20. " EVEN13[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x84 17.--19. " EVEN12[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x84 16. " EVEN12[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x84 13.--15. " EVEN11[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x84 12. " EVEN11[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x84 9.--11. " EVEN10[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x84 8. " EVEN10[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x84 5.--7. " EVEN9[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x84 4. " EVEN9[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x84 1.--3. " EVEN8[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x84 0. " EVEN8[0] ,Address update" "Increment,Decrment"
|
|
line.long 0x88 "CCDC_PRGODD0,Program Entries 0-7 For Even Lines Register"
|
|
bitfld.long 0x88 29.--31. " ODD7[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x88 28. " ODD7[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x88 25.--27. " ODD6[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x88 24. " ODD6[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x88 21.--23. " ODD5[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x88 20. " ODD5[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x88 17.--19. " ODD4[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x88 16. " ODD4[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x88 13.--15. " ODD3[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x88 12. " ODD3[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x88 9.--11. " ODD2[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x88 8. " ODD2[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x88 5.--7. " ODD1[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x88 4. " ODD1[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x88 1.--3. " ODD0[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x88 0. " ODD0[0] ,Address update" "Increment,Decrment"
|
|
line.long 0x8C "CCDC_PRGODD1,Program Entries 8-15 For Even Lines Register"
|
|
bitfld.long 0x8C 29.--31. " ODD15[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x8C 28. " ODD15[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x8C 25.--27. " ODD14[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x8C 24. " ODD14[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x8C 21.--23. " ODD13[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x8C 20. " ODD13[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x8C 17.--19. " ODD12[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x8C 16. " ODD12[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x8C 13.--15. " ODD11[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x8C 12. " ODD11[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x8C 9.--11. " ODD10[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x8C 8. " ODD10[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x8C 5.--7. " ODD9[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x8C 4. " ODD9[0] ,Address update" "Increment,Decrment"
|
|
textline " "
|
|
bitfld.long 0x8C 1.--3. " ODD8[3:1] ,Address update" "ADDR0,ADDR1,ADDR2,ADDR3,ADDR4,ADDR5,ADDR6,ADDR7"
|
|
bitfld.long 0x8C 0. " ODD8[0] ,Address update" "Increment,Decrment"
|
|
line.long 0x90 "CCDC_VP_OUT,Video Port Output Register"
|
|
hexmask.long.word 0x90 17.--30. 1. " VERT_NUM ,Number of vertical lines to clock out the video"
|
|
hexmask.long.word 0x90 4.--16. 1. " HORZ_NUM ,Number of horizontal pixel to clock out the video port"
|
|
textline " "
|
|
bitfld.long 0x90 0.--3. " HORZ_ST ,Horizontal start pixel in each output line" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x94 "CCDC_LSC_CONFIG,Lens Shading Compensation Control And Status Register"
|
|
bitfld.long 0x94 12.--14. " GAIN_MODE_M ,Define the horizontal dimension of a paxel" "M=4,M=8,M=16,M=32,M=64,?..."
|
|
bitfld.long 0x94 8.--10. " GAIN_MODE_N ,Define the vertical dimension of a paxel" "N=4,N=8,N=16,N=32,N=64,?..."
|
|
textline " "
|
|
bitfld.long 0x94 7. " BUSY ,Module busy or idle" "Idle,Busy"
|
|
bitfld.long 0x94 6. " AFTER_REFORMATTER ,Chooses if lens-shading compensation is done before/after data reformatting" "Before,After"
|
|
textline " "
|
|
bitfld.long 0x94 1.--3. " GAIN_FORMAT ,Sets gain table format" "8-bit fraction,8-bit fraction+1.0 of base,1-bit integer/7-bit fraction,1-bit integer/7-bit fraction+1.0,2-bit integer/6-bit fraction,2-bit integer/6-bit fraction+1.0,3-bit integer/5-bit fraction,3-bit integer/5-bit fraction+1.0"
|
|
textline " "
|
|
bitfld.long 0x94 0. " ENABLE ,Enables/disables LSC" "Disabled,Enabled"
|
|
line.long 0x98 "CCDC_LSC_INITIAL,Lens Shading Compensation Initial X/Y Register"
|
|
hexmask.long.byte 0x98 16.--21. 1. " Y ,Y position in pixels"
|
|
hexmask.long.byte 0x98 0.--5. 1. " X ,X position in pixels"
|
|
line.long 0x9C "CCDC_LSC_TABLE_BASE,Lens Shading Compensation Table Base Address Register"
|
|
line.long 0xA0 "CCDC_LSC_TABLE_OFFSET,Lens Shading Compensation Table Offset Register"
|
|
hexmask.long.word 0xA0 0.--15. 1. " OFFSET ,Defines the length in bytes of one row of the gain table"
|
|
width 0xb
|
|
tree.end
|
|
tree "ISP_HIST"
|
|
base ad:0x480BCA00
|
|
width 17.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "HIST_PID,Peripherial ID Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TID ,Peripheral identification: HIST MODULE"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CID ,Class identification: CAMERA ISP"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREV ,Peripheral revision number"
|
|
group.long 0x04++0x3F
|
|
line.long 0x00 "HIST_PCR,Peripherial Control Register"
|
|
bitfld.long 0x00 1. " BUSY ,HIST module busy" "Not busy,Busy"
|
|
bitfld.long 0x00 0. " ENABLE ,HIST module enable" "Disabled,Enabled"
|
|
line.long 0x04 "HIST_CNT,Histogram Control Register"
|
|
bitfld.long 0x04 8. " DATSIZ ,Input data width (pixels coded)" ">8 bits,=8 bits"
|
|
bitfld.long 0x04 7. " CLR ,Clear histogram data after read" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x04 6. " CFA ,CFA pattern" "Bayer,Foveon"
|
|
bitfld.long 0x04 4.--5. " BINS ,Number of bins" "32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x04 3. " SOURCE ,Input source" "CCDC,Memory"
|
|
bitfld.long 0x04 0.--2. " SHIFT ,Shift value" "0,1,2,3,4,5,6,7"
|
|
line.long 0x08 "HIST_WB_GAIN,Histogram White Balance Gain Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " WG00 ,White balance gain 00"
|
|
hexmask.long.byte 0x08 16.--23. 1. " WG01 ,White balance gain 01"
|
|
textline " "
|
|
hexmask.long.byte 0x08 8.--15. 1. " WG02 ,White balance gain 02"
|
|
hexmask.long.byte 0x08 0.--7. 1. " WG03 ,White balance gain 03"
|
|
line.long 0xC "HIST_R0_HORZ,Region 0 Horizontal Register"
|
|
hexmask.long.word 0xC 16.--29. 1. " HSTART ,Horizontal start position for REGION 0"
|
|
hexmask.long.word 0xC 0.--13. 1. " HEND ,Horizontal end position for REGION 0"
|
|
line.long 0x10 "HIST_R0_VERT,Region 0 Vertical Register"
|
|
hexmask.long.word 0x10 16.--29. 1. " VSTART ,Vertical start position for REGION 0"
|
|
hexmask.long.word 0x10 0.--13. 1. " VEND ,Vertical end position for REGION 0"
|
|
line.long 0x14 "HIST_R1_HORZ,Region 1 Horizontal Register"
|
|
hexmask.long.word 0x14 16.--29. 1. " HSTART ,Horizontal start position for REGION 1"
|
|
hexmask.long.word 0x14 0.--13. 1. " HEND ,Horizontal end position for REGION 1"
|
|
line.long 0x18 "HIST_R1_VERT,Region 1 Vertical Register"
|
|
hexmask.long.word 0x18 16.--29. 1. " VSTART ,Vertical start position for REGION 1"
|
|
hexmask.long.word 0x18 0.--13. 1. " VEND ,Vertical end position for REGION 1"
|
|
line.long 0x1C "HIST_R2_HORZ,Region 2 Horizontal Register"
|
|
hexmask.long.word 0x1C 16.--29. 1. " HSTART ,Horizontal start position for REGION 2"
|
|
hexmask.long.word 0x1C 0.--13. 1. " HEND ,Horizontal end position for REGION 2"
|
|
line.long 0x20 "HIST_R2_VERT,Region 2 Vertical Register"
|
|
hexmask.long.word 0x20 16.--29. 1. " VSTART ,Vertical start position for REGION 2"
|
|
hexmask.long.word 0x20 0.--13. 1. " VEND ,Vertical end position for REGION 2"
|
|
line.long 0x24 "HIST_R3_HORZ,Region 3 Horizontal Register"
|
|
hexmask.long.word 0x24 16.--29. 1. " HSTART ,Horizontal start position for REGION 3"
|
|
hexmask.long.word 0x24 0.--13. 1. " HEND ,Horizontal end position for REGION 3"
|
|
line.long 0x28 "HIST_R3_VERT,Region 3 Vertical Register"
|
|
hexmask.long.word 0x28 16.--29. 1. " VSTART ,Vertical start position for REGION 3"
|
|
hexmask.long.word 0x28 0.--13. 1. " VEND ,Vertical end position for REGION 3"
|
|
line.long 0x2C "HIST_ADDR,Histogram Address Register"
|
|
hexmask.long.word 0x2C 0.--9. 1. " ADDR ,Histogram memory address"
|
|
line.long 0x30 "HIST_DATA,Histogram Data Register"
|
|
hexmask.long.tbyte 0x30 0.--19. 1. " RDATA ,Histogram data"
|
|
line.long 0x34 "HIST_RADD,Address Register"
|
|
hexmask.long 0x34 0.--31. 0x20 " HIST_RADD ,Address"
|
|
line.long 0x38 "HIST_RADD_OFF,Address Offset Register"
|
|
hexmask.long.word 0x38 0.--15. 1. " OFFSET ,Offset value"
|
|
line.long 0x3C "HIST_H_V_INFO,Image Size Register"
|
|
hexmask.long.word 0x3C 16.--29. 1. " HSIZE ,Horizontal size"
|
|
hexmask.long.word 0x3C 0.--13. 1. " VSIZE ,Vertical size"
|
|
width 0xb
|
|
tree.end
|
|
tree "ISP_H3A"
|
|
base ad:0x480BCC00
|
|
width 17.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "HIST_PID,Peripherial ID Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TID ,Peripheral identification: H3A module"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CID ,Class identification: CAMERA ISP"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREV ,Peripheral revision number"
|
|
group.long 0x04++0x5B
|
|
line.long 0x00 "H3A_PCR,Peripherial Control Register"
|
|
hexmask.long.word 0x00 22.--31. 1. " AVE2LMT ,AE AWB saturation limit"
|
|
bitfld.long 0x00 18. " BUSYAEAWB ,AE AWB busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 17. " AEW_ALAW_EN ,AE AWB A-Law enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " AEW_EN ,AE AWB enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BUSYAF ,AF busy" "Not busy,Busy"
|
|
bitfld.long 0x00 14. " FVMODE ,Focus value accumulation mode" "Sum,Peak"
|
|
textline " "
|
|
bitfld.long 0x00 11.--13. " RGBPOS ,RGB pixel position in the AF windows" "GR/GB,RG/GB,GR/BG,RG/BG,GG/RB,RB/GG,?..."
|
|
hexmask.long.byte 0x00 3.--10. 1. " MED_TH ,Median filter threshold"
|
|
textline " "
|
|
bitfld.long 0x00 2. " AF_MED_EN ,AF median filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " AF_ALAW_EN ,AF A-Law table enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AF_EN ,AF enable" "Disabled,Enabled"
|
|
line.long 0x04 "H3A_AFPAX1,AF Paxel Configuration"
|
|
hexmask.long.byte 0x04 16.--22. 1. " PAXW ,Paxel width"
|
|
hexmask.long.byte 0x04 0.--6. 1. " PAXH ,Paxel height"
|
|
line.long 0x08 "H3A_AFPAX2,AF Paxel Configuration"
|
|
bitfld.long 0x08 13.--16. " AFINCV ,AF line increments" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32"
|
|
hexmask.long.byte 0x08 6.--12. 1. " PAXVC ,Paxel count in the vertical direction"
|
|
textline " "
|
|
bitfld.long 0x08 0.--5. " PAXHC ,Paxel count in the horizontal direction" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,?..."
|
|
line.long 0x0C "H3A_AFPAXSTART,AF Paxel Start Position Register"
|
|
hexmask.long.word 0x0C 16.--27. 1. " PAXSH ,AF paxel horizontal start position"
|
|
hexmask.long.word 0x0C 0.--11. 1. " PAXSV ,AF paxel vertical start position"
|
|
line.long 0x10 "H3A_AFIIRSH,AF IIR Horizontal Start Position Register"
|
|
hexmask.long.word 0x10 0.--11. 1. " IIRSH ,AF IIR horizontal start position"
|
|
line.long 0x14 "H3A_AFBUFST,AF Memory Address"
|
|
hexmask.long 0x14 5.--31. 1. " AFBUFST ,AF memory address"
|
|
line.long 0x18 "H3A_AFCOEF010,IIR Filter Coef Data Register - Set 0"
|
|
hexmask.long.word 0x18 16.--27. 1. " COEFF1 ,AF IIR filter coefficient 1"
|
|
hexmask.long.word 0x18 0.--11. 1. " COEFF0 ,AF IIR filter coefficient 0"
|
|
line.long 0x1C "H3A_AFCOEF032,IIR Filter Coef Data Register - Set 0"
|
|
hexmask.long.word 0x1C 16.--27. 1. " COEFF3 ,AF IIR filter coefficient 3"
|
|
hexmask.long.word 0x1C 0.--11. 1. " COEFF2 ,AF IIR filter coefficient 2"
|
|
line.long 0x20 "H3A_AFCOEF054,IIR Filter Coef Data Register - Set 0"
|
|
hexmask.long.word 0x20 16.--27. 1. " COEFF5 ,AF IIR filter coefficient 5"
|
|
hexmask.long.word 0x20 0.--11. 1. " COEFF4 ,AF IIR filter coefficient 4"
|
|
line.long 0x24 "H3A_AFCOEF076,IIR Filter Coef Data Register - Set 0"
|
|
hexmask.long.word 0x24 16.--27. 1. " COEFF7 ,AF IIR filter coefficient 7"
|
|
hexmask.long.word 0x24 0.--11. 1. " COEFF6 ,AF IIR filter coefficient 6"
|
|
line.long 0x28 "H3A_AFCOEF098,IIR Filter Coef Data Register - Set 0"
|
|
hexmask.long.word 0x28 16.--27. 1. " COEFF9 ,AF IIR filter coefficient 9"
|
|
hexmask.long.word 0x28 0.--11. 1. " COEFF8 ,AF IIR filter coefficient 8"
|
|
line.long 0x2C "H3A_AFCOEF0010,IIR Filter Coef Data Register - Set 0"
|
|
hexmask.long.word 0x2C 0.--11. 1. " COEFF10 ,AF IIR filter coefficient 10"
|
|
line.long 0x30 "H3A_AFCOEF110,IIR Filter Coef Data Register - Set 1"
|
|
hexmask.long.word 0x30 16.--27. 1. " COEFF1 ,AF IIR filter coefficient 1"
|
|
hexmask.long.word 0x30 0.--11. 1. " COEFF0 ,AF IIR filter coefficient 0"
|
|
line.long 0x34 "H3A_AFCOEF132,IIR Filter Coef Data Register - Set 1"
|
|
hexmask.long.word 0x34 16.--27. 1. " COEFF3 ,AF IIR filter coefficient 3"
|
|
hexmask.long.word 0x34 0.--11. 1. " COEFF2 ,AF IIR filter coefficient 2"
|
|
line.long 0x38 "H3A_AFCOEF154,IIR Filter Coef Data Register - Set 1"
|
|
hexmask.long.word 0x38 16.--27. 1. " COEFF5 ,AF IIR filter coefficient 5"
|
|
hexmask.long.word 0x38 0.--11. 1. " COEFF4 ,AF IIR filter coefficient 4"
|
|
line.long 0x3C "H3A_AFCOEF176,IIR Filter Coef Data Register - Set 1"
|
|
hexmask.long.word 0x3C 16.--27. 1. " COEFF7 ,AF IIR filter coefficient 7"
|
|
hexmask.long.word 0x3C 0.--11. 1. " COEFF6 ,AF IIR filter coefficient 6"
|
|
line.long 0x40 "H3A_AFCOEF198,IIR Filter Coef Data Register - Set 1"
|
|
hexmask.long.word 0x40 16.--27. 1. " COEFF9 ,AF IIR filter coefficient 9"
|
|
hexmask.long.word 0x40 0.--11. 1. " COEFF8 ,AF IIR filter coefficient 8"
|
|
line.long 0x44 "H3A_AFCOEF1010,IIR Filter Coef Data Register - Set 1"
|
|
hexmask.long.word 0x44 0.--11. 1. " COEFF10 ,AF IIR filter coefficient 10"
|
|
line.long 0x48 "H3A_AEWWIN1,AE AWB Control Register"
|
|
hexmask.long.byte 0x48 24.--30. 1. " WINH ,AE AWB window height"
|
|
hexmask.long.byte 0x48 13.--19. 1. " WINW ,AE AWB window width"
|
|
textline " "
|
|
hexmask.long.byte 0x48 6.--12. 1. " WINVC ,AE AWB vertical window count"
|
|
bitfld.long 0x48 0.--5. " WINHC ,AE AWB horizontal window count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,?..."
|
|
line.long 0x4C "H3A_AEWINSTART,AE AWB Start Position Register"
|
|
hexmask.long.word 0x4C 16.--27. 1. " WINSV ,AE AWB vertical window start position"
|
|
hexmask.long.word 0x4C 0.--11. 1. " WINSH ,AE AWB horizontal window start position"
|
|
line.long 0x50 "H3A_AEWINBLK,Black Line Register"
|
|
hexmask.long.word 0x50 16.--27. 1. " WINSV ,AE AWB vertical window start position for the single black line of windows"
|
|
hexmask.long.byte 0x50 0.--6. 1. " WINH ,AE AWB window height for the single black line of windows"
|
|
line.long 0x54 "H3A_AEWSUBWIN,AE AWB Register"
|
|
bitfld.long 0x54 8.--11. " AEWINCV ,AE AWB vertical sampling point increment" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32"
|
|
bitfld.long 0x54 0.--3. " AEWINCH ,AE AWB horizontal sampling point increment" "2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32"
|
|
line.long 0x58 "H3A_AEWBUFST,AE AWB Memory Address"
|
|
hexmask.long 0x58 5.--31. 1. " AEWBUFST ,AE AWB memory address"
|
|
width 0xb
|
|
tree.end
|
|
tree "ISP_PREVIEW"
|
|
base ad:0x480BCE00
|
|
width 17.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "PRV_PID,Peripherial ID Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TID ,Peripheral identification: PREVIEW module"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CID ,Class identification: CAMERA ISP"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREV ,Peripheral revision number"
|
|
group.long 0x04++0x83
|
|
line.long 0x00 "PRV_PCR,Peripherial Control Register"
|
|
bitfld.long 0x00 31. " DRK_FAIL ,Dark frame subtract fail status" "No error,Error"
|
|
bitfld.long 0x00 28. " DCOR_METHOD ,Defect correction method" "MinMax,MinMax2"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DCOREN ,Defect correction enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GAMMA_BYPASS ,Gamma bypass" "No bypass,Bypass"
|
|
textline " "
|
|
bitfld.long 0x00 22.--24. " SCOMP_SFT ,Shading compensation shift value after multiplication" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 21. " SCOMP_EN ,Shading compensation enable instead of dark frame" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SDRPORT ,PREVIEW module memory output port enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " RSZPORT ,RESIZER module output port enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--18. " YCPOS ,(CRYCBY) Cr0(31:24) Y1(23:16) Cb0(15:8) Y0(7:0)" "(YCRYCB) Y1(31:24)Cr0(23:16)Y0(15:8)Cb0(7:0),(YCBYCR) Y1(31:24)Cb0(23:16)Y0(15:8)Cr0(7:0),(CBYCRY) Cb0(31:24)Y1(23:16)Cr(15:8)Y0(7:0),(CRYCBY) Cr0(31:24)Y1(23:16)Cb0(15:8)Y0(7:0)"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SUPEN ,Color suppression" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " YNENHEN ,Non-linear enhancer" "Disabled,Enabled"
|
|
bitfld.long 0x00 11.--14. " CFAFMT ,CFA format" "Conventional Bayer,Horiz 2xdownsample,Bypass CFA stage (RGB Foveon),Horiz/vert 2xdownsample,Fuji Honeycom,Bypass CFA stage,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10. " CFAEN ,CFA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " NFEN ,Noise filter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " HMEDEN ,Horizontal median filter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " DRKFCAP ,Dark frame capture enable" "Normal,Captured"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DRKFEN ,Subtract dark frame enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " INVALAW ,Inverse A-Law enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WIDTH ,Input data width selection" "10-bit,8-bit"
|
|
bitfld.long 0x00 3. " ONESHOT ,One-shot mode selection" "Continuous,One shot"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SOURCE ,Input source selection" "Video port,Memory"
|
|
bitfld.long 0x00 1. " BUSY ,Busy bit" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Enable bit (PREVIEW)" "Disabled,Enabled"
|
|
line.long 0x04 "PRV_HORZ_INFO,Horizontal Setup Register"
|
|
hexmask.long.word 0x04 16.--29. 1. " SPH ,Start pixel horizontal"
|
|
hexmask.long.word 0x04 0.--13. 1. " EPH ,End pixel horizontal"
|
|
line.long 0x08 "PRV_VERT_INFO,Vertical Setup Register"
|
|
hexmask.long.word 0x08 16.--29. 1. " SLV ,Start line vertical"
|
|
hexmask.long.word 0x08 0.--13. 1. " ELV ,End line vertical"
|
|
line.long 0x0C "PRV_RSDR_ADDR,Memory Read Address Register"
|
|
line.long 0x10 "PRV_RADR_OFFSET,Memory Read Address Offset Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " OFFSET ,Line offset"
|
|
line.long 0x14 "PRV_DSDR_ADDR,Dark Frame Memory Address Register"
|
|
line.long 0x18 "PRV_DRKF_OFFSET,Dark Frame Memory Offset Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " OFFSET ,Dark frame line offset"
|
|
line.long 0x1C "PRV_WSDR_ADDR,Memory Write Address Register"
|
|
line.long 0x20 "PRV_WADD_OFFSET,Memory Write Offset Register"
|
|
hexmask.long.word 0x20 0.--15. 1. " OFFSET ,Line offset"
|
|
line.long 0x24 "PRV_AVE,Input Formatter Register"
|
|
bitfld.long 0x24 4.--5. " ODDDIST ,Distance between consecutive pixels of the same color in the odd line" "1,2,3,4"
|
|
bitfld.long 0x24 2.--3. " EVENDIST ,Distance between consecutive pixels of the same color in the even line" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x24 0.--1. " COUNT ,Number of horizontal pixels to average" "No averaging,2-pixel,4-pixel,8-pixel"
|
|
line.long 0x28 "PRV_HMED,Horizontal Median Filter Register"
|
|
bitfld.long 0x28 9. " ODDDIST ,Distance between consecutive pixels of the same color in the odd line" "1,2"
|
|
bitfld.long 0x28 8. " EVENDIST ,Distance between consecutive pixels of the same color in even line" "1,2"
|
|
textline " "
|
|
hexmask.long.byte 0x28 0.--7. 1. " THRESHOLD ,Horizontal median filter threshold"
|
|
line.long 0x2C "PRV_NF,Noise Filter Register"
|
|
bitfld.long 0x2C 0.--1. " SPR ,The spread value in noise filter algorithm" "0,1,2,3"
|
|
line.long 0x30 "PRV_WB_DGAIN,White Balance Coef Register"
|
|
hexmask.long.word 0x30 0.--9. 1. " DGAIN ,Digital gain for the white balance"
|
|
line.long 0x34 "PRV_WBGAIN,White Balance Coef Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " COEF3 ,White balance gain - COEF3"
|
|
hexmask.long.byte 0x34 16.--23. 1. " COEF2 ,White balance gain - COEF2"
|
|
textline " "
|
|
hexmask.long.byte 0x34 8.--15. 1. " COEF1 ,White balance gain - COEF1"
|
|
hexmask.long.byte 0x34 0.--7. 1. " COEF0 ,White balance gain - COEF0"
|
|
line.long 0x38 "PRV_WBSEL,White Balance Coef Selection Register"
|
|
bitfld.long 0x38 30.--31. " N3_3 ,Coefficient selection for 3nd line, 3rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
bitfld.long 0x38 28.--29. " N3_2 ,Coefficient selection for 3nd line, 2rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
textline " "
|
|
bitfld.long 0x38 26.--27. " N3_1 ,Coefficient selection for 3nd line, 1rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
bitfld.long 0x38 24.--25. " N3_0 ,Coefficient selection for 3nd line, 0rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
textline " "
|
|
bitfld.long 0x38 22.--23. " N2_3 ,Coefficient selection for 2nd line, 3rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
bitfld.long 0x38 20.--21. " N2_2 ,Coefficient selection for 2nd line, 2rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
textline " "
|
|
bitfld.long 0x38 18.--19. " N2_1 ,Coefficient selection for 2nd line, 1rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
bitfld.long 0x38 16.--17. " N2_0 ,Coefficient selection for 2nd line, 0rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
textline " "
|
|
bitfld.long 0x38 14.--15. " N1_3 ,Coefficient selection for 1st line, 3rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
bitfld.long 0x38 12.--13. " N1_2 ,Coefficient selection for 1st line, 2rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
textline " "
|
|
bitfld.long 0x38 10.--11. " N1_1 ,Coefficient selection for 1st line, 1rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
bitfld.long 0x38 8.--9. " N1_0 ,Coefficient selection for 1st line, 0rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
textline " "
|
|
bitfld.long 0x38 6.--7. " N0_3 ,Coefficient selection for 0rd line, 3rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
bitfld.long 0x38 4.--5. " N0_2 ,Coefficient selection for 0rd line, 2rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
textline " "
|
|
bitfld.long 0x38 2.--3. " N0_1 ,Coefficient selection for 0rd line, 1rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
bitfld.long 0x38 0.--1. " N0_0 ,Coefficient selection for 0rd line, 0rd pixel" "COEF0,COEF1,COEF2,COEF3"
|
|
line.long 0x3C "PRV_CFA,Color Filter Array Register"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " GRADTH_VER ,Gradient threshold vertical"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " GRADTH_HOR ,Gradient threshold horizontal"
|
|
line.long 0x40 "PRV_BLKADJOFF,Black Adjustment Offset Register"
|
|
hexmask.long.byte 0x40 16.--23. 1. " R ,Black-level offset adjustment for RED"
|
|
hexmask.long.byte 0x40 8.--15. 1. " G ,Black-level offset adjustment for GREEN"
|
|
textline " "
|
|
hexmask.long.byte 0x40 0.--7. 1. " B ,Black-level offset adjustment for BLUE"
|
|
line.long 0x44 "PRV_RGB_MAT1,RGB to RGB Matrix Coef Register"
|
|
hexmask.long.word 0x44 16.--27. 1. " MTX_GR ,Blending value for GR position"
|
|
hexmask.long.word 0x44 0.--11. 1. " MTX_RR ,Blending value for RR position"
|
|
line.long 0x48 "PRV_RGB_MAT2,RGB to RGB Matrix Coef Register"
|
|
hexmask.long.word 0x48 16.--27. 1. " MTX_RG ,Blending value for RG position"
|
|
hexmask.long.word 0x48 0.--11. 1. " MTX_BR ,Blending value for BR position"
|
|
line.long 0x4C "PRV_RGB_MAT3,RGB to RGB Matrix Coef Register"
|
|
hexmask.long.word 0x4C 16.--27. 1. " MTX_BG ,Blending value for BG position"
|
|
hexmask.long.word 0x4C 0.--11. 1. " MTX_GG ,Blending value for GG position"
|
|
line.long 0x50 "PRV_RGB_MAT4,RGB to RGB Matrix Coef Register"
|
|
hexmask.long.word 0x50 16.--27. 1. " MTX_GB ,Blending value for GB position"
|
|
hexmask.long.word 0x50 0.--11. 1. " MTX_RB ,Blending value for RB position"
|
|
line.long 0x54 "PRV_RGB_MAT5,RGB to RGB Matrix Coef Register"
|
|
hexmask.long.word 0x54 0.--11. 1. " MTX_BB ,Blending value for BB position"
|
|
line.long 0x58 "PRV_RGB_OFF1,RGB to RGB Matrix Offset Register"
|
|
hexmask.long.word 0x58 16.--25. 1. " MTX_OFFR ,Blending offset value for RED"
|
|
hexmask.long.word 0x58 0.--9. 1. " MTX_OFFG ,Blending offset value for GREEN"
|
|
line.long 0x5C "PRV_RGB_OFF2,RGB to RGB Matrix Offset Register"
|
|
hexmask.long.word 0x5C 0.--9. 1. " MTX_OFFB ,Blending offset value for BLUE"
|
|
line.long 0x60 "PRV_CSC0,Color Space Conversion Coef Register"
|
|
hexmask.long.word 0x60 20.--29. 1. " CSCBY ,Color space conversion coefficient of BLUE for computing Y"
|
|
hexmask.long.word 0x60 10.--19. 1. " CSCGY ,Color space conversion coefficient of GREEN for computing Y"
|
|
textline " "
|
|
hexmask.long.word 0x60 0.--9. 1. " CSCRY ,Color space conversion coefficient of RED for computing Y"
|
|
line.long 0x64 "PRV_CSC1,Color Space Conversion Coef Register"
|
|
hexmask.long.word 0x64 20.--29. 1. " CSCBCB ,Color space conversion coefficient of BLUE for computing Y"
|
|
hexmask.long.word 0x64 10.--19. 1. " CSCGCB ,Color space conversion coefficient of GREEN for computing Y"
|
|
textline " "
|
|
hexmask.long.word 0x64 0.--9. 1. " CSCRCB ,Color space conversion coefficient of RED for computing Cb"
|
|
line.long 0x68 "PRV_CSC2,Color Space Conversion Coef Register"
|
|
hexmask.long.word 0x68 20.--29. 1. " CSCBCR ,Color space conversion coefficient of BLUE for computing Cr"
|
|
hexmask.long.word 0x68 10.--19. 1. " CSCGCR ,Color space conversion coefficient of GREEN for computing Cr"
|
|
textline " "
|
|
hexmask.long.word 0x68 0.--9. 1. " CSCRCR ,Color space conversion coefficient of RED for computing Cr"
|
|
line.long 0x6C "PRV_CSC_OFFSET,Color Space Conversion Coef Register"
|
|
hexmask.long.word 0x6C 16.--23. 1. " YOFST ,DC offset value for Y component"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " OFSTCB ,DC offset value for Cb component"
|
|
textline " "
|
|
hexmask.long.byte 0x6C 0.--7. 1. " OFSTCR ,DC offset value for Cr component"
|
|
line.long 0x70 "PRV_CNT_BRT,Contrast Set Register"
|
|
hexmask.long.byte 0x70 8.--15. 1. " CNT ,Contrast adjustment"
|
|
hexmask.long.byte 0x70 0.--7. 1. " BRT ,Brightness adjustment"
|
|
line.long 0x74 "PRV_CSUP,Chrominance Suppression Set Register"
|
|
bitfld.long 0x74 16. " HPYF ,Use high-pass filter of luminance for chroma suppression" "Disabled,Enabled"
|
|
hexmask.long.byte 0x74 8.--15. 1. " CSUPTH ,Chroma suppression threshold"
|
|
textline " "
|
|
hexmask.long.byte 0x74 0.--7. 1. " CSUPG ,Gain value for chroma suppression function"
|
|
line.long 0x78 "PRV_SETUP_YC,Y And C Set Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " MAXY ,Maximum Y value"
|
|
hexmask.long.byte 0x78 16.--23. 1. " MINY ,Minimum Y value"
|
|
textline " "
|
|
hexmask.long.byte 0x78 8.--15. 1. " MAXC ,Maximum Cb and Cr values"
|
|
hexmask.long.byte 0x78 0.--7. 1. " MINC ,Minimum Cb and Cr values"
|
|
line.long 0x7C "PRV_SET_TBL_ADDR,Set Table Address Register"
|
|
hexmask.long.word 0x7C 0.--12. 1. " ADDR ,13-bit address"
|
|
line.long 0x80 "PRV_SET_TBL_DATA,Setup Table Data Register"
|
|
hexmask.long.tbyte 0x80 0.--19. 1. " DATA ,Data to be written"
|
|
group.long 0x90++0x13
|
|
line.long 0x0 "PRV_CDC_THR0,Couplet Defect Correction Threshold Register For Color0"
|
|
hexmask.long.word 0x0 16.--25. 1. " CORRECT ,Correction threshold when couplet defect correction selected"
|
|
hexmask.long.word 0x0 0.--9. 1. " DETECT ,Detection threshold when couplet defect correction selected"
|
|
line.long 0x4 "PRV_CDC_THR1,Couplet Defect Correction Threshold Register For Color1"
|
|
hexmask.long.word 0x4 16.--25. 1. " CORRECT ,Correction threshold when couplet defect correction selected"
|
|
hexmask.long.word 0x4 0.--9. 1. " DETECT ,Detection threshold when couplet defect correction selected"
|
|
line.long 0x8 "PRV_CDC_THR2,Couplet Defect Correction Threshold Register For Color2"
|
|
hexmask.long.word 0x8 16.--25. 1. " CORRECT ,Correction threshold when couplet defect correction selected"
|
|
hexmask.long.word 0x8 0.--9. 1. " DETECT ,Detection threshold when couplet defect correction selected"
|
|
line.long 0xC "PRV_CDC_THR3,Couplet Defect Correction Threshold Register For Color3"
|
|
hexmask.long.word 0xC 16.--25. 1. " CORRECT ,Correction threshold when couplet defect correction selected"
|
|
hexmask.long.word 0xC 0.--9. 1. " DETECT ,Detection threshold when couplet defect correction selected"
|
|
line.long 0x10 "PRV_CDC_THR4,Couplet Defect Correction Threshold Register For Color4"
|
|
hexmask.long.word 0x10 16.--25. 1. " CORRECT ,Correction threshold when couplet defect correction selected"
|
|
hexmask.long.word 0x10 0.--9. 1. " DETECT ,Detection threshold when couplet defect correction selected"
|
|
width 0xb
|
|
tree.end
|
|
tree "ISP_RESIZER"
|
|
base ad:0x480BD000
|
|
width 17.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "RSZ_PID,Peripherial ID Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TID ,Peripheral identification: RESIZER module"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CID ,Class identification: CAMERA ISP"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREV ,Peripheral revision number"
|
|
group.long 0x04++0xA7
|
|
line.long 0x00 "RSZ_PCR,Peripherial Control Register"
|
|
bitfld.long 0x00 2. " ONESHOT ,One-shot or continuous mode selection" "Continuous,One shot"
|
|
bitfld.long 0x00 1. " BUSY ,RESIZER module busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,RESIZER module enable" "Disabled,Enabled"
|
|
line.long 0x04 "RSZ_CNT,Resizer Control Register"
|
|
bitfld.long 0x04 29. " CBILIN ,Chrominance horizontal algorithm select" "Same as luminance,Bilinear interpolation"
|
|
textline " "
|
|
bitfld.long 0x04 28. " INPSRC ,Input source select" "PREVIEW/CCDC,Memory"
|
|
textline " "
|
|
bitfld.long 0x04 27. " INPTYP ,Input type select" "YUV422 color interleaved,Color separate data"
|
|
textline " "
|
|
bitfld.long 0x04 26. " YCPOS ,Luminance and chrominance position in 16-bit word" "YC,CY"
|
|
textline " "
|
|
bitfld.long 0x04 23.--25. " VSTPH ,Vertical starting phase" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 20.--22. " HSTPH ,Vertical resizing value" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
hexmask.long.word 0x04 10.--19. 1. " VRSZ ,Vertical resizing value"
|
|
hexmask.long.word 0x04 0.--9. 1. " HRSZ ,Horizontal resizing value"
|
|
line.long 0x08 "RSZ_OUT_SIZE,Output Size Register"
|
|
hexmask.long.word 0x08 16.--26. 1. " VERT ,Ouput height"
|
|
hexmask.long.word 0x08 0.--10. 1. " HORZ ,Output width in the horizontal direction"
|
|
line.long 0x0C "RSZ_IN_START,Input Configuration Register"
|
|
hexmask.long.word 0x0C 16.--28. 1. " VERT_ST ,Vertical start line"
|
|
hexmask.long.word 0x0C 0.--12. 1. " HORZ_ST ,Horizontal start pixel"
|
|
line.long 0x10 "RSZ_IN_SIZE,Input Size Register"
|
|
hexmask.long.word 0x10 16.--28. 1. " VERT ,Input height"
|
|
hexmask.long.word 0x10 0.--12. 1. " HORZ ,Input width"
|
|
line.long 0x14 "RSZ_SDR_INADD,Input Address Register"
|
|
line.long 0x18 "RSZ_SDR_INOFF,Input Offset Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " OFFSET ,Memory offset for the input lines"
|
|
line.long 0x1C "RSZ_SDR_OUTADD,Ouput Address Register"
|
|
line.long 0x20 "RSZ_SDR_OUTOFF,Output Offset Register"
|
|
hexmask.long.word 0x20 0.--15. 1. " OFFSET ,Memory offset for the ouput lines"
|
|
line.long 0x24 "RSZ_HFILT10,Horizontal Filter Coefficients 0 And 1 Register"
|
|
hexmask.long.word 0x24 16.--25. 1. " COEF1 ,10-bit coefficient"
|
|
hexmask.long.word 0x24 0.--9. 1. " COEF0 ,10-bit coefficient"
|
|
line.long 0x28 "RSZ_HFILT32,Horizontal Filter Coefficients 2 And 3 Register"
|
|
hexmask.long.word 0x28 16.--25. 1. " COEF3 ,10-bit coefficient"
|
|
hexmask.long.word 0x28 0.--9. 1. " COEF2 ,10-bit coefficient"
|
|
line.long 0x2C "RSZ_HFILT54,Horizontal Filter Coefficients 4 And 5 Register"
|
|
hexmask.long.word 0x2C 16.--25. 1. " COEF5 ,10-bit coefficient"
|
|
hexmask.long.word 0x2C 0.--9. 1. " COEF4 ,10-bit coefficient"
|
|
line.long 0x30 "RSZ_HFILT76,Horizontal Filter Coefficients 6 And 7 Register"
|
|
hexmask.long.word 0x30 16.--25. 1. " COEF7 ,10-bit coefficient"
|
|
hexmask.long.word 0x30 0.--9. 1. " COEF6 ,10-bit coefficient"
|
|
line.long 0x34 "RSZ_HFILT98,Horizontal Filter Coefficients 8 And 9 Register"
|
|
hexmask.long.word 0x34 16.--25. 1. " COEF9 ,10-bit coefficient"
|
|
hexmask.long.word 0x34 0.--9. 1. " COEF8 ,10-bit coefficient"
|
|
line.long 0x38 "RSZ_HFILT1110,Horizontal Filter Coefficients 10 And 11 Register"
|
|
hexmask.long.word 0x38 16.--25. 1. " COEF11 ,10-bit coefficient"
|
|
hexmask.long.word 0x38 0.--9. 1. " COEF10 ,10-bit coefficient"
|
|
line.long 0x3C "RSZ_HFILT1312,Horizontal Filter Coefficients 12 And 13 Register"
|
|
hexmask.long.word 0x3C 16.--25. 1. " COEF13 ,10-bit coefficient"
|
|
hexmask.long.word 0x3C 0.--9. 1. " COEF12 ,10-bit coefficient"
|
|
line.long 0x40 "RSZ_HFILT1514,Horizontal Filter Coefficients 14 And 15 Register"
|
|
hexmask.long.word 0x40 16.--25. 1. " COEF15 ,10-bit coefficient"
|
|
hexmask.long.word 0x40 0.--9. 1. " COEF14 ,10-bit coefficient"
|
|
line.long 0x44 "RSZ_HFILT1716,Horizontal Filter Coefficients 16 And 17 Register"
|
|
hexmask.long.word 0x44 16.--25. 1. " COEF17 ,10-bit coefficient"
|
|
hexmask.long.word 0x44 0.--9. 1. " COEF16 ,10-bit coefficient"
|
|
line.long 0x48 "RSZ_HFILT1918,Horizontal Filter Coefficients 18 And 19 Register"
|
|
hexmask.long.word 0x48 16.--25. 1. " COEF19 ,10-bit coefficient"
|
|
hexmask.long.word 0x48 0.--9. 1. " COEF18 ,10-bit coefficient"
|
|
line.long 0x4C "RSZ_HFILT2120,Horizontal Filter Coefficients 20 And 21 Register"
|
|
hexmask.long.word 0x4C 16.--25. 1. " COEF21 ,10-bit coefficient"
|
|
hexmask.long.word 0x4C 0.--9. 1. " COEF20 ,10-bit coefficient"
|
|
line.long 0x50 "RSZ_HFILT2322,Horizontal Filter Coefficients 22 And 23 Register"
|
|
hexmask.long.word 0x50 16.--25. 1. " COEF23 ,10-bit coefficient"
|
|
hexmask.long.word 0x50 0.--9. 1. " COEF22 ,10-bit coefficient"
|
|
line.long 0x54 "RSZ_HFILT2524,Horizontal Filter Coefficients 24 And 25 Register"
|
|
hexmask.long.word 0x54 16.--25. 1. " COEF25 ,10-bit coefficient"
|
|
hexmask.long.word 0x54 0.--9. 1. " COEF24 ,10-bit coefficient"
|
|
line.long 0x58 "RSZ_HFILT2726,Horizontal Filter Coefficients 26 And 27 Register"
|
|
hexmask.long.word 0x58 16.--25. 1. " COEF27 ,10-bit coefficient"
|
|
hexmask.long.word 0x58 0.--9. 1. " COEF26 ,10-bit coefficient"
|
|
line.long 0x5C "RSZ_HFILT2928,Horizontal Filter Coefficients 28 And 29 Register"
|
|
hexmask.long.word 0x5C 16.--25. 1. " COEF29 ,10-bit coefficient"
|
|
hexmask.long.word 0x5C 0.--9. 1. " COEF28 ,10-bit coefficient"
|
|
line.long 0x60 "RSZ_HFILT3130,Horizontal Filter Coefficients 30 And 31 Register"
|
|
hexmask.long.word 0x60 16.--25. 1. " COEF31 ,10-bit coefficient"
|
|
hexmask.long.word 0x60 0.--9. 1. " COEF30 ,10-bit coefficient"
|
|
line.long 0x64 "RSZ_VFILT10,Vertical Filter Coefficients 0 And 1 Register"
|
|
hexmask.long.word 0x64 16.--25. 1. " COEF1 ,10-bit coefficient"
|
|
hexmask.long.word 0x64 0.--9. 1. " COEF0 ,10-bit coefficient"
|
|
line.long 0x68 "RSZ_VFILT32,Vertical Filter Coefficients 2 And 3 Register"
|
|
hexmask.long.word 0x68 16.--25. 1. " COEF3 ,10-bit coefficient"
|
|
hexmask.long.word 0x68 0.--9. 1. " COEF2 ,10-bit coefficient"
|
|
line.long 0x6C "RSZ_VFILT54,Vertical Filter Coefficients 4 And 5 Register"
|
|
hexmask.long.word 0x6C 16.--25. 1. " COEF5 ,10-bit coefficient"
|
|
hexmask.long.word 0x6C 0.--9. 1. " COEF4 ,10-bit coefficient"
|
|
line.long 0x70 "RSZ_VFILT76,Vertical Filter Coefficients 6 And 7 Register"
|
|
hexmask.long.word 0x70 16.--25. 1. " COEF7 ,10-bit coefficient"
|
|
hexmask.long.word 0x70 0.--9. 1. " COEF6 ,10-bit coefficient"
|
|
line.long 0x74 "RSZ_VFILT98,Vertical Filter Coefficients 8 And 9 Register"
|
|
hexmask.long.word 0x74 16.--25. 1. " COEF9 ,10-bit coefficient"
|
|
hexmask.long.word 0x74 0.--9. 1. " COEF8 ,10-bit coefficient"
|
|
line.long 0x78 "RSZ_VFILT1110,Vertical Filter Coefficients 10 And 11 Register"
|
|
hexmask.long.word 0x78 16.--25. 1. " COEF11 ,10-bit coefficient"
|
|
hexmask.long.word 0x78 0.--9. 1. " COEF10 ,10-bit coefficient"
|
|
line.long 0x7C "RSZ_VFILT1312,Vertical Filter Coefficients 12 And 13 Register"
|
|
hexmask.long.word 0x7C 16.--25. 1. " COEF13 ,10-bit coefficient"
|
|
hexmask.long.word 0x7C 0.--9. 1. " COEF12 ,10-bit coefficient"
|
|
line.long 0x80 "RSZ_VFILT1514,Vertical Filter Coefficients 14 And 15 Register"
|
|
hexmask.long.word 0x80 16.--25. 1. " COEF15 ,10-bit coefficient"
|
|
hexmask.long.word 0x80 0.--9. 1. " COEF14 ,10-bit coefficient"
|
|
line.long 0x84 "RSZ_VFILT1716,Vertical Filter Coefficients 16 And 17 Register"
|
|
hexmask.long.word 0x84 16.--25. 1. " COEF17 ,10-bit coefficient"
|
|
hexmask.long.word 0x84 0.--9. 1. " COEF16 ,10-bit coefficient"
|
|
line.long 0x88 "RSZ_VFILT1918,Vertical Filter Coefficients 18 And 19 Register"
|
|
hexmask.long.word 0x88 16.--25. 1. " COEF19 ,10-bit coefficient"
|
|
hexmask.long.word 0x88 0.--9. 1. " COEF18 ,10-bit coefficient"
|
|
line.long 0x8C "RSZ_VFILT2120,Vertical Filter Coefficients 20 And 21 Register"
|
|
hexmask.long.word 0x8C 16.--25. 1. " COEF21 ,10-bit coefficient"
|
|
hexmask.long.word 0x8C 0.--9. 1. " COEF20 ,10-bit coefficient"
|
|
line.long 0x90 "RSZ_VFILT2322,Vertical Filter Coefficients 22 And 23 Register"
|
|
hexmask.long.word 0x90 16.--25. 1. " COEF23 ,10-bit coefficient"
|
|
hexmask.long.word 0x90 0.--9. 1. " COEF22 ,10-bit coefficient"
|
|
line.long 0x94 "RSZ_VFILT2524,Vertical Filter Coefficients 24 And 25 Register"
|
|
hexmask.long.word 0x94 16.--25. 1. " COEF25 ,10-bit coefficient"
|
|
hexmask.long.word 0x94 0.--9. 1. " COEF24 ,10-bit coefficient"
|
|
line.long 0x98 "RSZ_VFILT2726,Vertical Filter Coefficients 26 And 27 Register"
|
|
hexmask.long.word 0x98 16.--25. 1. " COEF27 ,10-bit coefficient"
|
|
hexmask.long.word 0x98 0.--9. 1. " COEF26 ,10-bit coefficient"
|
|
line.long 0x9C "RSZ_VFILT2928,Vertical Filter Coefficients 28 And 29 Register"
|
|
hexmask.long.word 0x9C 16.--25. 1. " COEF29 ,10-bit coefficient"
|
|
hexmask.long.word 0x9C 0.--9. 1. " COEF28 ,10-bit coefficient"
|
|
line.long 0xA0 "RSZ_VFILT3130,Vertical Filter Coefficients 30 And 31 Register"
|
|
hexmask.long.word 0xA0 16.--25. 1. " COEF31 ,10-bit coefficient"
|
|
hexmask.long.word 0xA0 0.--9. 1. " COEF30 ,10-bit coefficient"
|
|
line.long 0xA4 "RSZ_YENH,Luminance Enhancer Register"
|
|
bitfld.long 0xA4 16.--17. " ALGO ,Algorithm select" "Disabled,[-1 2 -1]/2 high-pass filter,[-1 -2 6 -2 -1]/4 high-pass filter,?..."
|
|
textline " "
|
|
hexmask.long 0xA4 12.--15. 1. " GAIN ,Maximum gain"
|
|
textline " "
|
|
hexmask.long 0xA4 8.--11. 1. " SLOP ,Slope"
|
|
textline " "
|
|
hexmask.long 0xA4 0.--7. 1. " CORE ,Coring offset"
|
|
width 0xb
|
|
tree.end
|
|
tree "ISP_SBL"
|
|
base ad:0x480BD200
|
|
width 20.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "SBL_PID,Peripherial ID Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " TID ,Peripheral identification: SBL"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CID ,Class identification: CAMERA ISP"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " PREV ,Peripheral revision number"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "SBL_PCR,Peripheral Control Register"
|
|
eventfld.long 0x00 24. " CCDCPRV_2_RSZ_OVF ,CCDC/PRV to RESIZER input overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 23. " CCDC_WBL_OVF ,CCDC Write buffer memory overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 22. " PRV_WBL_OVF ,PREVIEW Write buffer memory overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 21. " RSZ1_WBL_OVF ,RESIZER line 1 Write buffer memory overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 20. " RSZ2_WBL_OVF ,RESIZER line 2 Write buffer memory overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 19. " RSZ3_WBL_OVF ,RESIZER line 3 Write buffer memory overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 18. " RSZ4_WBL_OVF ,RESIZER line 4 Write buffer memory overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 17. " H3A_AF_WBL_OVF ,H3A AF Write buffer memory overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 16. " H3A_AEAWB_WBL_OVF ,H3A AE AWB Write buffer memory overflow" "No overflow,Overflow"
|
|
rgroup.long 0x08++0xEF
|
|
line.long 0x0 "SBL_GLB_REG_0,Global Register 0"
|
|
bitfld.long 0x0 7.--8. " SRC_DST_ID ,Individual module register command number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0 2.--6. " SRC_DST_M ,Source or destination module" "CCDC module out,CCDC module fault pixel correction in,PREVIEW module in,PREVIEW module out,PREVIEW module dark frame subtract in,RESIZER module in,RESIZER module out line 1,RESIZER module out line 2,RESIZER module out line 3,RESIZER module out line 4,HISTOGRAM module in,H3A module out auto focus,H3A module out auto exposure/white balance,CSIa module out,CSIb module out,?..."
|
|
textline " "
|
|
bitfld.long 0x0 1. " DIRECTION ,Direction" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x0 0. " VALID ,Valid bit" "Not valid,Valid"
|
|
line.long 0x4 "SBL_GLB_REG_1,Global Register 1"
|
|
bitfld.long 0x4 7.--8. " SRC_DST_ID ,Individual module register command number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x4 2.--6. " SRC_DST_M ,Source or destination module" "CCDC module out,CCDC module fault pixel correction in,PREVIEW module in,PREVIEW module out,PREVIEW module dark frame subtract in,RESIZER module in,RESIZER module out line 1,RESIZER module out line 2,RESIZER module out line 3,RESIZER module out line 4,HISTOGRAM module in,H3A module out auto focus,H3A module out auto exposure/white balance,CSIa module out,CSIb module out,?..."
|
|
textline " "
|
|
bitfld.long 0x4 1. " DIRECTION ,Direction" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x4 0. " VALID ,Valid bit" "Not valid,Valid"
|
|
line.long 0x8 "SBL_GLB_REG_2,Global Register 2"
|
|
bitfld.long 0x8 7.--8. " SRC_DST_ID ,Individual module register command number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x8 2.--6. " SRC_DST_M ,Source or destination module" "CCDC module out,CCDC module fault pixel correction in,PREVIEW module in,PREVIEW module out,PREVIEW module dark frame subtract in,RESIZER module in,RESIZER module out line 1,RESIZER module out line 2,RESIZER module out line 3,RESIZER module out line 4,HISTOGRAM module in,H3A module out auto focus,H3A module out auto exposure/white balance,CSIa module out,CSIb module out,?..."
|
|
textline " "
|
|
bitfld.long 0x8 1. " DIRECTION ,Direction" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x8 0. " VALID ,Valid bit" "Not valid,Valid"
|
|
line.long 0xC "SBL_GLB_REG_3,Global Register 3"
|
|
bitfld.long 0xC 7.--8. " SRC_DST_ID ,Individual module register command number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0xC 2.--6. " SRC_DST_M ,Source or destination module" "CCDC module out,CCDC module fault pixel correction in,PREVIEW module in,PREVIEW module out,PREVIEW module dark frame subtract in,RESIZER module in,RESIZER module out line 1,RESIZER module out line 2,RESIZER module out line 3,RESIZER module out line 4,HISTOGRAM module in,H3A module out auto focus,H3A module out auto exposure/white balance,CSIa module out,CSIb module out,?..."
|
|
textline " "
|
|
bitfld.long 0xC 1. " DIRECTION ,Direction" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0xC 0. " VALID ,Valid bit" "Not valid,Valid"
|
|
line.long 0x10 "SBL_GLB_REG_4,Global Register 4"
|
|
bitfld.long 0x10 7.--8. " SRC_DST_ID ,Individual module register command number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x10 2.--6. " SRC_DST_M ,Source or destination module" "CCDC module out,CCDC module fault pixel correction in,PREVIEW module in,PREVIEW module out,PREVIEW module dark frame subtract in,RESIZER module in,RESIZER module out line 1,RESIZER module out line 2,RESIZER module out line 3,RESIZER module out line 4,HISTOGRAM module in,H3A module out auto focus,H3A module out auto exposure/white balance,CSIa module out,CSIb module out,?..."
|
|
textline " "
|
|
bitfld.long 0x10 1. " DIRECTION ,Direction" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x10 0. " VALID ,Valid bit" "Not valid,Valid"
|
|
line.long 0x14 "SBL_GLB_REG_5,Global Register 5"
|
|
bitfld.long 0x14 7.--8. " SRC_DST_ID ,Individual module register command number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x14 2.--6. " SRC_DST_M ,Source or destination module" "CCDC module out,CCDC module fault pixel correction in,PREVIEW module in,PREVIEW module out,PREVIEW module dark frame subtract in,RESIZER module in,RESIZER module out line 1,RESIZER module out line 2,RESIZER module out line 3,RESIZER module out line 4,HISTOGRAM module in,H3A module out auto focus,H3A module out auto exposure/white balance,CSIa module out,CSIb module out,?..."
|
|
textline " "
|
|
bitfld.long 0x14 1. " DIRECTION ,Direction" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x14 0. " VALID ,Valid bit" "Not valid,Valid"
|
|
line.long 0x18 "SBL_GLB_REG_6,Global Register 6"
|
|
bitfld.long 0x18 7.--8. " SRC_DST_ID ,Individual module register command number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x18 2.--6. " SRC_DST_M ,Source or destination module" "CCDC module out,CCDC module fault pixel correction in,PREVIEW module in,PREVIEW module out,PREVIEW module dark frame subtract in,RESIZER module in,RESIZER module out line 1,RESIZER module out line 2,RESIZER module out line 3,RESIZER module out line 4,HISTOGRAM module in,H3A module out auto focus,H3A module out auto exposure/white balance,CSIa module out,CSIb module out,?..."
|
|
textline " "
|
|
bitfld.long 0x18 1. " DIRECTION ,Direction" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x18 0. " VALID ,Valid bit" "Not valid,Valid"
|
|
line.long 0x1C "SBL_GLB_REG_7,Global Register 7"
|
|
bitfld.long 0x1C 7.--8. " SRC_DST_ID ,Individual module register command number" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x1C 2.--6. " SRC_DST_M ,Source or destination module" "CCDC module out,CCDC module fault pixel correction in,PREVIEW module in,PREVIEW module out,PREVIEW module dark frame subtract in,RESIZER module in,RESIZER module out line 1,RESIZER module out line 2,RESIZER module out line 3,RESIZER module out line 4,HISTOGRAM module in,H3A module out auto focus,H3A module out auto exposure/white balance,CSIa module out,CSIb module out,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 1. " DIRECTION ,Direction" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " VALID ,Valid bit" "Not valid,Valid"
|
|
line.long 0x40 "SBL_CCDC_WR_0,CCDC Write Request 1 Register"
|
|
hexmask.long.byte 0x40 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0x40 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x40 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0x40 0.--19. 1. " ADDR ,Upper 20 bits of the write address"
|
|
line.long 0x44 "SBL_CCDC_WR_1,CCDC Write Request 2 Register"
|
|
hexmask.long.byte 0x44 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0x44 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x44 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0x44 0.--19. 1. " ADDR ,Upper 20 bits of the write address"
|
|
line.long 0x48 "SBL_CCDC_WR_2,CCDC Write Request 3 Register"
|
|
hexmask.long.byte 0x48 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0x48 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x48 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0x48 0.--19. 1. " ADDR ,Upper 20 bits of the write address"
|
|
line.long 0x4C "SBL_CCDC_WR_3,CCDC Write Request 4 Register"
|
|
hexmask.long.byte 0x4C 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0x4C 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x4C 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0x4C 0.--19. 1. " ADDR ,Upper 20 bits of the write address"
|
|
line.long 0x50 "SBL_CCDC_FP_RD_0,CCDC Fault Pixel Correction Read Request 1 Register"
|
|
bitfld.long 0x50 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x50 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x50 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x50 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x50 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x54 "SBL_CCDC_FP_RD_1,CCDC Fault Pixel Correction Read Request 2 Register"
|
|
bitfld.long 0x54 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x54 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x54 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x54 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x54 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x58 "SBL_PRV_RD_0,Preview Read Request 1 Register"
|
|
bitfld.long 0x58 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x58 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x58 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x58 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x58 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x5C "SBL_PRV_RD_1,Preview Read Request 2 Register"
|
|
bitfld.long 0x5C 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x5C 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x5C 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x5C 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x5C 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x60 "SBL_PRV_RD_2,Preview Read Request 3 Register"
|
|
bitfld.long 0x60 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x60 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x60 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x60 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x60 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x64 "SBL_PRV_RD_3,Preview Read Request 4 Register"
|
|
bitfld.long 0x64 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x64 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x64 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x64 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x64 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x68 "SBL_PRV_WR_0,Preview Write Request 1 Register"
|
|
hexmask.long.byte 0x68 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0x68 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x68 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0x68 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x6C "SBL_PRV_WR_1,Preview Write Request 2 Register"
|
|
hexmask.long.byte 0x6C 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0x6C 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x6C 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0x6C 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x70 "SBL_PRV_WR_2,Preview Write Request 3 Register"
|
|
hexmask.long.byte 0x70 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0x70 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x70 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0x70 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x74 "SBL_PRV_WR_3,Preview Write Request 4 Register"
|
|
hexmask.long.byte 0x74 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0x74 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x74 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0x74 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x78 "SBL_PRV_DK_RD_0,Preview Dark Frame Read Request 1 Register"
|
|
bitfld.long 0x78 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x78 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x78 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x78 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x78 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x7C "SBL_PRV_DK_RD_1,Preview Dark Frame Read Request 2 Register"
|
|
bitfld.long 0x7C 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x7C 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x7C 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x7C 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x7C 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x80 "SBL_PRV_DK_RD_2,Preview Dark Frame Read Request 3 Register"
|
|
bitfld.long 0x80 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x80 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x80 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x80 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x80 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x84 "SBL_PRV_DK_RD_3,Preview Dark Frame Read Request 4 Register"
|
|
bitfld.long 0x84 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x84 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x84 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x84 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x84 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x88 "SBL_RSZ_RD_0,Resizer Read Request 1 Register"
|
|
bitfld.long 0x88 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x88 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x88 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x88 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x88 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x8C "SBL_RSZ_RD_1,Resizer Read Request 2 Register"
|
|
bitfld.long 0x8C 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x8C 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x8C 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x8C 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x8C 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x90 "SBL_RSZ_RD_2,Resizer Read Request 3 Register"
|
|
bitfld.long 0x90 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x90 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x90 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x90 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x90 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x94 "SBL_RSZ_RD_3,Resizer Read Request 4 Register"
|
|
bitfld.long 0x94 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0x94 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x94 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0x94 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0x94 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x98 "SBL_RSZ1_WR_0,Resizer Line 1 Write Request 1 Register"
|
|
hexmask.long.byte 0x98 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0x98 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x98 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0x98 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0x9C "SBL_RSZ1_WR_1,Resizer Line 1 Write Request 2 Register"
|
|
hexmask.long.byte 0x9C 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0x9C 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x9C 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0x9C 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xA0 "SBL_RSZ1_WR_2,Resizer Line 1 Write Request 3 Register"
|
|
hexmask.long.byte 0xA0 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xA0 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xA0 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xA0 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xA4 "SBL_RSZ1_WR_3,Resizer Line 1 Write Request 4 Register"
|
|
hexmask.long.byte 0xA4 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xA4 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xA4 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xA4 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xA8 "SBL_RSZ2_WR_0,Resizer Line 2 Write Request 1 Register"
|
|
hexmask.long.byte 0xA8 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xA8 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xA8 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xA8 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xAC "SBL_RSZ2_WR_1,Resizer Line 2 Write Request 2 Register"
|
|
hexmask.long.byte 0xAC 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xAC 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xAC 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xAC 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xB0 "SBL_RSZ2_WR_2,Resizer Line 2 Write Request 3 Register"
|
|
hexmask.long.byte 0xB0 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xB0 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xB0 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xB0 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xB4 "SBL_RSZ2_WR_3,Resizer Line 2 Write Request 4 Register"
|
|
hexmask.long.byte 0xB4 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xB4 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xB4 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xB4 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xB8 "SBL_RSZ3_WR_0,Resizer Line 3 Write Request 1 Register"
|
|
hexmask.long.byte 0xB8 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xB8 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xB8 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xB8 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xBC "SBL_RSZ3_WR_1,Resizer Line 3 Write Request 2 Register"
|
|
hexmask.long.byte 0xBC 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xBC 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xBC 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xBC 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xC0 "SBL_RSZ3_WR_2,Resizer Line 3 Write Request 3 Register"
|
|
hexmask.long.byte 0xC0 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xC0 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xC0 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xC0 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xC4 "SBL_RSZ3_WR_3,Resizer Line 3 Write Request 4 Register"
|
|
hexmask.long.byte 0xC4 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xC4 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xC4 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xC4 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xC8 "SBL_RSZ4_WR_0,Resizer Line 4 Write Request 1 Register"
|
|
hexmask.long.byte 0xC8 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xC8 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xC8 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xC8 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xCC "SBL_RSZ4_WR_1,Resizer Line 4 Write Request 2 Register"
|
|
hexmask.long.byte 0xCC 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xCC 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xCC 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xCC 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xD0 "SBL_RSZ4_WR_2,Resizer Line 4 Write Request 3 Register"
|
|
hexmask.long.byte 0xD0 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xD0 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xD0 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xD0 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xD4 "SBL_RSZ4_WR_3,Resizer Line 4 Write Request 4 Register"
|
|
hexmask.long.byte 0xD4 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xD4 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xD4 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xD4 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xD8 "SBL_HIST_RD_0,Histogram Read Request 1 Register"
|
|
bitfld.long 0xD8 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0xD8 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xD8 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0xD8 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0xD8 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xDC "SBL_HIST_RD_1,Histogram Read Request 2 Register"
|
|
bitfld.long 0xDC 30. " VALID ,Valid bit" "No,Yes"
|
|
bitfld.long 0xDC 29. " DATA_WAIT ,Waiting for data" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xDC 28. " DATA_AVL ,Data available" "No,Yes"
|
|
hexmask.long.byte 0xDC 20.--27. 1. " BYTE_CNT ,Byte count requested"
|
|
textline " "
|
|
hexmask.long.tbyte 0xDC 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xE0 "SBL_H3A_AF_WR_0,H3A AF Write Request 1 Register"
|
|
hexmask.long.byte 0xE0 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xE0 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xE0 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xE0 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xE4 "SBL_H3A_AF_WR_1,H3A AF Write Request 2 Register"
|
|
hexmask.long.byte 0xE4 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xE4 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xE4 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xE4 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xE8 "SBL_H3A_AEAWB_WR_0,H3A AE AWB Write Request 1 Register"
|
|
hexmask.long.byte 0xE8 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xE8 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xE8 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xE8 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
line.long 0xEC "SBL_H3A_AEAWB_WR_1,H3A AE AWB Write Request 2 Register"
|
|
hexmask.long.byte 0xEC 22.--29. 1. " BYTE_CNT ,Current byte count"
|
|
bitfld.long 0xEC 21. " DATA_READY ,Data ready" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0xEC 20. " DATA_SENT ,Data sent to the destination" "No,Yes"
|
|
hexmask.long.tbyte 0xEC 0.--19. 1. " ADDR ,Upper 20 bits of the read address"
|
|
group.long 0xF8++0x3
|
|
line.long 0x00 "SBL_SDR_REQ_EXP,Memory Non Real Time Read Request Expand"
|
|
hexmask.long.word 0x00 20.--29. 1. " PRV_EXP ,PREVIEW module READ request expand"
|
|
hexmask.long.word 0x00 10.--19. 1. " RSZ_EXP ,RESIZER module READ request expand"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " HIST_EXP ,HISTOGRAM module READ request expand"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "Display Subsystem"
|
|
tree "DISS"
|
|
base ad:0x48050000
|
|
width 20.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "DSS_SYSCONFIG,Configuration Register"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Power management capability" "Disabled,Enabled"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x00 "DSS_SYSSTATUS,Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
line.long 0x04 "DSS_IRQSTATUS,Source Of The Interrupt And The Status Of The Interrupt Line"
|
|
bitfld.long 0x04 1. " DSI_IRQ ,DSI interrupt status" "Not active,Active"
|
|
bitfld.long 0x04 0. " DISPC_IRQ ,DISPC interrupt status" "Not active,Active"
|
|
group.long 0x40++0xb
|
|
line.long 0x00 "DSS_CONTROL,Display Subsystem Control Register"
|
|
bitfld.long 0x00 6. " VENC_OUT_SEL ,Venc output select" "Composite,Luminance"
|
|
bitfld.long 0x00 5. " DAC_POWERDN_BGZ ,DAC power-down band gap" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DAC_DEMEN ,DAC dynamic element matching enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " VENC_CLOCK_4X_ENABLE ,VENC clock 4x enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VENC_CLOCK_MODE ,VENC clock mode" "Normal,Square pixel"
|
|
bitfld.long 0x00 1. " DSI_CLK_SWITCH ,DSS1_ALWON_FCLK/DSI2_PLL_FCLK clock source for DSI clk" "DSS1_ALWON_FCLK,DSI2_PLL_FCLK"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DISPC_CLK_SWITCH ,DSS1_PLL_FCLK/DSI1_ALWON_FCLK clock siwtch" "DSI1_ALWON_FCLK,DSI1_PLL_FCLK"
|
|
line.long 0x04 "DSS_SDI_CONTROL,Display Subsystem Control Register"
|
|
bitfld.long 0x04 15.--19. " SDI_PDIV ,Ratio of PLL output to pixel clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x04 14. " SDI_PHYLPMODE ,FlatLink3G output buffer low power option" "Standard,Low-power"
|
|
textline " "
|
|
bitfld.long 0x04 12.--13. " SDI_RBITS ,FlatLink3G reserved bits F1 and F0" "0,1,2,3"
|
|
bitfld.long 0x04 11. " SDI_AUTOSTDBY ,High-speed serial buffers enable" "PLL locked,SDI active"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " SDI_PRSEL ,Selection of the number of data pairs" "DATA0,DATA0 and DATA1,DATA0 DATA1 and DATA2,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SDI_BWSEL ,Color depth" "Reserved,Reserved,24 bits,?..."
|
|
line.long 0x08 "DSS_PLL_CONTROL,Display Subsystem Control Register"
|
|
bitfld.long 0x08 28. " SDI_PLL_GOBIT ,PLL locking sequence request" "Not requested,Requested"
|
|
bitfld.long 0x08 26.--27. " SDI_PLL_LOCKSEL ,Lock criteria for PLL" "Phase,Fine phase,Frequency,?..."
|
|
textline " "
|
|
bitfld.long 0x08 22.--25. " SDI_PLL_FREQSEL ,PLL internal refererence frequency range selection" "Reserved,Reserved,Reserved,0.75MHz to 1.0MHz,1.0MHz to 1.25MHz,1.25MHz to 1.5MHz,1.5MHz to 1.75MHz,1.75MHz to 2.1MHz,Reserved,Reserved,Reserved,7.5MHz to 10MHz,10MHz to 12.5MHz,12.5MHz to 15MHz,15MHz to 17.5MHz,17.5MHz to 21MHz"
|
|
bitfld.long 0x08 21. " SDI_PLL_PLLPMODE ,Select the power / performance of the PLL" "Performance,Power"
|
|
textline " "
|
|
bitfld.long 0x08 20. " SDI_PLL_LOWCURRSTBY ,PLL low current standby" "Not selected,Selected"
|
|
bitfld.long 0x08 19. " SDI_PLL_HIGHFREQ ,Division of pixel clock by 2 before input of PLL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 18. " SDI_PLL_SYSRESET ,SDI PLL reset" "Reset,Operational"
|
|
bitfld.long 0x08 17. " SDI_PLL_STOPMODE ,SDI PLL STOPMODE" "Not selected,Selected"
|
|
textline " "
|
|
hexmask.long.byte 0x08 11.--16. 1. " SDI_PLL_REGN ,SDI PLL REGN register"
|
|
hexmask.long.word 0x08 1.--10. 1. " SDI_PLL_REGM ,SDI PLL REGM register"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SDI_PLL_IDLE ,IDLE select" "Not selected,Selected"
|
|
rgroup.long 0x5c++0x3
|
|
line.long 0x00 "DSS_SDI_STATUS,Display Subsystem Status Register"
|
|
bitfld.long 0x00 8. " DSI_PLL_CLK2_STATUS ,DSI2_PLL_FCLK clock selection status" "Not selected,Selected"
|
|
bitfld.long 0x00 7. " DSS_DSI_CLK1_STATUS ,DSI1_ALWON_FCLK clock selection status" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 6. " SDI_PLL_BUSYFLAG ,PLL locking sequence status" "Completed,Not completed"
|
|
bitfld.long 0x00 5. " SDI_PLL_LOCK ,SDI PLL lock status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SDI_PLL_RECAL ,SDI DPLL re-calibration status" "Not required,Required"
|
|
bitfld.long 0x00 3. " SDI_ERROR ,SDI error status" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SDI_RESET_DONE ,SDI reset done status" "Not done,Done"
|
|
bitfld.long 0x00 1. " DSI_PLL_CLK1_STATUS ,DSI1_PLL_FCLK clock selection status" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DSS_CLK1_STATUS ,DSI1_ALWON_FCLK clock selection status" "Not selected,Selected"
|
|
width 11.
|
|
tree.end
|
|
tree "DISPC"
|
|
base ad:0x48050400
|
|
width 15.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "DISPC_SYSCONFIG,Various Parameters Of The Interconnect Interface"
|
|
bitfld.long 0x00 12.--13. " MIDLEMODE ,Master interface power management" "Force standby,No standby,Smart Standby,?..."
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wake up mode period (interface clk/functional clk)" "Switched-off,Maintained/Switched-off,Switched-off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force idle,No idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENWAKEUP ,Wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal auto-clock gating strategy" "Free running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "DISPC_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "On-going,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "DISPC_IRQSTATUS,Status Of Module Internal Events That Generate An Interrupt"
|
|
eventfld.long 0x00 16. " WAKEUP ,Wakeup" "Not occurred,Occurred"
|
|
eventfld.long 0x00 15. " SYNCLOSTDIGITAL ,SyncLostDigital" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 14. " SYNCLOST ,SyncLost" "Not occurred,Occurred"
|
|
eventfld.long 0x00 13. " VID2ENDWINDOW ,Vid2EndWindow" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 12. " VID2FIFOUNDERFLOW ,Vid2FIFOUnderflow" "Not occurred,Occurred"
|
|
eventfld.long 0x00 11. " VID1ENDWINDOW ,Vid1EndWindow" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 10. " VID1FIFOUNDERFLOW ,Vid1FIFOUnderflow" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " OCPERROR ,OCPError" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " PALETTEGAMMALOADING ,PaletteGammaLoading" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " GFXENDWINDOW ,GfxEndWindow" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 6. " GFXFIFOUNDERFLOW ,GfxFIFOUnderflow" "Not occurred,Occurred"
|
|
eventfld.long 0x00 5. " PROGRAMMEDLINENUMBER ,ProgrammedLineNumber" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 4. " ACBIASCOUNTSTATUS ,ACBiasCountStatus" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " EVSYNC_ODD ,EVSYNC_ODD" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " EVSYNC_EVEN ,EVSYNC_EVEN" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " VSYNC ,VSYNC" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " FRAMEDONE ,FrameDone" "Not occurred,Occurred"
|
|
line.long 0x04 "DISPC_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 16. " WAKEUP ,Wakeup" "Masked,Not masked"
|
|
bitfld.long 0x04 15. " SYNCLOSTDIGITAL ,SyncLostDigital" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 14. " SYNCLOST ,SyncLost" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " VID2ENDWINDOW ,Vid2EndWindow" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 12. " VID2FIFOUNDERFLOW ,Vid2FIFOUnderflow" "Masked,Not masked"
|
|
bitfld.long 0x04 11. " VID1ENDWINDOW ,Vid1EndWindow" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 10. " VID1FIFOUNDERFLOW ,Vid1FIFOUnderflow" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " OCPERROR ,OCPError" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PALETTEGAMMALOADING ,PaletteGammaLoading" "Masked,Not masked"
|
|
bitfld.long 0x04 7. " GFXENDWINDOW ,GfxEndWindow" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 6. " GFXFIFOUNDERFLOW ,GfxFIFOUnderflow" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " PROGRAMMEDLINENUMBER ,ProgrammedLineNumber" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 4. " ACBIASCOUNTSTATUS ,ACBiasCountStatus" "Masked,Not masked"
|
|
bitfld.long 0x04 3. " EVSYNC_ODD ,EVSYNC_ODD" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 2. " EVSYNC_EVEN ,EVSYNC_EVEN" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " VSYNC ,VSYNC" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FRAMEDONE ,FrameDone" "Masked,Not masked"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "DISPC_CONTROL,Display Controller Module Configure Register"
|
|
bitfld.long 0x00 30.--31. " SPATIALTEMPORAL_DITHERINGFRAMES ,Spatial/Temporal dithering number of frames" "Spatial only,Spatial/temporal over 2,Spatial/temporal over 4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 29. " LCDENABLEPOL ,LCD Enable Signal Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " LCDENABLESIGNAL ,LCD Enable Signal" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PCKFREEENABLE ,Pixel clock free-running enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TDMUNUSEDBITS ,State of unused bits" "Low,High,Unchanged,?..."
|
|
bitfld.long 0x00 23.--24. " TDMCYCLEFORMAT ,Cycle format (cycle/pixel)" "1c/1p,2c/1p,3c/1p,3c/2p"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. " TDMPARALLELMODE ,Output Interface width" "8-bit,9-bit,12-bit,16-bit"
|
|
bitfld.long 0x00 20. " TDMENABLE ,Enable the multiple cycle format" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " HT ,Hold Time for digital output" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16. " GPOUT1 ,General Purpose Output Signal" "Reset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GPOUT0 ,General Purpose Output Signal" "Reset,Set"
|
|
bitfld.long 0x00 14. " GPIN1 ,General Purpose Input Signal" "Reset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " GPIN0 ,General Purpose Input Signal" "Reset,Set"
|
|
bitfld.long 0x00 12. " OVERLAYOPTIMIZATION ,Overlay Optimization" "Fetched,Not fetched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RFBIMODE ,RFBI Mode for the LCD output" "Normal,RFBI"
|
|
bitfld.long 0x00 10. " SECURE ,Secure bit set/reset by secure request only" "Non-secured,Secured"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TFTDATALINES ,Number of lines of the LCD interface" "12-bit,16-bit,18-bit,24-bit"
|
|
bitfld.long 0x00 7. " STDITHERENABLE ,Spatial temporal dithering enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " GODIGITAL ,Digital GO Command" "Hardaware finished,User finished"
|
|
bitfld.long 0x00 5. " GOLCD ,LCD GO Command" "Hardaware finished,User finished"
|
|
textline " "
|
|
bitfld.long 0x00 4. " M8B ,Mono 8-bit mode" "Pixel data[3:0],Pixel data[7:0]"
|
|
bitfld.long 0x00 3. " STNTFT ,LCD display type" "Passive/Passive matrix,Active matrix"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MONOCOLOR ,Monochrome/Color" "Color,Monochrome"
|
|
bitfld.long 0x00 1. " DIGITALENABLE ,Digital enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCDENABLE ,LCD enable" "Disabled,Enabled"
|
|
if (((d.l((ad:0x48050400+0x40)))&0x8)==0x8)
|
|
;DISPC_CONTROL(3) = Active matrix
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "DISPC_CONFIG,Display Controller Module Configuration Register"
|
|
bitfld.long 0x00 19. " TVALPHABLENDERENABLE ,Selects the alpha blender overlay manager (TV)" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " LCDALPHABLENDERENABLE ,Selects the alpha blender overlay manager (LCD)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FIFOFILLING ,FIFO control (when reach Low treshold)" "Each FIFO re-filled,All FIFO re-filled"
|
|
bitfld.long 0x00 16. " FIFOHANDCHECK ,Handscheck control" "Only STALL,STALL/FIFO"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CPR ,Color phase rotation control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOMERGE ,FIFO merge control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TCKDIGSELECTION ,Transparency color key selection" "Graphics destination,Video source"
|
|
bitfld.long 0x00 12. " TCKDIGENABLE ,Transparency color key enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCKLCDSELECTION ,Transparency color key selection" "Graphics destination,Video source"
|
|
bitfld.long 0x00 10. " TCKLCDENABLE ,Transparency color key enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FUNCGATED ,Functional clocks gated enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ACBIASGATED ,ACBias Gated Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VSYNCGATED ,VSYNC Gated Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HSYNCGATED ,HSYNC Gated Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIXELCLOCKGATED ,Pixel Clock Gated Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PIXELDATAGATED ,Pixel Data Gated Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PALETTEGAMMATABLE ,Palette/Gamma Table selection" "Palette,Gamma"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " LOADMODE ,Loading Mode for the Palette/Gamma Table (PGT) and Frame data (FD)" "PGT every frame,PGT loaded,FD every frame,PGT/FD first frame than 10"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PIXELGATED ,Pixel Gated Enable" "Always toggles,Toggles when valid data"
|
|
else
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "DISPC_CONFIG,Display Controller Module Configuration Register"
|
|
bitfld.long 0x00 19. " TVALPHABLENDERENABLE ,Selects the alpha blender overlay manager (TV)" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " LCDALPHABLENDERENABLE ,Selects the alpha blender overlay manager (LCD)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FIFOFILLING ,FIFO control (when reach Low treshold)" "Each FIFO re-filled,All FIFO re-filled"
|
|
bitfld.long 0x00 16. " FIFOHANDCHECK ,Handscheck control" "Only STALL,STALL/FIFO"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CPR ,Color phase rotation control" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " FIFOMERGE ,FIFO merge control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TCKDIGSELECTION ,Transparency color key selection" "Graphics destination,Video source"
|
|
bitfld.long 0x00 12. " TCKDIGENABLE ,Transparency color key enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TCKLCDSELECTION ,Transparency color key selection" "Graphics destination,Video source"
|
|
bitfld.long 0x00 10. " TCKLCDENABLE ,Transparency color key enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FUNCGATED ,Functional clocks gated enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ACBIASGATED ,ACBias Gated Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VSYNCGATED ,VSYNC Gated Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " HSYNCGATED ,HSYNC Gated Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PIXELCLOCKGATED ,Pixel Clock Gated Enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PIXELDATAGATED ,Pixel Data Gated Enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " PALETTEGAMMATABLE ,Palette/Gamma Table selection" "Palette,Gamma"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " LOADMODE ,Loading Mode for the Palette/Gamma Table (PGT) and Frame data (FD)" "PGT every frame,PGT loaded,FD every frame,PGT/FD first frame than 10"
|
|
endif
|
|
group.long 0x48++0x13
|
|
line.long 0x00 "DISPC_CAPABLE,Display Controller Capability Configuration Register"
|
|
bitfld.long 0x00 9. " GFXGAMMATABLECAPABLE ,GfxGammaTableCapable" "Not capable,Capable"
|
|
bitfld.long 0x00 8. " GFXLAYERCAPABLE ,GfxLayerCapable" "Not capable,Capable"
|
|
textline " "
|
|
bitfld.long 0x00 7. " GFXTRANSDSTCAPABLE ,GfxTransDstCapable" "Not capable,Capable"
|
|
bitfld.long 0x00 6. " STNDITHERINGCAPABLE ,STNditheringCapable" "Not capable,Capable"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TFTDITHERINGCAPABLE ,TFTditheringCapable" "Not capable,Capable"
|
|
bitfld.long 0x00 4. " VIDTRANSSRCCAPABLE ,VidTransSrcCapable" "Not capable,Capable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " VIDLAYERCAPABLE ,VidLayerCapable" "Not capable,Capable"
|
|
bitfld.long 0x00 2. " VIDVERTFIRCAPABLE ,VidVertFIRCapable" "Not capable,Capable"
|
|
textline " "
|
|
bitfld.long 0x00 1. " VIDHORFIRCAPABLE ,VidHorFIRCapable" "Not capable,Capable"
|
|
bitfld.long 0x00 0. " VIDCAPABLE ,VidCapable" "Not available,Available"
|
|
width 24.
|
|
line.long 0x4 "DISPC_DEFAULT_COLOR0,Default Solid Background Color For The LCD"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display"
|
|
line.long 0x8 "DISPC_DEFAULT_COLOR1,Default Solid Background Color For The LCD"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. " DEFAULTCOLOR ,24-bit RGB color value to specify the default solid color to display"
|
|
line.long 0xC "DISPC_TRANS_COLOR0,Transparency Color Value For The Video/Graphics Overlays"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. " TRANSCOLORKEY ,Transparency Color Key Value in RGB format"
|
|
line.long 0x10 "DISPC_TRANS_COLOR1,Transparency Color Value For The Video/Graphics Overlays"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " TRANSCOLORKEY ,Transparency Color Key Value in RGB format"
|
|
rgroup.long 0x5C++0x3
|
|
line.long 0x00 "DISPC_LINE_STATUS,Current LCD Panel Display Line Number"
|
|
hexmask.long.word 0x00 0.--10. 1. " LINENUMBER ,Current LCD panel line number"
|
|
group.long 0x60++0xB
|
|
line.long 0x00 "DISPC_LINE_NUMBER,LCD panel line number For Interrupt And DMA Request"
|
|
hexmask.long.word 0x00 0.--10. 1. " LINENUMBER ,LCD panel line number programming"
|
|
line.long 0x04 "DISPC_TIMING_H,Timing Logic For The HSYNC Signal"
|
|
hexmask.long.word 0x04 20.--31. 1. " HBP ,Horizontal Back Porch"
|
|
hexmask.long.word 0x04 8.--19. 1. " HFP ,Horizontal front porch"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " HSW ,Horizontal synchronization pulse width"
|
|
line.long 0x08 "DISPC_TIMING_V,Timing Logic For The VSYNC Signal"
|
|
hexmask.long.word 0x08 20.--31. 1. " VBP ,Vertical Back Porch"
|
|
hexmask.long.word 0x08 8.--19. 1. " VFP ,Vertical front porch"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " VSW ,Vertical synchronization pulse width"
|
|
if (((d.l((ad:0x48050400+0x6C)))&0x20000)==0x20000)
|
|
;DISPC_POL_FREQ(17) = Off
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "DISPC_POL_FREQ,Signal Configuration"
|
|
bitfld.long 0x00 17. " ONOFF ,HSYNC/VSYNC Pixel clock Control On/Off" "On,Off"
|
|
bitfld.long 0x00 16. " RF ,Program HSYNC/VSYNC Rise or Fall" "Falling-edge,Rising-edge"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IEO ,Invert output enable" "High,Low"
|
|
bitfld.long 0x00 14. " IPC ,Invert pixel clock" "Rising-edge,Falling-edge"
|
|
textline " "
|
|
bitfld.long 0x00 13. " IHS ,Invert HSYNC (Active/Inactive)" "High/Low,Low/High"
|
|
bitfld.long 0x00 12. " IVS ,Invert VSYNC (Active/Inactive)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " ACBI ,AC-bias pin transitions per interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ACB ,AC-bias pin frequency"
|
|
else
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "DISPC_POL_FREQ,Signal Configuration"
|
|
bitfld.long 0x00 17. " ONOFF ,HSYNC/VSYNC Pixel clock Control On/Off" "On,Off"
|
|
bitfld.long 0x00 15. " IEO ,Invert output enable" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 14. " IPC ,Invert pixel clock" "Rising-edge,Falling-edge"
|
|
bitfld.long 0x00 13. " IHS ,Invert HSYNC (Active/Inactive)" "High/Low,Low/High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IVS ,Invert VSYNC (Active/Inactive)" "High/Low,Low/High"
|
|
bitfld.long 0x00 8.--11. " ACBI ,AC-bias pin transitions per interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " ACB ,AC-bias pin frequency"
|
|
endif
|
|
group.long 0x70++0x7
|
|
line.long 0x00 "DISPC_DIVISOR,Divisors Configure Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " LCD ,Display Controller Logic Clock Divisor"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PCD ,Pixel Clock Divisor"
|
|
line.long 0x04 "DISPC_GLOBAL_ALPHA,Global Alpha Value For The Graphics And Video 2 Pipelines"
|
|
hexmask.long.byte 0x04 16.--23. 1. " VID2GLOBALALPHA ,Global alpha value from 0 to 255"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " GFXGLOBALALPHA ,Global alpha value from 0 to 255"
|
|
group.long 0x78++0x7
|
|
line.long 0x00 "DISPC_SIZE_DIG,Size Of The Digital Output Field"
|
|
hexmask.long.word 0x00 16.--26. 1. " LPP ,Lines per panel"
|
|
hexmask.long.word 0x00 0.--10. 1. " PPL ,Pixels per line"
|
|
line.long 0x04 "DISPC_SIZE_LCD,Panel Size"
|
|
hexmask.long.word 0x04 16.--26. 1. " LPP ,Lines per panel"
|
|
hexmask.long.word 0x04 0.--10. 1. " PPL ,Pixels per line"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "DISPC_GFX_BA0,Base Address Of The Graphics Buffer Displayed In The Graphics Window"
|
|
line.long 0x4 "DISPC_GFX_BA1,Base Address Of The Graphics Buffer Displayed In The Graphics Window"
|
|
line.long 0x08 "DISPC_GFX_POSITION,Position Of The Graphics Window"
|
|
hexmask.long.word 0x08 16.--26. 1. " GFXPOSY ,Y position of the graphics window"
|
|
hexmask.long.word 0x08 0.--10. 1. " GFXPOSX ,X position of the graphics window"
|
|
line.long 0x0c "DISPC_GFX_SIZE,Size Of The Graphics Window"
|
|
hexmask.long.word 0x0c 16.--26. 1. " GFXSIZEY ,Number of lines of the graphics window"
|
|
hexmask.long.word 0x0c 0.--10. 1. " GFXSIZEX ,Number of pixels of the graphics window"
|
|
group.long 0xA0++0x3
|
|
line.long 0x00 "DISPC_GFX_ATTRIBUTES,Graphics Attributes"
|
|
bitfld.long 0x00 15. " GFXSELFREFRESH ,Enables the self refresh of the graphics window (data from the system memory)" "Fetch,Not fetch"
|
|
bitfld.long 0x00 14. " GFXARBITRATION ,Priority of the graphics pipeline" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " GFXROTATION ,Graphics rotation flag" "No rotation,90 degrees,180 degrees,270 degrees"
|
|
bitfld.long 0x00 11. " GFXFIFOPRELOAD ,Graphics preload value (H/W prefetches pixels up to)" "Preload value,High threshold value"
|
|
textline " "
|
|
bitfld.long 0x00 9. " GFXNIBBLEMODE ,Graphics Nibble Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " GFXCHANNELOUT ,Graphics Channel Out configuration" "LCD,24-bit"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " GFXBURSTSIZE ,Graphics DMA Burst Size" "4x32bit,8x32bit,16x32bit,?..."
|
|
bitfld.long 0x00 5. " GFXREPLICATIONENABLE ,GfxReplicationEnable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " GFXFORMAT ,Graphics format" "BITMAP 1,BITMAP 2,BITMAP 4,BITMAP 8,RGB 12,ARGB 16,RGB 16,Reserved,RGB 24/32-bit,RGB 24/24-bit,Reserved,Reserved,ARGB 32,RGBA 32,RGBx 32,?..."
|
|
bitfld.long 0x00 0. " GFXENABLE ,GfxEnable" "Disabled,Enabled"
|
|
width 29.
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "DISPC_GFX_FIFO_THRESHOLD,Graphics FIFO Configuration Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " GFXFIFOHIGHTHRESHOLD ,Graphics FIFO High Threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " GFXFIFOLOWTHRESHOLD ,Graphics FIFO Low Threshold"
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x00 "DISPC_GFX_FIFO_SIZE_STATUS,Graphics FIFO Size Configuration Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " GFXFIFOSIZE ,Graphics FIFO Size"
|
|
group.long 0xAC++0xF
|
|
line.long 0x00 "DISPC_GFX_ROW_INC,Number Of Bytes To Increment At The End Of The Row"
|
|
line.long 0x04 "DISPC_GFX_PIXEL_INC,Number Of Bytes To Increment Between Two Pixels"
|
|
hexmask.long.word 0x04 0.--15. 1. " GFXPIXELINC ,Number of bytes to increment between two pixels"
|
|
line.long 0x08 "DISPC_GFX_WINDOW_SKIP,Number Of Bytes To Skip During Video Window Display"
|
|
line.long 0x0C "DISPC_GFX_TABLE_BA,Base Address Of The Palette Buffer Or The Gamma Table Buffer"
|
|
group.long 0x1D4++0x3
|
|
line.long 0x00 "DISPC_DATA_CYCLE1,Output Data Format For 1st Cycle"
|
|
hexmask.long.byte 0x00 24.--27. 1. " BITALIGNMENTPIXEL2 ,Bit alignment"
|
|
hexmask.long.byte 0x00 16.--20. 1. " NBBITSPIXEL2 ,Number of bits"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--11. 1. " BITALIGNMENTPIXEL1 ,Bit alignment"
|
|
hexmask.long.byte 0x00 0.--4. 1. " NBBITSPIXEL1 ,Number of bits"
|
|
group.long 0x1D8++0x3
|
|
line.long 0x00 "DISPC_DATA_CYCLE2,Output Data Format For 2nd Cycle"
|
|
hexmask.long.byte 0x00 24.--27. 1. " BITALIGNMENTPIXEL2 ,Bit alignment"
|
|
hexmask.long.byte 0x00 16.--20. 1. " NBBITSPIXEL2 ,Number of bits"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--11. 1. " BITALIGNMENTPIXEL1 ,Bit alignment"
|
|
hexmask.long.byte 0x00 0.--4. 1. " NBBITSPIXEL1 ,Number of bits"
|
|
group.long 0x1DC++0x3
|
|
line.long 0x00 "DISPC_DATA_CYCLE3,Output Data Format For 3rd Cycle"
|
|
hexmask.long.byte 0x00 24.--27. 1. " BITALIGNMENTPIXEL2 ,Bit alignment"
|
|
hexmask.long.byte 0x00 16.--20. 1. " NBBITSPIXEL2 ,Number of bits"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--11. 1. " BITALIGNMENTPIXEL1 ,Bit alignment"
|
|
hexmask.long.byte 0x00 0.--4. 1. " NBBITSPIXEL1 ,Number of bits"
|
|
group.long 0x220++0xF
|
|
line.long 0x00 "DISPC_CPR_COEF_R,Color Phase Rotation Matrix Coefficients Configuration"
|
|
hexmask.long.word 0x00 22.--31. 1. " RR ,RR coefficient"
|
|
hexmask.long.word 0x00 11.--20. 1. " RG ,RG coefficient"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " RB ,RB coefficient"
|
|
line.long 0x04 "DISPC_CPR_COEF_G,Color Phase Rotation Matrix Coefficients Configuration"
|
|
hexmask.long.word 0x04 22.--31. 1. " GR ,GR coefficient"
|
|
hexmask.long.word 0x04 11.--20. 1. " GG ,GG coefficient"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " GB ,GB coefficient"
|
|
line.long 0x08 "DISPC_CPR_COEF_B,Color Phase Rotation Matrix Coefficients Configuration"
|
|
hexmask.long.word 0x08 22.--31. 1. " BR ,BR coefficient"
|
|
hexmask.long.word 0x08 11.--20. 1. " BG ,BG coefficient"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--9. 1. " BB ,BB coefficient"
|
|
line.long 0x0C "DISPC_GFX_PRELOAD,Graphics FIFO Configuration"
|
|
hexmask.long.word 0x0C 0.--11. 1. " PRELOAD ,Graphics preload value"
|
|
group.long 0xBC++0x7 "VID 0"
|
|
line.long 0x00 "DISPC_VID0_BA0,Base Address Of The Video Buffer For Video Window"
|
|
line.long 0x04 "DISPC_VID0_BA1,Base Address Of The Video Buffer For Video Window"
|
|
group.long (0xBC+0x08)++0x3
|
|
line.long 0x00 "DISPC_VID0_POSITION,Position Of The Video Window"
|
|
hexmask.long.word 0x00 16.--26. 1. " VIDPOSY ,Y position of the Video window"
|
|
hexmask.long.word 0x00 0.--10. 1. " VIDPOSX ,X position of the Video window"
|
|
group.long (0xBC+0x0C)++0x3
|
|
line.long 0x00 "DISPC_VID0_SIZE,Size Of The Video Window"
|
|
hexmask.long.word 0x00 16.--26. 1. " VIDSIZEY ,Number of lines of the Video window"
|
|
hexmask.long.word 0x00 0.--10. 1. " VIDSIZEX ,Number of pixels of the Video window"
|
|
group.long (0xBC+0x10)++0x7
|
|
line.long 0x00 "DISPC_VID0_ATTRIBUTES,Video Attributes"
|
|
bitfld.long 0x00 24. " VIDSELFREFRESH ,Enables the self refresh of the video window (data from the system memory)" "Not fetch,Fetch"
|
|
textline " "
|
|
bitfld.long 0x00 23. " VIDARBITRATION ,Priority of the video pipeline" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VIDLINEBUFFERSPLIT ,Video vertical line buffer split" "Not split,Split"
|
|
textline " "
|
|
bitfld.long 0x00 21. " VIDVERTICALTAPS ,Video vertical resize tap number" "3,5"
|
|
textline " "
|
|
bitfld.long 0x00 20. " VIDDMAOPTIMIZATION ,Video optimization in case of (pixel for each 32-bit OCP)" "1,2"
|
|
textline " "
|
|
bitfld.long 0x00 19. " VIDFIFOPRELOAD ,Video preload value (H/W prefetches pixels up to)" "Preload,High threshold"
|
|
textline " "
|
|
bitfld.long 0x00 18. " VIDROWREPEATENABLE ,Video Row Repeat" "Disabled,Fetched twice"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VIDCHANNELOUT ,Video Channel Out configuration" "LCD,24 bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " VIDBURSTSIZE ,Video DMA Burst Size" "4x32bit,8x32bit,16x32bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " VIDROTATION ,Video rotation flag" "No rotation,90 degrees,180 degrees,270 degrees"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VIDFULLRANGE ,VidFullRange" "Limited,Full"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VIDREPLICATIONENABLE ,VidReplicationEnable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VIDCOLORCONVENABLE ,VidColorConvEnable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VIDVRESIZECONF ,Video Vertical Resize Configuration" "Up-sampling,Down-sampling"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VIDHRESIZECONF ,Video Horizontal Resize Configuration" "Up-sampling,Down-sampling"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VIDRESIZEENABLE ,Video Resize Enable" "Disabled,Horizontal,Vertical,Horizontal/Vertical"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " VIDFORMAT ,Video format" "Rederved,Rederved,Rederved,Rederved,RGB 12,ARGB 16,RGB 16,Reserved,RGB 24/32-bit,RGB 24/24-bit,YUV2 4:2:2 co-sited,UYVY 4:2:2 co-sited,ARGB 32,RGBA 32,RGBx 32,Rederved"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VIDENABLE ,VIDEnable" "Disabled,Enabled"
|
|
line.long 0x04 "DISPC_VID0_FIFO_THRESHOLD,Video FIFO Configuration Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " VIDFIFOHIGHTHRESHOLD ,Video FIFO High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " VIDFIFOLOWTHRESHOLD ,Video FIFO Low Threshold"
|
|
rgroup.long (0xBC+0x18)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIFO_SIZE_STATUS,Video FIFO Size Configuration Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " VIDFIFOSIZE ,Video FIFO Size"
|
|
group.long (0xBC+0x1C)++0x7
|
|
line.long 0x00 "DISPC_VID0_ROW_INC,Number Of Bytes To Increment At The End Of The Row"
|
|
line.long 0x04 "DISPC_VID0_PIXEL_INC,Number Of Bytes To Increment Between Two Pixels"
|
|
hexmask.long.word 0x04 0.--15. 1. " VIDPIXELINC ,Number of bytes to increment between two pixels"
|
|
group.long (0xBC+0x24)++0xF
|
|
line.long 0x00 "DISPC_VID0_FIR,Resize Factors For Horizontal And Vertical Up-/Down-sampling Of Video Window"
|
|
hexmask.long.word 0x00 16.--28. 1. " VIDFIRVINC ,Vertical increment of the up-/down-sampling filter"
|
|
hexmask.long.word 0x00 0.--12. 1. " VIDFIRHINC ,Horizontal increment of the up-/down-sampling filter"
|
|
line.long 0x04 "DISPC_VID0_FIFO_PICTURE_SIZE,Size Of The Video Picture Associated With Video Layer"
|
|
hexmask.long.word 0x04 16.--26. 1. " VIDORGSIZEY ,Number of lines of the video picture"
|
|
hexmask.long.word 0x04 0.--10. 1. " VIDORGSIZEX ,Number of pixels of the video picture"
|
|
line.long 0x08 "DISPC_VID0_ACCU0,Resize Accumulator Init Values For Horizontal And Vertical Up-/Down-sampling"
|
|
hexmask.long.word 0x08 16.--25. 1. " VIDVERTICALACCU ,Vertical initialization accu value"
|
|
hexmask.long.word 0x08 0.--9. 1. " VIDHORIZONTALACCU ,Horizontal initialization accu value"
|
|
line.long 0x0C "DISPC_VID0_ACCU1,Resize Accumulator Init Values For Horizontal And Vertical Up-/Down-sampling"
|
|
hexmask.long.word 0x0C 16.--25. 1. " VIDVERTICALACCU ,Vertical initialization accu value"
|
|
hexmask.long.word 0x0C 0.--9. 1. " VIDHORIZONTALACCU ,Horizontal initialization accu value"
|
|
group.long (0xBC+0x34)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H0,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x3C)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H1,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x44)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H2,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x4C)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H3,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x54)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H4,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x5C)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H5,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x64)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H6,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x6C)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_H7,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x38)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV0,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x40)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV1,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x48)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV2,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x50)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV3,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x58)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV4,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x60)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV5,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x68)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV6,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x70)++0x3
|
|
line.long 0x00 "DISPC_VID0_FIR_COEF_HV7,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 0"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 0"
|
|
group.long (0xBC+0x70)++0x13
|
|
line.long 0x00 "DISPC_VID0_CONV_COEF0,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x00 16.--26. 1. " RCR ,RCr Coefficient"
|
|
hexmask.long.word 0x00 0.--10. 1. " RY ,RY Coefficient"
|
|
line.long 0x04 "DISPC_VID0_CONV_COEF1,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x04 16.--26. 1. " GY ,GY Coefficient"
|
|
hexmask.long.word 0x04 0.--10. 1. " RCB ,RCB Coefficient"
|
|
line.long 0x08 "DISPC_VID0_CONV_COEF2,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x08 16.--26. 1. " GCB ,GCB Coefficient"
|
|
hexmask.long.word 0x08 0.--10. 1. " GCR ,GCR Coefficient"
|
|
line.long 0x0C "DISPC_VID0_CONV_COEF3,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x0C 16.--26. 1. " BCR ,BCR Coefficient"
|
|
hexmask.long.word 0x0C 0.--10. 1. " BY ,BY Coefficient"
|
|
line.long 0x10 "DISPC_VID0_CONV_COEF4,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x10 0.--10. 1. " BCB ,BCB Coefficient"
|
|
group.long (0x0+0x1E0)++0x3
|
|
line.long 0x00 " DISPC_VID0_FIR_COEF_V0,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1E4)++0x3
|
|
line.long 0x00 " DISPC_VID0_FIR_COEF_V1,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1E8)++0x3
|
|
line.long 0x00 " DISPC_VID0_FIR_COEF_V2,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1EC)++0x3
|
|
line.long 0x00 " DISPC_VID0_FIR_COEF_V3,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1F0)++0x3
|
|
line.long 0x00 " DISPC_VID0_FIR_COEF_V4,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1F4)++0x3
|
|
line.long 0x00 " DISPC_VID0_FIR_COEF_V5,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1F8)++0x3
|
|
line.long 0x00 " DISPC_VID0_FIR_COEF_V6,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x1FC)++0x3
|
|
line.long 0x00 " DISPC_VID0_FIR_COEF_V7,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 0"
|
|
group.long (0x0+0x230)++0x3
|
|
line.long 0x00 "DISPC_VID0_PRELOAD,Video FIFO Configuration"
|
|
hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,Video preload value"
|
|
group.long 0x14C++0x7 "VID 1"
|
|
line.long 0x00 "DISPC_VID1_BA0,Base Address Of The Video Buffer For Video Window"
|
|
line.long 0x04 "DISPC_VID1_BA1,Base Address Of The Video Buffer For Video Window"
|
|
group.long (0x14C+0x08)++0x3
|
|
line.long 0x00 "DISPC_VID1_POSITION,Position Of The Video Window"
|
|
hexmask.long.word 0x00 16.--26. 1. " VIDPOSY ,Y position of the Video window"
|
|
hexmask.long.word 0x00 0.--10. 1. " VIDPOSX ,X position of the Video window"
|
|
group.long (0x14C+0x0C)++0x3
|
|
line.long 0x00 "DISPC_VID1_SIZE,Size Of The Video Window"
|
|
hexmask.long.word 0x00 16.--26. 1. " VIDSIZEY ,Number of lines of the Video window"
|
|
hexmask.long.word 0x00 0.--10. 1. " VIDSIZEX ,Number of pixels of the Video window"
|
|
group.long (0x14C+0x10)++0x7
|
|
line.long 0x00 "DISPC_VID1_ATTRIBUTES,Video Attributes"
|
|
bitfld.long 0x00 24. " VIDSELFREFRESH ,Enables the self refresh of the video window (data from the system memory)" "Not fetch,Fetch"
|
|
textline " "
|
|
bitfld.long 0x00 23. " VIDARBITRATION ,Priority of the video pipeline" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VIDLINEBUFFERSPLIT ,Video vertical line buffer split" "Not split,Split"
|
|
textline " "
|
|
bitfld.long 0x00 21. " VIDVERTICALTAPS ,Video vertical resize tap number" "3,5"
|
|
textline " "
|
|
bitfld.long 0x00 20. " VIDDMAOPTIMIZATION ,Video optimization in case of (pixel for each 32-bit OCP)" "1,2"
|
|
textline " "
|
|
bitfld.long 0x00 19. " VIDFIFOPRELOAD ,Video preload value (H/W prefetches pixels up to)" "Preload,High threshold"
|
|
textline " "
|
|
bitfld.long 0x00 18. " VIDROWREPEATENABLE ,Video Row Repeat" "Disabled,Fetched twice"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VIDCHANNELOUT ,Video Channel Out configuration" "LCD,24 bit"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " VIDBURSTSIZE ,Video DMA Burst Size" "4x32bit,8x32bit,16x32bit,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " VIDROTATION ,Video rotation flag" "No rotation,90 degrees,180 degrees,270 degrees"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VIDFULLRANGE ,VidFullRange" "Limited,Full"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VIDREPLICATIONENABLE ,VidReplicationEnable" "Disable,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VIDCOLORCONVENABLE ,VidColorConvEnable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VIDVRESIZECONF ,Video Vertical Resize Configuration" "Up-sampling,Down-sampling"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VIDHRESIZECONF ,Video Horizontal Resize Configuration" "Up-sampling,Down-sampling"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VIDRESIZEENABLE ,Video Resize Enable" "Disabled,Horizontal,Vertical,Horizontal/Vertical"
|
|
textline " "
|
|
bitfld.long 0x00 1.--4. " VIDFORMAT ,Video format" "Rederved,Rederved,Rederved,Rederved,RGB 12,ARGB 16,RGB 16,Reserved,RGB 24/32-bit,RGB 24/24-bit,YUV2 4:2:2 co-sited,UYVY 4:2:2 co-sited,ARGB 32,RGBA 32,RGBx 32,Rederved"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VIDENABLE ,VIDEnable" "Disabled,Enabled"
|
|
line.long 0x04 "DISPC_VID1_FIFO_THRESHOLD,Video FIFO Configuration Register"
|
|
hexmask.long.word 0x04 16.--27. 1. " VIDFIFOHIGHTHRESHOLD ,Video FIFO High Threshold"
|
|
hexmask.long.word 0x04 0.--11. 1. " VIDFIFOLOWTHRESHOLD ,Video FIFO Low Threshold"
|
|
rgroup.long (0x14C+0x18)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIFO_SIZE_STATUS,Video FIFO Size Configuration Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " VIDFIFOSIZE ,Video FIFO Size"
|
|
group.long (0x14C+0x1C)++0x7
|
|
line.long 0x00 "DISPC_VID1_ROW_INC,Number Of Bytes To Increment At The End Of The Row"
|
|
line.long 0x04 "DISPC_VID1_PIXEL_INC,Number Of Bytes To Increment Between Two Pixels"
|
|
hexmask.long.word 0x04 0.--15. 1. " VIDPIXELINC ,Number of bytes to increment between two pixels"
|
|
group.long (0x14C+0x24)++0xF
|
|
line.long 0x00 "DISPC_VID1_FIR,Resize Factors For Horizontal And Vertical Up-/Down-sampling Of Video Window"
|
|
hexmask.long.word 0x00 16.--28. 1. " VIDFIRVINC ,Vertical increment of the up-/down-sampling filter"
|
|
hexmask.long.word 0x00 0.--12. 1. " VIDFIRHINC ,Horizontal increment of the up-/down-sampling filter"
|
|
line.long 0x04 "DISPC_VID1_FIFO_PICTURE_SIZE,Size Of The Video Picture Associated With Video Layer"
|
|
hexmask.long.word 0x04 16.--26. 1. " VIDORGSIZEY ,Number of lines of the video picture"
|
|
hexmask.long.word 0x04 0.--10. 1. " VIDORGSIZEX ,Number of pixels of the video picture"
|
|
line.long 0x08 "DISPC_VID1_ACCU0,Resize Accumulator Init Values For Horizontal And Vertical Up-/Down-sampling"
|
|
hexmask.long.word 0x08 16.--25. 1. " VIDVERTICALACCU ,Vertical initialization accu value"
|
|
hexmask.long.word 0x08 0.--9. 1. " VIDHORIZONTALACCU ,Horizontal initialization accu value"
|
|
line.long 0x0C "DISPC_VID1_ACCU1,Resize Accumulator Init Values For Horizontal And Vertical Up-/Down-sampling"
|
|
hexmask.long.word 0x0C 16.--25. 1. " VIDVERTICALACCU ,Vertical initialization accu value"
|
|
hexmask.long.word 0x0C 0.--9. 1. " VIDHORIZONTALACCU ,Horizontal initialization accu value"
|
|
group.long (0x14C+0x34)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H0,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x3C)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H1,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x44)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H2,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x4C)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H3,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x54)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H4,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x5C)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H5,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x64)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H6,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x6C)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_H7,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRHC3 ,Signed coefficient C3 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRHC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRHC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x38)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV0,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x40)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV1,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x48)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV2,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x50)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV3,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x58)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV4,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x60)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV5,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x68)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV6,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x70)++0x3
|
|
line.long 0x00 "DISPC_VID1_FIR_COEF_HV7,Up-/Down-scaling Coefficients For The Vertical And Horizontal Resize"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VIDFIRVC2 ,Signed coefficient C2 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VIDFIRVC1 ,Signed coefficient C1 for the horizontal up-/down-scaling with the phase 1"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC0 ,Signed coefficient C0 for the horizontal up-/down-scaling with the phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRHC4 ,Signed coefficient C4 for the horizontal up-/down-scaling with the phase 1"
|
|
group.long (0x14C+0x70)++0x13
|
|
line.long 0x00 "DISPC_VID1_CONV_COEF0,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x00 16.--26. 1. " RCR ,RCr Coefficient"
|
|
hexmask.long.word 0x00 0.--10. 1. " RY ,RY Coefficient"
|
|
line.long 0x04 "DISPC_VID1_CONV_COEF1,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x04 16.--26. 1. " GY ,GY Coefficient"
|
|
hexmask.long.word 0x04 0.--10. 1. " RCB ,RCB Coefficient"
|
|
line.long 0x08 "DISPC_VID1_CONV_COEF2,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x08 16.--26. 1. " GCB ,GCB Coefficient"
|
|
hexmask.long.word 0x08 0.--10. 1. " GCR ,GCR Coefficient"
|
|
line.long 0x0C "DISPC_VID1_CONV_COEF3,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x0C 16.--26. 1. " BCR ,BCR Coefficient"
|
|
hexmask.long.word 0x0C 0.--10. 1. " BY ,BY Coefficient"
|
|
line.long 0x10 "DISPC_VID1_CONV_COEF4,Color Space Conversion Matrix Coefficients"
|
|
hexmask.long.word 0x10 0.--10. 1. " BCB ,BCB Coefficient"
|
|
group.long (0x20+0x1E0)++0x3
|
|
line.long 0x00 " DISPC_VID1_FIR_COEF_V0,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1E4)++0x3
|
|
line.long 0x00 " DISPC_VID1_FIR_COEF_V1,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1E8)++0x3
|
|
line.long 0x00 " DISPC_VID1_FIR_COEF_V2,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1EC)++0x3
|
|
line.long 0x00 " DISPC_VID1_FIR_COEF_V3,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1F0)++0x3
|
|
line.long 0x00 " DISPC_VID1_FIR_COEF_V4,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1F4)++0x3
|
|
line.long 0x00 " DISPC_VID1_FIR_COEF_V5,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1F8)++0x3
|
|
line.long 0x00 " DISPC_VID1_FIR_COEF_V6,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x20+0x1FC)++0x3
|
|
line.long 0x00 " DISPC_VID1_FIR_COEF_V7,Down/Up/Down-scaling Coefficients For The Vertical Resize Configuration"
|
|
hexmask.long.byte 0x00 8.--15. 1. " VIDFIRVC22 ,Signed coefficient C22 for vertical up/down-scaling with phase 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VIDFIRVC00 ,Signed coefficient C00 for vertical up/down-scaling with phase 1"
|
|
group.long (0x4+0x230)++0x3
|
|
line.long 0x00 "DISPC_VID1_PRELOAD,Video FIFO Configuration"
|
|
hexmask.long.word 0x00 0.--11. 1. " PRELOAD ,Video preload value"
|
|
width 0xb
|
|
tree.end
|
|
tree "RFBI"
|
|
base ad:0x48050800
|
|
width 20.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "RFBI_SYSCONFIG,Various Parameters Of The Interconnect Interface"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force idle,No idle,Smart-idle,?..."
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal auto-clock gating strategy" "Free running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "DISPC_SYSSTATUS,Status Information About The Module"
|
|
bitfld.long 0x00 9. " BUSYRFBIDATA ,Data are pending to be processed from internal FIFO" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " BUSY ,L4 Interface busy status bit" "Not stalled,Stalled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "On-going,Completed"
|
|
group.long 0x40++0xB
|
|
line.long 0x00 "RFBI_CONTROL,Configuration Of The RFBI Module"
|
|
bitfld.long 0x00 8. " SMART_DMA_REQ ,Smart DMA request" "Asserted,Not asserted"
|
|
bitfld.long 0x00 7. " DISABLE_DMA_REQ ,Disable DMA request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " HIGHTHRESHOLD ,Defines the FIFO high threshold" "4 words,8 words,16 words,?..."
|
|
bitfld.long 0x00 4. " ITE ,Internal Trigger" "H/W wait,User set"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CONFIGSELECT ,Select the CS and configuration" "No CS,CS0,CS1,CS0/CS1"
|
|
bitfld.long 0x00 1. " BYPASSMODE ,Bypass Mode" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Enable/Disable flag" "Disabled,Enabled"
|
|
line.long 0x04 "RFBI_PIXEL_CNT,RFBI Pixel Count Value Configuration Register"
|
|
line.long 0x08 "RFBI_LINE_NUMBER,Number Of Lines To Synchronize The Beginning Of The Transfer"
|
|
hexmask.long.word 0x08 0.--10. 1. " LINENUMBER ,Programmable line number"
|
|
wgroup.long 0x4C++0xB
|
|
line.long 0x00 "RFBI_CMD,RFBI Command Configuration Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CMD ,Command value"
|
|
line.long 0x04 "RFBI_PARAM,RFBI Parameter Configuration Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " PARAM ,Param value"
|
|
line.long 0x08 "RFBI_DATA,RFBI Data Configuration Register"
|
|
group.long 0x58++0x7
|
|
line.long 0x00 "RFBI_READ,RFBI Read Configuration Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " READ ,Read value"
|
|
line.long 0x04 "RFBI_STATUS,RFBI Status Configuration Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " STATUS ,Status value"
|
|
group.long 0x60++0x3
|
|
line.long 0x00 "RFBI_CONFIG0,RFBI Module Configuration Register"
|
|
bitfld.long 0x00 21. " HSYNCPOLARITY ,HSYNC polarity" "Low,High"
|
|
bitfld.long 0x00 20. " TE_VSYNC_POLARITY ,TE or VSYNC Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSPOLARITY ,CS Polarity" "Low,High"
|
|
bitfld.long 0x00 18. " WEPOLARITY ,WE Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " REPOLARITY ,RE Polarity" "Low,High"
|
|
bitfld.long 0x00 16. " A0POLARITY ,A0 Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " UNUSEDBITS ,State of unused bits" "Low,High,Unchanged,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " CYCLEFORMAT ,Cycle format" "1 cycle/1 pixel,2 cycles/1 pixel,3 cycles/1 pixel,3 cycles/2 pixels"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " L4FORMAT ,L4 Write Access format" "1 pixel,Reserved,2 pixels 1st at[15:0],2 pixels 1st at[31:16]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " DATA_TYPE ,Data type from the display controller and L4" "12-bit,16-bit,18-bit,24-bit"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEGRANULARITY ,Multiplies signal timing latencies by two" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TRIGGERMODE ,Trigger Mode" "ITE bit mode,Tearing effect signal,RFB_TE_VSYNC/RFB_HSYNC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PARALLEL_MODE ,Parallel Mode" "8-bit,9-bit,12-bit,16-bit"
|
|
group.long 0x78++0x3
|
|
line.long 0x00 "RFBI_CONFIG1,RFBI Module Configuration Register"
|
|
bitfld.long 0x00 21. " HSYNCPOLARITY ,HSYNC polarity" "Low,High"
|
|
bitfld.long 0x00 20. " TE_VSYNC_POLARITY ,TE or VSYNC Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSPOLARITY ,CS Polarity" "Low,High"
|
|
bitfld.long 0x00 18. " WEPOLARITY ,WE Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " REPOLARITY ,RE Polarity" "Low,High"
|
|
bitfld.long 0x00 16. " A0POLARITY ,A0 Polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " UNUSEDBITS ,State of unused bits" "Low,High,Unchanged,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " CYCLEFORMAT ,Cycle format" "1 cycle/1 pixel,2 cycles/1 pixel,3 cycles/1 pixel,3 cycles/2 pixels"
|
|
textline " "
|
|
bitfld.long 0x00 7.--8. " L4FORMAT ,L4 Write Access format" "1 pixel,Reserved,2 pixels 1st at[15:0],2 pixels 1st at[31:16]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " DATA_TYPE ,Data type from the display controller and L4" "12-bit,16-bit,18-bit,24-bit"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TIMEGRANULARITY ,Multiplies signal timing latencies by two" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " TRIGGERMODE ,Trigger Mode" "ITE bit mode,Tearing effect signal,RFB_TE_VSYNC/RFB_HSYNC,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " PARALLEL_MODE ,Parallel Mode" "8-bit,9-bit,12-bit,16-bit"
|
|
group.long 0x64++0x3
|
|
line.long 0x00 "RFBI_ONOFF_TIME0,RFBI Timing Control Register"
|
|
hexmask.long.byte 0x00 24.--29. 1. " REOFFTIME ,Read Enable deassertion time from start access time"
|
|
bitfld.long 0x00 20.--23. " REONTIME ,Read Enable assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 14.--19. 1. " WEOFFTIME ,Write Enable deassertion time from start access time"
|
|
bitfld.long 0x00 10.--13. " WEONTIME ,Write Enable assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--9. 1. " CSOFFTIME ,CS deassertion time from start access time"
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,CS assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "RFBI_ONOFF_TIME1,RFBI Timing Control Register"
|
|
hexmask.long.byte 0x00 24.--29. 1. " REOFFTIME ,Read Enable deassertion time from start access time"
|
|
bitfld.long 0x00 20.--23. " REONTIME ,Read Enable assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 14.--19. 1. " WEOFFTIME ,Write Enable deassertion time from start access time"
|
|
bitfld.long 0x00 10.--13. " WEONTIME ,Write Enable assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--9. 1. " CSOFFTIME ,CS deassertion time from start access time"
|
|
bitfld.long 0x00 0.--3. " CSONTIME ,CS assertion time from start access time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x68++0x3
|
|
line.long 0x00 "RFBI_CYCLE_TIME0,RFBI Timing Configuration Register"
|
|
hexmask.long.byte 0x00 22.--27. 1. " ACCESSTIME ,Access Time"
|
|
bitfld.long 0x00 21. " WRENABLE ,Write to Read Pulse Width Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WWENABLE ,Write to Write Pulse Width Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " RRENABLE ,Read to Read Pulse Width Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RWENABLE ,Read to Write Pulse Width Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " CSPULSEWIDTH ,CS Pulse Width"
|
|
textline " "
|
|
hexmask.long.byte 0x00 6.--11. 1. " RECYCLETIME ,RE Cycle Time"
|
|
hexmask.long.byte 0x00 0.--5. 1. " WECYCLETIME ,WE Cycle Time"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "RFBI_CYCLE_TIME1,RFBI Timing Configuration Register"
|
|
hexmask.long.byte 0x00 22.--27. 1. " ACCESSTIME ,Access Time"
|
|
bitfld.long 0x00 21. " WRENABLE ,Write to Read Pulse Width Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " WWENABLE ,Write to Write Pulse Width Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " RRENABLE ,Read to Read Pulse Width Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RWENABLE ,Read to Write Pulse Width Enable" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 12.--17. 1. " CSPULSEWIDTH ,CS Pulse Width"
|
|
textline " "
|
|
hexmask.long.byte 0x00 6.--11. 1. " RECYCLETIME ,RE Cycle Time"
|
|
hexmask.long.byte 0x00 0.--5. 1. " WECYCLETIME ,WE Cycle Time"
|
|
group.long 0x6C++0x3
|
|
line.long 0x00 "RFBI_DATA_CYCLE1_0,RFBI Data Format For 1st Cycle Configuration Register"
|
|
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
group.long 0x84++0x3
|
|
line.long 0x00 "RFBI_DATA_CYCLE1_1,RFBI Data Format For 1st Cycle Configuration Register"
|
|
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
group.long 0x70++0x3
|
|
line.long 0x00 "RFBI_DATA_CYCLE2_0,RFBI Data Format For 2nd Cycle Configuration Register"
|
|
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
group.long 0x88++0x3
|
|
line.long 0x00 "RFBI_DATA_CYCLE2_1,RFBI Data Format For 2nd Cycle Configuration Register"
|
|
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
group.long 0x74++0x3
|
|
line.long 0x00 "RFBI_DATA_CYCLE3_0,RFBI Data Format For 3rd Cycle Configuration Register"
|
|
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
group.long 0x8C++0x3
|
|
line.long 0x00 "RFBI_DATA_CYCLE3_1,RFBI Data Format For 3rd Cycle Configuration Register"
|
|
bitfld.long 0x00 24.--27. " BITALIGNMENTPIXEL2 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--20. " NBBITSPIXEL2 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " BITALIGNMENTPIXEL1 ,Bit alignment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--4. " NBBITSPIXEL1 ,Number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd,Reservrd"
|
|
group.long 0x90++0x7
|
|
line.long 0x00 "RFBI_VSYNC_WIDTH,RFBI VSYNC Minimum Pulse Width Configuration Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MINVSYNCPULSEWIDTH ,Programmable min VSYNC pulse width"
|
|
line.long 0x04 "RFBI_HSYNC_WIDTH,RFBI HSYNC Minimum Pulse Width Configuration Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MINHSYNCPULSEWIDTH ,Programmable min HSYNC pulse width"
|
|
width 0xb
|
|
tree.end
|
|
tree "VENC"
|
|
base ad:0x48050C00
|
|
width 18.
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "VENC_STATUS,VENC Status Register"
|
|
bitfld.long 0x00 4. " CCE ,Closed Caption Status for Even Field" "Not encoded,Encoded"
|
|
bitfld.long 0x00 3. " CCO ,Closed Caption Status for Odd Field" "Not encoded,Encoded"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " FSQ ,Field Sequence ID" "ODD,EVEN,?..."
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "VENC_F_CONTROL,Input Video Source And Format Configuration Register"
|
|
bitfld.long 0x00 8. " RESET ,RESET the encoder" "No effect,Reset"
|
|
bitfld.long 0x00 6.--7. " SVDS ,Select Video Data Source" "External video source,Internal color BAR,Background color,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " RGBF ,RGB/YCrCb input coding range" "0-255,16-235"
|
|
bitfld.long 0x00 2.--4. " BCOLOR ,Background color select" "Black,Blue,Red,Magenta,Green,Cyan,Yellow,White"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " FMT ,Video input data stream format and timing" "24-bit 4:4:4 RGB,24-bit 4:4:4,16-bit 4:2:2,8-bit ITU-R 656 4:2:2"
|
|
group.long 0x10++0x7
|
|
line.long 0x00 "VENC_VIDOUT_CTRL,Encoder Output Clock"
|
|
bitfld.long 0x00 0. " 27_54 ,Encoder output clock" "54MHz 4xoversampling,27MHz 2xoversampling"
|
|
line.long 0x04 "VENC_SYNC_CTRL,Sync Control Register"
|
|
bitfld.long 0x04 15. " FREE ,Free running" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " ESAV ,Enable to detect F and V bits" "EAV/SAV,Only EAV"
|
|
textline " "
|
|
bitfld.long 0x04 13. " IGNP ,Ignore protection bits in ITU-R 656 input mode" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x04 12. " NBLNKS ,Blank shaping" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 10.--11. " VBLKM ,Vertical blanking mode" "Internal default,Internal default/programmable,?..."
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " HBLKM ,Horizontal blanking mode" "Internal default,Internal programmable,External,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6. " FID_POL ,FID output polarity" "ODD=0/EVEN=1,ODD=1/EVEN=0"
|
|
width 24.
|
|
group.long 0x1C++0x2B
|
|
line.long 0x00 "VENC_LLEN,VENC_LLEN Control Register"
|
|
hexmask.long.word 0x00 0.--10. 1. " LLEN ,Line length or total number of pixels in a scan line"
|
|
line.long 0x04 "VENC_FLENS,VENC_FLENS Control Register"
|
|
hexmask.long.word 0x04 0.--10. 1. " FLENS ,The frame length or total number of lines in a frame"
|
|
line.long 0x08 "VENC_HFLTR_CTRL,VENC_HFLTR_CTRL Control Register"
|
|
bitfld.long 0x08 1.--2. " CINTP ,Chrominance interpolation filter control" "Enabled,1st sec bypassed,2nd sec bypassed,1st/2nd sec bypassed"
|
|
bitfld.long 0x08 0. " YINTP ,Luminance interpolation filter control" "Enabled,Bypassed"
|
|
line.long 0x0C "VENC_CC_CARR_WSS_CARR,Frequency Code Control"
|
|
hexmask.long.word 0x0C 16.--31. 1. " FWSS ,Wide screen signaling run-in code frequency control"
|
|
hexmask.long.word 0x0C 0.--15. 1. " FCC ,Close caption run-in code frequency control"
|
|
line.long 0x10 "VENC_C_PHASE,VENC_C_PHASE Control Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " CPHS ,Phase of the encoded video color subcarrier"
|
|
line.long 0x14 "VENC_GAIN_U,Gain Control For Cb Signal"
|
|
hexmask.long.word 0x14 0.--8. 1. " GU ,Gain control for Cb signal"
|
|
line.long 0x18 "VENC_GAIN_V,Gain Control Of Cr Signal"
|
|
hexmask.long.word 0x18 0.--8. 1. " GV ,Gain control of Cr signal"
|
|
line.long 0x1C "VENC_GAIN_Y,Gain Control Of Y Signal"
|
|
hexmask.long.word 0x1C 0.--8. 1. " GY ,Gain control of Y signal"
|
|
line.long 0x20 "VENC_BLACK_LEVEL,Video Encoder BLACK LEVEL"
|
|
hexmask.long.byte 0x20 0.--6. 1. " BLACK ,Black level setting"
|
|
line.long 0x24 "VENC_BLANK_LEVEL,Video Encoder BLANK LEVEL"
|
|
hexmask.long.byte 0x24 0.--6. 1. " BLANK ,Blank level setting"
|
|
line.long 0x28 "VENC_X_COLOR,Cross-Colour Control Register"
|
|
bitfld.long 0x28 6. " XCE ,Cross color reduction enable for composite video output" "Disabled,Enabled"
|
|
bitfld.long 0x28 3.--4. " XCBW ,Cross color reduction filter selection" "Notch 32.8%,Notch 26.5%,Notch 30.0%,Notch 29.2%"
|
|
textline " "
|
|
bitfld.long 0x28 0.--2. " LCD ,chroma channel delay compensation" "0,0.5 pixel,1.0 pixel,1.5 pixel,-2.0 pixel,-1.5 pixel,-1.0 pixel,-0.5 pixel"
|
|
if (((d.l((ad:0x48050C00+0x4C)))&0x80)==0x80)
|
|
;VENC_BSTAMP_WSS_DATA[7] SQP = Square-pixel sampling rate
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "VENC_M_CONTROL,VENC_M Control Register"
|
|
bitfld.long 0x00 7. " PALI ,PAL I enable" "Normal,Enabled"
|
|
bitfld.long 0x00 6. " PALN ,PAL N enable" "Normal,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PALPHS ,PAL switch phase setting" "Nominal,Inverted"
|
|
bitfld.long 0x00 2.--4. " CBW ,Chrominance lowpass filter bandwidth control" "-6db 21.8%,-6db 19.8%,-6db 18.0%,Reserved,Reserved,-6db 23.7%,-6db 26.8%,Filter bypass"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PAL ,Phase alternation line encoding selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FFRQ ,number of horizontal pixels displayed per scan line" "944,780"
|
|
else
|
|
group.long 0x48++0x3
|
|
line.long 0x00 " VENC_M_CONTROL,VENC_M Control Register"
|
|
bitfld.long 0x00 7. " PALI ,PAL I enable" "Normal,Enabled"
|
|
bitfld.long 0x00 6. " PALN ,PAL N enable" "Normal,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PALPHS ,PAL switch phase setting" "Nominal,Inverted"
|
|
bitfld.long 0x00 2.--4. " CBW ,Chrominance lowpass filter bandwidth control" "-6db 21.8%,-6db 19.8%,-6db 18.0%,Reserved,Reserved,-6db 23.7%,-6db 26.8%,Filter bypass"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PAL ,Phase alternation line encoding selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FFRQ ,number of horizontal pixels displayed per scan line" "864,858"
|
|
endif
|
|
group.long 0x4C++0x3F
|
|
line.long 0x00 "VENC_BSTAMP_WSS_DATA,VENC BSTAMP and WSS_DATA"
|
|
hexmask.long.tbyte 0x00 8.--27. 1. " WSS_DAT ,Wide Screen Signaling data"
|
|
bitfld.long 0x00 7. " SQP ,Square-pixel sampling rate" "ITU-R 601,Square-pixel"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--6. 1. " BSTAP ,Setting of amplitude of color burst"
|
|
line.long 0x04 "VENC_S_CARR,Color Subcarrier Frequency Registers"
|
|
line.long 0x08 "VENC_LINE21,VENC LINE 21 Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " L21E ,The two bytes of the closed caption data in the even field"
|
|
hexmask.long.word 0x08 0.--15. 1. " L21O ,The two bytes of the closed caption data in the odd field"
|
|
line.long 0x0C "VENC_LN_SEL,VENC_LN_SEL Register"
|
|
hexmask.long.word 0x0C 16.--25. 1. " LN21_RUNIN ,The two bytes of the closed caption runin code position from the HSYNC"
|
|
hexmask.long.byte 0x0C 0.--4. 1. " SLINE ,Selects the line where closed caption or extended service data are encoded"
|
|
line.long 0x10 "VENC_L21_WC_CTL,VENC L21 & WC_CTL Registers"
|
|
bitfld.long 0x10 15. " INV ,WSS inverter" "No effect,Inverted"
|
|
bitfld.long 0x10 13.--14. " EVEN_ODD_EN ,WSS encoding control" "Off,ODD,EVEN,ODD/EVEN"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--12. 1. " LINE ,Selects the line where WSS data are encoded"
|
|
bitfld.long 0x10 0.--1. " L21EN ,Line21 closed caption encoding according to the mode" "Off,ODD,EVEN,ODD/EVEN"
|
|
line.long 0x14 "VENC_HTRIGGER_VTRIGGER,VENC HTRIGGER and VTRIGGER"
|
|
hexmask.long.word 0x14 16.--25. 1. " VTRIG ,Vertical trigger reference for VSYNC"
|
|
hexmask.long.word 0x14 0.--10. 1. " HTRIG ,Horizontal trigger phase"
|
|
line.long 0x18 "VENC_SAVID_EAVID,VENC SAVID and EAVID"
|
|
hexmask.long.word 0x18 16.--26. 1. " EAVID ,End of active video"
|
|
hexmask.long.word 0x18 0.--10. 1. " SAVID ,Start of active video"
|
|
line.long 0x1C "VENC_FLEN_FAL,VENC FLEN and FAL"
|
|
hexmask.long.word 0x1C 16.--24. 1. " FAL ,First Active Line of Field"
|
|
hexmask.long.word 0x1C 0.--9. 1. " FLEN ,Field length"
|
|
line.long 0x20 "VENC_LAL_PHASE_RESET,VENC LAL and PHASE_RESET"
|
|
bitfld.long 0x20 17.--18. " PRES ,Phase reset mode" "No reset,Reset every two lines,Reset every eight fields,Reset every four fields"
|
|
bitfld.long 0x20 16. " SBLANK ,Data output enable" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--8. 1. " LAL ,Last Active Line of Field"
|
|
width 35.
|
|
line.long 0x24 "VENC_HS_INT_START_STOP_X,HSYNC Internal Start/Stop Pixel Value"
|
|
hexmask.long.word 0x24 16.--25. 1. " HS_INT_STOP_X ,HSYNC internal stop"
|
|
textline " "
|
|
hexmask.long.word 0x24 0.--9. 1. " HS_INT_START_X ,HSYNC internal start"
|
|
line.long 0x28 "VENC_HS_EXT_START_STOP_X,HSYNC External Start/Stop Pixel Value"
|
|
hexmask.long.word 0x28 16.--25. 1. " HS_EXT_STOP_X ,HSYNC external stop"
|
|
textline " "
|
|
hexmask.long.word 0x28 0.--9. 1. " HS_EXT_START_X ,HSYNC external start"
|
|
line.long 0x2C "VENC_HS_EXT_START_STOP_X,VSYNC Internal Start Pixel Value"
|
|
hexmask.long.word 0x2C 16.--25. 1. " VS_INT_START_X ,VSYNC internal start"
|
|
line.long 0x30 "VENC_VS_INT_STOP_X_VS_INT_START_Y,VSYNC Internal Start/Stop Pixel Value"
|
|
hexmask.long.word 0x30 16.--25. 1. " VS_INT_START_Y ,VSYNC internal start"
|
|
textline " "
|
|
hexmask.long.word 0x30 0.--9. 1. " VS_INT_STOP_X ,VSYNC internal stop"
|
|
line.long 0x34 "VENC_VS_INT_STOP_Y_VS_EXT_START_X,VSYNC External Start/Stop Pixel Value"
|
|
hexmask.long.word 0x34 16.--25. 1. " VS_EXT_START_X ,VSYNC external start"
|
|
textline " "
|
|
hexmask.long.word 0x34 0.--9. 1. " VS_INT_STOP_Y ,VSYNC external stop"
|
|
line.long 0x38 "VENC_VS_EXT_STOP_X_VS_EXT_START_Y,VSYNC External Start/Stop Line Value"
|
|
hexmask.long.word 0x38 16.--25. 1. " VS_EXT_START_Y ,VSYNC external start"
|
|
textline " "
|
|
hexmask.long.word 0x38 0.--9. 1. " VS_EXT_STOP_X ,VSYNC external stop"
|
|
line.long 0x3C "VENC_VS_EXT_STOP_Y,VSYNC External Start/Stop Line Value"
|
|
hexmask.long.word 0x3C 0.--9. 1. " VS_EXT_STOP_Y ,VSYNC external stop"
|
|
group.long 0x90++0x7
|
|
line.long 0x00 "VENC_AVID_START_STOP_X,VSYNC External Start/Stop Line Value"
|
|
hexmask.long.word 0x00 16.--25. 1. " AVID_STOP_X ,AVID stop pixel value"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " AVID_START_X ,AVID start pixel value"
|
|
line.long 0x04 "VENC_AVID_START_STOP_Y,VSYNC External Start/Stop Line Value"
|
|
hexmask.long.word 0x04 16.--25. 1. " AVID_STOP_Y ,AVID stop"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " AVID_START_Y ,AVID start"
|
|
width 38.
|
|
group.long 0xA0++0xB
|
|
line.long 0x00 "VENC_FID_INT_START_X_FID_INT_START_Y,FID Internal Start Line/Pixel Value"
|
|
hexmask.long.word 0x00 16.--25. 1. " FID_INT_START_Y ,FID internal stop"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " FID_INT_START_X ,FID internal start"
|
|
line.long 0x04 "VENC_FID_INT_OFFSET_Y_FID_EXT_START_X,FID External Start Pixel/Internal Offset Line Value"
|
|
hexmask.long.word 0x04 16.--25. 1. " FID_EXT_START_X ,FID external start"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " FID_INT_OFFSET_Y ,FID internal offset"
|
|
line.long 0x08 "VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y,FID External Start/External Offset Line Value"
|
|
hexmask.long.word 0x08 16.--25. 1. " FID_EXT_OFFSET_Y ,FID external offset"
|
|
textline " "
|
|
hexmask.long.word 0x08 0.--9. 1. " FID_EXT_START_Y ,FID external start"
|
|
group.long 0xB0++0xB
|
|
line.long 0x00 "VENC_TVDETGP_INT_START_STOP_X,TV Detection Start And Stop Pixel Values"
|
|
hexmask.long.word 0x00 16.--25. 1. " TVDETGP_INT_STOP_X ,TVDETGP internal stop"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " TVDETGP_INT_START_X ,TVDETGP internal start"
|
|
line.long 0x04 "VENC_TVDETGP_INT_START_STOP_Y,TV Detection Start And Stop Line Values"
|
|
hexmask.long.word 0x04 16.--25. 1. " TVDETGP_INT_STOP_Y ,TVDETGP internal stop"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--9. 1. " TVDETGP_INT_START_Y ,TVDETGP internal start"
|
|
width 18.
|
|
line.long 0x08 "VENC_GEN_CTRL,TVDETGP Enable And SYNC_POLARITY And UVPHASE_POL"
|
|
bitfld.long 0x08 26. " MS ,UVPHASE_POL MS mode UV phase" "CbCr,CrCb"
|
|
bitfld.long 0x08 25. " 656 ,UVPHASE_POL 656 input mode UV phase" "CbCr,CrCb"
|
|
textline " "
|
|
bitfld.long 0x08 24. " CBAR ,UVPHASE_POL CBAR mode UV phase" "CbCr,CrCb"
|
|
bitfld.long 0x08 23. " HIP ,HSYNC internal polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 22. " VIP ,VSYNC internal polarity" "Low,High"
|
|
bitfld.long 0x08 21. " HEP ,HSYNC external polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 20. " VEP ,VSYNC external polarity" "Low,High"
|
|
bitfld.long 0x08 19. " AVIDP ,AVID polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 18. " FIP ,FID internal polarity" "Low,High"
|
|
bitfld.long 0x08 17. " FEP ,FID external polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x08 16. " TVDP ,TVDETGP polarity" "Low,High"
|
|
bitfld.long 0x08 0. " EN ,TVDETGP generation enable" "Disabled,Enabled"
|
|
group.long 0xC4++0x7
|
|
line.long 0x00 "VENC_DAC_TST,Video DACs Test Controls And Values"
|
|
bitfld.long 0x00 7. " DAC_C_SEL ,Chroma Video DAC2 input selection" "DAC_C [9:0],Video port G[1:0]"
|
|
bitfld.long 0x00 6. " DAC_B_SEL ,Luma/Composite Video DAC1 input selection" "DAC_B [9:0],Video port G[1:0]"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DAC_DX ,Direct DAC output" "Normal,Test"
|
|
bitfld.long 0x00 3. " DAC_INVT ,DAC invert" "Inverted,Normal"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DACX_C ,DAC2 output activation" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DACX_B ,DAC1 output activation" "Disabled,Enabled"
|
|
line.long 0x04 "VENC_DAC_B_DAC_C,DAC Test Value For Dual-video DACs"
|
|
hexmask.long.word 0x04 16.--25. 1. " DAC_C ,chroma DAC2 input value"
|
|
hexmask.long.word 0x04 0.--9. 1. " DAC_B ,luma/composite DAC1 input value"
|
|
width 0xb
|
|
tree.end
|
|
tree "DSI"
|
|
tree "Protocol Engine Registers"
|
|
base ad:0x4804FC00
|
|
width 15.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "DSI_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (Interface/Functional clocks)" "Off,Maintained/Off,Off/Maintained,Maintained"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENWAKEUP ,Wakeup enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFT_RESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTO_IDLE ,Internal intrface clock gating strategy" "Free running,Applied"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "DSI_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 0. " RESET_DONE ,Internal reset monitoring" "On going,reset"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "DSI_IRQSTATUS,Interrupt Status Register"
|
|
bitfld.long 0x00 20. " TA_TO_IRQ ,Turn-around Time out" "Not pending,Pending"
|
|
bitfld.long 0x00 19. " LDO_POWER_GOOD_IRQ ,Transition of the status signal LDOPWRGOOD" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 18. " SYNC_LOST_IRQ ,Synchronization with Video port is lost" "Not pending,Pending"
|
|
bitfld.long 0x00 17. " ACK_TRIGGER_IRQ ,Acknowledge Trigger" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TE_TRIGGER_IRQ ,Tearing Effect Trigger" "Not pending,Pending"
|
|
bitfld.long 0x00 15. " LP_RX_TO_IRQ ,Interrupt for Low Power Rx Time out" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HS_TX_TO_IRQ ,Interrupt for High Speed Tx Time out" "Not pending,Pending"
|
|
bitfld.long 0x00 10. " COMPLEXIO_ERR_IRQ ,Error signaling from complex I/O" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PLL_RECAL_IRQ ,PLL recalibration event" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " PLL_UNLOCK_IRQ ,PLL un-lock event" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PLL_LOCK_IRQ ,PLL lock event" "Not pending,Pending"
|
|
bitfld.long 0x00 5. " RESYNCHRONIZATION_IRQ ,Video mode resynchronization" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " WAKEUP_IRQ ,Wakeup" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " VIRTUAL_CHANNEL3_IRQ ,Virtual channel #3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VIRTUAL_CHANNEL2_IRQ ,Virtual channel #2" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " VIRTUAL_CHANNEL1_IRQ ,Virtual channel #1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VIRTUAL_CHANNEL0_IRQ ,Virtual channel #0" "Not pending,Pending"
|
|
line.long 0x04 "DSI_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 20. " TA_TO_IRQ_EN ,Turn-around Time out" "Masked,Enabled"
|
|
bitfld.long 0x04 19. " LDO_POWER_GOOD_IRQ_EN ,Transition of the status signal LDOPWRGOOD" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 18. " SYNC_LOST_IRQ_EN ,Synchronization with Video port is lost" "Masked,Enabled"
|
|
bitfld.long 0x04 17. " ACK_TRIGGER_IRQ_EN ,Acknowledge Trigger" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " TE_TRIGGER_IRQv ,Tearing Effect Trigger" "Masked,Enabled"
|
|
bitfld.long 0x04 15. " LP_RX_TO_IRQ_EN ,Interrupt for Low Power Rx Time out" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 14. " HS_TX_TO_IRQ_EN ,Interrupt for High Speed Tx Time out" "Masked,Enabled"
|
|
bitfld.long 0x04 9. " PLL_RECAL_IRQ_EN ,PLL recalibration event" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PLL_UNLOCK_IRQ_EN ,PLL un-lock event" "Masked,Enabled"
|
|
bitfld.long 0x04 7. " PLL_LOCK_IRQ_EN ,PLL lock event" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RESYNCHRONIZATION_IRQ_EN ,Video mode resynchronization" "0,1"
|
|
bitfld.long 0x04 4. " WAKEUP_IRQ_EN ,Wakeup" "Masked,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "DSI_CTRL,Global Control Register"
|
|
bitfld.long 0x00 23. " HSA_BLANKING_MODE ,Blanking mode" "Blanking period/LPM,Long blanking packets only"
|
|
textline " "
|
|
bitfld.long 0x00 22. " HBP_BLANKING_MODE ,Blanking mode" "Blanking period/LPM,Long blanking packets only"
|
|
textline " "
|
|
bitfld.long 0x00 21. " HFP_BLANKING_MODE ,Blanking mode" "Blanking period/LPM,Long blanking packets only"
|
|
textline " "
|
|
bitfld.long 0x00 20. " BLANKING_MODE ,Blanking mode" "ULPS,Long blanking packets"
|
|
textline " "
|
|
bitfld.long 0x00 18. " VP_HSYNC_END ,HSYNC end pulse" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " VP_HSYNC_START ,HSYNC start pulse" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " VP_VSYNC_END ,VSYNC end pulse" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " VP_VSYNC_START ,VSYNC start pulse" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TRIGGER_RESET_MODE ,Selection of the trigger reset mode" "Synchronized,Immediate"
|
|
bitfld.long 0x00 12.--13. " LINE_BUFFER ,Number of line buffers to be used while receiving data on the video port" "No line,1 line,2 line,?..."
|
|
textline " "
|
|
bitfld.long 0x00 11. " VP_VSYNC_POL ,VP vertical synchronization signal polarity" "Active low,Active high"
|
|
bitfld.long 0x00 10. " VP_HSYNC_POL ,VP horizontal synchronization signal polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 9. " VP_DE_POL ,VP data enable signal polarity" "Active low,Active high"
|
|
bitfld.long 0x00 8. " VP_CLK_POL ,VP clock polarity" "Falling edge,Raising edge"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " VP_DATA_BUS_WIDTH ,Defines the size of the video port data bus" "16-bits,18-bits,24-bits,?..."
|
|
bitfld.long 0x00 5. " TRIGGER_RESET ,Send the reset trigger to the peripheral" "Completed,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VP_CLK_RATIO ,The field indicates the clock ratio" "VP_CLK/2,VP_CLK/3"
|
|
bitfld.long 0x00 3. " TX_FIFO_ARBITRATION ,arbitration scheme for granting the virtual channel request" "Round-robin,Sequential"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ECC_RX_EN ,Enables the Error Correction Code check for the received header" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CS_RX_EN ,Enables the checksum check for the received payload" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IF_EN ,Enables the module" "Disabled,Enabled"
|
|
width 25.
|
|
group.long 0x48++0x33
|
|
line.long 0x00 "DSI_COMPLEXIO_CFG1,Complexio Configuration Register"
|
|
bitfld.long 0x00 31. " SHADOWING ,Shadowing configuration" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 30. " GOBIT ,Allows the synchronized update of the shadow registers" "Reset,Set"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RESET_DONE ,Internal reset monitoring" "On going,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 27.--28. " PWR_CMD ,Command for power control of the complex I/O" "Off,On,Ultra low power,?..."
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " PWR_STATUS ,Status of the power control of the complex I/O" "Off,On,Ultra low power,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21. " LDO_POWER_GOOD_STATE ,Indicates the state of the signal LDOPWRGOOD" "Down,Up"
|
|
textline " "
|
|
bitfld.long 0x00 20. " USE_LDO_EXTERNAL ,Select the external LDO for the DSIPHY" "Internal LDO,External LDO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DATA2_POL ,+/- differential pin order of DATA lane 2" "+/-,-/+"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " DATA2_POSITION ,Position and order of the DATA lane 2" "Not used/connected,Lane 2 at position 1,Lane 2 at position 2,Lane 2 at position 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " DATA1_POL ,+/- pin orderHS_MANUAL_STOP_CTRL" "+/-,-/+"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DATA1_POSITION ,Position and order of the DATA lane 1" "Reserved,Lane 1 at position 1,Lane 1 at position 2,Lane 1 at position 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 3. " CLOCK_POL ,+/- differential pin order of CLOCK lane" "+/-,-/+"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CLOCK_POSITION ,Position and order of the CLOCK lane" "Reserved,Lane is at the position 1,Lane is at the position 2,Lane is at the position 3,?..."
|
|
line.long 0x04 "DSI_COMPLEXIO_IRQSTATUS,Interrupt Status Register"
|
|
bitfld.long 0x04 31. " ULPSACTIVENOT_ALL1_IRQ ,ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 30. " ULPSACTIVENOT_ALL0_IRQ ,All signals ULPSActiveNOT are 0" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ERRCONTENTIONLP1_3_IRQ ,Contention LP1 error for lane #3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 24. " ERRCONTENTIONLP0_3_IRQ ,Contention LP0 error for lane #3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 23. " ERRCONTENTIONLP1_2_IRQ ,Contention LP1 error for lane #2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 22. " ERRCONTENTIONLP0_2_IRQ ,Contention LP0 error for lane #2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 21. " ERRCONTENTIONLP1_1_IRQ ,Contention LP1 error for lane #1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 20. " ERRCONTENTIONLP0_1_IRQ ,Contention LP0 error for lane #1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 17. " STATEULPS3_IRQ ,Lane #3 in Ultra Low Power State" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 16. " STATEULPS2_IRQ ,Lane #2 in Ultra Low Power State" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 15. " STATEULPS1_IRQ ,Lane #1 in Ultra Low Power State" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 12. " ERRCONTROL3_IRQ ,Control error for lane #3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 11. " ERRCONTROL2_IRQ ,Control error for lane #2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 10. " ERRCONTROL1_IRQ ,Control error for lane #1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ERRESC3_IRQ ,Escape entry error for lane #3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 6. " ERRESC2_IRQ ,Escape entry error for lane #2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ERRESC1_IRQ ,Escape entry error for lane #1" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 2. " ERRSYNCESC3_IRQ ,Low power Data transmission synchronization error for lane #3" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ERRSYNCESC2_IRQ ,Low power Data transmission synchronization error for lane #2" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ERRSYNCESC1_IRQ ,Low power Data transmission synchronization error for lane #1" "Not pending,Pending"
|
|
line.long 0x08 "DSI_COMPLEXIO_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x08 31. " ULPSACTIVENOT_ALL1_IRQ_EN ,ULPSActiveNOT signals corresponding to the lanes with TXULPSExit being high are high" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 30. " ULPSACTIVENOT_ALL0_IRQ_EN ,All signals ULPSActiveNOT are 0" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ERRCONTENTIONLP1_3_IRQ_EN ,Contention LP1 error for lane #3" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 24. " ERRCONTENTIONLP0_3_IRQ_EN ,Contention LP0 error for lane #3" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " ERRCONTENTIONLP1_2_IRQ_EN ,Contention LP1 error for lane #2" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " ERRCONTENTIONLP0_2_IRQ_EN ,Contention LP0 error for lane #2" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " ERRCONTENTIONLP1_1_IRQ_EN ,Contention LP1 error for lane #1" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 20. " ERRCONTENTIONLP0_1_IRQ_EN ,Contention LP0 error for lane #1" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " STATEULPS3_IRQ_EN ,Lane #3 in Ultra Low Power State" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 16. " STATEULPS2_IRQ_EN ,Lane #2 in Ultra Low Power State" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " STATEULPS1_IRQ_EN ,Lane #1 in Ultra Low Power State" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " ERRCONTROL3_IRQ_EN ,Control error for lane #3" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " ERRCONTROL2_IRQ_EN ,Control error for lane #2" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " ERRCONTROL1_IRQ_EN ,Control error for lane #1" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ERRESC3_IRQ_EN ,Escape entry error for lane #3" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " ERRESC2_IRQ_EN ,Escape entry error for lane #2" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " ERRESC1_IRQ_EN ,Escape entry error for lane #1" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ERRSYNCESC3_IRQ_EN ,Low power Data transmission synchronization error for lane #3" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ERRSYNCESC2_IRQ_EN ,Low power Data transmission synchronization error for lane #2" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ERRSYNCESC1_IRQ_EN ,Low power Data transmission synchronization error for lane #1" "Masked,Enabled"
|
|
width 16.
|
|
line.long 0x0C "DSI_CLK_CTRL,Clock Control Register"
|
|
bitfld.long 0x0C 30.--31. " PLL_PWR_CMD ,Command for power control of the DSI PLL Control module" "Off,On for PLL,On for PLL/HSDIVISER,On for PLL/HSDIVISER no clk"
|
|
textline " "
|
|
bitfld.long 0x0C 28.--29. " PLL_PWR_STATUS ,Status of the power control of the DSI PLL Control module" "Off,On for PLL,On for PLL/HSDIVISER,On for PLL/HSDIVISER no clk"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " LP_RX_SYNCHRO_ENABLE ,DSI functional clock is higher or lower than 30 MHz" "<=30MHz,>30MHz"
|
|
textline " "
|
|
bitfld.long 0x0C 20. " LP_CLK_ENABLE ,Controls the gating of the TXCLKESC clock" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " HS_MANUEL_STOP_CTRL ,In case HS_AUTO_STOP_ENABLE bit is set to 0" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " HS_AUTO_STOP_ENABLE ,Enables the automatic assertion/de-assertion of DSIStopClk" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 16.--17. " LP_CLK_NULL_PACKET_SIZE ,Indicates the size of LS NULL Packets" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " LP_CLK_NULL_PACKET_ENABLE ,Enables the generation of NULL packet in low speed" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " CIO_CLK_ICG ,Controls the signal for gating the L3_ICLK" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " DDR_CLK_ALWAYS_ON ,Defines if the DDR clock is also sent when there is no HS" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x0C 0.--12. 1. " LP_CLK_DIVISOR ,Ratio to be used for the generation of the Low Power mode clock from DSI functional clock"
|
|
line.long 0x10 "DSI_TIMING1,DSI Protocol Engine Module Timers Control"
|
|
bitfld.long 0x10 31. " TA_TO ,Enables the turn-around timer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 30. " TA_TO_X16 ,Multiplication factor for the number of DSI_FCLK clock cycles" "x1,x16"
|
|
textline " "
|
|
bitfld.long 0x10 29. " TA_TO_X8 ,Multiplication factor for the number of DSI_FCLK clock cycles" "x1,x8"
|
|
textline " "
|
|
hexmask.long.word 0x10 16.--28. 1. " TA_TO_COUNTER ,Turn around counter"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FORCE_TX_STOP_MODE_IO ,Control of ForceTxStopMode signal" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.long 0x10 14. " STOP_STATE_X16_IO ,Multiplication factor for the number of DSI_FCLK clock cycles" "x1,x16"
|
|
textline " "
|
|
bitfld.long 0x10 13. " STOP_STATE_X4_IO ,Multiplication factor for the number of DSI_FCLK clock cycles" "x1,x4"
|
|
textline " "
|
|
hexmask.long.word 0x10 0.--12. 1. " STOP_STATE_COUNTER_IO ,Stop state counter"
|
|
line.long 0x14 "DSI_TIMING2,DSI Protocol Engine Module Timers Control"
|
|
bitfld.long 0x14 31. " HS_TX_TO ,Enables the HS TX timer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 30. " HS_TX_TO_X16 ,Multiplication factor for the number of TxByteClkHS clock cycles" "x1,x16"
|
|
textline " "
|
|
bitfld.long 0x14 29. " HS_TX_TO_X8 ,Multiplication factor for the number of TxByteClkHS clock cycles" "x1,x8"
|
|
textline " "
|
|
hexmask.long.word 0x14 16.--28. 1. " HS_TX_TO_COUNTER ,HS_TX_TIMER counter"
|
|
textline " "
|
|
bitfld.long 0x14 15. " LP_RX_TO ,Enables the LP RX timer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 14. " LP_RX_TO_X16 ,Multiplication factor for the number of DSI_FCLK clock cycles" "x1,x16"
|
|
textline " "
|
|
bitfld.long 0x14 13. " LP_RX_TO_X4 ,Multiplication factor for the number of DSI_FCLK clock cycles" "x1,x4"
|
|
textline " "
|
|
hexmask.long.word 0x14 0.--12. 1. " LP_RX_TO_COUNTER ,LP_RX_TIMER counter"
|
|
line.long 0x18 "DSI_VM_TIMING1,Video Mode Timing Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " HSA ,Horizontal Sync active period used in video mode"
|
|
textline " "
|
|
hexmask.long.word 0x18 12.--23. 1. " HFP ,Horizontal front porch used in video mode"
|
|
textline " "
|
|
hexmask.long.word 0x18 0.--11. 1. " HBP ,Horizontal back porch used in video mode"
|
|
line.long 0x1C "DSI_VM_TIMING2,Video Mode Timing Register"
|
|
bitfld.long 0x1C 24.--27. " WINDOW_SYNC ,Number of TxByteClkHS clock cycles for the synchronization window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 16.--23. 1. " VSA ,vertical Sync active period used in video mode"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 8.--15. 1. " VFP ,vertical front porch used in video mode"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " VBP ,vertical back porch used in video mode"
|
|
line.long 0x20 "DSI_VM_TIMING3,Video Mode Timing Register"
|
|
hexmask.long.word 0x20 16.--31. 1. " TL ,Defines the number of length of the line in video mode"
|
|
textline " "
|
|
hexmask.long.word 0x20 0.--15. 1. " VACT ,Defines the number of active lines used in video mode"
|
|
line.long 0x24 "DSI_CLK_TIMING,Clock Timing Register"
|
|
hexmask.long.byte 0x24 8.--15. 1. " DDR_CLK_PRE ,Number of PPI Byte clock cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x24 0.--7. 1. " DDR_CLK_POST ,Number of PPI Byte clock cycles"
|
|
width 21.
|
|
line.long 0x28 "DSI_TX_FIFO_VC_SIZE,Corresponding Memory Entries Allocated For Each Virtual Channel"
|
|
bitfld.long 0x28 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x28 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x28 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x28 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x28 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x28 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x28 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x28 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x2C "DSI_RX_FIFO_VC_SIZE,Corresponding Memory Entries Allocated For Each Virtual Channel And The Addresses"
|
|
bitfld.long 0x2C 28.--31. " VC3_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 3" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x2C 24.--26. " VC3_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 3" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x2C 20.--23. " VC2_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 2" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x2C 16.--18. " VC2_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x2C 12.--15. " VC1_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 1" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x2C 8.--10. " VC1_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 1" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x2C 4.--7. " VC0_FIFO_SIZE ,Size of the FIFO allocated for virtual channel 0" "0,1,2,3,4,5,6,7,8,?..."
|
|
bitfld.long 0x2C 0.--2. " VC0_FIFO_ADD ,Address of the space allocated in the FIFO for virtual channel 0" "0,1,2,3,4,5,6,7"
|
|
line.long 0x30 "DSI_COMPLEXIO_CFG2,Complexio Configuration Register"
|
|
bitfld.long 0x30 17. " LP_BUSY ,still pending operations for VCs configured for LP mode" "Idle,Active"
|
|
bitfld.long 0x30 16. " HS_BUSY ,still pending operations for VCs configured for HS mode" "Idle,Active"
|
|
textline " "
|
|
bitfld.long 0x30 7. " LANE3_ULPS_SIG2 ,Enables the ULPS for the lane #3" "Not active,Active"
|
|
bitfld.long 0x30 6. " LANE2_ULPS_SIG2 ,Enables the ULPS for the lane #2" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x30 5. " LANE1_ULPS_SIG2 ,Enables the ULPS for the lane #1" "Not active,Active"
|
|
bitfld.long 0x30 2. " LANE3_ULPS_SIG1 ,Enables the ULPS for the lane #3" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x30 1. " LANE2_ULPS_SIG1 ,Enables the ULPS for the lane #2" "Not active,Active"
|
|
bitfld.long 0x30 0. " LANE1_ULPS_SIG1 ,Enables the ULPS for the lane #1" "Not active,Active"
|
|
width 25.
|
|
rgroup.long 0x7C++0x3
|
|
line.long 0x00 "DSI_RX_FIFO_VC_FULLNESS,Defines The Fullness Of Each Space Allocated For Each Virtual Channel"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VC3_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VC2_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VC1_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VC0_FIFO_FULLNESS ,Fullness of the FIFO allocated for virtual channel 0"
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "DSI_VM_TIMING4,Video Mode Timing Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HSA_HS_INTERLEAVING ,number of HS byte clock cycles during HSA"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HFP_HS_INTERLEAVING ,number of HS byte clock cycles during HFP"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " HBP_HS_INTERLEAVING ,number of HS byte clock cycles during HBP"
|
|
rgroup.long 0x84++0x3
|
|
line.long 0x00 "DSI_TX_FIFO_VC_EMPTINESS,Defines The Emptiness Of Each Space Allocated For Each Virtual Channel"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VC3_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " VC2_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 2"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " VC1_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " VC0_FIFO_EMPTINESS ,Emptiness of the FIFO allocated for virtual channel 0"
|
|
width 20.
|
|
group.long 0x88++0xF
|
|
line.long 0x00 "DSI_VM_TIMING5,Video Mode Timing Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " HSA_LP_INTERLEAVING ,Number of bytes for Low Power command mode during HSA"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HFP_LP_INTERLEAVING ,Number of bytes for Low Power command mode during HFP"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " HBP_LP_INTERLEAVING ,Number of bytes for Low Power command mode during HBP"
|
|
line.long 0x04 "DSI_VM_TIMING6,Video Mode Timing Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " BL_HS_INTERLEAVING ,Number of TxByteClkHS clock cycles"
|
|
hexmask.long.word 0x04 0.--15. 1. " BL_LP_INTERLEAVING ,Maximum number of bytes for Low Power command"
|
|
line.long 0x08 "DSI_VM_TIMING7,Video Mode Timing Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " ENTER_HS_MODE_LATENCY ,Number of TxByteClkHS clock cycles necessary for entering to HS mode"
|
|
hexmask.long.word 0x08 0.--15. 1. " EXIT_HS_MODE_LATENCY ,Number of TxByteClkHS clock cycles necessary for exiting from HS mode"
|
|
line.long 0x0C "DSI_STOPCLK_TIMING,Number Of Functional Clock Cycles To Wait For TxByteClock To Stop/Start"
|
|
hexmask.long.word 0x0C 0.--15. 1. " DSI_STOPCLK_LATENCY ,Clock gating latency from DSI Protocol engine to TxByteClkHS"
|
|
width 14.
|
|
group.long 0x100++0xB "Virtual Channel 0"
|
|
line.long 0x00 "DSI_VC0_CTRL,Virtual Channel Control Register"
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low power,High Speed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "completed,Requested"
|
|
bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODE ,Selection of the mode" "Command,Video"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after long packet transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between slave port and Video port" "Slave port,Video port"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_EN , Enables the virtual channel" "Disabled,Enabled"
|
|
line.long 0x04 "DSI_VC0_TE,Virtual Channel Control Register"
|
|
bitfld.long 0x04 17. " TE_SIZE ,Manual control of the start of the transfer" "End,Start"
|
|
bitfld.long 0x04 16. " TE_EN ,Tearing Effect Control" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " TE_START ,Defines the number of byte"
|
|
width 29.
|
|
line.long 0x08 "DSI_VC0_LONG_PACKET_HEADER,Long Packet Header Information"
|
|
wgroup.long (0x100+0xC)++0x3
|
|
line.long 0x00 "DSI_VC0_LONG_PACKET_PAYLOAD,Long Packet Payload Information"
|
|
group.long (0x100+0x10)++0x3
|
|
line.long 0x00 "DSI_VC0_SHORT_PACKET_HEADER,Short Packet Header Information"
|
|
width 19.
|
|
group.long (0x100+0x18)++0x7
|
|
line.long 0x00 "DSI_VC0_IRQSTATUS,Interrupt Status Register"
|
|
bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,ECC used to do the correction the only 1-bit error status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " CS_IRQ ,Check-Sum mismatch status" "Not pending,Pending"
|
|
line.long 0x04 "DSI_VC0_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow status" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BTA_IRQ_EN ,Virtual channel - BTA status" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
bitfld.long 0x04 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ECC_CORRECTION_IRQ_EN ,ECC used to do the correction the only 1-bit error status" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CS_IRQ_EN ,Check-Sum mismatch status" "Masked,Enabled"
|
|
width 14.
|
|
group.long 0x120++0xB "Virtual Channel 1"
|
|
line.long 0x00 "DSI_VC1_CTRL,Virtual Channel Control Register"
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low power,High Speed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "completed,Requested"
|
|
bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODE ,Selection of the mode" "Command,Video"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after long packet transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between slave port and Video port" "Slave port,Video port"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_EN , Enables the virtual channel" "Disabled,Enabled"
|
|
line.long 0x04 "DSI_VC1_TE,Virtual Channel Control Register"
|
|
bitfld.long 0x04 17. " TE_SIZE ,Manual control of the start of the transfer" "End,Start"
|
|
bitfld.long 0x04 16. " TE_EN ,Tearing Effect Control" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " TE_START ,Defines the number of byte"
|
|
width 29.
|
|
line.long 0x08 "DSI_VC1_LONG_PACKET_HEADER,Long Packet Header Information"
|
|
wgroup.long (0x120+0xC)++0x3
|
|
line.long 0x00 "DSI_VC1_LONG_PACKET_PAYLOAD,Long Packet Payload Information"
|
|
group.long (0x120+0x10)++0x3
|
|
line.long 0x00 "DSI_VC1_SHORT_PACKET_HEADER,Short Packet Header Information"
|
|
width 19.
|
|
group.long (0x120+0x18)++0x7
|
|
line.long 0x00 "DSI_VC1_IRQSTATUS,Interrupt Status Register"
|
|
bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,ECC used to do the correction the only 1-bit error status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " CS_IRQ ,Check-Sum mismatch status" "Not pending,Pending"
|
|
line.long 0x04 "DSI_VC1_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow status" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BTA_IRQ_EN ,Virtual channel - BTA status" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
bitfld.long 0x04 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ECC_CORRECTION_IRQ_EN ,ECC used to do the correction the only 1-bit error status" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CS_IRQ_EN ,Check-Sum mismatch status" "Masked,Enabled"
|
|
width 14.
|
|
group.long 0x140++0xB "Virtual Channel 2"
|
|
line.long 0x00 "DSI_VC2_CTRL,Virtual Channel Control Register"
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low power,High Speed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "completed,Requested"
|
|
bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODE ,Selection of the mode" "Command,Video"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after long packet transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between slave port and Video port" "Slave port,Video port"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_EN , Enables the virtual channel" "Disabled,Enabled"
|
|
line.long 0x04 "DSI_VC2_TE,Virtual Channel Control Register"
|
|
bitfld.long 0x04 17. " TE_SIZE ,Manual control of the start of the transfer" "End,Start"
|
|
bitfld.long 0x04 16. " TE_EN ,Tearing Effect Control" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " TE_START ,Defines the number of byte"
|
|
width 29.
|
|
line.long 0x08 "DSI_VC2_LONG_PACKET_HEADER,Long Packet Header Information"
|
|
wgroup.long (0x140+0xC)++0x3
|
|
line.long 0x00 "DSI_VC2_LONG_PACKET_PAYLOAD,Long Packet Payload Information"
|
|
group.long (0x140+0x10)++0x3
|
|
line.long 0x00 "DSI_VC2_SHORT_PACKET_HEADER,Short Packet Header Information"
|
|
width 19.
|
|
group.long (0x140+0x18)++0x7
|
|
line.long 0x00 "DSI_VC2_IRQSTATUS,Interrupt Status Register"
|
|
bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,ECC used to do the correction the only 1-bit error status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " CS_IRQ ,Check-Sum mismatch status" "Not pending,Pending"
|
|
line.long 0x04 "DSI_VC2_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow status" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BTA_IRQ_EN ,Virtual channel - BTA status" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
bitfld.long 0x04 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ECC_CORRECTION_IRQ_EN ,ECC used to do the correction the only 1-bit error status" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CS_IRQ_EN ,Check-Sum mismatch status" "Masked,Enabled"
|
|
width 14.
|
|
group.long 0x160++0xB "Virtual Channel 3"
|
|
line.long 0x00 "DSI_VC3_CTRL,Virtual Channel Control Register"
|
|
bitfld.long 0x00 27.--29. " DMA_RX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 24.--26. " DMA_RX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " DMA_TX_REQ_NB ,Selection of the use of the DMA request" "DSI_DMA_REQ0,DSI_DMA_REQ1,DSI_DMA_REQ2,DSI_DMA_REQ3,No DMA req,?..."
|
|
bitfld.long 0x00 20. " RX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " DMA_TX_THRESHOLD ,Defines the threshold value for the DMA request" "1x32 bits,2x32 bits,4x32 bits,8x32 bits,16x32 bits,32x32 bits,?..."
|
|
bitfld.long 0x00 16. " TX_FIFO_FULL ,FIFO status" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x00 15. " VC_BUSY ,Indicates if previously scheduled activities" "Not pending,Pending"
|
|
bitfld.long 0x00 9. " MODE_SPEED ,Selection of the mode" "Low power,High Speed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ECC_TX_EN ,Enables the Error Correction Code generation for the transmit header" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " CS_TX_EN ,Enables the checksum generation for the transmit payload" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BTA_EN ,Send the bus turn around to the peripheral" "completed,Requested"
|
|
bitfld.long 0x00 5. " TX_FIFO_NOT_EMPTY ,FIFO status" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MODE ,Selection of the mode" "Command,Video"
|
|
bitfld.long 0x00 3. " BTA_LONG_EN ,Enables the automatic bus turn-around after long packet transmission" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BTA_SHORT_EN ,Enables the automatic bus turn-around after short packet transmission" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOURCE ,Selection of the source between slave port and Video port" "Slave port,Video port"
|
|
textline " "
|
|
bitfld.long 0x00 0. " VC_EN , Enables the virtual channel" "Disabled,Enabled"
|
|
line.long 0x04 "DSI_VC3_TE,Virtual Channel Control Register"
|
|
bitfld.long 0x04 17. " TE_SIZE ,Manual control of the start of the transfer" "End,Start"
|
|
bitfld.long 0x04 16. " TE_EN ,Tearing Effect Control" "Disabled,Enabled"
|
|
textline " "
|
|
hexmask.long.word 0x04 0.--15. 1. " TE_START ,Defines the number of byte"
|
|
width 29.
|
|
line.long 0x08 "DSI_VC3_LONG_PACKET_HEADER,Long Packet Header Information"
|
|
wgroup.long (0x160+0xC)++0x3
|
|
line.long 0x00 "DSI_VC3_LONG_PACKET_PAYLOAD,Long Packet Payload Information"
|
|
group.long (0x160+0x10)++0x3
|
|
line.long 0x00 "DSI_VC3_SHORT_PACKET_HEADER,Short Packet Header Information"
|
|
width 19.
|
|
group.long (0x160+0x18)++0x7
|
|
line.long 0x00 "DSI_VC3_IRQSTATUS,Interrupt Status Register"
|
|
bitfld.long 0x00 7. " FIFO_TX_UDF_IRQ ,FIFO underflow status" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " ECC_NO_CORRECTION_IRQ ,ECC error status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BTA_IRQ ,Virtual channel - BTA status" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " FIFO_RX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FIFO_TX_OVF_IRQ ,FIFO overflow error status" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " PACKET_SENT_IRQ ,Indicates that a packet has been sent" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ECC_CORRECTION_IRQ ,ECC used to do the correction the only 1-bit error status" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " CS_IRQ ,Check-Sum mismatch status" "Not pending,Pending"
|
|
line.long 0x04 "DSI_VC3_IRQENABLE,Interrupt Enable Register"
|
|
bitfld.long 0x04 7. " FIFO_TX_UDF_IRQ_EN ,FIFO underflow status" "Masked,Enabled"
|
|
bitfld.long 0x04 6. " ECC_NO_CORRECTION_IRQ_EN ,ECC error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " BTA_IRQ_EN ,Virtual channel - BTA status" "Masked,Enabled"
|
|
bitfld.long 0x04 4. " FIFO_RX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FIFO_TX_OVF_IRQ_EN ,FIFO overflow error status" "Masked,Enabled"
|
|
bitfld.long 0x04 2. " PACKET_SENT_IRQ_EN ,Indicates that a packet has been sent" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ECC_CORRECTION_IRQ_EN ,ECC used to do the correction the only 1-bit error status" "Masked,Enabled"
|
|
bitfld.long 0x04 0. " CS_IRQ_EN ,Check-Sum mismatch status" "Masked,Enabled"
|
|
width 0xb
|
|
tree.end
|
|
tree "Complex I/O Registers"
|
|
base ad:0x4804FE00
|
|
width 13.
|
|
group.long 0x00++0xB
|
|
line.long 0x00 "DSIPHY_CFG0,Configuration Register For HS Mode Timings"
|
|
hexmask.long.byte 0x00 24.--31. 1. " THS_PREPARE ,THS-PREPARE timing parameter"
|
|
hexmask.long.byte 0x00 16.--23. 1. " THS_PREPARE_THS_ZERO ,THS-PREPARE + THS-ZERO timing parameter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " THS_TRAIL ,THS-TRAIL timing parameter"
|
|
hexmask.long.byte 0x00 0.--7. 1. " THS_EXIT ,Ths-exit timing parameter"
|
|
line.long 0x04 "DSIPHY_CFG1,Configuration Register For LP Mode And HS Mode Timings"
|
|
hexmask.long.byte 0x04 16.--22. 1. " TLPX_HALF ,(TLPX)/2 timing parameter in multiples of DDR clock frequency"
|
|
hexmask.long.byte 0x04 8.--15. 1. " TCLK_TRAIL ,TCLK-TRAIL timing parameter in multiples of DDR clock frequency"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " TCLK_ZERO ,TCLK-ZERO timing parameter in multiples of DDR clock period"
|
|
line.long 0x08 "DSIPHY_CFG2,Sync Pattern And Reserved Bits"
|
|
hexmask.long.byte 0x08 0.--7. 1. " TCLK_PREPARE ,TCLK-PREPARE timing parameter in multiples of DDR clock period"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "DSIPHY_CFG5,Reset Done Bits"
|
|
bitfld.long 0x00 31. " RESETDONETXBYTECLK ,RESETDONETXBYTECLK" "Normal,Reset"
|
|
bitfld.long 0x00 30. " RESETDONESCPCLK ,RESETDONESCPCLK" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 29. " RESETDONEPWRCLK ,RESETDONEPWRCLK" "Normal,Reset"
|
|
bitfld.long 0x00 28. " RESETDONETXCLKESC0 ,RESETDONETXCLKESC0" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 27. " RESETDONETXCLKESC1 ,RESETDONETXCLKESC1" "Normal,Reset"
|
|
bitfld.long 0x00 26. " RESETDONETXCLKESC2 ,RESETDONETXCLKESC2" "Normal,Reset"
|
|
width 0xb
|
|
tree.end
|
|
tree "PLL Control Module Registers"
|
|
base ad:0x4804FF00
|
|
width 24.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "DSI_PLL_CONTROL,This Register Controls The PLL Reset/Power And Modes"
|
|
bitfld.long 0x00 4. " DSI_HSDIV_SYSRESET ,Force HSDIVIDER SYSRESET" "Controlled by FSM,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSI_PLL_SYSRESET ,Force ADPLLV2 SYSRESET" "Controlled by FSM,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DSI_PLL_HALTMODE ,Allow PLL to be halted if no activity" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DSI_PLL_GATEMODE ,Allow PLL clock gating for poser saving" "On,Gated"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DSI_PLL_AUTOMODE ,Automatic update mode" "Manual,Automatic"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "DSI_PLL_STATUS,This Register Contains The Status Information"
|
|
bitfld.long 0x00 9. " DSI_BYPASSACKZ ,State of bypass mode on PHY and HSDIVIDER" "Switched,In use"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DSIPROTO_CLOCK_ACK ,Acknowledge for enable of DSI Protcol Engine clock" "Active,Not active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DSS_CLOCK_ACK ,Acknowledge for enable of DSS clock" "Active,Not active"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DSI_PLL_BYPASS ,DSI PLL Bypass status" "Not bypassing,Bypass"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DSI_PLL_HIGHJITTER ,DSI PLL High Jitter status" "Normal,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DSI_PLL_LIMP ,DSI PLL Limp status" "Active,Not active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSI_PLL_LOSSREF ,DSI PLL Reference Loss status" "Active,Not active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DSI_PLL_RECAL ,DSI PLL re-calibration status" "Not required,Required"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DSI_PLL_LOCK ,DSI PLL Lock status" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DSI_PLLCTRL_RESET_DONE ,DSI PLL Controller reset done status" "In progress,Completed"
|
|
group.long 0x08++0xB
|
|
line.long 0x00 "DSI_PLL_GO,This register contains the GO bit"
|
|
bitfld.long 0x00 0. " DSI_PLL_GO ,Request (re-)locking sequence of the PLL" "Not pending,Pending"
|
|
line.long 0x04 "DSI_PLL_CONFIGURATION1,Latched PLL And HSDIVDER Configuration Bits"
|
|
bitfld.long 0x04 23.--26. " DSIPROTO_CLOCK_DIV ,Divider value for DSI Protocol Engine clock source M4REG" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x04 19.--22. " DSS_CLOCK_DIV ,Divider value for DSS clock source M3REG" "0,1,?..."
|
|
textline " "
|
|
hexmask.long.word 0x04 8.--18. 1. " DSI_PLL_REGM ,M Divider for PLL"
|
|
textline " "
|
|
hexmask.long.byte 0x04 1.--7. 1. " DSI_PLL_REGN ,N Divider for PLL"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DSI_PLL_STOPMODE ,DSI PLL STOPMODE" "Not selected,Selected"
|
|
line.long 0x08 "DSI_PLL_CONFIGURATION2,Unlatched PLL And HSDIVDER Configuration Bits"
|
|
bitfld.long 0x08 20. " DSI_HSDIVBYPASS ,Forces HSDIVIDER to bypass mode" "Normal,Forced to bypass"
|
|
textline " "
|
|
bitfld.long 0x08 19. " DSI_PROTO_CLOCK_PWDN ,Power down for DSI Protocol Engine clock source" "Active,Powered-down"
|
|
textline " "
|
|
bitfld.long 0x08 18. " DSI_PROTO_CLOCK_EN ,Enable for DSI Protocol Engine clock source" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " DSS_CLOCK_PWDN ,Power down for DSS clock source" "Active,Powered-down"
|
|
textline " "
|
|
bitfld.long 0x08 16. " DSS_CLOCK_EN ,Enable for DSS clock source" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " DSI_BYPASSEN ,Selects DSS functional clock as DSIPHY clock source" "PLL DCO,Force DSS functional clk"
|
|
textline " "
|
|
bitfld.long 0x08 14. " DSIPHY_CLKINEN ,DSIPHY clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " DSI_PLL_REFEN ,PLL reference clock control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12. " DSI_PLL_HIGHFREQ ,Enables a division of pixel clock by 2 before input to the PLL" "Not divided,/2"
|
|
textline " "
|
|
bitfld.long 0x08 11. " DSI_PLL_CLKSEL ,Reference clock selection" "DSS2_ALWON_FCLK,Pixel Clock"
|
|
textline " "
|
|
bitfld.long 0x08 9.--10. " DSI_PLL_LOCKSEL ,Selects the lock criteria for the PLL" "Phase Lock,Frequency Lock,Spare,?..."
|
|
textline " "
|
|
bitfld.long 0x08 8. " DSI_PLL_DRIFTGUARDEN ,DSI PLL DRIFTGUARDEN" "Only RECAL flag,Automatic recalibration"
|
|
textline " "
|
|
bitfld.long 0x08 7. " DSI_PLL_TIGHTPHASELOCK ,DSI PLL Phase Lock criteria" "Normal,Tightenened"
|
|
textline " "
|
|
bitfld.long 0x08 6. " DSI_PLL_LOWCURRSTBY ,PLL LOW CURRENT STANDBY" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x08 5. " DSI_PLL_PLLLPMODE ,Select the power / performance of the PLL" "Full/minimised,Reduced/increased"
|
|
textline " "
|
|
bitfld.long 0x08 1.--4. " DSI_PLL_FREQSEL ,PLL internal reference frequency range selection" "Reserved,Reserved,Reserved,0.75MHz-1.0MHz,1.0MHz-1.25MHz,1.25MHz-1.5MHz,1.5MHz-1.75MHz,1.75MHz-2.1MHz,Reserved,Reserved,Reserved,7.5MHz-10MHz,10MHz-12.5MHz,12.5MHz-15MHz,15MHz-17.5MHz,17.5MHz-21MHz"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DSI_PLL_IDLE ,DSI PLL IDLE" "Not selected,Selected"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree.open "Timers"
|
|
tree "GPT"
|
|
tree "GPTIMER1"
|
|
base ad:0x48318000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 9. " W_PEND_TOWR ,Write pending for register TOWR" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " W_PEND_TOCR ,Write pending for register TOCR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " W_PEND_TCVR ,Write pending for register TCVR" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " W_PEND_TNIR ,Write pending for register TNIR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " W_PEND_TPIR ,Write pending for register TPIR" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
group.long 0x48++0x13
|
|
line.long 0x00 "TPIR,Timer Positive Increment Register"
|
|
line.long 0x04 "TNIR,GP Timer Negative Increment Register"
|
|
line.long 0x08 "TCVR,GP Timer Counter Value Register"
|
|
line.long 0x0c "TOCR,GP Timer Overflow Counter Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " OVF_COUNTER_VALUE ,The number of overflow events"
|
|
line.long 0x10 "TOWR,GP Timer Overflow Wrapping Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " OVF_WRAPPING_VALUE ,The number of masked interrupts"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER2"
|
|
base ad:0x49032000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 9. " W_PEND_TOWR ,Write pending for register TOWR" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " W_PEND_TOCR ,Write pending for register TOCR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " W_PEND_TCVR ,Write pending for register TCVR" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " W_PEND_TNIR ,Write pending for register TNIR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " W_PEND_TPIR ,Write pending for register TPIR" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
group.long 0x48++0x13
|
|
line.long 0x00 "TPIR,Timer Positive Increment Register"
|
|
line.long 0x04 "TNIR,GP Timer Negative Increment Register"
|
|
line.long 0x08 "TCVR,GP Timer Counter Value Register"
|
|
line.long 0x0c "TOCR,GP Timer Overflow Counter Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " OVF_COUNTER_VALUE ,The number of overflow events"
|
|
line.long 0x10 "TOWR,GP Timer Overflow Wrapping Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " OVF_WRAPPING_VALUE ,The number of masked interrupts"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER3"
|
|
base ad:0x49034000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER4"
|
|
base ad:0x49036000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER5"
|
|
base ad:0x49038000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER6"
|
|
base ad:0x4903A000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER7"
|
|
base ad:0x4903C000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER8"
|
|
base ad:0x4903E000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER9"
|
|
base ad:0x49040000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER10"
|
|
base ad:0x48086000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 9. " W_PEND_TOWR ,Write pending for register TOWR" "Not pending,Pending"
|
|
bitfld.long 0x00 8. " W_PEND_TOCR ,Write pending for register TOCR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 7. " W_PEND_TCVR ,Write pending for register TCVR" "Not pending,Pending"
|
|
bitfld.long 0x00 6. " W_PEND_TNIR ,Write pending for register TNIR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 5. " W_PEND_TPIR ,Write pending for register TPIR" "Not pending,Pending"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
group.long 0x48++0x13
|
|
line.long 0x00 "TPIR,Timer Positive Increment Register"
|
|
line.long 0x04 "TNIR,GP Timer Negative Increment Register"
|
|
line.long 0x08 "TCVR,GP Timer Counter Value Register"
|
|
line.long 0x0c "TOCR,GP Timer Overflow Counter Register"
|
|
hexmask.long.tbyte 0x0C 0.--23. 1. " OVF_COUNTER_VALUE ,The number of overflow events"
|
|
line.long 0x10 "TOWR,GP Timer Overflow Wrapping Register"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. " OVF_WRAPPING_VALUE ,The number of masked interrupts"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER11"
|
|
base ad:0x48088000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree "GPTIMER12"
|
|
base ad:0x48304000
|
|
width 11.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIOCP_CFG,GP Timer L4 Interface Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wakeup mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature global control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal L4 interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "TISTAT,GP Timer System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x1b
|
|
line.long 0x00 "TISR,GP Timer Interrupt Status Register"
|
|
eventfld.long 0x00 2. " TCAR_IT_FLAG ,Pending capture interrupt status" "Not pending,Pending"
|
|
eventfld.long 0x00 1. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 0. " MAT_IT_FLAG ,Pending match interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "TIER,GP Timer Interrupt Enable Register"
|
|
bitfld.long 0x04 2. " TCAR_IT_ENA ,Enable capture interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MAT_IT_ENA ,Enable match interrupt" "Disabled,Enabled"
|
|
line.long 0x08 "TWER,GP Timer Wake-Up Enable Register"
|
|
bitfld.long 0x08 2. " TCAR_WUP_ENA ,Enable capture wake-up" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OVF_WUP_ENA ,Enable overflow wake-up" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MAT_WUP_ENA ,Enable match wake-up" "Disabled,Enabled"
|
|
line.long 0x0c "TCLR,GP Timer Control Register"
|
|
bitfld.long 0x0c 14. " GPO_CFG ,PWM output/event detection input pin direction contro" "Output,Input"
|
|
bitfld.long 0x0c 13. " CAPT_MODE ,Capture mode select" "First,Second"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " PT ,Pulse or toggle select" "Pulse,Toggle"
|
|
bitfld.long 0x0c 10.--11. " TRG ,Trigger output mode" "No trigger,Overflow,Overflow/Match,?..."
|
|
textline " "
|
|
bitfld.long 0x0c 8.--9. " TCM ,Transition capture mode" "No capture,Rising edge,Falling edge,Both"
|
|
bitfld.long 0x0c 7. " SCPWM ,Pulse-width-modulation output pin setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " CE ,Compare enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 2.--4. " PTV ,Trigger output mode" "2,4,8,16,32,64,128,256"
|
|
bitfld.long 0x0c 1. " AR ,Autoreload mode" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " ST ,Start/stop timer control" "Stopped,Running"
|
|
line.long 0x10 "TCRR,Timer Counter Register"
|
|
line.long 0x14 "TLDR,GP Timer Load Register"
|
|
line.long 0x18 "TTGR,Timer Trigger Register"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "TWPS,Timer Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for register TMAR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for register TTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for register TLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for register TCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for register TCLR" "Not pending,Pending"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TMAR,GP Timer Match Value Register"
|
|
rgroup.long 0x3c++0x3
|
|
line.long 0x00 "TCAR1,GP Timer Counter 1 Capture Register"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TSICR,GP Timer L4 Interface Synchronization Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode selection" "Non-posted,Posted"
|
|
bitfld.long 0x00 1. " SFT ,Reset software functional registers" "No effect,Reset"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "TCAR2,GP Timer Counter 2 Capture Register"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree "WDT"
|
|
tree "WDT1"
|
|
base ad:0x4830c000
|
|
width 14.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "WD_SYSCONFIG,Watchdog System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity selection " "Cut off,At least L4,At least timer,Both"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode selection" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Enable wakeup control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,L4 interconnect clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "WD_SYSSTATUS,Watchdog System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "WISR,Watchdog Interrupt Event Pending"
|
|
eventfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "WIER,Watchdog Overflow Interrupt Control Register"
|
|
bitfld.long 0x04 0. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
group.long 0x24++0xf
|
|
line.long 0x00 "WCLR,Watchdog Control Register"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " PTV ,Prescaler value" "2,4,8,16,32,64,128,256"
|
|
line.long 0x04 "WCRR,Watchdog Counter Register"
|
|
line.long 0x08 "WLDR,Watchdog Load Register"
|
|
line.long 0x0c "WTGR,Watchdog Trigger Register"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "WWPS,Watchdog Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR" "Not pending,Pending"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "WSPR,Watchdog Start/Stop Register"
|
|
width 11.
|
|
tree.end
|
|
tree "WDT2"
|
|
base ad:0x48314000
|
|
width 14.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "WD_SYSCONFIG,Watchdog System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity selection " "Cut off,At least L4,At least timer,Both"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode selection" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Enable wakeup control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,L4 interconnect clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "WD_SYSSTATUS,Watchdog System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "WISR,Watchdog Interrupt Event Pending"
|
|
eventfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "WIER,Watchdog Overflow Interrupt Control Register"
|
|
bitfld.long 0x04 0. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
group.long 0x24++0xf
|
|
line.long 0x00 "WCLR,Watchdog Control Register"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " PTV ,Prescaler value" "2,4,8,16,32,64,128,256"
|
|
line.long 0x04 "WCRR,Watchdog Counter Register"
|
|
line.long 0x08 "WLDR,Watchdog Load Register"
|
|
line.long 0x0c "WTGR,Watchdog Trigger Register"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "WWPS,Watchdog Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR" "Not pending,Pending"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "WSPR,Watchdog Start/Stop Register"
|
|
width 11.
|
|
tree.end
|
|
tree "WDT3"
|
|
base ad:0x49030000
|
|
width 14.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "WD_SYSCONFIG,Watchdog System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity selection " "Cut off,At least L4,At least timer,Both"
|
|
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode selection" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Enable wakeup control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,L4 interconnect clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "WD_SYSSTATUS,Watchdog System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "WISR,Watchdog Interrupt Event Pending"
|
|
eventfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
|
|
line.long 0x04 "WIER,Watchdog Overflow Interrupt Control Register"
|
|
bitfld.long 0x04 0. " OVF_IT_ENA ,Enable overflow interrupt" "Disabled,Enabled"
|
|
group.long 0x24++0xf
|
|
line.long 0x00 "WCLR,Watchdog Control Register"
|
|
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " PTV ,Prescaler value" "2,4,8,16,32,64,128,256"
|
|
line.long 0x04 "WCRR,Watchdog Counter Register"
|
|
line.long 0x08 "WLDR,Watchdog Load Register"
|
|
line.long 0x0c "WTGR,Watchdog Trigger Register"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "WWPS,Watchdog Write-Posted Status Register"
|
|
bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR" "Not pending,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR" "Not pending,Pending"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "WSPR,Watchdog Start/Stop Register"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree "32-kHz Sync"
|
|
base ad:0x48320000
|
|
width 25.
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "REG_32KSYNCNT_SYSCONFIG,This Register Is Used For IDLE Modes Only"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management REQ/ACK control" "Force idle,No-idle,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "REG_32KSYNCNT_CR,Read Counter Register"
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree.open "UART/IrDA/CIR"
|
|
tree "UART1"
|
|
base ad:0x4806a000
|
|
width 17.
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "LCR_REG,Line Control Register"
|
|
bitfld.word 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " BREAK_EN ,Break control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " PARITY_TYPE2 ,Parity type" "0,1"
|
|
bitfld.word 0x00 04. " PARITY_TYPE1 ,Parity type" "Odd,Even"
|
|
textline " "
|
|
bitfld.word 0x00 03. " PARITY_EN ,Enable parity" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " NB_STOP ,Number of stop bits" "1 bit,1.5/1-2"
|
|
textline " "
|
|
bitfld.word 0x00 00.--01. " CHAR_LENGTH ,Byte length" "5 bit,6 bit,7 bit,8 bit"
|
|
if ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x4806a000+0x08)))&0x10)==0x0)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x0
|
|
width 17.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR_REG,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1_REG,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2_REG,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "XOFF1_REG,8-bit XOFF1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD1 ,8-bit XOFF1 character"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "XOFF2_REG,8-bit XOFF2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD2 ,8-bit XOFF2 character"
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x4806a000+0x08)))&0x10)==0x10)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x1
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR_REG,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1_REG,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2_REG,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
width 17.
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4806a000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4806a000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4806a000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
;uart
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4806a000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
;IrDA
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806a000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
;uart
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806a000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
;IrDA
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
;OPERATIONAL
|
|
width 17.
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806a000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,_REGBOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x4806a000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif (((d.w((ad:0x4806a000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x40&&((d.w((ad:0x4806a000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif (((d.w((ad:0x4806a000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x40&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif (((d.w((ad:0x4806a000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4806a000+0x10)))&0x40)==0x40&&((d.w((ad:0x4806a000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
else
|
|
textline " "
|
|
group.long 0x00++0x3
|
|
textline "Please choose appropriate UART/IrDA/CIR mode"
|
|
endif
|
|
width 17.
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "MDR1_REG,Mode Definition Register 1"
|
|
bitfld.word 0x00 07. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.word 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,Reserved,UART 16x autobaud,UART 13x,Reserved,Reserved,Reserved,Disabled"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "MDR2_REG,Mode Definition Register 2 (IrDA mode only)"
|
|
bitfld.word 0x00 03. " UART_PULSE ,Pulse shaping mode" "Disabled,Enabled"
|
|
hgroup.word 0x28++0x1
|
|
hide.word 0x00 "SFLSR/TXFLL_REG,Status FIFO Line Status Register (read) / Transmit Frame Length Low Register (write)"
|
|
hgroup.word 0x2c++0x1
|
|
hide.word 0x00 "RESUME/TXFLH_REG,Resume register (read) / Transmit Frame Length High Register (write)"
|
|
hgroup.word 0x30++0x1
|
|
hide.word 0x00 "SFREGL/RXFLL_REG,Status FIFO Register Low (read) / Received Frame Length Low Register (write)"
|
|
hgroup.word 0x34++0x1
|
|
hide.word 0x00 "SFREGH/RXFLH_REG,Status FIFO Register High (read) / Received Frame Length High Register (write)"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "SCR_REG,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
rgroup.word 0x44++0x1
|
|
line.word 0x00 "SSR_REG,Supplementary Status Register"
|
|
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX CTS or DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO" "Not full,Full"
|
|
rgroup.word 0x50++0x1
|
|
line.word 0x00 "MVR_REG,Module Version Register"
|
|
hexmask.word 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
|
|
hexmask.word 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
|
|
group.word 0x54++0x1
|
|
line.word 0x00 "SYSC_REG,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
group.word 0x58++0x1
|
|
line.word 0x00 "SYSS_REG,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x1
|
|
line.word 0x00 "WER_REG,Wake-Up Enable Register"
|
|
bitfld.word 0x00 6. " EVENT_6_RLS_INTERRUPT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EVENT_5_RLS_INTERRUPT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EVENT_4_RLS_INTERRUPT ,RX/RXIR activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " EVENT_2_RLS_INTERRUPT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EVENT_0_RLS_INTERRUPT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
hgroup.word 0x60++0x1
|
|
hide.word 0x00 "CFPS_REG,Carrier Frequency Prescaler"
|
|
width 11.
|
|
tree.end
|
|
tree "UART2"
|
|
base ad:0x4806c000
|
|
width 17.
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "LCR_REG,Line Control Register"
|
|
bitfld.word 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " BREAK_EN ,Break control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " PARITY_TYPE2 ,Parity type" "0,1"
|
|
bitfld.word 0x00 04. " PARITY_TYPE1 ,Parity type" "Odd,Even"
|
|
textline " "
|
|
bitfld.word 0x00 03. " PARITY_EN ,Enable parity" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " NB_STOP ,Number of stop bits" "1 bit,1.5/1-2"
|
|
textline " "
|
|
bitfld.word 0x00 00.--01. " CHAR_LENGTH ,Byte length" "5 bit,6 bit,7 bit,8 bit"
|
|
if ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x4806c000+0x08)))&0x10)==0x0)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x0
|
|
width 17.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR_REG,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1_REG,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2_REG,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "XOFF1_REG,8-bit XOFF1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD1 ,8-bit XOFF1 character"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "XOFF2_REG,8-bit XOFF2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD2 ,8-bit XOFF2 character"
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x4806c000+0x08)))&0x10)==0x10)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x1
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR_REG,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1_REG,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2_REG,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
width 17.
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4806c000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4806c000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4806c000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
;uart
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x4806c000+0x10)))&0x40)==0x40)&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
;IrDA
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806c000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
;uart
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x4806c000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
;IrDA
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
;OPERATIONAL
|
|
width 17.
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806c000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR,_REGBOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x4806c000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x00&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif (((d.w((ad:0x4806c000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x40&&((d.w((ad:0x4806c000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif (((d.w((ad:0x4806c000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x40&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif (((d.w((ad:0x4806c000+0x0c)))&0x80)==0x00&&((d.w((ad:0x4806c000+0x10)))&0x40)==0x40&&((d.w((ad:0x4806c000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
else
|
|
textline " "
|
|
group.long 0x00++0x3
|
|
textline "Please choose appropriate UART/IrDA/CIR mode"
|
|
endif
|
|
width 17.
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "MDR1_REG,Mode Definition Register 1"
|
|
bitfld.word 0x00 07. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.word 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,Reserved,UART 16x autobaud,UART 13x,Reserved,Reserved,Reserved,Disabled"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "MDR2_REG,Mode Definition Register 2 (IrDA mode only)"
|
|
bitfld.word 0x00 03. " UART_PULSE ,Pulse shaping mode" "Disabled,Enabled"
|
|
hgroup.word 0x28++0x1
|
|
hide.word 0x00 "SFLSR/TXFLL_REG,Status FIFO Line Status Register (read) / Transmit Frame Length Low Register (write)"
|
|
hgroup.word 0x2c++0x1
|
|
hide.word 0x00 "RESUME/TXFLH_REG,Resume register (read) / Transmit Frame Length High Register (write)"
|
|
hgroup.word 0x30++0x1
|
|
hide.word 0x00 "SFREGL/RXFLL_REG,Status FIFO Register Low (read) / Received Frame Length Low Register (write)"
|
|
hgroup.word 0x34++0x1
|
|
hide.word 0x00 "SFREGH/RXFLH_REG,Status FIFO Register High (read) / Received Frame Length High Register (write)"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "SCR_REG,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
rgroup.word 0x44++0x1
|
|
line.word 0x00 "SSR_REG,Supplementary Status Register"
|
|
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX CTS or DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO" "Not full,Full"
|
|
rgroup.word 0x50++0x1
|
|
line.word 0x00 "MVR_REG,Module Version Register"
|
|
hexmask.word 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
|
|
hexmask.word 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
|
|
group.word 0x54++0x1
|
|
line.word 0x00 "SYSC_REG,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
group.word 0x58++0x1
|
|
line.word 0x00 "SYSS_REG,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x1
|
|
line.word 0x00 "WER_REG,Wake-Up Enable Register"
|
|
bitfld.word 0x00 6. " EVENT_6_RLS_INTERRUPT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EVENT_5_RLS_INTERRUPT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EVENT_4_RLS_INTERRUPT ,RX/RXIR activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " EVENT_2_RLS_INTERRUPT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EVENT_0_RLS_INTERRUPT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
hgroup.word 0x60++0x1
|
|
hide.word 0x00 "CFPS_REG,Carrier Frequency Prescaler"
|
|
width 11.
|
|
tree.end
|
|
tree "UART3/IrDA/CIR"
|
|
base ad:0x49020000
|
|
width 17.
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "LCR_REG,Line Control Register"
|
|
bitfld.word 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " BREAK_EN ,Break control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " PARITY_TYPE2 ,Parity type" "0,1"
|
|
bitfld.word 0x00 04. " PARITY_TYPE1 ,Parity type" "Odd,Even"
|
|
textline " "
|
|
bitfld.word 0x00 03. " PARITY_EN ,Enable parity" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " NB_STOP ,Number of stop bits" "1 bit,1.5/1-2"
|
|
textline " "
|
|
bitfld.word 0x00 00.--01. " CHAR_LENGTH ,Byte length" "5 bit,6 bit,7 bit,8 bit"
|
|
if ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x49020000+0x08)))&0x10)==0x0)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x0
|
|
width 17.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR_REG,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1_REG,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2_REG,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "XOFF1_REG,8-bit XOFF1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD1 ,8-bit XOFF1 character"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "XOFF2_REG,8-bit XOFF2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XOFF_WORD2 ,8-bit XOFF2 character"
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)==0xbf)&&((d.w((ad:0x49020000+0x08)))&0x10)==0x10)
|
|
;MODE B(LCR [7:0]==0xBF) && EFR[4]==0x1
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "EFR_REG,Enhanced Feature Register"
|
|
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " SW_FLOW_CONTROL ,Software flow control selection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "XON1_ADDR1_REG,XON1_ADDR1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD1 ,XON1 character"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "XON2_ADDR2_REG,XON2_ADDR2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " XON_WORD2 ,XON2 character"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
width 17.
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x49020000+0x10)))&0x40)==0x40)&&((d.w((ad:0x49020000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
;cir
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
;cir
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x49020000+0x10)))&0x40)==0x40)&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
;uart
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x49020000+0x10)))&0x40)==0x40)&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
;IrDA
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FUL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x49020000+0x10)))&0x40)==0x00&&((d.w((ad:0x49020000+0x20)))&0x7)==0x6)
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
;cir
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x49020000+0x10)))&0x40)==0x00&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
|
|
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "No identified,115 200 baud,57 600 baud,38 400 baud,28 800 baud,19 200 baud,14 400 baud,9 600 baud,4 800 baud,4 800 baud,1 200 baud,?..."
|
|
;uart
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x80)&&(((d.w((ad:0x49020000+0x0c)))&0xff)!=0xbf)&&((d.w((ad:0x49020000+0x10)))&0x40)==0x00&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;MODEA(LCR[7]==0x1 && LCR[7:0]!=0xBF) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DLL_REG,Divisor Latch LSB Value Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit6 LSB divisor value"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "DLH_REG,Divisor Latch MSB Value Register"
|
|
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
;IrDA
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "UASR_REG,UART Autobauding Status"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FUL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
;OPERATIONAL
|
|
width 17.
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x49020000+0x10)))&0x40)==0x00&&((d.w((ad:0x49020000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
group.word 0x3c++0x1
|
|
line.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled start" "Not started,Started"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort" "Not aborted,Aborted"
|
|
bitfld.word 0x00 0. " OET_EN ,End of transmission" "Not occurred,Occurred"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "EBLR_REG,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,EBLR"
|
|
;cir
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x49020000+0x10)))&0x40)==0x00&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
;uart
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif ((((d.w((ad:0x49020000+0x0c)))&0x80)==0x00)&&((d.w((ad:0x49020000+0x10)))&0x40)==0x00&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x0 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "BLR_REG,BOF Control Register"
|
|
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
group.word 0x3c++0x1
|
|
line.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled start" "Not started,Started"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort" "Not aborted,Aborted"
|
|
bitfld.word 0x00 0. " OET_EN ,End of transmission" "Not occurred,Occurred"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "EBLR_REG,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,EBLR"
|
|
;IrDA
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " LINE_STS_IT_I ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FUL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "MSR_REG,Modem Status Register"
|
|
bitfld.word 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.word 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.word 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.word 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.word 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.word 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPR_REG,Scratchpad Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif (((d.w((ad:0x49020000+0x0c)))&0x80)==0x00&&((d.w((ad:0x49020000+0x10)))&0x40)==0x40&&((d.w((ad:0x49020000+0x20)))&0x7)==0x6)
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && cir mode(MDR1[2:0]==0x6)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
group.word 0x3c++0x1
|
|
line.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled start" "Not started,Started"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort" "Not aborted,Aborted"
|
|
bitfld.word 0x00 0. " OET_EN ,End of transmission" "Not occurred,Occurred"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "EBLR_REG,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,EBLR"
|
|
;cir
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif (((d.w((ad:0x49020000+0x0c)))&0x80)==0x00&&((d.w((ad:0x49020000+0x10)))&0x40)==0x40&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x2||0x3||0x0))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && uart(MDR1[2:0]==(0x2||0x3||0x0))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
hgroup.word 0x38++0x1
|
|
hide.word 0x00 "BLR_REG,BOF Control Register"
|
|
hgroup.word 0x3c++0x1
|
|
hide.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "EBLR_REG,BOF Length Register"
|
|
;uart
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
|
|
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,CTS/RTS inactive,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
|
|
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif (((d.w((ad:0x49020000+0x0c)))&0x80)==0x00&&((d.w((ad:0x49020000+0x10)))&0x40)==0x40&&((d.w((ad:0x49020000+0x20)))&0x7)==(0x1||0x4||0x5))
|
|
;OPERATIONAL(LCR[7]==0x0) && MCR[6]==0x1 && IrDA(MDR1[2:0]==(0x1||0x4||0x5))
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "RHR/THR_REG,Receive/Transmit Holding Register"
|
|
in
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "BLR_REG,BOF Control Register"
|
|
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
group.word 0x3c++0x1
|
|
line.word 0x00 "ACREG_REG,Auxiliary Control Register"
|
|
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disabled" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse" "No action,Sent"
|
|
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled start" "Not started,Started"
|
|
textline " "
|
|
bitfld.word 0x00 1. " ABORT_EN ,Frame abort" "Not aborted,Aborted"
|
|
bitfld.word 0x00 0. " OET_EN ,End of transmission" "Not occurred,Occurred"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "EBLR_REG,BOF Length Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,EBLR"
|
|
;IrDA
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "IER_REG,Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " LINE_STS_IT_I ,Receiver line status interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IIR/FCR_REG,Interrupt Identification Register"
|
|
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
|
|
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "MCR_REG,Modem Control Register"
|
|
bitfld.word 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.word 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.word 0x00 00. " DTR ,Force DTR output" "High,Low"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "LSR_REG,Line Status Register"
|
|
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
|
|
bitfld.word 0x00 6. " STS_FIFO_FUL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
|
|
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
|
|
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TCR_REG,Transmission Control Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TLR_REG,Trigger Level Register"
|
|
bitfld.word 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.word 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
else
|
|
textline " "
|
|
group.long 0x00++0x3
|
|
textline "Please choose appropriate UART/IrDA/CIR mode"
|
|
endif
|
|
width 17.
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "MDR1_REG,Mode Definition Register 1"
|
|
bitfld.word 0x00 07. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic"
|
|
textline " "
|
|
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
|
|
bitfld.word 0x00 4. " SET_TXIR ,IRTX pin output forced high" "No effect,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IR_SLEEP ,IrDA/CIR sleep mode enabled" "Disabled,Enabled"
|
|
bitfld.word 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
|
|
group.word 0x0024++0x1
|
|
line.word 0x00 "MDR2_REG,Mode Definition Register 2 (IrDA mode only)"
|
|
bitfld.word 0x00 6. " IRRXINVERT ,No inversion performed" "Inversion,No inversion"
|
|
bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles"
|
|
textline " "
|
|
bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse"
|
|
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
textline " "
|
|
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "SFLSR/TXFLL_REG,Status FIFO Line Status Register (read) / Transmit Frame Length Low Register (write) (IrDA mode only)"
|
|
bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error"
|
|
bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected"
|
|
bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error"
|
|
group.word 0x2c++0x1
|
|
line.word 0x00 "RESUME/TXFLH_REG,Resume register (read) / Transmit Frame Length High Register (write) (IrDA mode only)"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "SFREGL/RXFLL_REG,Status FIFO Register Low (read) / Received Frame Length Low Register (write) (IrDA mode only)"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SFREGL/RXFLL ,LSB part of the frame length"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "SFREGH/RXFLH_REG,Status FIFO Register High (read) / Received Frame Length High Register (write) (IrDA mode only)"
|
|
bitfld.word 0x00 0.--3. " SFREGH/RXFLH ,MSB part of frame length (read) / Frame length high (write)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "SCR_REG,Supplementary Control Register"
|
|
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
|
|
rgroup.word 0x44++0x1
|
|
line.word 0x00 "SSR_REG,Supplementary Status Register"
|
|
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX CTS or DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO" "Not full,Full"
|
|
rgroup.word 0x50++0x1
|
|
line.word 0x00 "MVR_REG,Module Version Register"
|
|
hexmask.word 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
|
|
hexmask.word 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
|
|
group.word 0x54++0x1
|
|
line.word 0x00 "SYSC_REG,System Configuration Register"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
|
|
group.word 0x58++0x1
|
|
line.word 0x00 "SYSS_REG,System Status Register"
|
|
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x5c++0x1
|
|
line.word 0x00 "WER_REG,Wake-Up Enable Register"
|
|
bitfld.word 0x00 6. " EVENT_6_RLS_INTERRUPT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EVENT_5_RLS_INTERRUPT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EVENT_4_RLS_INTERRUPT ,RX/RXIR activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 2. " EVENT_2_RLS_INTERRUPT ,RI activity allowed to wake up system" "Not allowed,Allowed"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EVENT_0_RLS_INTERRUPT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
|
|
group.word 0x60++0x1
|
|
line.word 0x00 "CFPS_REG,Carrier Frequency Prescaler (CIR mode only)"
|
|
hexmask.word 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree.open "High-Speed I2C Controller"
|
|
tree "I2C1"
|
|
base ad:0x48070000
|
|
width 13.
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "I2C_IE,I2C Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " XDR_IE ,Transmit draining interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RDR_IE ,Receive draining interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " AAS_IE ,Addressed as slave interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BF_IE ,Bus free interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " AERR_IE ,Access error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " STC_IE ,Start condition interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " GC_IE ,General call interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " NACK_IE ,No acknowledgment interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_STAT,I2C Status Information About Module"
|
|
eventfld.word 0x00 14. " XDR ,Transmit draining IRQ status" "Inactive,Active"
|
|
eventfld.word 0x00 13. " RDR ,Receive draining IRQ status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BB ,Bus busy status" "Free,Occupied"
|
|
bitfld.word 0x00 11. " ROVR ,Receive overrun status" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow"
|
|
eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status" "No effect,Recognized"
|
|
textline " "
|
|
eventfld.word 0x00 8. " BF ,Bus free IRQ status" "No effect,Free"
|
|
eventfld.word 0x00 7. " AERR ,Access error IRQ status" "No effect,Error"
|
|
textline " "
|
|
eventfld.word 0x00 6. " STC ,Start condition IRQ status" "No effect,Detected"
|
|
eventfld.word 0x00 5. " GC ,General call IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not requested,Requested"
|
|
eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ status" "Not availabled,Availabled"
|
|
textline " "
|
|
eventfld.word 0x00 2. " ARDY ,Register access ready IRQ status" "Busy,Ready"
|
|
eventfld.word 0x00 1. " NACK ,No acknowledgment IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 0. " AL ,Arbitration lost IRQ status" "Not detected,Detected"
|
|
group.word 0x0c++0x01
|
|
line.word 0x00 "I2C_WE,I2C Wakeup Enable Register"
|
|
bitfld.word 0x00 14. " XDR_WE ,Transmit draining wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RDR_WE ,Receive draining wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " AAS_WE ,Address as slave wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BF_WE ,Bus free wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STC_WE ,Start condition wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " GC_WE ,General call wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DRDY_WE ,Transmit/receive data ready wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ARDY_WE ,Register access ready wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " NACK_WE ,No acknowledgment wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " AL_WE ,Arbitration lost wakeup enable" "Disabled,Enabled"
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "I2C_SYSS,I2C Status Information About Module"
|
|
bitfld.word 0x00 0. " RDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "I2C_BUF,I2C Buffer Configuration Register"
|
|
bitfld.word 0x00 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RXFIFO_CLR ,Receive FIFO clear" "No effect,Reset"
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--13. 1. " RTRSH ,Threshold value for FIFO buffer in RX mode"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TXFIFO_CLR ,Transmit FIFO clear" "No effect,Reset"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--5. 1. " XTRSH ,Threshold value for FIFO buffer in TX mode"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "I2C_CNT,I2C Data Count Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCOUNT ,Data count"
|
|
hgroup.word 0x1c++0x01
|
|
hide.word 0x00 "I2C_DATA,I2C Transmit/Receive FIFO data"
|
|
in
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2C_SYSC,I2C Parameters of the L4-Core Interconnect Interface"
|
|
bitfld.word 0x00 8.--9. " CLOCK_ACTIVITY ,Clock activity (interface/functional)" "Cut off,Active/Cut off,Cut off/Active,Active"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
textline " "
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Enable wakeup" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " SRST ,Software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Auto idle enable" "Disabled,Enabled"
|
|
if (((d.w((ad:0x48070000+0x24)))&0x400)==0x400)
|
|
;master mode
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_CON,I2C Control Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,Module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard,I2C High Speed,SCCB,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.word 0x00 11. " STB ,Start byte mode" "Normal,Start byte"
|
|
textline " "
|
|
bitfld.word 0x00 9. " TRX ,Transmitter/receiver mode" "Receiver,Transmitter"
|
|
bitfld.word 0x00 8. " XSA ,Expand slave address enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XOA0 ,Expand own address 0 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 6. " XOA1 ,Expand own address 1 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 5. " XOA2 ,Expand own address 2 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 4. " XOA3 ,Expand own address 3 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STP ,Stop condition" "No action/Detected,Queried"
|
|
bitfld.word 0x00 0. " STT ,Start condition" "No action/Detected,Queried"
|
|
else
|
|
;slave mode
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_CON,I2C Control Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,Module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard,I2C High Speed,SCCB,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.word 0x00 8. " XSA ,Expand slave address enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XOA0 ,Expand own address 0 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 6. " XOA1 ,Expand own address 1 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 5. " XOA2 ,Expand own address 2 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 4. " XOA3 ,Expand own address 3 enable" "7-bit,10-bit"
|
|
endif
|
|
if (((d.w((ad:0x48070000+0x24)))&0x80)==0x80)
|
|
;I2C_CON[7]= 10-bit
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "I2C_OA0,I2C Own Address 0"
|
|
bitfld.word 0x00 13.--15. " MCODE ,Master code value" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--9. 1. " OA ,Own address 0 value"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "I2C_OA0,I2C Own Address 0"
|
|
bitfld.word 0x00 13.--15. " MCODE ,Master code value" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA ,Own address 0 value"
|
|
endif
|
|
if (((d.w((ad:0x48070000+0x24)))&0x100)==0x100)
|
|
;I2C_CON[8]= 10-bit
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2C_SA,I2C Slave Address"
|
|
hexmask.word 0x00 0.--9. 1. " SA ,Slave address value"
|
|
else
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2C_SA,I2C Slave Address"
|
|
hexmask.word.byte 0x00 0.--6. 1. " SA ,Slave address value"
|
|
endif
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "I2C_PSC,I2C Prescale Sampling Clock Divider"
|
|
hexmask.word.byte 0x00 0.--7. 1. " PSC ,Fast/Standard and SCCB modes prescale sampling clock divider value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "I2C_SCLL,I2C SCL"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HSSCLL ,I2C High Speed mode SCL low time value"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SCLL ,I2C Fast/Standard or SCCB modes SCL low time value"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "I2C_SCLH,I2C SCLH"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HSSCLH ,I2C high-speed mode SCL high time value"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SCLH ,I2C Fast/Standard or SCCB modes SCL high time value"
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "I2C_SYSTEST,I2C System Test Register"
|
|
bitfld.word 0x00 15. " ST_EN ,System test enable" "No effect,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free-running mode" "Stopped,Free-running"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,SCL counters,Loop back/SDA/SCL IO"
|
|
bitfld.word 0x00 11. " SSB ,Set status" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SCCBE_O ,SCCBE line sense output value" "0,1"
|
|
bitfld.word 0x00 3. " SCL_I ,SCL line sense input value" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SCL_O ,SCL line drive output value" "0,1"
|
|
bitfld.word 0x00 1. " SDA_I ,SDA line sense input value" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 0. " SDA_O ,SDA line drive output value" "0,1"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "I2C_BUFSTAT,I2C FIFO Status Information"
|
|
bitfld.word 0x00 14.--15. " FIFODEPTH ,FIFO depth" "8-bytes,16-bytes,32-bytes,64-bytes"
|
|
hexmask.word.byte 0x00 8.--13. 1. " RXSTAT ,RX buffer status"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--5. 1. " TXSTAT ,TX buffer status"
|
|
if (((d.w((ad:0x48070000+0x24)))&0x40)==0x40)
|
|
;I2C_CON[6]= 10-bit
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "I2C_OA1,I2C Own Address 1"
|
|
hexmask.word 0x00 0.--9. 1. " OA1 ,Own address 1 value"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "I2C_OA1,I2C Own Address 1"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA1 ,Own address 1 value"
|
|
endif
|
|
if (((d.w((ad:0x48070000+0x24)))&0x20)==0x20)
|
|
;I2C_CON[5]= 10-bit
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2C_OA2,I2C Own Address 2"
|
|
hexmask.word 0x00 0.--9. 1. " OA2 ,Own address 2 value"
|
|
else
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2C_OA2,I2C Own Address 2"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA2 ,Own address 2 value"
|
|
endif
|
|
if (((d.w((ad:0x48070000+0x24)))&0x10)==0x10)
|
|
;I2C_CON[4]= 10-bit
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2C_OA3,I2C Own Address 3"
|
|
hexmask.word 0x00 0.--9. 1. " OA3 ,Own address 3 value"
|
|
else
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2C_OA3,I2C Own Address 3"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA3 ,Own address 3 value"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "I2C_ACTOA,I2C Accessed Slave Own Address Indicators"
|
|
bitfld.word 0x00 3. " OA3_ACT ,Own address 3 active" "Inactive,Active"
|
|
bitfld.word 0x00 2. " OA2_ACT ,Own address 2 active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OA1_ACT ,Own address 1 active" "Inactive,Active"
|
|
bitfld.word 0x00 0. " OA0_ACT ,Own address 0 active" "Inactive,Active"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "I2C_SBLOCK,I2C Slave Mode Bus Lock Features"
|
|
bitfld.word 0x00 3. " OA3_EN ,Enable I2C clock blocking for own address 3" "Released,Blocked"
|
|
bitfld.word 0x00 2. " OA2_EN ,Enable I2C clock blocking for own address 2" "Released,Blocked"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OA1_EN ,Enable I2C clock blocking for own address 1" "Released,Blocked"
|
|
bitfld.word 0x00 0. " OA0_EN ,Enable I2C clock blocking for own address 0" "Released,Blocked"
|
|
width 11.
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x48072000
|
|
width 13.
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "I2C_IE,I2C Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " XDR_IE ,Transmit draining interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RDR_IE ,Receive draining interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " AAS_IE ,Addressed as slave interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BF_IE ,Bus free interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " AERR_IE ,Access error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " STC_IE ,Start condition interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " GC_IE ,General call interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " NACK_IE ,No acknowledgment interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_STAT,I2C Status Information About Module"
|
|
eventfld.word 0x00 14. " XDR ,Transmit draining IRQ status" "Inactive,Active"
|
|
eventfld.word 0x00 13. " RDR ,Receive draining IRQ status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BB ,Bus busy status" "Free,Occupied"
|
|
bitfld.word 0x00 11. " ROVR ,Receive overrun status" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow"
|
|
eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status" "No effect,Recognized"
|
|
textline " "
|
|
eventfld.word 0x00 8. " BF ,Bus free IRQ status" "No effect,Free"
|
|
eventfld.word 0x00 7. " AERR ,Access error IRQ status" "No effect,Error"
|
|
textline " "
|
|
eventfld.word 0x00 6. " STC ,Start condition IRQ status" "No effect,Detected"
|
|
eventfld.word 0x00 5. " GC ,General call IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not requested,Requested"
|
|
eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ status" "Not availabled,Availabled"
|
|
textline " "
|
|
eventfld.word 0x00 2. " ARDY ,Register access ready IRQ status" "Busy,Ready"
|
|
eventfld.word 0x00 1. " NACK ,No acknowledgment IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 0. " AL ,Arbitration lost IRQ status" "Not detected,Detected"
|
|
group.word 0x0c++0x01
|
|
line.word 0x00 "I2C_WE,I2C Wakeup Enable Register"
|
|
bitfld.word 0x00 14. " XDR_WE ,Transmit draining wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RDR_WE ,Receive draining wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " AAS_WE ,Address as slave wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BF_WE ,Bus free wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STC_WE ,Start condition wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " GC_WE ,General call wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DRDY_WE ,Transmit/receive data ready wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ARDY_WE ,Register access ready wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " NACK_WE ,No acknowledgment wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " AL_WE ,Arbitration lost wakeup enable" "Disabled,Enabled"
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "I2C_SYSS,I2C Status Information About Module"
|
|
bitfld.word 0x00 0. " RDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "I2C_BUF,I2C Buffer Configuration Register"
|
|
bitfld.word 0x00 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RXFIFO_CLR ,Receive FIFO clear" "No effect,Reset"
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--13. 1. " RTRSH ,Threshold value for FIFO buffer in RX mode"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TXFIFO_CLR ,Transmit FIFO clear" "No effect,Reset"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--5. 1. " XTRSH ,Threshold value for FIFO buffer in TX mode"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "I2C_CNT,I2C Data Count Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCOUNT ,Data count"
|
|
hgroup.word 0x1c++0x01
|
|
hide.word 0x00 "I2C_DATA,I2C Transmit/Receive FIFO data"
|
|
in
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2C_SYSC,I2C Parameters of the L4-Core Interconnect Interface"
|
|
bitfld.word 0x00 8.--9. " CLOCK_ACTIVITY ,Clock activity (interface/functional)" "Cut off,Active/Cut off,Cut off/Active,Active"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
textline " "
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Enable wakeup" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " SRST ,Software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Auto idle enable" "Disabled,Enabled"
|
|
if (((d.w((ad:0x48072000+0x24)))&0x400)==0x400)
|
|
;master mode
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_CON,I2C Control Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,Module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard,I2C High Speed,SCCB,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.word 0x00 11. " STB ,Start byte mode" "Normal,Start byte"
|
|
textline " "
|
|
bitfld.word 0x00 9. " TRX ,Transmitter/receiver mode" "Receiver,Transmitter"
|
|
bitfld.word 0x00 8. " XSA ,Expand slave address enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XOA0 ,Expand own address 0 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 6. " XOA1 ,Expand own address 1 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 5. " XOA2 ,Expand own address 2 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 4. " XOA3 ,Expand own address 3 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STP ,Stop condition" "No action/Detected,Queried"
|
|
bitfld.word 0x00 0. " STT ,Start condition" "No action/Detected,Queried"
|
|
else
|
|
;slave mode
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_CON,I2C Control Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,Module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard,I2C High Speed,SCCB,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.word 0x00 8. " XSA ,Expand slave address enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XOA0 ,Expand own address 0 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 6. " XOA1 ,Expand own address 1 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 5. " XOA2 ,Expand own address 2 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 4. " XOA3 ,Expand own address 3 enable" "7-bit,10-bit"
|
|
endif
|
|
if (((d.w((ad:0x48072000+0x24)))&0x80)==0x80)
|
|
;I2C_CON[7]= 10-bit
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "I2C_OA0,I2C Own Address 0"
|
|
bitfld.word 0x00 13.--15. " MCODE ,Master code value" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--9. 1. " OA ,Own address 0 value"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "I2C_OA0,I2C Own Address 0"
|
|
bitfld.word 0x00 13.--15. " MCODE ,Master code value" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA ,Own address 0 value"
|
|
endif
|
|
if (((d.w((ad:0x48072000+0x24)))&0x100)==0x100)
|
|
;I2C_CON[8]= 10-bit
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2C_SA,I2C Slave Address"
|
|
hexmask.word 0x00 0.--9. 1. " SA ,Slave address value"
|
|
else
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2C_SA,I2C Slave Address"
|
|
hexmask.word.byte 0x00 0.--6. 1. " SA ,Slave address value"
|
|
endif
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "I2C_PSC,I2C Prescale Sampling Clock Divider"
|
|
hexmask.word.byte 0x00 0.--7. 1. " PSC ,Fast/Standard and SCCB modes prescale sampling clock divider value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "I2C_SCLL,I2C SCL"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HSSCLL ,I2C High Speed mode SCL low time value"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SCLL ,I2C Fast/Standard or SCCB modes SCL low time value"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "I2C_SCLH,I2C SCLH"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HSSCLH ,I2C high-speed mode SCL high time value"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SCLH ,I2C Fast/Standard or SCCB modes SCL high time value"
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "I2C_SYSTEST,I2C System Test Register"
|
|
bitfld.word 0x00 15. " ST_EN ,System test enable" "No effect,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free-running mode" "Stopped,Free-running"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,SCL counters,Loop back/SDA/SCL IO"
|
|
bitfld.word 0x00 11. " SSB ,Set status" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SCCBE_O ,SCCBE line sense output value" "0,1"
|
|
bitfld.word 0x00 3. " SCL_I ,SCL line sense input value" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SCL_O ,SCL line drive output value" "0,1"
|
|
bitfld.word 0x00 1. " SDA_I ,SDA line sense input value" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 0. " SDA_O ,SDA line drive output value" "0,1"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "I2C_BUFSTAT,I2C FIFO Status Information"
|
|
bitfld.word 0x00 14.--15. " FIFODEPTH ,FIFO depth" "8-bytes,16-bytes,32-bytes,64-bytes"
|
|
hexmask.word.byte 0x00 8.--13. 1. " RXSTAT ,RX buffer status"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--5. 1. " TXSTAT ,TX buffer status"
|
|
if (((d.w((ad:0x48072000+0x24)))&0x40)==0x40)
|
|
;I2C_CON[6]= 10-bit
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "I2C_OA1,I2C Own Address 1"
|
|
hexmask.word 0x00 0.--9. 1. " OA1 ,Own address 1 value"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "I2C_OA1,I2C Own Address 1"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA1 ,Own address 1 value"
|
|
endif
|
|
if (((d.w((ad:0x48072000+0x24)))&0x20)==0x20)
|
|
;I2C_CON[5]= 10-bit
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2C_OA2,I2C Own Address 2"
|
|
hexmask.word 0x00 0.--9. 1. " OA2 ,Own address 2 value"
|
|
else
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2C_OA2,I2C Own Address 2"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA2 ,Own address 2 value"
|
|
endif
|
|
if (((d.w((ad:0x48072000+0x24)))&0x10)==0x10)
|
|
;I2C_CON[4]= 10-bit
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2C_OA3,I2C Own Address 3"
|
|
hexmask.word 0x00 0.--9. 1. " OA3 ,Own address 3 value"
|
|
else
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2C_OA3,I2C Own Address 3"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA3 ,Own address 3 value"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "I2C_ACTOA,I2C Accessed Slave Own Address Indicators"
|
|
bitfld.word 0x00 3. " OA3_ACT ,Own address 3 active" "Inactive,Active"
|
|
bitfld.word 0x00 2. " OA2_ACT ,Own address 2 active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OA1_ACT ,Own address 1 active" "Inactive,Active"
|
|
bitfld.word 0x00 0. " OA0_ACT ,Own address 0 active" "Inactive,Active"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "I2C_SBLOCK,I2C Slave Mode Bus Lock Features"
|
|
bitfld.word 0x00 3. " OA3_EN ,Enable I2C clock blocking for own address 3" "Released,Blocked"
|
|
bitfld.word 0x00 2. " OA2_EN ,Enable I2C clock blocking for own address 2" "Released,Blocked"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OA1_EN ,Enable I2C clock blocking for own address 1" "Released,Blocked"
|
|
bitfld.word 0x00 0. " OA0_EN ,Enable I2C clock blocking for own address 0" "Released,Blocked"
|
|
width 11.
|
|
tree.end
|
|
tree "I2C3"
|
|
base ad:0x48060000
|
|
width 13.
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "I2C_IE,I2C Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " XDR_IE ,Transmit draining interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RDR_IE ,Receive draining interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " AAS_IE ,Addressed as slave interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BF_IE ,Bus free interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " AERR_IE ,Access error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " STC_IE ,Start condition interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " GC_IE ,General call interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XRDY_IE ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RRDY_IE ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ARDY_IE ,Register access ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " NACK_IE ,No acknowledgment interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " AL_IE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "I2C_STAT,I2C Status Information About Module"
|
|
eventfld.word 0x00 14. " XDR ,Transmit draining IRQ status" "Inactive,Active"
|
|
eventfld.word 0x00 13. " RDR ,Receive draining IRQ status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BB ,Bus busy status" "Free,Occupied"
|
|
bitfld.word 0x00 11. " ROVR ,Receive overrun status" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow"
|
|
eventfld.word 0x00 9. " AAS ,Address recognized as slave IRQ status" "No effect,Recognized"
|
|
textline " "
|
|
eventfld.word 0x00 8. " BF ,Bus free IRQ status" "No effect,Free"
|
|
eventfld.word 0x00 7. " AERR ,Access error IRQ status" "No effect,Error"
|
|
textline " "
|
|
eventfld.word 0x00 6. " STC ,Start condition IRQ status" "No effect,Detected"
|
|
eventfld.word 0x00 5. " GC ,General call IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not requested,Requested"
|
|
eventfld.word 0x00 3. " RRDY ,Receive data ready IRQ status" "Not availabled,Availabled"
|
|
textline " "
|
|
eventfld.word 0x00 2. " ARDY ,Register access ready IRQ status" "Busy,Ready"
|
|
eventfld.word 0x00 1. " NACK ,No acknowledgment IRQ status" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 0. " AL ,Arbitration lost IRQ status" "Not detected,Detected"
|
|
group.word 0x0c++0x01
|
|
line.word 0x00 "I2C_WE,I2C Wakeup Enable Register"
|
|
bitfld.word 0x00 14. " XDR_WE ,Transmit draining wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RDR_WE ,Receive draining wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " AAS_WE ,Address as slave wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BF_WE ,Bus free wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " STC_WE ,Start condition wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " GC_WE ,General call wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DRDY_WE ,Transmit/receive data ready wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " ARDY_WE ,Register access ready wakeup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " NACK_WE ,No acknowledgment wakeup enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " AL_WE ,Arbitration lost wakeup enable" "Disabled,Enabled"
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "I2C_SYSS,I2C Status Information About Module"
|
|
bitfld.word 0x00 0. " RDONE ,Internal reset monitoring" "Ongoing,Completed"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "I2C_BUF,I2C Buffer Configuration Register"
|
|
bitfld.word 0x00 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RXFIFO_CLR ,Receive FIFO clear" "No effect,Reset"
|
|
textline " "
|
|
hexmask.word.byte 0x00 8.--13. 1. " RTRSH ,Threshold value for FIFO buffer in RX mode"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TXFIFO_CLR ,Transmit FIFO clear" "No effect,Reset"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--5. 1. " XTRSH ,Threshold value for FIFO buffer in TX mode"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "I2C_CNT,I2C Data Count Register"
|
|
hexmask.word 0x00 0.--15. 1. " DCOUNT ,Data count"
|
|
hgroup.word 0x1c++0x01
|
|
hide.word 0x00 "I2C_DATA,I2C Transmit/Receive FIFO data"
|
|
in
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "I2C_SYSC,I2C Parameters of the L4-Core Interconnect Interface"
|
|
bitfld.word 0x00 8.--9. " CLOCK_ACTIVITY ,Clock activity (interface/functional)" "Cut off,Active/Cut off,Cut off/Active,Active"
|
|
bitfld.word 0x00 3.--4. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
|
|
textline " "
|
|
bitfld.word 0x00 2. " ENAWAKEUP ,Enable wakeup" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " SRST ,Software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 0. " AUTOIDLE ,Auto idle enable" "Disabled,Enabled"
|
|
if (((d.w((ad:0x48060000+0x24)))&0x400)==0x400)
|
|
;master mode
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_CON,I2C Control Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,Module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard,I2C High Speed,SCCB,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.word 0x00 11. " STB ,Start byte mode" "Normal,Start byte"
|
|
textline " "
|
|
bitfld.word 0x00 9. " TRX ,Transmitter/receiver mode" "Receiver,Transmitter"
|
|
bitfld.word 0x00 8. " XSA ,Expand slave address enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XOA0 ,Expand own address 0 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 6. " XOA1 ,Expand own address 1 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 5. " XOA2 ,Expand own address 2 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 4. " XOA3 ,Expand own address 3 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 1. " STP ,Stop condition" "No action/Detected,Queried"
|
|
bitfld.word 0x00 0. " STT ,Start condition" "No action/Detected,Queried"
|
|
else
|
|
;slave mode
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "I2C_CON,I2C Control Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,Module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12.--13. " OPMODE ,Operation mode selection" "I2C Fast/Standard,I2C High Speed,SCCB,?..."
|
|
textline " "
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
bitfld.word 0x00 8. " XSA ,Expand slave address enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XOA0 ,Expand own address 0 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 6. " XOA1 ,Expand own address 1 enable" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.word 0x00 5. " XOA2 ,Expand own address 2 enable" "7-bit,10-bit"
|
|
bitfld.word 0x00 4. " XOA3 ,Expand own address 3 enable" "7-bit,10-bit"
|
|
endif
|
|
if (((d.w((ad:0x48060000+0x24)))&0x80)==0x80)
|
|
;I2C_CON[7]= 10-bit
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "I2C_OA0,I2C Own Address 0"
|
|
bitfld.word 0x00 13.--15. " MCODE ,Master code value" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x00 0.--9. 1. " OA ,Own address 0 value"
|
|
else
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "I2C_OA0,I2C Own Address 0"
|
|
bitfld.word 0x00 13.--15. " MCODE ,Master code value" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA ,Own address 0 value"
|
|
endif
|
|
if (((d.w((ad:0x48060000+0x24)))&0x100)==0x100)
|
|
;I2C_CON[8]= 10-bit
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2C_SA,I2C Slave Address"
|
|
hexmask.word 0x00 0.--9. 1. " SA ,Slave address value"
|
|
else
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "I2C_SA,I2C Slave Address"
|
|
hexmask.word.byte 0x00 0.--6. 1. " SA ,Slave address value"
|
|
endif
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "I2C_PSC,I2C Prescale Sampling Clock Divider"
|
|
hexmask.word.byte 0x00 0.--7. 1. " PSC ,Fast/Standard and SCCB modes prescale sampling clock divider value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "I2C_SCLL,I2C SCL"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HSSCLL ,I2C High Speed mode SCL low time value"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SCLL ,I2C Fast/Standard or SCCB modes SCL low time value"
|
|
group.word 0x38++0x01
|
|
line.word 0x00 "I2C_SCLH,I2C SCLH"
|
|
hexmask.word.byte 0x00 8.--15. 1. " HSSCLH ,I2C high-speed mode SCL high time value"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SCLH ,I2C Fast/Standard or SCCB modes SCL high time value"
|
|
group.word 0x3c++0x01
|
|
line.word 0x00 "I2C_SYSTEST,I2C System Test Register"
|
|
bitfld.word 0x00 15. " ST_EN ,System test enable" "No effect,Enabled"
|
|
bitfld.word 0x00 14. " FREE ,Free-running mode" "Stopped,Free-running"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,SCL counters,Loop back/SDA/SCL IO"
|
|
bitfld.word 0x00 11. " SSB ,Set status" "No effect,Set"
|
|
textline " "
|
|
bitfld.word 0x00 4. " SCCBE_O ,SCCBE line sense output value" "0,1"
|
|
bitfld.word 0x00 3. " SCL_I ,SCL line sense input value" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SCL_O ,SCL line drive output value" "0,1"
|
|
bitfld.word 0x00 1. " SDA_I ,SDA line sense input value" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 0. " SDA_O ,SDA line drive output value" "0,1"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "I2C_BUFSTAT,I2C FIFO Status Information"
|
|
bitfld.word 0x00 14.--15. " FIFODEPTH ,FIFO depth" "8-bytes,16-bytes,32-bytes,64-bytes"
|
|
hexmask.word.byte 0x00 8.--13. 1. " RXSTAT ,RX buffer status"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--5. 1. " TXSTAT ,TX buffer status"
|
|
if (((d.w((ad:0x48060000+0x24)))&0x40)==0x40)
|
|
;I2C_CON[6]= 10-bit
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "I2C_OA1,I2C Own Address 1"
|
|
hexmask.word 0x00 0.--9. 1. " OA1 ,Own address 1 value"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "I2C_OA1,I2C Own Address 1"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA1 ,Own address 1 value"
|
|
endif
|
|
if (((d.w((ad:0x48060000+0x24)))&0x20)==0x20)
|
|
;I2C_CON[5]= 10-bit
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2C_OA2,I2C Own Address 2"
|
|
hexmask.word 0x00 0.--9. 1. " OA2 ,Own address 2 value"
|
|
else
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "I2C_OA2,I2C Own Address 2"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA2 ,Own address 2 value"
|
|
endif
|
|
if (((d.w((ad:0x48060000+0x24)))&0x10)==0x10)
|
|
;I2C_CON[4]= 10-bit
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2C_OA3,I2C Own Address 3"
|
|
hexmask.word 0x00 0.--9. 1. " OA3 ,Own address 3 value"
|
|
else
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "I2C_OA3,I2C Own Address 3"
|
|
hexmask.word.byte 0x00 0.--6. 1. " OA3 ,Own address 3 value"
|
|
endif
|
|
rgroup.word 0x50++0x01
|
|
line.word 0x00 "I2C_ACTOA,I2C Accessed Slave Own Address Indicators"
|
|
bitfld.word 0x00 3. " OA3_ACT ,Own address 3 active" "Inactive,Active"
|
|
bitfld.word 0x00 2. " OA2_ACT ,Own address 2 active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OA1_ACT ,Own address 1 active" "Inactive,Active"
|
|
bitfld.word 0x00 0. " OA0_ACT ,Own address 0 active" "Inactive,Active"
|
|
group.word 0x54++0x01
|
|
line.word 0x00 "I2C_SBLOCK,I2C Slave Mode Bus Lock Features"
|
|
bitfld.word 0x00 3. " OA3_EN ,Enable I2C clock blocking for own address 3" "Released,Blocked"
|
|
bitfld.word 0x00 2. " OA2_EN ,Enable I2C clock blocking for own address 2" "Released,Blocked"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OA1_EN ,Enable I2C clock blocking for own address 1" "Released,Blocked"
|
|
bitfld.word 0x00 0. " OA0_EN ,Enable I2C clock blocking for own address 0" "Released,Blocked"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree.open "Multichannel SPI"
|
|
tree "MCSPI1"
|
|
base ad:0x48098000
|
|
width 20.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCSPI_SYSCONFIG,MCSPI System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Normal,Wake up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MCSPI_SYSSTATUS,MCSPI System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "MCSPI_IRQSTATUS,MCSPI Interrupt Status Register"
|
|
eventfld.long 0x00 17. " EOW ,End of word count event" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " WKS ,Wake up event in slave mode" "False,Pending"
|
|
eventfld.long 0x00 14. " RX3_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RX2_FULL ,Receiver register full" "False,Pending"
|
|
eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty" "False,Pending"
|
|
eventfld.long 0x00 6. " RX1_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow" "False,Pending"
|
|
eventfld.long 0x00 2. " RX0_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty" "False,Pending"
|
|
line.long 0x04 "MCSPI_IRQENABLE,MCSPI Interrupt Enable/Disable Register"
|
|
bitfld.long 0x04 17. " EOW ,End of word count event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " WKE ,Wake up event interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RX3_FULL_ENABLE ,Receiver register full Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " TX3_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " RX2_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " TX2_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RX1_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TX1_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX0_OVERFLOW_ENABLE ,Receiver register overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RX0_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TX0_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCSPI_WAKEUPENABLE,MCSPI Wakeup Enable/Disable Register"
|
|
bitfld.long 0x08 0. " WKEN ,Event allowed to wakeup the system" "Not allowed,Allowed"
|
|
line.long 0x0c "MCSPI_SYST,MCSPI System Test Register"
|
|
bitfld.long 0x0C 11. " SSB ,Set status" "No action,Forced to 1"
|
|
bitfld.long 0x0C 10. " SPIENDIR ,Set the direction of the spin_cs lines and spin_clk line" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input"
|
|
bitfld.long 0x0C 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " WAKD ,SWAKEUP output" "Low,High"
|
|
bitfld.long 0x0C 6. " SPICLK ,spin_clk line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " SPIDAT_1 ,spin_somi line value" "Low,High"
|
|
bitfld.long 0x0C 4. " SPIDAT_0 ,spin_simo line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " SPIEN_3 ,spin_cs3 line value" "Low,High"
|
|
bitfld.long 0x0C 2. " SPIEN_2 ,spin_cs2 line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPIEN_1 ,spin_cs1 line value" "Low,High"
|
|
bitfld.long 0x0C 0. " SPIEN_0 ,spin_cs0 line value" "Low,High"
|
|
if (((d.l((ad:0x48098000+0x28)))&0x4)==0x4)
|
|
;slave
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
else
|
|
;master
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channe" "Multi,Single"
|
|
endif
|
|
group.long 0x2C++0x3 "Channel 0"
|
|
line.long 0x00 "MCSPI_CH0CONF,MCSPI Channel 0 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
sif (cpu()!="OMAP3517"&&cpu()!="omap3505")
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 0" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x2C+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH0STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 0 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full"
|
|
group.long (0x2C+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH0CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX0,MCSPI Transmit Register"
|
|
hgroup.long (0x2C+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX0,MCSPI Receive Register"
|
|
in
|
|
group.long 0x40++0x3 "Channel 1"
|
|
line.long 0x00 "MCSPI_CH1CONF,MCSPI Channel 1 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
sif (cpu()!="OMAP3517"&&cpu()!="omap3505")
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x40+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH1STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 1 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 1 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 1 receiver register status" "Empty,Full"
|
|
group.long (0x40+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH1CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX1,MCSPI Transmit Register"
|
|
hgroup.long (0x40+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX1,MCSPI Receive Register"
|
|
in
|
|
group.long 0x54++0x3 "Channel 2"
|
|
line.long 0x00 "MCSPI_CH2CONF,MCSPI Channel 2 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
sif (cpu()!="OMAP3517"&&cpu()!="omap3505")
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 2" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x54+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH2STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 2 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 2 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 2 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 2 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 2 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 2 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 2 receiver register status" "Empty,Full"
|
|
group.long (0x54+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH2CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX2,MCSPI Transmit Register"
|
|
hgroup.long (0x54+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX2,MCSPI Receive Register"
|
|
in
|
|
group.long 0x68++0x3 "Channel 3"
|
|
line.long 0x00 "MCSPI_CH3CONF,MCSPI Channel 3 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
sif (cpu()!="OMAP3517"&&cpu()!="omap3505")
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 3" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x68+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH3STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 3 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 3 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 3 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 3 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 3 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 3 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 3 receiver register status" "Empty,Full"
|
|
group.long (0x68+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH3CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX3,MCSPI Transmit Register"
|
|
hgroup.long (0x68+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX3,MCSPI Receive Register"
|
|
in
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "MCSPI_XFERLEVEL,Transfer Levels Needed While Using FIFO Buffer During Transfer"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " AEL ,Buffer Almost Empty"
|
|
width 11.
|
|
tree.end
|
|
tree "MCSPI2"
|
|
base ad:0x4809a000
|
|
width 20.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCSPI_SYSCONFIG,MCSPI System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Normal,Wake up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MCSPI_SYSSTATUS,MCSPI System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "MCSPI_IRQSTATUS,MCSPI Interrupt Status Register"
|
|
eventfld.long 0x00 17. " EOW ,End of word count event" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " WKS ,Wake up event in slave mode" "False,Pending"
|
|
eventfld.long 0x00 6. " RX1_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow" "False,Pending"
|
|
eventfld.long 0x00 2. " RX0_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty" "False,Pending"
|
|
line.long 0x04 "MCSPI_IRQENABLE,MCSPI Interrupt Enable/Disable Register"
|
|
bitfld.long 0x04 17. " EOW ,End of word count event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " WKE ,Wake up event interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RX1_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TX1_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX0_OVERFLOW_ENABLE ,Receiver register overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RX0_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TX0_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCSPI_WAKEUPENABLE,MCSPI Wakeup Enable/Disable Register"
|
|
bitfld.long 0x08 0. " WKEN ,Event allowed to wakeup the system" "Not allowed,Allowed"
|
|
line.long 0x0c "MCSPI_SYST,MCSPI System Test Register"
|
|
bitfld.long 0x0C 11. " SSB ,Set status" "No action,Forced to 1"
|
|
bitfld.long 0x0C 10. " SPIENDIR ,Set the direction of the spin_cs lines and spin_clk line" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input"
|
|
bitfld.long 0x0C 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " WAKD ,SWAKEUP output" "Low,High"
|
|
bitfld.long 0x0C 6. " SPICLK ,spin_clk line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " SPIDAT_1 ,spin_somi line value" "Low,High"
|
|
bitfld.long 0x0C 4. " SPIDAT_0 ,spin_simo line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " SPIEN_3 ,spin_cs3 line value" "Low,High"
|
|
bitfld.long 0x0C 2. " SPIEN_2 ,spin_cs2 line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPIEN_1 ,spin_cs1 line value" "Low,High"
|
|
bitfld.long 0x0C 0. " SPIEN_0 ,spin_cs0 line value" "Low,High"
|
|
if (((d.l((ad:0x4809a000+0x28)))&0x4)==0x4)
|
|
;slave
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
else
|
|
;master
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channe" "Multi,Single"
|
|
endif
|
|
group.long 0x2C++0x3 "Channel 0"
|
|
line.long 0x00 "MCSPI_CH0CONF,MCSPI Channel 0 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 0" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x2C+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH0STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 0 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full"
|
|
group.long (0x2C+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH0CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX0,MCSPI Transmit Register"
|
|
hgroup.long (0x2C+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX0,MCSPI Receive Register"
|
|
in
|
|
group.long 0x40++0x3 "Channel 1"
|
|
line.long 0x00 "MCSPI_CH1CONF,MCSPI Channel 1 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x40+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH1STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 1 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 1 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 1 receiver register status" "Empty,Full"
|
|
group.long (0x40+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH1CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX1,MCSPI Transmit Register"
|
|
hgroup.long (0x40+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX1,MCSPI Receive Register"
|
|
in
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "MCSPI_XFERLEVEL,Transfer Levels Needed While Using FIFO Buffer During Transfer"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " AEL ,Buffer Almost Empty"
|
|
width 11.
|
|
tree.end
|
|
tree "MCSPI3"
|
|
base ad:0x480b8000
|
|
width 20.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCSPI_SYSCONFIG,MCSPI System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Normal,Wake up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MCSPI_SYSSTATUS,MCSPI System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "MCSPI_IRQSTATUS,MCSPI Interrupt Status Register"
|
|
eventfld.long 0x00 17. " EOW ,End of word count event" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " WKS ,Wake up event in slave mode" "False,Pending"
|
|
eventfld.long 0x00 6. " RX1_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow" "False,Pending"
|
|
eventfld.long 0x00 2. " RX0_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty" "False,Pending"
|
|
line.long 0x04 "MCSPI_IRQENABLE,MCSPI Interrupt Enable/Disable Register"
|
|
bitfld.long 0x04 17. " EOW ,End of word count event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " WKE ,Wake up event interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RX1_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TX1_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX0_OVERFLOW_ENABLE ,Receiver register overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RX0_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TX0_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCSPI_WAKEUPENABLE,MCSPI Wakeup Enable/Disable Register"
|
|
bitfld.long 0x08 0. " WKEN ,Event allowed to wakeup the system" "Not allowed,Allowed"
|
|
line.long 0x0c "MCSPI_SYST,MCSPI System Test Register"
|
|
bitfld.long 0x0C 11. " SSB ,Set status" "No action,Forced to 1"
|
|
bitfld.long 0x0C 10. " SPIENDIR ,Set the direction of the spin_cs lines and spin_clk line" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input"
|
|
bitfld.long 0x0C 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " WAKD ,SWAKEUP output" "Low,High"
|
|
bitfld.long 0x0C 6. " SPICLK ,spin_clk line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " SPIDAT_1 ,spin_somi line value" "Low,High"
|
|
bitfld.long 0x0C 4. " SPIDAT_0 ,spin_simo line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " SPIEN_3 ,spin_cs3 line value" "Low,High"
|
|
bitfld.long 0x0C 2. " SPIEN_2 ,spin_cs2 line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPIEN_1 ,spin_cs1 line value" "Low,High"
|
|
bitfld.long 0x0C 0. " SPIEN_0 ,spin_cs0 line value" "Low,High"
|
|
if (((d.l((ad:0x480b8000+0x28)))&0x4)==0x4)
|
|
;slave
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
else
|
|
;master
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channe" "Multi,Single"
|
|
endif
|
|
group.long 0x2C++0x3 "Channel 0"
|
|
line.long 0x00 "MCSPI_CH0CONF,MCSPI Channel 0 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 0" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x2C+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH0STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 0 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full"
|
|
group.long (0x2C+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH0CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX0,MCSPI Transmit Register"
|
|
hgroup.long (0x2C+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX0,MCSPI Receive Register"
|
|
in
|
|
group.long 0x40++0x3 "Channel 1"
|
|
line.long 0x00 "MCSPI_CH1CONF,MCSPI Channel 1 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 1" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x40+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH1STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 1 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 1 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 1 receiver register status" "Empty,Full"
|
|
group.long (0x40+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH1CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX1,MCSPI Transmit Register"
|
|
hgroup.long (0x40+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX1,MCSPI Receive Register"
|
|
in
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "MCSPI_XFERLEVEL,Transfer Levels Needed While Using FIFO Buffer During Transfer"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " AEL ,Buffer Almost Empty"
|
|
width 11.
|
|
tree.end
|
|
tree "MCSPI4"
|
|
base ad:0x480ba000
|
|
width 20.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCSPI_SYSCONFIG,MCSPI System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Normal,Wake up"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MCSPI_SYSSTATUS,MCSPI System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xf
|
|
line.long 0x00 "MCSPI_IRQSTATUS,MCSPI Interrupt Status Register"
|
|
eventfld.long 0x00 17. " EOW ,End of word count event" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 16. " WKS ,Wake up event in slave mode" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow" "False,Pending"
|
|
eventfld.long 0x00 2. " RX0_FULL ,Receiver register full" "False,Pending"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending"
|
|
eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty" "False,Pending"
|
|
line.long 0x04 "MCSPI_IRQENABLE,MCSPI Interrupt Enable/Disable Register"
|
|
bitfld.long 0x04 17. " EOW ,End of word count event enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 16. " WKE ,Wake up event interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RX0_OVERFLOW_ENABLE ,Receiver register overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RX0_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TX0_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCSPI_WAKEUPENABLE,MCSPI Wakeup Enable/Disable Register"
|
|
bitfld.long 0x08 0. " WKEN ,Event allowed to wakeup the system" "Not allowed,Allowed"
|
|
line.long 0x0c "MCSPI_SYST,MCSPI System Test Register"
|
|
bitfld.long 0x0C 11. " SSB ,Set status" "No action,Forced to 1"
|
|
bitfld.long 0x0C 10. " SPIENDIR ,Set the direction of the spin_cs lines and spin_clk line" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input"
|
|
bitfld.long 0x0C 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " WAKD ,SWAKEUP output" "Low,High"
|
|
bitfld.long 0x0C 6. " SPICLK ,spin_clk line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " SPIDAT_1 ,spin_somi line value" "Low,High"
|
|
bitfld.long 0x0C 4. " SPIDAT_0 ,spin_simo line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " SPIEN_3 ,spin_cs3 line value" "Low,High"
|
|
bitfld.long 0x0C 2. " SPIEN_2 ,spin_cs2 line value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " SPIEN_1 ,spin_cs1 line value" "Low,High"
|
|
bitfld.long 0x0C 0. " SPIEN_0 ,spin_cs0 line value" "Low,High"
|
|
if (((d.l((ad:0x480ba000+0x28)))&0x4)==0x4)
|
|
;slave
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
else
|
|
;master
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
|
|
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
|
|
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channe" "Multi,Single"
|
|
endif
|
|
group.long 0x2C++0x3 "Channel 0"
|
|
line.long 0x00 "MCSPI_CH0CONF,MCSPI Channel 0 Configuration Register"
|
|
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "not used,Used"
|
|
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "not used,Used"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
|
|
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
|
|
sif (cpu()!="OMAP3517"&&cpu()!="OMAP3505")
|
|
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "spin_cs0,spin_cs1,spin_cs2,spin_cs3"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 20. " FORCE ,Manual spin_cs assertion" "Not asserted,Asserted"
|
|
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
|
|
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
|
|
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
|
|
bitfld.long 0x00 6. " EPOL ,spin_cs polarity for channel 0" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for spin_clk" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,?..."
|
|
bitfld.long 0x00 1. " POL ,spin_clk polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PHA ,spin_clk phase" "Odd,Even"
|
|
rgroup.long (0x2C+0x04)++0x3
|
|
line.long 0x00 "MCSPI_CH0STAT,MCSPI Channel Status Register"
|
|
bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full"
|
|
bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EOT ,Channel 0 end of transfer status" "Not ended,Ended"
|
|
bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full"
|
|
group.long (0x2C+0x08)++0x7
|
|
line.long 0x00 "MCSPI_CH0CTRL,MCSPI Channel Control Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCSPI_TX0,MCSPI Transmit Register"
|
|
hgroup.long (0x2C+0x10)++0x3
|
|
hide.long 0x00 "MCSPI_RX0,MCSPI Receive Register"
|
|
in
|
|
group.long 0x7C++0x3
|
|
line.long 0x00 "MCSPI_XFERLEVEL,Transfer Levels Needed While Using FIFO Buffer During Transfer"
|
|
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--13. 1. " AFL ,Buffer Almost Full"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " AEL ,Buffer Almost Empty"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree "HDQ/1-Wire"
|
|
base ad:0x480b2000
|
|
width 17.
|
|
textline ""
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "HDQ_TX_DATA,HDQ Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TX_DATA ,Transmit data"
|
|
hgroup.long 0x08++0x3
|
|
hide.long 0x00 "HDQ_RX_DATA,HDQ Receive Data Register"
|
|
in
|
|
if (((d.l((ad:0x480b2000+0x0c)))&0x1)==0x1)
|
|
;1-wire
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "HDQ_CTRL_STATUS,HDQ Status Information About Module"
|
|
bitfld.long 0x00 0. " MODE ,Mode selection" "HDQ,1-Wire"
|
|
bitfld.long 0x00 7. " 1_WIRE_SINGLE_BIT ,Single-bit mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " INTERRUPTMASK ,Interrupt masking" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " CLOCKENABLE ,Power down mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GO ,Send the appropriate commands" "No effect,Sent"
|
|
bitfld.long 0x00 3. " PRESENCEDETECT ,Presence detect received" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INITIALIZATION ,Initialization pulse" "No effect,Sent"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Read,Write"
|
|
else
|
|
;HDQ
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "HDQ_CTRL_STATUS,HDQ Status Information About Module"
|
|
bitfld.long 0x00 0. " MODE ,Mode selection" "HDQ,1-Wire"
|
|
bitfld.long 0x00 6. " INTERRUPTMASK ,Interrupt masking" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CLOCKENABLE ,Power down mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " GO ,Send the appropriate commands" "No effect,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 2. " INITIALIZATION ,Initialization pulse" "No effect,Sent"
|
|
bitfld.long 0x00 1. " DIR ,Direction" "Read,Write"
|
|
endif
|
|
hgroup.long 0x10++0x3
|
|
hide.long 0x00 "HDQ_INT_STATUS,HDQ Interrupt Status Register"
|
|
in
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "HDQ_SYSCONFIG,HDQ System Configuration Register"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Start soft reset sequence" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Interconnect idle" "Free-running,Power-saving"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x00 "HDQ_SYSSTATUS,HDQ System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset monitoring" "Performing,Finished"
|
|
width 11.
|
|
tree.end
|
|
tree.open "Multi-Channel Buffered Serial Port"
|
|
tree "McBSP1"
|
|
base ad:0x48074000
|
|
width 23.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "MCBSPLP_DRR_REG,McBSPLP Data Receive Register"
|
|
in
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP Data Transmit Register"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP Serial Port Control Register 2"
|
|
bitfld.long 0x00 9. " FREE ,Free running mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFT ,Soft Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FRST ,Frame-sync generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 6. " GRST ,Sample-rate generator reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " XINTM ,Transmit interrupt mode" "XRDY,End-of-frame,New frame,XSYNCERR"
|
|
bitfld.long 0x00 3. "XSYNCERR ,Transmit synchronization error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XRST ,Transmitter reset" "Reset,Enabled"
|
|
line.long 0x04 "MCBSPLP_SPCR1_REG,McBSPLP Serial Port Control Register 1"
|
|
bitfld.long 0x04 15. " ALB ,Analog loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right-justify and zero-fill MSBs,Right-justify and sign-extend MSBs,Left-justify and zero-fill LSBs,?..."
|
|
textline " "
|
|
bitfld.long 0x04 7. " DXENA ,DX enabler" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RINTM ,Receive interrupt mode" "RRDY,End-of-block/End-of-frame,New frame,RSYNCERR"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RSYNCERR ,Receive synchronization error" "No error,Error"
|
|
bitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0. " RRST ,Receiver reset" "Reset,Enabled"
|
|
line.long 0x08 "MCBSPLP_RCR2_REG,McBSPLP Receive Control Register 2"
|
|
bitfld.long 0x08 15. " RPHASE ,Receive phases" "Single,Dual"
|
|
hexmask.long.byte 0x08 8.--14. 1. " RFRLEN2 ,Receive frame length 2"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " RWDLEN2 ,Receive word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x08 3.--4. " RREVERSE ,Receive reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x0c "MCBSPLP_RCR1_REG,McBSPLP Receive Control Register 1"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RFRLEN1 ,Receive frame length 1"
|
|
bitfld.long 0x0C 5.--7. " RWDLEN1 ,Receive word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
line.long 0x10 "MCBSPLP_XCR2_REG,McBSPLP Transmit Control Register 2"
|
|
bitfld.long 0x10 15. " XPHASE ,Transmit phases" "Single,Dual"
|
|
hexmask.long.byte 0x10 8.--14. 1. " XFRLEN2 ,Transmit frame length 2"
|
|
textline " "
|
|
bitfld.long 0x10 5.--7. " XWDLEN2 ,Transmit word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x10 3.--4. " XREVERSE ,Transmit reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x14 "MCBSPLP_XCR1_REG,McBSPLP Transmit Control Register 1"
|
|
hexmask.long.byte 0x14 8.--14. 1. " XFRLEN1 ,Transmit frame length 1"
|
|
bitfld.long 0x14 5.--7. " XWDLEN1 ,Transmit word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
if ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48074000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x48074000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48074000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x48074000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48074000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x48074000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48074000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x48074000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x48074000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x48074000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x48074000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x48074000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==1 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48074000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x48074000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x48074000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
else
|
|
;CLKSM==1 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
endif
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP SRG Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample rate generator clock divider"
|
|
if (((d.l((ad:0x48074000+0x30)))&0x3)==0x0)
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
else
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 9. " XMCME ,Transmit multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
endif
|
|
if (((d.l((ad:0x48074000+0x34)))&0x1)==0x0)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 9. " RMCME ,Receive multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
endif
|
|
group.long 0x38++0xf
|
|
line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[15] ,Receive channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[14] ,Receive channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[13] ,Receive channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[12] ,Receive channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[11] ,Receive channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[10] ,Receive channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[9] ,Receive channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[8] ,Receive channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[7] ,Receive channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[6] ,Receive channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[5] ,Receive channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[4] ,Receive channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[3] ,Receive channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[2] ,Receive channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[1] ,Receive channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[0] ,Receive channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERB_REG,McBSPLP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x04 15. " RCERB[31] ,Receive channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERB[30] ,Receive channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERB[29] ,Receive channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERB[28] ,Receive channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERB[27] ,Receive channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERB[26] ,Receive channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERB[25] ,Receive channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERB[24] ,Receive channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERB[23] ,Receive channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERA[22] ,Receive channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERA[21] ,Receive channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERA[20] ,Receive channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERA[19] ,Receive channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERA[18] ,Receive channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERA[17] ,Receive channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERA[16] ,Receive channel 16 enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_XCERA_REG,McBSPLP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x08 15. " XCERA[15] ,Transmit channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " XCERA[14] ,Transmit channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " XCERA[13] ,Transmit channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " XCERA[12] ,Transmit channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " XCERA[11] ,Transmit channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XCERA[10] ,Transmit channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " XCERA[9] ,Transmit channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " XCERA[8] ,Transmit channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " XCERA[7] ,Transmit channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " XCERA[6] ,Transmit channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " XCERA[5] ,Transmit channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XCERA[4] ,Transmit channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " XCERA[3] ,Transmit channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " XCERA[2] ,Transmit channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " XCERA[1] ,Transmit channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " XCERA[0] ,Transmit channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x0c "MCBSPLP_XCERB_REG,McBSPLP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x0c 15. " XCERB[31] ,Transmit channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " XCERB[30] ,Transmit channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " XCERB[29] ,Transmit channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " XCERB[28] ,Transmit channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " XCERB[27] ,Transmit channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " XCERB[26] ,Transmit channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " XCERB[25] ,Transmit channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " XCERB[24] ,Transmit channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " XCERB[23] ,Transmit channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " XCERB[22] ,Transmit channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " XCERB[21] ,Transmit channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " XCERB[20] ,Transmit channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " XCERB[19] ,Transmit channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " XCERB[18] ,Transmit channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " XCERB[17] ,Transmit channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " XCERB[16] ,Transmit channel 16 enable" "Disabled,Enabled"
|
|
if ((((d.l((ad:0x48074000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48074000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48074000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48074000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48074000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48074000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x20))
|
|
;xrst==1 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48074000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x48074000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x48074000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
else
|
|
;xrst==1 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
endif
|
|
if ((((d.l((ad:0x48074000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x48074000+0x34)))&0x1)==0x1))
|
|
group.long 0x4c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " RCERC[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERC[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERC[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERC[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERC[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERC[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERC[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERC[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERC[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERC[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERC[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERC[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERC[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERC[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERC[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERC[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " RCERD[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERD[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERD[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERD[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERD[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERD[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERD[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERD[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERD[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERD[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERD[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERD[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERD[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERD[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERD[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERD[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x4c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x48074000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x48074000+0x30)))&0x3)!=0x0))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " XCERC[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERC[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERC[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERC[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERC[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERC[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERC[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERC[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERC[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERC[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERC[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERC[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERC[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERC[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERC[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERC[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " XCERD[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERD[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERD[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERD[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERD[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERD[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERD[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERD[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERD[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERD[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERD[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERD[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERD[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERD[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERD[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERD[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x54++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x48074000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x48074000+0x34)))&0x1)==0x1))
|
|
group.long 0x5c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " RCERE[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERE[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERE[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERE[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERE[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERE[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERE[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERE[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERE[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERE[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERE[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERE[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERE[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERE[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERE[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERE[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " RCERF[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERF[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERF[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERF[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERF[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERF[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERF[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERF[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERF[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERF[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERF[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERF[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERF[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERF[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERF[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERF[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x5c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x48074000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x48074000+0x30)))&0x3)!=0x0))
|
|
group.long 0x64++0x7
|
|
line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " XCERE[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERE[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERE[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERE[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERE[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERE[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERE[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERE[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERE[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERE[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERE[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERE[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERE[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERE[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERE[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERE[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " XCERF[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERF[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERF[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERF[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERF[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERF[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERF[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERF[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERF[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERF[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERF[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERF[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERF[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERF[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERF[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERF[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x64++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x48074000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x48074000+0x34)))&0x1)==0x1))
|
|
group.long 0x6c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " RCERG[111],Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERG[110],Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERG[109],Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERG[108],Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERG[107],Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERG[106],Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERG[105],Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERG[104],Receive channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERG[103],Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERG[102],Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERG[101],Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERG[100],Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERG[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERG[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERG[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERG[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " RCERH[127],Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERH[126],Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERH[125],Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERH[124],Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERH[123],Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERH[122],Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERH[121],Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERH[120],Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERH[119],Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERH[118],Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERH[117],Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERH[116],Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERH[115],Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERH[114],Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERH[113],Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERH[112],Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x6c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
endif
|
|
if ((((d.l((ad:0x48074000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x48074000+0x30)))&0x3)!=0x0))
|
|
group.long 0x74++0x7
|
|
line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " XCERG[111],Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERG[110],Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERG[109],Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERG[108],Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERG[107],Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERG[106],Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERG[105],Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERG[104],Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERG[103],Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERG[102],Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERG[101],Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERG[100],Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERG[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERG[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERG[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERG[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " XCERH[127],Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERH[126],Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERH[125],Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERH[124],Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERH[123],Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERH[122],Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERH[121],Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERH[120],Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERH[119],Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERH[118],Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERH[117],Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERH[116],Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERH[115],Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERH[114],Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERH[113],Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERH[112],Transmit channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x74++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
endif
|
|
rgroup.long 0x7c++0x3
|
|
line.long 0x00 "MCBSPLP_REV_REG,MCBSPLP Revision Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP Revision"
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP Receive Interrupt Clear"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP Transmit Interrupt Clear"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP Receive Overflow Interrupt Clear"
|
|
in
|
|
group.long 0x8c++0xb
|
|
line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY,Clock activity (McBSPi_ICLK/PRCM)" "Switched off,Switched off/Maintained,Maintained/Switched off,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
line.long 0x04 "MCBSPLP_THRSH2_REG,McBSPLP Transmit Buffer Threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x08 "MCBSPLP_THRSH1_REG,McBSPLP Receive Buffer Threshold"
|
|
hexmask.long.byte 0x08 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
group.long 0xa0++0x13
|
|
line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status Register"
|
|
eventfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " XOVFLEN ,Transmit buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " XUNDFLEN ,Transmit buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDYEN ,Transmit buffer threshold reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " XEOFEN ,Transmit end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSXEN ,Transmit frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " XSYNCERREN ,Transmit frame synchronization error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ROVFLEN ,Receive buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RUNDFLEN ,Receive buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDYEN ,Receive buffer threshold enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REOFEN ,Receive end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSREN ,Receive frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RSYNCERREN ,Receive frame synchronization error enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable Register"
|
|
bitfld.long 0x08 10. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 10. " XRDYEN ,Transmit buffer threshold reached WK enable" "Not active,Active"
|
|
bitfld.long 0x08 9. " XEOFEN ,Transmit end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XFSXEN ,Transmit frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 7. " XSYNCERREN ,Transmit frame synchronization error WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDYEN ,Receive buffer threshold wakeup enable" "Not active,Active"
|
|
bitfld.long 0x08 2. " REOFEN ,Receive end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSREN ,Receive frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 0. " RSYNCERREN ,Receive frame synchronization error WK enable" "Not active,Active"
|
|
line.long 0x0c "MCBSPLP_XCCR_REG,McBSPLP Transmit Configuration Control Register"
|
|
bitfld.long 0x0C 15. " EXTCLKGATE ,External clock gating enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PPCONNECT ,Pair to pair connection" "No connection,Connection"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "18 ns,26 ns,35 ns,42 ns"
|
|
bitfld.long 0x0C 11. " XFULL_CYCLE ,Transmit full cycle mode" "Half-cycle,Full-cycle"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DLB ,Digital loop-back" "No DLB,DLB"
|
|
bitfld.long 0x0C 3. " XDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " XDISABLE ,Transmit disable" "Not stopped,Stopped"
|
|
line.long 0x10 "MCBSPLP_RCCR_REG,McBSPLP Receive Configuration Control Register"
|
|
bitfld.long 0x10 11. " RFULL_CYCLE ,Receive full cycle mode" "Half-cycle,Full-cycle"
|
|
bitfld.long 0x10 3. " RDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " RDISABLE ,Receive disable" "Not stopped,Stopped"
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP Transmit Buffer Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "MCBSPLP_RBUFFSTAT_REG,McBSPLP Receive Buffer Status"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RBUFFSTAT ,Receive buffer status"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "MCBSPLP_SSELCR_REG,McBSPLP Sidetone Select Register"
|
|
bitfld.long 0x00 10. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " OCH1ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OCH0ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 2.--3. " ICH1ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ICH0ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
rgroup.long 0xc0++0x3
|
|
line.long 0x00 "MCBSPLP_STATUS_REG,McBSPLP Status Register"
|
|
bitfld.long 0x00 0. " CLKMUXSTATUS ,Response to a different register access delayed" "No effect,Delayed"
|
|
width 11.
|
|
tree.end
|
|
tree "McBSP2"
|
|
base ad:0x49022000
|
|
width 23.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "MCBSPLP_DRR_REG,McBSPLP Data Receive Register"
|
|
in
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP Data Transmit Register"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP Serial Port Control Register 2"
|
|
bitfld.long 0x00 9. " FREE ,Free running mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFT ,Soft Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FRST ,Frame-sync generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 6. " GRST ,Sample-rate generator reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " XINTM ,Transmit interrupt mode" "XRDY,End-of-frame,New frame,XSYNCERR"
|
|
bitfld.long 0x00 3. "XSYNCERR ,Transmit synchronization error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XRST ,Transmitter reset" "Reset,Enabled"
|
|
line.long 0x04 "MCBSPLP_SPCR1_REG,McBSPLP Serial Port Control Register 1"
|
|
bitfld.long 0x04 15. " ALB ,Analog loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right-justify and zero-fill MSBs,Right-justify and sign-extend MSBs,Left-justify and zero-fill LSBs,?..."
|
|
textline " "
|
|
bitfld.long 0x04 7. " DXENA ,DX enabler" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RINTM ,Receive interrupt mode" "RRDY,End-of-block/End-of-frame,New frame,RSYNCERR"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RSYNCERR ,Receive synchronization error" "No error,Error"
|
|
bitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0. " RRST ,Receiver reset" "Reset,Enabled"
|
|
line.long 0x08 "MCBSPLP_RCR2_REG,McBSPLP Receive Control Register 2"
|
|
bitfld.long 0x08 15. " RPHASE ,Receive phases" "Single,Dual"
|
|
hexmask.long.byte 0x08 8.--14. 1. " RFRLEN2 ,Receive frame length 2"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " RWDLEN2 ,Receive word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x08 3.--4. " RREVERSE ,Receive reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x0c "MCBSPLP_RCR1_REG,McBSPLP Receive Control Register 1"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RFRLEN1 ,Receive frame length 1"
|
|
bitfld.long 0x0C 5.--7. " RWDLEN1 ,Receive word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
line.long 0x10 "MCBSPLP_XCR2_REG,McBSPLP Transmit Control Register 2"
|
|
bitfld.long 0x10 15. " XPHASE ,Transmit phases" "Single,Dual"
|
|
hexmask.long.byte 0x10 8.--14. 1. " XFRLEN2 ,Transmit frame length 2"
|
|
textline " "
|
|
bitfld.long 0x10 5.--7. " XWDLEN2 ,Transmit word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x10 3.--4. " XREVERSE ,Transmit reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x14 "MCBSPLP_XCR1_REG,McBSPLP Transmit Control Register 1"
|
|
hexmask.long.byte 0x14 8.--14. 1. " XFRLEN1 ,Transmit frame length 1"
|
|
bitfld.long 0x14 5.--7. " XWDLEN1 ,Transmit word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
if ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49022000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x49022000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49022000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x49022000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49022000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x49022000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49022000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x49022000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49022000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x49022000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49022000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x49022000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==1 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49022000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49022000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x49022000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
else
|
|
;CLKSM==1 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
endif
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP SRG Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample rate generator clock divider"
|
|
if (((d.l((ad:0x49022000+0x30)))&0x3)==0x0)
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
else
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 9. " XMCME ,Transmit multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
endif
|
|
if (((d.l((ad:0x49022000+0x34)))&0x1)==0x0)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 9. " RMCME ,Receive multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
endif
|
|
group.long 0x38++0xf
|
|
line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[15] ,Receive channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[14] ,Receive channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[13] ,Receive channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[12] ,Receive channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[11] ,Receive channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[10] ,Receive channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[9] ,Receive channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[8] ,Receive channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[7] ,Receive channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[6] ,Receive channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[5] ,Receive channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[4] ,Receive channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[3] ,Receive channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[2] ,Receive channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[1] ,Receive channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[0] ,Receive channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERB_REG,McBSPLP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x04 15. " RCERB[31] ,Receive channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERB[30] ,Receive channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERB[29] ,Receive channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERB[28] ,Receive channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERB[27] ,Receive channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERB[26] ,Receive channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERB[25] ,Receive channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERB[24] ,Receive channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERB[23] ,Receive channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERA[22] ,Receive channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERA[21] ,Receive channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERA[20] ,Receive channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERA[19] ,Receive channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERA[18] ,Receive channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERA[17] ,Receive channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERA[16] ,Receive channel 16 enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_XCERA_REG,McBSPLP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x08 15. " XCERA[15] ,Transmit channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " XCERA[14] ,Transmit channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " XCERA[13] ,Transmit channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " XCERA[12] ,Transmit channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " XCERA[11] ,Transmit channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XCERA[10] ,Transmit channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " XCERA[9] ,Transmit channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " XCERA[8] ,Transmit channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " XCERA[7] ,Transmit channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " XCERA[6] ,Transmit channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " XCERA[5] ,Transmit channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XCERA[4] ,Transmit channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " XCERA[3] ,Transmit channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " XCERA[2] ,Transmit channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " XCERA[1] ,Transmit channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " XCERA[0] ,Transmit channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x0c "MCBSPLP_XCERB_REG,McBSPLP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x0c 15. " XCERB[31] ,Transmit channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " XCERB[30] ,Transmit channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " XCERB[29] ,Transmit channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " XCERB[28] ,Transmit channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " XCERB[27] ,Transmit channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " XCERB[26] ,Transmit channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " XCERB[25] ,Transmit channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " XCERB[24] ,Transmit channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " XCERB[23] ,Transmit channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " XCERB[22] ,Transmit channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " XCERB[21] ,Transmit channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " XCERB[20] ,Transmit channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " XCERB[19] ,Transmit channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " XCERB[18] ,Transmit channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " XCERB[17] ,Transmit channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " XCERB[16] ,Transmit channel 16 enable" "Disabled,Enabled"
|
|
if ((((d.l((ad:0x49022000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49022000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49022000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49022000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49022000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49022000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x20))
|
|
;xrst==1 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49022000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49022000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49022000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
else
|
|
;xrst==1 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
endif
|
|
if ((((d.l((ad:0x49022000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x49022000+0x34)))&0x1)==0x1))
|
|
group.long 0x4c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " RCERC[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERC[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERC[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERC[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERC[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERC[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERC[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERC[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERC[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERC[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERC[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERC[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERC[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERC[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERC[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERC[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " RCERD[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERD[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERD[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERD[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERD[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERD[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERD[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERD[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERD[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERD[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERD[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERD[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERD[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERD[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERD[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERD[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x4c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x49022000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49022000+0x30)))&0x3)!=0x0))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " XCERC[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERC[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERC[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERC[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERC[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERC[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERC[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERC[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERC[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERC[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERC[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERC[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERC[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERC[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERC[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERC[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " XCERD[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERD[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERD[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERD[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERD[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERD[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERD[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERD[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERD[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERD[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERD[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERD[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERD[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERD[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERD[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERD[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x54++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x49022000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x49022000+0x34)))&0x1)==0x1))
|
|
group.long 0x5c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " RCERE[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERE[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERE[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERE[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERE[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERE[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERE[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERE[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERE[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERE[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERE[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERE[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERE[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERE[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERE[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERE[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " RCERF[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERF[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERF[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERF[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERF[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERF[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERF[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERF[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERF[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERF[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERF[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERF[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERF[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERF[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERF[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERF[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x5c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x49022000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49022000+0x30)))&0x3)!=0x0))
|
|
group.long 0x64++0x7
|
|
line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " XCERE[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERE[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERE[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERE[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERE[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERE[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERE[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERE[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERE[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERE[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERE[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERE[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERE[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERE[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERE[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERE[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " XCERF[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERF[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERF[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERF[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERF[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERF[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERF[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERF[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERF[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERF[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERF[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERF[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERF[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERF[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERF[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERF[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x64++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x49022000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x49022000+0x34)))&0x1)==0x1))
|
|
group.long 0x6c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " RCERG[111],Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERG[110],Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERG[109],Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERG[108],Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERG[107],Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERG[106],Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERG[105],Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERG[104],Receive channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERG[103],Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERG[102],Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERG[101],Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERG[100],Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERG[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERG[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERG[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERG[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " RCERH[127],Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERH[126],Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERH[125],Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERH[124],Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERH[123],Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERH[122],Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERH[121],Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERH[120],Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERH[119],Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERH[118],Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERH[117],Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERH[116],Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERH[115],Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERH[114],Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERH[113],Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERH[112],Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x6c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
endif
|
|
if ((((d.l((ad:0x49022000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49022000+0x30)))&0x3)!=0x0))
|
|
group.long 0x74++0x7
|
|
line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " XCERG[111],Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERG[110],Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERG[109],Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERG[108],Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERG[107],Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERG[106],Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERG[105],Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERG[104],Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERG[103],Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERG[102],Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERG[101],Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERG[100],Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERG[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERG[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERG[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERG[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " XCERH[127],Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERH[126],Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERH[125],Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERH[124],Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERH[123],Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERH[122],Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERH[121],Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERH[120],Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERH[119],Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERH[118],Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERH[117],Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERH[116],Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERH[115],Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERH[114],Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERH[113],Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERH[112],Transmit channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x74++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
endif
|
|
rgroup.long 0x7c++0x3
|
|
line.long 0x00 "MCBSPLP_REV_REG,MCBSPLP Revision Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP Revision"
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP Receive Interrupt Clear"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP Transmit Interrupt Clear"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP Receive Overflow Interrupt Clear"
|
|
in
|
|
group.long 0x8c++0xb
|
|
line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY,Clock activity (McBSPi_ICLK/PRCM)" "Switched off,Switched off/Maintained,Maintained/Switched off,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
line.long 0x04 "MCBSPLP_THRSH2_REG,McBSPLP Transmit Buffer Threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x08 "MCBSPLP_THRSH1_REG,McBSPLP Receive Buffer Threshold"
|
|
hexmask.long.byte 0x08 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
group.long 0xa0++0x13
|
|
line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status Register"
|
|
eventfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " XOVFLEN ,Transmit buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " XUNDFLEN ,Transmit buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDYEN ,Transmit buffer threshold reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " XEOFEN ,Transmit end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSXEN ,Transmit frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " XSYNCERREN ,Transmit frame synchronization error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ROVFLEN ,Receive buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RUNDFLEN ,Receive buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDYEN ,Receive buffer threshold enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REOFEN ,Receive end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSREN ,Receive frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RSYNCERREN ,Receive frame synchronization error enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable Register"
|
|
bitfld.long 0x08 10. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 10. " XRDYEN ,Transmit buffer threshold reached WK enable" "Not active,Active"
|
|
bitfld.long 0x08 9. " XEOFEN ,Transmit end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XFSXEN ,Transmit frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 7. " XSYNCERREN ,Transmit frame synchronization error WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDYEN ,Receive buffer threshold wakeup enable" "Not active,Active"
|
|
bitfld.long 0x08 2. " REOFEN ,Receive end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSREN ,Receive frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 0. " RSYNCERREN ,Receive frame synchronization error WK enable" "Not active,Active"
|
|
line.long 0x0c "MCBSPLP_XCCR_REG,McBSPLP Transmit Configuration Control Register"
|
|
bitfld.long 0x0C 15. " EXTCLKGATE ,External clock gating enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PPCONNECT ,Pair to pair connection" "No connection,Connection"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "18 ns,26 ns,35 ns,42 ns"
|
|
bitfld.long 0x0C 11. " XFULL_CYCLE ,Transmit full cycle mode" "Half-cycle,Full-cycle"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DLB ,Digital loop-back" "No DLB,DLB"
|
|
bitfld.long 0x0C 3. " XDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " XDISABLE ,Transmit disable" "Not stopped,Stopped"
|
|
line.long 0x10 "MCBSPLP_RCCR_REG,McBSPLP Receive Configuration Control Register"
|
|
bitfld.long 0x10 11. " RFULL_CYCLE ,Receive full cycle mode" "Half-cycle,Full-cycle"
|
|
bitfld.long 0x10 3. " RDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " RDISABLE ,Receive disable" "Not stopped,Stopped"
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP Transmit Buffer Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "MCBSPLP_RBUFFSTAT_REG,McBSPLP Receive Buffer Status"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RBUFFSTAT ,Receive buffer status"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "MCBSPLP_SSELCR_REG,McBSPLP Sidetone Select Register"
|
|
bitfld.long 0x00 10. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " OCH1ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OCH0ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 2.--3. " ICH1ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ICH0ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
rgroup.long 0xc0++0x3
|
|
line.long 0x00 "MCBSPLP_STATUS_REG,McBSPLP Status Register"
|
|
bitfld.long 0x00 0. " CLKMUXSTATUS ,Response to a different register access delayed" "No effect,Delayed"
|
|
width 11.
|
|
tree.end
|
|
tree "SIDETONE_McBSP2"
|
|
base ad:0x49028000
|
|
width 18.
|
|
sif (cpu()!="OMAP3515"&&cpu()!="OMAP3505")
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "ST_REV_REG,SIDETONE Revision Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP Revision"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "ST_SYSCONFIG_REG,SIDETONE System Configuration Register"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Automatic McBSPi_ICLK clock gating" "Disabled,Enabled"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "ST_IRQSTATUS_REG,SIDETONE Interrupt Status Register"
|
|
eventfld.long 0x00 0. " OVRRERROR ,Over-run error occured" "Not occurred,Occurred"
|
|
line.long 0x04 "ST_IRQENABLE_REG,SIDETONE Interrupt Enable Register"
|
|
bitfld.long 0x04 0. " OVRRERROREN ,Over-run error interrupt enable" "Disabled,Enabled"
|
|
group.long 0x24++0xb
|
|
line.long 0x00 "ST_SGAINCR_REG,Sidetone Gain Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CH1GAIN ,Second sidetone channel gain"
|
|
hexmask.long.word 0x00 0.--15. 1. " CH0GAIN ,First sidetone channel gain"
|
|
line.long 0x04 "ST_SFIRCR_REG,Sidetone FIR Coefficients Control Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " FIRCOEFF ,FIR coefficients control register"
|
|
line.long 0x08 "ST_SSELCR_REG,Sidetone Select Register"
|
|
bitfld.long 0x08 2. " COEFFWRDONE ,Write FIR coefficients completed" "Not completed,Completed"
|
|
bitfld.long 0x08 1. " COEFFWREN ,Write enable FIR coefficients" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
width 11.
|
|
tree.end
|
|
tree "McBSP3"
|
|
base ad:0x49024000
|
|
width 23.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "MCBSPLP_DRR_REG,McBSPLP Data Receive Register"
|
|
in
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP Data Transmit Register"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP Serial Port Control Register 2"
|
|
bitfld.long 0x00 9. " FREE ,Free running mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFT ,Soft Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FRST ,Frame-sync generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 6. " GRST ,Sample-rate generator reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " XINTM ,Transmit interrupt mode" "XRDY,End-of-frame,New frame,XSYNCERR"
|
|
bitfld.long 0x00 3. "XSYNCERR ,Transmit synchronization error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XRST ,Transmitter reset" "Reset,Enabled"
|
|
line.long 0x04 "MCBSPLP_SPCR1_REG,McBSPLP Serial Port Control Register 1"
|
|
bitfld.long 0x04 15. " ALB ,Analog loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right-justify and zero-fill MSBs,Right-justify and sign-extend MSBs,Left-justify and zero-fill LSBs,?..."
|
|
textline " "
|
|
bitfld.long 0x04 7. " DXENA ,DX enabler" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RINTM ,Receive interrupt mode" "RRDY,End-of-block/End-of-frame,New frame,RSYNCERR"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RSYNCERR ,Receive synchronization error" "No error,Error"
|
|
bitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0. " RRST ,Receiver reset" "Reset,Enabled"
|
|
line.long 0x08 "MCBSPLP_RCR2_REG,McBSPLP Receive Control Register 2"
|
|
bitfld.long 0x08 15. " RPHASE ,Receive phases" "Single,Dual"
|
|
hexmask.long.byte 0x08 8.--14. 1. " RFRLEN2 ,Receive frame length 2"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " RWDLEN2 ,Receive word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x08 3.--4. " RREVERSE ,Receive reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x0c "MCBSPLP_RCR1_REG,McBSPLP Receive Control Register 1"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RFRLEN1 ,Receive frame length 1"
|
|
bitfld.long 0x0C 5.--7. " RWDLEN1 ,Receive word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
line.long 0x10 "MCBSPLP_XCR2_REG,McBSPLP Transmit Control Register 2"
|
|
bitfld.long 0x10 15. " XPHASE ,Transmit phases" "Single,Dual"
|
|
hexmask.long.byte 0x10 8.--14. 1. " XFRLEN2 ,Transmit frame length 2"
|
|
textline " "
|
|
bitfld.long 0x10 5.--7. " XWDLEN2 ,Transmit word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x10 3.--4. " XREVERSE ,Transmit reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x14 "MCBSPLP_XCR1_REG,McBSPLP Transmit Control Register 1"
|
|
hexmask.long.byte 0x14 8.--14. 1. " XFRLEN1 ,Transmit frame length 1"
|
|
bitfld.long 0x14 5.--7. " XWDLEN1 ,Transmit word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
if ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49024000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x49024000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49024000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x49024000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49024000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x49024000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49024000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x49024000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49024000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x49024000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49024000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x49024000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==1 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49024000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49024000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x49024000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
else
|
|
;CLKSM==1 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
endif
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP SRG Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample rate generator clock divider"
|
|
if (((d.l((ad:0x49024000+0x30)))&0x3)==0x0)
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
else
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 9. " XMCME ,Transmit multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
endif
|
|
if (((d.l((ad:0x49024000+0x34)))&0x1)==0x0)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 9. " RMCME ,Receive multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
endif
|
|
group.long 0x38++0xf
|
|
line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[15] ,Receive channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[14] ,Receive channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[13] ,Receive channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[12] ,Receive channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[11] ,Receive channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[10] ,Receive channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[9] ,Receive channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[8] ,Receive channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[7] ,Receive channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[6] ,Receive channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[5] ,Receive channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[4] ,Receive channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[3] ,Receive channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[2] ,Receive channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[1] ,Receive channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[0] ,Receive channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERB_REG,McBSPLP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x04 15. " RCERB[31] ,Receive channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERB[30] ,Receive channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERB[29] ,Receive channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERB[28] ,Receive channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERB[27] ,Receive channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERB[26] ,Receive channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERB[25] ,Receive channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERB[24] ,Receive channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERB[23] ,Receive channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERA[22] ,Receive channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERA[21] ,Receive channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERA[20] ,Receive channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERA[19] ,Receive channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERA[18] ,Receive channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERA[17] ,Receive channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERA[16] ,Receive channel 16 enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_XCERA_REG,McBSPLP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x08 15. " XCERA[15] ,Transmit channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " XCERA[14] ,Transmit channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " XCERA[13] ,Transmit channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " XCERA[12] ,Transmit channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " XCERA[11] ,Transmit channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XCERA[10] ,Transmit channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " XCERA[9] ,Transmit channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " XCERA[8] ,Transmit channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " XCERA[7] ,Transmit channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " XCERA[6] ,Transmit channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " XCERA[5] ,Transmit channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XCERA[4] ,Transmit channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " XCERA[3] ,Transmit channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " XCERA[2] ,Transmit channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " XCERA[1] ,Transmit channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " XCERA[0] ,Transmit channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x0c "MCBSPLP_XCERB_REG,McBSPLP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x0c 15. " XCERB[31] ,Transmit channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " XCERB[30] ,Transmit channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " XCERB[29] ,Transmit channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " XCERB[28] ,Transmit channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " XCERB[27] ,Transmit channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " XCERB[26] ,Transmit channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " XCERB[25] ,Transmit channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " XCERB[24] ,Transmit channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " XCERB[23] ,Transmit channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " XCERB[22] ,Transmit channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " XCERB[21] ,Transmit channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " XCERB[20] ,Transmit channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " XCERB[19] ,Transmit channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " XCERB[18] ,Transmit channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " XCERB[17] ,Transmit channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " XCERB[16] ,Transmit channel 16 enable" "Disabled,Enabled"
|
|
if ((((d.l((ad:0x49024000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49024000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49024000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49024000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49024000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49024000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x20))
|
|
;xrst==1 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49024000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49024000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49024000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
else
|
|
;xrst==1 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
endif
|
|
if ((((d.l((ad:0x49024000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x49024000+0x34)))&0x1)==0x1))
|
|
group.long 0x4c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " RCERC[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERC[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERC[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERC[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERC[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERC[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERC[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERC[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERC[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERC[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERC[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERC[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERC[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERC[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERC[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERC[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " RCERD[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERD[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERD[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERD[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERD[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERD[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERD[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERD[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERD[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERD[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERD[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERD[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERD[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERD[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERD[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERD[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x4c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x49024000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49024000+0x30)))&0x3)!=0x0))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " XCERC[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERC[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERC[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERC[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERC[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERC[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERC[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERC[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERC[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERC[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERC[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERC[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERC[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERC[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERC[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERC[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " XCERD[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERD[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERD[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERD[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERD[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERD[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERD[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERD[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERD[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERD[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERD[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERD[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERD[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERD[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERD[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERD[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x54++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x49024000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x49024000+0x34)))&0x1)==0x1))
|
|
group.long 0x5c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " RCERE[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERE[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERE[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERE[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERE[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERE[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERE[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERE[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERE[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERE[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERE[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERE[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERE[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERE[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERE[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERE[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " RCERF[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERF[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERF[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERF[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERF[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERF[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERF[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERF[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERF[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERF[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERF[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERF[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERF[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERF[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERF[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERF[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x5c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x49024000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49024000+0x30)))&0x3)!=0x0))
|
|
group.long 0x64++0x7
|
|
line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " XCERE[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERE[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERE[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERE[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERE[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERE[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERE[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERE[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERE[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERE[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERE[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERE[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERE[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERE[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERE[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERE[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " XCERF[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERF[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERF[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERF[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERF[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERF[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERF[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERF[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERF[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERF[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERF[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERF[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERF[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERF[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERF[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERF[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x64++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x49024000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x49024000+0x34)))&0x1)==0x1))
|
|
group.long 0x6c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " RCERG[111],Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERG[110],Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERG[109],Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERG[108],Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERG[107],Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERG[106],Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERG[105],Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERG[104],Receive channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERG[103],Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERG[102],Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERG[101],Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERG[100],Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERG[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERG[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERG[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERG[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " RCERH[127],Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERH[126],Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERH[125],Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERH[124],Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERH[123],Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERH[122],Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERH[121],Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERH[120],Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERH[119],Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERH[118],Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERH[117],Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERH[116],Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERH[115],Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERH[114],Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERH[113],Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERH[112],Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x6c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
endif
|
|
if ((((d.l((ad:0x49024000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49024000+0x30)))&0x3)!=0x0))
|
|
group.long 0x74++0x7
|
|
line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " XCERG[111],Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERG[110],Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERG[109],Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERG[108],Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERG[107],Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERG[106],Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERG[105],Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERG[104],Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERG[103],Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERG[102],Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERG[101],Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERG[100],Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERG[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERG[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERG[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERG[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " XCERH[127],Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERH[126],Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERH[125],Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERH[124],Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERH[123],Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERH[122],Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERH[121],Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERH[120],Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERH[119],Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERH[118],Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERH[117],Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERH[116],Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERH[115],Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERH[114],Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERH[113],Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERH[112],Transmit channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x74++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
endif
|
|
rgroup.long 0x7c++0x3
|
|
line.long 0x00 "MCBSPLP_REV_REG,MCBSPLP Revision Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP Revision"
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP Receive Interrupt Clear"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP Transmit Interrupt Clear"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP Receive Overflow Interrupt Clear"
|
|
in
|
|
group.long 0x8c++0xb
|
|
line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY,Clock activity (McBSPi_ICLK/PRCM)" "Switched off,Switched off/Maintained,Maintained/Switched off,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
line.long 0x04 "MCBSPLP_THRSH2_REG,McBSPLP Transmit Buffer Threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x08 "MCBSPLP_THRSH1_REG,McBSPLP Receive Buffer Threshold"
|
|
hexmask.long.byte 0x08 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
group.long 0xa0++0x13
|
|
line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status Register"
|
|
eventfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " XOVFLEN ,Transmit buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " XUNDFLEN ,Transmit buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDYEN ,Transmit buffer threshold reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " XEOFEN ,Transmit end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSXEN ,Transmit frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " XSYNCERREN ,Transmit frame synchronization error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ROVFLEN ,Receive buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RUNDFLEN ,Receive buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDYEN ,Receive buffer threshold enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REOFEN ,Receive end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSREN ,Receive frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RSYNCERREN ,Receive frame synchronization error enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable Register"
|
|
bitfld.long 0x08 10. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 10. " XRDYEN ,Transmit buffer threshold reached WK enable" "Not active,Active"
|
|
bitfld.long 0x08 9. " XEOFEN ,Transmit end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XFSXEN ,Transmit frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 7. " XSYNCERREN ,Transmit frame synchronization error WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDYEN ,Receive buffer threshold wakeup enable" "Not active,Active"
|
|
bitfld.long 0x08 2. " REOFEN ,Receive end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSREN ,Receive frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 0. " RSYNCERREN ,Receive frame synchronization error WK enable" "Not active,Active"
|
|
line.long 0x0c "MCBSPLP_XCCR_REG,McBSPLP Transmit Configuration Control Register"
|
|
bitfld.long 0x0C 15. " EXTCLKGATE ,External clock gating enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PPCONNECT ,Pair to pair connection" "No connection,Connection"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "18 ns,26 ns,35 ns,42 ns"
|
|
bitfld.long 0x0C 11. " XFULL_CYCLE ,Transmit full cycle mode" "Half-cycle,Full-cycle"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DLB ,Digital loop-back" "No DLB,DLB"
|
|
bitfld.long 0x0C 3. " XDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " XDISABLE ,Transmit disable" "Not stopped,Stopped"
|
|
line.long 0x10 "MCBSPLP_RCCR_REG,McBSPLP Receive Configuration Control Register"
|
|
bitfld.long 0x10 11. " RFULL_CYCLE ,Receive full cycle mode" "Half-cycle,Full-cycle"
|
|
bitfld.long 0x10 3. " RDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " RDISABLE ,Receive disable" "Not stopped,Stopped"
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP Transmit Buffer Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "MCBSPLP_RBUFFSTAT_REG,McBSPLP Receive Buffer Status"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RBUFFSTAT ,Receive buffer status"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "MCBSPLP_SSELCR_REG,McBSPLP Sidetone Select Register"
|
|
bitfld.long 0x00 10. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " OCH1ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OCH0ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 2.--3. " ICH1ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ICH0ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
rgroup.long 0xc0++0x3
|
|
line.long 0x00 "MCBSPLP_STATUS_REG,McBSPLP Status Register"
|
|
bitfld.long 0x00 0. " CLKMUXSTATUS ,Response to a different register access delayed" "No effect,Delayed"
|
|
width 11.
|
|
tree.end
|
|
tree "SIDETONE_McBSP3"
|
|
base ad:0x4902a000
|
|
width 18.
|
|
sif (cpu()!="OMAP3515"&&cpu()!="OMAP3505")
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "ST_REV_REG,SIDETONE Revision Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP Revision"
|
|
endif
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "ST_SYSCONFIG_REG,SIDETONE System Configuration Register"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Automatic McBSPi_ICLK clock gating" "Disabled,Enabled"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "ST_IRQSTATUS_REG,SIDETONE Interrupt Status Register"
|
|
eventfld.long 0x00 0. " OVRRERROR ,Over-run error occured" "Not occurred,Occurred"
|
|
line.long 0x04 "ST_IRQENABLE_REG,SIDETONE Interrupt Enable Register"
|
|
bitfld.long 0x04 0. " OVRRERROREN ,Over-run error interrupt enable" "Disabled,Enabled"
|
|
group.long 0x24++0xb
|
|
line.long 0x00 "ST_SGAINCR_REG,Sidetone Gain Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " CH1GAIN ,Second sidetone channel gain"
|
|
hexmask.long.word 0x00 0.--15. 1. " CH0GAIN ,First sidetone channel gain"
|
|
line.long 0x04 "ST_SFIRCR_REG,Sidetone FIR Coefficients Control Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " FIRCOEFF ,FIR coefficients control register"
|
|
line.long 0x08 "ST_SSELCR_REG,Sidetone Select Register"
|
|
bitfld.long 0x08 2. " COEFFWRDONE ,Write FIR coefficients completed" "Not completed,Completed"
|
|
bitfld.long 0x08 1. " COEFFWREN ,Write enable FIR coefficients" "Read,Write"
|
|
textline " "
|
|
bitfld.long 0x08 0. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
width 11.
|
|
tree.end
|
|
tree "McBSP4"
|
|
base ad:0x49026000
|
|
width 23.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "MCBSPLP_DRR_REG,McBSPLP Data Receive Register"
|
|
in
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP Data Transmit Register"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP Serial Port Control Register 2"
|
|
bitfld.long 0x00 9. " FREE ,Free running mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFT ,Soft Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FRST ,Frame-sync generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 6. " GRST ,Sample-rate generator reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " XINTM ,Transmit interrupt mode" "XRDY,End-of-frame,New frame,XSYNCERR"
|
|
bitfld.long 0x00 3. "XSYNCERR ,Transmit synchronization error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XRST ,Transmitter reset" "Reset,Enabled"
|
|
line.long 0x04 "MCBSPLP_SPCR1_REG,McBSPLP Serial Port Control Register 1"
|
|
bitfld.long 0x04 15. " ALB ,Analog loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right-justify and zero-fill MSBs,Right-justify and sign-extend MSBs,Left-justify and zero-fill LSBs,?..."
|
|
textline " "
|
|
bitfld.long 0x04 7. " DXENA ,DX enabler" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RINTM ,Receive interrupt mode" "RRDY,End-of-block/End-of-frame,New frame,RSYNCERR"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RSYNCERR ,Receive synchronization error" "No error,Error"
|
|
bitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0. " RRST ,Receiver reset" "Reset,Enabled"
|
|
line.long 0x08 "MCBSPLP_RCR2_REG,McBSPLP Receive Control Register 2"
|
|
bitfld.long 0x08 15. " RPHASE ,Receive phases" "Single,Dual"
|
|
hexmask.long.byte 0x08 8.--14. 1. " RFRLEN2 ,Receive frame length 2"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " RWDLEN2 ,Receive word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x08 3.--4. " RREVERSE ,Receive reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x0c "MCBSPLP_RCR1_REG,McBSPLP Receive Control Register 1"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RFRLEN1 ,Receive frame length 1"
|
|
bitfld.long 0x0C 5.--7. " RWDLEN1 ,Receive word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
line.long 0x10 "MCBSPLP_XCR2_REG,McBSPLP Transmit Control Register 2"
|
|
bitfld.long 0x10 15. " XPHASE ,Transmit phases" "Single,Dual"
|
|
hexmask.long.byte 0x10 8.--14. 1. " XFRLEN2 ,Transmit frame length 2"
|
|
textline " "
|
|
bitfld.long 0x10 5.--7. " XWDLEN2 ,Transmit word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x10 3.--4. " XREVERSE ,Transmit reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x14 "MCBSPLP_XCR1_REG,McBSPLP Transmit Control Register 1"
|
|
hexmask.long.byte 0x14 8.--14. 1. " XFRLEN1 ,Transmit frame length 1"
|
|
bitfld.long 0x14 5.--7. " XWDLEN1 ,Transmit word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
if ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49026000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x49026000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49026000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x49026000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49026000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x49026000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x49026000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x49026000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49026000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x49026000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49026000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x49026000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==1 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x49026000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x49026000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x49026000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
else
|
|
;CLKSM==1 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
endif
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP SRG Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample rate generator clock divider"
|
|
if (((d.l((ad:0x49026000+0x30)))&0x3)==0x0)
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
else
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 9. " XMCME ,Transmit multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
endif
|
|
if (((d.l((ad:0x49026000+0x34)))&0x1)==0x0)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 9. " RMCME ,Receive multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
endif
|
|
group.long 0x38++0xf
|
|
line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[15] ,Receive channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[14] ,Receive channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[13] ,Receive channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[12] ,Receive channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[11] ,Receive channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[10] ,Receive channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[9] ,Receive channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[8] ,Receive channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[7] ,Receive channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[6] ,Receive channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[5] ,Receive channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[4] ,Receive channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[3] ,Receive channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[2] ,Receive channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[1] ,Receive channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[0] ,Receive channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERB_REG,McBSPLP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x04 15. " RCERB[31] ,Receive channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERB[30] ,Receive channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERB[29] ,Receive channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERB[28] ,Receive channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERB[27] ,Receive channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERB[26] ,Receive channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERB[25] ,Receive channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERB[24] ,Receive channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERB[23] ,Receive channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERA[22] ,Receive channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERA[21] ,Receive channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERA[20] ,Receive channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERA[19] ,Receive channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERA[18] ,Receive channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERA[17] ,Receive channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERA[16] ,Receive channel 16 enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_XCERA_REG,McBSPLP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x08 15. " XCERA[15] ,Transmit channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " XCERA[14] ,Transmit channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " XCERA[13] ,Transmit channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " XCERA[12] ,Transmit channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " XCERA[11] ,Transmit channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XCERA[10] ,Transmit channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " XCERA[9] ,Transmit channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " XCERA[8] ,Transmit channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " XCERA[7] ,Transmit channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " XCERA[6] ,Transmit channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " XCERA[5] ,Transmit channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XCERA[4] ,Transmit channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " XCERA[3] ,Transmit channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " XCERA[2] ,Transmit channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " XCERA[1] ,Transmit channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " XCERA[0] ,Transmit channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x0c "MCBSPLP_XCERB_REG,McBSPLP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x0c 15. " XCERB[31] ,Transmit channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " XCERB[30] ,Transmit channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " XCERB[29] ,Transmit channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " XCERB[28] ,Transmit channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " XCERB[27] ,Transmit channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " XCERB[26] ,Transmit channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " XCERB[25] ,Transmit channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " XCERB[24] ,Transmit channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " XCERB[23] ,Transmit channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " XCERB[22] ,Transmit channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " XCERB[21] ,Transmit channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " XCERB[20] ,Transmit channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " XCERB[19] ,Transmit channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " XCERB[18] ,Transmit channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " XCERB[17] ,Transmit channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " XCERB[16] ,Transmit channel 16 enable" "Disabled,Enabled"
|
|
if ((((d.l((ad:0x49026000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49026000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49026000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49026000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49026000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49026000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x20))
|
|
;xrst==1 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x49026000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x49026000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x49026000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
else
|
|
;xrst==1 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
endif
|
|
if ((((d.l((ad:0x49026000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x49026000+0x34)))&0x1)==0x1))
|
|
group.long 0x4c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " RCERC[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERC[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERC[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERC[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERC[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERC[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERC[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERC[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERC[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERC[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERC[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERC[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERC[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERC[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERC[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERC[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " RCERD[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERD[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERD[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERD[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERD[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERD[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERD[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERD[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERD[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERD[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERD[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERD[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERD[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERD[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERD[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERD[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x4c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x49026000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49026000+0x30)))&0x3)!=0x0))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " XCERC[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERC[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERC[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERC[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERC[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERC[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERC[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERC[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERC[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERC[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERC[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERC[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERC[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERC[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERC[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERC[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " XCERD[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERD[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERD[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERD[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERD[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERD[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERD[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERD[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERD[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERD[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERD[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERD[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERD[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERD[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERD[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERD[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x54++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x49026000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x49026000+0x34)))&0x1)==0x1))
|
|
group.long 0x5c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " RCERE[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERE[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERE[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERE[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERE[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERE[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERE[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERE[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERE[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERE[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERE[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERE[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERE[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERE[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERE[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERE[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " RCERF[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERF[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERF[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERF[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERF[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERF[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERF[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERF[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERF[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERF[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERF[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERF[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERF[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERF[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERF[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERF[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x5c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x49026000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49026000+0x30)))&0x3)!=0x0))
|
|
group.long 0x64++0x7
|
|
line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " XCERE[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERE[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERE[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERE[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERE[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERE[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERE[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERE[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERE[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERE[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERE[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERE[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERE[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERE[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERE[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERE[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " XCERF[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERF[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERF[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERF[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERF[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERF[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERF[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERF[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERF[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERF[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERF[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERF[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERF[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERF[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERF[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERF[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x64++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x49026000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x49026000+0x34)))&0x1)==0x1))
|
|
group.long 0x6c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " RCERG[111],Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERG[110],Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERG[109],Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERG[108],Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERG[107],Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERG[106],Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERG[105],Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERG[104],Receive channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERG[103],Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERG[102],Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERG[101],Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERG[100],Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERG[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERG[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERG[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERG[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " RCERH[127],Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERH[126],Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERH[125],Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERH[124],Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERH[123],Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERH[122],Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERH[121],Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERH[120],Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERH[119],Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERH[118],Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERH[117],Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERH[116],Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERH[115],Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERH[114],Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERH[113],Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERH[112],Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x6c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
endif
|
|
if ((((d.l((ad:0x49026000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x49026000+0x30)))&0x3)!=0x0))
|
|
group.long 0x74++0x7
|
|
line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " XCERG[111],Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERG[110],Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERG[109],Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERG[108],Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERG[107],Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERG[106],Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERG[105],Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERG[104],Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERG[103],Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERG[102],Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERG[101],Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERG[100],Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERG[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERG[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERG[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERG[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " XCERH[127],Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERH[126],Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERH[125],Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERH[124],Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERH[123],Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERH[122],Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERH[121],Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERH[120],Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERH[119],Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERH[118],Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERH[117],Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERH[116],Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERH[115],Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERH[114],Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERH[113],Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERH[112],Transmit channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x74++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
endif
|
|
rgroup.long 0x7c++0x3
|
|
line.long 0x00 "MCBSPLP_REV_REG,MCBSPLP Revision Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP Revision"
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP Receive Interrupt Clear"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP Transmit Interrupt Clear"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP Receive Overflow Interrupt Clear"
|
|
in
|
|
group.long 0x8c++0xb
|
|
line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY,Clock activity (McBSPi_ICLK/PRCM)" "Switched off,Switched off/Maintained,Maintained/Switched off,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
line.long 0x04 "MCBSPLP_THRSH2_REG,McBSPLP Transmit Buffer Threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x08 "MCBSPLP_THRSH1_REG,McBSPLP Receive Buffer Threshold"
|
|
hexmask.long.byte 0x08 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
group.long 0xa0++0x13
|
|
line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status Register"
|
|
eventfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " XOVFLEN ,Transmit buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " XUNDFLEN ,Transmit buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDYEN ,Transmit buffer threshold reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " XEOFEN ,Transmit end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSXEN ,Transmit frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " XSYNCERREN ,Transmit frame synchronization error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ROVFLEN ,Receive buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RUNDFLEN ,Receive buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDYEN ,Receive buffer threshold enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REOFEN ,Receive end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSREN ,Receive frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RSYNCERREN ,Receive frame synchronization error enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable Register"
|
|
bitfld.long 0x08 10. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 10. " XRDYEN ,Transmit buffer threshold reached WK enable" "Not active,Active"
|
|
bitfld.long 0x08 9. " XEOFEN ,Transmit end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XFSXEN ,Transmit frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 7. " XSYNCERREN ,Transmit frame synchronization error WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDYEN ,Receive buffer threshold wakeup enable" "Not active,Active"
|
|
bitfld.long 0x08 2. " REOFEN ,Receive end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSREN ,Receive frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 0. " RSYNCERREN ,Receive frame synchronization error WK enable" "Not active,Active"
|
|
line.long 0x0c "MCBSPLP_XCCR_REG,McBSPLP Transmit Configuration Control Register"
|
|
bitfld.long 0x0C 15. " EXTCLKGATE ,External clock gating enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PPCONNECT ,Pair to pair connection" "No connection,Connection"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "18 ns,26 ns,35 ns,42 ns"
|
|
bitfld.long 0x0C 11. " XFULL_CYCLE ,Transmit full cycle mode" "Half-cycle,Full-cycle"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DLB ,Digital loop-back" "No DLB,DLB"
|
|
bitfld.long 0x0C 3. " XDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " XDISABLE ,Transmit disable" "Not stopped,Stopped"
|
|
line.long 0x10 "MCBSPLP_RCCR_REG,McBSPLP Receive Configuration Control Register"
|
|
bitfld.long 0x10 11. " RFULL_CYCLE ,Receive full cycle mode" "Half-cycle,Full-cycle"
|
|
bitfld.long 0x10 3. " RDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " RDISABLE ,Receive disable" "Not stopped,Stopped"
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP Transmit Buffer Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "MCBSPLP_RBUFFSTAT_REG,McBSPLP Receive Buffer Status"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RBUFFSTAT ,Receive buffer status"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "MCBSPLP_SSELCR_REG,McBSPLP Sidetone Select Register"
|
|
bitfld.long 0x00 10. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " OCH1ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OCH0ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 2.--3. " ICH1ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ICH0ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
rgroup.long 0xc0++0x3
|
|
line.long 0x00 "MCBSPLP_STATUS_REG,McBSPLP Status Register"
|
|
bitfld.long 0x00 0. " CLKMUXSTATUS ,Response to a different register access delayed" "No effect,Delayed"
|
|
width 11.
|
|
tree.end
|
|
tree "McBSP5"
|
|
base ad:0x48096000
|
|
width 23.
|
|
hgroup.long 0x00++0x3
|
|
hide.long 0x00 "MCBSPLP_DRR_REG,McBSPLP Data Receive Register"
|
|
in
|
|
wgroup.long 0x08++0x3
|
|
line.long 0x00 "MCBSPLP_DXR_REG,McBSPLP Data Transmit Register"
|
|
group.long 0x10++0x17
|
|
line.long 0x00 "MCBSPLP_SPCR2_REG,McBSPLP Serial Port Control Register 2"
|
|
bitfld.long 0x00 9. " FREE ,Free running mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " SOFT ,Soft Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FRST ,Frame-sync generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 6. " GRST ,Sample-rate generator reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " XINTM ,Transmit interrupt mode" "XRDY,End-of-frame,New frame,XSYNCERR"
|
|
bitfld.long 0x00 3. "XSYNCERR ,Transmit synchronization error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
|
|
bitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XRST ,Transmitter reset" "Reset,Enabled"
|
|
line.long 0x04 "MCBSPLP_SPCR1_REG,McBSPLP Serial Port Control Register 1"
|
|
bitfld.long 0x04 15. " ALB ,Analog loopback mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right-justify and zero-fill MSBs,Right-justify and sign-extend MSBs,Left-justify and zero-fill LSBs,?..."
|
|
textline " "
|
|
bitfld.long 0x04 7. " DXENA ,DX enabler" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x04 4.--5. " RINTM ,Receive interrupt mode" "RRDY,End-of-block/End-of-frame,New frame,RSYNCERR"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RSYNCERR ,Receive synchronization error" "No error,Error"
|
|
bitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
bitfld.long 0x04 0. " RRST ,Receiver reset" "Reset,Enabled"
|
|
line.long 0x08 "MCBSPLP_RCR2_REG,McBSPLP Receive Control Register 2"
|
|
bitfld.long 0x08 15. " RPHASE ,Receive phases" "Single,Dual"
|
|
hexmask.long.byte 0x08 8.--14. 1. " RFRLEN2 ,Receive frame length 2"
|
|
textline " "
|
|
bitfld.long 0x08 5.--7. " RWDLEN2 ,Receive word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x08 3.--4. " RREVERSE ,Receive reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x0c "MCBSPLP_RCR1_REG,McBSPLP Receive Control Register 1"
|
|
hexmask.long.byte 0x0C 8.--14. 1. " RFRLEN1 ,Receive frame length 1"
|
|
bitfld.long 0x0C 5.--7. " RWDLEN1 ,Receive word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
line.long 0x10 "MCBSPLP_XCR2_REG,McBSPLP Transmit Control Register 2"
|
|
bitfld.long 0x10 15. " XPHASE ,Transmit phases" "Single,Dual"
|
|
hexmask.long.byte 0x10 8.--14. 1. " XFRLEN2 ,Transmit frame length 2"
|
|
textline " "
|
|
bitfld.long 0x10 5.--7. " XWDLEN2 ,Transmit word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
bitfld.long 0x10 3.--4. " XREVERSE ,Transmit reverse mode" "MSB first,LSB first,?..."
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
|
|
line.long 0x14 "MCBSPLP_XCR1_REG,McBSPLP Transmit Control Register 1"
|
|
hexmask.long.byte 0x14 8.--14. 1. " XFRLEN1 ,Transmit frame length 1"
|
|
bitfld.long 0x14 5.--7. " XWDLEN1 ,Transmit word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
|
|
if ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48096000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x48096000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48096000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x48096000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==0 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48096000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x48096000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x48096000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x48096000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==0 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
|
|
textline " "
|
|
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x48096000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x48096000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x48096000+0x48)))&0x80)==0x80)&&((((d.l((ad:0x48096000+0x48)))&0x800)==0x0))))
|
|
;CLKSM==1 && SCKLME==1 && FSXM==0
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
elif ((((d.l((ad:0x48096000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x48096000+0x48)))&0x80)==0x0)&&((((d.l((ad:0x48096000+0x48)))&0x800)==0x800))))
|
|
;CLKSM==1 && SCKLME==0 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
else
|
|
;CLKSM==1 && SCKLME==1 && FSXM==1
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR2_REG,McBSPLP SRG Register 2"
|
|
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
|
|
textline " "
|
|
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
|
|
endif
|
|
group.long 0x2c++0x3
|
|
line.long 0x00 "MCBSPLP_SRGR1_REG,McBSPLP SRG Register 1"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame width"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample rate generator clock divider"
|
|
if (((d.l((ad:0x48096000+0x30)))&0x3)==0x0)
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
else
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "MCBSPLP_MCR2_REG,McBSPLP Multi Channel Register 2"
|
|
bitfld.long 0x00 9. " XMCME ,Transmit multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
|
|
endif
|
|
if (((d.l((ad:0x48096000+0x34)))&0x1)==0x0)
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
else
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "MCBSPLP_MCR1_REG,McBSPLP Multi Channel Register 1"
|
|
bitfld.long 0x00 9. " RMCME ,Receive multichannel partition mode" "2-partition,8-partition"
|
|
bitfld.long 0x00 7.--8. "RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
|
|
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
|
|
endif
|
|
group.long 0x38++0xf
|
|
line.long 0x00 "MCBSPLP_RCERA_REG,McBSPLP Receive Channel Enable Register Partition A"
|
|
bitfld.long 0x00 15. " RCERA[15] ,Receive channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERA[14] ,Receive channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERA[13] ,Receive channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERA[12] ,Receive channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERA[11] ,Receive channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERA[10] ,Receive channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERA[9] ,Receive channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERA[8] ,Receive channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERA[7] ,Receive channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERA[6] ,Receive channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERA[5] ,Receive channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERA[4] ,Receive channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERA[3] ,Receive channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERA[2] ,Receive channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERA[1] ,Receive channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERA[0] ,Receive channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERB_REG,McBSPLP Receive Channel Enable Register Partition B"
|
|
bitfld.long 0x04 15. " RCERB[31] ,Receive channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERB[30] ,Receive channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERB[29] ,Receive channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERB[28] ,Receive channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERB[27] ,Receive channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERB[26] ,Receive channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERB[25] ,Receive channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERB[24] ,Receive channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERB[23] ,Receive channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERA[22] ,Receive channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERA[21] ,Receive channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERA[20] ,Receive channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERA[19] ,Receive channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERA[18] ,Receive channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERA[17] ,Receive channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERA[16] ,Receive channel 16 enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_XCERA_REG,McBSPLP Transmit Channel Enable Register Partition A"
|
|
bitfld.long 0x08 15. " XCERA[15] ,Transmit channel 15 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " XCERA[14] ,Transmit channel 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " XCERA[13] ,Transmit channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " XCERA[12] ,Transmit channel 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " XCERA[11] ,Transmit channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " XCERA[10] ,Transmit channel 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " XCERA[9] ,Transmit channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " XCERA[8] ,Transmit channel 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " XCERA[7] ,Transmit channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " XCERA[6] ,Transmit channel 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " XCERA[5] ,Transmit channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " XCERA[4] ,Transmit channel 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " XCERA[3] ,Transmit channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " XCERA[2] ,Transmit channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " XCERA[1] ,Transmit channel 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " XCERA[0] ,Transmit channel 0 enable" "Disabled,Enabled"
|
|
line.long 0x0c "MCBSPLP_XCERB_REG,McBSPLP Transmit Channel Enable Register Partition B"
|
|
bitfld.long 0x0c 15. " XCERB[31] ,Transmit channel 31 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " XCERB[30] ,Transmit channel 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " XCERB[29] ,Transmit channel 29 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " XCERB[28] ,Transmit channel 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " XCERB[27] ,Transmit channel 27 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " XCERB[26] ,Transmit channel 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " XCERB[25] ,Transmit channel 25 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " XCERB[24] ,Transmit channel 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " XCERB[23] ,Transmit channel 23 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " XCERB[22] ,Transmit channel 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " XCERB[21] ,Transmit channel 21 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " XCERB[20] ,Transmit channel 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " XCERB[19] ,Transmit channel 19 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " XCERB[18] ,Transmit channel 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " XCERB[17] ,Transmit channel 17 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " XCERB[16] ,Transmit channel 16 enable" "Disabled,Enabled"
|
|
if ((((d.l((ad:0x48096000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48096000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48096000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x0))
|
|
;xrst==0 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48096000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x20))
|
|
;xrst==0 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48096000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==0 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48096000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x20))
|
|
;xrst==1 && rrst==0 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
elif ((((d.l((ad:0x48096000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x48096000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x48096000+0xac)))&0x20)==0x0))
|
|
;xrst==1 && rrst==1 && DLB==0
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
else
|
|
;xrst==1 && rrst==1 && DLB==1
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "MCBSPLP_PCR_REG,McBSPLP Pin Control Register"
|
|
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
|
|
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
|
|
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
|
|
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
|
|
endif
|
|
if ((((d.l((ad:0x48096000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x48096000+0x34)))&0x1)==0x1))
|
|
group.long 0x4c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " RCERC[47] ,Receive channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERC[46] ,Receive channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERC[45] ,Receive channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERC[44] ,Receive channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERC[43] ,Receive channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERC[42] ,Receive channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERC[41] ,Receive channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERC[40] ,Receive channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERC[39] ,Receive channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERC[38] ,Receive channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERC[37] ,Receive channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERC[36] ,Receive channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERC[35] ,Receive channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERC[34] ,Receive channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERC[33] ,Receive channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERC[32] ,Receive channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " RCERD[63] ,Receive channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERD[62] ,Receive channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERD[61] ,Receive channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERD[60] ,Receive channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERD[59] ,Receive channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERD[58] ,Receive channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERD[57] ,Receive channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERD[56] ,Receive channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERD[55] ,Receive channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERD[54] ,Receive channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERD[53] ,Receive channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERD[52] ,Receive channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERD[51] ,Receive channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERD[50] ,Receive channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERD[49] ,Receive channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERD[48] ,Receive channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x4c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERC_REG,McBSPLP Receive Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_RCERD_REG,McBSPLP Receive Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x48096000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x48096000+0x30)))&0x3)!=0x0))
|
|
group.long 0x54++0x7
|
|
line.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
bitfld.long 0x00 15. " XCERC[47] ,Transmit channel 47 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERC[46] ,Transmit channel 46 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERC[45] ,Transmit channel 45 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERC[44] ,Transmit channel 44 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERC[43] ,Transmit channel 43 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERC[42] ,Transmit channel 42 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERC[41] ,Transmit channel 41 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERC[40] ,Transmit channel 40 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERC[39] ,Transmit channel 39 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERC[38] ,Transmit channel 38 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERC[37] ,Transmit channel 37 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERC[36] ,Transmit channel 36 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERC[35] ,Transmit channel 35 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERC[34] ,Transmit channel 34 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERC[33] ,Transmit channel 33 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERC[32] ,Transmit channel 32 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
bitfld.long 0x04 15. " XCERD[63] ,Transmit channel 63 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERD[62] ,Transmit channel 62 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERD[61] ,Transmit channel 61 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERD[60] ,Transmit channel 60 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERD[59] ,Transmit channel 59 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERD[58] ,Transmit channel 58 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERD[57] ,Transmit channel 57 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERD[56] ,Transmit channel 56 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERD[55] ,Transmit channel 55 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERD[54] ,Transmit channel 54 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERD[53] ,Transmit channel 53 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERD[52] ,Transmit channel 52 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERD[51] ,Transmit channel 51 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERD[50] ,Transmit channel 50 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERD[49] ,Transmit channel 49 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERD[48] ,Transmit channel 48 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x54++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERC_REG,McBSPLP Transmit Channel Enable Register Partition C"
|
|
hide.long 0x04 "MCBSPLP_XCERD_REG,McBSPLP Transmit Channel Enable Register Partition D"
|
|
endif
|
|
if ((((d.l((ad:0x48096000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x48096000+0x34)))&0x1)==0x1))
|
|
group.long 0x5c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " RCERE[79] ,Receive channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERE[78] ,Receive channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERE[77] ,Receive channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERE[76] ,Receive channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERE[75] ,Receive channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERE[74] ,Receive channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERE[73] ,Receive channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERE[72] ,Receive channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERE[71] ,Receive channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERE[70] ,Receive channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERE[69] ,Receive channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERE[68] ,Receive channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERE[67] ,Receive channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERE[66] ,Receive channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERE[65] ,Receive channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERE[64] ,Receive channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " RCERF[95] ,Receive channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERF[94] ,Receive channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERF[93] ,Receive channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERF[92] ,Receive channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERF[91] ,Receive channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERF[90] ,Receive channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERF[89] ,Receive channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERF[88] ,Receive channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERF[87] ,Receive channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERF[86] ,Receive channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERF[85] ,Receive channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERF[84] ,Receive channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERF[83] ,Receive channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERF[82] ,Receive channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERF[81] ,Receive channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERF[80] ,Receive channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x5c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERE_REG,McBSPLP Receive Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_RCERF_REG,McBSPLP Receive Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x48096000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x48096000+0x30)))&0x3)!=0x0))
|
|
group.long 0x64++0x7
|
|
line.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
bitfld.long 0x00 15. " XCERE[79] ,Transmit channel 79 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERE[78] ,Transmit channel 78 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERE[77] ,Transmit channel 77 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERE[76] ,Transmit channel 76 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERE[75] ,Transmit channel 75 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERE[74] ,Transmit channel 74 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERE[73] ,Transmit channel 73 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERE[72] ,Transmit channel 72 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERE[71] ,Transmit channel 71 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERE[70] ,Transmit channel 70 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERE[69] ,Transmit channel 69 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERE[68] ,Transmit channel 68 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERE[67] ,Transmit channel 67 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERE[66] ,Transmit channel 66 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERE[65] ,Transmit channel 65 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERE[64] ,Transmit channel 64 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
bitfld.long 0x04 15. " XCERF[95] ,Transmit channel 95 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERF[94] ,Transmit channel 94 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERF[93] ,Transmit channel 93 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERF[92] ,Transmit channel 92 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERF[91] ,Transmit channel 91 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERF[90] ,Transmit channel 90 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERF[89] ,Transmit channel 89 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERF[88] ,Transmit channel 88 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERF[87] ,Transmit channel 87 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERF[86] ,Transmit channel 86 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERF[85] ,Transmit channel 85 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERF[84] ,Transmit channel 84 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERF[83] ,Transmit channel 83 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERF[82] ,Transmit channel 82 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERF[81] ,Transmit channel 81 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERF[80] ,Transmit channel 80 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x64++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERE_REG,McBSPLP Transmit Channel Enable Register Partition E"
|
|
hide.long 0x04 "MCBSPLP_XCERF_REG,McBSPLP Transmit Channel Enable Register Partition F"
|
|
endif
|
|
if ((((d.l((ad:0x48096000+0x34)))&0x200)==0x200)&&(((d.l((ad:0x48096000+0x34)))&0x1)==0x1))
|
|
group.long 0x6c++0x7
|
|
line.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " RCERG[111],Receive channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " RCERG[110],Receive channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RCERG[109],Receive channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RCERG[108],Receive channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RCERG[107],Receive channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RCERG[106],Receive channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " RCERG[105],Receive channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RCERG[104],Receive channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " RCERG[103],Receive channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RCERG[102],Receive channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RCERG[101],Receive channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RCERG[100],Receive channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RCERG[99] ,Receive channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RCERG[98] ,Receive channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RCERG[97] ,Receive channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " RCERG[96] ,Receive channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " RCERH[127],Receive channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " RCERH[126],Receive channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RCERH[125],Receive channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " RCERH[124],Receive channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RCERH[123],Receive channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " RCERH[122],Receive channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " RCERH[121],Receive channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " RCERH[120],Receive channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RCERH[119],Receive channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " RCERH[118],Receive channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " RCERH[117],Receive channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RCERH[116],Receive channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RCERH[115],Receive channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " RCERH[114],Receive channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RCERH[113],Receive channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RCERH[112],Receive channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x6c++0x7
|
|
hide.long 0x00 "MCBSPLP_RCERG_REG,McBSPLP Receive Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_RCERH_REG,McBSPLP Receive Channel Enable Register Partition H"
|
|
endif
|
|
if ((((d.l((ad:0x48096000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x48096000+0x30)))&0x3)!=0x0))
|
|
group.long 0x74++0x7
|
|
line.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
bitfld.long 0x00 15. " XCERG[111],Transmit channel 111 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " XCERG[110],Transmit channel 110 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " XCERG[109],Transmit channel 109 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " XCERG[108],Transmit channel 108 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " XCERG[107],Transmit channel 107 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " XCERG[106],Transmit channel 106 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " XCERG[105],Transmit channel 105 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " XCERG[104],Transmit channel 104 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " XCERG[103],Transmit channel 103 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " XCERG[102],Transmit channel 102 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " XCERG[101],Transmit channel 101 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " XCERG[100],Transmit channel 100 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " XCERG[99] ,Transmit channel 99 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " XCERG[98] ,Transmit channel 98 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " XCERG[97] ,Transmit channel 97 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " XCERG[96] ,Transmit channel 96 enable" "Disabled,Enabled"
|
|
line.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
bitfld.long 0x04 15. " XCERH[127],Transmit channel 127 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " XCERH[126],Transmit channel 126 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " XCERH[125],Transmit channel 125 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " XCERH[124],Transmit channel 124 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " XCERH[123],Transmit channel 123 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " XCERH[122],Transmit channel 122 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " XCERH[121],Transmit channel 121 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " XCERH[120],Transmit channel 120 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " XCERH[119],Transmit channel 119 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " XCERH[118],Transmit channel 118 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " XCERH[117],Transmit channel 117 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " XCERH[116],Transmit channel 116 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " XCERH[115],Transmit channel 115 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " XCERH[114],Transmit channel 114 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " XCERH[113],Transmit channel 113 enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " XCERH[112],Transmit channel 112 enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x74++0x7
|
|
hide.long 0x00 "MCBSPLP_XCERG_REG,McBSPLP Transmit Channel Enable Register Partition G"
|
|
hide.long 0x04 "MCBSPLP_XCERH_REG,McBSPLP Transmit Channel Enable Register Partition H"
|
|
endif
|
|
rgroup.long 0x7c++0x3
|
|
line.long 0x00 "MCBSPLP_REV_REG,MCBSPLP Revision Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP Revision"
|
|
hgroup.long 0x80++0x3
|
|
hide.long 0x00 "MCBSPLP_RINTCLR_REG,McBSPLP Receive Interrupt Clear"
|
|
in
|
|
hgroup.long 0x84++0x3
|
|
hide.long 0x00 "MCBSPLP_XINTCLR_REG,McBSPLP Transmit Interrupt Clear"
|
|
in
|
|
hgroup.long 0x88++0x3
|
|
hide.long 0x00 "MCBSPLP_ROVFLCLR_REG,McBSPLP Receive Overflow Interrupt Clear"
|
|
in
|
|
group.long 0x8c++0xb
|
|
line.long 0x00 "MCBSPLP_SYSCONFIG_REG,McBSPLP System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY,Clock activity (McBSPi_ICLK/PRCM)" "Switched off,Switched off/Maintained,Maintained/Switched off,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
|
|
line.long 0x04 "MCBSPLP_THRSH2_REG,McBSPLP Transmit Buffer Threshold"
|
|
hexmask.long.byte 0x04 0.--6. 1. " XTHRESHOLD ,Transmit buffer threshold value"
|
|
line.long 0x08 "MCBSPLP_THRSH1_REG,McBSPLP Receive Buffer Threshold"
|
|
hexmask.long.byte 0x08 0.--6. 1. " RTHRESHOLD ,Receive buffer threshold value"
|
|
group.long 0xa0++0x13
|
|
line.long 0x00 "MCBSPLP_IRQSTATUS_REG,McBSPLP Interrupt Status Register"
|
|
eventfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
|
|
textline " "
|
|
eventfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
|
|
textline " "
|
|
eventfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
|
|
textline " "
|
|
eventfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
|
|
textline " "
|
|
eventfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
|
|
line.long 0x04 "MCBSPLP_IRQENABLE_REG,McBSPLP Interrupt Enable Register"
|
|
bitfld.long 0x04 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " XOVFLEN ,Transmit buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " XUNDFLEN ,Transmit buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 10. " XRDYEN ,Transmit buffer threshold reached enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " XEOFEN ,Transmit end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " XFSXEN ,Transmit frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " XSYNCERREN ,Transmit frame synchronization error enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " ROVFLEN ,Receive buffer overflow enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " RUNDFLEN ,Receive buffer underflow enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " RRDYEN ,Receive buffer threshold enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " REOFEN ,Receive end of frame enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RFSREN ,Receive frame synchronization enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " RSYNCERREN ,Receive frame synchronization error enable" "Disabled,Enabled"
|
|
line.long 0x08 "MCBSPLP_WAKEUPEN_REG,McBSPLP Wakeup Enable Register"
|
|
bitfld.long 0x08 10. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 10. " XRDYEN ,Transmit buffer threshold reached WK enable" "Not active,Active"
|
|
bitfld.long 0x08 9. " XEOFEN ,Transmit end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 8. " XFSXEN ,Transmit frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 7. " XSYNCERREN ,Transmit frame synchronization error WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RRDYEN ,Receive buffer threshold wakeup enable" "Not active,Active"
|
|
bitfld.long 0x08 2. " REOFEN ,Receive end of frame WK enable" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RFSREN ,Receive frame synchronization WK enable" "Not active,Active"
|
|
bitfld.long 0x08 0. " RSYNCERREN ,Receive frame synchronization error WK enable" "Not active,Active"
|
|
line.long 0x0c "MCBSPLP_XCCR_REG,McBSPLP Transmit Configuration Control Register"
|
|
bitfld.long 0x0C 15. " EXTCLKGATE ,External clock gating enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " PPCONNECT ,Pair to pair connection" "No connection,Connection"
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "18 ns,26 ns,35 ns,42 ns"
|
|
bitfld.long 0x0C 11. " XFULL_CYCLE ,Transmit full cycle mode" "Half-cycle,Full-cycle"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " DLB ,Digital loop-back" "No DLB,DLB"
|
|
bitfld.long 0x0C 3. " XDMAEN ,Transmit DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " XDISABLE ,Transmit disable" "Not stopped,Stopped"
|
|
line.long 0x10 "MCBSPLP_RCCR_REG,McBSPLP Receive Configuration Control Register"
|
|
bitfld.long 0x10 11. " RFULL_CYCLE ,Receive full cycle mode" "Half-cycle,Full-cycle"
|
|
bitfld.long 0x10 3. " RDMAEN ,Receive DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " RDISABLE ,Receive disable" "Not stopped,Stopped"
|
|
rgroup.long 0xb4++0x7
|
|
line.long 0x00 "MCBSPLP_XBUFFSTAT_REG,McBSPLP Transmit Buffer Status"
|
|
hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit buffer status"
|
|
line.long 0x04 "MCBSPLP_RBUFFSTAT_REG,McBSPLP Receive Buffer Status"
|
|
hexmask.long.byte 0x04 0.--7. 1. " RBUFFSTAT ,Receive buffer status"
|
|
group.long 0xbc++0x3
|
|
line.long 0x00 "MCBSPLP_SSELCR_REG,McBSPLP Sidetone Select Register"
|
|
bitfld.long 0x00 10. " SIDETONEEN ,Sidetone mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7.--9. " OCH1ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " OCH0ASSIGN ,Map the data for the speaker out channels" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 2.--3. " ICH1ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ICH0ASSIGN ,Map the data from digital microphone channels" "1,2,3,4"
|
|
rgroup.long 0xc0++0x3
|
|
line.long 0x00 "MCBSPLP_STATUS_REG,McBSPLP Status Register"
|
|
bitfld.long 0x00 0. " CLKMUXSTATUS ,Response to a different register access delayed" "No effect,Delayed"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree.open "MMC/SD/SDIO Card Interface"
|
|
tree "MMCHS1"
|
|
base ad:0x4809c000
|
|
width 17.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MMCHS_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "MMCHS_CSRE,Card Status Response Error"
|
|
bitfld.long 0x00 31. " CSRE[31] ,Card status response error bit 31" "No error,Error"
|
|
bitfld.long 0x00 30. " CSRE[30] ,Card status response error bit 30" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CSRE[29] ,Card status response error bit 29" "No error,Error"
|
|
bitfld.long 0x00 28. " CSRE[28] ,Card status response error bit 28" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CSRE[27] ,Card status response error bit 27" "No error,Error"
|
|
bitfld.long 0x00 26. " CSRE[26] ,Card status response error bit 26" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CSRE[25] ,Card status response error bit 25" "No error,Error"
|
|
bitfld.long 0x00 24. " CSRE[24] ,Card status response error bit 24" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CSRE[23] ,Card status response error bit 23" "No error,Error"
|
|
bitfld.long 0x00 22. " CSRE[22] ,Card status response error bit 22" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CSRE[21] ,Card status response error bit 21" "No error,Error"
|
|
bitfld.long 0x00 20. " CSRE[20] ,Card status response error bit 20" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSRE[19] ,Card status response error bit 19" "No error,Error"
|
|
bitfld.long 0x00 18. " CSRE[18] ,Card status response error bit 18" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CSRE[17] ,Card status response error bit 17" "No error,Error"
|
|
bitfld.long 0x00 16. " CSRE[16] ,Card status response error bit 16" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CSRE[15] ,Card status response error bit 15" "No error,Error"
|
|
bitfld.long 0x00 14. " CSRE[14] ,Card status response error bit 14" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CSRE[13] ,Card status response error bit 13" "No error,Error"
|
|
bitfld.long 0x00 12. " CSRE[12] ,Card status response error bit 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CSRE[11] ,Card status response error bit 11" "No error,Error"
|
|
bitfld.long 0x00 10. " CSRE[10] ,Card status response error bit 10" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CSRE[9] ,Card status response error bit 9" "No error,Error"
|
|
bitfld.long 0x00 8. " CSRE[8] ,Card status response error bit 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSRE[7] ,Card status response error bit 7" "No error,Error"
|
|
bitfld.long 0x00 6. " CSRE[6] ,Card status response error bit 6" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CSRE[5] ,Card status response error bit 5" "No error,Error"
|
|
bitfld.long 0x00 4. " CSRE[4] ,Card status response error bit 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSRE[3] ,Card status response error bit 3" "No error,Error"
|
|
bitfld.long 0x00 2. " CSRE[2] ,Card status response error bit 2" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSRE[1] ,Card status response error bit 1" "No error,Error"
|
|
bitfld.long 0x00 0. " CSRE[0] ,Card status response error bit 0" "No error,Error"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MMCHS_SYSTEST,System Test register"
|
|
group.long 0x2c++0x7
|
|
line.long 0x00 "MMCHS_CON,Configuration Register"
|
|
bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained"
|
|
bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OBIE ,Out-of-Band Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OBIP ,Out-of-Band Interrupt Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CEATA ,CE-ATA control mode" "Standard,CE-ATA"
|
|
bitfld.long 0x00 11. " CTPL ,Control Power for mmci_dat[1] line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value" "33 us,231 us,1 ms,8.4 ms"
|
|
bitfld.long 0x00 8. " WPP ,Write protect polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDP ,Card detect polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " MIT ,MMC interrupt command" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select" "1-bit/4-bit,8-bit"
|
|
bitfld.long 0x00 4. " MODE ,Mode select" "Functional,SYSTEST"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STR ,Stream command" "Block,Stream"
|
|
bitfld.long 0x00 2. " HR ,Broadcast host response" "No response,Response"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INIT ,Send initialization stream" "Not sent,Sent"
|
|
bitfld.long 0x00 0. " OD ,Card open drain mode" "No open drain,Open drain"
|
|
line.long 0x04 "MMCHS_PWCNT,Power Counter Register"
|
|
group.long 0x104++0xb
|
|
line.long 0x00 "MMCHS_BLK,Transfer Length Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer"
|
|
hexmask.long.word 0x00 0.--10. 1. " BLEN ,Transfer block size"
|
|
line.long 0x04 "MMCHS_ARG,Command Argument Register"
|
|
line.long 0x08 "MMCHS_CMD,Command and Transfer Mode Register"
|
|
hexmask.long.byte 0x08 24.--29. 1. " INDX ,Command index"
|
|
bitfld.long 0x08 22.--23. " CMD_TYPE ,Command type" "Other,Bus Suspend,Function Select,I/O Abort"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DP ,Data present" "No transfer,Transfer"
|
|
bitfld.long 0x08 20. " CICE ,Command Index check enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " CCCE ,Command CRC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits with busy"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSBS ,Multi/Single block select" "Single,Multi"
|
|
bitfld.long 0x08 4. " DDIR ,Data transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ACEN ,Auto CMD12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " BCE ,Block count enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DE ,DMA enable" "Disabled,Enabled"
|
|
rgroup.long 0x110++0xf
|
|
line.long 0x00 "MMCHS_RSP10,Command Response[31:0] Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command response"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command response"
|
|
line.long 0x04 "MMCHS_RSP32,Command Response[63:32] Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " RSP3 ,Command response"
|
|
hexmask.long.word 0x04 0.--15. 1. " RSP2 ,Command response"
|
|
line.long 0x08 "MMCHS_RSP54,Command Response[95:64] Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " RSP5 ,Command response"
|
|
hexmask.long.word 0x08 0.--15. 1. " RSP4 ,Command response"
|
|
line.long 0x0c "MMCHS_RSP76,Command Response[127:96] Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " RSP7 ,Command response"
|
|
hexmask.long.word 0x0C 0.--15. 1. " RSP6 ,Command response"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "MMCHS_DATA,Data Register"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x00 "MMCHS_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,The mmci_cmd line level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,The mmci_dat[3] line level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DLEV[2] ,The mmci_dat[2] line level" "0,1"
|
|
bitfld.long 0x00 21. " DLEV[1] ,The mmci_dat[1] line level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DLEV[0] ,The mmci_dat[0] line level" "0,1"
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DLA ,mmci_dat Line active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATI ,Issuing of command using the mmci_dat lines" "Allowed,Not allowed"
|
|
bitfld.long 0x00 0. " CMDI ,Issuing of command using mmci_cmd line" "Allowed,Not allowed"
|
|
group.long 0x128++0x13
|
|
line.long 0x00 "MMCHS_HCTL,Control Register"
|
|
bitfld.long 0x00 27. " OBWE ,Wakeup event enable for Out-of-Band interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " REM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " IWE ,Wakeup event enable on SD card interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IBG ,Interrupt block at gap" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RWC ,Read wait control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CR ,Continue request" "No effect,Restart"
|
|
bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select" "Reserved,Reserved,Reserved,Reserved,Reserved,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit"
|
|
line.long 0x04 "MMCHS_SYSCTL,SD System Control Register"
|
|
bitfld.long 0x04 26. " SRD ,Software reset for mmci_dat line" "Completed,Reset"
|
|
bitfld.long 0x04 25. " SRC ,Software reset for mmci_cmd line" "Completed,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 24. " SRA ,Software reset for all" "Completed,Reset"
|
|
bitfld.long 0x04 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCF x 2^13,TCF x 2^14,TCF x 2^15,TCF x 2^16,TCF x 2^17,TCF x 2^18,TCF x 2^19,TCF x 2^20,TCF x 2^21,TCF x 2^22,TCF x 2^23,TCF x 2^24,TCF x 2^25,TCF x 2^26,TCF x 2^27,?..."
|
|
textline " "
|
|
hexmask.long.word 0x04 6.--15. 1. " CLKD ,Clock frequency select"
|
|
bitfld.long 0x04 2. " CEN ,Clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ICS ,Internal clock stable" "Not stable,Stable"
|
|
bitfld.long 0x04 0. " ICE ,Internal clock enable" "Stopped,Enabled"
|
|
line.long 0x08 "MMCHS_STAT,Interrupt Status Register"
|
|
eventfld.long 0x08 29. " BADA ,Bad access to data space" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 28. " CERR ,Card error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 24. " ACE ,Auto CMD12 error" "No error,Error"
|
|
eventfld.long 0x08 22. " DEB ,Data End Bit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 21. " DCRC ,Data CRC error" "No error,Error"
|
|
eventfld.long 0x08 20. " DTO ,Data timeout error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 19. " CIE ,Command index error" "No error,Error"
|
|
eventfld.long 0x08 18. " CEB ,Command end bit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 17. " CCRC ,Command CRC error" "No error,Error"
|
|
eventfld.long 0x08 16. " CTO ,Command timeout error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 9. " OBI ,Out-Of-Band interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " BRR ,Buffer read ready" "Not ready,Ready"
|
|
eventfld.long 0x08 4. " BWR ,Buffer write ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x08 2. " BGE ,Block gap event" "No event,Interrupt"
|
|
eventfld.long 0x08 1. " TC ,Transfer completed" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x08 0. " CC ,Command completed" "Not completed,Completed"
|
|
line.long 0x0c "MMCHS_IE,Interrupt SD Enable Register"
|
|
bitfld.long 0x0C 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " NULL ,NULL" "0,1"
|
|
bitfld.long 0x0C 9. " OBI_ENABLE ,Out-of-Band interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled"
|
|
line.long 0x10 "MMCHS_ISE,Interrupt Signal Enable Register"
|
|
bitfld.long 0x10 29. " BADA_SIGEN ,Bad access to data space signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 28. " CERR_SIGEN ,Card error interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 22. " DEB_SIGEN ,Data end bit error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 20. " DTO_SIGEN ,Data timeout error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " CIE_SIGEN ,Command index error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 18. " CEB_SIGEN ,Command end bit error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 16. " CTO_SIGEN ,Command timeout error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " NULL ,NULL" "0,1"
|
|
bitfld.long 0x10 8. " OBI_SIGEN ,Out-Of-Band interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " BGE_SIGEN ,Black gap event signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 1. " TC_SIGEN ,Transfer completed signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CC_SIGEN ,Command completed signal status enable" "Masked,Enabled"
|
|
rgroup.long 0x13c++0x3
|
|
line.long 0x00 "MMCHS_AC12,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error" "No error,Error"
|
|
bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error"
|
|
bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error"
|
|
bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed" "Executed,Not executed"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "MMCHS_CAPA,Capabilities Register"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported"
|
|
bitfld.long 0x00 23. " SRS ,Suspend/Resume support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
|
|
hexmask.long.byte 0x00 8.--13. 1. " BCF ,Base clock frequency"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TCF ,Timeout clock frequency"
|
|
group.long 0x148++0x3
|
|
line.long 0x00 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V"
|
|
rgroup.long 0x1fc++0x3
|
|
line.long 0x00 "MMCHS_REV,Versions Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification version number"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SIS ,Slot interrupt status" "0,1"
|
|
width 11.
|
|
tree.end
|
|
tree "MMCHS2"
|
|
base ad:0x480b4000
|
|
width 17.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MMCHS_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "MMCHS_CSRE,Card Status Response Error"
|
|
bitfld.long 0x00 31. " CSRE[31] ,Card status response error bit 31" "No error,Error"
|
|
bitfld.long 0x00 30. " CSRE[30] ,Card status response error bit 30" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CSRE[29] ,Card status response error bit 29" "No error,Error"
|
|
bitfld.long 0x00 28. " CSRE[28] ,Card status response error bit 28" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CSRE[27] ,Card status response error bit 27" "No error,Error"
|
|
bitfld.long 0x00 26. " CSRE[26] ,Card status response error bit 26" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CSRE[25] ,Card status response error bit 25" "No error,Error"
|
|
bitfld.long 0x00 24. " CSRE[24] ,Card status response error bit 24" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CSRE[23] ,Card status response error bit 23" "No error,Error"
|
|
bitfld.long 0x00 22. " CSRE[22] ,Card status response error bit 22" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CSRE[21] ,Card status response error bit 21" "No error,Error"
|
|
bitfld.long 0x00 20. " CSRE[20] ,Card status response error bit 20" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSRE[19] ,Card status response error bit 19" "No error,Error"
|
|
bitfld.long 0x00 18. " CSRE[18] ,Card status response error bit 18" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CSRE[17] ,Card status response error bit 17" "No error,Error"
|
|
bitfld.long 0x00 16. " CSRE[16] ,Card status response error bit 16" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CSRE[15] ,Card status response error bit 15" "No error,Error"
|
|
bitfld.long 0x00 14. " CSRE[14] ,Card status response error bit 14" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CSRE[13] ,Card status response error bit 13" "No error,Error"
|
|
bitfld.long 0x00 12. " CSRE[12] ,Card status response error bit 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CSRE[11] ,Card status response error bit 11" "No error,Error"
|
|
bitfld.long 0x00 10. " CSRE[10] ,Card status response error bit 10" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CSRE[9] ,Card status response error bit 9" "No error,Error"
|
|
bitfld.long 0x00 8. " CSRE[8] ,Card status response error bit 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSRE[7] ,Card status response error bit 7" "No error,Error"
|
|
bitfld.long 0x00 6. " CSRE[6] ,Card status response error bit 6" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CSRE[5] ,Card status response error bit 5" "No error,Error"
|
|
bitfld.long 0x00 4. " CSRE[4] ,Card status response error bit 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSRE[3] ,Card status response error bit 3" "No error,Error"
|
|
bitfld.long 0x00 2. " CSRE[2] ,Card status response error bit 2" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSRE[1] ,Card status response error bit 1" "No error,Error"
|
|
bitfld.long 0x00 0. " CSRE[0] ,Card status response error bit 0" "No error,Error"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MMCHS_SYSTEST,System Test register"
|
|
group.long 0x2c++0x7
|
|
line.long 0x00 "MMCHS_CON,Configuration Register"
|
|
bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained"
|
|
bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OBIE ,Out-of-Band Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OBIP ,Out-of-Band Interrupt Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CEATA ,CE-ATA control mode" "Standard,CE-ATA"
|
|
bitfld.long 0x00 11. " CTPL ,Control Power for mmci_dat[1] line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value" "33 us,231 us,1 ms,8.4 ms"
|
|
bitfld.long 0x00 8. " WPP ,Write protect polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDP ,Card detect polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " MIT ,MMC interrupt command" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select" "1-bit/4-bit,8-bit"
|
|
bitfld.long 0x00 4. " MODE ,Mode select" "Functional,SYSTEST"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STR ,Stream command" "Block,Stream"
|
|
bitfld.long 0x00 2. " HR ,Broadcast host response" "No response,Response"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INIT ,Send initialization stream" "Not sent,Sent"
|
|
bitfld.long 0x00 0. " OD ,Card open drain mode" "No open drain,Open drain"
|
|
line.long 0x04 "MMCHS_PWCNT,Power Counter Register"
|
|
group.long 0x104++0xb
|
|
line.long 0x00 "MMCHS_BLK,Transfer Length Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer"
|
|
hexmask.long.word 0x00 0.--10. 1. " BLEN ,Transfer block size"
|
|
line.long 0x04 "MMCHS_ARG,Command Argument Register"
|
|
line.long 0x08 "MMCHS_CMD,Command and Transfer Mode Register"
|
|
hexmask.long.byte 0x08 24.--29. 1. " INDX ,Command index"
|
|
bitfld.long 0x08 22.--23. " CMD_TYPE ,Command type" "Other,Bus Suspend,Function Select,I/O Abort"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DP ,Data present" "No transfer,Transfer"
|
|
bitfld.long 0x08 20. " CICE ,Command Index check enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " CCCE ,Command CRC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits with busy"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSBS ,Multi/Single block select" "Single,Multi"
|
|
bitfld.long 0x08 4. " DDIR ,Data transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ACEN ,Auto CMD12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " BCE ,Block count enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DE ,DMA enable" "Disabled,Enabled"
|
|
rgroup.long 0x110++0xf
|
|
line.long 0x00 "MMCHS_RSP10,Command Response[31:0] Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command response"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command response"
|
|
line.long 0x04 "MMCHS_RSP32,Command Response[63:32] Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " RSP3 ,Command response"
|
|
hexmask.long.word 0x04 0.--15. 1. " RSP2 ,Command response"
|
|
line.long 0x08 "MMCHS_RSP54,Command Response[95:64] Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " RSP5 ,Command response"
|
|
hexmask.long.word 0x08 0.--15. 1. " RSP4 ,Command response"
|
|
line.long 0x0c "MMCHS_RSP76,Command Response[127:96] Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " RSP7 ,Command response"
|
|
hexmask.long.word 0x0C 0.--15. 1. " RSP6 ,Command response"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "MMCHS_DATA,Data Register"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x00 "MMCHS_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,The mmci_cmd line level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,The mmci_dat[3] line level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DLEV[2] ,The mmci_dat[2] line level" "0,1"
|
|
bitfld.long 0x00 21. " DLEV[1] ,The mmci_dat[1] line level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DLEV[0] ,The mmci_dat[0] line level" "0,1"
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DLA ,mmci_dat Line active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATI ,Issuing of command using the mmci_dat lines" "Allowed,Not allowed"
|
|
bitfld.long 0x00 0. " CMDI ,Issuing of command using mmci_cmd line" "Allowed,Not allowed"
|
|
group.long 0x128++0x13
|
|
line.long 0x00 "MMCHS_HCTL,Control Register"
|
|
bitfld.long 0x00 27. " OBWE ,Wakeup event enable for Out-of-Band interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " REM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " IWE ,Wakeup event enable on SD card interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IBG ,Interrupt block at gap" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RWC ,Read wait control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CR ,Continue request" "No effect,Restart"
|
|
bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select" "Reserved,Reserved,Reserved,Reserved,Reserved,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit"
|
|
line.long 0x04 "MMCHS_SYSCTL,SD System Control Register"
|
|
bitfld.long 0x04 26. " SRD ,Software reset for mmci_dat line" "Completed,Reset"
|
|
bitfld.long 0x04 25. " SRC ,Software reset for mmci_cmd line" "Completed,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 24. " SRA ,Software reset for all" "Completed,Reset"
|
|
bitfld.long 0x04 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCF x 2^13,TCF x 2^14,TCF x 2^15,TCF x 2^16,TCF x 2^17,TCF x 2^18,TCF x 2^19,TCF x 2^20,TCF x 2^21,TCF x 2^22,TCF x 2^23,TCF x 2^24,TCF x 2^25,TCF x 2^26,TCF x 2^27,?..."
|
|
textline " "
|
|
hexmask.long.word 0x04 6.--15. 1. " CLKD ,Clock frequency select"
|
|
bitfld.long 0x04 2. " CEN ,Clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ICS ,Internal clock stable" "Not stable,Stable"
|
|
bitfld.long 0x04 0. " ICE ,Internal clock enable" "Stopped,Enabled"
|
|
line.long 0x08 "MMCHS_STAT,Interrupt Status Register"
|
|
eventfld.long 0x08 29. " BADA ,Bad access to data space" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 28. " CERR ,Card error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 24. " ACE ,Auto CMD12 error" "No error,Error"
|
|
eventfld.long 0x08 22. " DEB ,Data End Bit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 21. " DCRC ,Data CRC error" "No error,Error"
|
|
eventfld.long 0x08 20. " DTO ,Data timeout error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 19. " CIE ,Command index error" "No error,Error"
|
|
eventfld.long 0x08 18. " CEB ,Command end bit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 17. " CCRC ,Command CRC error" "No error,Error"
|
|
eventfld.long 0x08 16. " CTO ,Command timeout error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 9. " OBI ,Out-Of-Band interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " BRR ,Buffer read ready" "Not ready,Ready"
|
|
eventfld.long 0x08 4. " BWR ,Buffer write ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x08 2. " BGE ,Block gap event" "No event,Interrupt"
|
|
eventfld.long 0x08 1. " TC ,Transfer completed" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x08 0. " CC ,Command completed" "Not completed,Completed"
|
|
line.long 0x0c "MMCHS_IE,Interrupt SD Enable Register"
|
|
bitfld.long 0x0C 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " NULL ,NULL" "0,1"
|
|
bitfld.long 0x0C 9. " OBI_ENABLE ,Out-of-Band interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled"
|
|
line.long 0x10 "MMCHS_ISE,Interrupt Signal Enable Register"
|
|
bitfld.long 0x10 29. " BADA_SIGEN ,Bad access to data space signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 28. " CERR_SIGEN ,Card error interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 22. " DEB_SIGEN ,Data end bit error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 20. " DTO_SIGEN ,Data timeout error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " CIE_SIGEN ,Command index error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 18. " CEB_SIGEN ,Command end bit error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 16. " CTO_SIGEN ,Command timeout error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " NULL ,NULL" "0,1"
|
|
bitfld.long 0x10 8. " OBI_SIGEN ,Out-Of-Band interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " BGE_SIGEN ,Black gap event signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 1. " TC_SIGEN ,Transfer completed signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CC_SIGEN ,Command completed signal status enable" "Masked,Enabled"
|
|
rgroup.long 0x13c++0x3
|
|
line.long 0x00 "MMCHS_AC12,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error" "No error,Error"
|
|
bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error"
|
|
bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error"
|
|
bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed" "Executed,Not executed"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "MMCHS_CAPA,Capabilities Register"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported"
|
|
bitfld.long 0x00 23. " SRS ,Suspend/Resume support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
|
|
hexmask.long.byte 0x00 8.--13. 1. " BCF ,Base clock frequency"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TCF ,Timeout clock frequency"
|
|
group.long 0x148++0x3
|
|
line.long 0x00 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V"
|
|
rgroup.long 0x1fc++0x3
|
|
line.long 0x00 "MMCHS_REV,Versions Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification version number"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SIS ,Slot interrupt status" "0,1"
|
|
width 11.
|
|
tree.end
|
|
tree "MMCHS3"
|
|
base ad:0x480AD000
|
|
width 17.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MMCHS_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal Clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "MMCHS_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "MMCHS_CSRE,Card Status Response Error"
|
|
bitfld.long 0x00 31. " CSRE[31] ,Card status response error bit 31" "No error,Error"
|
|
bitfld.long 0x00 30. " CSRE[30] ,Card status response error bit 30" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CSRE[29] ,Card status response error bit 29" "No error,Error"
|
|
bitfld.long 0x00 28. " CSRE[28] ,Card status response error bit 28" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CSRE[27] ,Card status response error bit 27" "No error,Error"
|
|
bitfld.long 0x00 26. " CSRE[26] ,Card status response error bit 26" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CSRE[25] ,Card status response error bit 25" "No error,Error"
|
|
bitfld.long 0x00 24. " CSRE[24] ,Card status response error bit 24" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CSRE[23] ,Card status response error bit 23" "No error,Error"
|
|
bitfld.long 0x00 22. " CSRE[22] ,Card status response error bit 22" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CSRE[21] ,Card status response error bit 21" "No error,Error"
|
|
bitfld.long 0x00 20. " CSRE[20] ,Card status response error bit 20" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSRE[19] ,Card status response error bit 19" "No error,Error"
|
|
bitfld.long 0x00 18. " CSRE[18] ,Card status response error bit 18" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CSRE[17] ,Card status response error bit 17" "No error,Error"
|
|
bitfld.long 0x00 16. " CSRE[16] ,Card status response error bit 16" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CSRE[15] ,Card status response error bit 15" "No error,Error"
|
|
bitfld.long 0x00 14. " CSRE[14] ,Card status response error bit 14" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CSRE[13] ,Card status response error bit 13" "No error,Error"
|
|
bitfld.long 0x00 12. " CSRE[12] ,Card status response error bit 12" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CSRE[11] ,Card status response error bit 11" "No error,Error"
|
|
bitfld.long 0x00 10. " CSRE[10] ,Card status response error bit 10" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CSRE[9] ,Card status response error bit 9" "No error,Error"
|
|
bitfld.long 0x00 8. " CSRE[8] ,Card status response error bit 8" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CSRE[7] ,Card status response error bit 7" "No error,Error"
|
|
bitfld.long 0x00 6. " CSRE[6] ,Card status response error bit 6" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CSRE[5] ,Card status response error bit 5" "No error,Error"
|
|
bitfld.long 0x00 4. " CSRE[4] ,Card status response error bit 4" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CSRE[3] ,Card status response error bit 3" "No error,Error"
|
|
bitfld.long 0x00 2. " CSRE[2] ,Card status response error bit 2" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CSRE[1] ,Card status response error bit 1" "No error,Error"
|
|
bitfld.long 0x00 0. " CSRE[0] ,Card status response error bit 0" "No error,Error"
|
|
group.long 0x28++0x3
|
|
line.long 0x00 "MMCHS_SYSTEST,System Test register"
|
|
group.long 0x2c++0x7
|
|
line.long 0x00 "MMCHS_CON,Configuration Register"
|
|
bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained"
|
|
bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OBIE ,Out-of-Band Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " OBIP ,Out-of-Band Interrupt Polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CEATA ,CE-ATA control mode" "Standard,CE-ATA"
|
|
bitfld.long 0x00 11. " CTPL ,Control Power for mmci_dat[1] line" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " DVAL ,Debounce filter value" "33 us,231 us,1 ms,8.4 ms"
|
|
bitfld.long 0x00 8. " WPP ,Write protect polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CDP ,Card detect polarity" "Active high,Active low"
|
|
bitfld.long 0x00 6. " MIT ,MMC interrupt command" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DW8 ,8-bit mode MMC select" "1-bit/4-bit,8-bit"
|
|
bitfld.long 0x00 4. " MODE ,Mode select" "Functional,SYSTEST"
|
|
textline " "
|
|
bitfld.long 0x00 3. " STR ,Stream command" "Block,Stream"
|
|
bitfld.long 0x00 2. " HR ,Broadcast host response" "No response,Response"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INIT ,Send initialization stream" "Not sent,Sent"
|
|
bitfld.long 0x00 0. " OD ,Card open drain mode" "No open drain,Open drain"
|
|
line.long 0x04 "MMCHS_PWCNT,Power Counter Register"
|
|
group.long 0x104++0xb
|
|
line.long 0x00 "MMCHS_BLK,Transfer Length Configuration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer"
|
|
hexmask.long.word 0x00 0.--10. 1. " BLEN ,Transfer block size"
|
|
line.long 0x04 "MMCHS_ARG,Command Argument Register"
|
|
line.long 0x08 "MMCHS_CMD,Command and Transfer Mode Register"
|
|
hexmask.long.byte 0x08 24.--29. 1. " INDX ,Command index"
|
|
bitfld.long 0x08 22.--23. " CMD_TYPE ,Command type" "Other,Bus Suspend,Function Select,I/O Abort"
|
|
textline " "
|
|
bitfld.long 0x08 21. " DP ,Data present" "No transfer,Transfer"
|
|
bitfld.long 0x08 20. " CICE ,Command Index check enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " CCCE ,Command CRC check enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits with busy"
|
|
textline " "
|
|
bitfld.long 0x08 5. " MSBS ,Multi/Single block select" "Single,Multi"
|
|
bitfld.long 0x08 4. " DDIR ,Data transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ACEN ,Auto CMD12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " BCE ,Block count enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DE ,DMA enable" "Disabled,Enabled"
|
|
rgroup.long 0x110++0xf
|
|
line.long 0x00 "MMCHS_RSP10,Command Response[31:0] Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command response"
|
|
hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command response"
|
|
line.long 0x04 "MMCHS_RSP32,Command Response[63:32] Register"
|
|
hexmask.long.word 0x04 16.--31. 1. " RSP3 ,Command response"
|
|
hexmask.long.word 0x04 0.--15. 1. " RSP2 ,Command response"
|
|
line.long 0x08 "MMCHS_RSP54,Command Response[95:64] Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " RSP5 ,Command response"
|
|
hexmask.long.word 0x08 0.--15. 1. " RSP4 ,Command response"
|
|
line.long 0x0c "MMCHS_RSP76,Command Response[127:96] Register"
|
|
hexmask.long.word 0x0C 16.--31. 1. " RSP7 ,Command response"
|
|
hexmask.long.word 0x0C 0.--15. 1. " RSP6 ,Command response"
|
|
group.long 0x120++0x3
|
|
line.long 0x00 "MMCHS_DATA,Data Register"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x00 "MMCHS_PSTATE,Present State Register"
|
|
bitfld.long 0x00 24. " CLEV ,The mmci_cmd line level" "0,1"
|
|
bitfld.long 0x00 23. " DLEV[3] ,The mmci_dat[3] line level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DLEV[2] ,The mmci_dat[2] line level" "0,1"
|
|
bitfld.long 0x00 21. " DLEV[1] ,The mmci_dat[1] line level" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 20. " DLEV[0] ,The mmci_dat[0] line level" "0,1"
|
|
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RTA ,Read transfer active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 8. " WTA ,Write transfer active" "Inactive,Active"
|
|
bitfld.long 0x00 2. " DLA ,mmci_dat Line active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DATI ,Issuing of command using the mmci_dat lines" "Allowed,Not allowed"
|
|
bitfld.long 0x00 0. " CMDI ,Issuing of command using mmci_cmd line" "Allowed,Not allowed"
|
|
group.long 0x128++0x13
|
|
line.long 0x00 "MMCHS_HCTL,Control Register"
|
|
bitfld.long 0x00 27. " OBWE ,Wakeup event enable for Out-of-Band interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " REM ,Wakeup event enable on SD card removal" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " INS ,Wakeup event enable on SD card insertion" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " IWE ,Wakeup event enable on SD card interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IBG ,Interrupt block at gap" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " RWC ,Read wait control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CR ,Continue request" "No effect,Restart"
|
|
bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select" "Reserved,Reserved,Reserved,Reserved,Reserved,1.8V,3.0V,3.3V"
|
|
bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit"
|
|
line.long 0x04 "MMCHS_SYSCTL,SD System Control Register"
|
|
bitfld.long 0x04 26. " SRD ,Software reset for mmci_dat line" "Completed,Reset"
|
|
bitfld.long 0x04 25. " SRC ,Software reset for mmci_cmd line" "Completed,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 24. " SRA ,Software reset for all" "Completed,Reset"
|
|
bitfld.long 0x04 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCF x 2^13,TCF x 2^14,TCF x 2^15,TCF x 2^16,TCF x 2^17,TCF x 2^18,TCF x 2^19,TCF x 2^20,TCF x 2^21,TCF x 2^22,TCF x 2^23,TCF x 2^24,TCF x 2^25,TCF x 2^26,TCF x 2^27,?..."
|
|
textline " "
|
|
hexmask.long.word 0x04 6.--15. 1. " CLKD ,Clock frequency select"
|
|
bitfld.long 0x04 2. " CEN ,Clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ICS ,Internal clock stable" "Not stable,Stable"
|
|
bitfld.long 0x04 0. " ICE ,Internal clock enable" "Stopped,Enabled"
|
|
line.long 0x08 "MMCHS_STAT,Interrupt Status Register"
|
|
eventfld.long 0x08 29. " BADA ,Bad access to data space" "No interrupt,Interrupt"
|
|
eventfld.long 0x08 28. " CERR ,Card error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 24. " ACE ,Auto CMD12 error" "No error,Error"
|
|
eventfld.long 0x08 22. " DEB ,Data End Bit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 21. " DCRC ,Data CRC error" "No error,Error"
|
|
eventfld.long 0x08 20. " DTO ,Data timeout error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 19. " CIE ,Command index error" "No error,Error"
|
|
eventfld.long 0x08 18. " CEB ,Command end bit error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x08 17. " CCRC ,Command CRC error" "No error,Error"
|
|
eventfld.long 0x08 16. " CTO ,Command timeout error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 9. " OBI ,Out-Of-Band interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x08 5. " BRR ,Buffer read ready" "Not ready,Ready"
|
|
eventfld.long 0x08 4. " BWR ,Buffer write ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.long 0x08 2. " BGE ,Block gap event" "No event,Interrupt"
|
|
eventfld.long 0x08 1. " TC ,Transfer completed" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x08 0. " CC ,Command completed" "Not completed,Completed"
|
|
line.long 0x0c "MMCHS_IE,Interrupt SD Enable Register"
|
|
bitfld.long 0x0C 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " NULL ,NULL" "0,1"
|
|
bitfld.long 0x0C 9. " OBI_ENABLE ,Out-of-Band interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled"
|
|
bitfld.long 0x0C 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled"
|
|
line.long 0x10 "MMCHS_ISE,Interrupt Signal Enable Register"
|
|
bitfld.long 0x10 29. " BADA_SIGEN ,Bad access to data space signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 28. " CERR_SIGEN ,Card error interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 22. " DEB_SIGEN ,Data end bit error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 20. " DTO_SIGEN ,Data timeout error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " CIE_SIGEN ,Command index error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 18. " CEB_SIGEN ,Command end bit error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 16. " CTO_SIGEN ,Command timeout error signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " NULL ,NULL" "0,1"
|
|
bitfld.long 0x10 8. " OBI_SIGEN ,Out-Of-Band interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " BGE_SIGEN ,Black gap event signal status enable" "Masked,Enabled"
|
|
bitfld.long 0x10 1. " TC_SIGEN ,Transfer completed signal status enable" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " CC_SIGEN ,Command completed signal status enable" "Masked,Enabled"
|
|
rgroup.long 0x13c++0x3
|
|
line.long 0x00 "MMCHS_AC12,Auto CMD12 Error Status Register"
|
|
bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error" "No error,Error"
|
|
bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error"
|
|
bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error"
|
|
bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed" "Executed,Not executed"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "MMCHS_CAPA,Capabilities Register"
|
|
bitfld.long 0x00 26. " VS18 ,Voltage support 1.8V" "Not supported,Supported"
|
|
bitfld.long 0x00 25. " VS30 ,Voltage support 3.0V" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " VS33 ,Voltage support 3.3V" "Not supported,Supported"
|
|
bitfld.long 0x00 23. " SRS ,Suspend/Resume support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
|
|
bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
|
|
hexmask.long.byte 0x00 8.--13. 1. " BCF ,Base clock frequency"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
|
|
hexmask.long.byte 0x00 0.--5. 1. " TCF ,Timeout clock frequency"
|
|
group.long 0x148++0x3
|
|
line.long 0x00 "MMCHS_CUR_CAPA,Maximum Current Capabilities Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0V"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3V"
|
|
rgroup.long 0x1fc++0x3
|
|
line.long 0x00 "MMCHS_REV,Versions Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor version number"
|
|
hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification version number"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SIS ,Slot interrupt status" "0,1"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree.open "High-Speed USB Host Subsystem/On-The-Go Controller"
|
|
tree "High-Speed USB Host Subsystem"
|
|
tree "USBTLL"
|
|
base ad:0x48062000
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "USBTLL_REVISION,OCP Standard Revision Number"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major revision number"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MINOR ,Minor revision number"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "USBTLL_SYSCONFIG,OCP Standard System Configuration Register"
|
|
bitfld.long 0x00 8. " CACTIVITY ,Enable autogating of OCP-derived internal clocks" "Off,On"
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management control" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Asynchronous wakeup generation control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Module software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal autogating control" "Running,Cut off"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "USBTLL_SYSSTATUS,OCP Standard System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Indicates when the module has entirely come out of reset" "Ongoing,Done"
|
|
group.long 0x18++0x7
|
|
line.long 0x00 "USBTLL_IRQSTATUS,OCP Standard IRQ Status Vector"
|
|
bitfld.long 0x00 2. " ACCESS_ERROR ,Access error to ULPI register over OCP" "Not pending,Pending"
|
|
bitfld.long 0x00 1. " FCLK_END ,Functional clock is no longer requested for USB clocking" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FCLK_START ,Functional clock is requested for USB clocking" "Not pending,Pending"
|
|
line.long 0x04 "USBTLL_IRQENABLE,OCP Standard IRQ Enable Vector"
|
|
bitfld.long 0x04 2. " ACCESS_ERROR_EN ,Enable access error to ULPI register over OCP" "Masked,Enabled"
|
|
bitfld.long 0x04 1. " FCLK_END_EN ,Enable functional clock is no longer requested for USB clocking" "Masked,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FCLK_START_EN ,Enable functional clock is requested for USB clocking" "Masked,Enabled"
|
|
group.long 0x30++0x3
|
|
line.long 0x00 "TLL_SHARED_CONF,Common Control Register For All TLL Channels"
|
|
bitfld.long 0x00 6. " USB_90D_DDR_EN ,Software enable/disable of the 90-degree phase shift scheme" "Aligned with CLK,Delayed by 90"
|
|
bitfld.long 0x00 5. " USB_180D_SDR_EN ,Software enable/disable of the 180-degree phase shift scheme" "Aligned with CLK,Delayed by 180"
|
|
textline " "
|
|
bitfld.long 0x00 2.--4. " USB_DIVRATIO ,division ratio from functional clock to USB clock" "2**0=1,2**1=2,2**2=4,2**3=8,2**4=16,2**5=32,2**6=64,2**7=128"
|
|
bitfld.long 0x00 1. " FCLK_REQ ,Functional clock request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FCLK_IS_ON ,Status of the functional clock input" "Not guaranteed,Guaranteed"
|
|
tree "Channel 0"
|
|
width 21.
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TLL_CHANNEL_CONF_0,Control And Status Register For Channel 0"
|
|
bitfld.long 0x00 28.--29. " FSLSLINESTATE ,Line state for Full/Low speed serial modes" "Single-ended 0,Full-speed J,Full-speed K,Single-ended 1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " FSLSMODE ,Multiple-mode serial interfaces mode select" "6-pin unidirectional PHY i/f Dat/Se0,6-pin unidirectional PHY i/f Dp/Dm,3-pin bidirectional PHY i/f,4-pin bidirectional PHY i/f,6-pin unidirectional TLL Dat/Se0,6-pin unidirectional TLL Dp/Dm,3-pin bidirectional TLL,4-pin bidirectional TLL,Reserved,Reserved,2-pin bidirectional TLL Dat/Se0,2-pin bidirectional TLL Dp/Dm,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20. " TESTTXSE0 ,Force-Se0 transmit override value for serial mode test" "Differential value,SE0"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TESTTXDAT ,Differential data transmit override value for serial mode test" "Full-speed K,Full-speed J"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TESTTXEN ,Differential data transmit override value for serial mode test" "TestTXDat/Se0,TX Hiz"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TESTEN ,Enable manual test override for serial mode TX path" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DRVVBUS ,VBUS-drive for ChanMode = serial" "Not driven,Driven to 5V"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHRGVBUS ,VBUS-drive for ChanMode = serial" "Not charged,Charged"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ULPINOBITSTUFF ,Disable bitstuff emulation in ULPI TLL for ULPI ChanMode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPIAUTOIDLE ,Allow the ULPI output clock to be stopped when ULPI goes into asynchronous mode" "Always on,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UTMIAUTOIDLE ,Allow the UTMI clock to be stopped when UTMII goes to suspended mode" "Always on,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ULPIDDRMODE ,Select single/double data rate" "SDR,DDR"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ULPIOUTCLKMODE ,ULPI clocking mode select for ULPI TLL ChanMode" "LINK,PHY"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TLLFULLSPEED ,Sets PHY speed emulation in TLL" "Low speed,Full speed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TLLCONNECT ,Emulation of Full/Low-Speed connect" "Unconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TLLATTACH ,Emulates cable attach/detach for all serial TLL modes" "Detach,Attach"
|
|
textline " "
|
|
bitfld.long 0x00 3. " UTMIISADEV ,Select the cable end seen by UTMI side of TLL" "UTMI peripheral/ULPI host,UTMI host/ULPI peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " CHANMODE ,Main channel mode selection" "UTMI-to-ULPI TLL,UTMI-to-serial,Transparent UTMI,No mode selected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANEN ,Active-high channel enable" "Disabled,Enabled"
|
|
rgroup.byte 0x800++0x3
|
|
line.byte 0x00 "ULPI_VENDOR_ID_LO_0,Lower Byte Of USB-IF-Supplied Vendor ID Value"
|
|
line.byte 0x01 "ULPI_VENDOR_ID_HI_0,Upper Byte Of USB-IF-Supplied Vendor ID Value"
|
|
line.byte 0x02 "ULPI_PRODUCT_ID_LO_0,Lower Byte Of Vendor-Chosen Product ID Value"
|
|
line.byte 0x03 "ULPI_PRODUCT_ID_HI_0,Upper Byte Of Vendor-Chosen Product ID Value"
|
|
width 29.
|
|
group.byte (0x800+0x4)++0x2
|
|
line.byte 0x00 "ULPI_FUNCTION_CTRL_0,Controls UTMI Function Settings Of The PHY"
|
|
bitfld.byte 0x00 6. " SUSPENDM ,Active low PHY suspend" "Low-power,Not in low-power"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " RESET ,Active high UTMI transceiver reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " OPMODE ,Select the required bit encoding style during transmit" "Normal,Non-driving,Disable bit-stuff/NRZI encoding,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TERMSELECT ,Controls the internal 1.5Kohms pull-up resistor and 45ohms HS terminations" "HS,FS"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " XCVRSELECT ,Select the required transceiver speed" "HS,FS,LS,FS for LS packets"
|
|
line.byte 0x01 "ULPI_FUNCTION_CTRL_SET_0,Controls UTMI Function Settings Of The PHY"
|
|
line.byte 0x02 "ULPI_FUNCTION_CTRL_CLR_0,Controls UTMI Function Settings Of The PHY"
|
|
group.byte (0x800+0x7)++0x2
|
|
line.byte 0x00 "ULPI_INTERFACE_CTRL_0,Enables Alternative Interfaces And PHY Features"
|
|
bitfld.byte 0x00 7. " INTERFACE_PROTECT_DISABLE ,Controls circuitry built into the PHY" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AUTORESUME ,Enables the PHY to automatically drive resume signaling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CLOCKSUSPENDM ,Active low clock suspend for serial modes" "Stop,Run"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FSLSSERIALMODE_3PIN ,Sets the ULPI interface to 3-pin Serial Mode" "Normal,3-pin serial"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSLSSERIALMODE_6PIN ,Sets the ULPI interface to 6-pin Serial Mode" "Normal,6-pin serial"
|
|
line.byte 0x01 "ULPI_INTERFACE_CTRL_SET_0,Enables Alternative Interfaces And PHY Features"
|
|
line.byte 0x02 "ULPI_INTERFACE_CTRL_CLR_0,Enables Alternative Interfaces And PHY Features"
|
|
group.byte (0x800+0xA)++0x0
|
|
line.byte 0x00 "ULPI_OTG_CTRL_0,Controls UTMI+ OTG Functions Of The PHY"
|
|
bitfld.byte 0x00 5. " DRVVBUS ,Drive 5V on VBUS" "No action,Drive"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CHRGVBUS ,Charge VBUS through a resistor for VBUS-pulsing SRP" "No action,Charge"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DISCHRGVBUS ,Discharge VBUS through a resistor" "No action,Discharge"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DMPULLDOWN ,Enables the 15k Ohm pull-down resistor on D-" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DPPULLDOWN ,Enables the 15k Ohm pull-down resistor on D+" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IDPULLUP ,Pull-up to the (OTG) ID line to allow its sampling" "Disabled,Enabled"
|
|
sif (cpu()=="OMAP3517"||cpu()=="OMAP3505")
|
|
group.long (0x800+0xB)++0x01
|
|
line.byte 0x00 "ULPI_OTG_CTRL_SET_0,Controls UTMI+ OTG Functions Of The PHY"
|
|
line.byte 0x01 "ULPI_OTG_CTRL_CLR_0,Controls UTMI+ OTG Functions Of The PHY"
|
|
endif
|
|
group.byte (0x800+0xD)++0x2
|
|
line.byte 0x00 "ULPI_USB_INT_EN_RISE_0,Enables An Interrupt Event Notification"
|
|
bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification for IdGnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification for SessEnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification for SessValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification for VbusValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification fpr Hostdisconnect" "No interrupt,Interrupt"
|
|
line.byte 0x01 "ULPI_USB_INT_EN_RISE_SET_0,Enables An Interrupt Event Notification"
|
|
line.byte 0x02 "ULPI_USB_INT_EN_RISE_CLR_0,Enables An Interrupt Event Notification"
|
|
group.byte (0x800+0x10)++0x2
|
|
line.byte 0x00 "ULPI_USB_INT_EN_FALL_0,Enables An Interrupt Event Notification"
|
|
bitfld.byte 0x00 4. " IDGND_FALL ,Generate an interrupt event notification for IdGnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND_FALL ,Generate an interrupt event notification for SessEnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID_FALL ,Generate an interrupt event notification for SessValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID_FALL ,Generate an interrupt event notification for VbusValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT_FALL ,Generate an interrupt event notification fpr Hostdisconnect" "No interrupt,Interrupt"
|
|
line.byte 0x01 "ULPI_USB_INT_EN_FALL_SET_0,Enables An Interrupt Event Notification"
|
|
line.byte 0x02 "ULPI_USB_INT_EN_FALL_CLR_0,Enables An Interrupt Event Notification"
|
|
rgroup.byte (0x800+0x13)++0x0
|
|
line.byte 0x00 "ULPI_USB_INT_STATUS_0,Indicates The Current Value Of The Interrupt Source Signal"
|
|
bitfld.byte 0x00 4. " IDGND ,Value of UTMI+ IdDig output" "Grounded,Floating"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND ,Current value of UTMI+ SessEnd output" "> Session-End,< Session-End"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID ,Current value of UTMI+ SessValid output" "> Session-Valid,< Session-Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID ,Current value of UTMI+ VbusValid output" "> Vbus-Valid,< Vbus-Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT ,Current value of UTMI+ Hostdisconnect output" "Not disconnected/Non-host mode,Disconnected"
|
|
hgroup.byte (0x800+0x14)++0x0
|
|
hide.byte 0x00 "ULPI_USB_INT_LATCH_0,ULPI Interrupt Status Register"
|
|
in
|
|
rgroup.byte (0x800+0x15)++0x0
|
|
line.byte 0x00 "ULPI_DEBUG_0,Indicates The Current Value Of Various Signals Useful For Debugging"
|
|
bitfld.byte 0x00 0.--1. " LINESTATE ,Current state of the USB line D+ (bit 0) and D- (bit 1)" "SE0 (LS/FS) Squelch (HS/Chirp),LS=K/FS=J/HS=!Squelch/Chirp=!Squelch & HS_DRO,LS=J/FS=K/HS=Invalid/Chirp=!Squelch & !HS_DRO,SE1 (LS/FS) Invalid (HS/Chirp)"
|
|
group.byte (0x800+0x16)++0x2
|
|
line.byte 0x00 "ULPI_SCRATCH_REGISTER_0,Register Byte For Register Access Testing Purposes"
|
|
line.byte 0x01 "ULPI_SCRATCH_REGISTER_SET_0,Register Byte For Register Access Testing Purposes"
|
|
line.byte 0x02 "ULPI_SCRATCH_REGISTER_CLR_0,Register Byte For Register Access Testing Purposes"
|
|
group.byte (0x800+0x30)++0x2
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_EN_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
bitfld.byte 0x00 7. " VC7_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " VC6_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " VC5_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " VC4_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VC3_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " VC2_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VC1_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " VC0_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
line.byte 0x01 "ULPI_UTMI_VCONTROL_EN_SET_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x02 "ULPI_UTMI_VCONTROL_EN_CLR_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
group.byte (0x800+0x33)++0x0
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_STATUS_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
rgroup.byte (0x800+0x34)++0x0
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_LATCH_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
bitfld.byte 0x00 7. " VC7_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " VC6_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " VC5_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " VC4_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VC3_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " VC2_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VC1_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " VC0_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
group.byte (0x800+0x35)++0x2
|
|
line.byte 0x00 "ULPI_UTMI_VSTATUS_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x01 "ULPI_UTMI_VSTATUS_SET_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x02 "ULPI_UTMI_VSTATUS_CLR_0,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
rgroup.byte (0x800+0x38)++0x0
|
|
line.byte 0x00 "ULPI_USB_INT_LATCH_NOCLR_0,Set By Unmasked Changes On Status Bits To Generate The ULPI Interrupt"
|
|
group.byte (0x800+0x3B)++0x2
|
|
line.byte 0x00 "ULPI_VENDOR_INT_EN_0,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x00 0. " P2P_EN ,Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm" "Disabled,Enabled"
|
|
line.byte 0x01 "ULPI_VENDOR_INT_EN_SET_0,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
line.byte 0x02 "ULPI_VENDOR_INT_EN_CLR_0,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
rgroup.byte (0x800+0x3E)++0x1
|
|
line.byte 0x00 "ULPI_VENDOR_INT_STATUS_0,Vendor-Specific Interrupt Sources For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x00 0. " UTMI_SUSPENDM ,UTMI suspendm status" "Suspended,Not suspended"
|
|
line.byte 0x01 "ULPI_VENDOR_INT_LATCH_0,Vendor-Specific Interrupt Latches For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x01 0. " P2P_LATCH ,PHY-to-PHY ULPI wakeup event latch" "Not latched,Latched"
|
|
tree.end
|
|
tree "Channel 1"
|
|
width 21.
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TLL_CHANNEL_CONF_1,Control And Status Register For Channel 1"
|
|
bitfld.long 0x00 28.--29. " FSLSLINESTATE ,Line state for Full/Low speed serial modes" "Single-ended 0,Full-speed J,Full-speed K,Single-ended 1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " FSLSMODE ,Multiple-mode serial interfaces mode select" "6-pin unidirectional PHY i/f Dat/Se0,6-pin unidirectional PHY i/f Dp/Dm,3-pin bidirectional PHY i/f,4-pin bidirectional PHY i/f,6-pin unidirectional TLL Dat/Se0,6-pin unidirectional TLL Dp/Dm,3-pin bidirectional TLL,4-pin bidirectional TLL,Reserved,Reserved,2-pin bidirectional TLL Dat/Se0,2-pin bidirectional TLL Dp/Dm,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20. " TESTTXSE0 ,Force-Se0 transmit override value for serial mode test" "Differential value,SE0"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TESTTXDAT ,Differential data transmit override value for serial mode test" "Full-speed K,Full-speed J"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TESTTXEN ,Differential data transmit override value for serial mode test" "TestTXDat/Se0,TX Hiz"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TESTEN ,Enable manual test override for serial mode TX path" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DRVVBUS ,VBUS-drive for ChanMode = serial" "Not driven,Driven to 5V"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHRGVBUS ,VBUS-drive for ChanMode = serial" "Not charged,Charged"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ULPINOBITSTUFF ,Disable bitstuff emulation in ULPI TLL for ULPI ChanMode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPIAUTOIDLE ,Allow the ULPI output clock to be stopped when ULPI goes into asynchronous mode" "Always on,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UTMIAUTOIDLE ,Allow the UTMI clock to be stopped when UTMII goes to suspended mode" "Always on,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ULPIDDRMODE ,Select single/double data rate" "SDR,DDR"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ULPIOUTCLKMODE ,ULPI clocking mode select for ULPI TLL ChanMode" "LINK,PHY"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TLLFULLSPEED ,Sets PHY speed emulation in TLL" "Low speed,Full speed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TLLCONNECT ,Emulation of Full/Low-Speed connect" "Unconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TLLATTACH ,Emulates cable attach/detach for all serial TLL modes" "Detach,Attach"
|
|
textline " "
|
|
bitfld.long 0x00 3. " UTMIISADEV ,Select the cable end seen by UTMI side of TLL" "UTMI peripheral/ULPI host,UTMI host/ULPI peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " CHANMODE ,Main channel mode selection" "UTMI-to-ULPI TLL,UTMI-to-serial,Transparent UTMI,No mode selected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANEN ,Active-high channel enable" "Disabled,Enabled"
|
|
rgroup.byte 0x900++0x3
|
|
line.byte 0x00 "ULPI_VENDOR_ID_LO_1,Lower Byte Of USB-IF-Supplied Vendor ID Value"
|
|
line.byte 0x01 "ULPI_VENDOR_ID_HI_1,Upper Byte Of USB-IF-Supplied Vendor ID Value"
|
|
line.byte 0x02 "ULPI_PRODUCT_ID_LO_1,Lower Byte Of Vendor-Chosen Product ID Value"
|
|
line.byte 0x03 "ULPI_PRODUCT_ID_HI_1,Upper Byte Of Vendor-Chosen Product ID Value"
|
|
width 29.
|
|
group.byte (0x900+0x4)++0x2
|
|
line.byte 0x00 "ULPI_FUNCTION_CTRL_1,Controls UTMI Function Settings Of The PHY"
|
|
bitfld.byte 0x00 6. " SUSPENDM ,Active low PHY suspend" "Low-power,Not in low-power"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " RESET ,Active high UTMI transceiver reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " OPMODE ,Select the required bit encoding style during transmit" "Normal,Non-driving,Disable bit-stuff/NRZI encoding,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TERMSELECT ,Controls the internal 1.5Kohms pull-up resistor and 45ohms HS terminations" "HS,FS"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " XCVRSELECT ,Select the required transceiver speed" "HS,FS,LS,FS for LS packets"
|
|
line.byte 0x01 "ULPI_FUNCTION_CTRL_SET_1,Controls UTMI Function Settings Of The PHY"
|
|
line.byte 0x02 "ULPI_FUNCTION_CTRL_CLR_1,Controls UTMI Function Settings Of The PHY"
|
|
group.byte (0x900+0x7)++0x2
|
|
line.byte 0x00 "ULPI_INTERFACE_CTRL_1,Enables Alternative Interfaces And PHY Features"
|
|
bitfld.byte 0x00 7. " INTERFACE_PROTECT_DISABLE ,Controls circuitry built into the PHY" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AUTORESUME ,Enables the PHY to automatically drive resume signaling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CLOCKSUSPENDM ,Active low clock suspend for serial modes" "Stop,Run"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FSLSSERIALMODE_3PIN ,Sets the ULPI interface to 3-pin Serial Mode" "Normal,3-pin serial"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSLSSERIALMODE_6PIN ,Sets the ULPI interface to 6-pin Serial Mode" "Normal,6-pin serial"
|
|
line.byte 0x01 "ULPI_INTERFACE_CTRL_SET_1,Enables Alternative Interfaces And PHY Features"
|
|
line.byte 0x02 "ULPI_INTERFACE_CTRL_CLR_1,Enables Alternative Interfaces And PHY Features"
|
|
group.byte (0x900+0xA)++0x0
|
|
line.byte 0x00 "ULPI_OTG_CTRL_1,Controls UTMI+ OTG Functions Of The PHY"
|
|
bitfld.byte 0x00 5. " DRVVBUS ,Drive 5V on VBUS" "No action,Drive"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CHRGVBUS ,Charge VBUS through a resistor for VBUS-pulsing SRP" "No action,Charge"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DISCHRGVBUS ,Discharge VBUS through a resistor" "No action,Discharge"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DMPULLDOWN ,Enables the 15k Ohm pull-down resistor on D-" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DPPULLDOWN ,Enables the 15k Ohm pull-down resistor on D+" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IDPULLUP ,Pull-up to the (OTG) ID line to allow its sampling" "Disabled,Enabled"
|
|
sif (cpu()=="OMAP3517"||cpu()=="OMAP3505")
|
|
group.long (0x900+0xB)++0x01
|
|
line.byte 0x00 "ULPI_OTG_CTRL_SET_1,Controls UTMI+ OTG Functions Of The PHY"
|
|
line.byte 0x01 "ULPI_OTG_CTRL_CLR_1,Controls UTMI+ OTG Functions Of The PHY"
|
|
endif
|
|
group.byte (0x900+0xD)++0x2
|
|
line.byte 0x00 "ULPI_USB_INT_EN_RISE_1,Enables An Interrupt Event Notification"
|
|
bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification for IdGnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification for SessEnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification for SessValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification for VbusValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification fpr Hostdisconnect" "No interrupt,Interrupt"
|
|
line.byte 0x01 "ULPI_USB_INT_EN_RISE_SET_1,Enables An Interrupt Event Notification"
|
|
line.byte 0x02 "ULPI_USB_INT_EN_RISE_CLR_1,Enables An Interrupt Event Notification"
|
|
group.byte (0x900+0x10)++0x2
|
|
line.byte 0x00 "ULPI_USB_INT_EN_FALL_1,Enables An Interrupt Event Notification"
|
|
bitfld.byte 0x00 4. " IDGND_FALL ,Generate an interrupt event notification for IdGnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND_FALL ,Generate an interrupt event notification for SessEnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID_FALL ,Generate an interrupt event notification for SessValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID_FALL ,Generate an interrupt event notification for VbusValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT_FALL ,Generate an interrupt event notification fpr Hostdisconnect" "No interrupt,Interrupt"
|
|
line.byte 0x01 "ULPI_USB_INT_EN_FALL_SET_1,Enables An Interrupt Event Notification"
|
|
line.byte 0x02 "ULPI_USB_INT_EN_FALL_CLR_1,Enables An Interrupt Event Notification"
|
|
rgroup.byte (0x900+0x13)++0x0
|
|
line.byte 0x00 "ULPI_USB_INT_STATUS_1,Indicates The Current Value Of The Interrupt Source Signal"
|
|
bitfld.byte 0x00 4. " IDGND ,Value of UTMI+ IdDig output" "Grounded,Floating"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND ,Current value of UTMI+ SessEnd output" "> Session-End,< Session-End"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID ,Current value of UTMI+ SessValid output" "> Session-Valid,< Session-Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID ,Current value of UTMI+ VbusValid output" "> Vbus-Valid,< Vbus-Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT ,Current value of UTMI+ Hostdisconnect output" "Not disconnected/Non-host mode,Disconnected"
|
|
hgroup.byte (0x900+0x14)++0x0
|
|
hide.byte 0x00 "ULPI_USB_INT_LATCH_1,ULPI Interrupt Status Register"
|
|
in
|
|
rgroup.byte (0x900+0x15)++0x0
|
|
line.byte 0x00 "ULPI_DEBUG_1,Indicates The Current Value Of Various Signals Useful For Debugging"
|
|
bitfld.byte 0x00 0.--1. " LINESTATE ,Current state of the USB line D+ (bit 0) and D- (bit 1)" "SE0 (LS/FS) Squelch (HS/Chirp),LS=K/FS=J/HS=!Squelch/Chirp=!Squelch & HS_DRO,LS=J/FS=K/HS=Invalid/Chirp=!Squelch & !HS_DRO,SE1 (LS/FS) Invalid (HS/Chirp)"
|
|
group.byte (0x900+0x16)++0x2
|
|
line.byte 0x00 "ULPI_SCRATCH_REGISTER_1,Register Byte For Register Access Testing Purposes"
|
|
line.byte 0x01 "ULPI_SCRATCH_REGISTER_SET_1,Register Byte For Register Access Testing Purposes"
|
|
line.byte 0x02 "ULPI_SCRATCH_REGISTER_CLR_1,Register Byte For Register Access Testing Purposes"
|
|
group.byte (0x900+0x30)++0x2
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_EN_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
bitfld.byte 0x00 7. " VC7_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " VC6_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " VC5_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " VC4_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VC3_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " VC2_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VC1_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " VC0_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
line.byte 0x01 "ULPI_UTMI_VCONTROL_EN_SET_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x02 "ULPI_UTMI_VCONTROL_EN_CLR_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
group.byte (0x900+0x33)++0x0
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_STATUS_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
rgroup.byte (0x900+0x34)++0x0
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_LATCH_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
bitfld.byte 0x00 7. " VC7_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " VC6_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " VC5_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " VC4_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VC3_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " VC2_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VC1_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " VC0_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
group.byte (0x900+0x35)++0x2
|
|
line.byte 0x00 "ULPI_UTMI_VSTATUS_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x01 "ULPI_UTMI_VSTATUS_SET_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x02 "ULPI_UTMI_VSTATUS_CLR_1,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
rgroup.byte (0x900+0x38)++0x0
|
|
line.byte 0x00 "ULPI_USB_INT_LATCH_NOCLR_1,Set By Unmasked Changes On Status Bits To Generate The ULPI Interrupt"
|
|
group.byte (0x900+0x3B)++0x2
|
|
line.byte 0x00 "ULPI_VENDOR_INT_EN_1,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x00 0. " P2P_EN ,Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm" "Disabled,Enabled"
|
|
line.byte 0x01 "ULPI_VENDOR_INT_EN_SET_1,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
line.byte 0x02 "ULPI_VENDOR_INT_EN_CLR_1,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
rgroup.byte (0x900+0x3E)++0x1
|
|
line.byte 0x00 "ULPI_VENDOR_INT_STATUS_1,Vendor-Specific Interrupt Sources For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x00 0. " UTMI_SUSPENDM ,UTMI suspendm status" "Suspended,Not suspended"
|
|
line.byte 0x01 "ULPI_VENDOR_INT_LATCH_1,Vendor-Specific Interrupt Latches For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x01 0. " P2P_LATCH ,PHY-to-PHY ULPI wakeup event latch" "Not latched,Latched"
|
|
tree.end
|
|
tree "Channel 2"
|
|
width 21.
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "TLL_CHANNEL_CONF_2,Control And Status Register For Channel 2"
|
|
bitfld.long 0x00 28.--29. " FSLSLINESTATE ,Line state for Full/Low speed serial modes" "Single-ended 0,Full-speed J,Full-speed K,Single-ended 1"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " FSLSMODE ,Multiple-mode serial interfaces mode select" "6-pin unidirectional PHY i/f Dat/Se0,6-pin unidirectional PHY i/f Dp/Dm,3-pin bidirectional PHY i/f,4-pin bidirectional PHY i/f,6-pin unidirectional TLL Dat/Se0,6-pin unidirectional TLL Dp/Dm,3-pin bidirectional TLL,4-pin bidirectional TLL,Reserved,Reserved,2-pin bidirectional TLL Dat/Se0,2-pin bidirectional TLL Dp/Dm,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20. " TESTTXSE0 ,Force-Se0 transmit override value for serial mode test" "Differential value,SE0"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TESTTXDAT ,Differential data transmit override value for serial mode test" "Full-speed K,Full-speed J"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TESTTXEN ,Differential data transmit override value for serial mode test" "TestTXDat/Se0,TX Hiz"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TESTEN ,Enable manual test override for serial mode TX path" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " DRVVBUS ,VBUS-drive for ChanMode = serial" "Not driven,Driven to 5V"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CHRGVBUS ,VBUS-drive for ChanMode = serial" "Not charged,Charged"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ULPINOBITSTUFF ,Disable bitstuff emulation in ULPI TLL for ULPI ChanMode" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ULPIAUTOIDLE ,Allow the ULPI output clock to be stopped when ULPI goes into asynchronous mode" "Always on,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 9. " UTMIAUTOIDLE ,Allow the UTMI clock to be stopped when UTMII goes to suspended mode" "Always on,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ULPIDDRMODE ,Select single/double data rate" "SDR,DDR"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ULPIOUTCLKMODE ,ULPI clocking mode select for ULPI TLL ChanMode" "LINK,PHY"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TLLFULLSPEED ,Sets PHY speed emulation in TLL" "Low speed,Full speed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TLLCONNECT ,Emulation of Full/Low-Speed connect" "Unconnected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 4. " TLLATTACH ,Emulates cable attach/detach for all serial TLL modes" "Detach,Attach"
|
|
textline " "
|
|
bitfld.long 0x00 3. " UTMIISADEV ,Select the cable end seen by UTMI side of TLL" "UTMI peripheral/ULPI host,UTMI host/ULPI peripheral"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " CHANMODE ,Main channel mode selection" "UTMI-to-ULPI TLL,UTMI-to-serial,Transparent UTMI,No mode selected"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CHANEN ,Active-high channel enable" "Disabled,Enabled"
|
|
rgroup.byte 0xA00++0x3
|
|
line.byte 0x00 "ULPI_VENDOR_ID_LO_2,Lower Byte Of USB-IF-Supplied Vendor ID Value"
|
|
line.byte 0x01 "ULPI_VENDOR_ID_HI_2,Upper Byte Of USB-IF-Supplied Vendor ID Value"
|
|
line.byte 0x02 "ULPI_PRODUCT_ID_LO_2,Lower Byte Of Vendor-Chosen Product ID Value"
|
|
line.byte 0x03 "ULPI_PRODUCT_ID_HI_2,Upper Byte Of Vendor-Chosen Product ID Value"
|
|
width 29.
|
|
group.byte (0xA00+0x4)++0x2
|
|
line.byte 0x00 "ULPI_FUNCTION_CTRL_2,Controls UTMI Function Settings Of The PHY"
|
|
bitfld.byte 0x00 6. " SUSPENDM ,Active low PHY suspend" "Low-power,Not in low-power"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " RESET ,Active high UTMI transceiver reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--4. " OPMODE ,Select the required bit encoding style during transmit" "Normal,Non-driving,Disable bit-stuff/NRZI encoding,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TERMSELECT ,Controls the internal 1.5Kohms pull-up resistor and 45ohms HS terminations" "HS,FS"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " XCVRSELECT ,Select the required transceiver speed" "HS,FS,LS,FS for LS packets"
|
|
line.byte 0x01 "ULPI_FUNCTION_CTRL_SET_2,Controls UTMI Function Settings Of The PHY"
|
|
line.byte 0x02 "ULPI_FUNCTION_CTRL_CLR_2,Controls UTMI Function Settings Of The PHY"
|
|
group.byte (0xA00+0x7)++0x2
|
|
line.byte 0x00 "ULPI_INTERFACE_CTRL_2,Enables Alternative Interfaces And PHY Features"
|
|
bitfld.byte 0x00 7. " INTERFACE_PROTECT_DISABLE ,Controls circuitry built into the PHY" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " AUTORESUME ,Enables the PHY to automatically drive resume signaling" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CLOCKSUSPENDM ,Active low clock suspend for serial modes" "Stop,Run"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FSLSSERIALMODE_3PIN ,Sets the ULPI interface to 3-pin Serial Mode" "Normal,3-pin serial"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " FSLSSERIALMODE_6PIN ,Sets the ULPI interface to 6-pin Serial Mode" "Normal,6-pin serial"
|
|
line.byte 0x01 "ULPI_INTERFACE_CTRL_SET_2,Enables Alternative Interfaces And PHY Features"
|
|
line.byte 0x02 "ULPI_INTERFACE_CTRL_CLR_2,Enables Alternative Interfaces And PHY Features"
|
|
group.byte (0xA00+0xA)++0x0
|
|
line.byte 0x00 "ULPI_OTG_CTRL_2,Controls UTMI+ OTG Functions Of The PHY"
|
|
bitfld.byte 0x00 5. " DRVVBUS ,Drive 5V on VBUS" "No action,Drive"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " CHRGVBUS ,Charge VBUS through a resistor for VBUS-pulsing SRP" "No action,Charge"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DISCHRGVBUS ,Discharge VBUS through a resistor" "No action,Discharge"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DMPULLDOWN ,Enables the 15k Ohm pull-down resistor on D-" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " DPPULLDOWN ,Enables the 15k Ohm pull-down resistor on D+" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " IDPULLUP ,Pull-up to the (OTG) ID line to allow its sampling" "Disabled,Enabled"
|
|
sif (cpu()=="OMAP3517"||cpu()=="OMAP3505")
|
|
group.long (0xA00+0xB)++0x01
|
|
line.byte 0x00 "ULPI_OTG_CTRL_SET_2,Controls UTMI+ OTG Functions Of The PHY"
|
|
line.byte 0x01 "ULPI_OTG_CTRL_CLR_2,Controls UTMI+ OTG Functions Of The PHY"
|
|
endif
|
|
group.byte (0xA00+0xD)++0x2
|
|
line.byte 0x00 "ULPI_USB_INT_EN_RISE_2,Enables An Interrupt Event Notification"
|
|
bitfld.byte 0x00 4. " IDGND_RISE ,Generate an interrupt event notification for IdGnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND_RISE ,Generate an interrupt event notification for SessEnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID_RISE ,Generate an interrupt event notification for SessValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID_RISE ,Generate an interrupt event notification for VbusValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT_RISE ,Generate an interrupt event notification fpr Hostdisconnect" "No interrupt,Interrupt"
|
|
line.byte 0x01 "ULPI_USB_INT_EN_RISE_SET_2,Enables An Interrupt Event Notification"
|
|
line.byte 0x02 "ULPI_USB_INT_EN_RISE_CLR_2,Enables An Interrupt Event Notification"
|
|
group.byte (0xA00+0x10)++0x2
|
|
line.byte 0x00 "ULPI_USB_INT_EN_FALL_2,Enables An Interrupt Event Notification"
|
|
bitfld.byte 0x00 4. " IDGND_FALL ,Generate an interrupt event notification for IdGnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND_FALL ,Generate an interrupt event notification for SessEnd" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID_FALL ,Generate an interrupt event notification for SessValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID_FALL ,Generate an interrupt event notification for VbusValid" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT_FALL ,Generate an interrupt event notification fpr Hostdisconnect" "No interrupt,Interrupt"
|
|
line.byte 0x01 "ULPI_USB_INT_EN_FALL_SET_2,Enables An Interrupt Event Notification"
|
|
line.byte 0x02 "ULPI_USB_INT_EN_FALL_CLR_2,Enables An Interrupt Event Notification"
|
|
rgroup.byte (0xA00+0x13)++0x0
|
|
line.byte 0x00 "ULPI_USB_INT_STATUS_2,Indicates The Current Value Of The Interrupt Source Signal"
|
|
bitfld.byte 0x00 4. " IDGND ,Value of UTMI+ IdDig output" "Grounded,Floating"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " SESSEND ,Current value of UTMI+ SessEnd output" "> Session-End,< Session-End"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SESSVALID ,Current value of UTMI+ SessValid output" "> Session-Valid,< Session-Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VBUSVALID ,Current value of UTMI+ VbusValid output" "> Vbus-Valid,< Vbus-Valid"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " HOSTDISCONNECT ,Current value of UTMI+ Hostdisconnect output" "Not disconnected/Non-host mode,Disconnected"
|
|
hgroup.byte (0xA00+0x14)++0x0
|
|
hide.byte 0x00 "ULPI_USB_INT_LATCH_2,ULPI Interrupt Status Register"
|
|
in
|
|
rgroup.byte (0xA00+0x15)++0x0
|
|
line.byte 0x00 "ULPI_DEBUG_2,Indicates The Current Value Of Various Signals Useful For Debugging"
|
|
bitfld.byte 0x00 0.--1. " LINESTATE ,Current state of the USB line D+ (bit 0) and D- (bit 1)" "SE0 (LS/FS) Squelch (HS/Chirp),LS=K/FS=J/HS=!Squelch/Chirp=!Squelch & HS_DRO,LS=J/FS=K/HS=Invalid/Chirp=!Squelch & !HS_DRO,SE1 (LS/FS) Invalid (HS/Chirp)"
|
|
group.byte (0xA00+0x16)++0x2
|
|
line.byte 0x00 "ULPI_SCRATCH_REGISTER_2,Register Byte For Register Access Testing Purposes"
|
|
line.byte 0x01 "ULPI_SCRATCH_REGISTER_SET_2,Register Byte For Register Access Testing Purposes"
|
|
line.byte 0x02 "ULPI_SCRATCH_REGISTER_CLR_2,Register Byte For Register Access Testing Purposes"
|
|
group.byte (0xA00+0x30)++0x2
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_EN_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
bitfld.byte 0x00 7. " VC7_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " VC6_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " VC5_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " VC4_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VC3_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " VC2_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VC1_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " VC0_EN ,enable alt_int assertion upon vcontrol_status bit change" "Disabled,Enabled"
|
|
line.byte 0x01 "ULPI_UTMI_VCONTROL_EN_SET_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x02 "ULPI_UTMI_VCONTROL_EN_CLR_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
group.byte (0xA00+0x33)++0x0
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_STATUS_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
rgroup.byte (0xA00+0x34)++0x0
|
|
line.byte 0x00 "ULPI_UTMI_VCONTROL_LATCH_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
bitfld.byte 0x00 7. " VC7_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 6. " VC6_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " VC5_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " VC4_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " VC3_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 2. " VC2_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " VC1_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " VC0_CHANGE ,Unmasked change on vcontrol_status bit" "Not occurred,Occurred"
|
|
group.byte (0xA00+0x35)++0x2
|
|
line.byte 0x00 "ULPI_UTMI_VSTATUS_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x01 "ULPI_UTMI_VSTATUS_SET_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
line.byte 0x02 "ULPI_UTMI_VSTATUS_CLR_2,Part Of Non-Standard UTMI-To-ULPI Mailbox System"
|
|
rgroup.byte (0xA00+0x38)++0x0
|
|
line.byte 0x00 "ULPI_USB_INT_LATCH_NOCLR_2,Set By Unmasked Changes On Status Bits To Generate The ULPI Interrupt"
|
|
group.byte (0xA00+0x3B)++0x2
|
|
line.byte 0x00 "ULPI_VENDOR_INT_EN_2,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x00 0. " P2P_EN ,Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm" "Disabled,Enabled"
|
|
line.byte 0x01 "ULPI_VENDOR_INT_EN_SET_2,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
line.byte 0x02 "ULPI_VENDOR_INT_EN_CLR_2,Vendor-Specific Interrupt Enables (Mask) For Miscellaneous ULPI alt_int Events"
|
|
rgroup.byte (0xA00+0x3E)++0x1
|
|
line.byte 0x00 "ULPI_VENDOR_INT_STATUS_2,Vendor-Specific Interrupt Sources For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x00 0. " UTMI_SUSPENDM ,UTMI suspendm status" "Suspended,Not suspended"
|
|
line.byte 0x01 "ULPI_VENDOR_INT_LATCH_2,Vendor-Specific Interrupt Latches For Miscellaneous ULPI alt_int Events"
|
|
bitfld.byte 0x01 0. " P2P_LATCH ,PHY-to-PHY ULPI wakeup event latch" "Not latched,Latched"
|
|
tree.end
|
|
tree.end
|
|
tree "UHH_config"
|
|
base ad:0x48064000
|
|
width 16.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "UHH_REVISION,Standard Revision Number"
|
|
hexmask.long.byte 0x00 4.--7. 1. " MAJ_REV ,Major revision number"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MIN_REV ,Minor revision number"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "UHH_SYSCONFIG,OCP Standard System Configuration Register"
|
|
bitfld.long 0x00 12.--13. " MIDLEMODE ,Master interface power management control" "Force standby,No standby,Smart standby,?..."
|
|
bitfld.long 0x00 8. " CACTIVITY ,Control of clock internal gating while module is idle" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management control" "Force idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Asynchronous wakeup generation control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Module software reset" "No effect,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal autogating control" "Always running,Cut off"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "UHH_SYSSTATUS,OCP Standard System Status Register"
|
|
bitfld.long 0x00 2. " EHCI_RESETDONE ,Indicated when the EHCI HS host is out of reset" "Ongoing,Done"
|
|
bitfld.long 0x00 1. " OHCI_RESETDONE ,Indicates when the OHCI FS/LS host is out of reset" "Ongoing,Done"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESETDONE ,Indicates when the USB Host has come out of reset" "Ongoing,Done"
|
|
group.long 0x40++0x7
|
|
line.long 0x00 "UHH_HOSTCONFIG,Static Configuration Of The OTG Controller Host"
|
|
bitfld.long 0x00 1. " AUTOPPD_ON_OVERCUR_EN ,Configure reaction upon port overcurrent condition" "Remains on,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ULPI_BYPASS ,Output ports mode control" "ULPI,UTMI"
|
|
line.long 0x04 "UHH_DEBUG_CSR,Debug Control And Status For The EHCI"
|
|
bitfld.long 0x04 19. " OHCI_CCS_3 ,Current Connect Status of port 3" "Not connected,Connected"
|
|
bitfld.long 0x04 18. " OHCI_CCS_2 ,Current Connect Status of port 2" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x04 17. " OHCI_CCS_1 ,Current Connect Status of port 1" "Not connected,Connected"
|
|
bitfld.long 0x04 16. " OHCI_GLOBALSUSPEND ,OHCI global suspend status" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x04 7. " OCHI_CNTSEL ,Selection of a shorter 1 ms counter in OHCI host" "Functional,Simulation"
|
|
bitfld.long 0x04 6. " EHCI_SIMULATION_MODE ,Sets the PHY to non-driving mode" "Functional,Non-driving"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--5. 1. " EHCI_FLADJ ,EHCI host frame length adjust"
|
|
width 0xb
|
|
tree.end
|
|
tree "OHCI"
|
|
base ad:0x48064400
|
|
width 21.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "HCREVISION,OHCI Revision Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,OHCI specification revision"
|
|
group.long 0x04++0x17
|
|
line.long 0x00 "HCCONTROL,HC Operating Mode Register"
|
|
bitfld.long 0x00 10. " RWE ,Remote wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RWC ,Remote wake-up connected" "Not connected,Connected"
|
|
textline " "
|
|
bitfld.long 0x00 8. " IR ,Interrupt routing" "0,1"
|
|
bitfld.long 0x00 6.--7. " HCFS ,Host controller functional state" "Reset,Resume,Operational,Suspend"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BLE ,Bulk list processing enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CLE ,Control list processing enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IE ,Isochronous ED processing enabled by host controller driver" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PLE ,Periodic list enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CBSR ,Control/bulk service ratio" "1,2,3,4"
|
|
line.long 0x04 "HCCOMMANDSTATUS,HC Command and Status"
|
|
bitfld.long 0x04 16.--17. " SOC ,Scheduling overrun count" "0,1,2,3"
|
|
bitfld.long 0x04 3. " OCR ,Ownership change request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 2. " BLF ,Bulk list filled" "Not filled,Filled"
|
|
bitfld.long 0x04 1. " CLF ,Control list filled" "Not filled,Filled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " HCR ,Host controller reset" "No effect,Reset"
|
|
line.long 0x08 "HCINTERRUPTSTATUS,HC Interrupt Status"
|
|
bitfld.long 0x08 30. " OC ,Ownership change" "Not changed,Changed"
|
|
eventfld.long 0x08 6. " RHSC ,Root hub status change" "No effect,Changed"
|
|
textline " "
|
|
eventfld.long 0x08 5. " FNO ,Frame number overflow" "No effect,Overflow"
|
|
eventfld.long 0x08 4. " UE ,Unrecoverable error" "No effect,Error"
|
|
textline " "
|
|
eventfld.long 0x08 3. " RD ,Resume detected" "No effect,Resume"
|
|
eventfld.long 0x08 2. " SF ,Start of frame" "No effect,SOF"
|
|
textline " "
|
|
eventfld.long 0x08 1. " WDH ,Write done head" "No effect,Written"
|
|
eventfld.long 0x08 0. " SO ,Scheduling overrun" "No effect,Overrun"
|
|
line.long 0x0c "HCINTERRUPTENABLE,HC Interrupt Enable"
|
|
bitfld.long 0x0C 31. " MIE ,Master interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " OC ,Ownership change" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " RHSC ,Root hub status change" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " FNO ,Frame number overflow" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " UE ,Unrecoverable error" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " RD ,Resume detected" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " SF ,Start of frame" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " WDH ,Write done head" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 0. " SO ,Scheduling overrun" "Disabled,Enabled"
|
|
line.long 0x10 "HCINTERRUPTDISABLE,HC Interrupt Disable"
|
|
bitfld.long 0x10 31. " MIE ,Master interrupt enable" "No effect,Disabled"
|
|
bitfld.long 0x10 30. " OC ,Ownership change" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 6. " RHSC ,Root hub status change" "No effect,Disabled"
|
|
bitfld.long 0x10 5. " FNO ,Frame number overflow" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 4. " UE ,Unrecoverable error" "No effect,Disabled"
|
|
bitfld.long 0x10 3. " RD ,Resume detected" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " SF ,Start of frame" "No effect,Disabled"
|
|
bitfld.long 0x10 1. " WDH ,Write done head RW 0" "No effect,Disabled"
|
|
textline " "
|
|
bitfld.long 0x10 0. " SO ,Scheduling overrun" "No effect,Disabled"
|
|
line.long 0x14 "HCHCCA,HC HCCA Address Register"
|
|
hexmask.long 0x14 8.--31. 0x100 " HCCA ,Physical address of the beginning of the HCCA"
|
|
rgroup.long 0x1c++0x3
|
|
line.long 0x00 "HCPERIODCURRENTED,HC Current Periodic Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " PCED ,Physical address of current ED on the periodic ED list"
|
|
group.long 0x20++0xf
|
|
line.long 0x00 "HCCONTROLHEADED,HC Head Control Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " CHED ,Physical address of head ED on the control ED list"
|
|
line.long 0x04 "HCCONTROLCURRENTED,HC Current Control Register"
|
|
hexmask.long 0x04 4.--31. 0x10 " CCED ,Physical address of current ED on the control ED list"
|
|
line.long 0x08 "HCBULKHEADED,HC Head Bulk Register"
|
|
hexmask.long 0x08 4.--31. 0x10 " BHED ,Physical address of head ED on the bulk ED list"
|
|
line.long 0x0c "HCBULKCURRENTED,HC Current Bulk Register"
|
|
hexmask.long 0x0C 4.--31. 0x10 " BCED ,Physical address of current ED on the bulk ED list"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x00 "HCDONEHEAD,HC Head Done Register"
|
|
hexmask.long 0x00 4.--31. 0x10 " DH ,Physical address of last TD that was added to the Done queue"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "HCFMINTERVAL,HC Frame Interval Register"
|
|
bitfld.long 0x00 31. " FIT ,Frame interval toggle" "0,1"
|
|
hexmask.long.word 0x00 16.--30. 1. " FSMPS ,Largest data packet size for full-speed packets"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--13. 1. " FI ,Frame interval"
|
|
rgroup.long 0x38++0x7
|
|
line.long 0x00 "HCFMREMAINING,HC Frame Remaining Register"
|
|
bitfld.long 0x00 31. " FRT ,Frame remaining toggle" "0,1"
|
|
hexmask.long.word 0x00 0.--13. 1. " FR ,Frame remaining"
|
|
line.long 0x04 "HCFMNUMBER,HC Frame Number Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " FN ,Frame number"
|
|
group.long 0x40++0x13
|
|
line.long 0x00 "HCPERIODICSTART,HC Periodic Start Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic start"
|
|
line.long 0x04 "HCLSTHRESHOLD,HC Low-speed Threshold Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " LST ,Low-speed threshold"
|
|
line.long 0x08 "HCRHDESCRIPTORA,HC Root Hub A Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " POTPG ,Power-on to power-good time"
|
|
bitfld.long 0x08 12. " NOCP ,No overcurrent protection" "Protection,No protection"
|
|
textline " "
|
|
bitfld.long 0x08 11. " OCPM ,Overcurrent protection mode" "0,1"
|
|
bitfld.long 0x08 10. " DT ,Device type" "Not compound,?..."
|
|
textline " "
|
|
bitfld.long 0x08 9. " NPS ,No power switching" "Switching,No switching"
|
|
bitfld.long 0x08 8. " PSM ,Power switching mode" "Same,Individual"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " NDP ,Number of downstream ports"
|
|
line.long 0x0c "HCRHDESCRIPTORB,HC Root Hub B Register"
|
|
bitfld.long 0x0c 31. " PPCM[15] ,Gange D-power mask on port #15" "Global,Port"
|
|
bitfld.long 0x0c 30. " PPCM[14] ,Gange D-power mask on port #14" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " PPCM[13] ,Gange D-power mask on port #13" "Global,Port"
|
|
bitfld.long 0x0c 28. " PPCM[12] ,Gange D-power mask on port #12" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " PPCM[11] ,Gange D-power mask on port #11" "Global,Port"
|
|
bitfld.long 0x0c 26. " PPCM[10] ,Gange D-power mask on port #10" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " PPCM[9] ,Gange D-power mask on port #9" "Global,Port"
|
|
bitfld.long 0x0c 24. " PPCM[8] ,Gange D-power mask on port #8" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " PPCM[7] ,Gange D-power mask on port #7" "Global,Port"
|
|
bitfld.long 0x0c 22. " PPCM[6] ,Gange D-power mask on port #6" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " PPCM[5] ,Gange D-power mask on port #5" "Global,Port"
|
|
bitfld.long 0x0c 20. " PPCM[4] ,Gange D-power mask on port #4" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " PPCM[3] ,Gange D-power mask on port #3" "Global,Port"
|
|
bitfld.long 0x0c 18. " PPCM[2] ,Gange D-power mask on port #2" "Global,Port"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " PPCM[1] ,Gange D-power mask on port #1" "Global,Port"
|
|
bitfld.long 0x0c 15. " DR[15] ,Device attached to port #15" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 14. " DR[14] ,Device attached to port #14" "Removable,Not removable"
|
|
bitfld.long 0x0c 13. " DR[13] ,Device attached to port #13" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " DR[12] ,Device attached to port #12" "Removable,Not removable"
|
|
bitfld.long 0x0c 11. " DR[11] ,Device attached to port #11" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " DR[10] ,Device attached to port #10" "Removable,Not removable"
|
|
bitfld.long 0x0c 9. " DR[9] ,Device attached to port #9" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 8. " DR[8] ,Device attached to port #8" "Removable,Not removable"
|
|
bitfld.long 0x0c 7. " DR[7] ,Device attached to port #7" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 6. " DR[6] ,Device attached to port #6" "Removable,Not removable"
|
|
bitfld.long 0x0c 5. " DR[5] ,Device attached to port #5" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 4. " DR[4] ,Device attached to port #4" "Removable,Not removable"
|
|
bitfld.long 0x0c 3. " DR[3] ,Device attached to port #3" "Removable,Not removable"
|
|
textline " "
|
|
bitfld.long 0x0c 2. " DR[2] ,Device attached to port #2" "Removable,Not removable"
|
|
bitfld.long 0x0c 1. " DR[1] ,Device attached to port #1" "Removable,Not removable"
|
|
line.long 0x10 "HCRHSTATUS,HC Root Hub Status Register"
|
|
bitfld.long 0x10 31. " CRWE ,Clear remote wake-up enable" "No effect,Cleared"
|
|
eventfld.long 0x10 17. " OCIC ,Overcurrent indication change" "No effect,Changed"
|
|
textline " "
|
|
bitfld.long 0x10 16. " LPSC ,Local power status change" "No effect,Changed"
|
|
bitfld.long 0x10 15. " DRWE ,Device remote wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " OCI ,Overcurrent indicator" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x10 0. " LPS ,Local power status" "No effect,Turned off"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS_1,HC Port 1 Status and Control Register"
|
|
eventfld.long 0x00 20. " PRSC ,Port 1 reset status change" "No effect,Changed"
|
|
eventfld.long 0x00 19. " OCIC ,Port 1 overcurrent indicator change" "No effect,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port 1 suspend status change" "No effect,Changed"
|
|
eventfld.long 0x00 17. " PESC ,Port 1 enable status change" "No effect,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Port 1 connect status change" "No effect,Changed"
|
|
bitfld.long 0x00 9. " LSDA_CPP ,Port 1 low-speed device attached/clear port power" "Full,Low"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS_SPP ,Port 1 power status/set port power" "Enabled,Not enabled"
|
|
bitfld.long 0x00 4. " PRS_SPR ,Port 1 reset status/set port reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI_CSS ,Port 1 overcurrent indicator/clear suspend status" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x00 2. " PSS_SPS ,Port 1 suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES_SPE ,Port 1 status/set enable" "Not enabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS_CPE ,Port 1 current connection status/clear port enable" "No device,Device"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS_2,HC Port 2 Status and Control Register"
|
|
eventfld.long 0x00 20. " PRSC ,Port 2 reset status change" "No effect,Changed"
|
|
eventfld.long 0x00 19. " OCIC ,Port 2 overcurrent indicator change" "No effect,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port 2 suspend status change" "No effect,Changed"
|
|
eventfld.long 0x00 17. " PESC ,Port 2 enable status change" "No effect,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Port 2 connect status change" "No effect,Changed"
|
|
bitfld.long 0x00 9. " LSDA_CPP ,Port 2 low-speed device attached/clear port power" "Full,Low"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS_SPP ,Port 2 power status/set port power" "Enabled,Not enabled"
|
|
bitfld.long 0x00 4. " PRS_SPR ,Port 2 reset status/set port reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI_CSS ,Port 2 overcurrent indicator/clear suspend status" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x00 2. " PSS_SPS ,Port 2 suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES_SPE ,Port 2 status/set enable" "Not enabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS_CPE ,Port 2 current connection status/clear port enable" "No device,Device"
|
|
group.long 0x5C++0x3
|
|
line.long 0x00 "HCRHPORTSTATUS_3,HC Port 3 Status and Control Register"
|
|
eventfld.long 0x00 20. " PRSC ,Port 3 reset status change" "No effect,Changed"
|
|
eventfld.long 0x00 19. " OCIC ,Port 3 overcurrent indicator change" "No effect,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 18. " PSSC ,Port 3 suspend status change" "No effect,Changed"
|
|
eventfld.long 0x00 17. " PESC ,Port 3 enable status change" "No effect,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 16. " CSC ,Port 3 connect status change" "No effect,Changed"
|
|
bitfld.long 0x00 9. " LSDA_CPP ,Port 3 low-speed device attached/clear port power" "Full,Low"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS_SPP ,Port 3 power status/set port power" "Enabled,Not enabled"
|
|
bitfld.long 0x00 4. " PRS_SPR ,Port 3 reset status/set port reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " POCI_CSS ,Port 3 overcurrent indicator/clear suspend status" "No overcurrent,Overcurrent"
|
|
bitfld.long 0x00 2. " PSS_SPS ,Port 3 suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PES_SPE ,Port 3 status/set enable" "Not enabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS_CPE ,Port 3 current connection status/clear port enable" "No device,Device"
|
|
width 0xb
|
|
tree.end
|
|
tree "EHCI"
|
|
base ad:0x48064800
|
|
width 18.
|
|
rgroup.long 0x00++0xb
|
|
line.long 0x00 "HCCAPBASE,Host Controller Capability Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,HCI VERSION"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,CAP LENGTH"
|
|
line.long 0x04 "HCSPARAMS,Host Controller Structural Parameters"
|
|
bitfld.long 0x04 16. " P_INDICATOR ,Port indicator support indication" "0,1"
|
|
bitfld.long 0x04 12.--15. " N_CC ,Number of Companion Controllers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " N_PCC ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 7. " PRR ,Port Routing Rules" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 4. " PPC ,Port Power control" "0,1"
|
|
bitfld.long 0x04 0.--3. " N_PORTS ,Number of downstream ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "HCCPARAMS,Host Controller Capability Parameters"
|
|
hexmask.long.byte 0x08 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer"
|
|
bitfld.long 0x08 4.--7. " IST ,Isochronous Scheduling Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x08 2. " ASPC ,Asynchronous Schedule Park Capability" "0,1"
|
|
bitfld.long 0x08 1. " PFLF ,Programmable Frame List Flag" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 0. " BIT64AC ,64-bit addressing capability" "0,1"
|
|
group.long 0x10++0xF
|
|
line.long 0x00 "USBCMD,USB Command"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control"
|
|
bitfld.long 0x00 11. " ASPME ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " ASPMC ,Asynchronous Schedule Park Mode Count" "0,1,2,3"
|
|
bitfld.long 0x00 7. " LHCR ,Light Host Controller Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IAAD ,Interrupt on Async Advance Doorbell" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--3. " FLS ,Frame List Size" "0,1,2,3"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HCR ,Host Controller Reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " RS ,Run/stop" "Run,Stop"
|
|
line.long 0x04 "USBSTS,USB Status"
|
|
bitfld.long 0x04 15. " ASS ,Asynchronous Schedule Status" "0,1"
|
|
bitfld.long 0x04 14. " PSS ,Periodic Schedule Status" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 13. " REC ,Reclamation" "0,1"
|
|
bitfld.long 0x04 12. " HCH ,Host Controller Halted" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x04 5. " IAA ,Interrept on Async Advance" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 4. " HSE ,Host System Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FLR ,Frame List Rollover" "No effect,Rollover"
|
|
bitfld.long 0x04 2. " PCD ,Port Change Detect" "No change,Changed"
|
|
textline " "
|
|
bitfld.long 0x04 1. " USBEI ,USB Error Interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " USBI ,USB Interrupt" "No interrupt,Interrupt"
|
|
line.long 0x08 "USBINTR,USB Interrupt Enable"
|
|
bitfld.long 0x08 5. " IAAE ,Interrupt on Async Advance Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HSEE ,Host System Error Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " FLRE ,Frame List Rollover Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " PCIE ,Port Change Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " USBEIE ,USB Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " USBIE ,USB Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x0C "FRINDEX,USB Frame Index"
|
|
hexmask.long.word 0x0C 0.--13. 1. " FI ,Frame Index"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x00 "CTRLDSSEGMENT,4G Segment Selector"
|
|
group.long 0x24++0x7
|
|
line.long 0x00 "PERIODICLISTBASE,Frame List Base Address"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BAL ,Base Address (Low)"
|
|
line.long 0x04 "ASYNCLISTADDR,Next Asynchronous List Address"
|
|
hexmask.long 0x04 5.--31. 0x10 " LPL ,Link Pointer Low"
|
|
group.long 0x50++0xF
|
|
line.long 0x00 "CONFIGFLAG,Configured Flag Register"
|
|
bitfld.long 0x00 0. " CF , Configure Flag" "0,1"
|
|
line.long 0x4 "PORTSC_0,Port Status / Control 0"
|
|
bitfld.long 0x4 22. " WOCE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x4 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x4 16.--19. " PTC ,Port Test Control" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x4 14.--15. " PIC ,Port Indicator Control" "0,1,?..."
|
|
bitfld.long 0x4 13. " PO ,Port Owner" "0,1"
|
|
textline " "
|
|
bitfld.long 0x4 12. " PP ,Port Power" "0,1"
|
|
bitfld.long 0x4 10.--11. " LS ,Line Status" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x4 8. " PR ,Port Reset" "No reset,Reset"
|
|
bitfld.long 0x4 7. " SUS ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x4 6. " FPR ,Force Port Resume" "No effect,Forced"
|
|
bitfld.long 0x4 5. " OCC ,Over Current Change" "No change,Changed"
|
|
textline " "
|
|
bitfld.long 0x4 4. " OCA ,Over Current Active" "Not active,Active"
|
|
bitfld.long 0x4 3. " PEDC ,Port Enabled/Disabled Change" "No change,Changed"
|
|
textline " "
|
|
bitfld.long 0x4 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
bitfld.long 0x4 1. " CSC ,Connect Status Change" "No change,Changed"
|
|
textline " "
|
|
bitfld.long 0x4 0. " CCS ,Current Connect Status" "Not connected,Connected"
|
|
line.long 0x8 "PORTSC_1,Port Status / Control 1"
|
|
bitfld.long 0x8 22. " WOCE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x8 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0x8 16.--19. " PTC ,Port Test Control" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x8 14.--15. " PIC ,Port Indicator Control" "0,1,?..."
|
|
bitfld.long 0x8 13. " PO ,Port Owner" "0,1"
|
|
textline " "
|
|
bitfld.long 0x8 12. " PP ,Port Power" "0,1"
|
|
bitfld.long 0x8 10.--11. " LS ,Line Status" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0x8 8. " PR ,Port Reset" "No reset,Reset"
|
|
bitfld.long 0x8 7. " SUS ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0x8 6. " FPR ,Force Port Resume" "No effect,Forced"
|
|
bitfld.long 0x8 5. " OCC ,Over Current Change" "No change,Changed"
|
|
textline " "
|
|
bitfld.long 0x8 4. " OCA ,Over Current Active" "Not active,Active"
|
|
bitfld.long 0x8 3. " PEDC ,Port Enabled/Disabled Change" "No change,Changed"
|
|
textline " "
|
|
bitfld.long 0x8 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
bitfld.long 0x8 1. " CSC ,Connect Status Change" "No change,Changed"
|
|
textline " "
|
|
bitfld.long 0x8 0. " CCS ,Current Connect Status" "Not connected,Connected"
|
|
line.long 0xC "PORTSC_2,Port Status / Control 2"
|
|
bitfld.long 0xC 22. " WOCE ,Wake on Over-Current Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 21. " WDE ,Wake on Disconnect Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0xC 20. " WCE ,Wake on Connect Enable" "Disabled,Enabled"
|
|
bitfld.long 0xC 16.--19. " PTC ,Port Test Control" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0xC 14.--15. " PIC ,Port Indicator Control" "0,1,?..."
|
|
bitfld.long 0xC 13. " PO ,Port Owner" "0,1"
|
|
textline " "
|
|
bitfld.long 0xC 12. " PP ,Port Power" "0,1"
|
|
bitfld.long 0xC 10.--11. " LS ,Line Status" "0,1,?..."
|
|
textline " "
|
|
bitfld.long 0xC 8. " PR ,Port Reset" "No reset,Reset"
|
|
bitfld.long 0xC 7. " SUS ,Suspend" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.long 0xC 6. " FPR ,Force Port Resume" "No effect,Forced"
|
|
bitfld.long 0xC 5. " OCC ,Over Current Change" "No change,Changed"
|
|
textline " "
|
|
bitfld.long 0xC 4. " OCA ,Over Current Active" "Not active,Active"
|
|
bitfld.long 0xC 3. " PEDC ,Port Enabled/Disabled Change" "No change,Changed"
|
|
textline " "
|
|
bitfld.long 0xC 2. " PED ,Port Enabled/Disabled" "Disabled,Enabled"
|
|
bitfld.long 0xC 1. " CSC ,Connect Status Change" "No change,Changed"
|
|
textline " "
|
|
bitfld.long 0xC 0. " CCS ,Current Connect Status" "Not connected,Connected"
|
|
group.long 0x90++0x13
|
|
line.long 0x00 "INSNREG00,Implementation-Specific Register #0"
|
|
hexmask.long.word 0x00 1.--13. 1. " UFRAME_CNT ,1-microframe length value"
|
|
bitfld.long 0x00 0. " EN ,Enable of this register" "Disabled,Enabled"
|
|
line.long 0x04 "INSNREG01,Implementation-Specific Register #1"
|
|
hexmask.long.word 0x04 16.--31. 1. " OUT_THRESHOLD ,Programmable output packet buffer threshold"
|
|
hexmask.long.word 0x04 0.--15. 1. " IN_THRESHOLD ,Programmable input packet buffer threshold"
|
|
line.long 0x08 "INSNREG02,Implementation-Specific Register #2"
|
|
hexmask.long.word 0x08 0.--11. 1. " BUF_DEPTH ,Programmable packet buffer depth"
|
|
line.long 0x0C "INSNREG03,Implementation-Specific Register #3"
|
|
bitfld.long 0x0C 0. " BRK_MEM_TRSF ,Break Memory Transfer" "Disabled,Enabled"
|
|
line.long 0x10 "INSNREG04,Implementation-Specific Register #4"
|
|
bitfld.long 0x10 4. " NAK_FIX_DIS ,Disable NAK fix" "Enabled,Disabled"
|
|
bitfld.long 0x10 2. " SHORT_PORT_ENUM ,Scale down Port enumeration time" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 1. " HCCPARAMS_WRE ,Make read-only HCCPARAMS register writable" "Read only,Writable"
|
|
bitfld.long 0x10 0. " HCSPARAMS_WRE ,Make read-only HCSPARAMS register writable" "Read only,Writable"
|
|
if (((d.l(ad:0x48064040))&0x1)==0x0)
|
|
;UHH_HOSTCONFIG[0] = ULPI
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "INSNREG05_ULPI,Implementation-Specific Register #5"
|
|
bitfld.long 0x00 31. " CONTROL ,Control/status of the ULPI register access" "Done,Start"
|
|
bitfld.long 0x00 24.--27. " PORTSEL ,Port selection" "Reserved,Port 1,Port 2,Port 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " OPSEL ,Register access selection" "Reserved,Reserved,Write,Read"
|
|
hexmask.long.byte 0x00 16.--21. 1. " REGADD ,ULPI direct register address"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " EXTREGADD ,Address for extended register accesses"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WRDATA ,Read/Write data of register access"
|
|
else
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "INSNREG05_UTMI,Implementation-Specific Register #5"
|
|
bitfld.long 0x00 17. " VBUSY ,Vendor interface busy" "Done/Inactive,Busy"
|
|
bitfld.long 0x00 13.--16. " VPORT ,Vendor interface port selection" "Reserved,Port 1,Port 2,Port 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12. " VCONTROLLOADM ,UTMI VcontrolLoadM output" "Load,No action"
|
|
bitfld.long 0x00 8.--11. " VCONTROL ,UTMI Vcontrol output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " VSTATUS ,UTMI Vstatus input image"
|
|
endif
|
|
width 0xb
|
|
tree.end
|
|
tree.end
|
|
tree "High-Speed USB OTG Controller"
|
|
base ad:0x480ab400
|
|
width 16.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "OTG_REVISION,OTG HS Core Revision Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " OTG_REVISION ,Revision number"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "OTG_SYSCONFIG,OCP Standard Configuration"
|
|
bitfld.long 0x00 12.--13. " MIDLEMODE ,Master interface power management" "Force standby,No standby,Smart standby,?..."
|
|
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENABLEWAKEUP ,Enable wakeup capability" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Auto idle enable" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x3
|
|
line.long 0x00 "OTG_SYSSTATUS,OCP Standard Status"
|
|
bitfld.long 0x00 0. " RESETDONE ,Reset done" "Not done,Done"
|
|
group.long 0x0c++0x3
|
|
line.long 0x00 "OTG_INTERFSEL,USB OTG HS Interface Selection"
|
|
bitfld.long 0x00 0.--1. " PHYSEL ,PHY interface selection" "0,1,2,3"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "OTG_FORCESTDBY,FORCESTDBY Enable"
|
|
bitfld.long 0x00 0. " ENABLEFORCE ,MSTANDBY enable" "Disabled,Enabled"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
tree.open "GPIO"
|
|
tree "GPIO1"
|
|
base ad:0x48310000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO Configuration"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt 1 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS1[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS1[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS1[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS1[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS1[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS1[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS1[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS1[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS1[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS1[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS1[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS1[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS1[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS1[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS1[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS1[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS1[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS1[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS1[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS1[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS1[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS1[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS1[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS1[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS1[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS1[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS1[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS1[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS1[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS1[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS1[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS1[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE1,Interrupt 1 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE1[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE1[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE1[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE1[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE1[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE1[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE1[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE1[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE1[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE1[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE1[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE1[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE1[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE1[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE1[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE1[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE1[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE1[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE1[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE1[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE1[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE1[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE1[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE1[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE1[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE1[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE1[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE1[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE1[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE1[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE1[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE1[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_WAKEUPENABLE,Wake Up Enable Register"
|
|
setclrfld.long 0x08 31. 0x6c 31. 0x68 31. " WAKEUPEN[31]_set/clr ,Wakeup generation bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x6c 30. 0x68 30. " WAKEUPEN[30]_set/clr ,Wakeup generation bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 29. 0x6c 29. 0x68 29. " WAKEUPEN[29]_set/clr ,Wakeup generation bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x6c 28. 0x68 28. " WAKEUPEN[28]_set/clr ,Wakeup generation bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. 0x6c 27. 0x68 27. " WAKEUPEN[27]_set/clr ,Wakeup generation bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x6c 26. 0x68 26. " WAKEUPEN[26]_set/clr ,Wakeup generation bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x6c 25. 0x68 25. " WAKEUPEN[25]_set/clr ,Wakeup generation bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x6c 24. 0x68 24. " WAKEUPEN[24]_set/clr ,Wakeup generation bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. 0x6c 23. 0x68 23. " WAKEUPEN[23]_set/clr ,Wakeup generation bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x6c 22. 0x68 22. " WAKEUPEN[22]_set/clr ,Wakeup generation bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 21. 0x6c 21. 0x68 21. " WAKEUPEN[21]_set/clr ,Wakeup generation bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x6c 20. 0x68 20. " WAKEUPEN[20]_set/clr ,Wakeup generation bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x6c 19. 0x68 19. " WAKEUPEN[19]_set/clr ,Wakeup generation bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x6c 18. 0x68 18. " WAKEUPEN[18]_set/clr ,Wakeup generation bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 17. 0x6c 17. 0x68 17. " WAKEUPEN[17]_set/clr ,Wakeup generation bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x6c 16. 0x68 16. " WAKEUPEN[16]_set/clr ,Wakeup generation bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 15. 0x6c 15. 0x68 15. " WAKEUPEN[15]_set/clr ,Wakeup generation bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x6c 14. 0x68 14. " WAKEUPEN[14]_set/clr ,Wakeup generation bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x6c 13. 0x68 13. " WAKEUPEN[13]_set/clr ,Wakeup generation bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x6c 12. 0x68 12. " WAKEUPEN[12]_set/clr ,Wakeup generation bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. 0x6c 11. 0x68 11. " WAKEUPEN[11]_set/clr ,Wakeup generation bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x6c 10. 0x68 10. " WAKEUPEN[10]_set/clr ,Wakeup generation bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 9. 0x6c 9. 0x68 9. " WAKEUPEN[9]_set/clr ,Wakeup generation bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x6c 8. 0x68 8. " WAKEUPEN[8]_set/clr ,Wakeup generation bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x6c 7. 0x68 7. " WAKEUPEN[7]_set/clr ,Wakeup generation bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x6c 6. 0x68 6. " WAKEUPEN[6]_set/clr ,Wakeup generation bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. 0x6c 5. 0x68 5. " WAKEUPEN[5]_set/clr ,Wakeup generation bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x6c 4. 0x68 4. " WAKEUPEN[4]_set/clr ,Wakeup generation bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 3. 0x6c 3. 0x68 3. " WAKEUPEN[3]_set/clr ,Wakeup generation bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x6c 2. 0x68 2. " WAKEUPEN[2]_set/clr ,Wakeup generation bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x6c 1. 0x68 1. " WAKEUPEN[1]_set/clr ,Wakeup generation bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x6c 0. 0x68 0. " WAKEUPEN[0]_set/clr ,Wakeup generation bit 0 enable" "Disabled,Enabled"
|
|
group.long 0x28++0xf
|
|
line.long 0x00 "GPIO_IRQSTATUS2,Interrupt 2 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS2[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS2[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS2[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS2[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS2[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS2[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS2[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS2[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS2[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS2[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS2[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS2[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS2[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS2[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS2[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS2[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS2[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS2[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS2[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS2[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS2[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS2[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS2[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS2[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS2[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS2[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS2[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS2[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS2[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS2[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS2[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS2[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE2,Interrupt 2 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE2[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE2[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE2[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE2[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE2[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE2[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE2[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE2[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE2[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE2[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE2[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE2[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE2[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE2[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE2[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE2[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE2[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE2[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE2[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE2[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE2[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE2[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE2[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE2[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE2[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE2[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE2[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE2[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE2[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE2[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE2[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE2[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_CTRL,GPIO Control"
|
|
bitfld.long 0x08 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x08 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x0c "GPIO_OE,Output Data Enable"
|
|
bitfld.long 0x0c 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x0c 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x0c 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x0c 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x0c 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x0c 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x0c 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x0c 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x0c 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x0c 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x0c 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x0c 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
|
|
bitfld.long 0x0c 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
|
bitfld.long 0x0c 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
|
|
bitfld.long 0x0c 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
|
bitfld.long 0x0c 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
textline " "
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bitfld.long 0x0c 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
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bitfld.long 0x0c 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
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rgroup.long 0x38++0x3
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line.long 0x00 "GPIO_DATAIN,Sampled Input Data"
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group.long 0x3c++0x1b
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line.long 0x00 "GPIO_DATAOUT,Output Data"
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setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
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setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
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textline " "
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setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
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setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
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textline " "
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setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
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setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
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textline " "
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setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
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setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
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textline " "
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setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
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setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
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textline " "
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setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
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setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
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textline " "
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setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
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setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
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textline " "
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setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
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setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
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textline " "
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setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
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setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
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textline " "
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setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
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setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
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textline " "
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setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
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setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
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textline " "
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setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
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setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
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textline " "
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setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
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setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
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textline " "
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setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
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setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
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textline " "
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setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
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setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
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textline " "
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setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
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setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
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line.long 0x04 "GPIO_LEVELDETECT0,Low Level Interrupt Enable"
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bitfld.long 0x04 31. " LOWLEVEL[31] ,Enable the IRQ assertion on low level detect bit 31 " "Disabled,Enabled"
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bitfld.long 0x04 30. " LOWLEVEL[30] ,Enable the IRQ assertion on low level detect bit 30 " "Disabled,Enabled"
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textline " "
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bitfld.long 0x04 29. " LOWLEVEL[29] ,Enable the IRQ assertion on low level detect bit 29 " "Disabled,Enabled"
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bitfld.long 0x04 28. " LOWLEVEL[28] ,Enable the IRQ assertion on low level detect bit 28 " "Disabled,Enabled"
|
|
textline " "
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bitfld.long 0x04 27. " LOWLEVEL[27] ,Enable the IRQ assertion on low level detect bit 27 " "Disabled,Enabled"
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|
bitfld.long 0x04 26. " LOWLEVEL[26] ,Enable the IRQ assertion on low level detect bit 26 " "Disabled,Enabled"
|
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textline " "
|
|
bitfld.long 0x04 25. " LOWLEVEL[25] ,Enable the IRQ assertion on low level detect bit 25 " "Disabled,Enabled"
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bitfld.long 0x04 24. " LOWLEVEL[24] ,Enable the IRQ assertion on low level detect bit 24 " "Disabled,Enabled"
|
|
textline " "
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bitfld.long 0x04 23. " LOWLEVEL[23] ,Enable the IRQ assertion on low level detect bit 23 " "Disabled,Enabled"
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|
bitfld.long 0x04 22. " LOWLEVEL[22] ,Enable the IRQ assertion on low level detect bit 22 " "Disabled,Enabled"
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textline " "
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bitfld.long 0x04 21. " LOWLEVEL[21] ,Enable the IRQ assertion on low level detect bit 21 " "Disabled,Enabled"
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bitfld.long 0x04 20. " LOWLEVEL[20] ,Enable the IRQ assertion on low level detect bit 20 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 19. " LOWLEVEL[19] ,Enable the IRQ assertion on low level detect bit 19 " "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LOWLEVEL[18] ,Enable the IRQ assertion on low level detect bit 18 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LOWLEVEL[17] ,Enable the IRQ assertion on low level detect bit 17 " "Disabled,Enabled"
|
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bitfld.long 0x04 16. " LOWLEVEL[16] ,Enable the IRQ assertion on low level detect bit 16 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 15. " LOWLEVEL[15] ,Enable the IRQ assertion on low level detect bit 15 " "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LOWLEVEL[14] ,Enable the IRQ assertion on low level detect bit 14 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " LOWLEVEL[13] ,Enable the IRQ assertion on low level detect bit 13 " "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LOWLEVEL[12] ,Enable the IRQ assertion on low level detect bit 12 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LOWLEVEL[11] ,Enable the IRQ assertion on low level detect bit 11 " "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LOWLEVEL[10] ,Enable the IRQ assertion on low level detect bit 10 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LOWLEVEL[9] ,Enable the IRQ assertion on low level detect bit 9 " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LOWLEVEL[8] ,Enable the IRQ assertion on low level detect bit 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LOWLEVEL[7] ,Enable the IRQ assertion on low level detect bit 7 " "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LOWLEVEL[6] ,Enable the IRQ assertion on low level detect bit 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " LOWLEVEL[5] ,Enable the IRQ assertion on low level detect bit 5 " "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LOWLEVEL[4] ,Enable the IRQ assertion on low level detect bit 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LOWLEVEL[3] ,Enable the IRQ assertion on low level detect bit 3 " "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LOWLEVEL[2] ,Enable the IRQ assertion on low level detect bit 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " LOWLEVEL[1] ,Enable the IRQ assertion on low level detect bit 1 " "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LOWLEVEL[0] ,Enable the IRQ assertion on low level detect bit 0 " "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_LEVELDETECT1,High Level Interrupt Enable"
|
|
bitfld.long 0x08 31. " HIGHLEVEL[31] ,Enable the IRQ assertion on high level detect bit 31" "Disabled,Enabled"
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|
bitfld.long 0x08 30. " HIGHLEVEL[30] ,Enable the IRQ assertion on high level detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " HIGHLEVEL[29] ,Enable the IRQ assertion on high level detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " HIGHLEVEL[28] ,Enable the IRQ assertion on high level detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " HIGHLEVEL[27] ,Enable the IRQ assertion on high level detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " HIGHLEVEL[26] ,Enable the IRQ assertion on high level detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " HIGHLEVEL[25] ,Enable the IRQ assertion on high level detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " HIGHLEVEL[24] ,Enable the IRQ assertion on high level detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HIGHLEVEL[23] ,Enable the IRQ assertion on high level detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " HIGHLEVEL[22] ,Enable the IRQ assertion on high level detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HIGHLEVEL[21] ,Enable the IRQ assertion on high level detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " HIGHLEVEL[20] ,Enable the IRQ assertion on high level detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HIGHLEVEL[19] ,Enable the IRQ assertion on high level detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " HIGHLEVEL[18] ,Enable the IRQ assertion on high level detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " HIGHLEVEL[17] ,Enable the IRQ assertion on high level detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " HIGHLEVEL[16] ,Enable the IRQ assertion on high level detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HIGHLEVEL[15] ,Enable the IRQ assertion on high level detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " HIGHLEVEL[14] ,Enable the IRQ assertion on high level detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " HIGHLEVEL[13] ,Enable the IRQ assertion on high level detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " HIGHLEVEL[12] ,Enable the IRQ assertion on high level detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HIGHLEVEL[11] ,Enable the IRQ assertion on high level detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " HIGHLEVEL[10] ,Enable the IRQ assertion on high level detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " HIGHLEVEL[9] ,Enable the IRQ assertion on high level detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " HIGHLEVEL[8] ,Enable the IRQ assertion on high level detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HIGHLEVEL[7] ,Enable the IRQ assertion on high level detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " HIGHLEVEL[6] ,Enable the IRQ assertion on high level detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIGHLEVEL[5] ,Enable the IRQ assertion on high level detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HIGHLEVEL[4] ,Enable the IRQ assertion on high level detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHLEVEL[3] ,Enable the IRQ assertion on high level detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " HIGHLEVEL[2] ,Enable the IRQ assertion on high level detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HIGHLEVEL[1] ,Enable the IRQ assertion on high level detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " HIGHLEVEL[0] ,Enable the IRQ assertion on high level detect bit 0" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_RISINGDETECT,Rising Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x0c 31. " RISINGEDGE[31] ,Enable IRQ/Wakeup on rising edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " RISINGEDGE[30] ,Enable IRQ/Wakeup on rising edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " RISINGEDGE[29] ,Enable IRQ/Wakeup on rising edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " RISINGEDGE[28] ,Enable IRQ/Wakeup on rising edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " RISINGEDGE[27] ,Enable IRQ/Wakeup on rising edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " RISINGEDGE[26] ,Enable IRQ/Wakeup on rising edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " RISINGEDGE[25] ,Enable IRQ/Wakeup on rising edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " RISINGEDGE[24] ,Enable IRQ/Wakeup on rising edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " RISINGEDGE[23] ,Enable IRQ/Wakeup on rising edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " RISINGEDGE[22] ,Enable IRQ/Wakeup on rising edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " RISINGEDGE[21] ,Enable IRQ/Wakeup on rising edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " RISINGEDGE[20] ,Enable IRQ/Wakeup on rising edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " RISINGEDGE[19] ,Enable IRQ/Wakeup on rising edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " RISINGEDGE[18] ,Enable IRQ/Wakeup on rising edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " RISINGEDGE[17] ,Enable IRQ/Wakeup on rising edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " RISINGEDGE[16] ,Enable IRQ/Wakeup on rising edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " RISINGEDGE[15] ,Enable IRQ/Wakeup on rising edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " RISINGEDGE[14] ,Enable IRQ/Wakeup on rising edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " RISINGEDGE[13] ,Enable IRQ/Wakeup on rising edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " RISINGEDGE[12] ,Enable IRQ/Wakeup on rising edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " RISINGEDGE[11] ,Enable IRQ/Wakeup on rising edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " RISINGEDGE[10] ,Enable IRQ/Wakeup on rising edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " RISINGEDGE[9] ,Enable IRQ/Wakeup on rising edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " RISINGEDGE[8] ,Enable IRQ/Wakeup on rising edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " RISINGEDGE[7] ,Enable IRQ/Wakeup on rising edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " RISINGEDGE[6] ,Enable IRQ/Wakeup on rising edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " RISINGEDGE[5] ,Enable IRQ/Wakeup on rising edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " RISINGEDGE[4] ,Enable IRQ/Wakeup on rising edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " RISINGEDGE[3] ,Enable IRQ/Wakeup on rising edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " RISINGEDGE[2] ,Enable IRQ/Wakeup on rising edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " RISINGEDGE[1] ,Enable IRQ/Wakeup on rising edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " RISINGEDGE[0] ,Enable IRQ/Wakeup on rising edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_FALLINGDETECT,Falling Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x10 31. " FALLINGEDGE[31] ,Enable IRQ/Wakeup on falling edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " FALLINGEDGE[30] ,Enable IRQ/Wakeup on falling edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " FALLINGEDGE[29] ,Enable IRQ/Wakeup on falling edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " FALLINGEDGE[28] ,Enable IRQ/Wakeup on falling edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " FALLINGEDGE[27] ,Enable IRQ/Wakeup on falling edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " FALLINGEDGE[26] ,Enable IRQ/Wakeup on falling edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " FALLINGEDGE[25] ,Enable IRQ/Wakeup on falling edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " FALLINGEDGE[24] ,Enable IRQ/Wakeup on falling edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " FALLINGEDGE[23] ,Enable IRQ/Wakeup on falling edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " FALLINGEDGE[22] ,Enable IRQ/Wakeup on falling edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " FALLINGEDGE[21] ,Enable IRQ/Wakeup on falling edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " FALLINGEDGE[20] ,Enable IRQ/Wakeup on falling edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " FALLINGEDGE[19] ,Enable IRQ/Wakeup on falling edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " FALLINGEDGE[18] ,Enable IRQ/Wakeup on falling edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " FALLINGEDGE[17] ,Enable IRQ/Wakeup on falling edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " FALLINGEDGE[16] ,Enable IRQ/Wakeup on falling edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FALLINGEDGE[15] ,Enable IRQ/Wakeup on falling edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " FALLINGEDGE[14] ,Enable IRQ/Wakeup on falling edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " FALLINGEDGE[13] ,Enable IRQ/Wakeup on falling edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " FALLINGEDGE[12] ,Enable IRQ/Wakeup on falling edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " FALLINGEDGE[11] ,Enable IRQ/Wakeup on falling edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " FALLINGEDGE[10] ,Enable IRQ/Wakeup on falling edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " FALLINGEDGE[9] ,Enable IRQ/Wakeup on falling edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " FALLINGEDGE[8] ,Enable IRQ/Wakeup on falling edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " FALLINGEDGE[7] ,Enable IRQ/Wakeup on falling edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " FALLINGEDGE[6] ,Enable IRQ/Wakeup on falling edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " FALLINGEDGE[5] ,Enable IRQ/Wakeup on falling edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " FALLINGEDGE[4] ,Enable IRQ/Wakeup on falling edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " FALLINGEDGE[3] ,Enable IRQ/Wakeup on falling edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " FALLINGEDGE[2] ,Enable IRQ/Wakeup on falling edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " FALLINGEDGE[1] ,Enable IRQ/Wakeup on falling edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " FALLINGEDGE[0] ,Enable IRQ/Wakeup on falling edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable"
|
|
bitfld.long 0x14 31. " DEBOUNCEEN[31] ,Enable debouncing feature bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " DEBOUNCEEN[30] ,Enable debouncing feature bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " DEBOUNCEEN[29] ,Enable debouncing feature bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " DEBOUNCEEN[28] ,Enable debouncing feature bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " DEBOUNCEEN[27] ,Enable debouncing feature bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " DEBOUNCEEN[26] ,Enable debouncing feature bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " DEBOUNCEEN[25] ,Enable debouncing feature bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DEBOUNCEEN[24] ,Enable debouncing feature bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " DEBOUNCEEN[23] ,Enable debouncing feature bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " DEBOUNCEEN[22] ,Enable debouncing feature bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " DEBOUNCEEN[21] ,Enable debouncing feature bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " DEBOUNCEEN[20] ,Enable debouncing feature bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " DEBOUNCEEN[19] ,Enable debouncing feature bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " DEBOUNCEEN[18] ,Enable debouncing feature bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " DEBOUNCEEN[17] ,Enable debouncing feature bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " DEBOUNCEEN[16] ,Enable debouncing feature bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DEBOUNCEEN[15] ,Enable debouncing feature bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DEBOUNCEEN[14] ,Enable debouncing feature bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DEBOUNCEEN[13] ,Enable debouncing feature bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DEBOUNCEEN[12] ,Enable debouncing feature bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DEBOUNCEEN[11] ,Enable debouncing feature bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DEBOUNCEEN[10] ,Enable debouncing feature bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DEBOUNCEEN[9] ,Enable debouncing feature bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DEBOUNCEEN[8] ,Enable debouncing feature bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DEBOUNCEEN[7] ,Enable debouncing feature bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DEBOUNCEEN[6] ,Enable debouncing feature bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DEBOUNCEEN[5] ,Enable debouncing feature bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DEBOUNCEEN[4] ,Enable debouncing feature bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DEBOUNCEEN[3] ,Enable debouncing feature bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DEBOUNCEEN[2] ,Enable debouncing feature bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DEBOUNCEEN[1] ,Enable debouncing feature bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DEBOUNCEEN[0] ,Enable debouncing feature bit 0" "Disabled,Enabled"
|
|
line.long 0x18 "GPIO_DEBOUNCINGTIME,Input Debouncing Value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCEVAL ,Input debouncing value"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO2"
|
|
base ad:0x49050000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO Configuration"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt 1 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS1[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS1[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS1[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS1[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS1[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS1[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS1[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS1[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS1[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS1[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS1[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS1[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS1[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS1[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS1[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS1[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS1[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS1[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS1[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS1[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS1[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS1[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS1[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS1[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS1[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS1[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS1[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS1[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS1[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS1[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS1[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS1[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE1,Interrupt 1 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE1[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE1[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE1[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE1[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE1[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE1[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE1[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE1[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE1[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE1[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE1[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE1[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE1[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE1[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE1[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE1[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE1[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE1[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE1[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE1[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE1[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE1[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE1[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE1[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE1[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE1[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE1[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE1[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE1[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE1[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE1[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE1[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_WAKEUPENABLE,Wake Up Enable Register"
|
|
setclrfld.long 0x08 31. 0x6c 31. 0x68 31. " WAKEUPEN[31]_set/clr ,Wakeup generation bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x6c 30. 0x68 30. " WAKEUPEN[30]_set/clr ,Wakeup generation bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 29. 0x6c 29. 0x68 29. " WAKEUPEN[29]_set/clr ,Wakeup generation bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x6c 28. 0x68 28. " WAKEUPEN[28]_set/clr ,Wakeup generation bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. 0x6c 27. 0x68 27. " WAKEUPEN[27]_set/clr ,Wakeup generation bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x6c 26. 0x68 26. " WAKEUPEN[26]_set/clr ,Wakeup generation bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x6c 25. 0x68 25. " WAKEUPEN[25]_set/clr ,Wakeup generation bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x6c 24. 0x68 24. " WAKEUPEN[24]_set/clr ,Wakeup generation bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. 0x6c 23. 0x68 23. " WAKEUPEN[23]_set/clr ,Wakeup generation bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x6c 22. 0x68 22. " WAKEUPEN[22]_set/clr ,Wakeup generation bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 21. 0x6c 21. 0x68 21. " WAKEUPEN[21]_set/clr ,Wakeup generation bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x6c 20. 0x68 20. " WAKEUPEN[20]_set/clr ,Wakeup generation bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x6c 19. 0x68 19. " WAKEUPEN[19]_set/clr ,Wakeup generation bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x6c 18. 0x68 18. " WAKEUPEN[18]_set/clr ,Wakeup generation bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 17. 0x6c 17. 0x68 17. " WAKEUPEN[17]_set/clr ,Wakeup generation bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x6c 16. 0x68 16. " WAKEUPEN[16]_set/clr ,Wakeup generation bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 15. 0x6c 15. 0x68 15. " WAKEUPEN[15]_set/clr ,Wakeup generation bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x6c 14. 0x68 14. " WAKEUPEN[14]_set/clr ,Wakeup generation bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x6c 13. 0x68 13. " WAKEUPEN[13]_set/clr ,Wakeup generation bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x6c 12. 0x68 12. " WAKEUPEN[12]_set/clr ,Wakeup generation bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. 0x6c 11. 0x68 11. " WAKEUPEN[11]_set/clr ,Wakeup generation bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x6c 10. 0x68 10. " WAKEUPEN[10]_set/clr ,Wakeup generation bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 9. 0x6c 9. 0x68 9. " WAKEUPEN[9]_set/clr ,Wakeup generation bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x6c 8. 0x68 8. " WAKEUPEN[8]_set/clr ,Wakeup generation bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x6c 7. 0x68 7. " WAKEUPEN[7]_set/clr ,Wakeup generation bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x6c 6. 0x68 6. " WAKEUPEN[6]_set/clr ,Wakeup generation bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. 0x6c 5. 0x68 5. " WAKEUPEN[5]_set/clr ,Wakeup generation bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x6c 4. 0x68 4. " WAKEUPEN[4]_set/clr ,Wakeup generation bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 3. 0x6c 3. 0x68 3. " WAKEUPEN[3]_set/clr ,Wakeup generation bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x6c 2. 0x68 2. " WAKEUPEN[2]_set/clr ,Wakeup generation bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x6c 1. 0x68 1. " WAKEUPEN[1]_set/clr ,Wakeup generation bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x6c 0. 0x68 0. " WAKEUPEN[0]_set/clr ,Wakeup generation bit 0 enable" "Disabled,Enabled"
|
|
group.long 0x28++0xf
|
|
line.long 0x00 "GPIO_IRQSTATUS2,Interrupt 2 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS2[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS2[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS2[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS2[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS2[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS2[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS2[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS2[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS2[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS2[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS2[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS2[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS2[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS2[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS2[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS2[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS2[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS2[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS2[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS2[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS2[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS2[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS2[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS2[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS2[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS2[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS2[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS2[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS2[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS2[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS2[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS2[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE2,Interrupt 2 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE2[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE2[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE2[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE2[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE2[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE2[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE2[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE2[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE2[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE2[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE2[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE2[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE2[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE2[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE2[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE2[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE2[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE2[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE2[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE2[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE2[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE2[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE2[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE2[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE2[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE2[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE2[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE2[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE2[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE2[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE2[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE2[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_CTRL,GPIO Control"
|
|
bitfld.long 0x08 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x08 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x0c "GPIO_OE,Output Data Enable"
|
|
bitfld.long 0x0c 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x0c 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x0c 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x0c 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x0c 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x0c 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x0c 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x0c 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x0c 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x0c 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x0c 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x0c 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
|
|
bitfld.long 0x0c 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
|
bitfld.long 0x0c 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
|
|
bitfld.long 0x0c 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
|
bitfld.long 0x0c 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
|
|
bitfld.long 0x0c 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x00 "GPIO_DATAIN,Sampled Input Data"
|
|
group.long 0x3c++0x1b
|
|
line.long 0x00 "GPIO_DATAOUT,Output Data"
|
|
setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
|
|
setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
|
|
setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
|
|
setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
|
|
setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
|
|
setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
|
|
setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
|
|
setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
|
|
setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
|
|
setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
|
|
setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
|
|
setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
|
setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
|
setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
|
setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
|
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
|
|
setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
|
|
line.long 0x04 "GPIO_LEVELDETECT0,Low Level Interrupt Enable"
|
|
bitfld.long 0x04 31. " LOWLEVEL[31] ,Enable the IRQ assertion on low level detect bit 31 " "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " LOWLEVEL[30] ,Enable the IRQ assertion on low level detect bit 30 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " LOWLEVEL[29] ,Enable the IRQ assertion on low level detect bit 29 " "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " LOWLEVEL[28] ,Enable the IRQ assertion on low level detect bit 28 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " LOWLEVEL[27] ,Enable the IRQ assertion on low level detect bit 27 " "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " LOWLEVEL[26] ,Enable the IRQ assertion on low level detect bit 26 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " LOWLEVEL[25] ,Enable the IRQ assertion on low level detect bit 25 " "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " LOWLEVEL[24] ,Enable the IRQ assertion on low level detect bit 24 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " LOWLEVEL[23] ,Enable the IRQ assertion on low level detect bit 23 " "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LOWLEVEL[22] ,Enable the IRQ assertion on low level detect bit 22 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " LOWLEVEL[21] ,Enable the IRQ assertion on low level detect bit 21 " "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LOWLEVEL[20] ,Enable the IRQ assertion on low level detect bit 20 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LOWLEVEL[19] ,Enable the IRQ assertion on low level detect bit 19 " "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LOWLEVEL[18] ,Enable the IRQ assertion on low level detect bit 18 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LOWLEVEL[17] ,Enable the IRQ assertion on low level detect bit 17 " "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " LOWLEVEL[16] ,Enable the IRQ assertion on low level detect bit 16 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LOWLEVEL[15] ,Enable the IRQ assertion on low level detect bit 15 " "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LOWLEVEL[14] ,Enable the IRQ assertion on low level detect bit 14 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " LOWLEVEL[13] ,Enable the IRQ assertion on low level detect bit 13 " "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LOWLEVEL[12] ,Enable the IRQ assertion on low level detect bit 12 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LOWLEVEL[11] ,Enable the IRQ assertion on low level detect bit 11 " "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LOWLEVEL[10] ,Enable the IRQ assertion on low level detect bit 10 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LOWLEVEL[9] ,Enable the IRQ assertion on low level detect bit 9 " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LOWLEVEL[8] ,Enable the IRQ assertion on low level detect bit 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LOWLEVEL[7] ,Enable the IRQ assertion on low level detect bit 7 " "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LOWLEVEL[6] ,Enable the IRQ assertion on low level detect bit 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " LOWLEVEL[5] ,Enable the IRQ assertion on low level detect bit 5 " "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LOWLEVEL[4] ,Enable the IRQ assertion on low level detect bit 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LOWLEVEL[3] ,Enable the IRQ assertion on low level detect bit 3 " "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LOWLEVEL[2] ,Enable the IRQ assertion on low level detect bit 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " LOWLEVEL[1] ,Enable the IRQ assertion on low level detect bit 1 " "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LOWLEVEL[0] ,Enable the IRQ assertion on low level detect bit 0 " "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_LEVELDETECT1,High Level Interrupt Enable"
|
|
bitfld.long 0x08 31. " HIGHLEVEL[31] ,Enable the IRQ assertion on high level detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " HIGHLEVEL[30] ,Enable the IRQ assertion on high level detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " HIGHLEVEL[29] ,Enable the IRQ assertion on high level detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " HIGHLEVEL[28] ,Enable the IRQ assertion on high level detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " HIGHLEVEL[27] ,Enable the IRQ assertion on high level detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " HIGHLEVEL[26] ,Enable the IRQ assertion on high level detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " HIGHLEVEL[25] ,Enable the IRQ assertion on high level detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " HIGHLEVEL[24] ,Enable the IRQ assertion on high level detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HIGHLEVEL[23] ,Enable the IRQ assertion on high level detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " HIGHLEVEL[22] ,Enable the IRQ assertion on high level detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HIGHLEVEL[21] ,Enable the IRQ assertion on high level detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " HIGHLEVEL[20] ,Enable the IRQ assertion on high level detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HIGHLEVEL[19] ,Enable the IRQ assertion on high level detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " HIGHLEVEL[18] ,Enable the IRQ assertion on high level detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " HIGHLEVEL[17] ,Enable the IRQ assertion on high level detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " HIGHLEVEL[16] ,Enable the IRQ assertion on high level detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HIGHLEVEL[15] ,Enable the IRQ assertion on high level detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " HIGHLEVEL[14] ,Enable the IRQ assertion on high level detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " HIGHLEVEL[13] ,Enable the IRQ assertion on high level detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " HIGHLEVEL[12] ,Enable the IRQ assertion on high level detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HIGHLEVEL[11] ,Enable the IRQ assertion on high level detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " HIGHLEVEL[10] ,Enable the IRQ assertion on high level detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " HIGHLEVEL[9] ,Enable the IRQ assertion on high level detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " HIGHLEVEL[8] ,Enable the IRQ assertion on high level detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HIGHLEVEL[7] ,Enable the IRQ assertion on high level detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " HIGHLEVEL[6] ,Enable the IRQ assertion on high level detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIGHLEVEL[5] ,Enable the IRQ assertion on high level detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HIGHLEVEL[4] ,Enable the IRQ assertion on high level detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHLEVEL[3] ,Enable the IRQ assertion on high level detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " HIGHLEVEL[2] ,Enable the IRQ assertion on high level detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HIGHLEVEL[1] ,Enable the IRQ assertion on high level detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " HIGHLEVEL[0] ,Enable the IRQ assertion on high level detect bit 0" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_RISINGDETECT,Rising Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x0c 31. " RISINGEDGE[31] ,Enable IRQ/Wakeup on rising edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " RISINGEDGE[30] ,Enable IRQ/Wakeup on rising edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " RISINGEDGE[29] ,Enable IRQ/Wakeup on rising edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " RISINGEDGE[28] ,Enable IRQ/Wakeup on rising edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " RISINGEDGE[27] ,Enable IRQ/Wakeup on rising edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " RISINGEDGE[26] ,Enable IRQ/Wakeup on rising edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " RISINGEDGE[25] ,Enable IRQ/Wakeup on rising edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " RISINGEDGE[24] ,Enable IRQ/Wakeup on rising edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " RISINGEDGE[23] ,Enable IRQ/Wakeup on rising edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " RISINGEDGE[22] ,Enable IRQ/Wakeup on rising edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " RISINGEDGE[21] ,Enable IRQ/Wakeup on rising edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " RISINGEDGE[20] ,Enable IRQ/Wakeup on rising edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " RISINGEDGE[19] ,Enable IRQ/Wakeup on rising edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " RISINGEDGE[18] ,Enable IRQ/Wakeup on rising edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " RISINGEDGE[17] ,Enable IRQ/Wakeup on rising edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " RISINGEDGE[16] ,Enable IRQ/Wakeup on rising edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " RISINGEDGE[15] ,Enable IRQ/Wakeup on rising edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " RISINGEDGE[14] ,Enable IRQ/Wakeup on rising edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " RISINGEDGE[13] ,Enable IRQ/Wakeup on rising edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " RISINGEDGE[12] ,Enable IRQ/Wakeup on rising edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " RISINGEDGE[11] ,Enable IRQ/Wakeup on rising edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " RISINGEDGE[10] ,Enable IRQ/Wakeup on rising edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " RISINGEDGE[9] ,Enable IRQ/Wakeup on rising edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " RISINGEDGE[8] ,Enable IRQ/Wakeup on rising edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " RISINGEDGE[7] ,Enable IRQ/Wakeup on rising edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " RISINGEDGE[6] ,Enable IRQ/Wakeup on rising edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " RISINGEDGE[5] ,Enable IRQ/Wakeup on rising edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " RISINGEDGE[4] ,Enable IRQ/Wakeup on rising edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " RISINGEDGE[3] ,Enable IRQ/Wakeup on rising edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " RISINGEDGE[2] ,Enable IRQ/Wakeup on rising edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " RISINGEDGE[1] ,Enable IRQ/Wakeup on rising edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " RISINGEDGE[0] ,Enable IRQ/Wakeup on rising edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_FALLINGDETECT,Falling Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x10 31. " FALLINGEDGE[31] ,Enable IRQ/Wakeup on falling edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " FALLINGEDGE[30] ,Enable IRQ/Wakeup on falling edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " FALLINGEDGE[29] ,Enable IRQ/Wakeup on falling edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " FALLINGEDGE[28] ,Enable IRQ/Wakeup on falling edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " FALLINGEDGE[27] ,Enable IRQ/Wakeup on falling edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " FALLINGEDGE[26] ,Enable IRQ/Wakeup on falling edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " FALLINGEDGE[25] ,Enable IRQ/Wakeup on falling edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " FALLINGEDGE[24] ,Enable IRQ/Wakeup on falling edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " FALLINGEDGE[23] ,Enable IRQ/Wakeup on falling edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " FALLINGEDGE[22] ,Enable IRQ/Wakeup on falling edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " FALLINGEDGE[21] ,Enable IRQ/Wakeup on falling edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " FALLINGEDGE[20] ,Enable IRQ/Wakeup on falling edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " FALLINGEDGE[19] ,Enable IRQ/Wakeup on falling edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " FALLINGEDGE[18] ,Enable IRQ/Wakeup on falling edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " FALLINGEDGE[17] ,Enable IRQ/Wakeup on falling edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " FALLINGEDGE[16] ,Enable IRQ/Wakeup on falling edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FALLINGEDGE[15] ,Enable IRQ/Wakeup on falling edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " FALLINGEDGE[14] ,Enable IRQ/Wakeup on falling edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " FALLINGEDGE[13] ,Enable IRQ/Wakeup on falling edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " FALLINGEDGE[12] ,Enable IRQ/Wakeup on falling edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " FALLINGEDGE[11] ,Enable IRQ/Wakeup on falling edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " FALLINGEDGE[10] ,Enable IRQ/Wakeup on falling edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " FALLINGEDGE[9] ,Enable IRQ/Wakeup on falling edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " FALLINGEDGE[8] ,Enable IRQ/Wakeup on falling edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " FALLINGEDGE[7] ,Enable IRQ/Wakeup on falling edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " FALLINGEDGE[6] ,Enable IRQ/Wakeup on falling edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " FALLINGEDGE[5] ,Enable IRQ/Wakeup on falling edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " FALLINGEDGE[4] ,Enable IRQ/Wakeup on falling edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " FALLINGEDGE[3] ,Enable IRQ/Wakeup on falling edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " FALLINGEDGE[2] ,Enable IRQ/Wakeup on falling edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " FALLINGEDGE[1] ,Enable IRQ/Wakeup on falling edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " FALLINGEDGE[0] ,Enable IRQ/Wakeup on falling edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable"
|
|
bitfld.long 0x14 31. " DEBOUNCEEN[31] ,Enable debouncing feature bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " DEBOUNCEEN[30] ,Enable debouncing feature bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " DEBOUNCEEN[29] ,Enable debouncing feature bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " DEBOUNCEEN[28] ,Enable debouncing feature bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " DEBOUNCEEN[27] ,Enable debouncing feature bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " DEBOUNCEEN[26] ,Enable debouncing feature bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " DEBOUNCEEN[25] ,Enable debouncing feature bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DEBOUNCEEN[24] ,Enable debouncing feature bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " DEBOUNCEEN[23] ,Enable debouncing feature bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " DEBOUNCEEN[22] ,Enable debouncing feature bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " DEBOUNCEEN[21] ,Enable debouncing feature bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " DEBOUNCEEN[20] ,Enable debouncing feature bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " DEBOUNCEEN[19] ,Enable debouncing feature bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " DEBOUNCEEN[18] ,Enable debouncing feature bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " DEBOUNCEEN[17] ,Enable debouncing feature bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " DEBOUNCEEN[16] ,Enable debouncing feature bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DEBOUNCEEN[15] ,Enable debouncing feature bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DEBOUNCEEN[14] ,Enable debouncing feature bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DEBOUNCEEN[13] ,Enable debouncing feature bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DEBOUNCEEN[12] ,Enable debouncing feature bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DEBOUNCEEN[11] ,Enable debouncing feature bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DEBOUNCEEN[10] ,Enable debouncing feature bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DEBOUNCEEN[9] ,Enable debouncing feature bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DEBOUNCEEN[8] ,Enable debouncing feature bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DEBOUNCEEN[7] ,Enable debouncing feature bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DEBOUNCEEN[6] ,Enable debouncing feature bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DEBOUNCEEN[5] ,Enable debouncing feature bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DEBOUNCEEN[4] ,Enable debouncing feature bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DEBOUNCEEN[3] ,Enable debouncing feature bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DEBOUNCEEN[2] ,Enable debouncing feature bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DEBOUNCEEN[1] ,Enable debouncing feature bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DEBOUNCEEN[0] ,Enable debouncing feature bit 0" "Disabled,Enabled"
|
|
line.long 0x18 "GPIO_DEBOUNCINGTIME,Input Debouncing Value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCEVAL ,Input debouncing value"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO3"
|
|
base ad:0x49052000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO Configuration"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt 1 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS1[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS1[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS1[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS1[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS1[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS1[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS1[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS1[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS1[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS1[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS1[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS1[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS1[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS1[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS1[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS1[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS1[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS1[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS1[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS1[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS1[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS1[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS1[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS1[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS1[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS1[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS1[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS1[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS1[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS1[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS1[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS1[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE1,Interrupt 1 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE1[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE1[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE1[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE1[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE1[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE1[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE1[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE1[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE1[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE1[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE1[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE1[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE1[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE1[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE1[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE1[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE1[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE1[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE1[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE1[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE1[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE1[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE1[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE1[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE1[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE1[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE1[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE1[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE1[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE1[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE1[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE1[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_WAKEUPENABLE,Wake Up Enable Register"
|
|
setclrfld.long 0x08 31. 0x6c 31. 0x68 31. " WAKEUPEN[31]_set/clr ,Wakeup generation bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x6c 30. 0x68 30. " WAKEUPEN[30]_set/clr ,Wakeup generation bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 29. 0x6c 29. 0x68 29. " WAKEUPEN[29]_set/clr ,Wakeup generation bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x6c 28. 0x68 28. " WAKEUPEN[28]_set/clr ,Wakeup generation bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. 0x6c 27. 0x68 27. " WAKEUPEN[27]_set/clr ,Wakeup generation bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x6c 26. 0x68 26. " WAKEUPEN[26]_set/clr ,Wakeup generation bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x6c 25. 0x68 25. " WAKEUPEN[25]_set/clr ,Wakeup generation bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x6c 24. 0x68 24. " WAKEUPEN[24]_set/clr ,Wakeup generation bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. 0x6c 23. 0x68 23. " WAKEUPEN[23]_set/clr ,Wakeup generation bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x6c 22. 0x68 22. " WAKEUPEN[22]_set/clr ,Wakeup generation bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 21. 0x6c 21. 0x68 21. " WAKEUPEN[21]_set/clr ,Wakeup generation bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x6c 20. 0x68 20. " WAKEUPEN[20]_set/clr ,Wakeup generation bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x6c 19. 0x68 19. " WAKEUPEN[19]_set/clr ,Wakeup generation bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x6c 18. 0x68 18. " WAKEUPEN[18]_set/clr ,Wakeup generation bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 17. 0x6c 17. 0x68 17. " WAKEUPEN[17]_set/clr ,Wakeup generation bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x6c 16. 0x68 16. " WAKEUPEN[16]_set/clr ,Wakeup generation bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 15. 0x6c 15. 0x68 15. " WAKEUPEN[15]_set/clr ,Wakeup generation bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x6c 14. 0x68 14. " WAKEUPEN[14]_set/clr ,Wakeup generation bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x6c 13. 0x68 13. " WAKEUPEN[13]_set/clr ,Wakeup generation bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x6c 12. 0x68 12. " WAKEUPEN[12]_set/clr ,Wakeup generation bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. 0x6c 11. 0x68 11. " WAKEUPEN[11]_set/clr ,Wakeup generation bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x6c 10. 0x68 10. " WAKEUPEN[10]_set/clr ,Wakeup generation bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 9. 0x6c 9. 0x68 9. " WAKEUPEN[9]_set/clr ,Wakeup generation bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x6c 8. 0x68 8. " WAKEUPEN[8]_set/clr ,Wakeup generation bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x6c 7. 0x68 7. " WAKEUPEN[7]_set/clr ,Wakeup generation bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x6c 6. 0x68 6. " WAKEUPEN[6]_set/clr ,Wakeup generation bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. 0x6c 5. 0x68 5. " WAKEUPEN[5]_set/clr ,Wakeup generation bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x6c 4. 0x68 4. " WAKEUPEN[4]_set/clr ,Wakeup generation bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 3. 0x6c 3. 0x68 3. " WAKEUPEN[3]_set/clr ,Wakeup generation bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x6c 2. 0x68 2. " WAKEUPEN[2]_set/clr ,Wakeup generation bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x6c 1. 0x68 1. " WAKEUPEN[1]_set/clr ,Wakeup generation bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x6c 0. 0x68 0. " WAKEUPEN[0]_set/clr ,Wakeup generation bit 0 enable" "Disabled,Enabled"
|
|
group.long 0x28++0xf
|
|
line.long 0x00 "GPIO_IRQSTATUS2,Interrupt 2 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS2[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS2[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS2[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS2[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS2[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS2[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS2[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS2[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS2[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS2[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS2[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS2[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS2[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS2[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS2[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS2[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS2[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS2[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS2[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS2[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS2[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS2[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS2[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS2[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS2[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS2[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS2[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS2[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS2[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS2[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS2[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS2[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE2,Interrupt 2 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE2[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE2[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE2[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE2[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE2[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE2[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE2[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE2[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE2[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE2[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE2[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE2[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE2[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE2[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE2[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE2[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE2[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE2[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE2[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE2[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE2[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE2[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE2[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE2[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE2[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE2[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE2[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE2[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE2[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE2[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE2[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE2[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_CTRL,GPIO Control"
|
|
bitfld.long 0x08 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x08 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x0c "GPIO_OE,Output Data Enable"
|
|
bitfld.long 0x0c 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x0c 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x0c 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x0c 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x0c 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x0c 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x0c 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x0c 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x0c 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x0c 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x0c 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x0c 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
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bitfld.long 0x0c 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
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bitfld.long 0x0c 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
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bitfld.long 0x0c 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
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bitfld.long 0x0c 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
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bitfld.long 0x0c 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
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rgroup.long 0x38++0x3
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line.long 0x00 "GPIO_DATAIN,Sampled Input Data"
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group.long 0x3c++0x1b
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line.long 0x00 "GPIO_DATAOUT,Output Data"
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setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
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setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
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textline " "
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setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
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setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
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textline " "
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setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
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setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
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textline " "
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setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
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setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
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textline " "
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setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
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setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
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textline " "
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setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
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setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
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textline " "
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setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
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setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
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textline " "
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setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
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setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
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textline " "
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setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
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setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
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textline " "
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setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
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setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
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textline " "
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setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
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setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
|
textline " "
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setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
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setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
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textline " "
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setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
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setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
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textline " "
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setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
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setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
|
textline " "
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setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
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setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
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|
textline " "
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setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
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setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
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line.long 0x04 "GPIO_LEVELDETECT0,Low Level Interrupt Enable"
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bitfld.long 0x04 31. " LOWLEVEL[31] ,Enable the IRQ assertion on low level detect bit 31 " "Disabled,Enabled"
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bitfld.long 0x04 30. " LOWLEVEL[30] ,Enable the IRQ assertion on low level detect bit 30 " "Disabled,Enabled"
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textline " "
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bitfld.long 0x04 29. " LOWLEVEL[29] ,Enable the IRQ assertion on low level detect bit 29 " "Disabled,Enabled"
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bitfld.long 0x04 28. " LOWLEVEL[28] ,Enable the IRQ assertion on low level detect bit 28 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 27. " LOWLEVEL[27] ,Enable the IRQ assertion on low level detect bit 27 " "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " LOWLEVEL[26] ,Enable the IRQ assertion on low level detect bit 26 " "Disabled,Enabled"
|
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textline " "
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bitfld.long 0x04 25. " LOWLEVEL[25] ,Enable the IRQ assertion on low level detect bit 25 " "Disabled,Enabled"
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bitfld.long 0x04 24. " LOWLEVEL[24] ,Enable the IRQ assertion on low level detect bit 24 " "Disabled,Enabled"
|
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textline " "
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bitfld.long 0x04 23. " LOWLEVEL[23] ,Enable the IRQ assertion on low level detect bit 23 " "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LOWLEVEL[22] ,Enable the IRQ assertion on low level detect bit 22 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 21. " LOWLEVEL[21] ,Enable the IRQ assertion on low level detect bit 21 " "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LOWLEVEL[20] ,Enable the IRQ assertion on low level detect bit 20 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 19. " LOWLEVEL[19] ,Enable the IRQ assertion on low level detect bit 19 " "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LOWLEVEL[18] ,Enable the IRQ assertion on low level detect bit 18 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LOWLEVEL[17] ,Enable the IRQ assertion on low level detect bit 17 " "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " LOWLEVEL[16] ,Enable the IRQ assertion on low level detect bit 16 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 15. " LOWLEVEL[15] ,Enable the IRQ assertion on low level detect bit 15 " "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LOWLEVEL[14] ,Enable the IRQ assertion on low level detect bit 14 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " LOWLEVEL[13] ,Enable the IRQ assertion on low level detect bit 13 " "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LOWLEVEL[12] ,Enable the IRQ assertion on low level detect bit 12 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LOWLEVEL[11] ,Enable the IRQ assertion on low level detect bit 11 " "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LOWLEVEL[10] ,Enable the IRQ assertion on low level detect bit 10 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 9. " LOWLEVEL[9] ,Enable the IRQ assertion on low level detect bit 9 " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LOWLEVEL[8] ,Enable the IRQ assertion on low level detect bit 8 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 7. " LOWLEVEL[7] ,Enable the IRQ assertion on low level detect bit 7 " "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LOWLEVEL[6] ,Enable the IRQ assertion on low level detect bit 6 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 5. " LOWLEVEL[5] ,Enable the IRQ assertion on low level detect bit 5 " "Disabled,Enabled"
|
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bitfld.long 0x04 4. " LOWLEVEL[4] ,Enable the IRQ assertion on low level detect bit 4 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 3. " LOWLEVEL[3] ,Enable the IRQ assertion on low level detect bit 3 " "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LOWLEVEL[2] ,Enable the IRQ assertion on low level detect bit 2 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 1. " LOWLEVEL[1] ,Enable the IRQ assertion on low level detect bit 1 " "Disabled,Enabled"
|
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bitfld.long 0x04 0. " LOWLEVEL[0] ,Enable the IRQ assertion on low level detect bit 0 " "Disabled,Enabled"
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line.long 0x08 "GPIO_LEVELDETECT1,High Level Interrupt Enable"
|
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bitfld.long 0x08 31. " HIGHLEVEL[31] ,Enable the IRQ assertion on high level detect bit 31" "Disabled,Enabled"
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bitfld.long 0x08 30. " HIGHLEVEL[30] ,Enable the IRQ assertion on high level detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 29. " HIGHLEVEL[29] ,Enable the IRQ assertion on high level detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " HIGHLEVEL[28] ,Enable the IRQ assertion on high level detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 27. " HIGHLEVEL[27] ,Enable the IRQ assertion on high level detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " HIGHLEVEL[26] ,Enable the IRQ assertion on high level detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 25. " HIGHLEVEL[25] ,Enable the IRQ assertion on high level detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " HIGHLEVEL[24] ,Enable the IRQ assertion on high level detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 23. " HIGHLEVEL[23] ,Enable the IRQ assertion on high level detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " HIGHLEVEL[22] ,Enable the IRQ assertion on high level detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HIGHLEVEL[21] ,Enable the IRQ assertion on high level detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " HIGHLEVEL[20] ,Enable the IRQ assertion on high level detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HIGHLEVEL[19] ,Enable the IRQ assertion on high level detect bit 19" "Disabled,Enabled"
|
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bitfld.long 0x08 18. " HIGHLEVEL[18] ,Enable the IRQ assertion on high level detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 17. " HIGHLEVEL[17] ,Enable the IRQ assertion on high level detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " HIGHLEVEL[16] ,Enable the IRQ assertion on high level detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HIGHLEVEL[15] ,Enable the IRQ assertion on high level detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " HIGHLEVEL[14] ,Enable the IRQ assertion on high level detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " HIGHLEVEL[13] ,Enable the IRQ assertion on high level detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " HIGHLEVEL[12] ,Enable the IRQ assertion on high level detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HIGHLEVEL[11] ,Enable the IRQ assertion on high level detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " HIGHLEVEL[10] ,Enable the IRQ assertion on high level detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " HIGHLEVEL[9] ,Enable the IRQ assertion on high level detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " HIGHLEVEL[8] ,Enable the IRQ assertion on high level detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HIGHLEVEL[7] ,Enable the IRQ assertion on high level detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " HIGHLEVEL[6] ,Enable the IRQ assertion on high level detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIGHLEVEL[5] ,Enable the IRQ assertion on high level detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HIGHLEVEL[4] ,Enable the IRQ assertion on high level detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHLEVEL[3] ,Enable the IRQ assertion on high level detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " HIGHLEVEL[2] ,Enable the IRQ assertion on high level detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HIGHLEVEL[1] ,Enable the IRQ assertion on high level detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " HIGHLEVEL[0] ,Enable the IRQ assertion on high level detect bit 0" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_RISINGDETECT,Rising Edge Interrupt/Wakeup Enable"
|
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bitfld.long 0x0c 31. " RISINGEDGE[31] ,Enable IRQ/Wakeup on rising edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " RISINGEDGE[30] ,Enable IRQ/Wakeup on rising edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x0c 29. " RISINGEDGE[29] ,Enable IRQ/Wakeup on rising edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " RISINGEDGE[28] ,Enable IRQ/Wakeup on rising edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " RISINGEDGE[27] ,Enable IRQ/Wakeup on rising edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " RISINGEDGE[26] ,Enable IRQ/Wakeup on rising edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " RISINGEDGE[25] ,Enable IRQ/Wakeup on rising edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " RISINGEDGE[24] ,Enable IRQ/Wakeup on rising edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " RISINGEDGE[23] ,Enable IRQ/Wakeup on rising edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " RISINGEDGE[22] ,Enable IRQ/Wakeup on rising edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " RISINGEDGE[21] ,Enable IRQ/Wakeup on rising edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " RISINGEDGE[20] ,Enable IRQ/Wakeup on rising edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " RISINGEDGE[19] ,Enable IRQ/Wakeup on rising edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " RISINGEDGE[18] ,Enable IRQ/Wakeup on rising edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " RISINGEDGE[17] ,Enable IRQ/Wakeup on rising edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " RISINGEDGE[16] ,Enable IRQ/Wakeup on rising edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " RISINGEDGE[15] ,Enable IRQ/Wakeup on rising edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " RISINGEDGE[14] ,Enable IRQ/Wakeup on rising edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " RISINGEDGE[13] ,Enable IRQ/Wakeup on rising edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " RISINGEDGE[12] ,Enable IRQ/Wakeup on rising edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " RISINGEDGE[11] ,Enable IRQ/Wakeup on rising edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " RISINGEDGE[10] ,Enable IRQ/Wakeup on rising edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " RISINGEDGE[9] ,Enable IRQ/Wakeup on rising edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " RISINGEDGE[8] ,Enable IRQ/Wakeup on rising edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " RISINGEDGE[7] ,Enable IRQ/Wakeup on rising edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " RISINGEDGE[6] ,Enable IRQ/Wakeup on rising edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " RISINGEDGE[5] ,Enable IRQ/Wakeup on rising edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " RISINGEDGE[4] ,Enable IRQ/Wakeup on rising edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " RISINGEDGE[3] ,Enable IRQ/Wakeup on rising edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " RISINGEDGE[2] ,Enable IRQ/Wakeup on rising edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " RISINGEDGE[1] ,Enable IRQ/Wakeup on rising edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " RISINGEDGE[0] ,Enable IRQ/Wakeup on rising edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_FALLINGDETECT,Falling Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x10 31. " FALLINGEDGE[31] ,Enable IRQ/Wakeup on falling edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " FALLINGEDGE[30] ,Enable IRQ/Wakeup on falling edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " FALLINGEDGE[29] ,Enable IRQ/Wakeup on falling edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " FALLINGEDGE[28] ,Enable IRQ/Wakeup on falling edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " FALLINGEDGE[27] ,Enable IRQ/Wakeup on falling edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " FALLINGEDGE[26] ,Enable IRQ/Wakeup on falling edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " FALLINGEDGE[25] ,Enable IRQ/Wakeup on falling edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " FALLINGEDGE[24] ,Enable IRQ/Wakeup on falling edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " FALLINGEDGE[23] ,Enable IRQ/Wakeup on falling edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " FALLINGEDGE[22] ,Enable IRQ/Wakeup on falling edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " FALLINGEDGE[21] ,Enable IRQ/Wakeup on falling edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " FALLINGEDGE[20] ,Enable IRQ/Wakeup on falling edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " FALLINGEDGE[19] ,Enable IRQ/Wakeup on falling edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " FALLINGEDGE[18] ,Enable IRQ/Wakeup on falling edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " FALLINGEDGE[17] ,Enable IRQ/Wakeup on falling edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " FALLINGEDGE[16] ,Enable IRQ/Wakeup on falling edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FALLINGEDGE[15] ,Enable IRQ/Wakeup on falling edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " FALLINGEDGE[14] ,Enable IRQ/Wakeup on falling edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " FALLINGEDGE[13] ,Enable IRQ/Wakeup on falling edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " FALLINGEDGE[12] ,Enable IRQ/Wakeup on falling edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " FALLINGEDGE[11] ,Enable IRQ/Wakeup on falling edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " FALLINGEDGE[10] ,Enable IRQ/Wakeup on falling edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " FALLINGEDGE[9] ,Enable IRQ/Wakeup on falling edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " FALLINGEDGE[8] ,Enable IRQ/Wakeup on falling edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " FALLINGEDGE[7] ,Enable IRQ/Wakeup on falling edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " FALLINGEDGE[6] ,Enable IRQ/Wakeup on falling edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " FALLINGEDGE[5] ,Enable IRQ/Wakeup on falling edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " FALLINGEDGE[4] ,Enable IRQ/Wakeup on falling edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " FALLINGEDGE[3] ,Enable IRQ/Wakeup on falling edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " FALLINGEDGE[2] ,Enable IRQ/Wakeup on falling edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " FALLINGEDGE[1] ,Enable IRQ/Wakeup on falling edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " FALLINGEDGE[0] ,Enable IRQ/Wakeup on falling edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable"
|
|
bitfld.long 0x14 31. " DEBOUNCEEN[31] ,Enable debouncing feature bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " DEBOUNCEEN[30] ,Enable debouncing feature bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " DEBOUNCEEN[29] ,Enable debouncing feature bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " DEBOUNCEEN[28] ,Enable debouncing feature bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " DEBOUNCEEN[27] ,Enable debouncing feature bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " DEBOUNCEEN[26] ,Enable debouncing feature bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " DEBOUNCEEN[25] ,Enable debouncing feature bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DEBOUNCEEN[24] ,Enable debouncing feature bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " DEBOUNCEEN[23] ,Enable debouncing feature bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " DEBOUNCEEN[22] ,Enable debouncing feature bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " DEBOUNCEEN[21] ,Enable debouncing feature bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " DEBOUNCEEN[20] ,Enable debouncing feature bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " DEBOUNCEEN[19] ,Enable debouncing feature bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " DEBOUNCEEN[18] ,Enable debouncing feature bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " DEBOUNCEEN[17] ,Enable debouncing feature bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " DEBOUNCEEN[16] ,Enable debouncing feature bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DEBOUNCEEN[15] ,Enable debouncing feature bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DEBOUNCEEN[14] ,Enable debouncing feature bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DEBOUNCEEN[13] ,Enable debouncing feature bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DEBOUNCEEN[12] ,Enable debouncing feature bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DEBOUNCEEN[11] ,Enable debouncing feature bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DEBOUNCEEN[10] ,Enable debouncing feature bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DEBOUNCEEN[9] ,Enable debouncing feature bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DEBOUNCEEN[8] ,Enable debouncing feature bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DEBOUNCEEN[7] ,Enable debouncing feature bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DEBOUNCEEN[6] ,Enable debouncing feature bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DEBOUNCEEN[5] ,Enable debouncing feature bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DEBOUNCEEN[4] ,Enable debouncing feature bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DEBOUNCEEN[3] ,Enable debouncing feature bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DEBOUNCEEN[2] ,Enable debouncing feature bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DEBOUNCEEN[1] ,Enable debouncing feature bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DEBOUNCEEN[0] ,Enable debouncing feature bit 0" "Disabled,Enabled"
|
|
line.long 0x18 "GPIO_DEBOUNCINGTIME,Input Debouncing Value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCEVAL ,Input debouncing value"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO4"
|
|
base ad:0x49054000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO Configuration"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt 1 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS1[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS1[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS1[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS1[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS1[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS1[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS1[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS1[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS1[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS1[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS1[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS1[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS1[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS1[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS1[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS1[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS1[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS1[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS1[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS1[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS1[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS1[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS1[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS1[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS1[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS1[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS1[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS1[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS1[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS1[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS1[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS1[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE1,Interrupt 1 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE1[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE1[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE1[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE1[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE1[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE1[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE1[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE1[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE1[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE1[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE1[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE1[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE1[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE1[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE1[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE1[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE1[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE1[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE1[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE1[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE1[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE1[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE1[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE1[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE1[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE1[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE1[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE1[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE1[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE1[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE1[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE1[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_WAKEUPENABLE,Wake Up Enable Register"
|
|
setclrfld.long 0x08 31. 0x6c 31. 0x68 31. " WAKEUPEN[31]_set/clr ,Wakeup generation bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x6c 30. 0x68 30. " WAKEUPEN[30]_set/clr ,Wakeup generation bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 29. 0x6c 29. 0x68 29. " WAKEUPEN[29]_set/clr ,Wakeup generation bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x6c 28. 0x68 28. " WAKEUPEN[28]_set/clr ,Wakeup generation bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. 0x6c 27. 0x68 27. " WAKEUPEN[27]_set/clr ,Wakeup generation bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x6c 26. 0x68 26. " WAKEUPEN[26]_set/clr ,Wakeup generation bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x6c 25. 0x68 25. " WAKEUPEN[25]_set/clr ,Wakeup generation bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x6c 24. 0x68 24. " WAKEUPEN[24]_set/clr ,Wakeup generation bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. 0x6c 23. 0x68 23. " WAKEUPEN[23]_set/clr ,Wakeup generation bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x6c 22. 0x68 22. " WAKEUPEN[22]_set/clr ,Wakeup generation bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 21. 0x6c 21. 0x68 21. " WAKEUPEN[21]_set/clr ,Wakeup generation bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x6c 20. 0x68 20. " WAKEUPEN[20]_set/clr ,Wakeup generation bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x6c 19. 0x68 19. " WAKEUPEN[19]_set/clr ,Wakeup generation bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x6c 18. 0x68 18. " WAKEUPEN[18]_set/clr ,Wakeup generation bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 17. 0x6c 17. 0x68 17. " WAKEUPEN[17]_set/clr ,Wakeup generation bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x6c 16. 0x68 16. " WAKEUPEN[16]_set/clr ,Wakeup generation bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 15. 0x6c 15. 0x68 15. " WAKEUPEN[15]_set/clr ,Wakeup generation bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x6c 14. 0x68 14. " WAKEUPEN[14]_set/clr ,Wakeup generation bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x6c 13. 0x68 13. " WAKEUPEN[13]_set/clr ,Wakeup generation bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x6c 12. 0x68 12. " WAKEUPEN[12]_set/clr ,Wakeup generation bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. 0x6c 11. 0x68 11. " WAKEUPEN[11]_set/clr ,Wakeup generation bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x6c 10. 0x68 10. " WAKEUPEN[10]_set/clr ,Wakeup generation bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 9. 0x6c 9. 0x68 9. " WAKEUPEN[9]_set/clr ,Wakeup generation bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x6c 8. 0x68 8. " WAKEUPEN[8]_set/clr ,Wakeup generation bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x6c 7. 0x68 7. " WAKEUPEN[7]_set/clr ,Wakeup generation bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x6c 6. 0x68 6. " WAKEUPEN[6]_set/clr ,Wakeup generation bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. 0x6c 5. 0x68 5. " WAKEUPEN[5]_set/clr ,Wakeup generation bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x6c 4. 0x68 4. " WAKEUPEN[4]_set/clr ,Wakeup generation bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 3. 0x6c 3. 0x68 3. " WAKEUPEN[3]_set/clr ,Wakeup generation bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x6c 2. 0x68 2. " WAKEUPEN[2]_set/clr ,Wakeup generation bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x6c 1. 0x68 1. " WAKEUPEN[1]_set/clr ,Wakeup generation bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x6c 0. 0x68 0. " WAKEUPEN[0]_set/clr ,Wakeup generation bit 0 enable" "Disabled,Enabled"
|
|
group.long 0x28++0xf
|
|
line.long 0x00 "GPIO_IRQSTATUS2,Interrupt 2 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS2[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS2[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS2[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS2[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS2[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS2[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS2[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS2[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS2[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS2[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS2[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS2[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS2[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS2[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS2[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS2[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS2[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS2[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS2[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS2[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS2[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS2[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS2[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS2[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS2[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS2[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS2[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS2[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS2[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS2[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS2[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS2[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE2,Interrupt 2 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE2[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE2[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE2[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE2[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE2[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE2[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE2[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE2[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE2[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE2[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE2[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE2[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE2[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE2[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE2[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE2[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE2[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE2[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE2[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE2[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE2[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE2[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE2[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE2[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE2[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE2[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE2[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE2[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE2[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE2[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE2[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE2[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_CTRL,GPIO Control"
|
|
bitfld.long 0x08 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x08 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x0c "GPIO_OE,Output Data Enable"
|
|
bitfld.long 0x0c 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x0c 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x0c 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x0c 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x0c 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x0c 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x0c 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x0c 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x0c 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x0c 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x0c 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x0c 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
|
|
bitfld.long 0x0c 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
|
bitfld.long 0x0c 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
|
|
bitfld.long 0x0c 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
|
bitfld.long 0x0c 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
|
|
bitfld.long 0x0c 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x00 "GPIO_DATAIN,Sampled Input Data"
|
|
group.long 0x3c++0x1b
|
|
line.long 0x00 "GPIO_DATAOUT,Output Data"
|
|
setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
|
|
setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
|
|
setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
|
|
setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
|
|
setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
|
|
setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
|
|
setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
|
|
setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
|
|
setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
|
|
setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
|
|
setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
|
|
setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
|
setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
|
setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
|
setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
|
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
|
|
setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
|
|
line.long 0x04 "GPIO_LEVELDETECT0,Low Level Interrupt Enable"
|
|
bitfld.long 0x04 31. " LOWLEVEL[31] ,Enable the IRQ assertion on low level detect bit 31 " "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " LOWLEVEL[30] ,Enable the IRQ assertion on low level detect bit 30 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " LOWLEVEL[29] ,Enable the IRQ assertion on low level detect bit 29 " "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " LOWLEVEL[28] ,Enable the IRQ assertion on low level detect bit 28 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " LOWLEVEL[27] ,Enable the IRQ assertion on low level detect bit 27 " "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " LOWLEVEL[26] ,Enable the IRQ assertion on low level detect bit 26 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " LOWLEVEL[25] ,Enable the IRQ assertion on low level detect bit 25 " "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " LOWLEVEL[24] ,Enable the IRQ assertion on low level detect bit 24 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " LOWLEVEL[23] ,Enable the IRQ assertion on low level detect bit 23 " "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LOWLEVEL[22] ,Enable the IRQ assertion on low level detect bit 22 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " LOWLEVEL[21] ,Enable the IRQ assertion on low level detect bit 21 " "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LOWLEVEL[20] ,Enable the IRQ assertion on low level detect bit 20 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LOWLEVEL[19] ,Enable the IRQ assertion on low level detect bit 19 " "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LOWLEVEL[18] ,Enable the IRQ assertion on low level detect bit 18 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LOWLEVEL[17] ,Enable the IRQ assertion on low level detect bit 17 " "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " LOWLEVEL[16] ,Enable the IRQ assertion on low level detect bit 16 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LOWLEVEL[15] ,Enable the IRQ assertion on low level detect bit 15 " "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LOWLEVEL[14] ,Enable the IRQ assertion on low level detect bit 14 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " LOWLEVEL[13] ,Enable the IRQ assertion on low level detect bit 13 " "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LOWLEVEL[12] ,Enable the IRQ assertion on low level detect bit 12 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LOWLEVEL[11] ,Enable the IRQ assertion on low level detect bit 11 " "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LOWLEVEL[10] ,Enable the IRQ assertion on low level detect bit 10 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LOWLEVEL[9] ,Enable the IRQ assertion on low level detect bit 9 " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LOWLEVEL[8] ,Enable the IRQ assertion on low level detect bit 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LOWLEVEL[7] ,Enable the IRQ assertion on low level detect bit 7 " "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LOWLEVEL[6] ,Enable the IRQ assertion on low level detect bit 6 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " LOWLEVEL[5] ,Enable the IRQ assertion on low level detect bit 5 " "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LOWLEVEL[4] ,Enable the IRQ assertion on low level detect bit 4 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " LOWLEVEL[3] ,Enable the IRQ assertion on low level detect bit 3 " "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LOWLEVEL[2] ,Enable the IRQ assertion on low level detect bit 2 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " LOWLEVEL[1] ,Enable the IRQ assertion on low level detect bit 1 " "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " LOWLEVEL[0] ,Enable the IRQ assertion on low level detect bit 0 " "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_LEVELDETECT1,High Level Interrupt Enable"
|
|
bitfld.long 0x08 31. " HIGHLEVEL[31] ,Enable the IRQ assertion on high level detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " HIGHLEVEL[30] ,Enable the IRQ assertion on high level detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " HIGHLEVEL[29] ,Enable the IRQ assertion on high level detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " HIGHLEVEL[28] ,Enable the IRQ assertion on high level detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " HIGHLEVEL[27] ,Enable the IRQ assertion on high level detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " HIGHLEVEL[26] ,Enable the IRQ assertion on high level detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " HIGHLEVEL[25] ,Enable the IRQ assertion on high level detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " HIGHLEVEL[24] ,Enable the IRQ assertion on high level detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HIGHLEVEL[23] ,Enable the IRQ assertion on high level detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " HIGHLEVEL[22] ,Enable the IRQ assertion on high level detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HIGHLEVEL[21] ,Enable the IRQ assertion on high level detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " HIGHLEVEL[20] ,Enable the IRQ assertion on high level detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HIGHLEVEL[19] ,Enable the IRQ assertion on high level detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " HIGHLEVEL[18] ,Enable the IRQ assertion on high level detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " HIGHLEVEL[17] ,Enable the IRQ assertion on high level detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " HIGHLEVEL[16] ,Enable the IRQ assertion on high level detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HIGHLEVEL[15] ,Enable the IRQ assertion on high level detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " HIGHLEVEL[14] ,Enable the IRQ assertion on high level detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " HIGHLEVEL[13] ,Enable the IRQ assertion on high level detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " HIGHLEVEL[12] ,Enable the IRQ assertion on high level detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HIGHLEVEL[11] ,Enable the IRQ assertion on high level detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " HIGHLEVEL[10] ,Enable the IRQ assertion on high level detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " HIGHLEVEL[9] ,Enable the IRQ assertion on high level detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " HIGHLEVEL[8] ,Enable the IRQ assertion on high level detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HIGHLEVEL[7] ,Enable the IRQ assertion on high level detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " HIGHLEVEL[6] ,Enable the IRQ assertion on high level detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIGHLEVEL[5] ,Enable the IRQ assertion on high level detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HIGHLEVEL[4] ,Enable the IRQ assertion on high level detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHLEVEL[3] ,Enable the IRQ assertion on high level detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " HIGHLEVEL[2] ,Enable the IRQ assertion on high level detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HIGHLEVEL[1] ,Enable the IRQ assertion on high level detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " HIGHLEVEL[0] ,Enable the IRQ assertion on high level detect bit 0" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_RISINGDETECT,Rising Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x0c 31. " RISINGEDGE[31] ,Enable IRQ/Wakeup on rising edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " RISINGEDGE[30] ,Enable IRQ/Wakeup on rising edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " RISINGEDGE[29] ,Enable IRQ/Wakeup on rising edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " RISINGEDGE[28] ,Enable IRQ/Wakeup on rising edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " RISINGEDGE[27] ,Enable IRQ/Wakeup on rising edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " RISINGEDGE[26] ,Enable IRQ/Wakeup on rising edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " RISINGEDGE[25] ,Enable IRQ/Wakeup on rising edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " RISINGEDGE[24] ,Enable IRQ/Wakeup on rising edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " RISINGEDGE[23] ,Enable IRQ/Wakeup on rising edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " RISINGEDGE[22] ,Enable IRQ/Wakeup on rising edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " RISINGEDGE[21] ,Enable IRQ/Wakeup on rising edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " RISINGEDGE[20] ,Enable IRQ/Wakeup on rising edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " RISINGEDGE[19] ,Enable IRQ/Wakeup on rising edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " RISINGEDGE[18] ,Enable IRQ/Wakeup on rising edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " RISINGEDGE[17] ,Enable IRQ/Wakeup on rising edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " RISINGEDGE[16] ,Enable IRQ/Wakeup on rising edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " RISINGEDGE[15] ,Enable IRQ/Wakeup on rising edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " RISINGEDGE[14] ,Enable IRQ/Wakeup on rising edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " RISINGEDGE[13] ,Enable IRQ/Wakeup on rising edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " RISINGEDGE[12] ,Enable IRQ/Wakeup on rising edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " RISINGEDGE[11] ,Enable IRQ/Wakeup on rising edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " RISINGEDGE[10] ,Enable IRQ/Wakeup on rising edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " RISINGEDGE[9] ,Enable IRQ/Wakeup on rising edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " RISINGEDGE[8] ,Enable IRQ/Wakeup on rising edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " RISINGEDGE[7] ,Enable IRQ/Wakeup on rising edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " RISINGEDGE[6] ,Enable IRQ/Wakeup on rising edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " RISINGEDGE[5] ,Enable IRQ/Wakeup on rising edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " RISINGEDGE[4] ,Enable IRQ/Wakeup on rising edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " RISINGEDGE[3] ,Enable IRQ/Wakeup on rising edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " RISINGEDGE[2] ,Enable IRQ/Wakeup on rising edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " RISINGEDGE[1] ,Enable IRQ/Wakeup on rising edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " RISINGEDGE[0] ,Enable IRQ/Wakeup on rising edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_FALLINGDETECT,Falling Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x10 31. " FALLINGEDGE[31] ,Enable IRQ/Wakeup on falling edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " FALLINGEDGE[30] ,Enable IRQ/Wakeup on falling edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " FALLINGEDGE[29] ,Enable IRQ/Wakeup on falling edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " FALLINGEDGE[28] ,Enable IRQ/Wakeup on falling edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " FALLINGEDGE[27] ,Enable IRQ/Wakeup on falling edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " FALLINGEDGE[26] ,Enable IRQ/Wakeup on falling edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " FALLINGEDGE[25] ,Enable IRQ/Wakeup on falling edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " FALLINGEDGE[24] ,Enable IRQ/Wakeup on falling edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " FALLINGEDGE[23] ,Enable IRQ/Wakeup on falling edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " FALLINGEDGE[22] ,Enable IRQ/Wakeup on falling edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " FALLINGEDGE[21] ,Enable IRQ/Wakeup on falling edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " FALLINGEDGE[20] ,Enable IRQ/Wakeup on falling edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " FALLINGEDGE[19] ,Enable IRQ/Wakeup on falling edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " FALLINGEDGE[18] ,Enable IRQ/Wakeup on falling edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " FALLINGEDGE[17] ,Enable IRQ/Wakeup on falling edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " FALLINGEDGE[16] ,Enable IRQ/Wakeup on falling edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FALLINGEDGE[15] ,Enable IRQ/Wakeup on falling edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " FALLINGEDGE[14] ,Enable IRQ/Wakeup on falling edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " FALLINGEDGE[13] ,Enable IRQ/Wakeup on falling edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " FALLINGEDGE[12] ,Enable IRQ/Wakeup on falling edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " FALLINGEDGE[11] ,Enable IRQ/Wakeup on falling edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " FALLINGEDGE[10] ,Enable IRQ/Wakeup on falling edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " FALLINGEDGE[9] ,Enable IRQ/Wakeup on falling edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " FALLINGEDGE[8] ,Enable IRQ/Wakeup on falling edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " FALLINGEDGE[7] ,Enable IRQ/Wakeup on falling edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " FALLINGEDGE[6] ,Enable IRQ/Wakeup on falling edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " FALLINGEDGE[5] ,Enable IRQ/Wakeup on falling edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " FALLINGEDGE[4] ,Enable IRQ/Wakeup on falling edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " FALLINGEDGE[3] ,Enable IRQ/Wakeup on falling edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " FALLINGEDGE[2] ,Enable IRQ/Wakeup on falling edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " FALLINGEDGE[1] ,Enable IRQ/Wakeup on falling edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " FALLINGEDGE[0] ,Enable IRQ/Wakeup on falling edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable"
|
|
bitfld.long 0x14 31. " DEBOUNCEEN[31] ,Enable debouncing feature bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " DEBOUNCEEN[30] ,Enable debouncing feature bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " DEBOUNCEEN[29] ,Enable debouncing feature bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " DEBOUNCEEN[28] ,Enable debouncing feature bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " DEBOUNCEEN[27] ,Enable debouncing feature bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " DEBOUNCEEN[26] ,Enable debouncing feature bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " DEBOUNCEEN[25] ,Enable debouncing feature bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DEBOUNCEEN[24] ,Enable debouncing feature bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " DEBOUNCEEN[23] ,Enable debouncing feature bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " DEBOUNCEEN[22] ,Enable debouncing feature bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " DEBOUNCEEN[21] ,Enable debouncing feature bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " DEBOUNCEEN[20] ,Enable debouncing feature bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " DEBOUNCEEN[19] ,Enable debouncing feature bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " DEBOUNCEEN[18] ,Enable debouncing feature bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " DEBOUNCEEN[17] ,Enable debouncing feature bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " DEBOUNCEEN[16] ,Enable debouncing feature bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DEBOUNCEEN[15] ,Enable debouncing feature bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DEBOUNCEEN[14] ,Enable debouncing feature bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DEBOUNCEEN[13] ,Enable debouncing feature bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DEBOUNCEEN[12] ,Enable debouncing feature bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DEBOUNCEEN[11] ,Enable debouncing feature bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DEBOUNCEEN[10] ,Enable debouncing feature bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DEBOUNCEEN[9] ,Enable debouncing feature bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DEBOUNCEEN[8] ,Enable debouncing feature bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DEBOUNCEEN[7] ,Enable debouncing feature bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DEBOUNCEEN[6] ,Enable debouncing feature bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DEBOUNCEEN[5] ,Enable debouncing feature bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DEBOUNCEEN[4] ,Enable debouncing feature bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DEBOUNCEEN[3] ,Enable debouncing feature bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DEBOUNCEEN[2] ,Enable debouncing feature bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DEBOUNCEEN[1] ,Enable debouncing feature bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DEBOUNCEEN[0] ,Enable debouncing feature bit 0" "Disabled,Enabled"
|
|
line.long 0x18 "GPIO_DEBOUNCINGTIME,Input Debouncing Value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCEVAL ,Input debouncing value"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO5"
|
|
base ad:0x49056000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO Configuration"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt 1 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS1[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS1[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS1[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS1[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS1[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS1[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS1[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS1[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS1[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS1[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS1[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS1[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS1[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS1[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS1[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS1[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS1[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS1[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS1[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS1[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS1[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS1[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS1[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS1[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS1[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS1[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS1[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS1[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS1[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS1[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS1[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS1[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE1,Interrupt 1 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE1[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE1[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE1[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE1[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE1[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE1[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE1[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE1[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE1[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE1[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE1[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE1[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE1[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE1[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE1[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE1[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE1[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE1[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE1[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE1[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE1[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE1[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE1[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE1[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE1[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE1[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE1[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE1[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE1[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE1[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE1[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE1[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_WAKEUPENABLE,Wake Up Enable Register"
|
|
setclrfld.long 0x08 31. 0x6c 31. 0x68 31. " WAKEUPEN[31]_set/clr ,Wakeup generation bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x6c 30. 0x68 30. " WAKEUPEN[30]_set/clr ,Wakeup generation bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 29. 0x6c 29. 0x68 29. " WAKEUPEN[29]_set/clr ,Wakeup generation bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x6c 28. 0x68 28. " WAKEUPEN[28]_set/clr ,Wakeup generation bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. 0x6c 27. 0x68 27. " WAKEUPEN[27]_set/clr ,Wakeup generation bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x6c 26. 0x68 26. " WAKEUPEN[26]_set/clr ,Wakeup generation bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x6c 25. 0x68 25. " WAKEUPEN[25]_set/clr ,Wakeup generation bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x6c 24. 0x68 24. " WAKEUPEN[24]_set/clr ,Wakeup generation bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. 0x6c 23. 0x68 23. " WAKEUPEN[23]_set/clr ,Wakeup generation bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x6c 22. 0x68 22. " WAKEUPEN[22]_set/clr ,Wakeup generation bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 21. 0x6c 21. 0x68 21. " WAKEUPEN[21]_set/clr ,Wakeup generation bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x6c 20. 0x68 20. " WAKEUPEN[20]_set/clr ,Wakeup generation bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x6c 19. 0x68 19. " WAKEUPEN[19]_set/clr ,Wakeup generation bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x6c 18. 0x68 18. " WAKEUPEN[18]_set/clr ,Wakeup generation bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 17. 0x6c 17. 0x68 17. " WAKEUPEN[17]_set/clr ,Wakeup generation bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x6c 16. 0x68 16. " WAKEUPEN[16]_set/clr ,Wakeup generation bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 15. 0x6c 15. 0x68 15. " WAKEUPEN[15]_set/clr ,Wakeup generation bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x6c 14. 0x68 14. " WAKEUPEN[14]_set/clr ,Wakeup generation bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x6c 13. 0x68 13. " WAKEUPEN[13]_set/clr ,Wakeup generation bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x6c 12. 0x68 12. " WAKEUPEN[12]_set/clr ,Wakeup generation bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. 0x6c 11. 0x68 11. " WAKEUPEN[11]_set/clr ,Wakeup generation bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x6c 10. 0x68 10. " WAKEUPEN[10]_set/clr ,Wakeup generation bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 9. 0x6c 9. 0x68 9. " WAKEUPEN[9]_set/clr ,Wakeup generation bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x6c 8. 0x68 8. " WAKEUPEN[8]_set/clr ,Wakeup generation bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x6c 7. 0x68 7. " WAKEUPEN[7]_set/clr ,Wakeup generation bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x6c 6. 0x68 6. " WAKEUPEN[6]_set/clr ,Wakeup generation bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. 0x6c 5. 0x68 5. " WAKEUPEN[5]_set/clr ,Wakeup generation bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x6c 4. 0x68 4. " WAKEUPEN[4]_set/clr ,Wakeup generation bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 3. 0x6c 3. 0x68 3. " WAKEUPEN[3]_set/clr ,Wakeup generation bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x6c 2. 0x68 2. " WAKEUPEN[2]_set/clr ,Wakeup generation bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x6c 1. 0x68 1. " WAKEUPEN[1]_set/clr ,Wakeup generation bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x6c 0. 0x68 0. " WAKEUPEN[0]_set/clr ,Wakeup generation bit 0 enable" "Disabled,Enabled"
|
|
group.long 0x28++0xf
|
|
line.long 0x00 "GPIO_IRQSTATUS2,Interrupt 2 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS2[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS2[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS2[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS2[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS2[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS2[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS2[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS2[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS2[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS2[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS2[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS2[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS2[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS2[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS2[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS2[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS2[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS2[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS2[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS2[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS2[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS2[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS2[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS2[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS2[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS2[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS2[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS2[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS2[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS2[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS2[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS2[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE2,Interrupt 2 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE2[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE2[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE2[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE2[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE2[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE2[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE2[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE2[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE2[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE2[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE2[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE2[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE2[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE2[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE2[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE2[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE2[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE2[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE2[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE2[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE2[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE2[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE2[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE2[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE2[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE2[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE2[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE2[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE2[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE2[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE2[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE2[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_CTRL,GPIO Control"
|
|
bitfld.long 0x08 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x08 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x0c "GPIO_OE,Output Data Enable"
|
|
bitfld.long 0x0c 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x0c 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x0c 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x0c 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x0c 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x0c 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x0c 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
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bitfld.long 0x0c 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
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bitfld.long 0x0c 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
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bitfld.long 0x0c 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
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bitfld.long 0x0c 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
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bitfld.long 0x0c 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
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bitfld.long 0x0c 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
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bitfld.long 0x0c 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
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bitfld.long 0x0c 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
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bitfld.long 0x0c 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
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textline " "
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bitfld.long 0x0c 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
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bitfld.long 0x0c 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
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rgroup.long 0x38++0x3
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line.long 0x00 "GPIO_DATAIN,Sampled Input Data"
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group.long 0x3c++0x1b
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line.long 0x00 "GPIO_DATAOUT,Output Data"
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setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
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setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
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textline " "
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setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
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setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
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textline " "
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setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
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setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
|
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textline " "
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setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
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setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
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textline " "
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setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
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setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
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textline " "
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setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
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setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
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textline " "
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setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
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setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
|
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textline " "
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setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
|
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setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
|
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textline " "
|
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setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
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setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
|
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textline " "
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setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
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setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
|
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textline " "
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setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
|
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setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
|
textline " "
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setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
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setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
|
textline " "
|
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setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
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setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
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textline " "
|
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setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
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setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
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textline " "
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setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
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setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
|
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textline " "
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setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
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setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
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line.long 0x04 "GPIO_LEVELDETECT0,Low Level Interrupt Enable"
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bitfld.long 0x04 31. " LOWLEVEL[31] ,Enable the IRQ assertion on low level detect bit 31 " "Disabled,Enabled"
|
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bitfld.long 0x04 30. " LOWLEVEL[30] ,Enable the IRQ assertion on low level detect bit 30 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 29. " LOWLEVEL[29] ,Enable the IRQ assertion on low level detect bit 29 " "Disabled,Enabled"
|
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bitfld.long 0x04 28. " LOWLEVEL[28] ,Enable the IRQ assertion on low level detect bit 28 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 27. " LOWLEVEL[27] ,Enable the IRQ assertion on low level detect bit 27 " "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " LOWLEVEL[26] ,Enable the IRQ assertion on low level detect bit 26 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " LOWLEVEL[25] ,Enable the IRQ assertion on low level detect bit 25 " "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " LOWLEVEL[24] ,Enable the IRQ assertion on low level detect bit 24 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 23. " LOWLEVEL[23] ,Enable the IRQ assertion on low level detect bit 23 " "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LOWLEVEL[22] ,Enable the IRQ assertion on low level detect bit 22 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 21. " LOWLEVEL[21] ,Enable the IRQ assertion on low level detect bit 21 " "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LOWLEVEL[20] ,Enable the IRQ assertion on low level detect bit 20 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LOWLEVEL[19] ,Enable the IRQ assertion on low level detect bit 19 " "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LOWLEVEL[18] ,Enable the IRQ assertion on low level detect bit 18 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LOWLEVEL[17] ,Enable the IRQ assertion on low level detect bit 17 " "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " LOWLEVEL[16] ,Enable the IRQ assertion on low level detect bit 16 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 15. " LOWLEVEL[15] ,Enable the IRQ assertion on low level detect bit 15 " "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LOWLEVEL[14] ,Enable the IRQ assertion on low level detect bit 14 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 13. " LOWLEVEL[13] ,Enable the IRQ assertion on low level detect bit 13 " "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LOWLEVEL[12] ,Enable the IRQ assertion on low level detect bit 12 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 11. " LOWLEVEL[11] ,Enable the IRQ assertion on low level detect bit 11 " "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LOWLEVEL[10] ,Enable the IRQ assertion on low level detect bit 10 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 9. " LOWLEVEL[9] ,Enable the IRQ assertion on low level detect bit 9 " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LOWLEVEL[8] ,Enable the IRQ assertion on low level detect bit 8 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 7. " LOWLEVEL[7] ,Enable the IRQ assertion on low level detect bit 7 " "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LOWLEVEL[6] ,Enable the IRQ assertion on low level detect bit 6 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 5. " LOWLEVEL[5] ,Enable the IRQ assertion on low level detect bit 5 " "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " LOWLEVEL[4] ,Enable the IRQ assertion on low level detect bit 4 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 3. " LOWLEVEL[3] ,Enable the IRQ assertion on low level detect bit 3 " "Disabled,Enabled"
|
|
bitfld.long 0x04 2. " LOWLEVEL[2] ,Enable the IRQ assertion on low level detect bit 2 " "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x04 1. " LOWLEVEL[1] ,Enable the IRQ assertion on low level detect bit 1 " "Disabled,Enabled"
|
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bitfld.long 0x04 0. " LOWLEVEL[0] ,Enable the IRQ assertion on low level detect bit 0 " "Disabled,Enabled"
|
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line.long 0x08 "GPIO_LEVELDETECT1,High Level Interrupt Enable"
|
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bitfld.long 0x08 31. " HIGHLEVEL[31] ,Enable the IRQ assertion on high level detect bit 31" "Disabled,Enabled"
|
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bitfld.long 0x08 30. " HIGHLEVEL[30] ,Enable the IRQ assertion on high level detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 29. " HIGHLEVEL[29] ,Enable the IRQ assertion on high level detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x08 28. " HIGHLEVEL[28] ,Enable the IRQ assertion on high level detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 27. " HIGHLEVEL[27] ,Enable the IRQ assertion on high level detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x08 26. " HIGHLEVEL[26] ,Enable the IRQ assertion on high level detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x08 25. " HIGHLEVEL[25] ,Enable the IRQ assertion on high level detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x08 24. " HIGHLEVEL[24] ,Enable the IRQ assertion on high level detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " HIGHLEVEL[23] ,Enable the IRQ assertion on high level detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " HIGHLEVEL[22] ,Enable the IRQ assertion on high level detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " HIGHLEVEL[21] ,Enable the IRQ assertion on high level detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " HIGHLEVEL[20] ,Enable the IRQ assertion on high level detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HIGHLEVEL[19] ,Enable the IRQ assertion on high level detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x08 18. " HIGHLEVEL[18] ,Enable the IRQ assertion on high level detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " HIGHLEVEL[17] ,Enable the IRQ assertion on high level detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " HIGHLEVEL[16] ,Enable the IRQ assertion on high level detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " HIGHLEVEL[15] ,Enable the IRQ assertion on high level detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x08 14. " HIGHLEVEL[14] ,Enable the IRQ assertion on high level detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " HIGHLEVEL[13] ,Enable the IRQ assertion on high level detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " HIGHLEVEL[12] ,Enable the IRQ assertion on high level detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " HIGHLEVEL[11] ,Enable the IRQ assertion on high level detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " HIGHLEVEL[10] ,Enable the IRQ assertion on high level detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " HIGHLEVEL[9] ,Enable the IRQ assertion on high level detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " HIGHLEVEL[8] ,Enable the IRQ assertion on high level detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " HIGHLEVEL[7] ,Enable the IRQ assertion on high level detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x08 6. " HIGHLEVEL[6] ,Enable the IRQ assertion on high level detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " HIGHLEVEL[5] ,Enable the IRQ assertion on high level detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " HIGHLEVEL[4] ,Enable the IRQ assertion on high level detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHLEVEL[3] ,Enable the IRQ assertion on high level detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " HIGHLEVEL[2] ,Enable the IRQ assertion on high level detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " HIGHLEVEL[1] ,Enable the IRQ assertion on high level detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " HIGHLEVEL[0] ,Enable the IRQ assertion on high level detect bit 0" "Disabled,Enabled"
|
|
line.long 0x0c "GPIO_RISINGDETECT,Rising Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x0c 31. " RISINGEDGE[31] ,Enable IRQ/Wakeup on rising edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x0c 30. " RISINGEDGE[30] ,Enable IRQ/Wakeup on rising edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x0c 29. " RISINGEDGE[29] ,Enable IRQ/Wakeup on rising edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " RISINGEDGE[28] ,Enable IRQ/Wakeup on rising edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x0c 27. " RISINGEDGE[27] ,Enable IRQ/Wakeup on rising edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " RISINGEDGE[26] ,Enable IRQ/Wakeup on rising edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x0c 25. " RISINGEDGE[25] ,Enable IRQ/Wakeup on rising edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " RISINGEDGE[24] ,Enable IRQ/Wakeup on rising edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " RISINGEDGE[23] ,Enable IRQ/Wakeup on rising edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " RISINGEDGE[22] ,Enable IRQ/Wakeup on rising edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x0c 21. " RISINGEDGE[21] ,Enable IRQ/Wakeup on rising edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " RISINGEDGE[20] ,Enable IRQ/Wakeup on rising edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x0c 19. " RISINGEDGE[19] ,Enable IRQ/Wakeup on rising edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " RISINGEDGE[18] ,Enable IRQ/Wakeup on rising edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " RISINGEDGE[17] ,Enable IRQ/Wakeup on rising edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " RISINGEDGE[16] ,Enable IRQ/Wakeup on rising edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " RISINGEDGE[15] ,Enable IRQ/Wakeup on rising edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " RISINGEDGE[14] ,Enable IRQ/Wakeup on rising edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " RISINGEDGE[13] ,Enable IRQ/Wakeup on rising edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " RISINGEDGE[12] ,Enable IRQ/Wakeup on rising edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " RISINGEDGE[11] ,Enable IRQ/Wakeup on rising edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " RISINGEDGE[10] ,Enable IRQ/Wakeup on rising edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " RISINGEDGE[9] ,Enable IRQ/Wakeup on rising edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " RISINGEDGE[8] ,Enable IRQ/Wakeup on rising edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " RISINGEDGE[7] ,Enable IRQ/Wakeup on rising edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " RISINGEDGE[6] ,Enable IRQ/Wakeup on rising edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " RISINGEDGE[5] ,Enable IRQ/Wakeup on rising edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " RISINGEDGE[4] ,Enable IRQ/Wakeup on rising edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " RISINGEDGE[3] ,Enable IRQ/Wakeup on rising edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " RISINGEDGE[2] ,Enable IRQ/Wakeup on rising edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " RISINGEDGE[1] ,Enable IRQ/Wakeup on rising edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " RISINGEDGE[0] ,Enable IRQ/Wakeup on rising edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_FALLINGDETECT,Falling Edge Interrupt/Wakeup Enable"
|
|
bitfld.long 0x10 31. " FALLINGEDGE[31] ,Enable IRQ/Wakeup on falling edge detect bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " FALLINGEDGE[30] ,Enable IRQ/Wakeup on falling edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " FALLINGEDGE[29] ,Enable IRQ/Wakeup on falling edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " FALLINGEDGE[28] ,Enable IRQ/Wakeup on falling edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " FALLINGEDGE[27] ,Enable IRQ/Wakeup on falling edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " FALLINGEDGE[26] ,Enable IRQ/Wakeup on falling edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 25. " FALLINGEDGE[25] ,Enable IRQ/Wakeup on falling edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " FALLINGEDGE[24] ,Enable IRQ/Wakeup on falling edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " FALLINGEDGE[23] ,Enable IRQ/Wakeup on falling edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " FALLINGEDGE[22] ,Enable IRQ/Wakeup on falling edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " FALLINGEDGE[21] ,Enable IRQ/Wakeup on falling edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " FALLINGEDGE[20] ,Enable IRQ/Wakeup on falling edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " FALLINGEDGE[19] ,Enable IRQ/Wakeup on falling edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " FALLINGEDGE[18] ,Enable IRQ/Wakeup on falling edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " FALLINGEDGE[17] ,Enable IRQ/Wakeup on falling edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " FALLINGEDGE[16] ,Enable IRQ/Wakeup on falling edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FALLINGEDGE[15] ,Enable IRQ/Wakeup on falling edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " FALLINGEDGE[14] ,Enable IRQ/Wakeup on falling edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " FALLINGEDGE[13] ,Enable IRQ/Wakeup on falling edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " FALLINGEDGE[12] ,Enable IRQ/Wakeup on falling edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " FALLINGEDGE[11] ,Enable IRQ/Wakeup on falling edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " FALLINGEDGE[10] ,Enable IRQ/Wakeup on falling edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " FALLINGEDGE[9] ,Enable IRQ/Wakeup on falling edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " FALLINGEDGE[8] ,Enable IRQ/Wakeup on falling edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " FALLINGEDGE[7] ,Enable IRQ/Wakeup on falling edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " FALLINGEDGE[6] ,Enable IRQ/Wakeup on falling edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " FALLINGEDGE[5] ,Enable IRQ/Wakeup on falling edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " FALLINGEDGE[4] ,Enable IRQ/Wakeup on falling edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " FALLINGEDGE[3] ,Enable IRQ/Wakeup on falling edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " FALLINGEDGE[2] ,Enable IRQ/Wakeup on falling edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " FALLINGEDGE[1] ,Enable IRQ/Wakeup on falling edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " FALLINGEDGE[0] ,Enable IRQ/Wakeup on falling edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable"
|
|
bitfld.long 0x14 31. " DEBOUNCEEN[31] ,Enable debouncing feature bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " DEBOUNCEEN[30] ,Enable debouncing feature bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " DEBOUNCEEN[29] ,Enable debouncing feature bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " DEBOUNCEEN[28] ,Enable debouncing feature bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " DEBOUNCEEN[27] ,Enable debouncing feature bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " DEBOUNCEEN[26] ,Enable debouncing feature bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " DEBOUNCEEN[25] ,Enable debouncing feature bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DEBOUNCEEN[24] ,Enable debouncing feature bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " DEBOUNCEEN[23] ,Enable debouncing feature bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " DEBOUNCEEN[22] ,Enable debouncing feature bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " DEBOUNCEEN[21] ,Enable debouncing feature bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " DEBOUNCEEN[20] ,Enable debouncing feature bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " DEBOUNCEEN[19] ,Enable debouncing feature bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " DEBOUNCEEN[18] ,Enable debouncing feature bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " DEBOUNCEEN[17] ,Enable debouncing feature bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " DEBOUNCEEN[16] ,Enable debouncing feature bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DEBOUNCEEN[15] ,Enable debouncing feature bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DEBOUNCEEN[14] ,Enable debouncing feature bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DEBOUNCEEN[13] ,Enable debouncing feature bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DEBOUNCEEN[12] ,Enable debouncing feature bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DEBOUNCEEN[11] ,Enable debouncing feature bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DEBOUNCEEN[10] ,Enable debouncing feature bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DEBOUNCEEN[9] ,Enable debouncing feature bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DEBOUNCEEN[8] ,Enable debouncing feature bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DEBOUNCEEN[7] ,Enable debouncing feature bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DEBOUNCEEN[6] ,Enable debouncing feature bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DEBOUNCEEN[5] ,Enable debouncing feature bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DEBOUNCEEN[4] ,Enable debouncing feature bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DEBOUNCEEN[3] ,Enable debouncing feature bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DEBOUNCEEN[2] ,Enable debouncing feature bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DEBOUNCEEN[1] ,Enable debouncing feature bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DEBOUNCEEN[0] ,Enable debouncing feature bit 0" "Disabled,Enabled"
|
|
line.long 0x18 "GPIO_DEBOUNCINGTIME,Input Debouncing Value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCEVAL ,Input debouncing value"
|
|
width 11.
|
|
tree.end
|
|
tree "GPIO6"
|
|
base ad:0x49058000
|
|
width 21.
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "GPIO_SYSCONFIG,GPIO Configuration"
|
|
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Idle,No idle,Smart idle,?..."
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enabled/disabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "GPIO_SYSSTATUS,GPIO Status Information Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long 0x18++0xb
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt 1 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS1[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS1[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS1[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS1[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS1[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS1[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS1[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS1[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS1[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS1[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS1[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS1[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS1[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS1[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS1[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS1[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS1[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS1[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS1[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS1[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS1[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS1[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS1[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS1[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS1[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS1[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS1[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS1[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS1[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS1[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS1[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS1[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE1,Interrupt 1 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE1[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE1[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE1[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE1[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE1[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE1[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE1[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE1[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE1[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE1[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE1[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE1[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE1[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE1[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE1[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE1[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE1[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE1[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE1[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE1[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE1[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE1[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE1[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE1[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE1[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE1[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE1[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE1[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE1[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE1[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE1[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE1[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_WAKEUPENABLE,Wake Up Enable Register"
|
|
setclrfld.long 0x08 31. 0x6c 31. 0x68 31. " WAKEUPEN[31]_set/clr ,Wakeup generation bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x6c 30. 0x68 30. " WAKEUPEN[30]_set/clr ,Wakeup generation bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 29. 0x6c 29. 0x68 29. " WAKEUPEN[29]_set/clr ,Wakeup generation bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x6c 28. 0x68 28. " WAKEUPEN[28]_set/clr ,Wakeup generation bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 27. 0x6c 27. 0x68 27. " WAKEUPEN[27]_set/clr ,Wakeup generation bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x6c 26. 0x68 26. " WAKEUPEN[26]_set/clr ,Wakeup generation bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x6c 25. 0x68 25. " WAKEUPEN[25]_set/clr ,Wakeup generation bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x6c 24. 0x68 24. " WAKEUPEN[24]_set/clr ,Wakeup generation bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 23. 0x6c 23. 0x68 23. " WAKEUPEN[23]_set/clr ,Wakeup generation bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x6c 22. 0x68 22. " WAKEUPEN[22]_set/clr ,Wakeup generation bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 21. 0x6c 21. 0x68 21. " WAKEUPEN[21]_set/clr ,Wakeup generation bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x6c 20. 0x68 20. " WAKEUPEN[20]_set/clr ,Wakeup generation bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x6c 19. 0x68 19. " WAKEUPEN[19]_set/clr ,Wakeup generation bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x6c 18. 0x68 18. " WAKEUPEN[18]_set/clr ,Wakeup generation bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 17. 0x6c 17. 0x68 17. " WAKEUPEN[17]_set/clr ,Wakeup generation bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x6c 16. 0x68 16. " WAKEUPEN[16]_set/clr ,Wakeup generation bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 15. 0x6c 15. 0x68 15. " WAKEUPEN[15]_set/clr ,Wakeup generation bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x6c 14. 0x68 14. " WAKEUPEN[14]_set/clr ,Wakeup generation bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x6c 13. 0x68 13. " WAKEUPEN[13]_set/clr ,Wakeup generation bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x6c 12. 0x68 12. " WAKEUPEN[12]_set/clr ,Wakeup generation bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 11. 0x6c 11. 0x68 11. " WAKEUPEN[11]_set/clr ,Wakeup generation bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x6c 10. 0x68 10. " WAKEUPEN[10]_set/clr ,Wakeup generation bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 9. 0x6c 9. 0x68 9. " WAKEUPEN[9]_set/clr ,Wakeup generation bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x6c 8. 0x68 8. " WAKEUPEN[8]_set/clr ,Wakeup generation bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x6c 7. 0x68 7. " WAKEUPEN[7]_set/clr ,Wakeup generation bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x6c 6. 0x68 6. " WAKEUPEN[6]_set/clr ,Wakeup generation bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 5. 0x6c 5. 0x68 5. " WAKEUPEN[5]_set/clr ,Wakeup generation bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x6c 4. 0x68 4. " WAKEUPEN[4]_set/clr ,Wakeup generation bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 3. 0x6c 3. 0x68 3. " WAKEUPEN[3]_set/clr ,Wakeup generation bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x6c 2. 0x68 2. " WAKEUPEN[2]_set/clr ,Wakeup generation bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x6c 1. 0x68 1. " WAKEUPEN[1]_set/clr ,Wakeup generation bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x6c 0. 0x68 0. " WAKEUPEN[0]_set/clr ,Wakeup generation bit 0 enable" "Disabled,Enabled"
|
|
group.long 0x28++0xf
|
|
line.long 0x00 "GPIO_IRQSTATUS2,Interrupt 2 Status Register"
|
|
eventfld.long 0x00 31. " IRQSTATUS2[31] ,IRQ status bit 31" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 30. " IRQSTATUS2[30] ,IRQ status bit 30" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 29. " IRQSTATUS2[29] ,IRQ status bit 29" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 28. " IRQSTATUS2[28] ,IRQ status bit 28" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 27. " IRQSTATUS2[27] ,IRQ status bit 27" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 26. " IRQSTATUS2[26] ,IRQ status bit 26" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 25. " IRQSTATUS2[25] ,IRQ status bit 25" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 24. " IRQSTATUS2[24] ,IRQ status bit 24" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 23. " IRQSTATUS2[23] ,IRQ status bit 23" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 22. " IRQSTATUS2[22] ,IRQ status bit 22" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 21. " IRQSTATUS2[21] ,IRQ status bit 21" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 20. " IRQSTATUS2[20] ,IRQ status bit 20" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 19. " IRQSTATUS2[19] ,IRQ status bit 19" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 18. " IRQSTATUS2[18] ,IRQ status bit 18" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 17. " IRQSTATUS2[17] ,IRQ status bit 17" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 16. " IRQSTATUS2[16] ,IRQ status bit 16" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 15. " IRQSTATUS2[15] ,IRQ status bit 15" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " IRQSTATUS2[14] ,IRQ status bit 14" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " IRQSTATUS2[13] ,IRQ status bit 13" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " IRQSTATUS2[12] ,IRQ status bit 12" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " IRQSTATUS2[11] ,IRQ status bit 11" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " IRQSTATUS2[10] ,IRQ status bit 10" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 9. " IRQSTATUS2[9] ,IRQ status bit 9" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " IRQSTATUS2[8] ,IRQ status bit 8" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " IRQSTATUS2[7] ,IRQ status bit 7" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " IRQSTATUS2[6] ,IRQ status bit 6" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " IRQSTATUS2[5] ,IRQ status bit 5" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " IRQSTATUS2[4] ,IRQ status bit 4" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 3. " IRQSTATUS2[3] ,IRQ status bit 3" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " IRQSTATUS2[2] ,IRQ status bit 2" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " IRQSTATUS2[1] ,IRQ status bit 1" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " IRQSTATUS2[0] ,IRQ status bit 0" "No interrupt,Interrupt"
|
|
line.long 0x04 "GPIO_IRQENABLE2,Interrupt 2 Enable Register"
|
|
setclrfld.long 0x04 31. 0x4c 31. 0x48 31. " IRQENABLE2[31]_set/clr ,IRQ bit 31 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x4c 30. 0x48 30. " IRQENABLE2[30]_set/clr ,IRQ bit 30 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 29. 0x4c 29. 0x48 29. " IRQENABLE2[29]_set/clr ,IRQ bit 29 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x4c 28. 0x48 28. " IRQENABLE2[28]_set/clr ,IRQ bit 28 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 27. 0x4c 27. 0x48 27. " IRQENABLE2[27]_set/clr ,IRQ bit 27 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x4c 26. 0x48 26. " IRQENABLE2[26]_set/clr ,IRQ bit 26 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x4c 25. 0x48 25. " IRQENABLE2[25]_set/clr ,IRQ bit 25 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x4c 24. 0x48 24. " IRQENABLE2[24]_set/clr ,IRQ bit 24 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 23. 0x4c 23. 0x48 23. " IRQENABLE2[23]_set/clr ,IRQ bit 23 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x4c 22. 0x48 22. " IRQENABLE2[22]_set/clr ,IRQ bit 22 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 21. 0x4c 21. 0x48 21. " IRQENABLE2[21]_set/clr ,IRQ bit 21 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x4c 20. 0x48 20. " IRQENABLE2[20]_set/clr ,IRQ bit 20 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x4c 19. 0x48 19. " IRQENABLE2[19]_set/clr ,IRQ bit 19 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x4c 18. 0x48 18. " IRQENABLE2[18]_set/clr ,IRQ bit 18 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 17. 0x4c 17. 0x48 17. " IRQENABLE2[17]_set/clr ,IRQ bit 17 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x4c 16. 0x48 16. " IRQENABLE2[16]_set/clr ,IRQ bit 16 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 15. 0x4c 15. 0x48 15. " IRQENABLE2[15]_set/clr ,IRQ bit 15 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x4c 14. 0x48 14. " IRQENABLE2[14]_set/clr ,IRQ bit 14 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x4c 13. 0x48 13. " IRQENABLE2[13]_set/clr ,IRQ bit 13 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x4c 12. 0x48 12. " IRQENABLE2[12]_set/clr ,IRQ bit 12 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 11. 0x4c 11. 0x48 11. " IRQENABLE2[11]_set/clr ,IRQ bit 11 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x4c 10. 0x48 10. " IRQENABLE2[10]_set/clr ,IRQ bit 10 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 9. 0x4c 9. 0x48 9. " IRQENABLE2[9]_set/clr ,IRQ bit 9 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x4c 8. 0x48 8. " IRQENABLE2[8]_set/clr ,IRQ bit 8 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x4c 7. 0x48 7. " IRQENABLE2[7]_set/clr ,IRQ bit 7 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x4c 6. 0x48 6. " IRQENABLE2[6]_set/clr ,IRQ bit 6 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 5. 0x4c 5. 0x48 5. " IRQENABLE2[5]_set/clr ,IRQ bit 5 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x4c 4. 0x48 4. " IRQENABLE2[4]_set/clr ,IRQ bit 4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 3. 0x4c 3. 0x48 3. " IRQENABLE2[3]_set/clr ,IRQ bit 3 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x4c 2. 0x48 2. " IRQENABLE2[2]_set/clr ,IRQ bit 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x4c 1. 0x48 1. " IRQENABLE2[1]_set/clr ,IRQ bit 1 enable" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x4c 0. 0x48 0. " IRQENABLE2[0]_set/clr ,IRQ bit 0 enable" "Disabled,Enabled"
|
|
line.long 0x08 "GPIO_CTRL,GPIO Control"
|
|
bitfld.long 0x08 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
|
|
bitfld.long 0x08 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
|
|
line.long 0x0c "GPIO_OE,Output Data Enable"
|
|
bitfld.long 0x0c 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
|
|
bitfld.long 0x0c 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
|
|
bitfld.long 0x0c 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
|
|
bitfld.long 0x0c 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
|
|
bitfld.long 0x0c 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
|
|
bitfld.long 0x0c 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
|
|
bitfld.long 0x0c 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
|
|
bitfld.long 0x0c 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
|
|
bitfld.long 0x0c 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
|
|
bitfld.long 0x0c 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
|
|
bitfld.long 0x0c 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
|
|
bitfld.long 0x0c 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
|
|
bitfld.long 0x0c 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
|
|
bitfld.long 0x0c 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
|
|
bitfld.long 0x0c 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
|
|
bitfld.long 0x0c 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
|
|
bitfld.long 0x0c 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x00 "GPIO_DATAIN,Sampled Input Data"
|
|
group.long 0x3c++0x1b
|
|
line.long 0x00 "GPIO_DATAOUT,Output Data"
|
|
setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
|
|
setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
|
|
setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
|
|
setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
|
|
setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
|
|
setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
|
|
setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
|
|
setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
|
|
setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
|
|
setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
|
|
setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
|
|
setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
|
|
setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
|
|
setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
|
|
setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
|
|
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
|
|
setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
|
|
line.long 0x04 "GPIO_LEVELDETECT0,Low Level Interrupt Enable"
|
|
bitfld.long 0x04 31. " LOWLEVEL[31] ,Enable the IRQ assertion on low level detect bit 31 " "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " LOWLEVEL[30] ,Enable the IRQ assertion on low level detect bit 30 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " LOWLEVEL[29] ,Enable the IRQ assertion on low level detect bit 29 " "Disabled,Enabled"
|
|
bitfld.long 0x04 28. " LOWLEVEL[28] ,Enable the IRQ assertion on low level detect bit 28 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " LOWLEVEL[27] ,Enable the IRQ assertion on low level detect bit 27 " "Disabled,Enabled"
|
|
bitfld.long 0x04 26. " LOWLEVEL[26] ,Enable the IRQ assertion on low level detect bit 26 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " LOWLEVEL[25] ,Enable the IRQ assertion on low level detect bit 25 " "Disabled,Enabled"
|
|
bitfld.long 0x04 24. " LOWLEVEL[24] ,Enable the IRQ assertion on low level detect bit 24 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " LOWLEVEL[23] ,Enable the IRQ assertion on low level detect bit 23 " "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " LOWLEVEL[22] ,Enable the IRQ assertion on low level detect bit 22 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " LOWLEVEL[21] ,Enable the IRQ assertion on low level detect bit 21 " "Disabled,Enabled"
|
|
bitfld.long 0x04 20. " LOWLEVEL[20] ,Enable the IRQ assertion on low level detect bit 20 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " LOWLEVEL[19] ,Enable the IRQ assertion on low level detect bit 19 " "Disabled,Enabled"
|
|
bitfld.long 0x04 18. " LOWLEVEL[18] ,Enable the IRQ assertion on low level detect bit 18 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LOWLEVEL[17] ,Enable the IRQ assertion on low level detect bit 17 " "Disabled,Enabled"
|
|
bitfld.long 0x04 16. " LOWLEVEL[16] ,Enable the IRQ assertion on low level detect bit 16 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " LOWLEVEL[15] ,Enable the IRQ assertion on low level detect bit 15 " "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " LOWLEVEL[14] ,Enable the IRQ assertion on low level detect bit 14 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " LOWLEVEL[13] ,Enable the IRQ assertion on low level detect bit 13 " "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " LOWLEVEL[12] ,Enable the IRQ assertion on low level detect bit 12 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " LOWLEVEL[11] ,Enable the IRQ assertion on low level detect bit 11 " "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " LOWLEVEL[10] ,Enable the IRQ assertion on low level detect bit 10 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LOWLEVEL[9] ,Enable the IRQ assertion on low level detect bit 9 " "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " LOWLEVEL[8] ,Enable the IRQ assertion on low level detect bit 8 " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LOWLEVEL[7] ,Enable the IRQ assertion on low level detect bit 7 " "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " LOWLEVEL[6] ,Enable the IRQ assertion on low level detect bit 6 " "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x04 5. " LOWLEVEL[5] ,Enable the IRQ assertion on low level detect bit 5 " "Disabled,Enabled"
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|
bitfld.long 0x04 4. " LOWLEVEL[4] ,Enable the IRQ assertion on low level detect bit 4 " "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x04 3. " LOWLEVEL[3] ,Enable the IRQ assertion on low level detect bit 3 " "Disabled,Enabled"
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|
bitfld.long 0x04 2. " LOWLEVEL[2] ,Enable the IRQ assertion on low level detect bit 2 " "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x04 1. " LOWLEVEL[1] ,Enable the IRQ assertion on low level detect bit 1 " "Disabled,Enabled"
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|
bitfld.long 0x04 0. " LOWLEVEL[0] ,Enable the IRQ assertion on low level detect bit 0 " "Disabled,Enabled"
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|
line.long 0x08 "GPIO_LEVELDETECT1,High Level Interrupt Enable"
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|
bitfld.long 0x08 31. " HIGHLEVEL[31] ,Enable the IRQ assertion on high level detect bit 31" "Disabled,Enabled"
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|
bitfld.long 0x08 30. " HIGHLEVEL[30] ,Enable the IRQ assertion on high level detect bit 30" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x08 29. " HIGHLEVEL[29] ,Enable the IRQ assertion on high level detect bit 29" "Disabled,Enabled"
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|
bitfld.long 0x08 28. " HIGHLEVEL[28] ,Enable the IRQ assertion on high level detect bit 28" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x08 27. " HIGHLEVEL[27] ,Enable the IRQ assertion on high level detect bit 27" "Disabled,Enabled"
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|
bitfld.long 0x08 26. " HIGHLEVEL[26] ,Enable the IRQ assertion on high level detect bit 26" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x08 25. " HIGHLEVEL[25] ,Enable the IRQ assertion on high level detect bit 25" "Disabled,Enabled"
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bitfld.long 0x08 24. " HIGHLEVEL[24] ,Enable the IRQ assertion on high level detect bit 24" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x08 23. " HIGHLEVEL[23] ,Enable the IRQ assertion on high level detect bit 23" "Disabled,Enabled"
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bitfld.long 0x08 22. " HIGHLEVEL[22] ,Enable the IRQ assertion on high level detect bit 22" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x08 21. " HIGHLEVEL[21] ,Enable the IRQ assertion on high level detect bit 21" "Disabled,Enabled"
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bitfld.long 0x08 20. " HIGHLEVEL[20] ,Enable the IRQ assertion on high level detect bit 20" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x08 19. " HIGHLEVEL[19] ,Enable the IRQ assertion on high level detect bit 19" "Disabled,Enabled"
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bitfld.long 0x08 18. " HIGHLEVEL[18] ,Enable the IRQ assertion on high level detect bit 18" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x08 17. " HIGHLEVEL[17] ,Enable the IRQ assertion on high level detect bit 17" "Disabled,Enabled"
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bitfld.long 0x08 16. " HIGHLEVEL[16] ,Enable the IRQ assertion on high level detect bit 16" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x08 15. " HIGHLEVEL[15] ,Enable the IRQ assertion on high level detect bit 15" "Disabled,Enabled"
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bitfld.long 0x08 14. " HIGHLEVEL[14] ,Enable the IRQ assertion on high level detect bit 14" "Disabled,Enabled"
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textline " "
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bitfld.long 0x08 13. " HIGHLEVEL[13] ,Enable the IRQ assertion on high level detect bit 13" "Disabled,Enabled"
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bitfld.long 0x08 12. " HIGHLEVEL[12] ,Enable the IRQ assertion on high level detect bit 12" "Disabled,Enabled"
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textline " "
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bitfld.long 0x08 11. " HIGHLEVEL[11] ,Enable the IRQ assertion on high level detect bit 11" "Disabled,Enabled"
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bitfld.long 0x08 10. " HIGHLEVEL[10] ,Enable the IRQ assertion on high level detect bit 10" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x08 9. " HIGHLEVEL[9] ,Enable the IRQ assertion on high level detect bit 9" "Disabled,Enabled"
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|
bitfld.long 0x08 8. " HIGHLEVEL[8] ,Enable the IRQ assertion on high level detect bit 8" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x08 7. " HIGHLEVEL[7] ,Enable the IRQ assertion on high level detect bit 7" "Disabled,Enabled"
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|
bitfld.long 0x08 6. " HIGHLEVEL[6] ,Enable the IRQ assertion on high level detect bit 6" "Disabled,Enabled"
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|
textline " "
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|
bitfld.long 0x08 5. " HIGHLEVEL[5] ,Enable the IRQ assertion on high level detect bit 5" "Disabled,Enabled"
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|
bitfld.long 0x08 4. " HIGHLEVEL[4] ,Enable the IRQ assertion on high level detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HIGHLEVEL[3] ,Enable the IRQ assertion on high level detect bit 3" "Disabled,Enabled"
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|
bitfld.long 0x08 2. " HIGHLEVEL[2] ,Enable the IRQ assertion on high level detect bit 2" "Disabled,Enabled"
|
|
textline " "
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bitfld.long 0x08 1. " HIGHLEVEL[1] ,Enable the IRQ assertion on high level detect bit 1" "Disabled,Enabled"
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bitfld.long 0x08 0. " HIGHLEVEL[0] ,Enable the IRQ assertion on high level detect bit 0" "Disabled,Enabled"
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line.long 0x0c "GPIO_RISINGDETECT,Rising Edge Interrupt/Wakeup Enable"
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bitfld.long 0x0c 31. " RISINGEDGE[31] ,Enable IRQ/Wakeup on rising edge detect bit 31" "Disabled,Enabled"
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bitfld.long 0x0c 30. " RISINGEDGE[30] ,Enable IRQ/Wakeup on rising edge detect bit 30" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x0c 29. " RISINGEDGE[29] ,Enable IRQ/Wakeup on rising edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x0c 28. " RISINGEDGE[28] ,Enable IRQ/Wakeup on rising edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
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bitfld.long 0x0c 27. " RISINGEDGE[27] ,Enable IRQ/Wakeup on rising edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x0c 26. " RISINGEDGE[26] ,Enable IRQ/Wakeup on rising edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " RISINGEDGE[25] ,Enable IRQ/Wakeup on rising edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x0c 24. " RISINGEDGE[24] ,Enable IRQ/Wakeup on rising edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " RISINGEDGE[23] ,Enable IRQ/Wakeup on rising edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x0c 22. " RISINGEDGE[22] ,Enable IRQ/Wakeup on rising edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
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|
bitfld.long 0x0c 21. " RISINGEDGE[21] ,Enable IRQ/Wakeup on rising edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x0c 20. " RISINGEDGE[20] ,Enable IRQ/Wakeup on rising edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
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bitfld.long 0x0c 19. " RISINGEDGE[19] ,Enable IRQ/Wakeup on rising edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x0c 18. " RISINGEDGE[18] ,Enable IRQ/Wakeup on rising edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 17. " RISINGEDGE[17] ,Enable IRQ/Wakeup on rising edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x0c 16. " RISINGEDGE[16] ,Enable IRQ/Wakeup on rising edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 15. " RISINGEDGE[15] ,Enable IRQ/Wakeup on rising edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x0c 14. " RISINGEDGE[14] ,Enable IRQ/Wakeup on rising edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " RISINGEDGE[13] ,Enable IRQ/Wakeup on rising edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x0c 12. " RISINGEDGE[12] ,Enable IRQ/Wakeup on rising edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " RISINGEDGE[11] ,Enable IRQ/Wakeup on rising edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x0c 10. " RISINGEDGE[10] ,Enable IRQ/Wakeup on rising edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 9. " RISINGEDGE[9] ,Enable IRQ/Wakeup on rising edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x0c 8. " RISINGEDGE[8] ,Enable IRQ/Wakeup on rising edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " RISINGEDGE[7] ,Enable IRQ/Wakeup on rising edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x0c 6. " RISINGEDGE[6] ,Enable IRQ/Wakeup on rising edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " RISINGEDGE[5] ,Enable IRQ/Wakeup on rising edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x0c 4. " RISINGEDGE[4] ,Enable IRQ/Wakeup on rising edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " RISINGEDGE[3] ,Enable IRQ/Wakeup on rising edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x0c 2. " RISINGEDGE[2] ,Enable IRQ/Wakeup on rising edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " RISINGEDGE[1] ,Enable IRQ/Wakeup on rising edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x0c 0. " RISINGEDGE[0] ,Enable IRQ/Wakeup on rising edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x10 "GPIO_FALLINGDETECT,Falling Edge Interrupt/Wakeup Enable"
|
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bitfld.long 0x10 31. " FALLINGEDGE[31] ,Enable IRQ/Wakeup on falling edge detect bit 31" "Disabled,Enabled"
|
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bitfld.long 0x10 30. " FALLINGEDGE[30] ,Enable IRQ/Wakeup on falling edge detect bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 29. " FALLINGEDGE[29] ,Enable IRQ/Wakeup on falling edge detect bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " FALLINGEDGE[28] ,Enable IRQ/Wakeup on falling edge detect bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " FALLINGEDGE[27] ,Enable IRQ/Wakeup on falling edge detect bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " FALLINGEDGE[26] ,Enable IRQ/Wakeup on falling edge detect bit 26" "Disabled,Enabled"
|
|
textline " "
|
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bitfld.long 0x10 25. " FALLINGEDGE[25] ,Enable IRQ/Wakeup on falling edge detect bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " FALLINGEDGE[24] ,Enable IRQ/Wakeup on falling edge detect bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 23. " FALLINGEDGE[23] ,Enable IRQ/Wakeup on falling edge detect bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x10 22. " FALLINGEDGE[22] ,Enable IRQ/Wakeup on falling edge detect bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 21. " FALLINGEDGE[21] ,Enable IRQ/Wakeup on falling edge detect bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " FALLINGEDGE[20] ,Enable IRQ/Wakeup on falling edge detect bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 19. " FALLINGEDGE[19] ,Enable IRQ/Wakeup on falling edge detect bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " FALLINGEDGE[18] ,Enable IRQ/Wakeup on falling edge detect bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 17. " FALLINGEDGE[17] ,Enable IRQ/Wakeup on falling edge detect bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " FALLINGEDGE[16] ,Enable IRQ/Wakeup on falling edge detect bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " FALLINGEDGE[15] ,Enable IRQ/Wakeup on falling edge detect bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " FALLINGEDGE[14] ,Enable IRQ/Wakeup on falling edge detect bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 13. " FALLINGEDGE[13] ,Enable IRQ/Wakeup on falling edge detect bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " FALLINGEDGE[12] ,Enable IRQ/Wakeup on falling edge detect bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 11. " FALLINGEDGE[11] ,Enable IRQ/Wakeup on falling edge detect bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x10 10. " FALLINGEDGE[10] ,Enable IRQ/Wakeup on falling edge detect bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " FALLINGEDGE[9] ,Enable IRQ/Wakeup on falling edge detect bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " FALLINGEDGE[8] ,Enable IRQ/Wakeup on falling edge detect bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 7. " FALLINGEDGE[7] ,Enable IRQ/Wakeup on falling edge detect bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x10 6. " FALLINGEDGE[6] ,Enable IRQ/Wakeup on falling edge detect bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 5. " FALLINGEDGE[5] ,Enable IRQ/Wakeup on falling edge detect bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " FALLINGEDGE[4] ,Enable IRQ/Wakeup on falling edge detect bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " FALLINGEDGE[3] ,Enable IRQ/Wakeup on falling edge detect bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x10 2. " FALLINGEDGE[2] ,Enable IRQ/Wakeup on falling edge detect bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 1. " FALLINGEDGE[1] ,Enable IRQ/Wakeup on falling edge detect bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " FALLINGEDGE[0] ,Enable IRQ/Wakeup on falling edge detect bit 0" "Disabled,Enabled"
|
|
line.long 0x14 "GPIO_DEBOUNCENABLE,Input Debounce Enable"
|
|
bitfld.long 0x14 31. " DEBOUNCEEN[31] ,Enable debouncing feature bit 31" "Disabled,Enabled"
|
|
bitfld.long 0x14 30. " DEBOUNCEEN[30] ,Enable debouncing feature bit 30" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 29. " DEBOUNCEEN[29] ,Enable debouncing feature bit 29" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " DEBOUNCEEN[28] ,Enable debouncing feature bit 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 27. " DEBOUNCEEN[27] ,Enable debouncing feature bit 27" "Disabled,Enabled"
|
|
bitfld.long 0x14 26. " DEBOUNCEEN[26] ,Enable debouncing feature bit 26" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 25. " DEBOUNCEEN[25] ,Enable debouncing feature bit 25" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " DEBOUNCEEN[24] ,Enable debouncing feature bit 24" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 23. " DEBOUNCEEN[23] ,Enable debouncing feature bit 23" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " DEBOUNCEEN[22] ,Enable debouncing feature bit 22" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 21. " DEBOUNCEEN[21] ,Enable debouncing feature bit 21" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " DEBOUNCEEN[20] ,Enable debouncing feature bit 20" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " DEBOUNCEEN[19] ,Enable debouncing feature bit 19" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " DEBOUNCEEN[18] ,Enable debouncing feature bit 18" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 17. " DEBOUNCEEN[17] ,Enable debouncing feature bit 17" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " DEBOUNCEEN[16] ,Enable debouncing feature bit 16" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " DEBOUNCEEN[15] ,Enable debouncing feature bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " DEBOUNCEEN[14] ,Enable debouncing feature bit 14" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 13. " DEBOUNCEEN[13] ,Enable debouncing feature bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x14 12. " DEBOUNCEEN[12] ,Enable debouncing feature bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 11. " DEBOUNCEEN[11] ,Enable debouncing feature bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " DEBOUNCEEN[10] ,Enable debouncing feature bit 10" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " DEBOUNCEEN[9] ,Enable debouncing feature bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " DEBOUNCEEN[8] ,Enable debouncing feature bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 7. " DEBOUNCEEN[7] ,Enable debouncing feature bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " DEBOUNCEEN[6] ,Enable debouncing feature bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " DEBOUNCEEN[5] ,Enable debouncing feature bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " DEBOUNCEEN[4] ,Enable debouncing feature bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 3. " DEBOUNCEEN[3] ,Enable debouncing feature bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " DEBOUNCEEN[2] ,Enable debouncing feature bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " DEBOUNCEEN[1] ,Enable debouncing feature bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DEBOUNCEEN[0] ,Enable debouncing feature bit 0" "Disabled,Enabled"
|
|
line.long 0x18 "GPIO_DEBOUNCINGTIME,Input Debouncing Value"
|
|
hexmask.long.byte 0x18 0.--7. 1. " DEBOUNCEVAL ,Input debouncing value"
|
|
width 11.
|
|
tree.end
|
|
tree.end
|
|
textline " "
|