2546 lines
165 KiB
Plaintext
2546 lines
165 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: NS7520 On-Chip Peripherals
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; @Props: Released
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; @Author: HUB
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; @Changelog: 2010-06-07 HUB
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; @Manufacturer: DIGI - Digi International Inc.
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; @Doc: NS7520_Hardware_Ref_90000353_B.pdf(2003.01)
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; prd_mp_ns7520_ds.pdf(2006.03)
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; @Core: ARM7TDMI
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; @Chip: NS7520
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perns7520.per 7594 2017-02-18 14:23:12Z askoncej $
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config 16. 8.
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tree "Icebreaker"
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width 8.
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group ice:0x8--0x0d "Watchpoint 0"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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group ice:0x10--0x15 "Watchpoint 1"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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tree.end
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tree "GEN Module"
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base ad:0xFFB00000
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width 8.
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group.long 0x00++0x0B
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line.long 0x00 "SYS_CON,System Control register"
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bitfld.long 0x00 31. " LENDIAN ,System endian configuration" "Big,Little"
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bitfld.long 0x00 29.--30. " BSPEED ,Bus speed configuration" "0,1,Full,3"
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textline " "
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bitfld.long 0x00 28. " BCLKD ,BCLK output disable" "Enabled,LOW state"
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bitfld.long 0x00 24. " SWE ,Software watchdog enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 22.--23. " SWRI ,Software watchdog reset/interrupt select" "Normal interrupt,Fast interrupt,Reset,?..."
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bitfld.long 0x00 20.--21. " SWT ,Software watchdog timeout" "2^20/FXTALE,2^22/FXTALE,2^24/FXTALE,2^25/FXTALE"
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textline " "
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bitfld.long 0x00 18. " BME ,Bus monitor enable" "Disabled,Enabled"
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bitfld.long 0x00 16.--17. " BMT ,Bus monitor timer" "128 BCLKS,64 BCLKS,32 BCLKS,16 BCLKS"
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textline " "
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bitfld.long 0x00 15. " USER ,Enable access to internal chip registers in CPU user mode" "Disabled,Enabled"
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bitfld.long 0x00 14. " BUSER ,Enable ARM CPU" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 13. " IARB ,Define system bus to internal arbiter" "Low,High"
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textline " "
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bitfld.long 0x00 12. " DMATST ,DMA module test mode" "Test mode disabled,Allow unrestricted access"
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textline " "
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bitfld.long 0x00 11. " TEALAST ,Bus interface TEA/LAST configuration" "Low,High"
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bitfld.long 0x00 10. " MISALIGN ,Bus error on misaligned cycles" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 7. " CPUDIS ,CPU disable" "CPU operational,CPU reset"
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bitfld.long 0x00 6. " DMARST ,DMA module reset" "No reset,Reset"
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textline " "
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bitfld.long 0x00 4.--5. " BSYNC ,TA_ input synchronizer" "1-stage,1-stage,2-stage,?..."
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width 8.
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line.long 0x04 "SYS_STAT,System Status register"
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hexmask.long.byte 0x04 24.--31. 1. " REV ,NS7520 revision ID"
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eventfld.long 0x04 23. " EXT ,Last reset caused by external reset" "No reset,Reset"
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eventfld.long 0x04 22. " WDOG ,Last reset caused by watchdog timer" "No reset,Reset"
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textline " "
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eventfld.long 0x04 21. " PLL ,Last reset caused by PLL update" "No reset,Reset"
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eventfld.long 0x04 20. " SOFT ,Last reset caused by software reset" "No reset,Reset"
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hexmask.long.word 0x04 0.--10. 1. " GEN_ID ,Product ID defined by external resistor jumpers"
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line.long 0x08 "PLL_CON,PLL Control register"
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bitfld.long 0x08 24.--27. " PLLCNT ,Frequency of SYS_CLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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wgroup.long 0x0C++0x03
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line.long 0x00 "SWSR,Software Service register"
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group.long 0x20++0x03
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line.long 0x00 "PORTACON,PORTA Configuration register"
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bitfld.long 0x00 31. " AMODEP7 ,PORTA pin7 mode configuration" "GPIO,Special function"
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bitfld.long 0x00 30. " AMODEP6 ,PORTA pin6 mode configuration" "GPIO,Special function"
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bitfld.long 0x00 29. " AMODEP5 ,PORTA pin5 mode configuration" "GPIO,Special function"
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textline " "
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bitfld.long 0x00 28. " AMODEP4 ,PORTA pin4 mode configuration" "GPIO,Special function"
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bitfld.long 0x00 27. " AMODEP3 ,PORTA pin3 mode configuration" "GPIO,Special function"
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bitfld.long 0x00 26. " AMODEP2 ,PORTA pin2 mode configuration" "GPIO,Special function"
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textline " "
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bitfld.long 0x00 25. " AMODEP1 ,PORTA pin1 mode configuration" "GPIO,Special function"
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bitfld.long 0x00 24. " AMODEP0 ,PORTA pin0 mode configuration" "GPIO,Special function"
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bitfld.long 0x00 23. " ADIRP7 ,PORTA pin7 data direction" "Input,Output"
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textline " "
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bitfld.long 0x00 22. " ADIRP6 ,PORTA pin6 data direction" "Input,Output"
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bitfld.long 0x00 21. " ADIRP5 ,PORTA pin5 data direction" "Input,Output"
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bitfld.long 0x00 20. " ADIRP4 ,PORTA pin4 data direction" "Input,Output"
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textline " "
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bitfld.long 0x00 19. " ADIRP3 ,PORTA pin3 data direction" "Input,Output"
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bitfld.long 0x00 18. " ADIRP2 ,PORTA pin2 data direction" "Input,Output"
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bitfld.long 0x00 17. " ADIRP1 ,PORTA pin1 data direction" "Input,Output"
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textline " "
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bitfld.long 0x00 16. " ADIRP0 ,PORTA pin0 data direction" "Input,Output"
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bitfld.long 0x00 7. " PORTA7 ,Current state of pin7" "Low,High"
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bitfld.long 0x00 6. " PORTA7 ,Current state of pin6" "Low,High"
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textline " "
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bitfld.long 0x00 5. " PORTA7 ,Current state of pin5" "Low,High"
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bitfld.long 0x00 5. " PORTA4 ,Current state of pin4" "Low,High"
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bitfld.long 0x00 5. " PORTA3 ,Current state of pin3" "Low,High"
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textline " "
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bitfld.long 0x00 5. " PORTA2 ,Current state of pin2" "Low,High"
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bitfld.long 0x00 5. " PORTA1 ,Current state of pin1" "Low,High"
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bitfld.long 0x00 5. " PORTA0 ,Current state of pin0" "Low,High"
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group.long 0x28++0x03
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line.long 0x00 "PORTCCON,PORTC Configuration register"
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bitfld.long 0x00 31. " CMODEP7 ,PORTC pin7 mode configuration" "GPIO,Special function"
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bitfld.long 0x00 30. " CMODEP6 ,PORTC pin6 mode configuration" "GPIO,Special function"
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bitfld.long 0x00 29. " CMODEP5 ,PORTC pin5 mode configuration" "GPIO,Special function"
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textline " "
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bitfld.long 0x00 28. " CMODEP4 ,PORTC pin4 mode configuration" "GPIO,Special function"
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bitfld.long 0x00 27. " CMODEP3 ,PORTC pin3 mode configuration" "GPIO,Special function"
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bitfld.long 0x00 26. " CMODEP2 ,PORTC pin2 mode configuration" "GPIO,Special function"
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textline " "
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bitfld.long 0x00 25. " CMODEP1 ,PORTC pin1 mode configuration" "GPIO,Special function"
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bitfld.long 0x00 24. " CMODEP0 ,PORTC pin0 mode configuration" "GPIO,Special function"
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bitfld.long 0x00 23. " CDIRP7 ,PORTC pin7 data direction" "Input,Output"
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textline " "
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bitfld.long 0x00 22. " CDIRP6 ,PORTC pin6 data direction" "Input,Output"
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bitfld.long 0x00 21. " CDIRP5 ,PORTC pin5 data direction" "Input,Output"
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bitfld.long 0x00 20. " CDIRP4 ,PORTC pin4 data direction" "Input,Output"
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textline " "
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bitfld.long 0x00 19. " CDIRP3 ,PORTC pin3 data direction" "Input,Output"
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bitfld.long 0x00 18. " CDIRP2 ,PORTC pin2 data direction" "Input,Output"
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bitfld.long 0x00 17. " CDIRP1 ,PORTC pin1 data direction" "Input,Output"
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textline " "
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bitfld.long 0x00 16. " CDIRP0 ,PORTC pin0 data direction" "Input,Output"
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bitfld.long 0x00 15. " CSFP7 ,PORTC pin7 special function" "Normal,Special"
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bitfld.long 0x00 14. " CSFP6 ,PORTC pin6 special function" "Normal,Special"
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textline " "
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bitfld.long 0x00 13. " CSFP5 ,PORTC pin5 special function" "Normal,Special"
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bitfld.long 0x00 12. " CSFP4 ,PORTC pin4 special function" "Normal,Special"
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bitfld.long 0x00 11. " CSFP3 ,PORTC pin3 special function" "Normal,Special"
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textline " "
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bitfld.long 0x00 10. " CSFP2 ,PORTC pin2 special function" "Normal,Special"
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bitfld.long 0x00 9. " CSFP1 ,PORTC pin1 special function" "Normal,Special"
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bitfld.long 0x00 8. " CSFP0 ,PORTC pin0 special function" "Normal,Special"
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textline " "
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bitfld.long 0x00 7. " PORTC7 ,Current state of pin7" "Low,High"
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bitfld.long 0x00 6. " PORTC7 ,Current state of pin6" "Low,High"
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bitfld.long 0x00 5. " PORTC7 ,Current state of pin5" "Low,High"
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textline " "
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bitfld.long 0x00 5. " PORTC4 ,Current state of pin4" "Low,High"
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bitfld.long 0x00 5. " PORTC3 ,Current state of pin3" "Low,High"
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bitfld.long 0x00 5. " PORTC2 ,Current state of pin2" "Low,High"
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textline " "
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bitfld.long 0x00 5. " PORTC1 ,Current state of pin1" "Low,High"
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bitfld.long 0x00 5. " PORTC0 ,Current state of pin0" "Low,High"
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group.long 0x30++0x0B
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line.long 0x00 "INTEN,Interrupt Enable register"
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bitfld.long 0x00 31. " DMA1 ,Enable interupt for DMA1" "Disabled,Enabled"
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bitfld.long 0x00 30. " DMA2 ,Enable interupt for DMA2" "Disabled,Enabled"
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bitfld.long 0x00 29. " DMA3 ,Enable interupt for DMA3" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 28. " DMA4 ,Enable interupt for DMA4" "Disabled,Enabled"
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bitfld.long 0x00 27. " DMA5 ,Enable interupt for DMA5" "Disabled,Enabled"
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bitfld.long 0x00 26. " DMA6 ,Enable interupt for DMA6" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 25. " DMA7 ,Enable interupt for DMA7" "Disabled,Enabled"
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bitfld.long 0x00 24. " DMA8 ,Enable interupt for DMA8" "Disabled,Enabled"
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bitfld.long 0x00 23. " DMA9 ,Enable interupt for DMA9" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 22. " DMA10 ,Enable interupt for DMA10" "Disabled,Enabled"
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bitfld.long 0x00 21. " DMA11 ,Enable interupt for DMA11" "Disabled,Enabled"
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bitfld.long 0x00 20. " DMA12 ,Enable interupt for DMA12" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 19. " DMA13 ,Enable interupt for DMA13" "Disabled,Enabled"
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bitfld.long 0x00 17. " ENET1RX ,Enable interrupt for the Ethernet receiver" "Disabled,Enabled"
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bitfld.long 0x00 16. " ENET1TX ,Enable interrupt for the Ethernet transmitter" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " SER1RX ,Enable interrupt for the Serial Channel A receiver" "Disabled,Enabled"
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bitfld.long 0x00 14. " SER1TX ,Enable interrupt for the Serial Channel A transmitter" "Disabled,Enabled"
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bitfld.long 0x00 13. " SER2RX ,Enable interrupt for the Serial Channel B receiver" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 12. " SER2TX ,Enable interrupt for the Serial Channel B transmitter" "Disabled,Enabled"
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bitfld.long 0x00 7. " MAC1 ,Enable interrupt for the Ethernet MAC 1" "Disabled,Enabled"
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bitfld.long 0x00 6. " WATCHDOG ,Enable interrupt for the WATCHDOG" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 5. " TIMER1 ,Enable interrupt for the TIMER1" "Disabled,Enabled"
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bitfld.long 0x00 4. " TIMER2 ,Enable interrupt for the TIMER2" "Disabled,Enabled"
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bitfld.long 0x00 3. " PORTC3 ,Enable interrupt for the PORTC3" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 2. " PORTC2 ,Enable interrupt for the PORTC2" "Disabled,Enabled"
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bitfld.long 0x00 1. " PORTC1 ,Enable interrupt for the PORTC1" "Disabled,Enabled"
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bitfld.long 0x00 0. " PORTC0 ,Enable interrupt for the PORTC0" "Disabled,Enabled"
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line.long 0x04 "INTCON,Interrupt controller registers"
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width 8.
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setclrfld.long 0x04 31. 0x04 31. 0x08 31. " DMA1_set/clr ,Interrupts sourced by DMA channel 1" "Disabled,Enabled"
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setclrfld.long 0x04 30. 0x04 30. 0x08 30. " DMA2_set/clr ,Interrupts sourced by DMA channel 2" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 29. 0x04 29. 0x08 29. " DMA3_set/clr ,Interrupts sourced by DMA channel 3" "Disabled,Enabled"
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setclrfld.long 0x04 28. 0x04 28. 0x08 28. " DMA4_set/clr ,Interrupts sourced by DMA channel 4" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 27. 0x04 27. 0x08 27. " DMA5_set/clr ,Interrupts sourced by DMA channel 5" "Disabled,Enabled"
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setclrfld.long 0x04 26. 0x04 26. 0x08 26. " DMA6_set/clr ,Interrupts sourced by DMA channel 6" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 25. 0x04 25. 0x08 25. " DMA7_set/clr ,Interrupts sourced by DMA channel 7" "Disabled,Enabled"
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setclrfld.long 0x04 24. 0x04 24. 0x08 24. " DMA8_set/clr ,Interrupts sourced by DMA channel 8" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 23. 0x04 23. 0x08 23. " DMA9_set/clr ,Interrupts sourced by DMA channel 9" "Disabled,Enabled"
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setclrfld.long 0x04 22. 0x04 22. 0x08 22. " DMA10_set/clr ,Interrupts sourced by DMA channel 10" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 21. 0x04 21. 0x08 21. " DMA11_set/clr ,Interrupts sourced by DMA channel 11" "Disabled,Enabled"
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setclrfld.long 0x04 20. 0x04 20. 0x08 20. " DMA12_set/clr ,Interrupts sourced by DMA channel 12" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 19. 0x04 19. 0x08 19. " DMA13_set/clr ,Interrupts sourced by DMA channel 13" "Disabled,Enabled"
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setclrfld.long 0x04 17. 0x04 17. 0x08 17. " ENET1RX_set/clr ,Interrupts sourced by the Ethernet receiver" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 16. 0x04 16. 0x08 16. " ENET1TX_set/clr ,Interrupts sourced by the Ethernet transmitter" "Disabled,Enabled"
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setclrfld.long 0x04 15. 0x04 15. 0x08 15. " SER1RX_set/clr ,Interrupts sourced by the Serial Channel A receiver" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 14. 0x04 14. 0x08 14. " SER1TX_set/clr ,Interrupts sourced by the Serial Channel A transmitter" "Disabled,Enabled"
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setclrfld.long 0x04 13. 0x04 13. 0x08 13. " SER2RX_set/clr ,Interrupts sourced by the Serial Channel B receiver" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 12. 0x04 12. 0x08 12. " SER2TX_set/clr ,Interrupts sourced by the Serial Channel B transmitter" "Disabled,Enabled"
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setclrfld.long 0x04 7. 0x04 7. 0x08 7. " MAC1_set/clr ,Interrupts sourced by the Ethernet MAC 1" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 6. 0x04 6. 0x08 6. " WATCHDOG_set/clr ,Interrupts sourced by the WATCHDOG" "Disabled,Enabled"
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setclrfld.long 0x04 5. 0x04 5. 0x08 5. " TIMER1_set/clr ,Interrupts condition sourced by the TIMER1" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 4. 0x04 4. 0x08 4. " TIMER2_set/clr ,Interrupts condition sourced by the TIMER2" "Disabled,Enabled"
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setclrfld.long 0x04 3. 0x04 3. 0x08 3. " PORTC3_set/clr ,Interrupts condition sourced by the PORTC3" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 2. 0x04 2. 0x08 2. " PORTC2_set/clr ,Interrupts condition sourced by the PORTC2" "Disabled,Enabled"
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setclrfld.long 0x04 1. 0x04 1. 0x08 1. " PORTC1_set/clr ,Interrupts condition sourced by the PORTC1" "Disabled,Enabled"
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textline " "
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setclrfld.long 0x04 0. 0x04 0. 0x08 0. " PORTC0_set/clr ,Interrupts condition sourced by the PORTC0" "Disabled,Enabled"
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width 8.
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rgroup.long 0x40++0x03
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line.long 0x00 "PLLSET,PLL Settings register"
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bitfld.long 0x00 7.--8. " IS ,Charge pump current" "1_4,4_7,8_15,16_32"
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bitfld.long 0x00 5.--6. " FS ,Output divider" "0,1,2,3"
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bitfld.long 0x00 0.--4. " ND ,PLL multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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width 0xB
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tree "TIMER1"
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base ad:0xFFB00010
|
|
width 10.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "TIMCON,Timer Control registers"
|
|
bitfld.long 0x00 31. " TE ,Timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TIE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " TIRO ,Timer interrupt mode" "Normal,Fast"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TPRE ,Timer prescaler" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TPRE ,Timer clock source" "F_XTALE,F_SYSCLK"
|
|
hexmask.long 0x00 0.--26. 1. " ITC ,Initial timer count"
|
|
line.long 0x04 "TIMSTA,Timer Status registers"
|
|
eventfld.long 0x04 30. " TIP ,Timer interrupt pending" "Disabled,Enabled"
|
|
hexmask.long 0x04 0.--26. 1. " CTC ,Current timer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "TIMER2"
|
|
base ad:0xFFB00018
|
|
width 10.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "TIMCON,Timer Control registers"
|
|
bitfld.long 0x00 31. " TE ,Timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TIE ,Timer interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 29. " TIRO ,Timer interrupt mode" "Normal,Fast"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TPRE ,Timer prescaler" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " TPRE ,Timer clock source" "F_XTALE,F_SYSCLK"
|
|
hexmask.long 0x00 0.--26. 1. " ITC ,Initial timer count"
|
|
line.long 0x04 "TIMSTA,Timer Status registers"
|
|
eventfld.long 0x04 30. " TIP ,Timer interrupt pending" "Disabled,Enabled"
|
|
hexmask.long 0x04 0.--26. 1. " CTC ,Current timer count"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "MEM (Memory Controller Module)"
|
|
base ad:0xFFC00000
|
|
width 6.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MMCR,Memory Module Configuration register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " RFCNT ,Refresh count value"
|
|
bitfld.long 0x00 23. " REFEN ,Enable DRAM refresh" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. " RCYC ,Refresh cycle count" "0,1,2,3"
|
|
bitfld.long 0x00 20. " AMUX ,Enable external address multiplexing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " A27 ,Enable A27 output" "CS0OE_ signal on the A27 pin,A27 signal on the A27 pin"
|
|
textline " "
|
|
bitfld.long 0x00 18. " A26 ,Enable A26 output" "CS0WE_ signal on the A26 pin,A26 signal on the A26 pin"
|
|
textline " "
|
|
bitfld.long 0x00 17. " A25 ,Enable A25 output" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " AMUX2 ,Internal/External/RAS/CAS mux" "Normal operation,DRAM MUX control"
|
|
width 6.
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "BAR0,Base Address register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BASE ,Base address"
|
|
bitfld.long 0x00 10.--11. " PGSIZE ,Peripheral page size" "64,32,16,8"
|
|
bitfld.long 0x00 8.--9. " DMODE ,DRAM configuration mode" "FP DRAM,EDO DRAM,SDRAM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMUXS ,DRAM address multiplexer select" "Internal,External"
|
|
bitfld.long 0x00 6. " EXTTA ,External TA_ configuration" "Internally,Externally"
|
|
bitfld.long 0x00 5. " DMUXM ,DRAM internal address multiplexer mode" "10 CAS,8 CAS"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,Force BCLK at end of memory cycle" "Low,High"
|
|
bitfld.long 0x00 3. " DRSEL ,Enable DRAM mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BURST ,Burst memory cycle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WP ,Write-protect the chip select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " V ,Valid bit" "Disabled,Enabled"
|
|
line.long 0x04 "OR0A,Option Register A"
|
|
bitfld.long 0x04 31. " Mask[19:0] ,Addres bit 19 Mask" "0,1"
|
|
bitfld.long 0x04 30. ",Addres bit 18 Mask" "0,1"
|
|
bitfld.long 0x04 29. ",Addres bit 17 Mask" "0,1"
|
|
bitfld.long 0x04 28. ",Addres bit 16 Mask" "0,1"
|
|
bitfld.long 0x04 27. ",Addres bit 15 Mask" "0,1"
|
|
bitfld.long 0x04 26. ",Addres bit 14 Mask" "0,1"
|
|
bitfld.long 0x04 25. ",Addres bit 13 Mask" "0,1"
|
|
bitfld.long 0x04 24. ",Addres bit 12 Mask" "0,1"
|
|
bitfld.long 0x04 23. ",Addres bit 11 Mask" "0,1"
|
|
bitfld.long 0x04 22. ",Addres bit 10 Mask" "0,1"
|
|
bitfld.long 0x04 21. ",Addres bit 9 Mask" "0,1"
|
|
bitfld.long 0x04 20. ",Addres bit 8 Mask" "0,1"
|
|
bitfld.long 0x04 19. ",Addres bit 7 Mask" "0,1"
|
|
bitfld.long 0x04 18. ",Addres bit 6 Mask" "0,1"
|
|
bitfld.long 0x04 17. ",Addres bit 5 Mask" "0,1"
|
|
bitfld.long 0x04 16. ",Addres bit 4 Mask" "0,1"
|
|
bitfld.long 0x04 15. ",Addres bit 3 Mask" "0,1"
|
|
bitfld.long 0x04 14. ",Addres bit 2 Mask" "0,1"
|
|
bitfld.long 0x04 13. ",Addres bit 1 Mask" "0,1"
|
|
bitfld.long 0x04 12. ",Addres bit 0 Mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " WAIT[3:0] ,Memory timing control fields" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 6.--7. " BCYC[1:0] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BSIZE ,Burst access size in beats" "2,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " PS ,Port size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x04 1. " OE_CTRL ,Read cycle mode" "OE,CS"
|
|
bitfld.long 0x04 0. " WE_CTRL ,Write cycle mode" "WE,CS"
|
|
line.long 0x08 "OR0B,Option Register B"
|
|
bitfld.long 0x08 4.--5. " WAIT[5:4] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x08 2.--3. " BCYC[3:2] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " SYNC ,TA_ input synchronizer" "Reserved,1-stage,2-stage,?..."
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "BAR1,Base Address register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BASE ,Base address"
|
|
bitfld.long 0x00 10.--11. " PGSIZE ,Peripheral page size" "64,32,16,8"
|
|
bitfld.long 0x00 8.--9. " DMODE ,DRAM configuration mode" "FP DRAM,EDO DRAM,SDRAM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMUXS ,DRAM address multiplexer select" "Internal,External"
|
|
bitfld.long 0x00 6. " EXTTA ,External TA_ configuration" "Internally,Externally"
|
|
bitfld.long 0x00 5. " DMUXM ,DRAM internal address multiplexer mode" "10 CAS,8 CAS"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,Force BCLK at end of memory cycle" "Low,High"
|
|
bitfld.long 0x00 3. " DRSEL ,Enable DRAM mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BURST ,Burst memory cycle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WP ,Write-protect the chip select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " V ,Valid bit" "Disabled,Enabled"
|
|
line.long 0x04 "OR1A,Option Register A"
|
|
bitfld.long 0x04 31. " Mask[19:0] ,Addres bit 19 Mask" "0,1"
|
|
bitfld.long 0x04 30. ",Addres bit 18 Mask" "0,1"
|
|
bitfld.long 0x04 29. ",Addres bit 17 Mask" "0,1"
|
|
bitfld.long 0x04 28. ",Addres bit 16 Mask" "0,1"
|
|
bitfld.long 0x04 27. ",Addres bit 15 Mask" "0,1"
|
|
bitfld.long 0x04 26. ",Addres bit 14 Mask" "0,1"
|
|
bitfld.long 0x04 25. ",Addres bit 13 Mask" "0,1"
|
|
bitfld.long 0x04 24. ",Addres bit 12 Mask" "0,1"
|
|
bitfld.long 0x04 23. ",Addres bit 11 Mask" "0,1"
|
|
bitfld.long 0x04 22. ",Addres bit 10 Mask" "0,1"
|
|
bitfld.long 0x04 21. ",Addres bit 9 Mask" "0,1"
|
|
bitfld.long 0x04 20. ",Addres bit 8 Mask" "0,1"
|
|
bitfld.long 0x04 19. ",Addres bit 7 Mask" "0,1"
|
|
bitfld.long 0x04 18. ",Addres bit 6 Mask" "0,1"
|
|
bitfld.long 0x04 17. ",Addres bit 5 Mask" "0,1"
|
|
bitfld.long 0x04 16. ",Addres bit 4 Mask" "0,1"
|
|
bitfld.long 0x04 15. ",Addres bit 3 Mask" "0,1"
|
|
bitfld.long 0x04 14. ",Addres bit 2 Mask" "0,1"
|
|
bitfld.long 0x04 13. ",Addres bit 1 Mask" "0,1"
|
|
bitfld.long 0x04 12. ",Addres bit 0 Mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " WAIT[3:0] ,Memory timing control fields" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 6.--7. " BCYC[1:0] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BSIZE ,Burst access size in beats" "2,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " PS ,Port size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x04 1. " OE_CTRL ,Read cycle mode" "OE,CS"
|
|
bitfld.long 0x04 0. " WE_CTRL ,Write cycle mode" "WE,CS"
|
|
line.long 0x08 "OR1B,Option Register B"
|
|
bitfld.long 0x08 4.--5. " WAIT[5:4] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x08 2.--3. " BCYC[3:2] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " SYNC ,TA_ input synchronizer" "Reserved,1-stage,2-stage,?..."
|
|
group.long 0x30++0x0B
|
|
line.long 0x00 "BAR2,Base Address register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BASE ,Base address"
|
|
bitfld.long 0x00 10.--11. " PGSIZE ,Peripheral page size" "64,32,16,8"
|
|
bitfld.long 0x00 8.--9. " DMODE ,DRAM configuration mode" "FP DRAM,EDO DRAM,SDRAM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMUXS ,DRAM address multiplexer select" "Internal,External"
|
|
bitfld.long 0x00 6. " EXTTA ,External TA_ configuration" "Internally,Externally"
|
|
bitfld.long 0x00 5. " DMUXM ,DRAM internal address multiplexer mode" "10 CAS,8 CAS"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,Force BCLK at end of memory cycle" "Low,High"
|
|
bitfld.long 0x00 3. " DRSEL ,Enable DRAM mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BURST ,Burst memory cycle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WP ,Write-protect the chip select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " V ,Valid bit" "Disabled,Enabled"
|
|
line.long 0x04 "OR2A,Option Register A"
|
|
bitfld.long 0x04 31. " Mask[19:0] ,Addres bit 19 Mask" "0,1"
|
|
bitfld.long 0x04 30. ",Addres bit 18 Mask" "0,1"
|
|
bitfld.long 0x04 29. ",Addres bit 17 Mask" "0,1"
|
|
bitfld.long 0x04 28. ",Addres bit 16 Mask" "0,1"
|
|
bitfld.long 0x04 27. ",Addres bit 15 Mask" "0,1"
|
|
bitfld.long 0x04 26. ",Addres bit 14 Mask" "0,1"
|
|
bitfld.long 0x04 25. ",Addres bit 13 Mask" "0,1"
|
|
bitfld.long 0x04 24. ",Addres bit 12 Mask" "0,1"
|
|
bitfld.long 0x04 23. ",Addres bit 11 Mask" "0,1"
|
|
bitfld.long 0x04 22. ",Addres bit 10 Mask" "0,1"
|
|
bitfld.long 0x04 21. ",Addres bit 9 Mask" "0,1"
|
|
bitfld.long 0x04 20. ",Addres bit 8 Mask" "0,1"
|
|
bitfld.long 0x04 19. ",Addres bit 7 Mask" "0,1"
|
|
bitfld.long 0x04 18. ",Addres bit 6 Mask" "0,1"
|
|
bitfld.long 0x04 17. ",Addres bit 5 Mask" "0,1"
|
|
bitfld.long 0x04 16. ",Addres bit 4 Mask" "0,1"
|
|
bitfld.long 0x04 15. ",Addres bit 3 Mask" "0,1"
|
|
bitfld.long 0x04 14. ",Addres bit 2 Mask" "0,1"
|
|
bitfld.long 0x04 13. ",Addres bit 1 Mask" "0,1"
|
|
bitfld.long 0x04 12. ",Addres bit 0 Mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " WAIT[3:0] ,Memory timing control fields" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 6.--7. " BCYC[1:0] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BSIZE ,Burst access size in beats" "2,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " PS ,Port size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x04 1. " OE_CTRL ,Read cycle mode" "OE,CS"
|
|
bitfld.long 0x04 0. " WE_CTRL ,Write cycle mode" "WE,CS"
|
|
line.long 0x08 "OR2B,Option Register B"
|
|
bitfld.long 0x08 4.--5. " WAIT[5:4] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x08 2.--3. " BCYC[3:2] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " SYNC ,TA_ input synchronizer" "Reserved,1-stage,2-stage,?..."
|
|
group.long 0x40++0x0B
|
|
line.long 0x00 "BAR3,Base Address register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BASE ,Base address"
|
|
bitfld.long 0x00 10.--11. " PGSIZE ,Peripheral page size" "64,32,16,8"
|
|
bitfld.long 0x00 8.--9. " DMODE ,DRAM configuration mode" "FP DRAM,EDO DRAM,SDRAM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMUXS ,DRAM address multiplexer select" "Internal,External"
|
|
bitfld.long 0x00 6. " EXTTA ,External TA_ configuration" "Internally,Externally"
|
|
bitfld.long 0x00 5. " DMUXM ,DRAM internal address multiplexer mode" "10 CAS,8 CAS"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,Force BCLK at end of memory cycle" "Low,High"
|
|
bitfld.long 0x00 3. " DRSEL ,Enable DRAM mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BURST ,Burst memory cycle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WP ,Write-protect the chip select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " V ,Valid bit" "Disabled,Enabled"
|
|
line.long 0x04 "OR3A,Option Register A"
|
|
bitfld.long 0x04 31. " Mask[19:0] ,Addres bit 19 Mask" "0,1"
|
|
bitfld.long 0x04 30. ",Addres bit 18 Mask" "0,1"
|
|
bitfld.long 0x04 29. ",Addres bit 17 Mask" "0,1"
|
|
bitfld.long 0x04 28. ",Addres bit 16 Mask" "0,1"
|
|
bitfld.long 0x04 27. ",Addres bit 15 Mask" "0,1"
|
|
bitfld.long 0x04 26. ",Addres bit 14 Mask" "0,1"
|
|
bitfld.long 0x04 25. ",Addres bit 13 Mask" "0,1"
|
|
bitfld.long 0x04 24. ",Addres bit 12 Mask" "0,1"
|
|
bitfld.long 0x04 23. ",Addres bit 11 Mask" "0,1"
|
|
bitfld.long 0x04 22. ",Addres bit 10 Mask" "0,1"
|
|
bitfld.long 0x04 21. ",Addres bit 9 Mask" "0,1"
|
|
bitfld.long 0x04 20. ",Addres bit 8 Mask" "0,1"
|
|
bitfld.long 0x04 19. ",Addres bit 7 Mask" "0,1"
|
|
bitfld.long 0x04 18. ",Addres bit 6 Mask" "0,1"
|
|
bitfld.long 0x04 17. ",Addres bit 5 Mask" "0,1"
|
|
bitfld.long 0x04 16. ",Addres bit 4 Mask" "0,1"
|
|
bitfld.long 0x04 15. ",Addres bit 3 Mask" "0,1"
|
|
bitfld.long 0x04 14. ",Addres bit 2 Mask" "0,1"
|
|
bitfld.long 0x04 13. ",Addres bit 1 Mask" "0,1"
|
|
bitfld.long 0x04 12. ",Addres bit 0 Mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " WAIT[3:0] ,Memory timing control fields" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 6.--7. " BCYC[1:0] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BSIZE ,Burst access size in beats" "2,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " PS ,Port size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x04 1. " OE_CTRL ,Read cycle mode" "OE,CS"
|
|
bitfld.long 0x04 0. " WE_CTRL ,Write cycle mode" "WE,CS"
|
|
line.long 0x08 "OR3B,Option Register B"
|
|
bitfld.long 0x08 4.--5. " WAIT[5:4] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x08 2.--3. " BCYC[3:2] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " SYNC ,TA_ input synchronizer" "Reserved,1-stage,2-stage,?..."
|
|
group.long 0x50++0x0B
|
|
line.long 0x00 "BAR4,Base Address register"
|
|
hexmask.long 0x00 12.--31. 0x1000 " BASE ,Base address"
|
|
bitfld.long 0x00 10.--11. " PGSIZE ,Peripheral page size" "64,32,16,8"
|
|
bitfld.long 0x00 8.--9. " DMODE ,DRAM configuration mode" "FP DRAM,EDO DRAM,SDRAM,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMUXS ,DRAM address multiplexer select" "Internal,External"
|
|
bitfld.long 0x00 6. " EXTTA ,External TA_ configuration" "Internally,Externally"
|
|
bitfld.long 0x00 5. " DMUXM ,DRAM internal address multiplexer mode" "10 CAS,8 CAS"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLE ,Force BCLK at end of memory cycle" "Low,High"
|
|
bitfld.long 0x00 3. " DRSEL ,Enable DRAM mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BURST ,Burst memory cycle enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " WP ,Write-protect the chip select" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " V ,Valid bit" "Disabled,Enabled"
|
|
line.long 0x04 "OR4A,Option Register A"
|
|
bitfld.long 0x04 31. " Mask[19:0] ,Addres bit 19 Mask" "0,1"
|
|
bitfld.long 0x04 30. ",Addres bit 18 Mask" "0,1"
|
|
bitfld.long 0x04 29. ",Addres bit 17 Mask" "0,1"
|
|
bitfld.long 0x04 28. ",Addres bit 16 Mask" "0,1"
|
|
bitfld.long 0x04 27. ",Addres bit 15 Mask" "0,1"
|
|
bitfld.long 0x04 26. ",Addres bit 14 Mask" "0,1"
|
|
bitfld.long 0x04 25. ",Addres bit 13 Mask" "0,1"
|
|
bitfld.long 0x04 24. ",Addres bit 12 Mask" "0,1"
|
|
bitfld.long 0x04 23. ",Addres bit 11 Mask" "0,1"
|
|
bitfld.long 0x04 22. ",Addres bit 10 Mask" "0,1"
|
|
bitfld.long 0x04 21. ",Addres bit 9 Mask" "0,1"
|
|
bitfld.long 0x04 20. ",Addres bit 8 Mask" "0,1"
|
|
bitfld.long 0x04 19. ",Addres bit 7 Mask" "0,1"
|
|
bitfld.long 0x04 18. ",Addres bit 6 Mask" "0,1"
|
|
bitfld.long 0x04 17. ",Addres bit 5 Mask" "0,1"
|
|
bitfld.long 0x04 16. ",Addres bit 4 Mask" "0,1"
|
|
bitfld.long 0x04 15. ",Addres bit 3 Mask" "0,1"
|
|
bitfld.long 0x04 14. ",Addres bit 2 Mask" "0,1"
|
|
bitfld.long 0x04 13. ",Addres bit 1 Mask" "0,1"
|
|
bitfld.long 0x04 12. ",Addres bit 0 Mask" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " WAIT[3:0] ,Memory timing control fields" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 6.--7. " BCYC[1:0] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x04 4.--5. " BSIZE ,Burst access size in beats" "2,4,8,16"
|
|
textline " "
|
|
bitfld.long 0x04 2.--3. " PS ,Port size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x04 1. " OE_CTRL ,Read cycle mode" "OE,CS"
|
|
bitfld.long 0x04 0. " WE_CTRL ,Write cycle mode" "WE,CS"
|
|
line.long 0x08 "OR4B,Option Register B"
|
|
bitfld.long 0x08 4.--5. " WAIT[5:4] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x08 2.--3. " BCYC[3:2] ,Memory timing control fields" "0,1,2,3"
|
|
bitfld.long 0x08 0.--1. " SYNC ,TA_ input synchronizer" "Reserved,1-stage,2-stage,?..."
|
|
width 0xB
|
|
tree.end
|
|
tree.open "DMA Module"
|
|
tree "DMA Channel 1A"
|
|
base ad:0xFF900000
|
|
width 12.
|
|
if (((d.l(ad:0xFF900010))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_1A,DMA Channel 1A Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_1A,DMA Channel 1A Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_1A,DMA Channel 1A Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_1A,DMA Channel 1A Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL1A,DMA Channel 1A Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 1A enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 1A abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN1A,DMA Channel 1A Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 1B"
|
|
base ad:0xFF900020
|
|
width 12.
|
|
if (((d.l(ad:0xFF900030))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_1B,DMA Channel 1B Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_1B,DMA Channel 1B Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_1B,DMA Channel 1B Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_1B,DMA Channel 1B Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL1B,DMA Channel 1B Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 1B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 1B abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN1B,DMA Channel 1B Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 1C"
|
|
base ad:0xFF900040
|
|
width 12.
|
|
if (((d.l(ad:0xFF900050))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_1C,DMA Channel 1C Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_1C,DMA Channel 1C Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_1C,DMA Channel 1C Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_1C,DMA Channel 1C Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL1C,DMA Channel 1C Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 1C enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 1C abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN1C,DMA Channel 1C Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 1D"
|
|
base ad:0xFF900060
|
|
width 12.
|
|
if (((d.l(ad:0xFF900070))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_1D,DMA Channel 1D Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_1D,DMA Channel 1D Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_1D,DMA Channel 1D Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_1D,DMA Channel 1D Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL1D,DMA Channel 1D Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 1D enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 1D abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN1D,DMA Channel 1D Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 2"
|
|
base ad:0xFF900080
|
|
width 12.
|
|
if (((d.l(ad:0xFF900090))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_2,DMA Channel 2 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_2,DMA Channel 2 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_2,DMA Channel 2 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_2,DMA Channel 2 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL2,DMA Channel 2 Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 2 abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN2,DMA Channel 2 Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 3"
|
|
base ad:0xFF9000A0
|
|
width 12.
|
|
if (((d.l(ad:0xFF9000B0))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_3,DMA Channel 3 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_3,DMA Channel 3 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_3,DMA Channel 3 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_3,DMA Channel 3 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL3,DMA Channel 3 Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 3 abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN3,DMA Channel 3 Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 4"
|
|
base ad:0xFF9000C0
|
|
width 12.
|
|
if (((d.l(ad:0xFF9000D0))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_4,DMA Channel 4 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_4,DMA Channel 4 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_4,DMA Channel 4 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_4,DMA Channel 4 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL4,DMA Channel 4 Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 4 abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN4,DMA Channel 4 Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 5"
|
|
base ad:0xFF9000E0
|
|
width 12.
|
|
if (((d.l(ad:0xFF9000F0))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_5,DMA Channel 5 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_5,DMA Channel 5 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_5,DMA Channel 5 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_5,DMA Channel 5 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL5,DMA Channel 5 Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 5 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 5 abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN5,DMA Channel 5 Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 6"
|
|
base ad:0xFF900100
|
|
width 12.
|
|
if (((d.l(ad:0xFF900110))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_6,DMA Channel 6 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_6,DMA Channel 6 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_6,DMA Channel 6 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_6,DMA Channel 6 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL6,DMA Channel 6 Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 6 abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN6,DMA Channel 6 Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 7"
|
|
base ad:0xFF900120
|
|
width 12.
|
|
if (((d.l(ad:0xFF900130))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_7,DMA Channel 7 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_7,DMA Channel 7 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_7,DMA Channel 7 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_7,DMA Channel 7 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL7,DMA Channel 7 Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 7 abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN7,DMA Channel 7 Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 8"
|
|
base ad:0xFF900140
|
|
width 12.
|
|
if (((d.l(ad:0xFF900150))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_8,DMA Channel 8 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_8,DMA Channel 8 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_8,DMA Channel 8 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_8,DMA Channel 8 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL8,DMA Channel 8 Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 8 abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN8,DMA Channel 8 Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 9"
|
|
base ad:0xFF900160
|
|
width 12.
|
|
if (((d.l(ad:0xFF900170))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_9,DMA Channel 9 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_9,DMA Channel 9 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_9,DMA Channel 9 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_9,DMA Channel 9 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL9,DMA Channel 9 Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 9 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 9 abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN9,DMA Channel 9 Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 10"
|
|
base ad:0xFF900180
|
|
width 12.
|
|
if (((d.l(ad:0xFF900190))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_10,DMA Channel 10 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_10,DMA Channel 10 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_10,DMA Channel 10 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_10,DMA Channel 10 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL10,DMA Channel 10 Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 10 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 10 abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN10,DMA Channel 10 Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 11"
|
|
base ad:0xFF9001A0
|
|
width 12.
|
|
if (((d.l(ad:0xFF9001B0))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_11,DMA Channel 11 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_11,DMA Channel 11 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_11,DMA Channel 11 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_11,DMA Channel 11 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL11,DMA Channel 11 Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 11 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 11 abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN11,DMA Channel 11 Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 12"
|
|
base ad:0xFF9001C0
|
|
width 12.
|
|
if (((d.l(ad:0xFF9001D0))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_12,DMA Channel 12 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_12,DMA Channel 12 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_12,DMA Channel 12 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_12,DMA Channel 12 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL12,DMA Channel 12 Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 12 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 12 abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN12,DMA Channel 12 Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree "DMA Channel 13"
|
|
base ad:0xFF9001E0
|
|
width 12.
|
|
if (((d.l(ad:0xFF9001F0))&0xC000000)==0x8000000)
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_13,DMA Channel 13 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,Tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_13,DMA Channel 13 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
line.long 0x08 "DBUFFP,Destination buffer pointer"
|
|
else
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "DMABDP1_13,DMA Channel 13 Buffer Descriptor Pointer"
|
|
bitfld.long 0x00 31. " W ,Warp bit" "Not wrapped,Wrapped"
|
|
bitfld.long 0x00 30. " I ,Tells the DMA controller to issue an interrupt to the CPU" "Not caused,Caused"
|
|
bitfld.long 0x00 29. " L ,tells the DMA controller that this buffer descriptor is the last descriptor" "Not caused,Caused"
|
|
textline " "
|
|
hexmask.long 0x00 0.--28. 1. " SOBUPO ,Source buffer pointer"
|
|
line.long 0x04 "DMABDP2_13,DMA Channel 13 Buffer Descriptor Pointer"
|
|
hexmask.long.word 0x04 16.--31. 1. " STATUS ,Store transmit and receive status words"
|
|
bitfld.long 0x04 15. " F ,fly-by operations" "Masked,No masked"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLENGTH ,Buffer length"
|
|
endif
|
|
width 12.
|
|
group.long 0x10++0x07
|
|
line.long 0x00 "DMACTRL13,DMA Channel 13 Control Register"
|
|
bitfld.long 0x00 31. " CE ,Channel 13 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " CA ,Channel 13 abort" "Not aborted,Aborted"
|
|
bitfld.long 0x00 28.--29. " BB ,Bus bandwidth" "100%,75%,50%,25%"
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " MODE ,Fly-by mode" "Fly_by Write,Fly_by Read,Memory-to-memory,?..."
|
|
bitfld.long 0x00 24.--25. " BTE ,Burst transfer enable" "1 operand,2 operands,4 operands,?..."
|
|
textline " "
|
|
bitfld.long 0x00 23. " REQ ,Channel request source" "Internal,External"
|
|
bitfld.long 0x00 21. " SINC_ ,Source address increment" "Increment,Not increment"
|
|
bitfld.long 0x00 20. " DINC_ ,Destination address increment" "Increment,Not increment"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " SIZE ,Data operand size" "32bit,16bit,8bit,?..."
|
|
bitfld.long 0x00 10.--15. " STATE ,Current DMA channel state" "IDLE,Load source buffer address,Reserved,Reserved,Load destination buffer address,Reserved,Reserved,Reserved,First operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory-to-memory second operand,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Update buffer description,?..."
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " INDEX ,Index"
|
|
line.long 0x04 "DMASINTEN13,DMA Channel 13 Status and Interrupt Enable Register"
|
|
width 12.
|
|
eventfld.long 0x04 31. " NCIP ,Normal completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 30. " ECIP ,Error completion interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 29. " NRIP ,Buffer not ready interrupt pending" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x04 28. " CAIP ,Channel abort interrupt pending" "Not pending,Pending"
|
|
eventfld.long 0x04 27. " PCIP ,Premature complete interrupt pending" "Not pending,Pending"
|
|
bitfld.long 0x04 24. " PCIE ,Premature complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " NCIE ,Normal completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " ECIE ,Error completion interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 21. " NRIE ,Buffer not ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 20. " CAIE ,Channel abort interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 19. " WRAP ,Debug field that indicates the last descriptor in the descriptor list" "Not wrapped,Wrapped"
|
|
bitfld.long 0x04 18. " IDONE ,Debug field that indicates the status of the DONE signal" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x04 17. " LAST ,Debug field that indicates the last buffer descriptor in the current data frame" "Not last,Last"
|
|
bitfld.long 0x04 16. " FULL ,Debug field that indicates the status of the F bit from the current DMA buffer descriptor" "Not full,Full"
|
|
hexmask.long.word 0x04 0.--14. 1. " BLEN ,Debug field that indicates the current byte transfer count"
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
tree "EFE (Ethernet Module)"
|
|
base ad:0xFF800000
|
|
width 7.
|
|
if ((((d.l(ad:0xFF800000))&0xC000)==0xC000)||(((d.l(ad:0xFF800000))&0xC000)==0x8000))
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "EGCR,Ethernet General Control Register"
|
|
width 7.
|
|
bitfld.long 0x00 31. " ERX ,Enable receive FIFO" "Reset,Enabled"
|
|
bitfld.long 0x00 30. " ERXDMA ,Enable receive DMA" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ERXLNG ,Accept long (>1520 bytes [MAXF setting]) receive packets" "No accepted,Accepted"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ERXSHT ,Accept short (<64) receive frames" "Not accepted,Accepted"
|
|
bitfld.long 0x00 27. " ERXREG ,Enable Receive Data register ready interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ERFIFOH ,Enable receive data FIFO half full interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ERXBR ,Enable receive buffer ready interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ERXBAD ,Accept bad receive packets" "Not accepted,Accepted"
|
|
bitfld.long 0x00 23. " ETX ,Enable TX packet processing" "Reset,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ETXDMA ,Enable transmit DMA" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " ETXWM ,Transmit FIFO water mark before transmit start" "25% FIFO full,50% FIFO full,75% FIFO full,?..."
|
|
bitfld.long 0x00 19. " ETXREG ,Enable Transmit Data register ready interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " ETFIFOH ,Enable transmit data FIFO half empty interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ETXBC ,Enable transmit buffer complete interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EFULLD ,Enable full-duplex operation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODE ,Ethernet interface mode" "10/100 Mbps MII mode,Reserved,10 Mbps Level 1 ENDEC mode,10 Mbps SEEQ ENDEC mode"
|
|
bitfld.long 0x00 12. " RXCINV ,Invert the receive clock input" "No inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXCINV ,Invert the transmit clock input" "No inverted,Inverted"
|
|
bitfld.long 0x00 10. " pNA ,pSOS pNA buffer descriptors" "Standard receiver format,pSOS pNA receiver format"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MAC_RESET ,MAC software reset" "Restored,Reset"
|
|
bitfld.long 0x00 8. " ITXA ,Insert transmit source address" "TX_FIFO,MAC Ethernet address"
|
|
textline " "
|
|
bitfld.long 0x00 7. " PDN ,Inverted state of PDN bit, open collector" "Low,High"
|
|
bitfld.long 0x00 6. " AUI_TP0 ,State of AUI_TP[0] bit" "Low,High"
|
|
bitfld.long 0x00 5. " AUI_TP1 ,State of AUI_TP[1] bit" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LNK_DIS ,State of LNK_DIS_ bit" "Low,High"
|
|
bitfld.long 0x00 3. " LPBK ,State of LPBK bit" "Low,High"
|
|
bitfld.long 0x00 2. " UTP_STP ,State of UTP_STP bit" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " EXINT ,External interface mode" "MII normal operation,TP-PMD mode,10 Mbit mode,?..."
|
|
width 7.
|
|
line.long 0x04 "EGSR,Ethernet General Status register"
|
|
bitfld.long 0x04 28.--29. " RXFDB ,Receive FIFO data available" "Full-word,One byte,Half-word,Three bytes"
|
|
bitfld.long 0x04 27. " RXREGR ,Receive register ready" "Not ready,Ready"
|
|
bitfld.long 0x04 26. " RXFIFOH ,Receive FIFO half full" "Not full,Full"
|
|
textline " "
|
|
eventfld.long 0x04 25. " RXBR ,Receive buffer ready" "Not ready,Ready"
|
|
bitfld.long 0x04 24. " RXSKIP ,Receive buffer skip" "No skiped,Skiped"
|
|
bitfld.long 0x04 19. " TXREGE ,Transmit register empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 18. " TXFIFOH ,Transmit FIFO half empty" "Not empty,Empty"
|
|
eventfld.long 0x04 17. " TXBC ,Transmit buffer complete" "Not Complete,Complete"
|
|
bitfld.long 0x04 16. " TXFIFOE ,Transmit FIFO empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 15. " RXD2 ,ENDEC PHY status" "Low,High"
|
|
bitfld.long 0x04 13. " RXD1 ,ENDEC PHY status" "Low,High"
|
|
bitfld.long 0x04 12. " RXD3 ,ENDEC PHY status" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x04 11. " RXER ,ENDEC PHY status" "Low,High"
|
|
bitfld.long 0x04 10. " RXDV ,ENDEC PHY status" "Low,High"
|
|
else
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "EGCR,Ethernet General Control Register"
|
|
width 7.
|
|
bitfld.long 0x00 31. " ERX ,Enable receive FIFO" "Reset,Enabled"
|
|
bitfld.long 0x00 30. " ERXDMA ,Enable receive DMA" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " ERXLNG ,Accept long (>1520 bytes [MAXF setting]) receive packets" "No accepted,Accepted"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ERXSHT ,Accept short (<64) receive frames" "Not accepted,Accepted"
|
|
bitfld.long 0x00 27. " ERXREG ,Enable Receive Data register ready interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " ERFIFOH ,Enable receive data FIFO half full interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ERXBR ,Enable receive buffer ready interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " ERXBAD ,Accept bad receive packets" "Not accepted,Accepted"
|
|
bitfld.long 0x00 23. " ETX ,Enable TX packet processing" "Reset,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ETXDMA ,Enable transmit DMA" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " ETXWM ,Transmit FIFO water mark before transmit start" "25% FIFO full,50% FIFO full,75% FIFO full,?..."
|
|
bitfld.long 0x00 19. " ETXREG ,Enable Transmit Data register ready interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " ETFIFOH ,Enable transmit data FIFO half empty interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ETXBC ,Enable transmit buffer complete interrupt" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EFULLD ,Enable full-duplex operation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MODE ,Ethernet interface mode" "10/100 Mbps MII mode,Reserved,10 Mbps Level 1 ENDEC mode,10 Mbps SEEQ ENDEC mode"
|
|
bitfld.long 0x00 12. " RXCINV ,Invert the receive clock input" "No inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TXCINV ,Invert the transmit clock input" "No inverted,Inverted"
|
|
bitfld.long 0x00 10. " pNA ,pSOS pNA buffer descriptors" "Standard receiver format,pSOS pNA receiver format"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MAC_RESET ,MAC software reset" "Restored,Reset"
|
|
bitfld.long 0x00 8. " ITXA ,Insert transmit source address" "TX_FIFO,MAC Ethernet address"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " EXINT ,External interface mode" "MII normal operation,TP-PMD mode,10 Mbit mode,?..."
|
|
width 7.
|
|
line.long 0x04 "EGSR,Ethernet General Status register"
|
|
bitfld.long 0x04 28.--29. " RXFDB ,Receive FIFO data available" "Full-word,One byte,Half-word,Three bytes"
|
|
bitfld.long 0x04 27. " RXREGR ,Receive register ready" "Not ready,Ready"
|
|
bitfld.long 0x04 26. " RXFIFOH ,Receive FIFO half full" "Not full,Full"
|
|
textline " "
|
|
eventfld.long 0x04 25. " RXBR ,Receive buffer ready" "Not ready,Ready"
|
|
bitfld.long 0x04 24. " RXSKIP ,Receive buffer skip" "No skiped,Skiped"
|
|
bitfld.long 0x04 19. " TXREGE ,Transmit register empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.long 0x04 18. " TXFIFOH ,Transmit FIFO half empty" "Not empty,Empty"
|
|
eventfld.long 0x04 17. " TXBC ,Transmit buffer complete" "Not complete,Complete"
|
|
bitfld.long 0x04 16. " TXFIFOE ,Transmit FIFO empty" "Not empty,Empty"
|
|
endif
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "FIFO,Ethernet FIFO Data register"
|
|
in
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "FIFOL,Ethernet FIFO Data register"
|
|
in
|
|
rgroup.long 0x10++0x07
|
|
line.long 0x00 "ETSR,Ethernet Transmit Status Register"
|
|
bitfld.long 0x00 15. " TXOK ,Frame transmitted OK" "Not ok,Ok"
|
|
bitfld.long 0x00 14. " TXBR ,Broadcast frame transmitted" "Not broadcast,Broadcast"
|
|
bitfld.long 0x00 13. " TXMC ,Multicast frame transmitted" "Not multicast,Multicast"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TXAL ,TX abort - late collision" "Not aborted,Aborted"
|
|
bitfld.long 0x00 11. " TXAED ,TX abort - excessive deferral" "Not aborted,Aborted"
|
|
bitfld.long 0x00 10. " TXAEC ,TX abort - excessive collisions" "Not aborted,Aborted"
|
|
textline " "
|
|
bitfld.long 0x00 9. " TXAUR ,TX abort - underrun" "Not aborted,Aborted"
|
|
bitfld.long 0x00 8. " TXAJ ,TX abort - jumbo" "Not aborted,Aborted"
|
|
bitfld.long 0x00 6. " TXDEF ,Transmit frame deferred" "Not deferred,Deferred"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TXCRC ,Transmit CRC error" "No error,Error"
|
|
bitfld.long 0x00 0.--3. " TXCOLC ,Transmit collision count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x04 "ERSR,Ethernet Receive Status register"
|
|
hexmask.long.word 0x04 16.--31. 1. " RXSIZE ,Receive buffer size in bytes"
|
|
bitfld.long 0x04 15. " RXCE ,Receive carrier event previously seen" "Not active,Active"
|
|
bitfld.long 0x04 14. " RXDV ,Receive data violation event previously seen" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " RXOK ,Receive frame OK" "Not valid,Valid"
|
|
bitfld.long 0x04 12. " RXBR ,Receive broadcast frame" "Not valid,Valid"
|
|
bitfld.long 0x04 11. " RXMC ,Receive multicast frame" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 10. " RXCRC ,Receive packet has CRC error" "Not valid,Valid"
|
|
bitfld.long 0x04 9. " RXDR ,Receive frame has dribble bits" "Not received,Received"
|
|
bitfld.long 0x04 8. " RXCV ,Receive packet has code violation" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.long 0x04 7. " RXLNG ,Receive packet is too long" "Correct,Too long"
|
|
bitfld.long 0x04 6. " RXSHT ,Receive frame is too short" "Correct,Too short"
|
|
bitfld.long 0x04 5. " ROVER ,Receive overflow" "Not occurred,Occurred"
|
|
group.long 0x400++0x2F
|
|
line.long 0x00 "MAC1,MAC Configuration register 1"
|
|
bitfld.long 0x00 15. " SRST ,Soft reset" "No reset,Reset"
|
|
bitfld.long 0x00 14. " SIMRST ,Simulation reset" "No reset,Reset"
|
|
bitfld.long 0x00 11. " RPEMCSR ,Reset PEMCS/RX" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RPERFUN ,Reset PERFUN" "No reset,Reset"
|
|
bitfld.long 0x00 9. " RPEMCST ,Reset PEMCS/TX" "No reset,Reset"
|
|
bitfld.long 0x00 8. " RPETFUN ,Reset PETFUN" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOOPBK ,Internal loopback" "Normal,Loopback"
|
|
bitfld.long 0x00 3. " TXFLOW ,TX flow control" "By Blocks,By MAC"
|
|
bitfld.long 0x00 2. " RXFLOW ,TX flow control" "Ignore,Acts on"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PALLRX ,Pass ALL receive frames" "Not accepted,Accepted"
|
|
bitfld.long 0x00 0. " RXEN ,Receive enable" "Disabled,Enabled"
|
|
line.long 0x04 "MAC2,MAC Configuration Register 2"
|
|
bitfld.long 0x04 14. " EDEFER ,Excess deferral" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " BACKP ,Backpressure/NO back off" "Backpressure,NO back off"
|
|
bitfld.long 0x04 12. " NOBO ,No backoff" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x04 9. " LONGP ,Long preamble enforcement" "Any length,<=12 bytes"
|
|
bitfld.long 0x04 8. " PUREP ,Pure preamble enforcement" "No preamble,Preamble"
|
|
bitfld.long 0x04 7. " AUTOP ,Auto detect pad enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 6. " VLANP ,VLAN pad enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 5. " PADEN ,Pad/CRC enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " CRCEN ,CRC enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " DELCRC ,Delayed CRC" "Zero bytes,Four bytes"
|
|
bitfld.long 0x04 2. " HUGE ,Huge frame enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " FLENC ,Frame length checking" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 0. " FULLD ,Full-duplex" "Half-duplex,Full-duplex"
|
|
line.long 0x08 "IPGT,Back-to-Back Inter-Packet-Gap Register"
|
|
hexmask.long.byte 0x08 0.--6. 1. " IPGT ,Back-to-back inter-packet-gap"
|
|
line.long 0x0C "IPGR,Non Back-to-Back Inter-Packet-Gap Register"
|
|
hexmask.long.byte 0x0c 8.--14. 1. " IPGR1 ,Non back-to-back inter-packet-gap part 1"
|
|
hexmask.long.byte 0x0c 0.--6. 1. " IPGR2 ,Non back-to-back inter-packet-gap part 2"
|
|
line.long 0x10 "CLRT,Collision Window/Retry Register"
|
|
hexmask.long.byte 0x10 8.--13. 1. " CWIN ,Collision window"
|
|
hexmask.long.byte 0x10 0.--3. 1. " RETX ,Retransmission maximum"
|
|
line.long 0x14 "MAXF,Maximum Frame Register"
|
|
hexmask.long.word 0x14 0.--15. 1. " MAXF ,Maximum frame length"
|
|
line.long 0x18 "SUPP,PHY Support register"
|
|
bitfld.long 0x18 7. " RPE100X ,Reset PE100X module" "No reset,Reset"
|
|
bitfld.long 0x18 6. " FORCEQ ,Force quiet" "Normal,Quieted"
|
|
bitfld.long 0x18 5. " NOCIPH ,No cipher" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 4. " DLINKF ,Disable link fail" "Normal,Disabled"
|
|
bitfld.long 0x18 3. " RPE10T ,Reset PE10T module" "No reset,Reset"
|
|
bitfld.long 0x18 1. " JABBER ,Enable Jabber protection" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 0. " BITMODE ,Bit mode" "Disabled,Enabled"
|
|
line.long 0x1C "TEST,Test register"
|
|
bitfld.long 0x1C 2. " TBACK ,Test backpressure" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " TPAUSE ,Test pause" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " SPQ ,Shortcut pause quanta" "Disabled,Enabled"
|
|
line.long 0x20 "MCFG,MII Management Configuration register"
|
|
width 7.
|
|
bitfld.long 0x20 15. " RMIIM ,Reset MII management" "No reset,Reset"
|
|
bitfld.long 0x20 2.--4. " CLKS ,Clock select" "SYS_CLK/4,SYS_CLK/4,SYS_CLK/6,SYS_CLK/8,SYS_CLK/10,SYS_CLK/14,SYS_CLK/20,SYS_CLK/28"
|
|
bitfld.long 0x20 1. " SPRE ,Suppress preamble" "Normal,Without the 32-bit preamble"
|
|
textline " "
|
|
bitfld.long 0x20 0. " SCANI ,Scan increment (single scan for read data)" "Disabled,Enabled"
|
|
width 7.
|
|
line.long 0x24 "MCMD,MII Management Command register"
|
|
bitfld.long 0x24 1. " SCAN ,Automatically scan for read data" "Disabled,Enabled"
|
|
bitfld.long 0x24 0. " READ ,Single scan for read data" "Disabled,Enabled"
|
|
line.long 0x28 "MADR,MII Management Address register"
|
|
hexmask.long.byte 0x28 8.--12. 1. " DADR ,MII PHY device address"
|
|
hexmask.long.byte 0x28 0.--4. 1. " RADR ,MII PHY register address"
|
|
line.long 0x2C "MWDT,MII Management Write Data register"
|
|
hexmask.long.word 0x2C 0.--15. 1. " MWTD ,MII write data"
|
|
rgroup.long 0x430++0x0B
|
|
line.long 0x00 "MRDD,MII Management Read Data register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MRDD ,MII read data"
|
|
line.long 0x04 "MIND,MII Management Indicators register"
|
|
bitfld.long 0x04 2. " NVALID ,Read data not valid" "Valid,Not Valid"
|
|
bitfld.long 0x04 1. " SCAN ,Automatically scan for read data in progress" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " BUSY ,MII interface BUSY with read/write operation" "Not busy,Busy"
|
|
line.long 0x08 "SMII,SMII Status register"
|
|
bitfld.long 0x08 4. " CLASH ,MAC-to-MAC with PHY" "Normal mode,MAC-to-MAC mode"
|
|
bitfld.long 0x08 3. " JABBER ,Jabber condition present" "Not present,Present"
|
|
bitfld.long 0x08 2. " LINK ,Link OK" "Error,Link OK"
|
|
textline " "
|
|
bitfld.long 0x08 1. " DUPLEX ,Full-duplex operation" "Half-duplex,Full-duplex"
|
|
bitfld.long 0x08 0. " SPEED ,100 Mbps" "10 Mbps,100 Mbps"
|
|
group.word 0x440++0x0B
|
|
line.word 0x00 "SA1,Station Address Register 1"
|
|
hexmask.word.byte 0x00 8.--15. 0x1 " OCTET1 ,Station address octet 1"
|
|
hexmask.word.byte 0x00 0.--7. 0x1 " OCTET2 ,Station address octet 2"
|
|
line.word 0x04 "SA2,Station Address Register 2"
|
|
hexmask.word.byte 0x04 8.--15. 0x1 " OCTET3 ,Station address octet 3"
|
|
hexmask.word.byte 0x04 0.--7. 0x1 " OCTET4 ,Station address octet 4"
|
|
line.word 0x08 "SA3,Station Address Register 3"
|
|
hexmask.word.byte 0x08 8.--15. 0x1 " OCTET5 ,Station address octet 5"
|
|
hexmask.word.byte 0x08 0.--7. 0x1 " OCTET6 ,Station address octet 6"
|
|
group.long 0x5C0++0x03
|
|
line.long 0x00 "SAFR,Station Address Filter register"
|
|
bitfld.long 0x00 3. " PRO ,Enable promiscuous mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PRM ,Accept ALL multicast packets" "Not accepted,Accepted"
|
|
bitfld.long 0x00 1. " PRA ,Accept multicast packets using hash table" "Not accepted,Accepted"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BROAD ,Accept ALL broadcast packets" "Not accepted,Accepted"
|
|
group.long 0x5D0++0x0F
|
|
line.long 0x00 "HT1,Hash Table register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " HT1 ,CRC value 15-0"
|
|
line.long 0x04 "HT2,Hash Table register 2"
|
|
hexmask.long.word 0x04 0.--15. 1. " HT2 ,CRC value 31-16"
|
|
line.long 0x08 "HT3,Hash Table register 3"
|
|
hexmask.long.word 0x08 0.--15. 1. " HT3 ,CRC value 47-32"
|
|
line.long 0x0C "HT4,Hash Table register 4"
|
|
hexmask.long.word 0x0C 0.--15. 1. " HT4 ,CRC value 63-48"
|
|
width 0xB
|
|
tree.end
|
|
tree.open "SER (Serial Controller Module)"
|
|
tree "Channel 1"
|
|
base ad:0xFFD00000
|
|
width 8.
|
|
if (((d.l(ad:0xFFD00000+0x00))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCCRA1,Serial Channel 1 Control Register A"
|
|
bitfld.long 0x00 31. " CE ,Channel enable" "Reset,Enabled"
|
|
bitfld.long 0x00 30. " BRK ,Send break" "Not forced,Forced"
|
|
bitfld.long 0x00 29. " STICKP ,Stick parity" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 28. " EPS ,Even parity select" "Odd parity,Even parity"
|
|
bitfld.long 0x00 27. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " STOP ,Number of stop bits" "1 stop bit,1.5 stop bits"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " WLS ,Data word length select" "5,6,7,8"
|
|
bitfld.long 0x00 23. " CTSTX ,Enable the transmitter with active CTS" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RTSRX ,Enable active RTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RL ,Remote loopback" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LL ,Local loopback" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " OUT1 ,General-purpose output 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OUT2 ,General-purpose output 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DTR ,Data terminal ready active" "Not activated,Activated"
|
|
bitfld.long 0x00 16. " RTS ,Request-to-send active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERXBRT ,Receive break interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ERFE ,Receive framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ERXPE ,Receive parity error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ERXORUN ,Receive overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ERXRDY ,Receive register ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ERXHALF ,Receive FIFO half-full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ERXBC ,Receive buffer closed interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ERXDMA ,Enable receive DMA requests" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ERXDCD ,Change in DCD interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ERXRI ,Change in RI interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ERXDSR ,Change in DSR interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ERXCTS ,Change in CTS interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ETXRDY ,Transmit register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ETXHALF ,Transmit FIFO half-empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ERXBC ,Transmit buffer closed interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ETXDMA ,Enable transmit DMA requests" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCCRA1,Serial Channel 1 Control Register A"
|
|
bitfld.long 0x00 31. " CE ,Channel enable" "Reset,Enabled"
|
|
bitfld.long 0x00 30. " BRK ,Send break" "Not forced,Forced"
|
|
bitfld.long 0x00 29. " STICKP ,Stick parity" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 28. " EPS ,Even parity select" "Odd parity,Even parity"
|
|
bitfld.long 0x00 27. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " STOP ,Number of stop bits" "1 stop bit,2 stop bits"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " WLS ,Data word length select" "5,6,7,8"
|
|
bitfld.long 0x00 23. " CTSTX ,Enable the transmitter with active CTS" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RTSRX ,Enable active RTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RL ,Remote loopback" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LL ,Local loopback" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " OUT1 ,General-purpose output 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OUT2 ,General-purpose output 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DTR ,Data terminal ready active" "Not activated,Activated"
|
|
bitfld.long 0x00 16. " RTS ,Request-to-send active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERXBRT ,Receive break interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ERFE ,Receive framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ERXPE ,Receive parity error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ERXORUN ,Receive overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ERXRDY ,Receive register ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ERXHALF ,Receive FIFO half-full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ERXBC ,Receive buffer closed interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ERXDMA ,Enable receive DMA requests" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ERXDCD ,Change in DCD interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ERXRI ,Change in RI interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ERXDSR ,Change in DSR interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ERXCTS ,Change in CTS interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ETXRDY ,Transmit register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ETXHALF ,Transmit FIFO half-empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ERXBC ,Transmit buffer closed interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ETXDMA ,Enable transmit DMA requests" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
width 8.
|
|
line.long 0x00 "SCCRB1,Serial Channel 1 Control Register B"
|
|
bitfld.long 0x00 31. " RDM1 ,Enable receive data match1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RDM2 ,Enable receive data match2" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RDM3 ,Enable receive data match3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RDM4 ,Enable receive data match4" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RBGT ,Enable receive buffer GAP timer" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RCGT ,Enable receive character GAP timer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE ,SCC mode" "UART,HDLC,SPI master,SPI slave"
|
|
bitfld.long 0x00 19. " BITORDR ,Bit ordering" "Normal,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MAM1 ,Match address mode 1" "Match3/Match4 for each 8-bit address,Match1/Match2 combined for 16-bit address"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MAM2 ,Match address mode 2" "Match3/Match4 for each 8-bit address,Match1/Match2 combined for 16-bit address"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RTSTX ,Enable active RTS only while transmitting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " TENC ,Transmit encoding" "NRZ,NRZB,NRZI-Mark,NRZI-Space,FM0,FM1,Manchester,Differential Manchester"
|
|
bitfld.long 0x00 6.--8. " RDEC ,Receive data encoding" "NRZ,NRZB,NRZI-Mark,NRZI-Space,FM0,FM1,Manchester,Differential Manchester"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " TPL ,Transmit preamble length" "No preamble,8 bits,16 bits,32 bits"
|
|
bitfld.long 0x00 2. " TEND ,Transmitter frame ending" "TXD encoded only for valid data,TXD always encoded"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TPP ,Transmit preamble pattern" "All zeros,Repeating 10s,Repeating 01s,All ones"
|
|
width 8.
|
|
if (((d.l(ad:0xFFD00000+0x08))&0x200)==0x200)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SCSRA1,Serial Channel 1 Status Register A"
|
|
eventfld.long 0x00 31. " Match1 ,Character Match1" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " Match2 ,Character Match2" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " Match3 ,Character Match3" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " Match4 ,Character Match4" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " BGAP ,Buffer GAP timer" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CGAP ,Character GAP timer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " RXFDB ,Receive FIFO data available" "Full-word,One byte,Half-word,Three bytes"
|
|
bitfld.long 0x00 19. " DCD ,Current data carrier detect state" "Inactive,Active"
|
|
bitfld.long 0x00 18. " RI ,Current ring indicator state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSR ,Current data set ready state" "Inactive,Active"
|
|
bitfld.long 0x00 16. " CTS ,Current clear to send state" "Inactive,Active"
|
|
eventfld.long 0x00 15. " RBRK ,Receive break interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " RFE ,Receive framing error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " RPE ,Receive parity error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ROVER ,Receive overrun interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " RRDY ,Receive register ready interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " RHALF ,Receive FIFO half-full interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " RBC ,Receive buffer closed interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RFULL ,Receive FIFO full" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " DCDI ,Change in DCD interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " RII ,Change in RI interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " DSRI ,Change in DSR interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " CTSI ,Change in CTS interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TRDY ,Transmit register empty interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " THALF ,Transmit FIFO half-empty interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " TBC ,Transmit buffer closed interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " TEMPTY ,Transmit FIFO empty" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SCSRA1,Serial Channel 1 Status Register A"
|
|
eventfld.long 0x00 27. " BGAP ,Buffer GAP timer" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CGAP ,Character GAP timer" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " RXFDB ,Receive FIFO data available" "Full-word,One byte,Half-word,Three bytes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DCD ,Current data carrier detect state" "Inactive,Active"
|
|
bitfld.long 0x00 18. " RI ,Current ring indicator state" "Inactive,Active"
|
|
bitfld.long 0x00 17. " DSR ,Current data set ready state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CTS ,Current clear to send state" "Inactive,Active"
|
|
eventfld.long 0x00 15. " RBRK ,Receive break interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " RFE ,Receive framing error interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " RPE ,Receive parity error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ROVER ,Receive overrun interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " RRDY ,Receive register ready interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RHALF ,Receive FIFO half-full interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " RBC ,Receive buffer closed interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " RFULL ,Receive FIFO full" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " DCDI ,Change in DCD interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " RII ,Change in RI interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " DSRI ,Change in DSR interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CTSI ,Change in CTS interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TRDY ,Transmit register empty interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " THALF ,Transmit FIFO half-empty interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TBC ,Transmit buffer closed interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " TEMPTY ,Transmit FIFO empty" "No interrupt,Interrupt"
|
|
endif
|
|
width 8.
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SCBR1,Serial Channel 1 Bit-Rate registers"
|
|
bitfld.long 0x00 31. " EBIT ,Bit-rate generator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TMODE ,Timing mode" "16X mode,Used TDCR/RDCR"
|
|
bitfld.long 0x00 29. " RXSRC ,Receive clock source" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXSRC ,Transmit clock source" "Internal,External"
|
|
bitfld.long 0x00 27. " RXEXT ,Drive receive clock external" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TXEXT ,Drive transmit clock external" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " CLKMUX ,BRG input clock" "defined by F_XTALE,defined by F_SYSCLK,defined by input on OUT1,defined by input on OUT2"
|
|
bitfld.long 0x00 23. " TXCINV ,Transmit clock invert" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXCINV ,Receive clock invert" "Normal,Inverted"
|
|
bitfld.long 0x00 19.--20. " TDCR ,Transmit divide clock rate" "1x,8x,16x,32x"
|
|
bitfld.long 0x00 16.--17. " RDCR ,Receive divide clock rate" "1x,8x,16x,32x"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TICS ,Transmit internal clock source" "BRG,DPLL"
|
|
bitfld.long 0x00 12. " RICS ,Receiver internal clock source" "BRG,DPLL"
|
|
hexmask.long.word 0x00 0.--10. 1. " N ,N register"
|
|
width 8.
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "DATA,Serial Channel 1 FIFO Data register"
|
|
in
|
|
if (((d.l(ad:0xFFD00000+0x04))&0x300000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SCMLR1,Serial Channel 1 HDLC Max Length register"
|
|
hexmask.long.word 0x00 0.--14. 1. " MAXLEN ,Maximum frame length"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SCRB1,Serial Channel 1 Receive Buffer Gap Timer"
|
|
bitfld.long 0x00 31. " TRUN ,Enable timer to run" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--14. 1. " BT ,BT timer"
|
|
endif
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "SCRCGT1,Serial Channel 1 Receive Character Gap Timer"
|
|
bitfld.long 0x00 31. " TRUN ,Enable timer to run" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--9. 1. " CT ,CT value"
|
|
line.long 0x04 "SCRMR1,Serial Channel 1 Receive Match register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " RDMB1 ,Receive data match byte 1"
|
|
hexmask.long.byte 0x04 16.--23. 1. " RDMB2 ,Receive data match byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RDMB3 ,Receive data match byte 3"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " RDMB4 ,Receive data match byte 4"
|
|
line.long 0x08 "SCRMMR1,Serial Channel 1 Receive Match MASK register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " RMMB1 ,Receive mask match byte 1"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RMMB2 ,Receive mask match byte 2"
|
|
hexmask.long.byte 0x08 8.--15. 1. " RMMB3 ,Receive mask match byte 3"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " RMMB4 ,Receive mask match byte 4"
|
|
if (((d.l(ad:0xFFD00000+0x04))&0x300000)==0x100000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SCCRC1,Serial Channel 1 Control Register C"
|
|
bitfld.long 0x00 28.--31. " NFLAG ,Number of flags between frames" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. " CRC ,CRC mode" "No CRC,Reserved,16-bit CCITT CRC-16,32-bit CCITT CRC-32"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RXCRC ,Receive CRC" "Not inserted,Inserted"
|
|
bitfld.long 0x00 20. " CHKCRC_ ,Check the receive CRC" "Checked,Not Checked"
|
|
bitfld.long 0x00 17. " TXCRC ,Transmit CRC" "Sent,Not sent"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FLAG_/IDL ,Send flag or Idle between frames" "Sent,Not sent"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SCSRB1,Serial Channel 1 Status Register B"
|
|
bitfld.long 0x00 31. " FLAGS ,Static receiver flags status" "Active,IDLE"
|
|
bitfld.long 0x00 30. " IDLE ,Static receiver IDLE status" "Not received,Received"
|
|
bitfld.long 0x00 25. " RXBCAM1 ,Receive buffer closed due to address match 1" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RXBCAM2 ,Receive buffer closed due to address match 2" "Not caused,Caused"
|
|
bitfld.long 0x00 23. " RXBCAM3 ,Receive buffer closed due to address match 3" "Not caused,Caused"
|
|
bitfld.long 0x00 22. " RXBCAM4 ,Receive buffer closed due to address match 4" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RXBCN ,Receive buffer closed NORMAL" "Erorr,No error"
|
|
bitfld.long 0x00 20. " RXBCC ,Receive buffer closed due to CRC error" "No error,CRC error"
|
|
bitfld.long 0x00 19. " RXBCO ,Receive buffer closed due to OVERRUN error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RXBCA ,Receive buffer closed due to ALIGNMENT error" "No error,Error"
|
|
bitfld.long 0x00 17. " RXBCL ,Receive buffer closed due to LARGE error" "No error,Error"
|
|
bitfld.long 0x00 16. " RXBCAB ,Receive buffer closed due to ABORT" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TXBCC ,Transmit buffer closed due to loss of CTS" "Not aborded,Aborted"
|
|
bitfld.long 0x00 14. " TXBCU ,Transmit buffer closed due to UNDERRUN condition" "Not Caused,Caused"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "SCSRC1,Serial Channel 1 Status Register C"
|
|
in
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "DATA,Serial Channel 1 FIFO Data Register LAST"
|
|
in
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "SCCRC1,Serial Channel 1 Control Register C"
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "SCSRB1,Serial Channel 1 Status Register B"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "SCSRC1,Serial Channel 1 Status Register C"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "DATA,Serial Channel 1 FIFO Data Register LAST"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "Channel 2"
|
|
base ad:0xFFD00040
|
|
width 8.
|
|
if (((d.l(ad:0xFFD00040+0x00))&0x3000000)==0x0000000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCCRA2,Serial Channel 2 Control Register A"
|
|
bitfld.long 0x00 31. " CE ,Channel enable" "Reset,Enabled"
|
|
bitfld.long 0x00 30. " BRK ,Send break" "Not forced,Forced"
|
|
bitfld.long 0x00 29. " STICKP ,Stick parity" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 28. " EPS ,Even parity select" "Odd parity,Even parity"
|
|
bitfld.long 0x00 27. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " STOP ,Number of stop bits" "1 stop bit,1.5 stop bits"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " WLS ,Data word length select" "5,6,7,8"
|
|
bitfld.long 0x00 23. " CTSTX ,Enable the transmitter with active CTS" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RTSRX ,Enable active RTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RL ,Remote loopback" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LL ,Local loopback" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " OUT1 ,General-purpose output 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OUT2 ,General-purpose output 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DTR ,Data terminal ready active" "Not activated,Activated"
|
|
bitfld.long 0x00 16. " RTS ,Request-to-send active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERXBRT ,Receive break interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ERFE ,Receive framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ERXPE ,Receive parity error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ERXORUN ,Receive overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ERXRDY ,Receive register ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ERXHALF ,Receive FIFO half-full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ERXBC ,Receive buffer closed interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ERXDMA ,Enable receive DMA requests" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ERXDCD ,Change in DCD interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ERXRI ,Change in RI interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ERXDSR ,Change in DSR interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ERXCTS ,Change in CTS interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ETXRDY ,Transmit register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ETXHALF ,Transmit FIFO half-empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ERXBC ,Transmit buffer closed interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ETXDMA ,Enable transmit DMA requests" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SCCRA2,Serial Channel 2 Control Register A"
|
|
bitfld.long 0x00 31. " CE ,Channel enable" "Reset,Enabled"
|
|
bitfld.long 0x00 30. " BRK ,Send break" "Not forced,Forced"
|
|
bitfld.long 0x00 29. " STICKP ,Stick parity" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 28. " EPS ,Even parity select" "Odd parity,Even parity"
|
|
bitfld.long 0x00 27. " PE ,Parity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " STOP ,Number of stop bits" "1 stop bit,2 stop bits"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " WLS ,Data word length select" "5,6,7,8"
|
|
bitfld.long 0x00 23. " CTSTX ,Enable the transmitter with active CTS" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " RTSRX ,Enable active RTS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RL ,Remote loopback" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LL ,Local loopback" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " OUT1 ,General-purpose output 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OUT2 ,General-purpose output 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DTR ,Data terminal ready active" "Not activated,Activated"
|
|
bitfld.long 0x00 16. " RTS ,Request-to-send active" "Not activated,Activated"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ERXBRT ,Receive break interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ERFE ,Receive framing error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ERXPE ,Receive parity error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ERXORUN ,Receive overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " ERXRDY ,Receive register ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ERXHALF ,Receive FIFO half-full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ERXBC ,Receive buffer closed interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ERXDMA ,Enable receive DMA requests" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ERXDCD ,Change in DCD interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ERXRI ,Change in RI interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " ERXDSR ,Change in DSR interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " ERXCTS ,Change in CTS interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ETXRDY ,Transmit register empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ETXHALF ,Transmit FIFO half-empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ERXBC ,Transmit buffer closed interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ETXDMA ,Enable transmit DMA requests" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
width 8.
|
|
line.long 0x00 "SCCRB2,Serial Channel 2 Control Register B"
|
|
bitfld.long 0x00 31. " RDM1 ,Enable receive data match1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " RDM2 ,Enable receive data match2" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RDM3 ,Enable receive data match3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " RDM4 ,Enable receive data match4" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " RBGT ,Enable receive buffer GAP timer" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RCGT ,Enable receive character GAP timer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " MODE ,SCC mode" "UART,HDLC,SPI master,SPI slave"
|
|
bitfld.long 0x00 19. " BITORDR ,Bit ordering" "Normal,Reverse"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MAM1 ,Match address mode 1" "Match3/Match4 for each 8-bit address,Match1/Match2 combined for 16-bit address"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MAM2 ,Match address mode 2" "Match3/Match4 for each 8-bit address,Match1/Match2 combined for 16-bit address"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RTSTX ,Enable active RTS only while transmitting" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " TENC ,Transmit encoding" "NRZ,NRZB,NRZI-Mark,NRZI-Space,FM0,FM1,Manchester,Differential Manchester"
|
|
bitfld.long 0x00 6.--8. " RDEC ,Receive data encoding" "NRZ,NRZB,NRZI-Mark,NRZI-Space,FM0,FM1,Manchester,Differential Manchester"
|
|
textline " "
|
|
bitfld.long 0x00 3.--4. " TPL ,Transmit preamble length" "No preamble,8 bits,16 bits,32 bits"
|
|
bitfld.long 0x00 2. " TEND ,Transmitter frame ending" "TXD encoded only for valid data,TXD always encoded"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " TPP ,Transmit preamble pattern" "All zeros,Repeating 10s,Repeating 01s,All ones"
|
|
width 8.
|
|
if (((d.l(ad:0xFFD00040+0x08))&0x200)==0x200)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SCSRA2,Serial Channel 2 Status Register A"
|
|
eventfld.long 0x00 31. " Match1 ,Character Match1" "Disabled,Enabled"
|
|
eventfld.long 0x00 30. " Match2 ,Character Match2" "Disabled,Enabled"
|
|
eventfld.long 0x00 29. " Match3 ,Character Match3" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 28. " Match4 ,Character Match4" "Disabled,Enabled"
|
|
eventfld.long 0x00 27. " BGAP ,Buffer GAP timer" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CGAP ,Character GAP timer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " RXFDB ,Receive FIFO data available" "Full-word,One byte,Half-word,Three bytes"
|
|
bitfld.long 0x00 19. " DCD ,Current data carrier detect state" "Inactive,Active"
|
|
bitfld.long 0x00 18. " RI ,Current ring indicator state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 17. " DSR ,Current data set ready state" "Inactive,Active"
|
|
bitfld.long 0x00 16. " CTS ,Current clear to send state" "Inactive,Active"
|
|
eventfld.long 0x00 15. " RBRK ,Receive break interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 14. " RFE ,Receive framing error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 13. " RPE ,Receive parity error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ROVER ,Receive overrun interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " RRDY ,Receive register ready interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " RHALF ,Receive FIFO half-full interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " RBC ,Receive buffer closed interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 8. " RFULL ,Receive FIFO full" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 7. " DCDI ,Change in DCD interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " RII ,Change in RI interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 5. " DSRI ,Change in DSR interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 4. " CTSI ,Change in CTS interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TRDY ,Transmit register empty interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 2. " THALF ,Transmit FIFO half-empty interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 1. " TBC ,Transmit buffer closed interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " TEMPTY ,Transmit FIFO empty" "No interrupt,Interrupt"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SCSRA2,Serial Channel 2 Status Register A"
|
|
eventfld.long 0x00 27. " BGAP ,Buffer GAP timer" "Disabled,Enabled"
|
|
eventfld.long 0x00 26. " CGAP ,Character GAP timer" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " RXFDB ,Receive FIFO data available" "Full-word,One byte,Half-word,Three bytes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DCD ,Current data carrier detect state" "Inactive,Active"
|
|
bitfld.long 0x00 18. " RI ,Current ring indicator state" "Inactive,Active"
|
|
bitfld.long 0x00 17. " DSR ,Current data set ready state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CTS ,Current clear to send state" "Inactive,Active"
|
|
eventfld.long 0x00 15. " RBRK ,Receive break interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " RFE ,Receive framing error interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " RPE ,Receive parity error interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " ROVER ,Receive overrun interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 11. " RRDY ,Receive register ready interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 10. " RHALF ,Receive FIFO half-full interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 9. " RBC ,Receive buffer closed interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 8. " RFULL ,Receive FIFO full" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 7. " DCDI ,Change in DCD interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 6. " RII ,Change in RI interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 5. " DSRI ,Change in DSR interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CTSI ,Change in CTS interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 3. " TRDY ,Transmit register empty interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 2. " THALF ,Transmit FIFO half-empty interrupt pending" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 1. " TBC ,Transmit buffer closed interrupt pending" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 0. " TEMPTY ,Transmit FIFO empty" "No interrupt,Interrupt"
|
|
endif
|
|
width 8.
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SCBR2,Serial Channel 2 Bit-Rate registers"
|
|
bitfld.long 0x00 31. " EBIT ,Bit-rate generator enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " TMODE ,Timing mode" "16X mode,Used TDCR/RDCR"
|
|
bitfld.long 0x00 29. " RXSRC ,Receive clock source" "Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TXSRC ,Transmit clock source" "Internal,External"
|
|
bitfld.long 0x00 27. " RXEXT ,Drive receive clock external" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " TXEXT ,Drive transmit clock external" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " CLKMUX ,BRG input clock" "defined by F_XTALE,defined by F_SYSCLK,defined by input on OUT1,defined by input on OUT2"
|
|
bitfld.long 0x00 23. " TXCINV ,Transmit clock invert" "Normal,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RXCINV ,Receive clock invert" "Normal,Inverted"
|
|
bitfld.long 0x00 19.--20. " TDCR ,Transmit divide clock rate" "1x,8x,16x,32x"
|
|
bitfld.long 0x00 16.--17. " RDCR ,Receive divide clock rate" "1x,8x,16x,32x"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TICS ,Transmit internal clock source" "BRG,DPLL"
|
|
bitfld.long 0x00 12. " RICS ,Receiver internal clock source" "BRG,DPLL"
|
|
hexmask.long.word 0x00 0.--10. 1. " N ,N register"
|
|
width 8.
|
|
hgroup.long 0x10++0x03
|
|
hide.long 0x00 "DATA,Serial Channel 2 FIFO Data register"
|
|
in
|
|
if (((d.l(ad:0xFFD00040+0x04))&0x300000)==0x100000)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SCMLR2,Serial Channel 2 HDLC Max Length register"
|
|
hexmask.long.word 0x00 0.--14. 1. " MAXLEN ,Maximum frame length"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SCRB2,Serial Channel 2 Receive Buffer Gap Timer"
|
|
bitfld.long 0x00 31. " TRUN ,Enable timer to run" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--14. 1. " BT ,BT timer"
|
|
endif
|
|
group.long 0x18++0x0B
|
|
line.long 0x00 "SCRCGT2,Serial Channel 2 Receive Character Gap Timer"
|
|
bitfld.long 0x00 31. " TRUN ,Enable timer to run" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 0.--9. 1. " CT ,CT value"
|
|
line.long 0x04 "SCRMR2,Serial Channel 2 Receive Match register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " RDMB1 ,Receive data match byte 1"
|
|
hexmask.long.byte 0x04 16.--23. 1. " RDMB2 ,Receive data match byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " RDMB3 ,Receive data match byte 3"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--7. 1. " RDMB4 ,Receive data match byte 4"
|
|
line.long 0x08 "SCRMMR2,Serial Channel 2 Receive Match MASK register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " RMMB1 ,Receive mask match byte 1"
|
|
hexmask.long.byte 0x08 16.--23. 1. " RMMB2 ,Receive mask match byte 2"
|
|
hexmask.long.byte 0x08 8.--15. 1. " RMMB3 ,Receive mask match byte 3"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " RMMB4 ,Receive mask match byte 4"
|
|
if (((d.l(ad:0xFFD00040+0x04))&0x300000)==0x100000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SCCRC2,Serial Channel 2 Control Register C"
|
|
bitfld.long 0x00 28.--31. " NFLAG ,Number of flags between frames" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 22.--23. " CRC ,CRC mode" "No CRC,Reserved,16-bit CCITT CRC-16,32-bit CCITT CRC-32"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RXCRC ,Receive CRC" "Not inserted,Inserted"
|
|
bitfld.long 0x00 20. " CHKCRC_ ,Check the receive CRC" "Checked,Not Checked"
|
|
bitfld.long 0x00 17. " TXCRC ,Transmit CRC" "Sent,Not sent"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FLAG_/IDL ,Send flag or Idle between frames" "Sent,Not sent"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "SCSRB2,Serial Channel 2 Status Register B"
|
|
bitfld.long 0x00 31. " FLAGS ,Static receiver flags status" "Active,IDLE"
|
|
bitfld.long 0x00 30. " IDLE ,Static receiver IDLE status" "Not received,Received"
|
|
bitfld.long 0x00 25. " RXBCAM1 ,Receive buffer closed due to address match 1" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RXBCAM2 ,Receive buffer closed due to address match 2" "Not caused,Caused"
|
|
bitfld.long 0x00 23. " RXBCAM3 ,Receive buffer closed due to address match 3" "Not caused,Caused"
|
|
bitfld.long 0x00 22. " RXBCAM4 ,Receive buffer closed due to address match 4" "Not caused,Caused"
|
|
textline " "
|
|
bitfld.long 0x00 21. " RXBCN ,Receive buffer closed NORMAL" "Erorr,No error"
|
|
bitfld.long 0x00 20. " RXBCC ,Receive buffer closed due to CRC error" "No error,CRC error"
|
|
bitfld.long 0x00 19. " RXBCO ,Receive buffer closed due to OVERRUN error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 18. " RXBCA ,Receive buffer closed due to ALIGNMENT error" "No error,Error"
|
|
bitfld.long 0x00 17. " RXBCL ,Receive buffer closed due to LARGE error" "No error,Error"
|
|
bitfld.long 0x00 16. " RXBCAB ,Receive buffer closed due to ABORT" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TXBCC ,Transmit buffer closed due to loss of CTS" "Not aborded,Aborted"
|
|
bitfld.long 0x00 14. " TXBCU ,Transmit buffer closed due to UNDERRUN condition" "Not Caused,Caused"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "SCSRC2,Serial Channel 2 Status Register C"
|
|
in
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "DATA,Serial Channel 2 FIFO Data Register LAST"
|
|
in
|
|
else
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "SCCRC2,Serial Channel 2 Control Register C"
|
|
hgroup.long 0x28++0x03
|
|
hide.long 0x00 "SCSRB2,Serial Channel 2 Status Register B"
|
|
hgroup.long 0x2C++0x03
|
|
hide.long 0x00 "SCSRC2,Serial Channel 2 Status Register C"
|
|
hgroup.long 0x30++0x03
|
|
hide.long 0x00 "DATA,Serial Channel 2 FIFO Data Register LAST"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree.end
|
|
textline ""
|