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Gen4_R-Car_Trace32/2_Trunk/pernetx50.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: NETX50 On-Chip Peripherals
; @Props: Released
; @Author: MPO
; @Changelog: 2008-08-27 MPO
; @Manufacturer: HILSCHER - Hilscher GmbH
; @Doc: netX50 Program Reference Guide Rev01 (2007-12-17)
; @Core: ARM926EJ-S
; @Chip: NETX50
; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: pernetx50.per 7592 2017-02-18 13:54:14Z askoncej $
config 16. 8.
width 0x0B
tree "ARM Core Registers"
AUTOINDENT.PUSH
AUTOINDENT.OFF
width 8.
tree "ID Registers"
group c15:0x0000--0x0000
line.long 0x0 "MIDR,Identity Code"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer"
hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision"
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version"
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision"
group c15:0x0100--0x0100
line.long 0x0 "CTR,Cache Type"
bitfld.long 0x0 25.--28. " CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes"
textline " "
bitfld.long 0x0 18.--21. " DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
bitfld.long 0x0 14. " DM ,Data Cache Multiplier Bit" "0,1"
bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16"
textline " "
bitfld.long 0x0 6.--9. " ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
bitfld.long 0x0 2. " IM ,Instruction Cache Multiplier Bit" "0,1"
bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16"
group c15:0x0200--0x0200
line.long 0x0 "TCMTR,Tightly-Coupled Memory Type Register"
bitfld.long 0x0 16. " DP ,Data TCM Present" "no,yes"
bitfld.long 0x0 0. " IP ,Instruction TCM Present" "no,yes"
tree.end
tree "MMU Control and Configuration"
width 8.
group c15:0x0001--0x0001
line.long 0x0 "CR,Control Register"
bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable"
bitfld.long 0x0 14. " RR ,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin"
bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000"
textline " "
bitfld.long 0x0 12. " I ,Instruction Cache" "Disable,Enable"
bitfld.long 0x0 9. " R ,ROM Protection" "Disable,Enable"
bitfld.long 0x0 8. " S ,System Protection" "Disable,Enable"
bitfld.long 0x0 7. " B ,Endianism" "Little,Big"
textline " "
bitfld.long 0x0 2. " C ,Data Cache" "Disable,Enable"
bitfld.long 0x0 1. " A ,Alignment Fault Checking" "Disable,Enable"
bitfld.long 0x0 0. " M ,MMU" "Disable,Enable"
textline " "
group c15:0x0002--0x0002
line.long 0x0 "TTBR,Translation Table Base Register"
hexmask.long 0x0 14.--31. 0x4000 " TTBA ,Translation Table Base Address"
textline " "
group c15:0x3--0x3
line.long 0x0 "DACR,Domain Access Control Register"
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
textline " "
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
textline " "
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
textline " "
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
textline " "
group c15:0x0005--0x0005
line.long 0x0 "DFSR,Data Fault Status Register"
bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
group c15:0x0105--0x0105
line.long 0x0 "IFSR,Instruction Fault Status Register"
bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
group c15:0x0006--0x0006
line.long 0x0 "DFAR,Data Fault Address Register"
textline " "
group c15:0x000a--0x000a
line.long 0x0 "TLBR,TLB Lockdown Register"
bitfld.long 0x0 26.--28. " VICTIM ,Victim" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. " P ,P bit" "0,1"
textline " "
group c15:0x000d--0x000d
line.long 0x0 "FCSEPID,FCSE Process ID"
group c15:0x010d--0x010d
line.long 0x0 "CONTEXT,Context ID"
tree.end
tree "Cache Control and Configuration"
group c15:0x0009--0x0009
line.long 0x0 "DCACHE,Data Cache Lockdown"
bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
group c15:0x0109--0x0109
line.long 0x0 "ICACHE,Instruction Cache Lockdown"
bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
tree.end
tree "TCM Control and Configuration"
group c15:0x0019--0x0019
line.long 0x0 "DTCM,Data TCM Region Register"
hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
group c15:0x0119--0x0119
line.long 0x0 "ITCM,Instruction TCM Region Register"
hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
tree.end
tree "Test and Debug"
group c15:0x000f--0x000f
line.long 0x0 "DOVRR,Debug Override Register"
bitfld.long 0x0 19. " TCALL ,Test and clean all" "disable,enable"
bitfld.long 0x0 18. " DTLBMISS ,Abort Data TLB Miss" "no abort,abort"
bitfld.long 0x0 17. " ITLBMISS ,Abort Instruction TLB Miss" "no abort,abort"
textline " "
bitfld.long 0x0 16. " PREFETCH ,NC Instruction Prefetching" "enable,disable"
bitfld.long 0x0 15. " CLOCKGATE ,Block Level Clock Gating" "enable,disable"
bitfld.long 0x0 14. " NCBSTORE ,NCB Stores" "disable,enable"
bitfld.long 0x0 13. " MMU/DC ,MMU disable DCache Enabled Behaviour" "NCNB,WT"
group c15:0x001f--0x001f
line.long 0x0 "ADDRESS,Debug/Test Address"
;wgroup c15:0x402f--0x402f
; line.long 0x0 "RMTLBTAG,Read tag in main TLB entry"
;wgroup c15:0x403f--0x403f
; line.long 0x0 "WMTLBTAG,Write tag in main TLB entry"
;wgroup c15:0x404f--0x404f
; line.long 0x0 "RMTLBPA,Read PA in main TLB entry"
;wgroup c15:0x405f--0x405f
; line.long 0x0 "WMTLBPA,Write PA in main TLB entry"
;wgroup c15:0x407f--0x407f
; line.long 0x0 "TMTLB,Transfer main TLB entry into RAM"
;wgroup c15:0x412f--0x412f
; line.long 0x0 "RLTLBTAG,Read tag in lockdown TLB entry"
;wgroup c15:0x413f--0x413f
; line.long 0x0 "WLTLBTAG,Write tag in lockdown TLB entry"
;wgroup c15:0x414f--0x414f
; line.long 0x0 "RLTLBPA,Read PA in lockdown TLB entry"
;wgroup c15:0x415f--0x415f
; line.long 0x0 "WLTLBPA,Write PA in lockdown TLB entry"
;wgroup c15:0x417f--0x417f
; line.long 0x0 "TLTLB,Transfer lockdown TLB entry into RAM"
group c15:0x101f--0x101f
line.long 0x0 "TRACE,Trace Control"
bitfld.long 0x0 2. " FIQ ,Stalling Core when FIQ and ETM FIFOFULL" "stall, no stall"
bitfld.long 0x0 1. " IRQ ,Stalling Core when IRQ and ETM FIFOFULL" "stall, no stall"
group c15:0x700f--0x700f
line.long 0x0 "CACHE,Cache Debug Control"
bitfld.long 0x0 2. " DWT ,Disable Writeback (force WT)" "writeback,write-through"
bitfld.long 0x0 1. " DIL ,Disable ICache Linefill" "enable,disable"
bitfld.long 0x0 0. " DDL ,Disable DCache Linefill" "enable,disable"
group c15:0x701f--0x701f
line.long 0x0 "MMU,MMU Debug Control"
bitfld.long 0x0 7. " TLBMI ,Disable Main TLB Matching for Instruction Fetches" "enable,disable"
bitfld.long 0x0 6. " TLBMD ,Disable Main TLB Matching for Data Accesses" "enable,disable"
bitfld.long 0x0 5. " TLBLI ,Disable Main TLB Load Due to Instruction Fetches Miss" "enable,disable"
bitfld.long 0x0 4. " TLBLD ,Disable Main TLB Load Due to Data Access Miss" "enable,disable"
textline " "
bitfld.long 0x0 3. " TLBMMI ,Disable Micro TLB Matching for Instruction Fetches" "enable,disable"
bitfld.long 0x0 2. " TLBMMD ,Disable Micro TLB Matching for Data Accesses" "enable,disable"
bitfld.long 0x0 1. " TLBMLI ,Disable Micro TLB Load Due to Instruction Fetches Miss" "enable,disable"
bitfld.long 0x0 0. " TLBMLD ,Disable Micro TLB Load Due to Data Access Miss" "enable,disable"
group c15:0x002f--0x002f
line.long 0x0 "REMAP,Memory Region Remap"
bitfld.long 0x0 14.--15. " IWB ," "NCNB,NCB,WT,WB"
bitfld.long 0x0 12.--13. " IWT ," "NCNB,NCB,WT,WB"
bitfld.long 0x0 10.--11. " INCB ," "NCNB,NCB,WT,WB"
bitfld.long 0x0 8.--9. " INCNB ," "NCNB,NCB,WT,WB"
textline " "
bitfld.long 0x0 6.--7. " DWB ," "NCNB,NCB,WT,WB"
bitfld.long 0x0 4.--5. " DWT ," "NCNB,NCB,WT,WB"
bitfld.long 0x0 2.--3. " DNCB ," "NCNB,NCB,WT,WB"
bitfld.long 0x0 0.--1. " DNCNB ," "NCNB,NCB,WT,WB"
tree.end
tree "ICEbreaker"
width 8.
group ice:0x0--0x5 "Debug Control"
line.long 0x0 "DBGCTRL,Debug Control Register"
bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled"
bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled"
textline " "
bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled"
bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled"
bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes"
bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
line.long 0x4 "DBGSTAT,Debug Status Register"
bitfld.long 0x4 0x6--0x9 " MOE ,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res"
bitfld.long 0x4 0x5 " IJBIT ,IJBIT" "0,java"
bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,thumb"
bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1"
bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled"
bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes"
bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
line.long 0x8 "VECTOR,Vector Catch Register"
bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena"
bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena"
bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena"
bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena"
bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena"
bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena"
bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena"
line.long 0x10 "COMCTRL,Debug Communication Control Register"
bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend"
bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend"
line.long 0x14 "COMDATA,Debug Communication Data Register"
group ice:0x8--0x0d "Watchpoint 0"
line.long 0x0 "AV,Address Value"
line.long 0x4 "AM,Address Mask"
line.long 0x8 "DV,Data Value"
line.long 0x0c "DM,Data Mask"
line.long 0x10 "CV,Control Value"
bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W"
line.long 0x14 "CM,Control Mask"
bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
group ice:0x10--0x15 "Watchpoint 1"
line.long 0x0 "AV,Address Value"
line.long 0x4 "AM,Address Mask"
line.long 0x8 "DV,Data Value"
line.long 0x0c "DM,Data Mask"
line.long 0x10 "CV,Control Value"
bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w"
line.long 0x14 "CM,Control Mask"
bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
tree.end
AUTOINDENT.POP
tree.end
tree "System Functions"
base asd:0x1c000000
width 14.
rgroup.long 0x34++0x03 "IOC (IO Configuration)"
line.long 0x00 "NETX_REV,NetX Revision"
hexmask.long.byte 0x00 0.--7. 1. " NETX_VERSION ,NetX50 revision number"
group.long 0x70++0x03 "ACCESS_KEY,Access Protection"
line.long 0x00 "IO_CFG_ACC_KEY,ASIC Control Locking Access Key Register"
hexmask.long.word 0x00 0.--15. 1. " ACCESS_KEY ,Access key for next write access"
group.long 0x04++0x07 "IOC (IO Configuration)"
line.long 0x00 "IOC_CR,IO Configuration Register"
bitfld.long 0x00 31. " IF_SELECT_N ,Host interface modes disable" "DPM/EBM/PIO,Disabled"
bitfld.long 0x00 30. " SEL_EXT_PHY1 ,External/internal PHY1 select" "Internal,External"
textline " "
bitfld.long 0x00 29. " SEL_EXT_PHY0 ,External/internal PHY0 select" "Internal,External"
bitfld.long 0x00 23. " SEL_ETM ,Select pins for ETM9 " "Not selected,Selected"
textline " "
bitfld.long 0x00 10. " SEL_I2C_MMIO ,Select pads for I2C" "I2C_SDA/I2C_SCL,I2C via MMIO"
bitfld.long 0x00 9. " SEL_XM1_ECLK ,Select pad for xMAC1 eclk" "Not selected,Selected"
textline " "
bitfld.long 0x00 8. " SEL_XM0_ECLK ,Select pad for xMAC0 eclk" "Not selected,Selected"
bitfld.long 0x00 7. " SEL_FO1 ,Select Fiber Optics of PHY1" "Standard,Fiber Optics"
textline " "
bitfld.long 0x00 6. " SEL_FO0 ,Select Fiber Optics of PHY0" "Standard,Fiber Optics"
bitfld.long 0x00 5. " SEL_FB1_CLK_B ,Select pad for fieldbus-clk1 at position b" "Not selected,Selected"
textline " "
bitfld.long 0x00 4. " SEL_FB1_CLK_A ,Select pad for fieldbus-clk1 at position a" "Not selected,Selected"
bitfld.long 0x00 3. " SEL_FB0_CLK_B ,Select pad for fieldbus-clk0 at position b" "Not selected,Selected"
textline " "
bitfld.long 0x00 2. " SEL_FB0_CLK_A ,Select pad for fieldbus-clk0 at position a " "Not selected,Selected"
bitfld.long 0x00 1. " SEL_XM1_TX ,Select pad for xMAC1 tx-bitstream direct output " "Not selected,Selected"
textline " "
bitfld.long 0x00 0. " SEL_XM0_TX ,Select pad for xMAC0 tx-bitstream direct output" "Not selected,Selected"
width 14.
group.long 0x1300++0x9f
line.long 0x0 "MMIO0_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO0"
bitfld.long 0x0 9. " MMIO0_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x0 8. " MMIO0_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x0 0.--7. 1. " MMIO0_SEL , MMIO0 signal selection"
line.long 0x4 "MMIO1_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO1"
bitfld.long 0x4 9. " MMIO1_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x4 8. " MMIO1_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x4 0.--7. 1. " MMIO1_SEL , MMIO1 signal selection"
line.long 0x8 "MMIO2_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO2"
bitfld.long 0x8 9. " MMIO2_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x8 8. " MMIO2_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x8 0.--7. 1. " MMIO2_SEL , MMIO2 signal selection"
line.long 0xC "MMIO3_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO3"
bitfld.long 0xC 9. " MMIO3_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0xC 8. " MMIO3_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0xC 0.--7. 1. " MMIO3_SEL , MMIO3 signal selection"
line.long 0x10 "MMIO4_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO4"
bitfld.long 0x10 9. " MMIO4_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x10 8. " MMIO4_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x10 0.--7. 1. " MMIO4_SEL , MMIO4 signal selection"
line.long 0x14 "MMIO5_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO5"
bitfld.long 0x14 9. " MMIO5_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x14 8. " MMIO5_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x14 0.--7. 1. " MMIO5_SEL , MMIO5 signal selection"
line.long 0x18 "MMIO6_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO6"
bitfld.long 0x18 9. " MMIO6_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x18 8. " MMIO6_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x18 0.--7. 1. " MMIO6_SEL , MMIO6 signal selection"
line.long 0x1C "MMIO7_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO7"
bitfld.long 0x1C 9. " MMIO7_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x1C 8. " MMIO7_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x1C 0.--7. 1. " MMIO7_SEL , MMIO7 signal selection"
line.long 0x20 "MMIO8_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO8"
bitfld.long 0x20 9. " MMIO8_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x20 8. " MMIO8_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x20 0.--7. 1. " MMIO8_SEL , MMIO8 signal selection"
line.long 0x24 "MMIO9_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO9"
bitfld.long 0x24 9. " MMIO9_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x24 8. " MMIO9_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x24 0.--7. 1. " MMIO9_SEL , MMIO9 signal selection"
line.long 0x28 "MMIO10_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO10"
bitfld.long 0x28 9. " MMIO10_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x28 8. " MMIO10_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x28 0.--7. 1. " MMIO10_SEL , MMIO10 signal selection"
line.long 0x2C "MMIO11_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO11"
bitfld.long 0x2C 9. " MMIO11_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x2C 8. " MMIO11_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x2C 0.--7. 1. " MMIO11_SEL , MMIO11 signal selection"
line.long 0x30 "MMIO12_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO12"
bitfld.long 0x30 9. " MMIO12_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x30 8. " MMIO12_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x30 0.--7. 1. " MMIO12_SEL , MMIO12 signal selection"
line.long 0x34 "MMIO13_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO13"
bitfld.long 0x34 9. " MMIO13_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x34 8. " MMIO13_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x34 0.--7. 1. " MMIO13_SEL , MMIO13 signal selection"
line.long 0x38 "MMIO14_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO14"
bitfld.long 0x38 9. " MMIO14_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x38 8. " MMIO14_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x38 0.--7. 1. " MMIO14_SEL , MMIO14 signal selection"
line.long 0x3C "MMIO15_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO15"
bitfld.long 0x3C 9. " MMIO15_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x3C 8. " MMIO15_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x3C 0.--7. 1. " MMIO15_SEL , MMIO15 signal selection"
line.long 0x40 "MMIO16_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO16"
bitfld.long 0x40 9. " MMIO16_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x40 8. " MMIO16_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x40 0.--7. 1. " MMIO16_SEL , MMIO16 signal selection"
line.long 0x44 "MMIO17_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO17"
bitfld.long 0x44 9. " MMIO17_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x44 8. " MMIO17_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x44 0.--7. 1. " MMIO17_SEL , MMIO17 signal selection"
line.long 0x48 "MMIO18_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO18"
bitfld.long 0x48 9. " MMIO18_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x48 8. " MMIO18_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x48 0.--7. 1. " MMIO18_SEL , MMIO18 signal selection"
line.long 0x4C "MMIO19_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO19"
bitfld.long 0x4C 9. " MMIO19_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x4C 8. " MMIO19_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x4C 0.--7. 1. " MMIO19_SEL , MMIO19 signal selection"
line.long 0x50 "MMIO20_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO20"
bitfld.long 0x50 9. " MMIO20_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x50 8. " MMIO20_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x50 0.--7. 1. " MMIO20_SEL , MMIO20 signal selection"
line.long 0x54 "MMIO21_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO21"
bitfld.long 0x54 9. " MMIO21_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x54 8. " MMIO21_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x54 0.--7. 1. " MMIO21_SEL , MMIO21 signal selection"
line.long 0x58 "MMIO22_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO22"
bitfld.long 0x58 9. " MMIO22_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x58 8. " MMIO22_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x58 0.--7. 1. " MMIO22_SEL , MMIO22 signal selection"
line.long 0x5C "MMIO23_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO23"
bitfld.long 0x5C 9. " MMIO23_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x5C 8. " MMIO23_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x5C 0.--7. 1. " MMIO23_SEL , MMIO23 signal selection"
line.long 0x60 "MMIO24_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO24"
bitfld.long 0x60 9. " MMIO24_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x60 8. " MMIO24_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x60 0.--7. 1. " MMIO24_SEL , MMIO24 signal selection"
line.long 0x64 "MMIO25_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO25"
bitfld.long 0x64 9. " MMIO25_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x64 8. " MMIO25_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x64 0.--7. 1. " MMIO25_SEL , MMIO25 signal selection"
line.long 0x68 "MMIO26_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO26"
bitfld.long 0x68 9. " MMIO26_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x68 8. " MMIO26_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x68 0.--7. 1. " MMIO26_SEL , MMIO26 signal selection"
line.long 0x6C "MMIO27_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO27"
bitfld.long 0x6C 9. " MMIO27_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x6C 8. " MMIO27_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x6C 0.--7. 1. " MMIO27_SEL , MMIO27 signal selection"
line.long 0x70 "MMIO28_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO28"
bitfld.long 0x70 9. " MMIO28_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x70 8. " MMIO28_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x70 0.--7. 1. " MMIO28_SEL , MMIO28 signal selection"
line.long 0x74 "MMIO29_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO29"
bitfld.long 0x74 9. " MMIO29_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x74 8. " MMIO29_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x74 0.--7. 1. " MMIO29_SEL , MMIO29 signal selection"
line.long 0x78 "MMIO30_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO30"
bitfld.long 0x78 9. " MMIO30_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x78 8. " MMIO30_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x78 0.--7. 1. " MMIO30_SEL , MMIO30 signal selection"
line.long 0x7C "MMIO31_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO31"
bitfld.long 0x7C 9. " MMIO31_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x7C 8. " MMIO31_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x7C 0.--7. 1. " MMIO31_SEL , MMIO31 signal selection"
line.long 0x80 "MMIO32_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO32"
bitfld.long 0x80 9. " MMIO32_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x80 8. " MMIO32_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x80 0.--7. 1. " MMIO32_SEL , MMIO32 signal selection"
line.long 0x84 "MMIO33_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO33"
bitfld.long 0x84 9. " MMIO33_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x84 8. " MMIO33_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x84 0.--7. 1. " MMIO33_SEL , MMIO33 signal selection"
line.long 0x88 "MMIO34_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO34"
bitfld.long 0x88 9. " MMIO34_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x88 8. " MMIO34_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x88 0.--7. 1. " MMIO34_SEL , MMIO34 signal selection"
line.long 0x8C "MMIO35_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO35"
bitfld.long 0x8C 9. " MMIO35_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x8C 8. " MMIO35_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x8C 0.--7. 1. " MMIO35_SEL , MMIO35 signal selection"
line.long 0x90 "MMIO36_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO36"
bitfld.long 0x90 9. " MMIO36_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x90 8. " MMIO36_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x90 0.--7. 1. " MMIO36_SEL , MMIO36 signal selection"
line.long 0x94 "MMIO37_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO37"
bitfld.long 0x94 9. " MMIO37_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x94 8. " MMIO37_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x94 0.--7. 1. " MMIO37_SEL , MMIO37 signal selection"
line.long 0x98 "MMIO38_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO38"
bitfld.long 0x98 9. " MMIO38_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x98 8. " MMIO38_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x98 0.--7. 1. " MMIO38_SEL , MMIO38 signal selection"
line.long 0x9C "MMIO39_CFG,IO-Multiplex matrix Configuration Register For Signal MMIO39"
bitfld.long 0x9C 9. " MMIO39_IN_INV ,Invert input" "Not inverted,Inverted"
bitfld.long 0x9C 8. " MMIO39_OUT_INV ,Invert output" "Not inverted,Inverted"
textline " "
hexmask.long.byte 0x9C 0.--7. 1. " MMIO39_SEL , MMIO39 signal selection"
width 20.
group.long 0x14++0x13 "Clock Control Clock Generation and Control"
line.long 0x00 "ARM_CLK_RATE_MUL_ADD,Rate Multiplier Add Value of System Clock "
hexmask.long.word 0x00 0.--8. 1. " ARMCLK_RATE_MUL_ADD ,This value is added each clk400 cycle to armclk_rate_mul"
line.long 0x04 "USB_CLK_RATE_MUL_ADD,Rate Multiplier Add Value of USB clock"
hexmask.long.word 0x04 16.--31. 1. " USBCLK_RATE_MUL_ADD ,This value is added each clk400 cycle to usbclk_rate_mul"
line.long 0x08 "FB0CLK_RATE_MUL_ADD,Rate Multiplier Add Value"
line.long 0x0c "FB1CLK_RATE_MUL_ADD,Rate Multiplier Add Value"
line.long 0x10 "CLK_EN,Global Clock Enable Register "
bitfld.long 0x10 11. " FB1 ,Enables clock for fieldbus1" "Disabled,Enabled"
bitfld.long 0x10 10. " FB0 ,Enables clock for fieldbus0" "Disabled,Enabled"
textline " "
bitfld.long 0x10 8. " HIF ,Enables clock for HIF " "Disabled,Enabled"
bitfld.long 0x10 5. " XMAC1 ,Enables clock for xMAC1 " "Disabled,Enabled"
textline " "
bitfld.long 0x10 4. " XMAC0 ,Enables clock for xMAC0 " "Disabled,Enabled"
bitfld.long 0x10 1. " XPEC1 ,Enables clock for xPEC1 " "Disabled,Enabled"
textline " "
bitfld.long 0x10 0. " XPEC0 ,Enables clock for xPEC0 " "Disabled,Enabled"
width 20.
group.long 0x0C++0x03 "RES (RESET Controller)"
line.long 0x00 "RESET_CTRL,RESET Control Register"
bitfld.long 0x00 26. " EN_RSTOUTn ,Enable the output driver of the reset out pin" "Disabled,Enabled"
bitfld.long 0x00 25. " RSTOUTn ,Programmable reset (control the signal of the RSTOUT pin of the netX)" "No reset,Reset"
textline " "
bitfld.long 0x00 24. " FIRMW_RES ,System reset activation" "No active,Active"
bitfld.long 0x00 23. " FIRMW_STATUS3 ,Firmware Flag 3" "0,1"
textline " "
bitfld.long 0x00 22. " FIRMW_STATUS2 ,Firmware Flag 2" "0,1"
bitfld.long 0x00 21. " FIRMW_STATUS1 ,Firmware Flag 1" "0,1"
textline " "
bitfld.long 0x00 20. " FIRMW_STATUS0 ,Firmware Flag 0" "0,1"
bitfld.long 0x00 17. " DIS_XPEC1_RES ,XPEC1 module reset disable" "Enabled,Disabled"
textline " "
bitfld.long 0x00 16. " DIS_XPEC0_RES ,XPEC0 module reset disable" "Enabled,Disabled"
bitfld.long 0x00 5. " XPEC1_RES ,XPEC1 module reset" "No reset,Reset"
textline " "
bitfld.long 0x00 4. " XPEC0_RES ,XPEC0 module reset" "No reset,Reset"
eventfld.long 0x00 3. " FIRMW_RES ,Firmware reset" "No reset,Reset"
textline " "
eventfld.long 0x00 2. " HOST_RES ,Host Interface module reset" "No reset,Reset"
eventfld.long 0x00 1. " WDG_RES ,Watchdog reset" "No reset,Reset"
textline " "
eventfld.long 0x00 0. " RSTINn ,External reset" "No reset,Reset"
width 20.
group.long 0x200++0x03 "WDG (Watchdog)"
line.long 0x00 "WDG_TRIG,Watchdog Trigger Register"
bitfld.long 0x00 31. " WR_ENABLE ,Write enable for timeout register" "Disabled,Enabled"
bitfld.long 0x00 29. " WDG_ACT_EN ,Watchdog Active Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " WDG_TRIG ,Watchdog trigger" "Disabled,Enabled"
eventfld.long 0x00 24. " IRQ_Status ,Interrupt request" "Not active,Active"
textline " "
hexmask.long.tbyte 0x00 0.--19. 1. " WDG_ACCESS_CODE ,Watchdog access code for triggering"
rgroup.long 0x204++0x03
line.long 0x00 "WDG_CNTR,Watchdog Counter"
hexmask.long.tbyte 0x00 0.--16. 1. " WDG_COUNTER ,Actual watchdog counter value"
if (((d.l(ad:(0x1c000000+0x200)))&0x80000000)==0x00000000)
; Write disabled
rgroup.long 0x208++0x07
line.long 0x00 "WDG_IRQ_TIMEOUT,Watchdog Interrupt Timeout"
hexmask.long.word 0x00 0.--15. 1. " WDG_IRQ_TIMEOUT ,Watchdog interrupt request timeout"
line.long 0x04 "WDG_RESET_TIMEOUT,Watchdog Reset Timeout"
hexmask.long.word 0x04 0.--15. 1. " WDG_RESET_TIMEOUT ,Watchdog reset request timeout"
else
group.long 0x208++0x07
line.long 0x00 "WDG_IRQ_TIMEOUT,Watchdog Interrupt Timeout"
hexmask.long.word 0x00 0.--15. 1. " WDG_IRQ_TIMeOUT ,Watchdog interrupt request timeout"
line.long 0x04 "WDG_RESET_TIMEOUT,Watchdog Reset Timeout"
hexmask.long.word 0x04 0.--15. 1. " WDG_RESET_TIMeOUT ,Watchdog reset request timeout"
endif
width 20.
group.long 0x34D8++0x03 "SYS_STA (System Status)"
line.long 0x00 "SYS_STA,System Status"
bitfld.long 0x00 25. " RUN_DRV ,Driver enable for RUN LED" "Disabled,Enabled"
bitfld.long 0x00 24. " RDY_DRV ,Driver enable for RDY LED" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " RUN_POL ,Output polarity RUN LED" "Low,High"
bitfld.long 0x00 18. " RDY_POL ,Output polarity RUN LED" "Low,High"
textline " "
bitfld.long 0x00 17. " RUN_IN ,Physical input signal level at RUN pin" "Low,High"
bitfld.long 0x00 16. " RDY_IN ,Physical input signal level at RDY pin" "Low,High"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " NETX_STA_CODE ,NetX status code"
hexmask.long.byte 0x00 4.--7. 1. " HOST_STATE[3:0] ,User defined host status signals"
textline " "
hexmask.long.byte 0x00 2.--3. 1. " NETX_STATE[3:2] ,User defined netX status signals"
bitfld.long 0x00 1. " RUN ,Signal Level of the RUN LED output" "Low,High"
textline " "
bitfld.long 0x00 0. " RDY ,Signal level of the RDY LED output" "Low,High"
width 0x0B
tree.end
tree "Memory Controller (MC)"
base asd:0x1c000100
width 20.
group.long 0x00++0x0B "Memory Controller for SRAM and FLASH"
line.long 0x00 "MEM_SRAM0_CTRL,Memory SRAM Control Register for Chip Select Area 0"
bitfld.long 0x00 24.--25. " WIDTHEXTMEM ,Data path width of ExtMem0 area" "8 bit,16 bit,32 bit,?..."
bitfld.long 0x00 16.--17. " WSPOSTPAUSEEXTMEM ,Additional wait states after access" "0 cycles,1 cycle,2 cycles,3 cycles"
textline " "
bitfld.long 0x00 8.--9. " WSPREPASEEXTMEM ,Additional wait states for setup time" "0 cycles,1 cycle,2 cycles,3 cycles"
bitfld.long 0x00 0.--5. " WSEXTMEM ,Wait states 0 - 63 cycles" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles"
line.long 0x04 "MEM_SRAM1_CTRL,Memory SRAM Control Register for Chip Select Area 1"
bitfld.long 0x04 24.--25. " WIDTHEXTMEM ,Data path width of ExtMem0 area" "8 bit,16 bit,32 bit,?..."
bitfld.long 0x04 16.--17. " WSPOSTPAUSEEXTMEM ,Additional wait states after access" "0 cycles,1 cycle,2 cycles,3 cycles"
textline " "
bitfld.long 0x04 8.--9. " WSPREPASEEXTMEM ,Additional wait states for setup time" "0 cycles,1 cycle,2 cycles,3 cycles"
bitfld.long 0x04 0.--5. " WSEXTMEM ,Wait states 0 - 63 cycles" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles"
line.long 0x08 "MEM_SRAM2_CTRL,Memory SRAM Control Register for Chip Select Area 2"
bitfld.long 0x08 24.--25. " WIDTHEXTMEM ,Data path width of ExtMem0 area" "8 bit,16 bit,32 bit,?..."
bitfld.long 0x08 16.--17. " WSPOSTPAUSEEXTMEM ,Additional wait states after access" "0 cycles,1 cycle,2 cycles,3 cycles"
textline " "
bitfld.long 0x08 8.--9. " WSPREPASEEXTMEM ,Additional wait states for setup time" "0 cycles,1 cycle,2 cycles,3 cycles"
bitfld.long 0x08 0.--5. " WSEXTMEM ,Wait states 0 - 63 cycles" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles,33 cycles,34 cycles,35 cycles,36 cycles,37 cycles,38 cycles,39 cycles,40 cycles,41 cycles,42 cycles,43 cycles,44 cycles,45 cycles,46 cycles,47 cycles,48 cycles,49 cycles,50 cycles,51 cycles,52 cycles,53 cycles,54 cycles,55 cycles,56 cycles,57 cycles,58 cycles,59 cycles,60 cycles,61 cycles,62 cycles,63 cycles"
group.long 0x40++0x0B "Memory Controller for SDRAM"
line.long 0x00 "MEM_SDRAM_CFG_CTRL,Memory SDRAM Configuration Control Register"
bitfld.long 0x00 31. " REFRESH_REQUEST ,Refresh command error" "Not requested,Requested"
bitfld.long 0x00 30. " SDRAM_READY ,SDRAM access ready" "Not ready,Ready"
textline " "
bitfld.long 0x00 24.--25. " REFRESH_MODE ,Refresh priortity mode" "Fixed interval,8 refreshes,16 refreshes,2047 refreshes"
bitfld.long 0x00 19. " CTRL_EN ,SDRAM controller enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 18. " EXTCLK_EN ,External SDRAM clock enable" "Disabled,Enabled"
bitfld.long 0x00 17. " SDRAM_PWDN ,SDRAM Power Down" "No power down,Power down"
textline " "
bitfld.long 0x00 16. " DBUS32 ,SDRAM data bus width" "16 bit,32 bit"
bitfld.long 0x00 8.--10. " COLUMNS ,Column address coding" "256,512,1k,2k,4k,8k,16k,?..."
textline " "
bitfld.long 0x00 4.--6. " ROWS ,Row adress coding" "2k,4k,8k,16k,32k,64k,?..."
bitfld.long 0x00 0.--1. " BANKS ,Bank address coding" "2,4,8,?..."
line.long 0x04 "MEM_SDRAM_TIM_CTRL,Memory SDRAM Timing Control Register"
bitfld.long 0x04 28. " BYPASS_NEG_DELAY ,Bypass phase shift logic for SDRAM data sampling" "Not bypassed,Bypassed"
bitfld.long 0x04 24.--26. " DATA_SAMPLE_PHASE ,Adjustable phase-shift for data sampling SDRAM loopback clock" "0,1,2,3,4,5,?..."
textline " "
bitfld.long 0x04 23. " MEM_SDCLK_SSNEG ,Edge polarity of clk400 for clk_memsig sampling" "Positive,Negative"
bitfld.long 0x04 20.--22. " MEM_SDCLK_PHASE ,Adjustable phase-shift for external SDRAM clock" "0,1,2,3,4,5,?..."
textline " "
bitfld.long 0x04 16.--17. " T_REFI ,Average Periodic refresh interval" "3.90 us,7.80 us,15.60 us,31.20 us"
bitfld.long 0x04 12.--15. " T_RFC ,Refresh to Command time" "4 clks,5 clks,6 clks,7 clks,8 clks,9 clks,10 clks,11 clks,12 clks,13 clks,14 clks,15 clks,16 clks,17 clks,18 clks,19 clks"
textline " "
bitfld.long 0x04 8.--10. " T_RAS ,Active to Precharge command time" "3 clks,4 clks,5 clks,6 clks,7 clks,8 clks,9 clks,10 clks"
bitfld.long 0x04 6.--7. " T_RP ,Precharge command period time" "1 clk,2 clks,3 clks,?..."
textline " "
bitfld.long 0x04 4.--5. " T_WR ,Write recovery time" "1 clk,2 clks,3 clks,?..."
bitfld.long 0x04 0.--1. " T_RCD ,Active to Read or Write time" "1 clk,2 clks,3 clks,?..."
line.long 0x08 "MEM_SDRAM_MODE,Memory SDRAM Mode Register"
hexmask.long.word 0x08 16.--29. 1. " EMR ,SDRAM Mode Register for SDRAM devices"
textline " "
bitfld.long 0x08 4.--6. " MR_CAS ,Reflect CAS latency bits" "Reserved,Reserved,CL2,CL3,?..."
bitfld.long 0x08 0.--2. " MR_BURST ,Reflect Burst Length Bits" "Reserved,Reserved,Data width 32 Bit,Data width 16 Bit,?..."
group.long 0x80++0x07 "MEMPRIO (Memory Priority Controller)"
line.long 0x00 "MEM_PRIO_TIMESL_CTRL,Memory Priority Timeslot Control Register"
bitfld.long 0x00 12.--14. " TS_LENGTH_DMA_MI ,Length of the timeslot of master m3 (ARM instruction fetch) on external memory interface" "64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8192 cycles"
textline " "
bitfld.long 0x00 8.--10. " TS_LENGTH_ARM_MI ,Length of the timeslot of master m2 on external memory interface" "64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8192 cycles"
bitfld.long 0x00 4.--6. " TS_LENGTH_XC_MI ,Length of the timeslot of master m1 on external memory interface" "64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8192 cycles"
textline " "
bitfld.long 0x00 0.--2. " TS_LENGTH_HIF_MI ,Length of the timeslot of master m0 on external memory interface" "64 cycles,128 cycles,256 cycles,512 cycles,1024 cycles,2048 cycles,4096 cycles,8192 cycles"
line.long 0x04 "MEM_PRIO_ACCESS_CTRL,Memory Priority Access Control Register"
hexmask.long.byte 0x04 18.--23. 1. " TS_ACCESSRATE_DMA_MI ,Master m4 (ARM data fetch) is allowed to request"
textline " "
hexmask.long.byte 0x04 12.--17. 1. " TS_ACCESSRATE_ARM_MI ,Master m2 is alowed to request"
hexmask.long.byte 0x04 6.--11. 1. " TS_ACCESSRATE_XC_MI ,Master m1 is allowed to request"
textline " "
hexmask.long.byte 0x04 0.--5. 1. " TS_ACCESSRATE_HIF_MI ,Master m0 is allowed to request"
width 0x0B
tree.end
tree "Extension Bus (EB)"
base asd:0x1c003610
width 0x0F
group.long 0x00++0x0F
line.long 0x0 "EXT_CONFIG_CS0,Extension Bus Configuration Chip Select 0"
hexmask.long.byte 0x0 29.--31. 1. " Talewidth ,Delay time from start cycle until ALE inactive"
hexmask.long.byte 0x0 26.--28. 1. " Tadrhold ,Delay time from start cycle until invalid address at the data bus"
textline " "
hexmask.long.byte 0x0 23.--25. 1. " Tcson ,Delay time from start cycle until Chip Select low"
hexmask.long.byte 0x0 20.--22. 1. " Trdon ,Delay time from start cycle until RD low in system clocks"
textline " "
hexmask.long.byte 0x0 17.--19. 1. " Twron ,Delay time from start cycle until WR low in system clocks"
hexmask.long.byte 0x0 12.--16. 1. " Trdwroff ,Delay time from start cycle until RD and WR inactive"
textline " "
hexmask.long.byte 0x0 7.--11. 1. " Trdwrcyc ,Set the end of an access cycle in system clocks"
bitfld.long 0x0 6. " WAIT_POLARITY ,WAIT input polarity" "Not wait,Wait"
textline " "
bitfld.long 0x0 5. " WAIT_EN ,External Wait Enable" "Disabled,Enabled"
bitfld.long 0x0 4. " nRD_MODE ,NRD mode" "Normal,Data direction"
textline " "
bitfld.long 0x0 3. " DS_MODE ,Data Strobe Mode" "NWR/nWRL/nWRH,NDS/nDSL/nDSH"
bitfld.long 0x0 2. " nWR_MODE ,NWR mode" "All,Low write"
textline " "
bitfld.long 0x0 1. " 8/16BIT ,Interface width selection" "8 bit,16 bit"
bitfld.long 0x0 0. " CS_EN ,Chip Select Enable" "Disabled,Enabled"
line.long 0x4 "EXT_CONFIG_CS1,Extension Bus Configuration Chip Select 1"
hexmask.long.byte 0x4 29.--31. 1. " Talewidth ,Delay time from start cycle until ALE inactive"
hexmask.long.byte 0x4 26.--28. 1. " Tadrhold ,Delay time from start cycle until invalid address at the data bus"
textline " "
hexmask.long.byte 0x4 23.--25. 1. " Tcson ,Delay time from start cycle until Chip Select low"
hexmask.long.byte 0x4 20.--22. 1. " Trdon ,Delay time from start cycle until RD low in system clocks"
textline " "
hexmask.long.byte 0x4 17.--19. 1. " Twron ,Delay time from start cycle until WR low in system clocks"
hexmask.long.byte 0x4 12.--16. 1. " Trdwroff ,Delay time from start cycle until RD and WR inactive"
textline " "
hexmask.long.byte 0x4 7.--11. 1. " Trdwrcyc ,Set the end of an access cycle in system clocks"
bitfld.long 0x4 6. " WAIT_POLARITY ,WAIT input polarity" "Not wait,Wait"
textline " "
bitfld.long 0x4 5. " WAIT_EN ,External Wait Enable" "Disabled,Enabled"
bitfld.long 0x4 4. " nRD_MODE ,NRD mode" "Normal,Data direction"
textline " "
bitfld.long 0x4 3. " DS_MODE ,Data Strobe Mode" "NWR/nWRL/nWRH,NDS/nDSL/nDSH"
bitfld.long 0x4 2. " nWR_MODE ,NWR mode" "All,Low write"
textline " "
bitfld.long 0x4 1. " 8/16BIT ,Interface width selection" "8 bit,16 bit"
bitfld.long 0x4 0. " CS_EN ,Chip Select Enable" "Disabled,Enabled"
line.long 0x8 "EXT_CONFIG_CS2,Extension Bus Configuration Chip Select 2"
hexmask.long.byte 0x8 29.--31. 1. " Talewidth ,Delay time from start cycle until ALE inactive"
hexmask.long.byte 0x8 26.--28. 1. " Tadrhold ,Delay time from start cycle until invalid address at the data bus"
textline " "
hexmask.long.byte 0x8 23.--25. 1. " Tcson ,Delay time from start cycle until Chip Select low"
hexmask.long.byte 0x8 20.--22. 1. " Trdon ,Delay time from start cycle until RD low in system clocks"
textline " "
hexmask.long.byte 0x8 17.--19. 1. " Twron ,Delay time from start cycle until WR low in system clocks"
hexmask.long.byte 0x8 12.--16. 1. " Trdwroff ,Delay time from start cycle until RD and WR inactive"
textline " "
hexmask.long.byte 0x8 7.--11. 1. " Trdwrcyc ,Set the end of an access cycle in system clocks"
bitfld.long 0x8 6. " WAIT_POLARITY ,WAIT input polarity" "Not wait,Wait"
textline " "
bitfld.long 0x8 5. " WAIT_EN ,External Wait Enable" "Disabled,Enabled"
bitfld.long 0x8 4. " nRD_MODE ,NRD mode" "Normal,Data direction"
textline " "
bitfld.long 0x8 3. " DS_MODE ,Data Strobe Mode" "NWR/nWRL/nWRH,NDS/nDSL/nDSH"
bitfld.long 0x8 2. " nWR_MODE ,NWR mode" "All,Low write"
textline " "
bitfld.long 0x8 1. " 8/16BIT ,Interface width selection" "8 bit,16 bit"
bitfld.long 0x8 0. " CS_EN ,Chip Select Enable" "Disabled,Enabled"
line.long 0xC "EXT_CONFIG_CS3,Extension Bus Configuration Chip Select 3"
hexmask.long.byte 0xC 29.--31. 1. " Talewidth ,Delay time from start cycle until ALE inactive"
hexmask.long.byte 0xC 26.--28. 1. " Tadrhold ,Delay time from start cycle until invalid address at the data bus"
textline " "
hexmask.long.byte 0xC 23.--25. 1. " Tcson ,Delay time from start cycle until Chip Select low"
hexmask.long.byte 0xC 20.--22. 1. " Trdon ,Delay time from start cycle until RD low in system clocks"
textline " "
hexmask.long.byte 0xC 17.--19. 1. " Twron ,Delay time from start cycle until WR low in system clocks"
hexmask.long.byte 0xC 12.--16. 1. " Trdwroff ,Delay time from start cycle until RD and WR inactive"
textline " "
hexmask.long.byte 0xC 7.--11. 1. " Trdwrcyc ,Set the end of an access cycle in system clocks"
bitfld.long 0xC 6. " WAIT_POLARITY ,WAIT input polarity" "Not wait,Wait"
textline " "
bitfld.long 0xC 5. " WAIT_EN ,External Wait Enable" "Disabled,Enabled"
bitfld.long 0xC 4. " nRD_MODE ,NRD mode" "Normal,Data direction"
textline " "
bitfld.long 0xC 3. " DS_MODE ,Data Strobe Mode" "NWR/nWRL/nWRH,NDS/nDSL/nDSH"
bitfld.long 0xC 2. " nWR_MODE ,NWR mode" "All,Low write"
textline " "
bitfld.long 0xC 1. " 8/16BIT ,Interface width selection" "8 bit,16 bit"
bitfld.long 0xC 0. " CS_EN ,Chip Select Enable" "Disabled,Enabled"
width 0x0B
tree.end
tree.open "Dual-Port Memory (DPM)"
tree "Dual-Port Memory Host Side (DPMHS)"
base asd:0x1c003100
width 0x17
group.long 0xF0++0x03
line.long 0x00 "DPMHS_INT_EN0,DPM Host Side Interrupt Enable 0"
bitfld.long 0x00 31. " INT_EN ,Global interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 30. " MEM_LCK ,Memory lock interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 29. " WDG_NETX ,Watchdog timeout of netX supervision interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 26. " SYS_STA ,System status change interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " TMR ,Timer interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 15. " HS_EVENT15 ,Handshake event 15 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 14. " HS_EVENT14 ,Handshake event 14 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 13. " HS_EVENT13 ,Handshake event 13 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " HS_EVENT12 ,Handshake event 12 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 11. " HS_EVENT11 ,Handshake event 11 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " HS_EVENT10 ,Handshake event 10 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 9. " HS_EVENT9 ,Handshake event 9 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " HS_EVENT8 ,Handshake event 8 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 7. " HS_EVENT7 ,Handshake event 7 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " HS_EVENT6 ,Handshake event 6 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 5. " HS_EVENT5 ,Handshake event 5 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " HS_EVENT4 ,Handshake event 4 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 3. " HS_EVENT3 ,Handshake event 3 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " HS_EVENT2 ,Handshake event 2 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " HS_EVENT1 ,Handshake event 1 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " HS_EVENT0 ,Handshake event 0 interrupt enable" "Disabled,Enabled"
group.long 0xD0++0x13
line.long 0x10 "DPMHS_INT_STA0,DPM Host Side Interrupt Status 0"
eventfld.long 0x10 31. " INT_REQ ,Interrupt request" "Not requested,Requested"
eventfld.long 0x10 30. " MEM_LCK ,Memory lock interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x10 29. " WDG_NETX ,Watchdog timeout netX supervision interrupt" "No interrupt,Interrupt"
eventfld.long 0x10 26. " SYS_STA ,System status change interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x10 25. " TMR ,Timer interrupt" "No interrupt,Interrupt"
hexmask.long.byte 0x10 16.--23. 1. " IRQ_VECTOR[7:0] ,Interrupt Vector according to the status flags"
textline " "
eventfld.long 0x10 15. " HS_EVENT15 ,Handshake event 15 interrupt" "No interrupt,Interrupt"
eventfld.long 0x10 14. " HS_EVENT14 ,Handshake event 14 interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x10 13. " HS_EVENT13 ,Handshake event 13 interrupt" "No interrupt,Interrupt"
eventfld.long 0x10 12. " HS_EVENT12 ,Handshake event 12 interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x10 11. " HS_EVENT11 ,Handshake event 11 interrupt" "No interrupt,Interrupt"
eventfld.long 0x10 10. " HS_EVENT10 ,Handshake event 10 interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x10 9. " HS_EVENT9 ,Handshake event 9 interrupt" "No interrupt,Interrupt"
eventfld.long 0x10 8. " HS_EVENT8 ,Handshake event 8 interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x10 7. " HS_EVENT7 ,Handshake event 7 interrupt" "No interrupt,Interrupt"
eventfld.long 0x10 6. " HS_EVENT6 ,Handshake event 6 interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x10 5. " HS_EVENT5 ,Handshake event 5 interrupt" "No interrupt,Interrupt"
eventfld.long 0x10 4. " HS_EVENT4 ,Handshake event 4 interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x10 3. " HS_EVENT3 ,Handshake event 3 interrupt" "No interrupt,Interrupt"
eventfld.long 0x10 2. " HS_EVENT2 ,Handshake event 2 interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x10 1. " HS_EVENT1 ,Handshake event 1 interrupt" "No interrupt,Interrupt"
eventfld.long 0x10 0. " HS_EVENT0 ,Handshake event 0 interrupt" "No interrupt,Interrupt"
line.long 0x0C "DPMHS_RES_REQ,DPM Host Side Reset Request"
hexmask.long.word 0x0C 8.--16. 1. " DEL_CNT[16:8] ,Delay counter value (not linear counting)"
textline " "
hexmask.long.byte 0x0C 0.--7. 1. " CONTROL[7:0]/DEL_CNT[7:0] ,Initiation sequence control/Delay counter value (not linear value)"
line.long 0x08 "DPMHS_SYS_STA,DPM Host Side System Status"
hexmask.long.byte 0x08 8.--15. 1. " NETX_STA_CODE ,NetX status code"
hexmask.long.byte 0x08 4.--7. 1. " HOST_STATE[3:0] ,User defined host status signals"
textline " "
hexmask.long.byte 0x08 2.--3. 1. " NETX_STATE[1:0] ,User defined netX status signals"
bitfld.long 0x08 1. " RUN ,Signal Level of the RUN LED output" "Low,High"
textline " "
bitfld.long 0x08 0. " RDY ,Signal level of the RDY LED output" "Low,High"
line.long 0x04 "DPMHS_TMR_START_VALUE,DPM Host Side Timer Start Value"
hexmask.long.word 0x04 0.--15. 1. " TMR_START ,Timer start value for count down or cyclic reload"
line.long 0x00 "DPMHS_TMR_CTRL,DPM Host Side Timer Control"
bitfld.long 0x00 15. " START ,Start Timer Count" "Not started,Started"
bitfld.long 0x00 3. " FNCT ,Timer mode function" "Not reloaded,Reloaded"
textline " "
bitfld.long 0x00 0.--2. " CLKDIV ,Timer clock divider" "100 us,10 us,1 us,100 ns,?..."
group.long 0xC8++0x3
line.long 0x0 "DPMHS_WDG_ARM_TIMEOUT,DPM Host Side Watchdog ARM"
hexmask.long.word 0x0 0.--15. 1. " TIMEOUT_VAL ,Timeout value"
group.long 0xC4++0x3
line.long 0x0 "DPMHS_WDG_HOST_TRIG,DPM Host Side Watchdog Host Trigger"
hexmask.long.byte 0x0 0.--7. 1. " WDG_TRIGGER_CODE ,Watchdog trigger code"
rgroup.long 0xC0++0x0B
line.long 0x00 "DPMHS_WDG_HOST_TIMEOUT,DPM Host Side Watchdog Host Timeout"
hexmask.long.word 0x00 0.--15. 1. " TIMEOUT_VAL ,Timeout value"
base ad:0x00000000
hgroup.long 0x00++0x03
hide.long 0x00 "DPM_HSRP,DPM Host Side Handshake Register Pair"
button "DPM_HSRP" " data ad:0x00000000++0xFDFF /long"
width 0x0B
tree.end
tree "Dual-Port Memory ARM Side (DPMAS)"
base asd:0x1c003000
width 22.
tree "DPMAS_HSCR (DPM ARM Side Handshake Control Registers)"
group.long 0x680++0x03F
line.long 0x0 "DPM_ARM_HS_CTRL0,DPM ARM Side Handshake Control Register 0"
bitfld.long 0x0 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x0 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x0 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x4 "DPM_ARM_HS_CTRL1,DPM ARM Side Handshake Control Register 1"
bitfld.long 0x4 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x4 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x4 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x8 "DPM_ARM_HS_CTRL2,DPM ARM Side Handshake Control Register 2"
bitfld.long 0x8 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x8 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x8 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0xC "DPM_ARM_HS_CTRL3,DPM ARM Side Handshake Control Register 3"
bitfld.long 0xC 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0xC 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0xC 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x10 "DPM_ARM_HS_CTRL4,DPM ARM Side Handshake Control Register 4"
bitfld.long 0x10 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x10 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x10 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x14 "DPM_ARM_HS_CTRL5,DPM ARM Side Handshake Control Register 5"
bitfld.long 0x14 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x14 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x14 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x18 "DPM_ARM_HS_CTRL6,DPM ARM Side Handshake Control Register 6"
bitfld.long 0x18 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x18 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x18 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x1C "DPM_ARM_HS_CTRL7,DPM ARM Side Handshake Control Register 7"
bitfld.long 0x1C 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x1C 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x1C 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x20 "DPM_ARM_HS_CTRL8,DPM ARM Side Handshake Control Register 8"
bitfld.long 0x20 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x20 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x20 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x24 "DPM_ARM_HS_CTRL9,DPM ARM Side Handshake Control Register 9"
bitfld.long 0x24 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x24 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x24 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x28 "DPM_ARM_HS_CTRL10,DPM ARM Side Handshake Control Register 10"
bitfld.long 0x28 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x28 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x28 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x2C "DPM_ARM_HS_CTRL11,DPM ARM Side Handshake Control Register 11"
bitfld.long 0x2C 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x2C 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x2C 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x30 "DPM_ARM_HS_CTRL12,DPM ARM Side Handshake Control Register 12"
bitfld.long 0x30 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x30 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x30 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x34 "DPM_ARM_HS_CTRL13,DPM ARM Side Handshake Control Register 13"
bitfld.long 0x34 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x34 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x34 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x38 "DPM_ARM_HS_CTRL14,DPM ARM Side Handshake Control Register 14"
bitfld.long 0x38 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x38 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x38 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
line.long 0x3C "DPM_ARM_HS_CTRL15,DPM ARM Side Handshake Control Register 15"
bitfld.long 0x3C 31. " ENABLE ,Handshake register pair function enabled" "Disabled,Enabled"
hexmask.long.word 0x3C 2.--15. 0x4 " DPM_BASE_ADDR ,Base address of handshake register pair in Dual-Port memory"
textline " "
bitfld.long 0x3C 0. " 8/16_BIT ,Select the handshake register pair width" "8 bit,16 bit"
tree.end
tree "Data Block End And Mapping"
group.long 0x640++0x03F
line.long 0x0 "DPM_ARM_DB_END0,DPM ARM Side Data Block 0 End"
bitfld.long 0x0 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
hexmask.long.byte 0x0 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
line.long 0x8 "DPM_ARM_DB_END1,DPM ARM Side Data Block 1 End"
bitfld.long 0x8 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
hexmask.long.byte 0x8 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
textline " "
line.long 0x10 "DPM_ARM_DB_END2,DPM ARM Side Data Block 2 End"
bitfld.long 0x10 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
hexmask.long.byte 0x10 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
line.long 0x18 "DPM_ARM_DB_END3,DPM ARM Side Data Block 3 End"
bitfld.long 0x18 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
hexmask.long.byte 0x18 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
line.long 0x20 "DPM_ARM_DB_END4,DPM ARM Side Data Block 4 End"
bitfld.long 0x20 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
hexmask.long.byte 0x20 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
line.long 0x28 "DPM_ARM_DB_END5,DPM ARM Side Data Block 5 End"
bitfld.long 0x28 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
hexmask.long.byte 0x28 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
line.long 0x30 "DPM_ARM_DB_END6,DPM ARM Side Data Block 6 End"
bitfld.long 0x30 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
hexmask.long.byte 0x30 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
line.long 0x38 "DPM_ARM_DB_END7,DPM ARM Side Data Block 7 End"
bitfld.long 0x38 31. " ENABLE ,Data Block Enable" "Disabled,Enabled"
hexmask.long.byte 0x38 8.--15. 1. " DATA_BLOCK_END ,Data Block End Address"
line.long 0x4 "DPM_ARM_DB_MAP0,DPM ARM Side Data Block 0 Address Mapping"
hexmask.long 0x4 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
line.long 0xC "DPM_ARM_DB_MAP1,DPM ARM Side Data Block 1 Address Mapping"
hexmask.long 0xC 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
line.long 0x14 "DPM_ARM_DB_MAP2,DPM ARM Side Data Block 2 Address Mapping"
hexmask.long 0x14 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
line.long 0x1C "DPM_ARM_DB_MAP3,DPM ARM Side Data Block 3 Address Mapping"
hexmask.long 0x1C 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
line.long 0x24 "DPM_ARM_DB_MAP4,DPM ARM Side Data Block 4 Address Mapping"
hexmask.long 0x24 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
line.long 0x2C "DPM_ARM_DB_MAP5,DPM ARM Side Data Block 5 Address Mapping"
hexmask.long 0x2C 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
line.long 0x34 "DPM_ARM_DB_MAP6,DPM ARM Side Data Block 6 Address Mapping"
hexmask.long 0x34 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
line.long 0x3C "DPM_ARM_DB_MAP7,DPM ARM Side Data Block 7 Address Mapping"
hexmask.long 0x3C 8.--31. 0x100 " NETX_MAP_ADDR ,Data block base address in netX memory range"
tree.end
tree "Input/Output Pins Control"
textline " "
group.long 0x630++0x0B
line.long 0x008 "DPM_ARM_IO_DATA1,DPM ARM Side Input / Output Data 1"
bitfld.long 0x08 21. " PIO_DATA85 ,Input/output pin level" "0,1"
bitfld.long 0x08 20. " PIO_DATA84 ,Input/output pin level" "0,1"
bitfld.long 0x08 19. " PIO_DATA83 ,Input/output pin level" "0,1"
bitfld.long 0x08 18. " PIO_DATA82 ,Input/output pin level" "0,1"
textline " "
bitfld.long 0x08 17. " PIO_DATA81 ,Input/output pin level" "0,1"
bitfld.long 0x08 16. " PIO_DATA80 ,Input/output pin level" "0,1"
bitfld.long 0x08 15. " PIO_DATA79 ,Input/output pin level" "0,1"
textline " "
bitfld.long 0x08 14. " PIO_DATA78 ,Input/output pin level" "0,1"
bitfld.long 0x08 13. " PIO_DATA77 ,Input/output pin level" "0,1"
bitfld.long 0x08 12. " PIO_DATA76 ,Input/output pin level" "0,1"
bitfld.long 0x08 11. " PIO_DATA75 ,Input/output pin level" "0,1"
textline " "
bitfld.long 0x08 10. " PIO_DATA74 ,Input/output pin level" "0,1"
bitfld.long 0x08 9. " PIO_DATA73 ,Input/output pin level" "0,1"
bitfld.long 0x08 8. " PIO_DATA72 ,Input/output pin level" "0,1"
bitfld.long 0x08 7. " PIO_DATA71 ,Input/output pin level" "0,1"
textline " "
bitfld.long 0x08 6. " PIO_DATA70 ,Input/output pin level" "0,1"
bitfld.long 0x08 5. " PIO_DATA69 ,Input/output pin level" "0,1"
bitfld.long 0x08 4. " PIO_DATA68 ,Input/output pin level" "0,1"
bitfld.long 0x08 3. " PIO_DATA67 ,Input/output pin level" "0,1"
textline " "
bitfld.long 0x08 2. " PIO_DATA66 ,Input/output pin level" "0,1"
bitfld.long 0x08 1. " PIO_DATA65 ,Input/output pin level" "0,1"
bitfld.long 0x08 0. " PIO_DATA64 ,Input/output pin level" "0,1"
line.long 0x004 "DPM_ARM_IO_DRV_EN1,DPM ARM Side Input / Output Driver Enable 1"
bitfld.long 0x04 21. " PIO_DRV85 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 20. " PIO_DRV84 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 19. " PIO_DRV83 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 18. " PIO_DRV82 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 17. " PIO_DRV81 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 16. " PIO_DRV80 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 15. " PIO_DRV79 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 14. " PIO_DRV78 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 13. " PIO_DRV77 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 12. " PIO_DRV76 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 11. " PIO_DRV75 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 10. " PIO_DRV74 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " PIO_DRV73 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 8. " PIO_DRV72 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 7. " PIO_DRV71 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 6. " PIO_DRV70 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 5. " PIO_DRV69 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 4. " PIO_DRV68 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " PIO_DRV67 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 2. " PIO_DRV66 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 1. " PIO_DRV65 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " PIO_DRV64 ,I/O Pin driver output enable" "Disabled,Enabled"
line.long 0x00 "DPM_ARM_IO_MODE1,DPM ARM Side Input / Output Mode 1"
bitfld.long 0x00 30.--31. " IN_CONTROL ,Input data control" "NPOR,100 MHz,PIO[77] low,PIO[77] high"
textline " "
bitfld.long 0x00 21. " PIO_MODE85 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 20. " PIO_MODE84 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 19. " PIO_MODE83 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 18. " PIO_MODE82 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 17. " PIO_MODE81 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 16. " PIO_MODE80 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 15. " PIO_MODE79 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 14. " PIO_MODE78 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 13. " PIO_MODE77 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 12. " PIO_MODE76 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 11. " PIO_MODE75 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 10. " PIO_MODE74 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 9. " PIO_MODE73 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 8. " PIO_MODE72 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 7. " PIO_MODE71 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 6. " PIO_MODE70 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 5. " PIO_MODE69 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 4. " PIO_MODE68 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 3. " PIO_MODE67 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 2. " PIO_MODE66 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 1. " PIO_MODE65 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 0. " PIO_MODE64 ,Pin mode selection" "PIO,Host interface"
group.long 0x620++0x00B
line.long 0x08 "DPM_ARM_IO_DATA0,DPM ARM Side Input / Output Data 0"
bitfld.long 0x08 31. " PIO_DATA63 ,Input/output pin level" "0,1"
bitfld.long 0x08 30. " PIO_DATA62 ,Input/output pin level" "0,1"
bitfld.long 0x08 29. " PIO_DATA61 ,Input/output pin level" "0,1"
bitfld.long 0x08 28. " PIO_DATA60 ,Input/output pin level" "0,1"
textline " "
bitfld.long 0x08 27. " PIO_DATA59 ,Input/output pin level" "0,1"
bitfld.long 0x08 26. " PIO_DATA58 ,Input/output pin level" "0,1"
bitfld.long 0x08 25. " PIO_DATA57 ,Input/output pin level" "0,1"
bitfld.long 0x08 24. " PIO_DATA56 ,Input/output pin level" "0,1"
textline " "
bitfld.long 0x08 23. " PIO_DATA55 ,Input/output pin level" "0,1"
bitfld.long 0x08 22. " PIO_DATA54 ,Input/output pin level" "0,1"
bitfld.long 0x08 21. " PIO_DATA53 ,Input/output pin level" "0,1"
bitfld.long 0x08 20. " PIO_DATA52 ,Input/output pin level" "0,1"
textline " "
bitfld.long 0x08 19. " PIO_DATA51 ,Input/output pin level" "0,1"
bitfld.long 0x08 18. " PIO_DATA50 ,Input/output pin level" "0,1"
bitfld.long 0x08 17. " PIO_DATA49 ,Input/output pin level" "0,1"
bitfld.long 0x08 16. " PIO_DATA48 ,Input/output pin level" "0,1"
textline " "
bitfld.long 0x08 15. " PIO_DATA47 ,Input/output pin level" "0,1"
bitfld.long 0x08 14. " PIO_DATA46 ,Input/output pin level" "0,1"
bitfld.long 0x08 13. " PIO_DATA45 ,Input/output pin level" "0,1"
bitfld.long 0x08 12. " PIO_DATA44 ,Input/output pin level" "0,1"
textline " "
bitfld.long 0x08 11. " PIO_DATA43 ,Input/output pin level" "0,1"
bitfld.long 0x08 10. " PIO_DATA42 ,Input/output pin level" "0,1"
bitfld.long 0x08 9. " PIO_DATA41 ,Input/output pin level" "0,1"
bitfld.long 0x08 8. " PIO_DATA40 ,Input/output pin level" "0,1"
textline " "
bitfld.long 0x08 7. " PIO_DATA39 ,Input/output pin level" "0,1"
bitfld.long 0x08 6. " PIO_DATA38 ,Input/output pin level" "0,1"
bitfld.long 0x08 5. " PIO_DATA37 ,Input/output pin level" "0,1"
bitfld.long 0x08 4. " PIO_DATA36 ,Input/output pin level" "0,1"
textline " "
bitfld.long 0x08 3. " PIO_DATA35 ,Input/output pin level" "0,1"
bitfld.long 0x08 2. " PIO_DATA34 ,Input/output pin level" "0,1"
bitfld.long 0x08 1. " PIO_DATA33 ,Input/output pin level" "0,1"
bitfld.long 0x08 0. " PIO_DATA32 ,Input/output pin level" "0,1"
line.long 0x04 "DPM_ARM_IO_DRV_EN0,DPM ARM Side Input / Output Driver Enable 0"
bitfld.long 0x04 31. " PIO_DRV63 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 30. " PIO_DRV62 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 29. " PIO_DRV61 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " PIO_DRV60 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 27. " PIO_DRV59 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 26. " PIO_DRV58 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 25. " PIO_DRV57 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 24. " PIO_DRV56 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 23. " PIO_DRV55 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 22. " PIO_DRV54 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 21. " PIO_DRV53 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 20. " PIO_DRV52 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " PIO_DRV51 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 18. " PIO_DRV50 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 17. " PIO_DRV49 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " PIO_DRV48 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 15. " PIO_DRV47 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 14. " PIO_DRV46 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 13. " PIO_DRV45 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 12. " PIO_DRV44 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 11. " PIO_DRV43 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " PIO_DRV43 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 10. " PIO_DRV42 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 9. " PIO_DRV41 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 8. " PIO_DRV40 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 7. " PIO_DRV39 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 6. " PIO_DRV38 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " PIO_DRV37 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 4. " PIO_DRV36 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 3. " PIO_DRV35 ,I/O Pin driver output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 2. " PIO_DRV34 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 1. " PIO_DRV33 ,I/O Pin driver output enable" "Disabled,Enabled"
bitfld.long 0x04 0. " PIO_DRV32 ,I/O Pin driver output enable" "Disabled,Enabled"
line.long 0x00 "DPM_ARM_IO_MODE0,DPM ARM Side Input / Output Mode 0"
bitfld.long 0x00 31. " PIO_MODE63 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 30. " PIO_MODE62 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 29. " PIO_MODE61 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 28. " PIO_MODE60 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 27. " PIO_MODE59 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 26. " PIO_MODE58 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 25. " PIO_MODE57 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 24. " PIO_MODE56 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 23. " PIO_MODE55 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 22. " PIO_MODE54 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 21. " PIO_MODE53 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 20. " PIO_MODE52 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 19. " PIO_MODE51 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 18. " PIO_MODE50 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 17. " PIO_MODE49 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 16. " PIO_MODE48 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 15. " PIO_MODE47 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 14. " PIO_MODE46 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 13. " PIO_MODE45 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 12. " PIO_MODE44 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 11. " PIO_MODE43 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 10. " PIO_MODE42 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 9. " PIO_MODE41 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 8. " PIO_MODE40 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 7. " PIO_MODE39 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 6. " PIO_MODE38 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 5. " PIO_MODE37 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 4. " PIO_MODE36 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 3. " PIO_MODE35 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 2. " PIO_MODE34 ,Pin mode selection" "PIO,Host interface"
textline " "
bitfld.long 0x00 1. " PIO_MODE33 ,Pin mode selection" "PIO,Host interface"
bitfld.long 0x00 0. " PIO_MODE32 ,Pin mode selection" "PIO,Host interface"
tree.end
tree "Interface and Clockout Configuration"
group.long 0x604++0x00B
line.long 0x008 "DPM_ARM_IF_CFG1,DPM ARM Side Interface Configuration Register 1"
bitfld.long 0x008 31. " WRITE_PROTECT ,Write protection" "Disabled,Enabled"
bitfld.long 0x008 30. " IRQ_POL_PIO72 ,External interrupt polarity for PIO[72]" "Low,High"
textline " "
bitfld.long 0x008 29. " IRQ_POL_PIO47 ,External interrupt polarity for PIO[47]" "Low,High"
bitfld.long 0x008 28. " IRQ_POL_PIO40 ,External interrupt polarity for PIO[40]" "Low,High"
textline " "
bitfld.long 0x008 27. " IRQ_POL_PIO36 ,External interrupt polarity for PIO[36]" "Low,High"
bitfld.long 0x008 26. " IRQ_POL_PIO35 ,External interrupt polarity for PIO[35]" "Low,High"
textline " "
bitfld.long 0x008 24.--25. " DATAOUT_VALID_TIME ,This value sets the valid read data output time in system clocks" "0,1,2,3"
bitfld.long 0x008 23. " DIS_BUSY_TIMEOUT ,Disable busy timeout" "Enabled,Disabled"
textline " "
bitfld.long 0x008 19. " ADR_IN15 ,Logical level for Dual-Port memory address line 15" "Low,High"
bitfld.long 0x008 18. " ADR_IN14 ,Logical level for Dual-Port memory address line 14" "Low,High"
textline " "
bitfld.long 0x008 17. " ADR_IN13 ,Logical level for Dual-Port memory address line 13" "Low,High"
bitfld.long 0x008 16. " ADR_IN12 ,Logical level for Dual-Port memory address line 12" "Low,High"
textline " "
bitfld.long 0x008 15. " CS_COMP_SRC19 ,Chip select compare source for address 19" "Internal,External"
bitfld.long 0x008 14. " CS_COMP_SRC18 ,Chip select compare source for address 18" "Internal,External"
textline " "
bitfld.long 0x008 13. " CS_COMP_SRC17 ,Chip select compare source for address 17" "Internal,External"
bitfld.long 0x008 12. " CS_COMP_SRC16 ,Chip select compare source for address 16" "Internal,External"
textline " "
bitfld.long 0x008 11. " CS_COMP_SRC15 ,Chip select compare source for address 15" "Internal,External"
bitfld.long 0x008 10. " CS_COMP_SRC14 ,Chip select compare source for address 14" "Internal,External"
textline " "
bitfld.long 0x008 9. " CS_COMP_SRC13 ,Chip select compare source for address 13" "Internal,External"
bitfld.long 0x008 8. " CS_COMP_SRC12 ,Chip select compare source for address 12" "Internal,External"
textline " "
hexmask.long.byte 0x008 0.--7. 1. " CS_COMP_VAL[19:12] ,Chip Select compare value"
line.long 0x004 "DPM_ARM_IF_CFG0,DPM ARM Side Host Interface Configuration Register 0"
bitfld.long 0x004 31. " DISABLE_WR ,Write access to the register" "Enabled,Disabled"
textline " "
bitfld.long 0x004 28.--30. " HIF_MODE ,Host interface mode selection" "Disabled,Extension Bus,uP Bus 8 bit,uP Bus 16 bit,I/O Mode,uP Bus 32 bit,?..."
textline " "
bitfld.long 0x004 26.--27. " RD_CTRL ,Configure the control lines for Dual-Port memory read accesses to netX" "RDn;PIO[52],RDn/A0/BHEn;PIO[52/73/43],Disabled,RDn/BHEn;PIO[52/43]"
textline " "
bitfld.long 0x004 24.--25. " WR_CTRL ,Configure the control lines for Dual-Port memory write accesses to netX" "WRLn;PIO[45],RDn/A0/BHEn;PIO[52/72/43],WRLn/WRHn;PIO[45/44],RDn/BHEn;PIO[52/43]"
textline " "
bitfld.long 0x004 21.--23. " BE1_MODE ,Byte Enable 1 selection" "Low BHEn;PIO[43],High A0;PIO[73],Low RDn/WRLn;PIO[52/45],Low RDn/WRHnPIO[52/44],High internal A0,High BHEn;PIO[43],High activation,High activation"
textline " "
bitfld.long 0x004 18.--20. " BE0_MODE ,Byte Enable 0 selection" "Low CS0n;PIO[51],Low A0;PIO[73],Low RDn/WRLn;PIO[52/45],Low internal A0,Low activation,Low activation,Low activation,Low activation"
textline " "
bitfld.long 0x004 16.--17. " CIS_MODE ,The CIS memory array select" "Never,Always,Low WRHn,Low PIO[40]"
textline " "
bitfld.long 0x004 14.--15. " WAIT_DRV ,Wait mode output drive control; RDY / PIO[46]" "Tri-state,Push/pull,Open drain/source,Sustained tri-state"
textline " "
bitfld.long 0x004 13. " WAIT_MODE ,WAIT/BUSY or READY mode function" "Wait,Ready"
textline " "
bitfld.long 0x004 12. " WAIT_POLARITY ,Active polarity output" "Low,High"
textline " "
bitfld.long 0x004 9.--11. " CS_MODE ,Configure the logic for chip select generation" "Disabled,Internal,Low CS0n/BHEn;PIO[51/43],High CS0n/BHEn;PIO[51/43],Low CS0n PIO[51],Disabled,Low ALE;PIO[35],High ALE;PIO[35]"
textline " "
bitfld.long 0x004 7.--8. " IRQ_MODE ,Select the interrupt pin output function of IRQ / INT pin (PIO[47])" "Tri-state,Fixed level,Push/pull,Open drain/source"
textline " "
bitfld.long 0x004 6. " IRQ_POLARITY ,Active polarity output" "Low,High"
textline " "
bitfld.long 0x004 4.--5. " ALE_MODE ,Selection of address input latching mode (PIO[35] == ALE/AEN)" "Low,High,Falling,Rising"
textline " "
bitfld.long 0x004 3. " ADDR_MODE ,8/16 bit address mode" "Non multiplexed,Multiplexed"
textline " "
bitfld.long 0x004 0.--2. " OE_MODE ,Output driver control of data lines for read accesses" "High RDn low BHe/low A0;PIO[52/43/73],Low RDn BHE/low A0;PIO[52/43/73],Low RDn;PIO[52],Low RDn CS0n/low BHEn;PIO[52/43/51],High RDn BHEn;PIO[52/43],Reserved,RDn/BE[3:0],RD/WRn/BE[3:0]"
line.long 0x000 "DPMAS_CLKOUT_CONF,DPM ARM Side Clock out configuration"
bitfld.long 0x000 31. " CLKOUT_EN ,CLKOUT driver enable" "Disabled,Enabled"
textline " "
hexmask.long 0x000 0.--29. 1. " CLK_SEL ,Clockout frequency selection"
tree.end
tree "DPM_ARM_HS_DATA (DPM ARM View Handshake Registers)"
hgroup.long 0x500++0x003
hide.long 0x000 "DPM_ARM_HS_DATA0,DPM ARM View Handshake Register 0"
in
hgroup.long 0x504++0x003
hide.long 0x000 "DPM_ARM_HS_DATA1,DPM ARM View Handshake Register 1"
in
hgroup.long 0x508++0x003
hide.long 0x000 "DPM_ARM_HS_DATA2,DPM ARM View Handshake Register 2"
in
hgroup.long 0x50C++0x003
hide.long 0x000 "DPM_ARM_HS_DATA3,DPM ARM View Handshake Register 3"
in
hgroup.long 0x510++0x003
hide.long 0x000 "DPM_ARM_HS_DATA4,DPM ARM View Handshake Register 4"
in
hgroup.long 0x514++0x003
hide.long 0x000 "DPM_ARM_HS_DATA5,DPM ARM View Handshake Register 5"
in
hgroup.long 0x518++0x003
hide.long 0x000 "DPM_ARM_HS_DATA6,DPM ARM View Handshake Register 6"
in
hgroup.long 0x51C++0x003
hide.long 0x000 "DPM_ARM_HS_DATA7,DPM ARM View Handshake Register 7"
in
hgroup.long 0x520++0x003
hide.long 0x000 "DPM_ARM_HS_DATA8,DPM ARM View Handshake Register 8"
in
hgroup.long 0x524++0x003
hide.long 0x000 "DPM_ARM_HS_DATA9,DPM ARM View Handshake Register 9"
in
hgroup.long 0x528++0x003
hide.long 0x000 "DPM_ARM_HS_DATA10,DPM ARM View Handshake Register 10"
in
hgroup.long 0x52C++0x003
hide.long 0x000 "DPM_ARM_HS_DATA11,DPM ARM View Handshake Register 11"
in
hgroup.long 0x530++0x003
hide.long 0x000 "DPM_ARM_HS_DATA12,DPM ARM View Handshake Register 12"
in
hgroup.long 0x534++0x003
hide.long 0x000 "DPM_ARM_HS_DATA13,DPM ARM View Handshake Register 13"
in
hgroup.long 0x538++0x003
hide.long 0x000 "DPM_ARM_HS_DATA14,DPM ARM View Handshake Register 14"
in
hgroup.long 0x53C++0x003
hide.long 0x000 "DPM_ARM_HS_DATA15,DPM ARM View Handshake Register 15"
in
wgroup 0x0++0x0
tree.end
tree "Interrupt Registers"
textline " "
group.long 0x4F0++0x003
line.long 0x000 "DPM_ARM_INT_EN0,DPM ARM Side Interrupt Enable 0"
bitfld.long 0x000 31. " GLB_EN ,Global Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x000 30. " MEM_LCK ,Memory Lock Error" "Disabled,Enabled"
textline " "
bitfld.long 0x000 29. " WDG ,Watchdog timeout host supervision" "Disabled,Enabled"
bitfld.long 0x000 28. " INT_PIO72 ,External interrupt enable for pin PIO72" "Disabled,Enabled"
textline " "
bitfld.long 0x000 27. " INT_PIO47 ,External interrupt enable for pin PIO47" "Disabled,Enabled"
bitfld.long 0x000 26. " INT_PIO40 ,External interrupt enable for pin PIO40" "Disabled,Enabled"
textline " "
bitfld.long 0x000 25. " INT_PIO36 ,External interrupt enable for pin PIO36" "Disabled,Enabled"
bitfld.long 0x000 24. " INT_PIO35 ,External interrupt enable for pin PIO35" "Disabled,Enabled"
textline " "
bitfld.long 0x000 15. " HS15 ,Handshake event enable 15" "Disabled,Enabled"
bitfld.long 0x000 14. " HS14 ,Handshake event enable 14" "Disabled,Enabled"
textline " "
bitfld.long 0x000 13. " HS13 ,Handshake event enable 13" "Disabled,Enabled"
bitfld.long 0x000 12. " HS12 ,Handshake event enable 12" "Disabled,Enabled"
textline " "
bitfld.long 0x000 11. " HS11 ,Handshake event enable 11" "Disabled,Enabled"
bitfld.long 0x000 10. " HS10 ,Handshake event enable 10" "Disabled,Enabled"
textline " "
bitfld.long 0x000 9. " HS9 ,Handshake event enable 9" "Disabled,Enabled"
bitfld.long 0x000 8. " HS8 ,Handshake event enable 8" "Disabled,Enabled"
textline " "
bitfld.long 0x000 7. " HS7 ,Handshake event enable 7" "Disabled,Enabled"
bitfld.long 0x000 6. " HS6 ,Handshake event enable 6" "Disabled,Enabled"
textline " "
bitfld.long 0x000 5. " HS5 ,Handshake event enable 5" "Disabled,Enabled"
bitfld.long 0x000 4. " HS4 ,Handshake event enable 4" "Disabled,Enabled"
textline " "
bitfld.long 0x000 3. " HS3 ,Handshake event enable 3" "Disabled,Enabled"
bitfld.long 0x000 2. " HS2 ,Handshake event enable 2" "Disabled,Enabled"
textline " "
bitfld.long 0x000 1. " HS1 ,Handshake event enable 1" "Disabled,Enabled"
bitfld.long 0x000 0. " HS0 ,Handshake event enable 0" "Disabled,Enabled"
group.long 0x4E0++0x003
line.long 0x0 "DPM_ARM_INT_STAT0,DPM ARM Side Interrupt Status 0"
eventfld.long 0x000 31. " IRQ_REQ ,Global signaling of interrupt request" "No interrupt,Interrupt"
textline " "
eventfld.long 0x000 30. " MEM_LCK ,Memory Lock Error" "No error,Error"
textline " "
eventfld.long 0x000 29. " WDG_IRQ ,Watchdog timeout host supervision" "No supervision,Supervision"
textline " "
eventfld.long 0x000 28. " INT_PIO72 ,External interrupt enable for pin PIO72" "No interrupt,Interrupt"
textline " "
eventfld.long 0x000 27. " INT_PIO47 ,External interrupt enable for pin PIO47" "No interrupt,Interrupt"
textline " "
eventfld.long 0x000 26. " INT_PIO40 ,External interrupt enable for pin PIO40" "No interrupt,Interrupt"
textline " "
eventfld.long 0x000 25. " INT_PIO36 ,External interrupt enable for pin PIO36" "No interrupt,Interrupt"
textline " "
eventfld.long 0x000 24. " INT_PIO35 ,External interrupt enable for pin PIO35" "No interrupt,Interrupt"
textline " "
hexmask.long.byte 0x000 16.--23. 1. " IRQ_VECTOR[7:0] ,Interrupt Vector generated by the interrupt status flags"
textline " "
eventfld.long 0x000 15. " HS15 ,Handshake event status 15" "No interrupt,Interrupt"
eventfld.long 0x000 14. " HS14 ,Handshake event status 14" "No interrupt,Interrupt"
textline " "
eventfld.long 0x000 13. " HS13 ,Handshake event status 13" "No interrupt,Interrupt"
eventfld.long 0x000 12. " HS12 ,Handshake event status 12" "No interrupt,Interrupt"
textline " "
eventfld.long 0x000 11. " HS11 ,Handshake event status 11" "No interrupt,Interrupt"
eventfld.long 0x000 10. " HS10 ,Handshake event status 10" "No interrupt,Interrupt"
textline " "
eventfld.long 0x000 9. " HS9 ,Handshake event status 9" "No interrupt,Interrupt"
eventfld.long 0x000 8. " HS8 ,Handshake event status 8" "No interrupt,Interrupt"
textline " "
eventfld.long 0x000 7. " HS7 ,Handshake event status 7" "No interrupt,Interrupt"
eventfld.long 0x000 6. " HS6 ,Handshake event status 6" "No interrupt,Interrupt"
textline " "
eventfld.long 0x000 5. " HS5 ,Handshake event status 5" "No interrupt,Interrupt"
eventfld.long 0x000 4. " HS4 ,Handshake event status 4" "No interrupt,Interrupt"
textline " "
eventfld.long 0x000 3. " HS3 ,Handshake event status 3" "No interrupt,Interrupt"
eventfld.long 0x000 2. " HS2 ,Handshake event status 2" "No interrupt,Interrupt"
textline " "
eventfld.long 0x000 1. " HS1 ,Handshake event status 1" "No interrupt,Interrupt"
eventfld.long 0x000 0. " HS0 ,Handshake event status 0" "No interrupt,Interrupt"
tree.end
tree "WDG, CIS, Extension Bus, Handshake Data AND SYS Status Registers"
group.long 0x4Cc++0x03
line.long 0x00 "DPM_ARM_WDGA_TRIG,DPM ARM Side Watchdog ARM Supervision Trigger"
hexmask.long.byte 0x00 0.--7. 1. " WDG_ACCESS_CODE ,Watchdog access code for triggering"
rgroup.long 0x4C8++0x03
line.long 0x00 "DPM_ARM_WDG_ARM_TOUT,DPM ARM Side Watchdog ARM Timeout"
hexmask.long.word 0x00 0.--15. 1. " TIMEOUT_VAL ,Timeout value"
group.long 0x4BC++0x007
line.long 0x004 "DPM_ARM_WDG_HOST_TOUT,DPM ARM Side Watchdog Host Timeout"
hexmask.long.word 0x004 0.--15. 1. " TIMEOUT_VAL ,Timeout value"
line.long 0x000 "DPM_ARM_CIS_MAP,DPM ARM Side CIS Mapping Address"
hexmask.long.tbyte 0x000 8.--31. 1. " CIS_MAPPING ,CIS Mapping Address"
textline " "
bitfld.long 0x000 1. " WR_ENABLE ,Write accesses to the CIS enable" "Disabled,Enabled"
textline " "
bitfld.long 0x000 0. " CIS_ENABLE ,Enable CIS MODE" "Disabled,Enabled"
tree.end
width 0x0B
tree.end
tree.end
tree.open "Peripheral Functions"
tree "General Purpose IOs (GPIO)"
base asd:0x1c000800
width 15.
group.long 0x00++0x7f
line.long 0x0 "GPIO_CFG0,GPIO 0 Configuration register"
bitfld.long 0x0 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x0 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x0 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x4 "GPIO_CFG1,GPIO 1 Configuration register"
bitfld.long 0x4 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x4 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x4 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x8 "GPIO_CFG2,GPIO 2 Configuration register"
bitfld.long 0x8 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x8 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x8 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0xC "GPIO_CFG3,GPIO 3 Configuration register"
bitfld.long 0xC 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0xC 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0xC 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x10 "GPIO_CFG4,GPIO 4 Configuration register"
bitfld.long 0x10 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x10 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x10 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x14 "GPIO_CFG5,GPIO 5 Configuration register"
bitfld.long 0x14 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x14 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x14 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x18 "GPIO_CFG6,GPIO 6 Configuration register"
bitfld.long 0x18 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x18 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x18 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x1C "GPIO_CFG7,GPIO 7 Configuration register"
bitfld.long 0x1C 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x1C 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x1C 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x20 "GPIO_CFG8,GPIO 8 Configuration register"
bitfld.long 0x20 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x20 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x20 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x24 "GPIO_CFG9,GPIO 9 Configuration register"
bitfld.long 0x24 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x24 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x24 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x28 "GPIO_CFG10,GPIO 10 Configuration register"
bitfld.long 0x28 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x28 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x28 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x2C "GPIO_CFG11,GPIO 11 Configuration register"
bitfld.long 0x2C 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x2C 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x2C 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x30 "GPIO_CFG12,GPIO 12 Configuration register"
bitfld.long 0x30 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x30 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x30 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x34 "GPIO_CFG13,GPIO 13 Configuration register"
bitfld.long 0x34 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x34 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x34 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x38 "GPIO_CFG14,GPIO 14 Configuration register"
bitfld.long 0x38 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x38 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x38 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x3C "GPIO_CFG15,GPIO 15 Configuration register"
bitfld.long 0x3C 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x3C 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x3C 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x40 "GPIO_CFG16,GPIO 16 Configuration register"
bitfld.long 0x40 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x40 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x40 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x44 "GPIO_CFG17,GPIO 17 Configuration register"
bitfld.long 0x44 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x44 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x44 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x48 "GPIO_CFG18,GPIO 18 Configuration register"
bitfld.long 0x48 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x48 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x48 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x4C "GPIO_CFG19,GPIO 19 Configuration register"
bitfld.long 0x4C 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x4C 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x4C 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x50 "GPIO_CFG20,GPIO 20 Configuration register"
bitfld.long 0x50 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x50 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x50 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x54 "GPIO_CFG21,GPIO 21 Configuration register"
bitfld.long 0x54 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x54 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x54 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x58 "GPIO_CFG22,GPIO 22 Configuration register"
bitfld.long 0x58 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x58 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x58 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x5C "GPIO_CFG23,GPIO 23 Configuration register"
bitfld.long 0x5C 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x5C 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x5C 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x60 "GPIO_CFG24,GPIO 24 Configuration register"
bitfld.long 0x60 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x60 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x60 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x64 "GPIO_CFG25,GPIO 25 Configuration register"
bitfld.long 0x64 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x64 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x64 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x68 "GPIO_CFG26,GPIO 26 Configuration register"
bitfld.long 0x68 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x68 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x68 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x6C "GPIO_CFG27,GPIO 27 Configuration register"
bitfld.long 0x6C 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x6C 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x6C 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x70 "GPIO_CFG28,GPIO 28 Configuration register"
bitfld.long 0x70 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x70 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x70 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x74 "GPIO_CFG29,GPIO 29 Configuration register"
bitfld.long 0x74 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x74 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x74 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x78 "GPIO_CFG30,GPIO 30 Configuration register"
bitfld.long 0x78 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x78 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x78 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
line.long 0x7C "GPIO_CFG31,GPIO 31 Configuration register"
bitfld.long 0x7C 5.--7. " COUNT_REF ,Counter reference" "Counter 0,Counter 1,Counter 2,Counter 3,Counter 4,Reserved,Reserved,System time"
bitfld.long 0x7C 4. " INV ,Inversion" "Not inverted,Inverted"
textline " "
bitfld.long 0x7C 0.--3. " MODE ,I/O Mode" "[IN]read mode,[IN]capture continued at rising edge,[IN]capture once at rising edge,[IN]capture once at high level,[OUT]set to 0,[OUT]set to 1,[OUT]set to line,[OUT]PWM,IO-Link mode,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Pwm2-mode"
width 18.
group.long 0x080++0x7f
line.long 0x0 "GPIO_THRSH_CAPT0,GPIO 0 Threshhold/Capture register"
line.long 0x4 "GPIO_THRSH_CAPT1,GPIO 1 Threshhold/Capture register"
line.long 0x8 "GPIO_THRSH_CAPT2,GPIO 2 Threshhold/Capture register"
line.long 0xC "GPIO_THRSH_CAPT3,GPIO 3 Threshhold/Capture register"
line.long 0x10 "GPIO_THRSH_CAPT4,GPIO 4 Threshhold/Capture register"
line.long 0x14 "GPIO_THRSH_CAPT5,GPIO 5 Threshhold/Capture register"
line.long 0x18 "GPIO_THRSH_CAPT6,GPIO 6 Threshhold/Capture register"
line.long 0x1C "GPIO_THRSH_CAPT7,GPIO 7 Threshhold/Capture register"
line.long 0x20 "GPIO_THRSH_CAPT8,GPIO 8 Threshhold/Capture register"
line.long 0x24 "GPIO_THRSH_CAPT9,GPIO 9 Threshhold/Capture register"
line.long 0x28 "GPIO_THRSH_CAPT10,GPIO 10 Threshhold/Capture register"
line.long 0x2C "GPIO_THRSH_CAPT11,GPIO 11 Threshhold/Capture register"
line.long 0x30 "GPIO_THRSH_CAPT12,GPIO 12 Threshhold/Capture register"
line.long 0x34 "GPIO_THRSH_CAPT13,GPIO 13 Threshhold/Capture register"
line.long 0x38 "GPIO_THRSH_CAPT14,GPIO 14 Threshhold/Capture register"
line.long 0x3C "GPIO_THRSH_CAPT15,GPIO 15 Threshhold/Capture register"
line.long 0x40 "GPIO_THRSH_CAPT16,GPIO 16 Threshhold/Capture register"
line.long 0x44 "GPIO_THRSH_CAPT17,GPIO 17 Threshhold/Capture register"
line.long 0x48 "GPIO_THRSH_CAPT18,GPIO 18 Threshhold/Capture register"
line.long 0x4C "GPIO_THRSH_CAPT19,GPIO 19 Threshhold/Capture register"
line.long 0x50 "GPIO_THRSH_CAPT20,GPIO 20 Threshhold/Capture register"
line.long 0x54 "GPIO_THRSH_CAPT21,GPIO 21 Threshhold/Capture register"
line.long 0x58 "GPIO_THRSH_CAPT22,GPIO 22 Threshhold/Capture register"
line.long 0x5C "GPIO_THRSH_CAPT23,GPIO 23 Threshhold/Capture register"
line.long 0x60 "GPIO_THRSH_CAPT24,GPIO 24 Threshhold/Capture register"
line.long 0x64 "GPIO_THRSH_CAPT25,GPIO 25 Threshhold/Capture register"
line.long 0x68 "GPIO_THRSH_CAPT26,GPIO 26 Threshhold/Capture register"
line.long 0x6C "GPIO_THRSH_CAPT27,GPIO 27 Threshhold/Capture register"
line.long 0x70 "GPIO_THRSH_CAPT28,GPIO 28 Threshhold/Capture register"
line.long 0x74 "GPIO_THRSH_CAPT29,GPIO 29 Threshhold/Capture register"
line.long 0x78 "GPIO_THRSH_CAPT30,GPIO 30 Threshhold/Capture register"
line.long 0x7C "GPIO_THRSH_CAPT31,GPIO 31 Threshhold/Capture register"
width 16.
group.long 0x100++0x3 "GPIO Counter 0 "
line.long 0x00 "GPIO_CNTR0_CTRL,Counter 0 Control register"
bitfld.long 0x00 7.--11. " GPIO_REF ,GPIO reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4. " ONCE ,Run only once" "No (cyclic),Yes"
textline " "
bitfld.long 0x00 5.--6. " EVENT_ACT ,Event action" "Count every clock,Count external event,Watchdog mode,Run by external event"
bitfld.long 0x00 3. " SEL_EVENT ,Counter event" "High level,Positive edge"
textline " "
bitfld.long 0x00 2. " IRQ_EN ,IRQ enable" "Disabled,Enabled"
bitfld.long 0x00 1. " SYM/ASYM ,Symmetric" "Assymetric (sawtooth),Symmetric (triangle)"
textline " "
bitfld.long 0x00 0. " RUN ,Start/Stop" "Stop,Start"
group.long 0x114++0x3
line.long 0x00 "COUNTER0_MAX,Counter 0 maximum value"
group.long 0x128++0x3
line.long 0x00 "COUNTER0_CNT,Counter 0 current value"
width 16.
group.long 0x104++0x3 "GPIO Counter 1 "
line.long 0x00 "COUNTER_CTRL1,Counter 1 Control register"
bitfld.long 0x00 7.--11. " GPIO_REF ,GPIO reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4. " ONCE ,Run only once" "No (cyclic),Yes"
textline " "
bitfld.long 0x00 5.--6. " EVENT_ACT ,Event action" "Count every clock,Count external event,Watchdog mode,Run by external event"
bitfld.long 0x00 3. " SEL_EVENT ,Counter event" "High level,Positive edge"
textline " "
bitfld.long 0x00 2. " IRQ_EN ,IRQ enable" "Disabled,Enabled"
bitfld.long 0x00 1. " SYM/ASYM ,Symmetric" "Assymetric (sawtooth),Symmetric (triangle)"
textline " "
bitfld.long 0x00 0. " RUN ,Start/Stop" "Stop,Start"
group.long 0x118++0x3
line.long 0x00 "COUNTER1_MAX,Counter 1 maximum value"
group.long 0x12C++0x3
line.long 0x00 "COUNTER1_CNT,Counter 1 current value"
width 16.
group.long 0x108++0x3 "GPIO Counter 2 "
line.long 0x00 "COUNTER_CTRL2,Counter 2 Control register"
bitfld.long 0x00 7.--11. " GPIO_REF ,GPIO reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4. " ONCE ,Run only once" "No (cyclic),Yes"
textline " "
bitfld.long 0x00 5.--6. " EVENT_ACT ,Event action" "Count every clock,Count external event,Watchdog mode,Run by external event"
bitfld.long 0x00 3. " SEL_EVENT ,Counter event" "High level,Positive edge"
textline " "
bitfld.long 0x00 2. " IRQ_EN ,IRQ enable" "Disabed,Enabled"
bitfld.long 0x00 1. " SYM/ASYM ,Symmetric" "Assymetric (sawtooth),Symmetric (triangle)"
textline " "
bitfld.long 0x00 0. " RUN ,Start/Stop" "Stop,Start"
group.long 0x11C++0x3
line.long 0x00 "COUNTER2_MAX,Counter 2 maximum value"
group.long 0x130++0x3
line.long 0x00 "COUNTER2_CNT,Counter 2 current value"
width 16.
group.long 0x10C++0x3 "GPIO Counter 3 "
line.long 0x00 "COUNTER_CTRL3,Counter 3 Control register"
bitfld.long 0x00 7.--11. " GPIO_REF ,GPIO reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4. " ONCE ,Run only once" "No (cyclic),Yes"
textline " "
bitfld.long 0x00 5.--6. " EVENT_ACT ,Event action" "Count every clock,Count external event,Watchdog mode,Run by external event"
bitfld.long 0x00 3. " SEL_EVENT ,Counter event" "High level,Positive edge"
textline " "
bitfld.long 0x00 2. " IRQ_EN ,IRQ enable" "Disabed,Enabled"
bitfld.long 0x00 1. " SYM/ASYM ,Symmetric" "Assymetric (sawtooth),Symmetric (triangle)"
textline " "
bitfld.long 0x00 0. " RUN ,Start/Stop" "Stop,Start"
group.long 0x120++0x3
line.long 0x00 "COUNTER3_MAX,Counter 3 maximum value"
group.long 0x134++0x3
line.long 0x00 "COUNTER3_CNT,Counter 3 current value"
width 16.
group.long 0x110++0x3 "GPIO Counter 4 "
line.long 0x00 "COUNTER_CTRL4,Counter 4 Control register"
bitfld.long 0x00 7.--11. " GPIO_REF ,GPIO reference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4. " ONCE ,Run only once" "No (cyclic),Yes"
textline " "
bitfld.long 0x00 5.--6. " EVENT_ACT ,Event action" "Count every clock,Count external event,Watchdog mode,Run by external event"
bitfld.long 0x00 3. " SEL_EVENT ,Counter event" "High level,Positive edge"
textline " "
bitfld.long 0x00 2. " IRQ_EN ,IRQ enable" "Disabed,Enabled"
bitfld.long 0x00 1. " SYM/ASYM ,Symmetric" "Assymetric (sawtooth),Symmetric (triangle)"
textline " "
bitfld.long 0x00 0. " RUN ,Start/Stop" "Stop,Start"
group.long 0x124++0x3
line.long 0x00 "COUNTER4_MAX,Counter 4 maximum value"
group.long 0x138++0x3
line.long 0x00 "COUNTER4_CNT,Counter 4 current value"
textline " "
width 16.
group.long 0x13C++0x3
line.long 0x00 "SYSTIME_CMP,Systime compare value"
group.long 0x140++0x3
line.long 0x00 "GPIO_OUT,GPIO Output Register"
bitfld.long 0x00 31. " GPIO_OUT31 ,Interrupt bit for GPIO31" "Low,High"
bitfld.long 0x00 30. " GPIO_OUT30 ,Interrupt bit for GPIO30" "Low,High"
bitfld.long 0x00 29. " GPIO_OUT29 ,Interrupt bit for GPIO29" "Low,High"
bitfld.long 0x00 28. " GPIO_OUT28 ,Interrupt bit for GPIO28" "Low,High"
textline " "
bitfld.long 0x00 27. " GPIO_OUT27 ,Interrupt bit for GPIO27" "Low,High"
bitfld.long 0x00 26. " GPIO_OUT26 ,Interrupt bit for GPIO26" "Low,High"
bitfld.long 0x00 25. " GPIO_OUT25 ,Interrupt bit for GPIO25" "Low,High"
bitfld.long 0x00 24. " GPIO_OUT24 ,Interrupt bit for GPIO24" "Low,High"
textline " "
bitfld.long 0x00 23. " GPIO_OUT23 ,Interrupt bit for GPIO23" "Low,High"
bitfld.long 0x00 22. " GPIO_OUT22 ,Interrupt bit for GPIO22" "Low,High"
bitfld.long 0x00 21. " GPIO_OUT21 ,Interrupt bit for GPIO21" "Low,High"
bitfld.long 0x00 20. " GPIO_OUT20 ,Interrupt bit for GPIO20" "Low,High"
textline " "
bitfld.long 0x00 19. " GPIO_OUT19 ,Interrupt bit for GPIO19" "Low,High"
bitfld.long 0x00 18. " GPIO_OUT18 ,Interrupt bit for GPIO18" "Low,High"
bitfld.long 0x00 17. " GPIO_OUT17 ,Interrupt bit for GPIO17" "Low,High"
bitfld.long 0x00 16. " GPIO_OUT16 ,Interrupt bit for GPIO16" "Low,High"
textline " "
bitfld.long 0x00 15. " GPIO_OUT15 ,Interrupt bit for GPIO15" "Low,High"
bitfld.long 0x00 14. " GPIO_OUT14 ,Interrupt bit for GPIO14" "Low,High"
bitfld.long 0x00 13. " GPIO_OUT13 ,Interrupt bit for GPIO13" "Low,High"
bitfld.long 0x00 12. " GPIO_OUT12 ,Interrupt bit for GPIO12" "Low,High"
textline " "
bitfld.long 0x00 11. " GPIO_OUT11 ,Interrupt bit for GPIO11" "Low,High"
bitfld.long 0x00 10. " GPIO_OUT10 ,Interrupt bit for GPIO10" "Low,High"
bitfld.long 0x00 9. " GPIO_OUT9 ,Interrupt bit for GPIO9" "Low,High"
bitfld.long 0x00 8. " GPIO_OUT8 ,Interrupt bit for GPIO8" "Low,High"
textline " "
bitfld.long 0x00 7. " GPIO_OUT7 ,Interrupt bit for GPIO7 " "Low,High"
bitfld.long 0x00 6. " GPIO_OUT6 ,Interrupt bit for GPIO6 " "Low,High"
bitfld.long 0x00 5. " GPIO_OUT5 ,Interrupt bit for GPIO5 " "Low,High"
bitfld.long 0x00 4. " GPIO_OUT4 ,Interrupt bit for GPIO4 " "Low,High"
textline " "
bitfld.long 0x00 3. " GPIO_OUT3 ,Interrupt bit for GPIO3 " "Low,High"
bitfld.long 0x00 2. " GPIO_OUT2 ,Interrupt bit for GPIO2 " "Low,High"
bitfld.long 0x00 1. " GPIO_OUT1 ,Interrupt bit for GPIO1 " "Low,High"
bitfld.long 0x00 0. " GPIO_OUT0 ,Interrupt bit for GPIO0 " "Low,High"
rgroup.long 0x144++0x3
line.long 0x00 "GPIO_IN,GPIO Input register"
bitfld.long 0x00 31. " GPIO_IN31 ,Interrupt bit for GPIO31" "Low,High"
bitfld.long 0x00 30. " GPIO_IN30 ,Interrupt bit for GPIO30" "Low,High"
bitfld.long 0x00 29. " GPIO_IN29 ,Interrupt bit for GPIO29" "Low,High"
bitfld.long 0x00 28. " GPIO_IN28 ,Interrupt bit for GPIO28" "Low,High"
textline " "
bitfld.long 0x00 27. " GPIO_IN27 ,Interrupt bit for GPIO27" "Low,High"
bitfld.long 0x00 26. " GPIO_IN26 ,Interrupt bit for GPIO26" "Low,High"
bitfld.long 0x00 25. " GPIO_IN25 ,Interrupt bit for GPIO25" "Low,High"
bitfld.long 0x00 24. " GPIO_IN24 ,Interrupt bit for GPIO24" "Low,High"
textline " "
bitfld.long 0x00 23. " GPIO_IN23 ,Interrupt bit for GPIO23" "Low,High"
bitfld.long 0x00 22. " GPIO_IN22 ,Interrupt bit for GPIO22" "Low,High"
bitfld.long 0x00 21. " GPIO_IN21 ,Interrupt bit for GPIO21" "Low,High"
bitfld.long 0x00 20. " GPIO_IN20 ,Interrupt bit for GPIO20" "Low,High"
textline " "
bitfld.long 0x00 19. " GPIO_IN19 ,Interrupt bit for GPIO19" "Low,High"
bitfld.long 0x00 18. " GPIO_IN18 ,Interrupt bit for GPIO18" "Low,High"
bitfld.long 0x00 17. " GPIO_IN17 ,Interrupt bit for GPIO17" "Low,High"
bitfld.long 0x00 16. " GPIO_IN16 ,Interrupt bit for GPIO16" "Low,High"
textline " "
bitfld.long 0x00 15. " GPIO_IN15 ,Interrupt bit for GPIO15" "Low,High"
bitfld.long 0x00 14. " GPIO_IN14 ,Interrupt bit for GPIO14" "Low,High"
bitfld.long 0x00 13. " GPIO_IN13 ,Interrupt bit for GPIO13" "Low,High"
bitfld.long 0x00 12. " GPIO_IN12 ,Interrupt bit for GPIO12" "Low,High"
textline " "
bitfld.long 0x00 11. " GPIO_IN11 ,Interrupt bit for GPIO11" "Low,High"
bitfld.long 0x00 10. " GPIO_IN10 ,Interrupt bit for GPIO10" "Low,High"
bitfld.long 0x00 9. " GPIO_IN9 ,Interrupt bit for GPIO9" "Low,High"
bitfld.long 0x00 8. " GPIO_IN8 ,Interrupt bit for GPIO8" "Low,High"
textline " "
bitfld.long 0x00 7. " GPIO_IN7 ,Interrupt bit for GPIO7 " "Low,High"
bitfld.long 0x00 6. " GPIO_IN6 ,Interrupt bit for GPIO6 " "Low,High"
bitfld.long 0x00 5. " GPIO_IN5 ,Interrupt bit for GPIO5 " "Low,High"
bitfld.long 0x00 4. " GPIO_IN4 ,Interrupt bit for GPIO4 " "Low,High"
textline " "
bitfld.long 0x00 3. " GPIO_IN3 ,Interrupt bit for GPIO3 " "Low,High"
bitfld.long 0x00 2. " GPIO_IN2 ,Interrupt bit for GPIO2 " "Low,High"
bitfld.long 0x00 1. " GPIO_IN1 ,Interrupt bit for GPIO1 " "Low,High"
bitfld.long 0x00 0. " GPIO_IN0 ,Interrupt bit for GPIO0 " "Low,High"
width 16.
group.long 0x148++0x3 "GPIO_IRQ_RAW"
line.long 0x00 "GPIO_IRQ_RAW,GPIO raw IRQ Register "
bitfld.long 0x00 31. " GPIO31 ,Interrupt bit for GPIO31" "No interrupt,Interrupt"
bitfld.long 0x00 30. " GPIO30 ,Interrupt bit for GPIO30" "No interrupt,Interrupt"
bitfld.long 0x00 29. " GPIO29 ,Interrupt bit for GPIO29" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 28. " GPIO28 ,Interrupt bit for GPIO28" "No interrupt,Interrupt"
bitfld.long 0x00 27. " GPIO27 ,Interrupt bit for GPIO27" "No interrupt,Interrupt"
bitfld.long 0x00 26. " GPIO26 ,Interrupt bit for GPIO26" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 25. " GPIO25 ,Interrupt bit for GPIO25" "No interrupt,Interrupt"
bitfld.long 0x00 24. " GPIO24 ,Interrupt bit for GPIO24" "No interrupt,Interrupt"
bitfld.long 0x00 23. " GPIO23 ,Interrupt bit for GPIO23" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 22. " GPIO22 ,Interrupt bit for GPIO22" "No interrupt,Interrupt"
bitfld.long 0x00 21. " GPIO21 ,Interrupt bit for GPIO21" "No interrupt,Interrupt"
bitfld.long 0x00 20. " GPIO20 ,Interrupt bit for GPIO20" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " GPIO19 ,Interrupt bit for GPIO19" "No interrupt,Interrupt"
bitfld.long 0x00 18. " GPIO18 ,Interrupt bit for GPIO18" "No interrupt,Interrupt"
bitfld.long 0x00 17. " GPIO17 ,Interrupt bit for GPIO17" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 16. " GPIO16 ,Interrupt bit for GPIO16" "No interrupt,Interrupt"
bitfld.long 0x00 15. " GPIO15 ,Interrupt bit for GPIO15" "No interrupt,Interrupt"
bitfld.long 0x00 14. " GPIO14 ,Interrupt bit for GPIO14" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 13. " GPIO13 ,Interrupt bit for GPIO13" "No interrupt,Interrupt"
bitfld.long 0x00 12. " GPIO12 ,Interrupt bit for GPIO12" "No interrupt,Interrupt"
bitfld.long 0x00 11. " GPIO11 ,Interrupt bit for GPIO11" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 10. " GPIO10 ,Interrupt bit for GPIO10" "No interrupt,Interrupt"
bitfld.long 0x00 9. " GPIO9 ,Interrupt bit for GPIO9" "No interrupt,Interrupt"
bitfld.long 0x00 8. " GPIO8 ,Interrupt bit for GPIO8" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " GPIO7 ,Interrupt bit for GPIO7 " "No interrupt,Interrupt"
bitfld.long 0x00 6. " GPIO6 ,Interrupt bit for GPIO6 " "No interrupt,Interrupt"
bitfld.long 0x00 5. " GPIO5 ,Interrupt bit for GPIO5 " "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 4. " GPIO4 ,Interrupt bit for GPIO4 " "No interrupt,Interrupt"
bitfld.long 0x00 3. " GPIO3 ,Interrupt bit for GPIO3 " "No interrupt,Interrupt"
bitfld.long 0x00 2. " GPIO2 ,Interrupt bit for GPIO2 " "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 1. " GPIO1 ,Interrupt bit for GPIO1 " "No interrupt,Interrupt"
bitfld.long 0x00 0. " GPIO0 ,Interrupt bit for GPIO0 " "No interrupt,Interrupt"
width 16.
group.long 0x14C++0x3
line.long 0x00 "GPIO_IRQ_MSK,GPIO Masked IRQ Register "
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " GPIO31_set/clr ,Status of masked IRQs for GPIO31" "Not masked,Masked"
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " GPIO30_set/clr ,Status of masked IRQs for GPIO30" "Not masked,Masked"
textline " "
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " GPIO29_set/clr ,Status of masked IRQs for GPIO29" "Not masked,Masked"
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " GPIO28_set/clr ,Status of masked IRQs for GPIO28" "Not masked,Masked"
textline " "
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " GPIO27_set/clr ,Status of masked IRQs for GPIO27" "Not masked,Masked"
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " GPIO26_set/clr ,Status of masked IRQs for GPIO26" "Not masked,Masked"
textline " "
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " GPIO25_set/clr ,Status of masked IRQs for GPIO25" "Not masked,Masked"
setclrfld.long 0x00 24. 0x04 24. 0x08 24. " GPIO24_set/clr ,Status of masked IRQs for GPIO24" "Not masked,Masked"
textline " "
setclrfld.long 0x00 23. 0x04 23. 0x08 23. " GPIO23_set/clr ,Status of masked IRQs for GPIO23" "Not masked,Masked"
setclrfld.long 0x00 22. 0x04 22. 0x08 22. " GPIO22_set/clr ,Status of masked IRQs for GPIO22" "Not masked,Masked"
textline " "
setclrfld.long 0x00 21. 0x04 21. 0x08 21. " GPIO21_set/clr ,Status of masked IRQs for GPIO21" "Not masked,Masked"
setclrfld.long 0x00 20. 0x04 20. 0x08 20. " GPIO20_set/clr ,Status of masked IRQs for GPIO20" "Not masked,Masked"
textline " "
setclrfld.long 0x00 19. 0x04 19. 0x08 19. " GPIO19_set/clr ,Status of masked IRQs for GPIO19" "Not masked,Masked"
setclrfld.long 0x00 18. 0x04 18. 0x08 18. " GPIO18_set/clr ,Status of masked IRQs for GPIO18" "Not masked,Masked"
textline " "
setclrfld.long 0x00 17. 0x04 17. 0x08 17. " GPIO17_set/clr ,Status of masked IRQs for GPIO17" "Not masked,Masked"
setclrfld.long 0x00 16. 0x04 16. 0x08 16. " GPIO16_set/clr ,Status of masked IRQs for GPIO16" "Not masked,Masked"
textline " "
setclrfld.long 0x00 15. 0x04 15. 0x08 15. " GPIO15_set/clr ,Status of masked IRQs for GPIO15" "Not masked,Masked"
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " GPIO14_set/clr ,Status of masked IRQs for GPIO14" "Not masked,Masked"
textline " "
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " GPIO13_set/clr ,Status of masked IRQs for GPIO13" "Not masked,Masked"
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " GPIO12_set/clr ,Status of masked IRQs for GPIO12" "Not masked,Masked"
textline " "
setclrfld.long 0x00 11. 0x04 11. 0x08 11. " GPIO11_set/clr ,Status of masked IRQs for GPIO11" "Not masked,Masked"
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " GPIO10_set/clr ,Status of masked IRQs for GPIO10" "Not masked,Masked"
textline " "
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " GPIO9_set/clr ,Status of masked IRQs for GPIO9" "Not masked,Masked"
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " GPIO8_set/clr ,Status of masked IRQs for GPIO8" "Not masked,Masked"
textline " "
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GPIO7_set/clr ,Status of masked IRQs for GPIO7 " "Not masked,Masked"
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " GPIO6_set/clr ,Status of masked IRQs for GPIO6 " "Not masked,Masked"
textline " "
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " GPIO5_set/clr ,Status of masked IRQs for GPIO5 " "Not masked,Masked"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " GPIO4_set/clr ,Status of masked IRQs for GPIO4 " "Not masked,Masked"
textline " "
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " GPIO3_set/clr ,Status of masked IRQs for GPIO3 " "Not masked,Masked"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " GPIO2_set/clr ,Status of masked IRQs for GPIO2 " "Not masked,Masked"
textline " "
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " GPIO1_set/clr ,Status of masked IRQs for GPIO1 " "Not masked,Masked"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " GPIO0_set/clr ,Status of masked IRQs for GPIO0 " "Not masked,Masked"
width 16.
group.long 0x158++0x3
line.long 0x00 "CNTR_IRQ_RAW,Counter raw IRQ register"
bitfld.long 0x00 5. " SYSTIME ,Interrupt bit for sys_time " "No interrupt,Interrupt"
bitfld.long 0x00 4. " CNT4 ,Interrupt bit for counter4 " "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " CNT3 ,Interrupt bit for counter3 " "No interrupt,Interrupt"
bitfld.long 0x00 2. " CNT2 ,Interrupt bit for counter2 " "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 1. " CNT1 ,Interrupt bit for counter1 " "No interrupt,Interrupt"
bitfld.long 0x00 0. " CNT0 ,Interrupt bit for counter0 " "No interrupt,Interrupt"
width 16.
group.long 0x15C++0x3 "CNT_IRQ_MASKED"
line.long 0x00 "CNTR_IRQ_MSK,Counter masked IRQ register"
setclrfld.long 0x00 5. 0x04 5. 0x08 5. " SYSTIME_set/clr ,Interrupt status for sys_time " "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CNT4_set/clr ,Interrupt status for counter4 " "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CNT3_set/clr ,Interrupt status for counter3 " "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " CNT2_set/clr ,Interrupt status for counter2 " "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CNT1_set/clr ,Interrupt status for counter1 " "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CNT0_set/clr ,Interrupt status for counter0 " "No interrupt,Interrupt"
width 0x0b
tree.end
tree "IO-Link"
base asd:0x1c000880
width 18.
rgroup.long 0x880++0x0f "IO-Link Configuration Register 0"
line.long 0x00 "IOLINK0_CFG,IO-Link 0 Configuration Register "
hexmask.long.byte 0x0 25.--31. 1. " Tclk_cnt_r ,MSB of the baud rate counter"
bitfld.long 0x00 22.--24. " Ad_rx_oct_r ,Current rx transfer counter " "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--21. 1. " Frame_cycle_cnt_r ,Current frame cycle counter"
textline " "
bitfld.long 0x00 10.--12. " Tx_oct_cnt_r ,Lower bits of current tx transfer counter " "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. " Stop_bit_error_r ,Stop bit error in last transmission " "0,1"
bitfld.long 0x00 8. " Rx_sum_p_err_r ,Parity error in last transmission " "0,1"
textline " "
bitfld.long 0x00 4.--7. " Fsm_io_link_st ,Status of the IOLINK state machine " "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x00 3. " Tx_oe_r ,Current status tx_oe port" "0,1"
bitfld.long 0x00 2. " Wake_up_r ,Current status of wake up port " "0,1"
textline " "
bitfld.long 0x00 1. " Rxd_in ,Current status of rx port " "0,1"
bitfld.long 0x00 0. " Txd_r ,Current status of tx port " "0,1"
line.long 0x04 "IOLINK0_TX_FRM0,IO-Link 0 TX0 Data Register"
hexmask.long.byte 0x04 24.--31. 1. " TX_OCTET4 ,Transmit octet 4 "
hexmask.long.byte 0x04 16.--23. 1. " TX_OCTET3 ,Transmit octet 3 "
textline " "
hexmask.long.byte 0x04 8.--15. 1. " TX_OCTET2 ,Transmit octet 2 "
hexmask.long.byte 0x04 0.--7. 1. " TX_OCTET1 ,Transmit octet 1 "
line.long 0x08 "IOLINK0_TX_FRM1,IO-Link 0 TX1 Data Register"
hexmask.long.byte 0x08 24.--31. 1. " TX_OCTET8 ,Transmit octet 8 "
hexmask.long.byte 0x08 16.--23. 1. " TX_OCTET7 ,Transmit octet 7 "
textline " "
hexmask.long.byte 0x08 8.--15. 1. " TX_OCTET6 ,Transmit octet 6 "
hexmask.long.byte 0x08 0.--7. 1. " TX_OCTET5 ,Transmit octet 5 "
line.long 0x0c "IOLINK0_RX_FRM,IO-Link 0 RX Data Register "
hexmask.long.byte 0x0c 24.--31. 1. " RX_OCTET4 ,Receive octet 4 "
hexmask.long.byte 0x0c 16.--23. 1. " RX_OCTET3 ,Receive octet 3 "
textline " "
hexmask.long.byte 0x0c 8.--15. 1. " RX_OCTET2 ,Receive octet 2 "
hexmask.long.byte 0x0c 0.--7. 1. " RX_OCTET1 ,Receive octet 1 "
; group.long 0x880++0x03
; line.long 0x00 "IOLINK0_CFG,IO-Link 0 Configuration Register "
; bitfld.long 0x00 31. "SET_STATUS,Set status vector to this register address " "Disabled,Enabled"
; bitfld.long 0x00 28.--30. "DEBUG_VEC,Debug vector" "0,1,2,3,4,5,6,7"
; textline " "
; bitfld.long 0x00 27. "RX_LSB_FIRST,LSByte first for receive process" "Disabled,Enabled"
; bitfld.long 0x00 26. "GEN_WAKE_UP,Set this bit to generate one wake up pulse " "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 25. "PIO_TX_OE_ACTIVE,Activate the link output control" "Disabled,Enabled"
; bitfld.long 0x00 24. "ENABLE_FM_INTR,Enable frame interrup" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 23. "LATCH_DVAL,Latch the delay value" "Disabled,Enabled"
; bitfld.long 0x00 22. "EN_DELAY,Enable delay function before transmitting the frame" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 21. "TX_LOOP,Enable tx auto repeat transmission" "Disabled,Enabled"
; bitfld.long 0x00 20. "TX_OE_DIS,Disable the tx_oe generation if wake up generation proceeds" "Enabled,Disabled"
; textline " "
; bitfld.long 0x00 19. "EN_FRAME_TIMEOUT,Enable the frame timeout function" "Disabled,Enabled"
; bitfld.long 0x00 18. "TX_INIT,Default tx output level" "Low,High"
; textline " "
; bitfld.long 0x00 17. "TX_LSB_FIRST,LSByte first for transmit process" "Disabled,Enabled"
; bitfld.long 0x00 16. "SNGL_TRANS,Single frame transfer mode" "0,1"
; textline " "
; bitfld.long 0x00 13.--14. "NR_RX_OCT,Number for octets to receive" "1,2,3,4"
; bitfld.long 0x00 10.--12. "NR_TX_OCT,Number for octets to transmit" "1,2,3,4,5,?..."
; textline " "
; bitfld.long 0x00 8.--9. "FREQ_SEL,Set the baud rate (T_clk)" "250ns test only,208.33 us com1 - 4800 Baud,26.04 us com2 - 38400 Baud,4.34 us com3 - 230400 Baud"
; textline " "
; hexmask.long.byte 0x00 0.--7. 1. "FRAME_CYCLE,Half of number of T_clk cycles"
rgroup.long 0x890++0x0f "IO-Link Configuration Register 1"
line.long 0x00 "IOLINK1_CFG,IO-Link 1 Configuration Register "
hexmask.long.byte 0x0 25.--31. 1. " Tclk_cnt_r ,MSB of the baud rate counter"
bitfld.long 0x00 22.--24. " Ad_rx_oct_r ,Current rx transfer counter " "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--21. 1. " Frame_cycle_cnt_r ,Current frame cycle counter"
textline " "
bitfld.long 0x00 10.--12. " Tx_oct_cnt_r ,Lower bits of current tx transfer counter " "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. " Stop_bit_error_r ,Stop bit error in last transmission " "0,1"
bitfld.long 0x00 8. " Rx_sum_p_err_r ,Parity error in last transmission " "0,1"
textline " "
bitfld.long 0x00 4.--7. " Fsm_io_link_st ,Status of the IOLINK state machine " "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x00 3. " Tx_oe_r ,Current status tx_oe port" "0,1"
bitfld.long 0x00 2. " Wake_up_r ,Current status of wake up port " "0,1"
textline " "
bitfld.long 0x00 1. " Rxd_in ,Current status of rx port " "0,1"
bitfld.long 0x00 0. " Txd_r ,Current status of tx port " "0,1"
line.long 0x04 "IOLINK1_TX_FRM0,IO-Link 1 TX0 Data Register"
hexmask.long.byte 0x04 24.--31. 1. " TX_OCTET4 ,Transmit octet 4 "
hexmask.long.byte 0x04 16.--23. 1. " TX_OCTET3 ,Transmit octet 3 "
textline " "
hexmask.long.byte 0x04 8.--15. 1. " TX_OCTET2 ,Transmit octet 2 "
hexmask.long.byte 0x04 0.--7. 1. " TX_OCTET1 ,Transmit octet 1 "
line.long 0x08 "IOLINK1_TX_FRM1,IO-Link 1 TX1 Data Register"
hexmask.long.byte 0x08 24.--31. 1. " TX_OCTET8 ,Transmit octet 8 "
hexmask.long.byte 0x08 16.--23. 1. " TX_OCTET7 ,Transmit octet 7 "
textline " "
hexmask.long.byte 0x08 8.--15. 1. " TX_OCTET6 ,Transmit octet 6 "
hexmask.long.byte 0x08 0.--7. 1. " TX_OCTET5 ,Transmit octet 5 "
line.long 0x0c "IOLINK1_RX_FRM,IO-Link 1 RX Data Register "
hexmask.long.byte 0x0c 24.--31. 1. " RX_OCTET4 ,Receive octet 4 "
hexmask.long.byte 0x0c 16.--23. 1. " RX_OCTET3 ,Receive octet 3 "
textline " "
hexmask.long.byte 0x0c 8.--15. 1. " RX_OCTET2 ,Receive octet 2 "
hexmask.long.byte 0x0c 0.--7. 1. " RX_OCTET1 ,Receive octet 1 "
; group.long 0x890++0x03
; line.long 0x00 "IOLINK1_CFG,IO-Link 1 Configuration Register "
; bitfld.long 0x00 31. "SET_STATUS,Set status vector to this register address " "Disabled,Enabled"
; bitfld.long 0x00 28.--30. "DEBUG_VEC,Debug vector" "0,1,2,3,4,5,6,7"
; textline " "
; bitfld.long 0x00 27. "RX_LSB_FIRST,LSByte first for receive process" "Disabled,Enabled"
; bitfld.long 0x00 26. "GEN_WAKE_UP,Set this bit to generate one wake up pulse " "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 25. "PIO_TX_OE_ACTIVE,Activate the link output control" "Disabled,Enabled"
; bitfld.long 0x00 24. "ENABLE_FM_INTR,Enable frame interrup" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 23. "LATCH_DVAL,Latch the delay value" "Disabled,Enabled"
; bitfld.long 0x00 22. "EN_DELAY,Enable delay function before transmitting the frame" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 21. "TX_LOOP,Enable tx auto repeat transmission" "Disabled,Enabled"
; bitfld.long 0x00 20. "TX_OE_DIS,Disable the tx_oe generation if wake up generation proceeds" "Enabled,Disabled"
; textline " "
; bitfld.long 0x00 19. "EN_FRAME_TIMEOUT,Enable the frame timeout function" "Disabled,Enabled"
; bitfld.long 0x00 18. "TX_INIT,Default tx output level" "Low,High"
; textline " "
; bitfld.long 0x00 17. "TX_LSB_FIRST,LSByte first for transmit process" "Disabled,Enabled"
; bitfld.long 0x00 16. "SNGL_TRANS,Single frame transfer mode" "0,1"
; textline " "
; bitfld.long 0x00 13.--14. "NR_RX_OCT,Number for octets to receive" "1,2,3,4"
; bitfld.long 0x00 10.--12. "NR_TX_OCT,Number for octets to transmit" "1,2,3,4,5,?..."
; textline " "
; bitfld.long 0x00 8.--9. "FREQ_SEL,Set the baud rate (T_clk)" "250ns test only,208.33 us com1 - 4800 Baud,26.04 us com2 - 38400 Baud,4.34 us com3 - 230400 Baud"
; textline " "
; hexmask.long.byte 0x00 0.--7. 1. "FRAME_CYCLE,Half of number of T_clk cycles"
rgroup.long 0x8A0++0x0f "IO-Link Configuration Register 2"
line.long 0x00 "IOLINK2_CFG,IO-Link 2 Configuration Register "
hexmask.long.byte 0x0 25.--31. 1. " Tclk_cnt_r ,MSB of the baud rate counter"
bitfld.long 0x00 22.--24. " Ad_rx_oct_r ,Current rx transfer counter " "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--21. 1. " Frame_cycle_cnt_r ,Current frame cycle counter"
textline " "
bitfld.long 0x00 10.--12. " Tx_oct_cnt_r ,Lower bits of current tx transfer counter " "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. " Stop_bit_error_r ,Stop bit error in last transmission " "0,1"
bitfld.long 0x00 8. " Rx_sum_p_err_r ,Parity error in last transmission " "0,1"
textline " "
bitfld.long 0x00 4.--7. " Fsm_io_link_st ,Status of the IOLINK state machine " "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x00 3. " Tx_oe_r ,Current status tx_oe port" "0,1"
bitfld.long 0x00 2. " Wake_up_r ,Current status of wake up port " "0,1"
textline " "
bitfld.long 0x00 1. " Rxd_in ,Current status of rx port " "0,1"
bitfld.long 0x00 0. " Txd_r ,Current status of tx port " "0,1"
line.long 0x04 "IOLINK2_TX_FRM0,IO-Link 2 TX0 Data Register"
hexmask.long.byte 0x04 24.--31. 1. " TX_OCTET4 ,Transmit octet 4 "
hexmask.long.byte 0x04 16.--23. 1. " TX_OCTET3 ,Transmit octet 3 "
textline " "
hexmask.long.byte 0x04 8.--15. 1. " TX_OCTET2 ,Transmit octet 2 "
hexmask.long.byte 0x04 0.--7. 1. " TX_OCTET1 ,Transmit octet 1 "
line.long 0x08 "IOLINK2_TX_FRM1,IO-Link 2 TX1 Data Register"
hexmask.long.byte 0x08 24.--31. 1. " TX_OCTET8 ,Transmit octet 8 "
hexmask.long.byte 0x08 16.--23. 1. " TX_OCTET7 ,Transmit octet 7 "
textline " "
hexmask.long.byte 0x08 8.--15. 1. " TX_OCTET6 ,Transmit octet 6 "
hexmask.long.byte 0x08 0.--7. 1. " TX_OCTET5 ,Transmit octet 5 "
line.long 0x0c "IOLINK2_RX_FRM,IO-Link 2 RX Data Register "
hexmask.long.byte 0x0c 24.--31. 1. " RX_OCTET4 ,Receive octet 4 "
hexmask.long.byte 0x0c 16.--23. 1. " RX_OCTET3 ,Receive octet 3 "
textline " "
hexmask.long.byte 0x0c 8.--15. 1. " RX_OCTET2 ,Receive octet 2 "
hexmask.long.byte 0x0c 0.--7. 1. " RX_OCTET1 ,Receive octet 1 "
; group.long 0x8A0++0x03
; line.long 0x00 "IOLINK2_CFG,IO-Link 2 Configuration Register "
; bitfld.long 0x00 31. "SET_STATUS,Set status vector to this register address " "Disabled,Enabled"
; bitfld.long 0x00 28.--30. "DEBUG_VEC,Debug vector" "0,1,2,3,4,5,6,7"
; textline " "
; bitfld.long 0x00 27. "RX_LSB_FIRST,LSByte first for receive process" "Disabled,Enabled"
; bitfld.long 0x00 26. "GEN_WAKE_UP,Set this bit to generate one wake up pulse " "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 25. "PIO_TX_OE_ACTIVE,Activate the link output control" "Disabled,Enabled"
; bitfld.long 0x00 24. "ENABLE_FM_INTR,Enable frame interrup" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 23. "LATCH_DVAL,Latch the delay value" "Disabled,Enabled"
; bitfld.long 0x00 22. "EN_DELAY,Enable delay function before transmitting the frame" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 21. "TX_LOOP,Enable tx auto repeat transmission" "Disabled,Enabled"
; bitfld.long 0x00 20. "TX_OE_DIS,Disable the tx_oe generation if wake up generation proceeds" "Enabled,Disabled"
; textline " "
; bitfld.long 0x00 19. "EN_FRAME_TIMEOUT,Enable the frame timeout function" "Disabled,Enabled"
; bitfld.long 0x00 18. "TX_INIT,Default tx output level" "Low,High"
; textline " "
; bitfld.long 0x00 17. "TX_LSB_FIRST,LSByte first for transmit process" "Disabled,Enabled"
; bitfld.long 0x00 16. "SNGL_TRANS,Single frame transfer mode" "0,1"
; textline " "
; bitfld.long 0x00 13.--14. "NR_RX_OCT,Number for octets to receive" "1,2,3,4"
; bitfld.long 0x00 10.--12. "NR_TX_OCT,Number for octets to transmit" "1,2,3,4,5,?..."
; textline " "
; bitfld.long 0x00 8.--9. "FREQ_SEL,Set the baud rate (T_clk)" "250ns test only,208.33 us com1 - 4800 Baud,26.04 us com2 - 38400 Baud,4.34 us com3 - 230400 Baud"
; textline " "
; hexmask.long.byte 0x00 0.--7. 1. "FRAME_CYCLE,Half of number of T_clk cycles"
rgroup.long 0x8B0++0x0f "IO-Link Configuration Register 3"
line.long 0x00 "IOLINK3_CFG,IO-Link 3 Configuration Register "
hexmask.long.byte 0x0 25.--31. 1. " Tclk_cnt_r ,MSB of the baud rate counter"
bitfld.long 0x00 22.--24. " Ad_rx_oct_r ,Current rx transfer counter " "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--21. 1. " Frame_cycle_cnt_r ,Current frame cycle counter"
textline " "
bitfld.long 0x00 10.--12. " Tx_oct_cnt_r ,Lower bits of current tx transfer counter " "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. " Stop_bit_error_r ,Stop bit error in last transmission " "0,1"
bitfld.long 0x00 8. " Rx_sum_p_err_r ,Parity error in last transmission " "0,1"
textline " "
bitfld.long 0x00 4.--7. " Fsm_io_link_st ,Status of the IOLINK state machine " "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x00 3. " Tx_oe_r ,Current status tx_oe port" "0,1"
bitfld.long 0x00 2. " Wake_up_r ,Current status of wake up port " "0,1"
textline " "
bitfld.long 0x00 1. " Rxd_in ,Current status of rx port " "0,1"
bitfld.long 0x00 0. " Txd_r ,Current status of tx port " "0,1"
line.long 0x04 "IOLINK3_TX_FRM0,IO-Link 3 TX0 Data Register"
hexmask.long.byte 0x04 24.--31. 1. " TX_OCTET4 ,Transmit octet 4 "
hexmask.long.byte 0x04 16.--23. 1. " TX_OCTET3 ,Transmit octet 3 "
textline " "
hexmask.long.byte 0x04 8.--15. 1. " TX_OCTET2 ,Transmit octet 2 "
hexmask.long.byte 0x04 0.--7. 1. " TX_OCTET1 ,Transmit octet 1 "
line.long 0x08 "IOLINK3_TX_FRM1,IO-Link 3 TX1 Data Register"
hexmask.long.byte 0x08 24.--31. 1. " TX_OCTET8 ,Transmit octet 8 "
hexmask.long.byte 0x08 16.--23. 1. " TX_OCTET7 ,Transmit octet 7 "
textline " "
hexmask.long.byte 0x08 8.--15. 1. " TX_OCTET6 ,Transmit octet 6 "
hexmask.long.byte 0x08 0.--7. 1. " TX_OCTET5 ,Transmit octet 5 "
line.long 0x0c "IOLINK3_RX_FRM,IO-Link 3 RX Data Register "
hexmask.long.byte 0x0c 24.--31. 1. " RX_OCTET4 ,Receive octet 4 "
hexmask.long.byte 0x0c 16.--23. 1. " RX_OCTET3 ,Receive octet 3 "
textline " "
hexmask.long.byte 0x0c 8.--15. 1. " RX_OCTET2 ,Receive octet 2 "
hexmask.long.byte 0x0c 0.--7. 1. " RX_OCTET1 ,Receive octet 1 "
; group.long 0x8B0++0x03
; line.long 0x00 "IOLINK3_CFG,IO-Link 3 Configuration Register "
; bitfld.long 0x00 31. "SET_STATUS,Set status vector to this register address " "Disabled,Enabled"
; bitfld.long 0x00 28.--30. "DEBUG_VEC,Debug vector" "0,1,2,3,4,5,6,7"
; textline " "
; bitfld.long 0x00 27. "RX_LSB_FIRST,LSByte first for receive process" "Disabled,Enabled"
; bitfld.long 0x00 26. "GEN_WAKE_UP,Set this bit to generate one wake up pulse " "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 25. "PIO_TX_OE_ACTIVE,Activate the link output control" "Disabled,Enabled"
; bitfld.long 0x00 24. "ENABLE_FM_INTR,Enable frame interrup" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 23. "LATCH_DVAL,Latch the delay value" "Disabled,Enabled"
; bitfld.long 0x00 22. "EN_DELAY,Enable delay function before transmitting the frame" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 21. "TX_LOOP,Enable tx auto repeat transmission" "Disabled,Enabled"
; bitfld.long 0x00 20. "TX_OE_DIS,Disable the tx_oe generation if wake up generation proceeds" "Enabled,Disabled"
; textline " "
; bitfld.long 0x00 19. "EN_FRAME_TIMEOUT,Enable the frame timeout function" "Disabled,Enabled"
; bitfld.long 0x00 18. "TX_INIT,Default tx output level" "Low,High"
; textline " "
; bitfld.long 0x00 17. "TX_LSB_FIRST,LSByte first for transmit process" "Disabled,Enabled"
; bitfld.long 0x00 16. "SNGL_TRANS,Single frame transfer mode" "0,1"
; textline " "
; bitfld.long 0x00 13.--14. "NR_RX_OCT,Number for octets to receive" "1,2,3,4"
; bitfld.long 0x00 10.--12. "NR_TX_OCT,Number for octets to transmit" "1,2,3,4,5,?..."
; textline " "
; bitfld.long 0x00 8.--9. "FREQ_SEL,Set the baud rate (T_clk)" "250ns test only,208.33 us com1 - 4800 Baud,26.04 us com2 - 38400 Baud,4.34 us com3 - 230400 Baud"
; textline " "
; hexmask.long.byte 0x00 0.--7. 1. "FRAME_CYCLE,Half of number of T_clk cycles"
rgroup.long 0x8C0++0x0f "IO-Link Configuration Register 4"
line.long 0x00 "IOLINK4_CFG,IO-Link 4 Configuration Register "
hexmask.long.byte 0x0 25.--31. 1. " Tclk_cnt_r ,MSB of the baud rate counter"
bitfld.long 0x00 22.--24. " Ad_rx_oct_r ,Current rx transfer counter " "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--21. 1. " Frame_cycle_cnt_r ,Current frame cycle counter"
textline " "
bitfld.long 0x00 10.--12. " Tx_oct_cnt_r ,Lower bits of current tx transfer counter " "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. " Stop_bit_error_r ,Stop bit error in last transmission " "0,1"
bitfld.long 0x00 8. " Rx_sum_p_err_r ,Parity error in last transmission " "0,1"
textline " "
bitfld.long 0x00 4.--7. " Fsm_io_link_st ,Status of the IOLINK state machine " "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x00 3. " Tx_oe_r ,Current status tx_oe port" "0,1"
bitfld.long 0x00 2. " Wake_up_r ,Current status of wake up port " "0,1"
textline " "
bitfld.long 0x00 1. " Rxd_in ,Current status of rx port " "0,1"
bitfld.long 0x00 0. " Txd_r ,Current status of tx port " "0,1"
line.long 0x04 "IOLINK4_TX_FRM0,IO-Link 4 TX0 Data Register"
hexmask.long.byte 0x04 24.--31. 1. " TX_OCTET4 ,Transmit octet 4 "
hexmask.long.byte 0x04 16.--23. 1. " TX_OCTET3 ,Transmit octet 3 "
textline " "
hexmask.long.byte 0x04 8.--15. 1. " TX_OCTET2 ,Transmit octet 2 "
hexmask.long.byte 0x04 0.--7. 1. " TX_OCTET1 ,Transmit octet 1 "
line.long 0x08 "IOLINK4_TX_FRM1,IO-Link 4 TX1 Data Register"
hexmask.long.byte 0x08 24.--31. 1. " TX_OCTET8 ,Transmit octet 8 "
hexmask.long.byte 0x08 16.--23. 1. " TX_OCTET7 ,Transmit octet 7 "
textline " "
hexmask.long.byte 0x08 8.--15. 1. " TX_OCTET6 ,Transmit octet 6 "
hexmask.long.byte 0x08 0.--7. 1. " TX_OCTET5 ,Transmit octet 5 "
line.long 0x0c "IOLINK4_RX_FRM,IO-Link 4 RX Data Register "
hexmask.long.byte 0x0c 24.--31. 1. " RX_OCTET4 ,Receive octet 4 "
hexmask.long.byte 0x0c 16.--23. 1. " RX_OCTET3 ,Receive octet 3 "
textline " "
hexmask.long.byte 0x0c 8.--15. 1. " RX_OCTET2 ,Receive octet 2 "
hexmask.long.byte 0x0c 0.--7. 1. " RX_OCTET1 ,Receive octet 1 "
; group.long 0x8C0++0x03
; line.long 0x00 "IOLINK4_CFG,IO-Link 4 Configuration Register "
; bitfld.long 0x00 31. "SET_STATUS,Set status vector to this register address " "Disabled,Enabled"
; bitfld.long 0x00 28.--30. "DEBUG_VEC,Debug vector" "0,1,2,3,4,5,6,7"
; textline " "
; bitfld.long 0x00 27. "RX_LSB_FIRST,LSByte first for receive process" "Disabled,Enabled"
; bitfld.long 0x00 26. "GEN_WAKE_UP,Set this bit to generate one wake up pulse " "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 25. "PIO_TX_OE_ACTIVE,Activate the link output control" "Disabled,Enabled"
; bitfld.long 0x00 24. "ENABLE_FM_INTR,Enable frame interrup" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 23. "LATCH_DVAL,Latch the delay value" "Disabled,Enabled"
; bitfld.long 0x00 22. "EN_DELAY,Enable delay function before transmitting the frame" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 21. "TX_LOOP,Enable tx auto repeat transmission" "Disabled,Enabled"
; bitfld.long 0x00 20. "TX_OE_DIS,Disable the tx_oe generation if wake up generation proceeds" "Enabled,Disabled"
; textline " "
; bitfld.long 0x00 19. "EN_FRAME_TIMEOUT,Enable the frame timeout function" "Disabled,Enabled"
; bitfld.long 0x00 18. "TX_INIT,Default tx output level" "Low,High"
; textline " "
; bitfld.long 0x00 17. "TX_LSB_FIRST,LSByte first for transmit process" "Disabled,Enabled"
; bitfld.long 0x00 16. "SNGL_TRANS,Single frame transfer mode" "0,1"
; textline " "
; bitfld.long 0x00 13.--14. "NR_RX_OCT,Number for octets to receive" "1,2,3,4"
; bitfld.long 0x00 10.--12. "NR_TX_OCT,Number for octets to transmit" "1,2,3,4,5,?..."
; textline " "
; bitfld.long 0x00 8.--9. "FREQ_SEL,Set the baud rate (T_clk)" "250ns test only,208.33 us com1 - 4800 Baud,26.04 us com2 - 38400 Baud,4.34 us com3 - 230400 Baud"
; textline " "
; hexmask.long.byte 0x00 0.--7. 1. "FRAME_CYCLE,Half of number of T_clk cycles"
rgroup.long 0x8D0++0x0f "IO-Link Configuration Register 5"
line.long 0x00 "IOLINK5_CFG,IO-Link 5 Configuration Register "
hexmask.long.byte 0x0 25.--31. 1. " Tclk_cnt_r ,MSB of the baud rate counter"
bitfld.long 0x00 22.--24. " Ad_rx_oct_r ,Current rx transfer counter " "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--21. 1. " Frame_cycle_cnt_r ,Current frame cycle counter"
textline " "
bitfld.long 0x00 10.--12. " Tx_oct_cnt_r ,Lower bits of current tx transfer counter " "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. " Stop_bit_error_r ,Stop bit error in last transmission " "0,1"
bitfld.long 0x00 8. " Rx_sum_p_err_r ,Parity error in last transmission " "0,1"
textline " "
bitfld.long 0x00 4.--7. " Fsm_io_link_st ,Status of the IOLINK state machine " "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x00 3. " Tx_oe_r ,Current status tx_oe port" "0,1"
bitfld.long 0x00 2. " Wake_up_r ,Current status of wake up port " "0,1"
textline " "
bitfld.long 0x00 1. " Rxd_in ,Current status of rx port " "0,1"
bitfld.long 0x00 0. " Txd_r ,Current status of tx port " "0,1"
line.long 0x04 "IOLINK5_TX_FRM0,IO-Link 5 TX0 Data Register"
hexmask.long.byte 0x04 24.--31. 1. " TX_OCTET4 ,Transmit octet 4 "
hexmask.long.byte 0x04 16.--23. 1. " TX_OCTET3 ,Transmit octet 3 "
textline " "
hexmask.long.byte 0x04 8.--15. 1. " TX_OCTET2 ,Transmit octet 2 "
hexmask.long.byte 0x04 0.--7. 1. " TX_OCTET1 ,Transmit octet 1 "
line.long 0x08 "IOLINK5_TX_FRM1,IO-Link 5 TX1 Data Register"
hexmask.long.byte 0x08 24.--31. 1. " TX_OCTET8 ,Transmit octet 8 "
hexmask.long.byte 0x08 16.--23. 1. " TX_OCTET7 ,Transmit octet 7 "
textline " "
hexmask.long.byte 0x08 8.--15. 1. " TX_OCTET6 ,Transmit octet 6 "
hexmask.long.byte 0x08 0.--7. 1. " TX_OCTET5 ,Transmit octet 5 "
line.long 0x0c "IOLINK5_RX_FRM,IO-Link 5 RX Data Register "
hexmask.long.byte 0x0c 24.--31. 1. " RX_OCTET4 ,Receive octet 4 "
hexmask.long.byte 0x0c 16.--23. 1. " RX_OCTET3 ,Receive octet 3 "
textline " "
hexmask.long.byte 0x0c 8.--15. 1. " RX_OCTET2 ,Receive octet 2 "
hexmask.long.byte 0x0c 0.--7. 1. " RX_OCTET1 ,Receive octet 1 "
; group.long 0x8D0++0x03
; line.long 0x00 "IOLINK5_CFG,IO-Link 5 Configuration Register "
; bitfld.long 0x00 31. "SET_STATUS,Set status vector to this register address " "Disabled,Enabled"
; bitfld.long 0x00 28.--30. "DEBUG_VEC,Debug vector" "0,1,2,3,4,5,6,7"
; textline " "
; bitfld.long 0x00 27. "RX_LSB_FIRST,LSByte first for receive process" "Disabled,Enabled"
; bitfld.long 0x00 26. "GEN_WAKE_UP,Set this bit to generate one wake up pulse " "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 25. "PIO_TX_OE_ACTIVE,Activate the link output control" "Disabled,Enabled"
; bitfld.long 0x00 24. "ENABLE_FM_INTR,Enable frame interrup" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 23. "LATCH_DVAL,Latch the delay value" "Disabled,Enabled"
; bitfld.long 0x00 22. "EN_DELAY,Enable delay function before transmitting the frame" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 21. "TX_LOOP,Enable tx auto repeat transmission" "Disabled,Enabled"
; bitfld.long 0x00 20. "TX_OE_DIS,Disable the tx_oe generation if wake up generation proceeds" "Enabled,Disabled"
; textline " "
; bitfld.long 0x00 19. "EN_FRAME_TIMEOUT,Enable the frame timeout function" "Disabled,Enabled"
; bitfld.long 0x00 18. "TX_INIT,Default tx output level" "Low,High"
; textline " "
; bitfld.long 0x00 17. "TX_LSB_FIRST,LSByte first for transmit process" "Disabled,Enabled"
; bitfld.long 0x00 16. "SNGL_TRANS,Single frame transfer mode" "0,1"
; textline " "
; bitfld.long 0x00 13.--14. "NR_RX_OCT,Number for octets to receive" "1,2,3,4"
; bitfld.long 0x00 10.--12. "NR_TX_OCT,Number for octets to transmit" "1,2,3,4,5,?..."
; textline " "
; bitfld.long 0x00 8.--9. "FREQ_SEL,Set the baud rate (T_clk)" "250ns test only,208.33 us com1 - 4800 Baud,26.04 us com2 - 38400 Baud,4.34 us com3 - 230400 Baud"
; textline " "
; hexmask.long.byte 0x00 0.--7. 1. "FRAME_CYCLE,Half of number of T_clk cycles"
rgroup.long 0x8E0++0x0f "IO-Link Configuration Register 6"
line.long 0x00 "IOLINK6_CFG,IO-Link 6 Configuration Register "
hexmask.long.byte 0x0 25.--31. 1. " Tclk_cnt_r ,MSB of the baud rate counter"
bitfld.long 0x00 22.--24. " Ad_rx_oct_r ,Current rx transfer counter " "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--21. 1. " Frame_cycle_cnt_r ,Current frame cycle counter"
textline " "
bitfld.long 0x00 10.--12. " Tx_oct_cnt_r ,Lower bits of current tx transfer counter " "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. " Stop_bit_error_r ,Stop bit error in last transmission " "0,1"
bitfld.long 0x00 8. " Rx_sum_p_err_r ,Parity error in last transmission " "0,1"
textline " "
bitfld.long 0x00 4.--7. " Fsm_io_link_st ,Status of the IOLINK state machine " "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x00 3. " Tx_oe_r ,Current status tx_oe port" "0,1"
bitfld.long 0x00 2. " Wake_up_r ,Current status of wake up port " "0,1"
textline " "
bitfld.long 0x00 1. " Rxd_in ,Current status of rx port " "0,1"
bitfld.long 0x00 0. " Txd_r ,Current status of tx port " "0,1"
line.long 0x04 "IOLINK6_TX_FRM0,IO-Link 6 TX0 Data Register"
hexmask.long.byte 0x04 24.--31. 1. " TX_OCTET4 ,Transmit octet 4 "
hexmask.long.byte 0x04 16.--23. 1. " TX_OCTET3 ,Transmit octet 3 "
textline " "
hexmask.long.byte 0x04 8.--15. 1. " TX_OCTET2 ,Transmit octet 2 "
hexmask.long.byte 0x04 0.--7. 1. " TX_OCTET1 ,Transmit octet 1 "
line.long 0x08 "IOLINK6_TX_FRM1,IO-Link 6 TX1 Data Register"
hexmask.long.byte 0x08 24.--31. 1. " TX_OCTET8 ,Transmit octet 8 "
hexmask.long.byte 0x08 16.--23. 1. " TX_OCTET7 ,Transmit octet 7 "
textline " "
hexmask.long.byte 0x08 8.--15. 1. " TX_OCTET6 ,Transmit octet 6 "
hexmask.long.byte 0x08 0.--7. 1. " TX_OCTET5 ,Transmit octet 5 "
line.long 0x0c "IOLINK6_RX_FRM,IO-Link 6 RX Data Register "
hexmask.long.byte 0x0c 24.--31. 1. " RX_OCTET4 ,Receive octet 4 "
hexmask.long.byte 0x0c 16.--23. 1. " RX_OCTET3 ,Receive octet 3 "
textline " "
hexmask.long.byte 0x0c 8.--15. 1. " RX_OCTET2 ,Receive octet 2 "
hexmask.long.byte 0x0c 0.--7. 1. " RX_OCTET1 ,Receive octet 1 "
; group.long 0x8E0++0x03
; line.long 0x00 "IOLINK6_CFG,IO-Link 6 Configuration Register "
; bitfld.long 0x00 31. "SET_STATUS,Set status vector to this register address " "Disabled,Enabled"
; bitfld.long 0x00 28.--30. "DEBUG_VEC,Debug vector" "0,1,2,3,4,5,6,7"
; textline " "
; bitfld.long 0x00 27. "RX_LSB_FIRST,LSByte first for receive process" "Disabled,Enabled"
; bitfld.long 0x00 26. "GEN_WAKE_UP,Set this bit to generate one wake up pulse " "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 25. "PIO_TX_OE_ACTIVE,Activate the link output control" "Disabled,Enabled"
; bitfld.long 0x00 24. "ENABLE_FM_INTR,Enable frame interrup" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 23. "LATCH_DVAL,Latch the delay value" "Disabled,Enabled"
; bitfld.long 0x00 22. "EN_DELAY,Enable delay function before transmitting the frame" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 21. "TX_LOOP,Enable tx auto repeat transmission" "Disabled,Enabled"
; bitfld.long 0x00 20. "TX_OE_DIS,Disable the tx_oe generation if wake up generation proceeds" "Enabled,Disabled"
; textline " "
; bitfld.long 0x00 19. "EN_FRAME_TIMEOUT,Enable the frame timeout function" "Disabled,Enabled"
; bitfld.long 0x00 18. "TX_INIT,Default tx output level" "Low,High"
; textline " "
; bitfld.long 0x00 17. "TX_LSB_FIRST,LSByte first for transmit process" "Disabled,Enabled"
; bitfld.long 0x00 16. "SNGL_TRANS,Single frame transfer mode" "0,1"
; textline " "
; bitfld.long 0x00 13.--14. "NR_RX_OCT,Number for octets to receive" "1,2,3,4"
; bitfld.long 0x00 10.--12. "NR_TX_OCT,Number for octets to transmit" "1,2,3,4,5,?..."
; textline " "
; bitfld.long 0x00 8.--9. "FREQ_SEL,Set the baud rate (T_clk)" "250ns test only,208.33 us com1 - 4800 Baud,26.04 us com2 - 38400 Baud,4.34 us com3 - 230400 Baud"
; textline " "
; hexmask.long.byte 0x00 0.--7. 1. "FRAME_CYCLE,Half of number of T_clk cycles"
rgroup.long 0x8F0++0x0f "IO-Link Configuration Register 7"
line.long 0x00 "IOLINK7_CFG,IO-Link 7 Configuration Register "
hexmask.long.byte 0x0 25.--31. 1. " Tclk_cnt_r ,MSB of the baud rate counter"
bitfld.long 0x00 22.--24. " Ad_rx_oct_r ,Current rx transfer counter " "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 13.--21. 1. " Frame_cycle_cnt_r ,Current frame cycle counter"
textline " "
bitfld.long 0x00 10.--12. " Tx_oct_cnt_r ,Lower bits of current tx transfer counter " "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. " Stop_bit_error_r ,Stop bit error in last transmission " "0,1"
bitfld.long 0x00 8. " Rx_sum_p_err_r ,Parity error in last transmission " "0,1"
textline " "
bitfld.long 0x00 4.--7. " Fsm_io_link_st ,Status of the IOLINK state machine " "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x00 3. " Tx_oe_r ,Current status tx_oe port" "0,1"
bitfld.long 0x00 2. " Wake_up_r ,Current status of wake up port " "0,1"
textline " "
bitfld.long 0x00 1. " Rxd_in ,Current status of rx port " "0,1"
bitfld.long 0x00 0. " Txd_r ,Current status of tx port " "0,1"
line.long 0x04 "IOLINK7_TX_FRM0,IO-Link 7 TX0 Data Register"
hexmask.long.byte 0x04 24.--31. 1. " TX_OCTET4 ,Transmit octet 4 "
hexmask.long.byte 0x04 16.--23. 1. " TX_OCTET3 ,Transmit octet 3 "
textline " "
hexmask.long.byte 0x04 8.--15. 1. " TX_OCTET2 ,Transmit octet 2 "
hexmask.long.byte 0x04 0.--7. 1. " TX_OCTET1 ,Transmit octet 1 "
line.long 0x08 "IOLINK7_TX_FRM1,IO-Link 7 TX1 Data Register"
hexmask.long.byte 0x08 24.--31. 1. " TX_OCTET8 ,Transmit octet 8 "
hexmask.long.byte 0x08 16.--23. 1. " TX_OCTET7 ,Transmit octet 7 "
textline " "
hexmask.long.byte 0x08 8.--15. 1. " TX_OCTET6 ,Transmit octet 6 "
hexmask.long.byte 0x08 0.--7. 1. " TX_OCTET5 ,Transmit octet 5 "
line.long 0x0c "IOLINK7_RX_FRM,IO-Link 7 RX Data Register "
hexmask.long.byte 0x0c 24.--31. 1. " RX_OCTET4 ,Receive octet 4 "
hexmask.long.byte 0x0c 16.--23. 1. " RX_OCTET3 ,Receive octet 3 "
textline " "
hexmask.long.byte 0x0c 8.--15. 1. " RX_OCTET2 ,Receive octet 2 "
hexmask.long.byte 0x0c 0.--7. 1. " RX_OCTET1 ,Receive octet 1 "
; group.long 0x8F0++0x03
; line.long 0x00 "IOLINK7_CFG,IO-Link 7 Configuration Register "
; bitfld.long 0x00 31. "SET_STATUS,Set status vector to this register address " "Disabled,Enabled"
; bitfld.long 0x00 28.--30. "DEBUG_VEC,Debug vector" "0,1,2,3,4,5,6,7"
; textline " "
; bitfld.long 0x00 27. "RX_LSB_FIRST,LSByte first for receive process" "Disabled,Enabled"
; bitfld.long 0x00 26. "GEN_WAKE_UP,Set this bit to generate one wake up pulse " "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 25. "PIO_TX_OE_ACTIVE,Activate the link output control" "Disabled,Enabled"
; bitfld.long 0x00 24. "ENABLE_FM_INTR,Enable frame interrup" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 23. "LATCH_DVAL,Latch the delay value" "Disabled,Enabled"
; bitfld.long 0x00 22. "EN_DELAY,Enable delay function before transmitting the frame" "Disabled,Enabled"
; textline " "
; bitfld.long 0x00 21. "TX_LOOP,Enable tx auto repeat transmission" "Disabled,Enabled"
; bitfld.long 0x00 20. "TX_OE_DIS,Disable the tx_oe generation if wake up generation proceeds" "Enabled,Disabled"
; textline " "
; bitfld.long 0x00 19. "EN_FRAME_TIMEOUT,Enable the frame timeout function" "Disabled,Enabled"
; bitfld.long 0x00 18. "TX_INIT,Default tx output level" "Low,High"
; textline " "
; bitfld.long 0x00 17. "TX_LSB_FIRST,LSByte first for transmit process" "Disabled,Enabled"
; bitfld.long 0x00 16. "SNGL_TRANS,Single frame transfer mode" "0,1"
; textline " "
; bitfld.long 0x00 13.--14. "NR_RX_OCT,Number for octets to receive" "1,2,3,4"
; bitfld.long 0x00 10.--12. "NR_TX_OCT,Number for octets to transmit" "1,2,3,4,5,?..."
; textline " "
; bitfld.long 0x00 8.--9. "FREQ_SEL,Set the baud rate (T_clk)" "250ns test only,208.33 us com1 - 4800 Baud,26.04 us com2 - 38400 Baud,4.34 us com3 - 230400 Baud"
; textline " "
; hexmask.long.byte 0x00 0.--7. 1. "FRAME_CYCLE,Half of number of T_clk cycles"
width 0x0b
tree.end
tree "Peripheral Inputs Outputs (PIO)"
base asd:0x1c000a00
width 9.
rgroup.long 0x00++0x03
line.long 0x00 "PIO_IN,PIO Input Register"
bitfld.long 0x00 7. " VAL7 ,PIO7 input value" "0,1"
bitfld.long 0x00 6. " VAL6 ,PIO6 input value" "0,1"
bitfld.long 0x00 5. " VAL5 ,PIO5 input value" "0,1"
textline " "
bitfld.long 0x00 4. " VAL4 ,PIO4 input value" "0,1"
bitfld.long 0x00 3. " VAL3 ,PIO3 input value" "0,1"
bitfld.long 0x00 2. " VAL2 ,PIO2 input value" "0,1"
textline " "
bitfld.long 0x00 1. " VAL1 ,PIO1 input value" "0,1"
bitfld.long 0x00 0. " VAL0 ,PIO0 input value" "0,1"
group.long 0x04++0x07
line.long 0x00 "PIO_OUT,PIO Output Register"
bitfld.long 0x00 7. " VAL7 ,PIO7 output value" "0,1"
bitfld.long 0x00 6. " VAL6 ,PIO6 output value" "0,1"
bitfld.long 0x00 5. " VAL5 ,PIO5 output value" "0,1"
textline " "
bitfld.long 0x00 4. " VAL4 ,PIO4 output value" "0,1"
bitfld.long 0x00 3. " VAL3 ,PIO3 output value" "0,1"
bitfld.long 0x00 2. " VAL2 ,PIO2 output value" "0,1"
textline " "
bitfld.long 0x00 1. " VAL1 ,PIO1 output value" "0,1"
bitfld.long 0x00 0. " VAL0 ,PIO0 output value" "0,1"
line.long 0x04 "PIO_OE,PIO Output Enable Register"
bitfld.long 0x04 7. " VAL7 ,PIO7 output enable" "Disabled,Enabled"
bitfld.long 0x04 6. " VAL6 ,PIO6 output enable" "Disabled,Enabled"
bitfld.long 0x04 5. " VAL5 ,PIO5 output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 4. " VAL4 ,PIO4 output enable" "Disabled,Enabled"
bitfld.long 0x04 3. " VAL3 ,PIO3 output enable" "Disabled,Enabled"
bitfld.long 0x04 2. " VAL2 ,PIO2 output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " VAL1 ,PIO1 output enable" "Disabled,Enabled"
bitfld.long 0x04 0. " VAL0 ,PIO0 output enable" "Disabled,Enabled"
width 0x0b
tree.end
tree "Universal Asynchronous Receiver Transmitter (UART)"
tree "UART0"
base asd:0x1c000b00
width 25.
hgroup.long 0x00++0x03
hide.long 0x00 "UART0_DATA,UART 0 Data Register"
in
group.long 0x04++0x13
line.long 0x00 "UART0_STAT,UART 0 Status Register"
bitfld.long 0x00 3. " OE ,Overrun Error" "No error,Error"
bitfld.long 0x00 2. " BE ,Break Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " PE ,Parity Error" "No error,Error"
bitfld.long 0x00 0. " FE ,Framing Error" "No error,Error"
line.long 0x04 "UART0_LINE_CTRL,UART 0 Line Control Register"
bitfld.long 0x04 5.--6. " WLEN ,Word length" "5 bits,6 bits,7 bits,8 bits"
bitfld.long 0x04 4. " FEN ,Enable FIFOs" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "Disabled,Enabled"
bitfld.long 0x04 2. " EPS ,Even Parity Select" "Odd,Even"
textline " "
bitfld.long 0x04 1. " PEN ,Parity Enable" "Disabled,Enabled"
bitfld.long 0x04 0. " BRK ,Send Break" "Disabled,Enabled"
line.long 0x08 "UART0_BAUDDIV_MSB,UART 0 Baud Rate Divisor MSB"
hexmask.long.byte 0x08 0.--7. 1. " BAUDDIV_MSB ,Baud Rate Divisor [15:8]"
line.long 0x0c "UART0_BAUDDIV_LSB,UART 0 Baud Rate Divisor LSB"
hexmask.long.byte 0x0c 0.--7. 1. " BAUDDIV_LSB ,Baud Rate Divisor [7:0]"
line.long 0x10 "UART0_CTRL,UART 0 Control Register"
bitfld.long 0x10 8. " TX_RX_LOOP ,Internal loop (TX -> RX)" "Disabled,Enabled"
textline " "
bitfld.long 0x10 7. " LBE ,Loop back enable" "Disabled,Enabled"
bitfld.long 0x10 6. " RTIE ,Receive timeout interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 5. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 4. " RIE ,Receive interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 3. " MSIE ,Modem status interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 2. " SIRLP ,IrDA SIR low power mode" "Disabled,Enabled"
textline " "
bitfld.long 0x10 1. " SIREN ,The IrDA SIR Endec enable" "Disabled,Enabled"
bitfld.long 0x10 0. " UARTEN ,UART enable" "Disabled,Enabled"
rgroup.long 0x18++0x03
line.long 0x00 "UART0_FLAG,UART 0 Flag Register"
bitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
bitfld.long 0x00 6. " RXFF ,Receive FIFO full" "Not full,Full"
textline " "
bitfld.long 0x00 5. " TXFF ,Transmit FIFO full" "Not full,Full"
bitfld.long 0x00 4. " RXFE ,Receive FIFO empty" "Not empty,Empty"
textline " "
bitfld.long 0x00 3. " BUSY ,UART busy" "Not busy,Busy"
bitfld.long 0x00 2. " DCD ,Data carrier detect" "Not detected,Detected"
textline " "
bitfld.long 0x00 1. " DSR ,Data set ready" "Not ready,Ready"
bitfld.long 0x00 0. " CTS ,Clear to send" "Low,High"
group.long 0x1C++0x23
line.long 0x00 "UART0_INT_ID,UART 0 Interrupt Identification Register"
bitfld.long 0x00 3. " RTIS ,Receive timeout interrupt status" "Not asserted,Asserted"
bitfld.long 0x00 2. " TIS ,Transmit interrupt status" "Not asserted,Asserted"
textline " "
bitfld.long 0x00 1. " RIS ,Receive interrupt status" "Not asserted,Asserted"
bitfld.long 0x00 0. " MIS ,Modem Interrupt Status" "Not asserted,Asserted"
line.long 0x04 "UART0_IR_LO_PWR_CR,UART 0 IrDA Low Power Counter Register"
hexmask.long.byte 0x04 0.--7. 1. " ILPDVSR ,IrDA Low Power Divisor value [7:0]"
line.long 0x08 "UART0_RTS_CTRL,UART 0 RTS Control Register"
bitfld.long 0x08 7. " STICK ,Parity bit works as stick bit" "Disabled,Enabled"
bitfld.long 0x08 6. " CTS_POL ,CTS polarity" "Low,High"
textline " "
bitfld.long 0x08 5. " CTS_CTR ,CTS control" "Disabled,Enabled"
bitfld.long 0x08 4. " RTS_POL ,RTS polarity" "Low,High"
textline " "
bitfld.long 0x08 3. " MOD2 ,Machine trail state activated by" "Character sent,Empty FIFO"
bitfld.long 0x08 2. " COUNT ,RTS counter time base" "Baud,System clock"
textline " "
bitfld.long 0x08 1. " RTS ,RTS output" "Disabled,Enabled"
bitfld.long 0x08 0. " AUTO ,RTS output controll" "Direct,Automatic"
line.long 0x0c "UART0_RTS_LEAD_CYC,UART 0 RTS Leading Cycles"
hexmask.long.byte 0x0c 0.--7. 1. " LEAD_CYC ,Number of leading cycles in system clocks or baud rate cycles"
line.long 0x10 "UART0_RTS_TRAIL_CYC,UART 0 RTS Trailing cycles"
hexmask.long.byte 0x10 0.--7. 1. " TRAIL_CYC ,Number of trail cycles in system clocks or baud rate cycles"
line.long 0x14 "UART0_OUT_DRV_EN,UART 0 Driver Enable Register"
bitfld.long 0x14 1. " DRVRTS ,Driver for UARTi_RTS output pin" "Disabled,Enabled"
bitfld.long 0x14 0. " DRVTX ,Driver for UARTi_TXD output pin" "Disabled,Enabled"
line.long 0x18 "UART0_BM_CTRL,UART 0 Baud Rate Mode Control Register"
bitfld.long 0x18 0. " BAUD_RATE_MODE ,Sets the generation method of baudrate" "Mode 1,Mode 2"
line.long 0x1c "UART0_RX_FIFO_IRQ_LVL,UART 0 Receive FIFO Interrupt Trigger Level"
bitfld.long 0x1c 5. " RXDMA ,Enable DMA-requests for RX-fifo-data" "Disabled,Enabled"
bitfld.long 0x1c 0.--4. " RFIRQLEVEL ,IRQ trigger level of the receive FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x20 "UART0_TX_FIFO_IRQ_LVL,UART 0 Transmit FIFO Interrupt Trigger Level"
bitfld.long 0x20 5. " TXDMA ,Enable DMA-requests for TX-fifo-data" "Disabled,Enabled"
bitfld.long 0x20 0.--4. " TFIRQLEVEL ,IRQ trigger level of the transmit FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
width 0x0B
tree.end
tree "UART1"
base asd:0x1c000b40
width 25.
hgroup.long 0x00++0x03
hide.long 0x00 "UART1_DATA,UART 1 Data Register"
in
group.long 0x04++0x13
line.long 0x00 "UART1_STAT,UART 1 Status Register"
bitfld.long 0x00 3. " OE ,Overrun Error" "No error,Error"
bitfld.long 0x00 2. " BE ,Break Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " PE ,Parity Error" "No error,Error"
bitfld.long 0x00 0. " FE ,Framing Error" "No error,Error"
line.long 0x04 "UART1_LINE_CTRL,UART 1 Line Control Register"
bitfld.long 0x04 5.--6. " WLEN ,Word length" "5 bits,6 bits,7 bits,8 bits"
bitfld.long 0x04 4. " FEN ,Enable FIFOs" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "Disabled,Enabled"
bitfld.long 0x04 2. " EPS ,Even Parity Select" "Odd,Even"
textline " "
bitfld.long 0x04 1. " PEN ,Parity Enable" "Disabled,Enabled"
bitfld.long 0x04 0. " BRK ,Send Break" "Disabled,Enabled"
line.long 0x08 "UART1_BAUDDIV_MSB,UART 1 Baud Rate Divisor MSB"
hexmask.long.byte 0x08 0.--7. 1. " BAUDDIV_MSB ,Baud Rate Divisor [15:8]"
line.long 0x0c "UART1_BAUDDIV_LSB,UART 1 Baud Rate Divisor LSB"
hexmask.long.byte 0x0c 0.--7. 1. " BAUDDIV_LSB ,Baud Rate Divisor [7:0]"
line.long 0x10 "UART1_CTRL,UART 1 Control Register"
bitfld.long 0x10 8. " TX_RX_LOOP ,Internal loop (TX -> RX)" "Disabled,Enabled"
textline " "
bitfld.long 0x10 7. " LBE ,Loop back enable" "Disabled,Enabled"
bitfld.long 0x10 6. " RTIE ,Receive timeout interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 5. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 4. " RIE ,Receive interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 3. " MSIE ,Modem status interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 2. " SIRLP ,IrDA SIR low power mode" "Disabled,Enabled"
textline " "
bitfld.long 0x10 1. " SIREN ,The IrDA SIR Endec enable" "Disabled,Enabled"
bitfld.long 0x10 0. " UARTEN ,UART enable" "Disabled,Enabled"
rgroup.long 0x18++0x03
line.long 0x00 "UART1_FLAG,UART 1 Flag Register"
bitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
bitfld.long 0x00 6. " RXFF ,Receive FIFO full" "Not full,Full"
textline " "
bitfld.long 0x00 5. " TXFF ,Transmit FIFO full" "Not full,Full"
bitfld.long 0x00 4. " RXFE ,Receive FIFO empty" "Not empty,Empty"
textline " "
bitfld.long 0x00 3. " BUSY ,UART busy" "Not busy,Busy"
bitfld.long 0x00 2. " DCD ,Data carrier detect" "Not detected,Detected"
textline " "
bitfld.long 0x00 1. " DSR ,Data set ready" "Not ready,Ready"
bitfld.long 0x00 0. " CTS ,Clear to send" "Low,High"
group.long 0x1C++0x23
line.long 0x00 "UART1_INT_ID,UART 1 Interrupt Identification Register"
bitfld.long 0x00 3. " RTIS ,Receive timeout interrupt status" "Not asserted,Asserted"
bitfld.long 0x00 2. " TIS ,Transmit interrupt status" "Not asserted,Asserted"
textline " "
bitfld.long 0x00 1. " RIS ,Receive interrupt status" "Not asserted,Asserted"
bitfld.long 0x00 0. " MIS ,Modem Interrupt Status" "Not asserted,Asserted"
line.long 0x04 "UART1_IR_LO_PWR_CR,UART 1 IrDA Low Power Counter Register"
hexmask.long.byte 0x04 0.--7. 1. " ILPDVSR ,IrDA Low Power Divisor value [7:0]"
line.long 0x08 "UART1_RTS_CTRL,UART 1 RTS Control Register"
bitfld.long 0x08 7. " STICK ,Parity bit works as stick bit" "Disabled,Enabled"
bitfld.long 0x08 6. " CTS_POL ,CTS polarity" "Low,High"
textline " "
bitfld.long 0x08 5. " CTS_CTR ,CTS control" "Disabled,Enabled"
bitfld.long 0x08 4. " RTS_POL ,RTS polarity" "Low,High"
textline " "
bitfld.long 0x08 3. " MOD2 ,Machine trail state activated by" "Character sent,Empty FIFO"
bitfld.long 0x08 2. " COUNT ,RTS counter time base" "Baud,System clock"
textline " "
bitfld.long 0x08 1. " RTS ,RTS output" "Disabled,Enabled"
bitfld.long 0x08 0. " AUTO ,RTS output controll" "Direct,Automatic"
line.long 0x0c "UART1_RTS_LEAD_CYC,UART 1 RTS Leading Cycles"
hexmask.long.byte 0x0c 0.--7. 1. " LEAD_CYC ,Number of leading cycles in system clocks or baud rate cycles"
line.long 0x10 "UART1_RTS_TRAIL_CYC,UART 1 RTS Trailing cycles"
hexmask.long.byte 0x10 0.--7. 1. " TRAIL_CYC ,Number of trail cycles in system clocks or baud rate cycles"
line.long 0x14 "UART1_OUT_DRV_EN,UART 1 Driver Enable Register"
bitfld.long 0x14 1. " DRVRTS ,Driver for UARTi_RTS output pin" "Disabled,Enabled"
bitfld.long 0x14 0. " DRVTX ,Driver for UARTi_TXD output pin" "Disabled,Enabled"
line.long 0x18 "UART1_BM_CTRL,UART 1 Baud Rate Mode Control Register"
bitfld.long 0x18 0. " BAUD_RATE_MODE ,Sets the generation method of baudrate" "Mode 1,Mode 2"
line.long 0x1c "UART1_RX_FIFO_IRQ_LVL,UART 1 Receive FIFO Interrupt Trigger Level"
bitfld.long 0x1c 5. " RXDMA ,Enable DMA-requests for RX-fifo-data" "Disabled,Enabled"
bitfld.long 0x1c 0.--4. " RFIRQLEVEL ,IRQ trigger level of the receive FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x20 "UART1_TX_FIFO_IRQ_LVL,UART 1 Transmit FIFO Interrupt Trigger Level"
bitfld.long 0x20 5. " TXDMA ,Enable DMA-requests for TX-fifo-data" "Disabled,Enabled"
bitfld.long 0x20 0.--4. " TFIRQLEVEL ,IRQ trigger level of the transmit FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
width 0x0B
tree.end
tree "UART2"
base asd:0x1c000b80
width 25.
hgroup.long 0x00++0x03
hide.long 0x00 "UART2_DATA,UART 2 Data Register"
in
group.long 0x04++0x13
line.long 0x00 "UART2_STAT,UART 2 Status Register"
bitfld.long 0x00 3. " OE ,Overrun Error" "No error,Error"
bitfld.long 0x00 2. " BE ,Break Error" "No error,Error"
textline " "
bitfld.long 0x00 1. " PE ,Parity Error" "No error,Error"
bitfld.long 0x00 0. " FE ,Framing Error" "No error,Error"
line.long 0x04 "UART2_LINE_CTRL,UART 2 Line Control Register"
bitfld.long 0x04 5.--6. " WLEN ,Word length" "5 bits,6 bits,7 bits,8 bits"
bitfld.long 0x04 4. " FEN ,Enable FIFOs" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "Disabled,Enabled"
bitfld.long 0x04 2. " EPS ,Even Parity Select" "Odd,Even"
textline " "
bitfld.long 0x04 1. " PEN ,Parity Enable" "Disabled,Enabled"
bitfld.long 0x04 0. " BRK ,Send Break" "Disabled,Enabled"
line.long 0x08 "UART2_BAUDDIV_MSB,UART 2 Baud Rate Divisor MSB"
hexmask.long.byte 0x08 0.--7. 1. " BAUDDIV_MSB ,Baud Rate Divisor [15:8]"
line.long 0x0c "UART2_BAUDDIV_LSB,UART 2 Baud Rate Divisor LSB"
hexmask.long.byte 0x0c 0.--7. 1. " BAUDDIV_LSB ,Baud Rate Divisor [7:0]"
line.long 0x10 "UART2_CTRL,UART 2 Control Register"
bitfld.long 0x10 8. " TX_RX_LOOP ,Internal loop (TX -> RX)" "Disabled,Enabled"
textline " "
bitfld.long 0x10 7. " LBE ,Loop back enable" "Disabled,Enabled"
bitfld.long 0x10 6. " RTIE ,Receive timeout interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 5. " TIE ,Transmit interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 4. " RIE ,Receive interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 3. " MSIE ,Modem status interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 2. " SIRLP ,IrDA SIR low power mode" "Disabled,Enabled"
textline " "
bitfld.long 0x10 1. " SIREN ,The IrDA SIR Endec enable" "Disabled,Enabled"
bitfld.long 0x10 0. " UARTEN ,UART enable" "Disabled,Enabled"
rgroup.long 0x18++0x03
line.long 0x00 "UART2_FLAG,UART 2 Flag Register"
bitfld.long 0x00 7. " TXFE ,Transmit FIFO empty" "Not empty,Empty"
bitfld.long 0x00 6. " RXFF ,Receive FIFO full" "Not full,Full"
textline " "
bitfld.long 0x00 5. " TXFF ,Transmit FIFO full" "Not full,Full"
bitfld.long 0x00 4. " RXFE ,Receive FIFO empty" "Not empty,Empty"
textline " "
bitfld.long 0x00 3. " BUSY ,UART busy" "Not busy,Busy"
bitfld.long 0x00 2. " DCD ,Data carrier detect" "Not detected,Detected"
textline " "
bitfld.long 0x00 1. " DSR ,Data set ready" "Not ready,Ready"
bitfld.long 0x00 0. " CTS ,Clear to send" "Low,High"
group.long 0x1C++0x23
line.long 0x00 "UART2_INT_ID,UART 2 Interrupt Identification Register"
bitfld.long 0x00 3. " RTIS ,Receive timeout interrupt status" "Not asserted,Asserted"
bitfld.long 0x00 2. " TIS ,Transmit interrupt status" "Not asserted,Asserted"
textline " "
bitfld.long 0x00 1. " RIS ,Receive interrupt status" "Not asserted,Asserted"
bitfld.long 0x00 0. " MIS ,Modem Interrupt Status" "Not asserted,Asserted"
line.long 0x04 "UART2_IR_LO_PWR_CR,UART 2 IrDA Low Power Counter Register"
hexmask.long.byte 0x04 0.--7. 1. " ILPDVSR ,IrDA Low Power Divisor value [7:0]"
line.long 0x08 "UART2_RTS_CTRL,UART 2 RTS Control Register"
bitfld.long 0x08 7. " STICK ,Parity bit works as stick bit" "Disabled,Enabled"
bitfld.long 0x08 6. " CTS_POL ,CTS polarity" "Low,High"
textline " "
bitfld.long 0x08 5. " CTS_CTR ,CTS control" "Disabled,Enabled"
bitfld.long 0x08 4. " RTS_POL ,RTS polarity" "Low,High"
textline " "
bitfld.long 0x08 3. " MOD2 ,Machine trail state activated by" "Character sent,Empty FIFO"
bitfld.long 0x08 2. " COUNT ,RTS counter time base" "Baud,System clock"
textline " "
bitfld.long 0x08 1. " RTS ,RTS output" "Disabled,Enabled"
bitfld.long 0x08 0. " AUTO ,RTS output controll" "Direct,Automatic"
line.long 0x0c "UART2_RTS_LEAD_CYC,UART 2 RTS Leading Cycles"
hexmask.long.byte 0x0c 0.--7. 1. " LEAD_CYC ,Number of leading cycles in system clocks or baud rate cycles"
line.long 0x10 "UART2_RTS_TRAIL_CYC,UART 2 RTS Trailing cycles"
hexmask.long.byte 0x10 0.--7. 1. " TRAIL_CYC ,Number of trail cycles in system clocks or baud rate cycles"
line.long 0x14 "UART2_OUT_DRV_EN,UART 2 Driver Enable Register"
bitfld.long 0x14 1. " DRVRTS ,Driver for UARTi_RTS output pin" "Disabled,Enabled"
bitfld.long 0x14 0. " DRVTX ,Driver for UARTi_TXD output pin" "Disabled,Enabled"
line.long 0x18 "UART2_BM_CTRL,UART 2 Baud Rate Mode Control Register"
bitfld.long 0x18 0. " BAUD_RATE_MODE ,Sets the generation method of baudrate" "Mode 1,Mode 2"
line.long 0x1c "UART2_RX_FIFO_IRQ_LVL,UART 2 Receive FIFO Interrupt Trigger Level"
bitfld.long 0x1c 5. " RXDMA ,Enable DMA-requests for RX-fifo-data" "Disabled,Enabled"
bitfld.long 0x1c 0.--4. " RFIRQLEVEL ,IRQ trigger level of the receive FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
line.long 0x20 "UART2_TX_FIFO_IRQ_LVL,UART 2 Transmit FIFO Interrupt Trigger Level"
bitfld.long 0x20 5. " TXDMA ,Enable DMA-requests for TX-fifo-data" "Disabled,Enabled"
bitfld.long 0x20 0.--4. " TFIRQLEVEL ,IRQ trigger level of the transmit FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
width 0x0B
tree.end
tree.end
tree "Serial Peripheral Interface (SPI)"
tree "SPI0"
base asd:0x1c000d00
width 13.
group.long 0x00++0x3
line.long 0x00 "SPI0_CTRL0,SPI0 control register 0"
bitfld.long 0x00 28. " SLAVE_SIG_EARLY ,Generate MISO in slavemode" "Not generated,Generated"
bitfld.long 0x00 31. " NETX100_COMP ,Use netx100/500-compatible SPI mode" "Start transfer after writing data,Start transfer after setting CR_write or CR_read"
textline " "
bitfld.long 0x00 27. " FILTER_IN ,Receive-data is sampled every 10ns" "Not sampled,Sampled"
bitfld.long 0x00 24.--25. " FORMAT ,Frame format" "MOTOROLA SPI format,?..."
textline " "
hexmask.long.word 0x00 8.--19. 1. " SCK_MULADD ,Serial clock rate multiply add value"
bitfld.long 0x00 7. " SPH ,Serial clock phase" "Sample data at first clock edge edge,Sample data at second clock edge edge"
textline " "
bitfld.long 0x00 6. " SPO ,Serial clock polarity" "Idle: clock is low; first edge is rising,Idle: clock is high; first edge is falling"
textline " "
bitfld.long 0x00 0.--3. " DSS ,Data size select" "Reserved,Reserved,Reserved,4Bit,5Bit,6Bit,7Bit,8Bit,9Bit,10Bit,11Bit,12Bit,13Bit,14Bit,15Bit,16Bit"
group.long 0x04++0x3
line.long 0x00 "SPI0_CTRL1,SPI0 control register 1"
bitfld.long 0x00 28. " RX_FIFO_CLR ,Clear the receive-FIFOs" "Normal operation,Clear FIFO"
bitfld.long 0x00 24.--27. " RX_FIFO_WM ,Receive FIFO watermark for IRQ-generation" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
textline " "
bitfld.long 0x00 20. " TX_FIFO_CLR ,Clear the transmit-FIFOs" "Normal operation,Clear FIFO"
bitfld.long 0x00 16.--19. " TX_FIFO_WM ,Transmit FIFO watermark for IRQ-generation" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
textline " "
bitfld.long 0x00 11. " FSS_STATIC ,SPI static chip select" "CS auto-assert,CS manual via FSS"
bitfld.long 0x00 10. " FSS_SLV2 ,Frame or slave select" "0,1"
textline " "
bitfld.long 0x00 9. " FSS_SLV1 ,Frame or slave select" "0,1"
bitfld.long 0x00 8. " FSS_SLV0 ,Frame or slave select" "0,1"
textline " "
bitfld.long 0x00 3. " SOD ,Slave mode output disable" "No,Yes"
bitfld.long 0x00 2. " MS ,Mode select" "Master,Slave"
textline " "
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal operation,Loopback mode"
hgroup.long 0x08++0x3
hide.long 0x00 "SPI0_DATA,SPI0 data register"
in
width 22.
rgroup.long 0x0C++0x3
line.long 0x00 "SPI0_STATUS,SPI0 status register"
bitfld.long 0x00 31. " RX_FIFO_ERR_UNDR ,Receive FIFO under-run error occurred" "No error,Error"
textline " "
bitfld.long 0x00 30. " RX_FIFO_ERR_OVFL ,Receive FIFO overflow error occurred" "No error,Error"
bitfld.long 0x00 24.--28. " RX_FIFO_LEVEL ,Receive FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 23. " TX_FIFO_ERR_UNDR ,Transmit FIFO under-run error occurred" "No error,Error"
bitfld.long 0x00 22. " TX_FIFO_ERR_OVFL ,Transmit FIFO overflow error occurred" "No error,Error"
textline " "
bitfld.long 0x00 16.--20. " TX_FIFO_LEVEL ,Transmit FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4. " BSY ,Device busy" "Not busy,Busy"
textline " "
sif (cpuis("NETX51"))
bitfld.long 0x00 3. " RFF ,Receive FIFO is full" "Not Full,Full"
else
bitfld.long 0x00 3. " RFF ,Receive FIFO is full" "Full,Not Full"
endif
bitfld.long 0x00 2. " RNE ,Receive FIFO is not empty" "Empty,Not empty"
textline " "
bitfld.long 0x00 1. " TNF ,Transmit FIFO is not full" "Full,Not Full"
bitfld.long 0x00 0. " TFE ,Transmit FIFO is empty" "Not empty,Empty"
width 22.
group.long 0x10++0x3
line.long 0x00 "SPI0_CLK_PRE_SCL,SPI0 Clock Prescale Register"
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,Obsolete"
group.long 0x14++0x3
line.long 0x00 "SPI0_INT_MSK_SET_CLR,SPI0 Interrupt Mask Set or Clear"
bitfld.long 0x00 6. " TXEIM ,Transmit FIFO empty interrupt mask" "Not masked,Masked"
textline " "
bitfld.long 0x00 5. " RXFIM ,Receive FIFO full interrupt mask" "Not masked,Masked"
bitfld.long 0x00 4. " RXNEIM ,Transmit FIFO interrupt mask" "Not masked,Masked"
textline " "
bitfld.long 0x00 3. " TXIM ,Transmit FIFO interrupt mask" "Not masked,Masked"
bitfld.long 0x00 2. " RXIM ,Receive FIFO interrupt mask" "Not masked,Masked"
textline " "
bitfld.long 0x00 1. " RTIM ,Receive timeout interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. " RORIM ,Receive FIFO overrun interrupt mask" "Not masked,Masked"
rgroup.long 0x18++0x3
line.long 0x00 "SPI0_RAW_INT_STAT,SPI0 raw Interrupt status"
bitfld.long 0x00 6. " TXERIS ,Unmasked transmit FIFO empty interrupt state" "Not empty,Empty"
textline " "
bitfld.long 0x00 5. " RXFRIS ,Unmasked receive FIFO full interrupt state" "Not full,Full"
bitfld.long 0x00 4. " RXNERIS ,Unmasked receive FIFO not empty interrupt state" "Empty,Not empty"
textline " "
bitfld.long 0x00 3. " TXRIS ,Unmasked transmit FIFO interrupt state" "> = spi_ctrl1.tx_fifo_wm,< spi_ctrl1.tx_fifo_wm"
textline " "
bitfld.long 0x00 2. " RXRIS ,Unmasked receive FIFO interrupt state" "< = spi_ctrl1.rx_fifo_wm,> spi_ctrl1.rx_fifo_wm"
textline " "
bitfld.long 0x00 1. " RTRIS ,Unmasked receive timeout interrupt state" "Empty,Not empty"
bitfld.long 0x00 0. " RORRIS ,Unmasked receive FIFO overrun interrupt state" "No error,Error"
rgroup.long 0x1C++0x3
line.long 0x00 "SPI0_MSK_INT_STAT,SPI0 Mask Interrupt Status Register"
bitfld.long 0x00 6. " TXEMIS ,Masked transmit FIFO empty interrupt state" "No Interrupt,Interrupt"
textline " "
bitfld.long 0x00 5. " RXFMIS ,Masked receive FIFO full interrupt state" "No Interrupt,Interrupt"
bitfld.long 0x00 4. " RXNEMIS ,Masked receive FIFO not empty interrupt state" "No Interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " TXMIS ,Masked transmit FIFO interrupt state" "No Interrupt,Interrupt"
bitfld.long 0x00 2. " RXMIS ,Masked receive FIFO interrupt state" "No Interrupt,Interrupt"
textline " "
bitfld.long 0x00 1. " RTMIS ,Masked receive timeout interrupt state" "No Interrupt,Interrupt"
bitfld.long 0x00 0. " RORMIS ,Masked receive FIFO overrun interrupt state" "No Interrupt,Interrupt"
group.long 0x20++0x7
line.long 0x00 "SPI0_INT_CLR,SPI0 Interrupt Clear Register"
bitfld.long 0x00 6. " TXEIC ,Clear transmit FIFO empty interrupt" "No effect,Cleared"
textline " "
bitfld.long 0x00 5. " RXFIC ,Clear receive FIFO full interrupt" "No effect,Cleared"
bitfld.long 0x00 4. " RXNEIC ,Clear receive FIFO not empty interrupt" "No effect,Cleared"
textline " "
bitfld.long 0x00 3. " TXIC ,Clear transmit FIFO interrupt" "No effect,Cleared"
bitfld.long 0x00 2. " RXIC ,Clear receive FIFO interrupt" "No effect,Cleared"
textline " "
bitfld.long 0x00 1. " RTIC ,Clear receive FIFO overrun interrupt" "No effect,Cleared"
bitfld.long 0x00 0. " RORIC ,Clear receive FIFO overrun interrupt" "No effect,Cleared"
sif (cpu()=="NETX51")
line.long 0x04 "SPI0_IRQ_CPU_SEL,SPI0 Interrupt CPU Select Register"
bitfld.long 0x04 1. " XPIC ,IRQ signal to xPIC enable" "Disabled,Enabled"
bitfld.long 0x04 0. " ARM ,IRQ signal to ARM enable" "Disabled,Enabled"
else
line.long 0x04 "SPI0_DMA_CTRL,SPI0 DMA Control Register"
bitfld.long 0x04 1. " RXDMAE ,Enable DMA for SPI-receive data" "Disabled,Enabled"
bitfld.long 0x04 0. " TXDMAE ,Enable DMA for SPI-transmit data" "Disabled,Enabled"
endif
sif (cpu()=="NETX51")
group.long 0x28++0x3
line.long 0x00 "SPI0_DMA_CTRL,SPI0 DMA Control Register"
bitfld.long 0x00 1. " TXDMAE ,Enable DMA for SPI-transmit data" "Disabled,Enabled"
bitfld.long 0x00 0. " RXDMAE ,Enable DMA for SPI-receive data" "Disabled,Enabled"
endif
width 22.
sif (cpu()=="NETX51")
rgroup.long 0x34++0x03
line.long 0x00 "SPI0_LGY_STAT,SPI0 Legacy Status Register"
bitfld.long 0x00 25. " SR_SELECTED ,External master has access to spi-interface" "Disabled,Enabled"
bitfld.long 0x00 24. " SR_OUT_FULL ,Output FIFO is full (no IRQ)" "Not Full,Full"
textline " "
bitfld.long 0x00 23. " SR_OUT_EMPTY ,Output FIFO is empty" "Not empty,Empty"
bitfld.long 0x00 22. " SR_OUT_FW ,ARM is writing data too fast into output FIFO" "Not too fast,Too fast"
textline " "
bitfld.long 0x00 21. " SR_OUT_FUEL ,Adjustable fuel value of output FIFO reached" "Not reached,Reached"
bitfld.long 0x00 20. " SR_IN_FULL ,Input FIFO is full" "Not Full,Full"
textline " "
bitfld.long 0x00 19. " SR_IN_RECDATA ,Valid data bytes in input FIFO" "Not valid,Valid"
bitfld.long 0x00 18. " SR_IN_FILL_LEVEL ,Adjustable fill level of input FIFO reached" "Not reached,Reached"
textline " "
hexmask.long.word 0x00 9.--17. 1. " SR_OUT_FILL_VAL ,Output FIFO fill value"
hexmask.long.word 0x00 0.--8. 1. " SR_IN_FILL_VAL ,Input FIFO fill value"
endif
group.long 0x30++0x0f
line.long 0x00 "SPI0_LGY_DATA,SPI0 Legacy Datal Register"
bitfld.long 0x00 16. " DR_VALID0 ,This bit shows if DATA_BYTE_0 is valid" "No valid,Valid"
hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE_0 ,Data byte 0"
sif (cpu()!="NETX51")
line.long 0x04 "SPI0_LGY_STAT,SPI0 Legacy Status Register"
bitfld.long 0x04 25. " SR_SELECTED ,External master has access to spi-interface" "Disabled,Enabled"
bitfld.long 0x04 24. " SR_OUT_FULL ,Output FIFO is full (no IRQ)" "Not Full,Full"
textline " "
bitfld.long 0x04 23. " SR_OUT_EMPTY ,Output FIFO is empty" "Not empty,Empty"
bitfld.long 0x04 22. " SR_OUT_FW ,ARM is writing data too fast into output FIFO" "Not too fast,Too fast"
textline " "
bitfld.long 0x04 21. " SR_OUT_FUEL ,Adjustable fuel value of output FIFO reached" "Not reached,Reached"
bitfld.long 0x04 20. " SR_IN_FULL ,Input FIFO is full" "Not Full,Full"
textline " "
bitfld.long 0x04 19. " SR_IN_RECDATA ,Valid data bytes in input FIFO" "Not valid,Valid"
bitfld.long 0x04 18. " SR_IN_FILL_LEVEL ,Adjustable fill level of input FIFO reached" "Not reached,Reached"
textline " "
hexmask.long.word 0x04 9.--17. 1. " SR_OUT_FILL_VAL ,Output FIFO fill value"
hexmask.long.word 0x04 0.--8. 1. " SR_IN_FILL_VAL ,Input FIFO fill value"
endif
line.long 0x08 "SPI0_LGY_CTRL,SPI0 Legacy Control Register"
bitfld.long 0x08 31. " CR_EN ,Enable SPI interface" "Disabled,Enabled"
bitfld.long 0x08 30. " CR_MS ,Mode" "Slave,Master"
textline " "
bitfld.long 0x08 29. " CR_CPOL ,Edge of spi sck polarity" "Rising,Falling"
bitfld.long 0x08 28. " CR_NCPHA ,Relative to CR_cpol" "Secondary,Primary"
textline " "
bitfld.long 0x08 21. " CR_CLR_OUTFIFO ,Clear output FIFO" "Not cleared,Cleared"
bitfld.long 0x08 20. " CR_CLR_INFIFO ,Clear input FIFO" "Not cleared,Cleared"
textline " "
bitfld.long 0x08 11. " CS_MODE ,Chip select mode" "Directly,Automatically"
bitfld.long 0x08 8.--10. " CR_SS ,External slave select" "0,1,2,3,4,5,6,7"
textline " "
sif (cpu()=="NETX51")
bitfld.long 0x08 1.--4. " CR_SPEED ,SPI Clock Speed" "0.025 MHz,0.05 MHz,0.1 MHz,0.2 MHz,0.5 MHz,1 MHz,1.25 MHz,2 MHz,2.5 MHz,3.3333 MHz,5 MHz,10 MHz,12.5 MHz,16.6666 MHz,25 MHz,50 MHz"
else
bitfld.long 0x08 1.--4. " CR_SPEED ,SPI Clock Speed" "0.195 MHz,0.195 MHz,0.2 MHz,0.5 MHz,1 MHz,1.25 MHz,2 MHz,2.5 MHz,3.3333 MHz,5 MHz,10 MHz,12.5 MHz,16.6666 MHz,25 MHz,50 MHz,?..."
endif
bitfld.long 0x08 0. " CR_SOFTRESET ,Clears IRQs and FIFOs" "Not cleared,Cleared"
line.long 0x0c "SPI0_LGY_INT_CTRL,SPI0 Legacy Interrupt Control Register"
bitfld.long 0x0c 23. " IR_OUT_EMPTY_EN ,IRQ enable for output FIFO is empty" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 21. " IR_OUT_FUEL_EN ,IRQ enable for adjustable fuel value of output FIFO reached" "Disabled,Enabled"
bitfld.long 0x0c 20. " IR_IN_FULL_EN ,IRQ enable for input FIFO is full" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 19. " IR_IN_RECDATA_EN ,IRQ enable for valid data bytes in input FIFO" "Disabled,Enabled"
bitfld.long 0x0c 18. " IR_IN_FUEL_EN ,IRQ enable for adjustable fill level of input FIFO reached" "Disabled,Enabled"
textline " "
hexmask.long.word 0x0c 9.--17. 1. " IR_OUT_FUEL ,Watermark level for output FIFO"
hexmask.long.word 0x0c 0.--8. 1. " IR_IN_FUEL ,Watermark level for input FIFO"
width 0x0b
tree.end
tree "SPI1"
base asd:0x1c000d40
width 13.
group.long 0x00++0x3
line.long 0x00 "SPI1_CTRL0,SPI1 control register 0"
bitfld.long 0x00 28. " SLAVE_SIG_EARLY ,Generate MISO in slavemode" "Not generated,Generated"
bitfld.long 0x00 31. " NETX100_COMP ,Use netx100/500-compatible SPI mode" "Start transfer after writing data,Start transfer after setting CR_write or CR_read"
textline " "
bitfld.long 0x00 27. " FILTER_IN ,Receive-data is sampled every 10ns" "Not sampled,Sampled"
bitfld.long 0x00 24.--25. " FORMAT ,Frame format" "MOTOROLA SPI format,?..."
textline " "
hexmask.long.word 0x00 8.--19. 1. " SCK_MULADD ,Serial clock rate multiply add value"
bitfld.long 0x00 7. " SPH ,Serial clock phase" "Sample data at first clock edge edge,Sample data at second clock edge edge"
textline " "
bitfld.long 0x00 6. " SPO ,Serial clock polarity" "Idle: clock is low; first edge is rising,Idle: clock is high; first edge is falling"
textline " "
bitfld.long 0x00 0.--3. " DSS ,Data size select" "Reserved,Reserved,Reserved,4Bit,5Bit,6Bit,7Bit,8Bit,9Bit,10Bit,11Bit,12Bit,13Bit,14Bit,15Bit,16Bit"
group.long 0x04++0x3
line.long 0x00 "SPI1_CTRL1,SPI1 control register 1"
bitfld.long 0x00 28. " RX_FIFO_CLR ,Clear the receive-FIFOs" "Normal operation,Clear FIFO"
bitfld.long 0x00 24.--27. " RX_FIFO_WM ,Receive FIFO watermark for IRQ-generation" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
textline " "
bitfld.long 0x00 20. " TX_FIFO_CLR ,Clear the transmit-FIFOs" "Normal operation,Clear FIFO"
bitfld.long 0x00 16.--19. " TX_FIFO_WM ,Transmit FIFO watermark for IRQ-generation" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
textline " "
bitfld.long 0x00 11. " FSS_STATIC ,SPI static chip select" "CS auto-assert,CS manual via FSS"
bitfld.long 0x00 10. " FSS_SLV2 ,Frame or slave select" "0,1"
textline " "
bitfld.long 0x00 9. " FSS_SLV1 ,Frame or slave select" "0,1"
bitfld.long 0x00 8. " FSS_SLV0 ,Frame or slave select" "0,1"
textline " "
bitfld.long 0x00 3. " SOD ,Slave mode output disable" "No,Yes"
bitfld.long 0x00 2. " MS ,Mode select" "Master,Slave"
textline " "
bitfld.long 0x00 1. " SSE ,SPI enable" "Disabled,Enabled"
bitfld.long 0x00 0. " LBM ,Loop back mode" "Normal operation,Loopback mode"
hgroup.long 0x08++0x3
hide.long 0x00 "SPI1_DATA,SPI1 data register"
in
width 22.
rgroup.long 0x0C++0x3
line.long 0x00 "SPI1_STATUS,SPI1 status register"
bitfld.long 0x00 31. " RX_FIFO_ERR_UNDR ,Receive FIFO under-run error occurred" "No error,Error"
textline " "
bitfld.long 0x00 30. " RX_FIFO_ERR_OVFL ,Receive FIFO overflow error occurred" "No error,Error"
bitfld.long 0x00 24.--28. " RX_FIFO_LEVEL ,Receive FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 23. " TX_FIFO_ERR_UNDR ,Transmit FIFO under-run error occurred" "No error,Error"
bitfld.long 0x00 22. " TX_FIFO_ERR_OVFL ,Transmit FIFO overflow error occurred" "No error,Error"
textline " "
bitfld.long 0x00 16.--20. " TX_FIFO_LEVEL ,Transmit FIFO level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4. " BSY ,Device busy" "Not busy,Busy"
textline " "
sif (cpuis("NETX51"))
bitfld.long 0x00 3. " RFF ,Receive FIFO is full" "Not Full,Full"
else
bitfld.long 0x00 3. " RFF ,Receive FIFO is full" "Full,Not Full"
endif
bitfld.long 0x00 2. " RNE ,Receive FIFO is not empty" "Empty,Not empty"
textline " "
bitfld.long 0x00 1. " TNF ,Transmit FIFO is not full" "Full,Not Full"
bitfld.long 0x00 0. " TFE ,Transmit FIFO is empty" "Not empty,Empty"
width 22.
group.long 0x10++0x3
line.long 0x00 "SPI1_CLK_PRE_SCL,SPI1 Clock Prescale Register"
hexmask.long.byte 0x00 0.--7. 1. " CPSDVSR ,Obsolete"
group.long 0x14++0x3
line.long 0x00 "SPI1_INT_MSK_SET_CLR,SPI1 Interrupt Mask Set or Clear"
bitfld.long 0x00 6. " TXEIM ,Transmit FIFO empty interrupt mask" "Not masked,Masked"
textline " "
bitfld.long 0x00 5. " RXFIM ,Receive FIFO full interrupt mask" "Not masked,Masked"
bitfld.long 0x00 4. " RXNEIM ,Transmit FIFO interrupt mask" "Not masked,Masked"
textline " "
bitfld.long 0x00 3. " TXIM ,Transmit FIFO interrupt mask" "Not masked,Masked"
bitfld.long 0x00 2. " RXIM ,Receive FIFO interrupt mask" "Not masked,Masked"
textline " "
bitfld.long 0x00 1. " RTIM ,Receive timeout interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. " RORIM ,Receive FIFO overrun interrupt mask" "Not masked,Masked"
rgroup.long 0x18++0x3
line.long 0x00 "SPI1_RAW_INT_STAT,SPI1 raw Interrupt status"
bitfld.long 0x00 6. " TXERIS ,Unmasked transmit FIFO empty interrupt state" "Not empty,Empty"
textline " "
bitfld.long 0x00 5. " RXFRIS ,Unmasked receive FIFO full interrupt state" "Not full,Full"
bitfld.long 0x00 4. " RXNERIS ,Unmasked receive FIFO not empty interrupt state" "Empty,Not empty"
textline " "
bitfld.long 0x00 3. " TXRIS ,Unmasked transmit FIFO interrupt state" "> = spi_ctrl1.tx_fifo_wm,< spi_ctrl1.tx_fifo_wm"
textline " "
bitfld.long 0x00 2. " RXRIS ,Unmasked receive FIFO interrupt state" "< = spi_ctrl1.rx_fifo_wm,> spi_ctrl1.rx_fifo_wm"
textline " "
bitfld.long 0x00 1. " RTRIS ,Unmasked receive timeout interrupt state" "Empty,Not empty"
bitfld.long 0x00 0. " RORRIS ,Unmasked receive FIFO overrun interrupt state" "No error,Error"
rgroup.long 0x1C++0x3
line.long 0x00 "SPI1_MSK_INT_STAT,SPI1 Mask Interrupt Status Register"
bitfld.long 0x00 6. " TXEMIS ,Masked transmit FIFO empty interrupt state" "No Interrupt,Interrupt"
textline " "
bitfld.long 0x00 5. " RXFMIS ,Masked receive FIFO full interrupt state" "No Interrupt,Interrupt"
bitfld.long 0x00 4. " RXNEMIS ,Masked receive FIFO not empty interrupt state" "No Interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " TXMIS ,Masked transmit FIFO interrupt state" "No Interrupt,Interrupt"
bitfld.long 0x00 2. " RXMIS ,Masked receive FIFO interrupt state" "No Interrupt,Interrupt"
textline " "
bitfld.long 0x00 1. " RTMIS ,Masked receive timeout interrupt state" "No Interrupt,Interrupt"
bitfld.long 0x00 0. " RORMIS ,Masked receive FIFO overrun interrupt state" "No Interrupt,Interrupt"
group.long 0x20++0x7
line.long 0x00 "SPI1_INT_CLR,SPI1 Interrupt Clear Register"
bitfld.long 0x00 6. " TXEIC ,Clear transmit FIFO empty interrupt" "No effect,Cleared"
textline " "
bitfld.long 0x00 5. " RXFIC ,Clear receive FIFO full interrupt" "No effect,Cleared"
bitfld.long 0x00 4. " RXNEIC ,Clear receive FIFO not empty interrupt" "No effect,Cleared"
textline " "
bitfld.long 0x00 3. " TXIC ,Clear transmit FIFO interrupt" "No effect,Cleared"
bitfld.long 0x00 2. " RXIC ,Clear receive FIFO interrupt" "No effect,Cleared"
textline " "
bitfld.long 0x00 1. " RTIC ,Clear receive FIFO overrun interrupt" "No effect,Cleared"
bitfld.long 0x00 0. " RORIC ,Clear receive FIFO overrun interrupt" "No effect,Cleared"
sif (cpu()=="NETX51")
line.long 0x04 "SPI1_IRQ_CPU_SEL,SPI1 Interrupt CPU Select Register"
bitfld.long 0x04 1. " XPIC ,IRQ signal to xPIC enable" "Disabled,Enabled"
bitfld.long 0x04 0. " ARM ,IRQ signal to ARM enable" "Disabled,Enabled"
else
line.long 0x04 "SPI1_DMA_CTRL,SPI1 DMA Control Register"
bitfld.long 0x04 1. " RXDMAE ,Enable DMA for SPI-receive data" "Disabled,Enabled"
bitfld.long 0x04 0. " TXDMAE ,Enable DMA for SPI-transmit data" "Disabled,Enabled"
endif
sif (cpu()=="NETX51")
group.long 0x28++0x3
line.long 0x00 "SPI1_DMA_CTRL,SPI1 DMA Control Register"
bitfld.long 0x00 1. " TXDMAE ,Enable DMA for SPI-transmit data" "Disabled,Enabled"
bitfld.long 0x00 0. " RXDMAE ,Enable DMA for SPI-receive data" "Disabled,Enabled"
endif
width 22.
sif (cpu()=="NETX51")
rgroup.long 0x34++0x03
line.long 0x00 "SPI1_LGY_STAT,SPI1 Legacy Status Register"
bitfld.long 0x00 25. " SR_SELECTED ,External master has access to spi-interface" "Disabled,Enabled"
bitfld.long 0x00 24. " SR_OUT_FULL ,Output FIFO is full (no IRQ)" "Not Full,Full"
textline " "
bitfld.long 0x00 23. " SR_OUT_EMPTY ,Output FIFO is empty" "Not empty,Empty"
bitfld.long 0x00 22. " SR_OUT_FW ,ARM is writing data too fast into output FIFO" "Not too fast,Too fast"
textline " "
bitfld.long 0x00 21. " SR_OUT_FUEL ,Adjustable fuel value of output FIFO reached" "Not reached,Reached"
bitfld.long 0x00 20. " SR_IN_FULL ,Input FIFO is full" "Not Full,Full"
textline " "
bitfld.long 0x00 19. " SR_IN_RECDATA ,Valid data bytes in input FIFO" "Not valid,Valid"
bitfld.long 0x00 18. " SR_IN_FILL_LEVEL ,Adjustable fill level of input FIFO reached" "Not reached,Reached"
textline " "
hexmask.long.word 0x00 9.--17. 1. " SR_OUT_FILL_VAL ,Output FIFO fill value"
hexmask.long.word 0x00 0.--8. 1. " SR_IN_FILL_VAL ,Input FIFO fill value"
endif
group.long 0x30++0x0f
line.long 0x00 "SPI1_LGY_DATA,SPI1 Legacy Datal Register"
bitfld.long 0x00 16. " DR_VALID0 ,This bit shows if DATA_BYTE_0 is valid" "No valid,Valid"
hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE_0 ,Data byte 0"
sif (cpu()!="NETX51")
line.long 0x04 "SPI1_LGY_STAT,SPI1 Legacy Status Register"
bitfld.long 0x04 25. " SR_SELECTED ,External master has access to spi-interface" "Disabled,Enabled"
bitfld.long 0x04 24. " SR_OUT_FULL ,Output FIFO is full (no IRQ)" "Not Full,Full"
textline " "
bitfld.long 0x04 23. " SR_OUT_EMPTY ,Output FIFO is empty" "Not empty,Empty"
bitfld.long 0x04 22. " SR_OUT_FW ,ARM is writing data too fast into output FIFO" "Not too fast,Too fast"
textline " "
bitfld.long 0x04 21. " SR_OUT_FUEL ,Adjustable fuel value of output FIFO reached" "Not reached,Reached"
bitfld.long 0x04 20. " SR_IN_FULL ,Input FIFO is full" "Not Full,Full"
textline " "
bitfld.long 0x04 19. " SR_IN_RECDATA ,Valid data bytes in input FIFO" "Not valid,Valid"
bitfld.long 0x04 18. " SR_IN_FILL_LEVEL ,Adjustable fill level of input FIFO reached" "Not reached,Reached"
textline " "
hexmask.long.word 0x04 9.--17. 1. " SR_OUT_FILL_VAL ,Output FIFO fill value"
hexmask.long.word 0x04 0.--8. 1. " SR_IN_FILL_VAL ,Input FIFO fill value"
endif
line.long 0x08 "SPI1_LGY_CTRL,SPI1 Legacy Control Register"
bitfld.long 0x08 31. " CR_EN ,Enable SPI interface" "Disabled,Enabled"
bitfld.long 0x08 30. " CR_MS ,Mode" "Slave,Master"
textline " "
bitfld.long 0x08 29. " CR_CPOL ,Edge of spi sck polarity" "Rising,Falling"
bitfld.long 0x08 28. " CR_NCPHA ,Relative to CR_cpol" "Secondary,Primary"
textline " "
bitfld.long 0x08 21. " CR_CLR_OUTFIFO ,Clear output FIFO" "Not cleared,Cleared"
bitfld.long 0x08 20. " CR_CLR_INFIFO ,Clear input FIFO" "Not cleared,Cleared"
textline " "
bitfld.long 0x08 11. " CS_MODE ,Chip select mode" "Directly,Automatically"
bitfld.long 0x08 8.--10. " CR_SS ,External slave select" "0,1,2,3,4,5,6,7"
textline " "
sif (cpu()=="NETX51")
bitfld.long 0x08 1.--4. " CR_SPEED ,SPI Clock Speed" "0.025 MHz,0.05 MHz,0.1 MHz,0.2 MHz,0.5 MHz,1 MHz,1.25 MHz,2 MHz,2.5 MHz,3.3333 MHz,5 MHz,10 MHz,12.5 MHz,16.6666 MHz,25 MHz,50 MHz"
else
bitfld.long 0x08 1.--4. " CR_SPEED ,SPI Clock Speed" "0.195 MHz,0.195 MHz,0.2 MHz,0.5 MHz,1 MHz,1.25 MHz,2 MHz,2.5 MHz,3.3333 MHz,5 MHz,10 MHz,12.5 MHz,16.6666 MHz,25 MHz,50 MHz,?..."
endif
bitfld.long 0x08 0. " CR_SOFTRESET ,Clears IRQs and FIFOs" "Not cleared,Cleared"
line.long 0x0c "SPI1_LGY_INT_CTRL,SPI1 Legacy Interrupt Control Register"
bitfld.long 0x0c 23. " IR_OUT_EMPTY_EN ,IRQ enable for output FIFO is empty" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 21. " IR_OUT_FUEL_EN ,IRQ enable for adjustable fuel value of output FIFO reached" "Disabled,Enabled"
bitfld.long 0x0c 20. " IR_IN_FULL_EN ,IRQ enable for input FIFO is full" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 19. " IR_IN_RECDATA_EN ,IRQ enable for valid data bytes in input FIFO" "Disabled,Enabled"
bitfld.long 0x0c 18. " IR_IN_FUEL_EN ,IRQ enable for adjustable fill level of input FIFO reached" "Disabled,Enabled"
textline " "
hexmask.long.word 0x0c 9.--17. 1. " IR_OUT_FUEL ,Watermark level for output FIFO"
hexmask.long.word 0x0c 0.--8. 1. " IR_IN_FUEL ,Watermark level for input FIFO"
width 0x0b
tree.end
tree.end
tree "Serial I2C-Interface (I2C)"
base asd:0x1c000e00
width 20.
group.long 0x00++0x3
line.long 0x00 "I2C_MASTER_CTRL,I2C Master Control Register"
sif (cpu()=="NETX51")
bitfld.long 0x00 17. " RST_I2C ,Reset detected I2C bus states" "No reset,Reset"
textline " "
bitfld.long 0x00 16. " PIO_MODE ,Pio mode" "Disabled,Enabled"
endif
hexmask.long.byte 0x00 4.--10. 0x1 " SADR ,Slave device ID"
textline " "
bitfld.long 0x00 1.--3. " MODE ,I2C-speed-mode" "50kb/s,100kb/s,200kb/s,400kb/s,800kb/s,1.2Mb/s,1.7Mb/s,3.4Mb/s"
bitfld.long 0x00 0. " EN_I2C ,Interface enable" "Disabled,Enabled"
if (((d.l(asd:0x1c000e00+0x04))&0x400)==0x400)
group.long 0x04++0x3
line.long 0x00 "I2C_SLAVE_CTRL,I2C Slave Control Register"
sif (cpu()=="NETX51")
bitfld.long 0x00 20. " ARES_AC_START ,Auto reset ac_start" "Disabled,Enabled"
endif
bitfld.long 0x00 18. " AC_GCALL ,General Call acknowledge" "Generate ACK on generic call,Suppress ACK on generic call"
textline " "
bitfld.long 0x00 17. " AC_START ,Enable start sequence acknowledge" "Generate ACK on start seq,Suppress ACK on start seq"
textline " "
bitfld.long 0x00 16. " AC_SRX ,Enable slave-receive-data acknowledge" "Generate ACK on RX bytes,Suppress ACK on RX bytes"
textline " "
bitfld.long 0x00 10. " SID10 ,10-bit Slave device ID" "7 Bit Slave ID,10Bit Slave ID"
hexmask.long.word 0x00 0.--9. 0x1 " SID ,Slave device ID"
else
group.long 0x04++0x3
line.long 0x00 "I2C_SLAVE_CTRL,I2C Slave Control Register"
sif (cpu()=="NETX51")
bitfld.long 0x00 20. " ARES_AC_START ,Auto reset ac_start" "Disabled,Enabled"
endif
bitfld.long 0x00 18. " AC_GCALL ,General Call acknowledge" "Generate ACK on generic call,Suppress ACK on generic call"
textline " "
bitfld.long 0x00 17. " AC_START ,Enable start sequence acknowledge" "Generate ACK on start seq,Suppress ACK on start seq"
textline " "
bitfld.long 0x00 16. " AC_SRX ,Enable slave-receive-data acknowledge" "Generate ACK on RX bytes,Suppress ACK on RX bytes"
textline " "
bitfld.long 0x00 10. " SID10 ,10-bit Slave device ID" "7 Bit Slave ID,10Bit Slave ID"
hexmask.long.byte 0x00 0.--6. 0x1 " SID ,Slave device ID"
endif
group.long 0x08++0x3
line.long 0x00 "I2C_MASTER_CMD,I2C Command Register"
hexmask.long.byte 0x00 20.--27. 0x1 " ACPOLLMAX ,Maximum tries for ACK polling"
hexmask.long.word 0x00 8.--17. 0x1 " TSIZE ,Transfer Size"
textline " "
bitfld.long 0x00 1.--3. " CMD ,I2C sequence command" "START,S_AC,S_AC_T,S_AC_TC,CT,CTC,STOP,IDLE"
bitfld.long 0x00 0. " NWR ,Transfer direction" "Write,Read"
hgroup.long 0x0C++0x3
hide.long 0x00 "I2C_MASTER_DATA,Master data register"
in
hgroup.long 0x10++0x3
hide.long 0x00 "I2C_SLAVE_DATA,Slave data register"
in
group.long 0x14++0x3
line.long 0x00 "I2C_MFIFO_CTRL,I2C Master FIFO control register"
bitfld.long 0x00 8. " MFIFO_CLR ,Clear master data FIFO" "No effect,Clear"
bitfld.long 0x00 0.--3. " MFIFO_WM ,Master FIFO IRQ Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x18++0x3
line.long 0x00 "I2C_SFIFO_CTRL,I2C Slave FIFO control register"
bitfld.long 0x00 8. " SFIFO_CLR ,Clear slave data FIFO" "No effect,Clear"
textline " "
bitfld.long 0x00 0.--3. " SFIFO_WM ,Slave FIFO IRQ Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
sif (cpuis("NETX51"))
rgroup.long 0x1c++0x03
else
group.long 0x1C++0x3
endif
line.long 0x00 "I2C_STAT,I2C status register"
bitfld.long 0x00 31. " SDA_STATE ,SDA signal state sampled and filtered from bus" "Not detected,Detected"
bitfld.long 0x00 30. " SCL_STATE ,SCL signal state sampled and filtered from bus" "Not detected,Detected"
textline " "
bitfld.long 0x00 27. " SID10_ACED ,Master detected that a 10-bit addressed slave acknowledge" "Not acknowledged,Acknowledged"
textline " "
bitfld.long 0x00 26. " GCALL_ACED ,Received General Call was acknowledged" "Not acknowledged,Acknowledged"
textline " "
bitfld.long 0x00 25. " NWR_ACED ,Last transfer direction" "Write,Read"
bitfld.long 0x00 24. " LAST_AC ,Last acknowledge detected on bus" "Not detected,Detected"
textline " "
bitfld.long 0x00 23. " SLV_ACCESS ,Slave access" "No accessed,Accessed"
bitfld.long 0x00 22. " STARTED ,START condition detection" "Stopped,Started"
textline " "
bitfld.long 0x00 21. " NWR ,Transfer direction detected after last (s)START" "Write,Read"
bitfld.long 0x00 20. " BUS_MASTER ,Bus arbitration" "Not gained,Gained"
textline " "
bitfld.long 0x00 19. " SFIFO_ERR_UNDR ,Slave FIFO underrun error occurred" "No error,Error"
bitfld.long 0x00 18. " SFIFO_ERR_OVFL ,Slave FIFO overflow error occurred" "No error,Error"
textline " "
bitfld.long 0x00 17. " SFIFO_FULL ,Slave FIFO is full" "Not full,Full"
bitfld.long 0x00 16. " SFIFO_EMPTY ,Slave FIFO is empty" "Not empty,Empty"
textline " "
bitfld.long 0x00 10.--14. " SFIFO_LEVEL ,Slave FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,12,13,14,15,16,?..."
textline " "
bitfld.long 0x00 9. " MFIFO_ERR_UNDR ,Master FIFO underrun error occurred" "No error,Error"
bitfld.long 0x00 8. " MFIFO_ERR_OVFL ,Master FIFO overflow error occurred" "No error,Error"
textline " "
bitfld.long 0x00 7. " MFIFO_FULL ,Master FIFO is full" "Not full,Full"
bitfld.long 0x00 6. " MFIFO_EMPTY ,Master FIFO is empty" "Not empty,Empty"
textline " "
bitfld.long 0x00 0.--4. " MFIFO_LEVEL ,Master FIFO fill level" "0,1,2,3,4,5,6,7,8,9,10,12,13,14,15,16,?..."
group.long 0x20++0x3
line.long 0x00 "I2C_INT_MSK_SET_CLR,I2C Interrupt Mask Set or Clear Register "
bitfld.long 0x00 6. " SREQ ,Slave request interrupt mask" "Not masked,Masked"
textline " "
bitfld.long 0x00 5. " SFIFO_REQ ,Slave FIFO action request interrupt mask" "Not masked,Masked"
bitfld.long 0x00 4. " MFIFO_REQ ,Master FIFO action request interrupt mask" "Not masked,Masked"
textline " "
bitfld.long 0x00 3. " BUS_BUSY ,External I2C-bus is busy interrupt mask" "Not masked,Masked"
bitfld.long 0x00 2. " FIFO_ERR ,FIFO error interrupt mask" "Not masked,Masked"
textline " "
bitfld.long 0x00 1. " CMD_ERR ,Command error interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. " CMD_OK ,Command OK interrupt mask" "Not masked,Masked"
group.long 0x24++0x3
line.long 0x00 "I2C_INT_MSK_SET_CLR,I2C Interrupt Mask Set or Clear Register "
bitfld.long 0x00 6. " SREQ ,Unmasked slave request interrupt state" "Not requested,Requested"
textline " "
bitfld.long 0x00 5. " SFIFO_REQ ,Unmasked slave FIFO action request interrupt state" "Not requested,Requested"
bitfld.long 0x00 4. " MFIFO_REQ ,Unmasked master FIFO action request interrupt state" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " BUS_BUSY ,Unmasked external I2C-bus is busy interrupt state" "Not busy,Busy"
bitfld.long 0x00 2. " FIFO_ERR ,Unmasked FIFO error interrupt state" "Not error,Error"
textline " "
bitfld.long 0x00 1. " CMD_ERR ,Unmasked command error interrupt state" "Not error,Error"
bitfld.long 0x00 0. " CMD_OK ,Unmasked command OK interrupt state" "Not finished,Finished"
rgroup.long 0x28++0x3
line.long 0x00 "I2C_MSK_INT_STAT,I2C Mask Interrupt Status Register "
sif (cpu()=="NETX51")
bitfld.long 0x00 6. " SREQ ,Masked slave request interrupt state" "Not masked,Masked"
bitfld.long 0x00 5. " SFIFO_REQ ,Masked slave FIFO action request interrupt state" "Not masked,Masked"
textline " "
bitfld.long 0x00 4. " MFIFO_REQ ,Masked master FIFO action request interrupt state" "Not masked,Masked"
bitfld.long 0x00 3. " BUS_BUSY ,Masked external I2C-bus is busy interrupt state" "Not masked,Masked"
textline " "
bitfld.long 0x00 2. " FIFO_ERR ,Masked FIFO error interrupt state" "Not masked,Masked"
bitfld.long 0x00 1. " CMD_ERR ,Masked command error interrupt state" "Not masked,Masked"
textline " "
bitfld.long 0x00 0. " CMD_OK ,Masked command OK interrupt state" "Not masked,Masked"
else
eventfld.long 0x00 6. " SREQ ,Masked slave request interrupt state" "Not masked,Masked"
textline " "
eventfld.long 0x00 5. " SFIFO_REQ ,Masked slave FIFO action request interrupt state" "Not masked,Masked"
eventfld.long 0x00 4. " MFIFO_REQ ,Masked master FIFO action request interrupt state" "Not masked,Masked"
textline " "
eventfld.long 0x00 3. " BUS_BUSY ,Masked external I2C-bus is busy interrupt state" "Not masked,Masked"
eventfld.long 0x00 2. " FIFO_ERR ,Masked FIFO error interrupt state" "Not masked,Masked"
textline " "
eventfld.long 0x00 1. " CMD_ERR ,Masked command error interrupt state" "Not masked,Masked"
eventfld.long 0x00 0. " CMD_OK ,Masked command OK interrupt state" "Not masked,Masked"
endif
group.long 0x2C++0x3
line.long 0x00 "I2C_DMA_CTRL,I2C DMA control register"
sif (cpu()=="NETX51")
bitfld.long 0x00 3. " SDMAB_EN ,Enable DMA burst requests for I2C slave data" "Disabled,Enabled"
bitfld.long 0x00 2. " SDMAS_EN ,Enable DMA single requests for I2C slave data" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " MDMAB_EN ,Enable DMA burst requests for I2C master data" "Disabled,Enabled"
bitfld.long 0x00 0. " MDMAS_EN ,Enable DMA single requests for I2C master data" "Disabled,Enabled"
else
bitfld.long 0x00 3. " MDMAS_EN ,Enable DMA single requests for I2C master data" "Disabled,Enabled"
bitfld.long 0x00 2. " MDMAB_EN ,Enable DMA burst requests for I2C master data" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " SDMAS_EN ,Enable DMA single requests for I2C slave data" "Disabled,Enabled"
bitfld.long 0x00 0. " SDMAB_EN ,Enable DMA burst requests for I2C slave data" "Disabled,Enabled"
endif
sif (cpu()=="NETX51")
group.long 0x30++0x3
line.long 0x00 "I2C_PIO,Direct I2C IO Access Controlling"
bitfld.long 0x00 6. " SDA_IN_RO ,SDA input state" "0,1"
bitfld.long 0x00 5. " SDA_OE ,SDA output enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " SDA_OUT ,Driving level" "Low,High"
bitfld.long 0x00 2. " SCL_IN_RO ,SCL input state" "0,1"
textline " "
bitfld.long 0x00 1. " SCL_OE ,SCL output enable" "Disabled,Enabled"
bitfld.long 0x00 0. " SCL_OUT ,Driving level" "Low,High"
endif
width 0x0b
tree.end
tree "CCD Controller (CCDC)"
base asd:0x1c000f00
width 12.
group.long 0x00++0x3
line.long 0x00 "CCDC_CFG,CCDC Config Register"
bitfld.long 0x00 28. " LAST_MODE ,?..." "0,1"
bitfld.long 0x00 27. " FIFO_2_NXT ,value in fifo" "0,1"
textline " "
bitfld.long 0x00 26. " FIFO_2_UNFL ,Underflow" "No underflow,Underflow"
bitfld.long 0x00 25. " FIFO_2_OVFL ,Overflow" "No overflow,Overflow"
textline " "
bitfld.long 0x00 24. " FIFO_2_RES ,Reset mode" "No reset,Reset"
bitfld.long 0x00 23. " FIFO_1_NXT ,value in fifo" "0,1"
textline " "
bitfld.long 0x00 22. " FIFO_1_UNFL ,Underflow" "No underflow,Underflow"
bitfld.long 0x00 21. " FIFO_1_OVFL ,Overflow" "No overflow,Overflow"
textline " "
bitfld.long 0x00 20. " FIFO_1_RES ,Overflow" "No reset,Reset"
bitfld.long 0x00 19. " FIFO_0_NXT ,value in fifo" "0,1"
textline " "
bitfld.long 0x00 18. " FIFO_0_UNFL ,Underflow" "No underflow,Underflow"
bitfld.long 0x00 17. " FIFO_0_OVFL ,Overflow" "No overflow,Overflow"
textline " "
bitfld.long 0x00 16. " FIFO_0_RES ,Reset" "No reset,Reset"
bitfld.long 0x00 12.--15. " SAMPLE_TIME ,Sample time - 100Mhz clocks after pos/negedge" "With edge,After edge,After edge,After edge,After edge,After edge,After edge,After edge,After edge,After edge,After edge,After edge,After edge,After edge,After edge,Before edge"
textline " "
hexmask.long.byte 0x00 4.--11. 1. " BRIGHT_STEP ,Bright_step"
bitfld.long 0x00 1. " EDGE_MODE ,Edge mode" "Posedge,Negedge"
textline " "
bitfld.long 0x00 0. " ENABLE ,Enable CCD - Controller" "Disabled,Enabled"
width 22.
group.long 0x04++0x7
line.long 0x00 "CCDC_HORIZ_START_STOP,CCDC Horizontal Start/Stop Values"
hexmask.long.word 0x00 16.--31. 1. " HORIZ_STOP ,Byte count stop to cut picture"
hexmask.long.word 0x00 0.--15. 1. " HORIZ_START ,Byte count start to cut picture"
line.long 0x04 "CCDC_VERT_START_STOP,CCDC Vertical Start/Stop Values"
hexmask.long.word 0x04 16.--31. 1. " VERTI_STOP ,Line count stop to cut picture"
hexmask.long.word 0x04 0.--15. 1. " VERTI_START ,Line count start to cut picture"
rgroup.long 0x0c++0x13
line.long 0x00 "CCDC_HORIZ_VERT_CNTR,CCDC Horizontal/Vertical Counter"
hexmask.long.word 0x00 16.--31. 1. " VERTI_COUNTER ,Line count while frame valid"
hexmask.long.word 0x00 0.--15. 1. " HORIZ_COUNTER ,Byte count while line_valid"
line.long 0x04 "CCDC_BRIGHT,CCDC Brightness Counter"
line.long 0x08 "CCDC_FIFO0,CCDC FIFO 0"
line.long 0x0c "CCDC_FIFO1,CCDC FIFO 1"
line.long 0x10 "CCDC_FIFO2,CCDC FIFO 2"
width 22.
group.long 0x20++0x0b
line.long 0x00 "CCDC_BYTE0_POS,CCDC Byte 0 Position Register"
bitfld.long 0x00 31. " FIFO_0_AND_MASK[7:0] ,AND mask bit 7" "0,1"
bitfld.long 0x00 30. ",AND mask bit 6" "0,1"
bitfld.long 0x00 29. ",AND mask bit 5" "0,1"
bitfld.long 0x00 28. ",AND mask bit 4" "0,1"
bitfld.long 0x00 27. ",AND mask bit 3" "0,1"
bitfld.long 0x00 26. ",AND mask bit 2" "0,1"
bitfld.long 0x00 25. ",AND mask bit 1" "0,1"
bitfld.long 0x00 24. ",AND mask bit 0" "0,1"
textline " "
bitfld.long 0x00 23. " FOURTH_0_BYTE_ENABLE ,Enable byte selection" "Enabled,Disabled"
bitfld.long 0x00 18.--22. " FOURTH_0_BYTE_START ,Fourth byte start position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 17. " THIRD_0_BYTE_ENABLE ,Enable byte selection" "Disabled,Enabled"
bitfld.long 0x00 12.--16. " THIRD_0_BYTE_START ,Third byte start position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 11. " SECOND_0_BYTE_ENABLE ,Enable byte selection" "Disabled,Enabled"
bitfld.long 0x00 6.--10. " SECOND_0_BYTE_START ,Second byte start position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 5. " FIRST_0_BYTE_ENABLE ,Enable byte selection" "Disabled,Enabled"
bitfld.long 0x00 0.--4. " FIRST_0_BYTE_START ,First byte start position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "CCDC_BYTE1_POS,CCDC Byte 1 Position Register"
bitfld.long 0x04 31. " FIFO_1_AND_MASK[7:0] ,AND mask bit 7" "0,1"
bitfld.long 0x00 30. ",AND mask bit 6" "0,1"
bitfld.long 0x00 29. ",AND mask bit 5" "0,1"
bitfld.long 0x00 28. ",AND mask bit 4" "0,1"
bitfld.long 0x00 27. ",AND mask bit 3" "0,1"
bitfld.long 0x00 26. ",AND mask bit 2" "0,1"
bitfld.long 0x00 25. ",AND mask bit 1" "0,1"
bitfld.long 0x00 24. ",AND mask bit 0" "0,1"
textline " "
bitfld.long 0x04 23. " FOURTH_1_BYTE_ENABLE ,Enable byte selection" "Enabled,Disabled"
bitfld.long 0x04 18.--22. " FOURTH_1_BYTE_START ,Fourth byte start position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x04 17. " THIRD_1_BYTE_ENABLE ,Enable byte selection" "Disabled,Enabled"
bitfld.long 0x04 12.--16. " THIRD_1_BYTE_START ,Third byte start position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x04 11. " SECOND_1_BYTE_ENABLE ,Enable byte selection" "Disabled,Enabled"
bitfld.long 0x04 6.--10. " SECOND_1_BYTE_START ,Second byte start position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x04 5. " FIRST_1_BYTE_ENABLE ,Enable byte selection" "Disabled,Enabled"
bitfld.long 0x04 0.--4. " FIRST_1_BYTE_START ,First byte start position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "CCDC_BYTE2_POS,CCDC Byte 2 Position Register"
bitfld.long 0x08 31. " FIFO_2_AND_MASK[7:0] ,AND mask bit 7" "0,1"
bitfld.long 0x00 30. ",AND mask bit 6" "0,1"
bitfld.long 0x00 29. ",AND mask bit 5" "0,1"
bitfld.long 0x00 28. ",AND mask bit 4" "0,1"
bitfld.long 0x00 27. ",AND mask bit 3" "0,1"
bitfld.long 0x00 26. ",AND mask bit 2" "0,1"
bitfld.long 0x00 25. ",AND mask bit 1" "0,1"
bitfld.long 0x00 24. ",AND mask bit 0" "0,1"
textline " "
bitfld.long 0x08 23. " FOURTH_2_BYTE_ENABLE ,Enable byte selection" "Enabled,Disabled"
bitfld.long 0x08 18.--22. " FOURTH_2_BYTE_START ,Fourth byte start position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x08 17. " THIRD_2_BYTE_ENABLE ,Enable byte selection" "Disabled,Enabled"
bitfld.long 0x08 12.--16. " THIRD_2_BYTE_START ,Third byte start position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x08 11. " SECOND_2_BYTE_ENABLE ,Enable byte selection" "Disabled,Enabled"
bitfld.long 0x08 6.--10. " SECOND_2_BYTE_START ,Second byte start position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x08 5. " FIRST_2_BYTE_ENABLE ,Enable byte selection" "Disabled,Enabled"
bitfld.long 0x08 0.--4. " FIRST_2_BYTE_START ,First byte start position" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0b
tree.end
tree "System time with IEEE 1588 functionality (SYSTIME)"
base asd:0x1c001100
width 20.
group.long 0x00++0x1B
line.long 0x00 "SYS_TIME_NS,System Time Nanosecond Register"
line.long 0x04 "SYS_TIME_S,System Time Second Register"
line.long 0x08 "SYS_TIME_NS_BOR,System Time Nanoseconds Border Register"
line.long 0x0C "SYS_TIME_NS_ADD_UP,System Time Nanoseconds Add Up Register"
line.long 0x10 "SYS_TIME_S_CMP,System Time Second Compare Register"
line.long 0x14 "SYS_TIME_S_CMP_EN,System Time Second Compare Enable Register"
bitfld.long 0x14 0. " ENABLE ,Enable compare with SYSTIME_S (seconds)" "Disabled,Enabled"
line.long 0x18 "SYS_TIME_S_CMP_INT,System Time Second Compare Interrupt Register"
eventfld.long 0x18 0. " COMPARE_IRQ ,System time compare interrupt" "No interrupt,Interrupt"
width 0x0B
tree.end
tree "Serial USB-Interface (USB)"
base asd:0x1c020000
width 17.
rgroup.long 0x00++0x03
line.long 0x00 "USB_ID,USB ID Register"
hexmask.long.byte 0x00 8.--12. 1. " CORE_ID ,Core ID"
hexmask.long.byte 0x00 0.--7. 1. " REV_ID ,Revision ID number of the core"
group.long 0x04++0x1B
line.long 0x00 "USB_CTRL,USB Control Register"
bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " ASE ,Async Schedule Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " HRS ,Host Run/Stop" "Stopped,Running"
bitfld.long 0x00 1. " XSUSP ,XCVR Suspend" "Not suspended,Suspended"
textline " "
bitfld.long 0x00 0. " CSUSP ,Core Suspend" "Not suspended,Suspended"
line.long 0x04 "USB_FRM_TMR,USB Frame Timer Register"
bitfld.long 0x04 12. " AGSOF ,Artificially Generated SOF" "Not generated,Generated"
bitfld.long 0x04 11. " FTLOCK ,Frame Timer Locked" "Not locked,Locked"
textline " "
hexmask.long.word 0x04 0.--10. 1. " FRAME_NR ,Current Frame Number"
line.long 0x08 "USB_MAIN_EV,USB Main Event Register"
eventfld.long 0x08 5. " BWERR_EV ,Bandwidth Error Event" "No error,Error"
eventfld.long 0x08 4. " HCHA_EV ,Host Controller Halted Event" "Not halted,Halted"
textline " "
bitfld.long 0x08 3. " GPIPE_EV ,Global Pipe Transfer Event" "Not occurred,Occurred"
bitfld.long 0x08 2. " GPORT_EV ,Global Port Status Change Event" "Not occurred,Occurred"
textline " "
eventfld.long 0x08 1. " FRM32_EV ,Frame 32 Event" "Not occurred,Occurred"
eventfld.long 0x08 0. " FRM_EV ,Frame Event" "Not occurred,Occurred"
line.long 0x0C "USB_MAIN_EV_MSK,USB Main Event Mask Register"
bitfld.long 0x0C 5. " BWERR_EM ,Bandwidth Error Event Mask" "Not masked,Masked"
bitfld.long 0x0C 4. " HCHA_EM ,HC Halted Mask" "Not masked,Masked"
textline " "
bitfld.long 0x0C 3. " GPIPE_EM ,Global Pipe Event Mask" "Not masked,Masked"
bitfld.long 0x0C 2. " GPORT_EM ,Global Port Status Change Event Mask" "Not masked,Masked"
textline " "
bitfld.long 0x0C 1. " FRM32_EM ,Frame 32 Event Mask" "Not masked,Masked"
bitfld.long 0x0C 0. " FRM_EM ,Frame Event Mask" "Not masked,Masked"
line.long 0x10 "USB_PIPE_EV,USB Pipe Event Register"
eventfld.long 0x10 7. " PI_EV7 ,Pipe Event Flag 7" "Not occurred,Occurred"
eventfld.long 0x10 6. " PI_EV6 ,Pipe Event Flag 6" "Not occurred,Occurred"
textline " "
eventfld.long 0x10 5. " PI_EV5 ,Pipe Event Flag 5" "Not occurred,Occurred"
eventfld.long 0x10 4. " PI_EV4 ,Pipe Event Flag 4" "Not occurred,Occurred"
textline " "
eventfld.long 0x10 3. " PI_EV3 ,Pipe Event Flag 3" "Not occurred,Occurred"
eventfld.long 0x10 2. " PI_EV2 ,Pipe Event Flag 2" "Not occurred,Occurred"
textline " "
eventfld.long 0x10 1. " PI_EV1 ,Pipe Event Flag 1" "Not occurred,Occurred"
eventfld.long 0x10 0. " PI_EV0 ,Pipe Event Flag 0" "Not occurred,Occurred"
line.long 0x14 "USB_PIPE_EV_MSK,USB Pipe Event Mask Register"
bitfld.long 0x14 7. " PI_EM7 ,Pipe Event Mask 7 Setting" "Disabled,Enabled"
bitfld.long 0x14 6. " PI_EM6 ,Pipe Event Mask 6 Setting" "Disabled,Enabled"
textline " "
bitfld.long 0x14 5. " PI_EM5 ,Pipe Event Mask 5 Setting" "Disabled,Enabled"
bitfld.long 0x14 4. " PI_EM4 ,Pipe Event Mask 4 Setting" "Disabled,Enabled"
textline " "
bitfld.long 0x14 3. " PI_EM3 ,Pipe Event Mask 3 Setting" "Disabled,Enabled"
bitfld.long 0x14 2. " PI_EM2 ,Pipe Event Mask 2 Setting" "Disabled,Enabled"
textline " "
bitfld.long 0x14 1. " PI_EM1 ,Pipe Event Mask 1 Setting" "Disabled,Enabled"
bitfld.long 0x14 0. " PI_EM0 ,Pipe Event Mask 0 Setting" "Disabled,Enabled"
group.long 0x24++0x03
line.long 0x00 "USB_PIPE_SEL,USB Pipe Select Register"
bitfld.long 0x00 0.--2. " PI_SEL ,Pipe Select" "Pipe 0,Pipe 1,Pipe 2,Pipe 3,Pipe 4,Pipe 5,Pipe 6,Pipe 7"
rgroup.long 0x2C++0x03
line.long 0x00 "USB_PORT_STAT,USB Port Status Register"
bitfld.long 0x00 9. " LINESTATE1 ,USB Line State 1" "Ser_rx_dp,Ser_rx_dm"
bitfld.long 0x00 8. " LINESTATE0 ,USB Line State 0" "Ser_rx_dp,Ser_rx_dm"
textline " "
bitfld.long 0x00 7. " OCURC ,Over Current Condition" "Not detected,Detected"
bitfld.long 0x00 6. " DLS ,Connected device speed" "Full,Low"
textline " "
bitfld.long 0x00 5. " PCS ,Port Connect Status" "Not connected,Connected"
bitfld.long 0x00 4. " CONN_ID ,USB Connector ID Value" "A-Device,B-Device"
textline " "
bitfld.long 0x00 3. " VB_SESS_END ,VB Session End" "Not ended,Ended"
bitfld.long 0x00 2. " VB_SESS_VLD ,VB Session Valid" "Not valid,Valid"
textline " "
bitfld.long 0x00 1. " VA_SESS_VLD ,VA Session Valid" "Not valid,Valid"
bitfld.long 0x00 0. " VBUS_VLD ,Vbus Valid" "Not valid,Valid"
group.long 0x30++0x0B
line.long 0x00 "USB_PORT_CTRL,USB Port Control Register"
hexmask.long.byte 0x00 16.--23. 1. " P_LEN ,Pulse Length"
bitfld.long 0x00 12. " ID_PU ,ID-Pullup Output Signal Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " VBS_ON ,VBUS Session Request Control" "Not controled,Controled"
bitfld.long 0x00 9. " DCHRG ,Enable Discharge Circuitry" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " TERM_ENA ,Termination Enable" "Disabled,Enabled"
bitfld.long 0x00 7. " TERM_SEL ,Termination Select" "Host,Device"
textline " "
bitfld.long 0x00 6. " VB_ON ,VBUS Control" "Disabled,Enabled"
bitfld.long 0x00 5. " PSUSP ,Port Suspend" "Not suspended,Suspended"
textline " "
bitfld.long 0x00 4. " PENA ,Port Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " FPRESU ,Force Resume" "Not forced,Forced"
textline " "
bitfld.long 0x00 2. " URESET ,USB Reset" "No reset,Reset"
bitfld.long 0x00 0.--1. " PTESTC ,Port Test Mode" "Disabled,J State,K State,SE0"
width 26.
line.long 0x04 "USB_PORT_STAT_CHG_EV,USB Port Status Change Event Register"
eventfld.long 0x04 8. " P_END_EV ,Pulse End Event" "Not occurred,Occurred"
eventfld.long 0x04 7. " PWRSC_EV ,Power Status Change Event" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 6. " CDC_EV ,Connect/Disconnect Event" "Not occurred,Occurred"
eventfld.long 0x04 5. " URES_EV ,USB Reset Event" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 4. " SUSP_EV ,Suspend Event" "Not occurred,Occurred"
eventfld.long 0x04 3. " RSUC_EV ,Resume Complete Event" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 2. " RSU_EV ,Resume Event" "Not occurred,Occurred"
eventfld.long 0x04 1. " BERR_EV ,Babble Error Event" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 0. " OCU_EV ,Over Current Event" "Not occurred,Occurred"
line.long 0x08 "USB_PORT_STAT_CHG_EV_MSK,USB Port Status Change Event Mask Register"
bitfld.long 0x08 8. " P_END_EM ,Pulse End Event Mask" "Not masked,Masked"
bitfld.long 0x08 7. " PWRSC_EM ,Power Status Change Event Mask" "Not masked,Masked"
textline " "
bitfld.long 0x08 6. " CDC_EM ,Connect/Disconnect Event Mask" "Not masked,Masked"
bitfld.long 0x08 5. " URES_EM ,USB Reset Event Mask" "Not masked,Masked"
textline " "
bitfld.long 0x08 4. " SUSP_EM ,Suspend Event Mask" "Not masked,Masked"
bitfld.long 0x08 3. " RSUC_EM ,Resume Complete Event Mask" "Not masked,Masked"
textline " "
bitfld.long 0x08 2. " RSU_EM ,Resume Event Mask" "Not masked,Masked"
bitfld.long 0x08 1. " BERR_EM ,Babble Error Event Mask" "Not masked,Masked"
textline " "
bitfld.long 0x08 0. " OCU_EM ,Over Current Event Mask" "Not masked,Masked"
width 15.
group.long 0x40++0x1F
line.long 0x00 "USB_PIPE_CTRL,USB Pipe Control Register"
bitfld.long 0x00 2. " ACT ,Activate Pipe" "Not activated,Activated"
bitfld.long 0x00 0.--1. " TPID ,Token PID/Direction" "OUT,IN,SETUP,?..."
line.long 0x04 "USB_PIPE_CFG,USB Pipe Configuration Register"
bitfld.long 0x04 30. " IOT ,Interrupt on Transaction" "Disabled,Enabled"
bitfld.long 0x04 29. " HIDBE ,Halt on ISO Data Buffer Error" "No error,Error"
textline " "
bitfld.long 0x04 28. " SKIPISO ,Skip ISO Token" "Not skipped,Skipped"
bitfld.long 0x04 24.--27. " PI ,Polling Interval" "1 frame,2 frames,4 frames,8 frames,16 frames,32 frames,64 frames,128 frames,256 frames,?..."
textline " "
hexmask.long.byte 0x04 16.--23. 1. " POFF ,Polling Offset"
bitfld.long 0x04 15. " STALL ,Stall Pipe" "Disabled,Enabled"
textline " "
bitfld.long 0x04 14. " ACID ,Accept corrupted ISO Data" "Disabled,Enabled"
bitfld.long 0x04 13. " EPS ,Endpoint Speed" "Full,Low"
textline " "
bitfld.long 0x04 12. " STRM ,Streaming Mode" "Not activated,Activated"
bitfld.long 0x04 10.--11. " ET ,Endpoint Transfer Type" "Control,Isochronous,Bulk,Interrupt"
textline " "
hexmask.long.word 0x04 0.--9. 1. " MPS ,Maximum Packet Size"
line.long 0x08 "USB_PIPE_ADDR,USB Pipe Address Register"
hexmask.long.byte 0x08 4.--10. 1. " EPADDR ,Endpoint Address"
bitfld.long 0x08 0.--3. " ERNR ,Endpoint Number" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15."
line.long 0x0C "USB_PIPE_STAT,USB Pipe Status Register"
bitfld.long 0x0C 8.--9. " CERR ,Error Counter" "0,1,2,3"
bitfld.long 0x0C 7. " DBERR ,Data Buffer Error" "No error,Error"
textline " "
bitfld.long 0x0C 6. " ACTS ,Active Pipe Status" "Not active,Active"
bitfld.long 0x0C 5. " HALT ,Pipe Halted" "Not halted,Halted"
textline " "
bitfld.long 0x0C 4. " BBL ,Babble detected" "Not detected,Detected"
bitfld.long 0x0C 3. " DBSEL ,Selected Data Buffer" "Normal,Alternative"
textline " "
bitfld.long 0x0C 2. " DT ,Data Toggle" "DATA0,DATA1"
bitfld.long 0x0C 0.--1. " DBOFF ,Data Byte Offset" "0,1,2,3"
width 23.
line.long 0x10 "USB_PIPE_DATA_PTR,USB Pipe Data Pointer Register"
hexmask.long.word 0x10 0.--9. 1. " DPTR ,Data Pointer"
line.long 0x14 "USB_PIPE_DATA_TOT,USB Pipe Total Bytes Register"
bitfld.long 0x14 31. " DBV ,Data Buffer Valid" "Not valid,Valid"
hexmask.long.word 0x14 0.--12. 1. " TBYTES ,Total Bytes To Transfer"
line.long 0x18 "USB_PIPE_ALT_DATA_PTR,USB Pipe Alternative Data Pointer Register"
hexmask.long.word 0x18 0.--9. 1. " ALT_DATA_PTR ,Alternative Data Pointer"
line.long 0x1C "USB_PIPE_ALT_DATA_TOT,USB Pipe Alternative Data Total Bytes Register"
bitfld.long 0x1C 31. " ADBV ,Alternative Data Buffer Valid" "Not valid,Valid"
hexmask.long.word 0x1C 0.--10. 1. " ATBYTES ,Alternative Total Bytes To Transfer"
width 16.
group.long 0x60++0x07
line.long 0x00 "USB_DBG_CTRL,USB Debug Control Register"
bitfld.long 0x00 9. " UDTPID ,Debug Token PID" "Not used,Used"
bitfld.long 0x00 8. " UDHSPID ,Debug Handshake PID" "Not used,Used"
textline " "
bitfld.long 0x00 7. " UDDPID ,Use Debug Data PID" "Not used,Used"
bitfld.long 0x00 6. " FRXCRC16G ,Force Receive Good CRC16" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " FRXCRC5G ,Force Receive Good CRC5" "Disabled,Enabled"
bitfld.long 0x00 4. " FRXCRCE ,Force Receive CRC Error" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " FTXCRC16E ,Force Transmit CRC16 Error" "Disabled,Enabled"
bitfld.long 0x00 2. " FTXCRC5E ,Force Transmit CRC5 Error" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " DBSTX ,Disable Bitstuffing Transmit" "No,Yes"
bitfld.long 0x00 0. " DBSERRDET ,Disable Bitstuff Error Detection" "No,Yes"
line.long 0x04 "USB_DBG_PID,USB Debug PID Register"
hexmask.long.byte 0x04 16.--23. 1. " DHSPID ,Debug Handshake PID"
hexmask.long.byte 0x04 8.--15. 1. " DTPID ,Debug Token PID"
textline " "
hexmask.long.byte 0x04 0.--7. 1. " DDPID ,Debug Data PID"
rgroup.long 0x68++0x03
line.long 0x00 "USB_DEBUG_STAT,USB Debug Status Register"
hexmask.long.byte 0x00 0.--7. 1. " DRXPIP ,Debug Receive PID"
group.long 0x6C++0x03
line.long 0x00 "USB_TEST,USB Test Register"
rgroup.long 0x80++0x07
line.long 0x00 "USB_MAIN_CFG,USB Main Configuration Register"
bitfld.long 0x00 24.--29. " RAW_CFG ,RAM Address Width Configuration" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
bitfld.long 0x00 6.--11. " DW_CFG ,Data Width Configuration" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
textline " "
bitfld.long 0x00 0.--5. " NOP_CFG ,Number of Pipes Configuration" "0.,1.,2.,3.,4.,5.,6.,7.,8.,9.,10.,11.,12.,13.,14.,15.,16.,17.,18.,19.,20.,21.,22.,23.,24.,25.,26.,27.,28.,29.,30.,31.,32.,33.,34.,35.,36.,37.,38.,39.,40.,41.,42.,43.,44.,45.,46.,47.,48.,49.,50.,51.,52.,53.,54.,55.,56.,57.,58.,59.,60.,61.,62.,63."
line.long 0x04 "USB_MODE_CFG,USB Mode Configuration Register"
bitfld.long 0x04 17. " XDBG_CFG ,Core Configured For Extended Debug" "Not configured,Configured"
bitfld.long 0x04 16. " DBG_CFG ,Core Configured For Debug Support" "Not configured,Configured"
textline " "
hexmask.long.byte 0x04 0.--7. 1. " ABUFF_CFG ,Alternative Buffer Configuration"
hgroup.long 0x1c030000++0x03
hide.long 0x00 "USB_FIFO,FIFO for USB-Interface"
button "USB_FIFO" "D ad:0x1c030000++0xFFFF /long"
group.long 0x88++0x03
line.long 0x00 "USB_CORE_CTRL,USB Core Control and Status Register"
bitfld.long 0x00 24. " USB_IRQ ,Reflects usb_irq" "No interrupt,Interrput"
textline " "
bitfld.long 0x00 23. " UCIF_RDY ,Reflects ucif_rdy" "Not ready,Ready"
textline " "
bitfld.long 0x00 22. " DISCHRG_VBUS ,Reflects dischrg_vbus" "Not discharged,Discharged"
textline " "
bitfld.long 0x00 21. " VB_ON ,Reflects vb_on" "Off,On"
textline " "
bitfld.long 0x00 20. " DLP_ACTIVE ,Reflects dlp_active" "Not activated,Activated"
textline " "
bitfld.long 0x00 19. " CHRG_VBUS ,Reflects chrg_vbus" "Not charged,Charged"
textline " "
bitfld.long 0x00 18. " VBUS_VLD ,Reflects vbus_vld" "Not valid,Valid"
textline " "
bitfld.long 0x00 17. " VB_SESS_VLD ,Reflects vb_sess_vld" "Not valid,Valid"
textline " "
bitfld.long 0x00 16. " VB_SESS_END ,Reflects vb_sess_end" "Not ended,Ended"
textline " "
bitfld.long 0x00 15. " VA_SESS_VLD ,Reflects va_sess_vld" "Not valid,Valid"
textline " "
bitfld.long 0x00 14. " OVER_CURRENT ,Reflects over_current" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XCVR_SUSPEND_N ,Reflects xcvr_suspend_n" "Not suspended,Suspended"
textline " "
bitfld.long 0x00 12. " CORE_SUSPEND_N ,Reflects core_suspend_n" "Not suspended,Suspended"
textline " "
hexmask.long.byte 0x00 4.--11. 1. " ALT_BUFF_SUPPORT ,Alt Buffer Support"
textline " "
bitfld.long 0x00 3. " SOFT_ID_DIG ,Set id_dig Via Software" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " XTD_DBG_SUPPORT ,Extended Debug Support Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " DBG_SUPPORT ,Debug Support Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " RESET ,Software Reset" "Disabled,Enabled"
width 0x0B
tree.end
tree "Vector Interrupt Controller (VIC)"
base asd:0x1c7ff000
width 0x11
rgroup.long 0x000++0x00B
line.long 0x00 "VIC_IRQ_STAT,VIC IRQ Status Register"
bitfld.long 0x00 30. " TIMER4 ,Timer 4" "No interrupt,Interrupt"
bitfld.long 0x00 29. " TIMER3 ,Timer 3" "No interrupt,Interrupt"
bitfld.long 0x00 28. " TRIGGER_LT ,TRIGGER LT" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " DMAC ,DMAC " "No interrupt,Interrupt"
bitfld.long 0x00 25. " INT_PHY ,Internal PHY" "No interrupt,Interrupt"
bitfld.long 0x00 22. " MSYNC1 ,Motion synchronization channel 1" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 21. " MSYNC0 ,Motion synchronization channel 0" "No interrupt,Interrupt"
bitfld.long 0x00 18. " COM1 ,Communication channel 1" "No interrupt,Interrupt"
bitfld.long 0x00 17. " COM0 ,Communication channel 0" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 16. " GPIO ,External Interrupts from GPIO 0-14" "No interrupt,Interrupt"
bitfld.long 0x00 15. " PCI/HIF ,PCI/HIF interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 13. " I2C ,I2C" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " SPI ,SPI interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 11. " USB ,USB interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 10. " UART2 ,UART 2" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 9. " UART1 ,UART 1" "No interrupt,Interrupt"
bitfld.long 0x00 8. " UART0 ,UART 0" "No interrupt,Interrupt"
bitfld.long 0x00 7. " WATCHDOG ,WATCHDOG" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 6. " GPIO31 ,External interrupt at GPIO 31" "No interrupt,Interrupt"
bitfld.long 0x00 5. " SYSTIME_S ,System time IRQ from SYSTIME module" "No interrupt,Interrupt"
bitfld.long 0x00 4. " SYSTIME_NS ,System time ns compare interrupt from GPIO module" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " TIMER2 ,Timer 2 / Counter 2 from GPIO Module" "No interrupt,Interrupt"
bitfld.long 0x00 2. " TIMER1 ,Timer 1 / Counter 1 from GPIO Module" "No interrupt,Interrupt"
bitfld.long 0x00 1. " TIMER0 ,Timer 0 / Counter 0 from GPIO Module" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 0. " SW ,Software Interrupt" "No interrupt,Interrupt"
line.long 0x04 "VIC_FIQ_STAT,VIC FIQ Status Register"
bitfld.long 0x04 30. " TIMER4 ,Timer 4" "No interrupt,Interrupt"
bitfld.long 0x04 29. " TIMER3 ,Timer 3" "No interrupt,Interrupt"
bitfld.long 0x04 28. " TRIGGER_LT ,TRIGGER LT" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 27. " DMAC ,DMAC " "No interrupt,Interrupt"
bitfld.long 0x04 25. " INT_PHY ,Internal PHY" "No interrupt,Interrupt"
bitfld.long 0x04 22. " MSYNC1 ,Motion synchronization channel 1" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 21. " MSYNC0 ,Motion synchronization channel 0" "No interrupt,Interrupt"
bitfld.long 0x04 18. " COM1 ,Communication channel 1" "No interrupt,Interrupt"
bitfld.long 0x04 17. " COM0 ,Communication channel 0" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 16. " GPIO ,External Interrupts from GPIO 0-14" "No interrupt,Interrupt"
bitfld.long 0x04 15. " PCI/HIF ,PCI/HIF interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 13. " I2C ,I2C" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 12. " SPI ,SPI interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 11. " USB ,USB interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 10. " UART2 ,UART 2" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 9. " UART1 ,UART 1" "No interrupt,Interrupt"
bitfld.long 0x04 8. " UART0 ,UART 0" "No interrupt,Interrupt"
bitfld.long 0x04 7. " WATCHDOG ,WATCHDOG" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 6. " GPIO31 ,External interrupt at GPIO 31" "No interrupt,Interrupt"
bitfld.long 0x04 5. " SYSTIME_S ,System time IRQ from SYSTIME module" "No interrupt,Interrupt"
bitfld.long 0x04 4. " SYSTIME_NS ,System time ns compare interrupt from GPIO module" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " TIMER2 ,Timer 2 / Counter 2 from GPIO Module" "No interrupt,Interrupt"
bitfld.long 0x04 2. " TIMER1 ,Timer 1 / Counter 1 from GPIO Module" "No interrupt,Interrupt"
bitfld.long 0x04 1. " TIMER0 ,Timer 0 / Counter 0 from GPIO Module" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " SW ,Software Interrupt" "No interrupt,Interrupt"
line.long 0x08 "VIC_RAW_INT_STAT,VIC Raw Interrupt Status Register"
bitfld.long 0x08 30. " TIMER4 ,Timer 4" "No interrupt,Interrupt"
bitfld.long 0x08 29. " TIMER3 ,Timer 3" "No interrupt,Interrupt"
bitfld.long 0x08 28. " TRIGGER_LT ,TRIGGER LT" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 27. " DMAC ,DMAC " "No interrupt,Interrupt"
bitfld.long 0x08 25. " INT_PHY ,Internal PHY" "No interrupt,Interrupt"
bitfld.long 0x08 22. " MSYNC1 ,Motion synchronization channel 1" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 21. " MSYNC0 ,Motion synchronization channel 0" "No interrupt,Interrupt"
bitfld.long 0x08 18. " COM1 ,Communication channel 1" "No interrupt,Interrupt"
bitfld.long 0x08 17. " COM0 ,Communication channel 0" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 16. " GPIO ,External Interrupts from GPIO 0-14" "No interrupt,Interrupt"
bitfld.long 0x08 15. " PCI/HIF ,PCI/HIF interrupt" "No interrupt,Interrupt"
bitfld.long 0x08 13. " I2C ,I2C" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 12. " SPI ,SPI interrupt" "No interrupt,Interrupt"
bitfld.long 0x08 11. " USB ,USB interrupt" "No interrupt,Interrupt"
bitfld.long 0x08 10. " UART2 ,UART 2" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 9. " UART1 ,UART 1" "No interrupt,Interrupt"
bitfld.long 0x08 8. " UART0 ,UART 0" "No interrupt,Interrupt"
bitfld.long 0x08 7. " WATCHDOG ,WATCHDOG" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 6. " GPIO31 ,External interrupt at GPIO 31" "No interrupt,Interrupt"
bitfld.long 0x08 5. " SYSTIME_S ,System time IRQ from SYSTIME module" "No interrupt,Interrupt"
bitfld.long 0x08 4. " SYSTIME_NS ,System time ns compare interrupt from GPIO module" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 3. " TIMER2 ,Timer 2 / Counter 2 from GPIO Module" "No interrupt,Interrupt"
bitfld.long 0x08 2. " TIMER1 ,Timer 1 / Counter 1 from GPIO Module" "No interrupt,Interrupt"
bitfld.long 0x08 1. " TIMER0 ,Timer 0 / Counter 0 from GPIO Module" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 0. " SW ,Software Interrupt" "No interrupt,Interrupt"
group.long 0x00C++0x003
line.long 0x00 "VIC_INT_SEL,VIC Interrupt Select Register"
bitfld.long 0x00 30. " TIMER4 ,Timer 4" "IRQ,FIQ"
bitfld.long 0x00 29. " TIMER3 ,Timer 3" "IRQ,FIQ"
bitfld.long 0x00 28. " TRIGGER_LT ,TRIGGER LT" "IRQ,FIQ"
bitfld.long 0x00 27. " DMAC ,DMAC " "IRQ,FIQ"
textline " "
bitfld.long 0x00 25. " INT_PHY ,Internal PHY" "IRQ,FIQ"
bitfld.long 0x00 22. " MSYNC1 ,Motion synchronization channel 1" "IRQ,FIQ"
bitfld.long 0x00 21. " MSYNC0 ,Motion synchronization channel 0" "IRQ,FIQ"
bitfld.long 0x00 18. " COM1 ,Communication channel 1" "IRQ,FIQ"
textline " "
bitfld.long 0x00 17. " COM0 ,Communication channel 0" "IRQ,FIQ"
bitfld.long 0x00 16. " GPIO ,External Interrupts from GPIO 0-14" "IRQ,FIQ"
bitfld.long 0x00 15. " PCI/HIF ,PCI/HIF interrupt" "IRQ,FIQ"
bitfld.long 0x00 13. " I2C ,I2C" "IRQ,FIQ"
textline " "
bitfld.long 0x00 12. " SPI ,SPI interrupt" "IRQ,FIQ"
bitfld.long 0x00 11. " USB ,USB interrupt" "IRQ,FIQ"
bitfld.long 0x00 10. " UART2 ,UART 2" "IRQ,FIQ"
bitfld.long 0x00 9. " UART1 ,UART 1" "IRQ,FIQ"
textline " "
bitfld.long 0x00 8. " UART0 ,UART 0" "IRQ,FIQ"
bitfld.long 0x00 7. " WATCHDOG ,WATCHDOG" "IRQ,FIQ"
bitfld.long 0x00 6. " GPIO31 ,External interrupt at GPIO 31" "IRQ,FIQ"
bitfld.long 0x00 5. " SYSTIME_S ,System time IRQ from SYSTIME module" "IRQ,FIQ"
textline " "
bitfld.long 0x00 4. " SYSTIME_NS ,System time ns compare interrupt from GPIO module" "IRQ,FIQ"
bitfld.long 0x00 3. " TIMER2 ,Timer 2 / Counter 2 from GPIO Module" "IRQ,FIQ"
bitfld.long 0x00 2. " TIMER1 ,Timer 1 / Counter 1 from GPIO Module" "IRQ,FIQ"
bitfld.long 0x00 1. " TIMER0 ,Timer 0 / Counter 0 from GPIO Module" "IRQ,FIQ"
textline " "
bitfld.long 0x00 0. " SW ,Software Interrupt" "IRQ,FIQ"
group.long 0x010++0x03
line.long 0x00 "VIC_INT_EN,VIC Interrupt Enable Register"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " TIMER4_set/clr ,Timer 4" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " TIMER3_set/clr ,Timer 3" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " TRIGGER_LT_set/clr ,TRIGGER LT " "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " DMAC_set/clr ,TRIGGER LT " "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INT_PHY_set/clr ,Internal PHY" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " MSYNC1_set/clr ,Motion synchronization channel 1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " MSYNC0_set/clr ,Motion synchronization channel 0" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " COM1_set/clr ,Communication channel 1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " COM0_set/clr ,Communication channel 0" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " GPIO_set/clr ,External Interrupts from GPIO 0-14" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PCI/HIF_set/clr ,PCI/HIF interrupt" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " I2C_set/clr ,I2C" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " SPI_set/clr ,SPI interrupt" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " USB_set/clr ,USB interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " UART2_set/clr ,UART 2" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " UART1_set/clr ,UART 1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " UART0_set/clr ,UART 0" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " WATCHDOG_set/clr ,WATCHDOG" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " GPIO31_set/clr ,External interrupt at GPIO 31" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SYSTIME_S_set/clr ,System time IRQ from SYSTIME module" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SYSTIME_NS_set/clr ,System time ns compare interrupt from GPIO module" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TIMER2_set/clr ,Timer 2 / Counter 2 from GPIO Module" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TIMER1_set/clr ,Timer 1 / Counter 1 from GPIO Module" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TIMER0_set/clr ,Timer 0 / Counter 0 from GPIO Module" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SW_set/clr ,Software Interrupt" "Disabled,Enabled"
group.long 0x018++0x003
line.long 0x00 "VIC_SWI,VIC Software Interrupt Register"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " TIMER4_set/clr ,Timer 4" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " TIMER3_set/clr ,Timer 3" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " TRIGGER_LT_set/clr ,TRIGGER LT " "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " DMAC_set/clr ,TRIGGER LT " "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INT_PHY_set/clr ,Internal PHY" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " MSYNC1_set/clr ,Motion synchronization channel 1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " MSYNC0_set/clr ,Motion synchronization channel 0" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " COM1_set/clr ,Communication channel 1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " COM0_set/clr ,Communication channel 0" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " GPIO_set/clr ,External Interrupts from GPIO 0-14" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " PCI/HIF_set/clr ,PCI/HIF interrupt" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " I2C_set/clr ,I2C" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " SPI_set/clr ,SPI interrupt" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " USB_set/clr ,USB interrupt" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " UART2_set/clr ,UART 2" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " UART1_set/clr ,UART 1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " UART0_set/clr ,UART 0" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " WATCHDOG_set/clr ,WATCHDOG" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " GPIO31_set/clr ,External interrupt at GPIO 31" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " SYSTIME_S_set/clr ,System time IRQ from SYSTIME module" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " SYSTIME_NS_set/clr ,System time ns compare interrupt from GPIO module" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TIMER2_set/clr ,Timer 2 / Counter 2 from GPIO Module" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " TIMER1_set/clr ,Timer 1 / Counter 1 from GPIO Module" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " TIMER0_set/clr ,Timer 0 / Counter 0 from GPIO Module" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SW_set/clr ,Software Interrupt" "Disabled,Enabled"
group.long 0x020++0x003
line.long 0x00 "VIC_PROT_EN,VIC Protection Enable Register"
bitfld.long 0x00 0. " VIC_PROT_EN ,VIC Registers Protection Enable" "Disabled,Enabled"
group.long 0x030++0x007
line.long 0x000 "VIC_VECT_ADDR,VIC Vector Address Register"
line.long 0x004 "IC_DFLT_VECT_ADDR,VIC Default Vector Address Register"
tree "VIC Vector Address Registers"
group.long 0x100++0x03F
line.long 0x0 "VIC_VECT_ADDR0,VIC Vector Address Register 0"
line.long 0x4 "VIC_VECT_ADDR1,VIC Vector Address Register 1"
line.long 0x8 "VIC_VECT_ADDR2,VIC Vector Address Register 2"
line.long 0xC "VIC_VECT_ADDR3,VIC Vector Address Register 3"
line.long 0x10 "VIC_VECT_ADDR4,VIC Vector Address Register 4"
line.long 0x14 "VIC_VECT_ADDR5,VIC Vector Address Register 5"
line.long 0x18 "VIC_VECT_ADDR6,VIC Vector Address Register 6"
line.long 0x1C "VIC_VECT_ADDR7,VIC Vector Address Register 7"
line.long 0x20 "VIC_VECT_ADDR8,VIC Vector Address Register 8"
line.long 0x24 "VIC_VECT_ADDR9,VIC Vector Address Register 9"
line.long 0x28 "VIC_VECT_ADDR10,VIC Vector Address Register 10"
line.long 0x2C "VIC_VECT_ADDR11,VIC Vector Address Register 11"
line.long 0x30 "VIC_VECT_ADDR12,VIC Vector Address Register 12"
line.long 0x34 "VIC_VECT_ADDR13,VIC Vector Address Register 13"
line.long 0x38 "VIC_VECT_ADDR14,VIC Vector Address Register 14"
line.long 0x3C "VIC_VECT_ADDR15,VIC Vector Address Register 15"
tree.end
tree "VIC Vector Control Registers"
group.long 0x200++0x03F
line.long 0x0 "VIC_VECT_CTRL0,VIC Vector Control Register 0"
bitfld.long 0x0 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x0 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x4 "VIC_VECT_CTRL1,VIC Vector Control Register 1"
bitfld.long 0x4 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x4 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x8 "VIC_VECT_CTRL2,VIC Vector Control Register 2"
bitfld.long 0x8 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x8 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0xC "VIC_VECT_CTRL3,VIC Vector Control Register 3"
bitfld.long 0xC 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0xC 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x10 "VIC_VECT_CTRL4,VIC Vector Control Register 4"
bitfld.long 0x10 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x10 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x14 "VIC_VECT_CTRL5,VIC Vector Control Register 5"
bitfld.long 0x14 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x14 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x18 "VIC_VECT_CTRL6,VIC Vector Control Register 6"
bitfld.long 0x18 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x18 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x1C "VIC_VECT_CTRL7,VIC Vector Control Register 7"
bitfld.long 0x1C 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x1C 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x20 "VIC_VECT_CTRL8,VIC Vector Control Register 8"
bitfld.long 0x20 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x20 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x24 "VIC_VECT_CTRL9,VIC Vector Control Register 9"
bitfld.long 0x24 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x24 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x28 "VIC_VECT_CTRL10,VIC Vector Control Register 10"
bitfld.long 0x28 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x28 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x2C "VIC_VECT_CTRL11,VIC Vector Control Register 11"
bitfld.long 0x2C 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x2C 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x30 "VIC_VECT_CTRL12,VIC Vector Control Register 12"
bitfld.long 0x30 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x30 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x34 "VIC_VECT_CTRL13,VIC Vector Control Register 13"
bitfld.long 0x34 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x34 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x38 "VIC_VECT_CTRL14,VIC Vector Control Register 14"
bitfld.long 0x38 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x38 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
line.long 0x3C "VIC_VECT_CTRL15,VIC Vector Control Register 15"
bitfld.long 0x3C 5. " ENABLE ,Vector Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x3C 0.--4. " INT_SOURCE ,Select interrupt source" "SW,TIMER0,TIMER1,TIMER2,SYSTIME_NS,SYSTIME_S,GPIO31,WATCHDOG,UART0,UART1,UART2,USB,SPI,I2C,Reserved,PCI/HIF,GPIO,COM0,COM1,Reserved,Reserved,MSYNC0,MSYNC1,Reserved,Reserved,INT_PHY,Reserved,DMAC,TRIGGER_LT,TIMER3,TIMER4,?..."
tree.end
width 0x0B
tree.end
tree.end
tree.open "Communication Functions"
tree "Controller for internal PHYs (PHY)"
base asd:0x1c000010
width 0x08
group.long 0x00++0x03
line.long 0x00 "PHY_CR,PHY Control Register"
bitfld.long 0x00 31. " PHY_RESET ,Hardware reset for PHY" "No reset,Reset"
textline " "
bitfld.long 0x00 30. " PHY_SIM_BYP ,PHY Power up Bypass" "Normal,Bypass"
textline " "
sif (cpu()!="NETX50")
bitfld.long 0x00 29. " PHY_CLK_XLATIN ,Source for clock Ethernet PHY" "Phyclk_rate_mul_add,External oscillator"
textline " "
endif
bitfld.long 0x00 21. " PHY1_ENABLE ,PHY1 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 18.--20. " PHY1_NP_MSG_CODE ,PHY1 Next Page Message Code" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 17. " PHY1_AUTOMDIX ,PHY1 Enable AutoMDIX state machine" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " PHY1_FXMODE ,PHY1 100BASE-FX mode" "TX,FX"
textline " "
bitfld.long 0x00 13.--15. " PHY1_MODE ,PHY1 Mode" "10BASE-T Half Duplex,10BASE-T Full Duplex,100BASE-TX/FX Half Duplex,100BASE-TX/FX Full Duplex,100BASE-TX Half Duplex,Repeater mode,Power Down mode,All capable"
textline " "
bitfld.long 0x00 12. " PHY0_ENABLE ,PHY0 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9.--11. " PHY0_NP_MSG_CODE ,PHY0 Next Page Message Code" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 8. " PHY0_AUTOMDIX ,PHY0 Enable AutoMDIX state machine" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " PHY0_FXMODE ,PHY0 100BASE-FX mode" "TX,FX"
textline " "
bitfld.long 0x00 4.--6. " PHY0_MODE ,PHY0 Mode" "10BASE-T Half Duplex,10BASE-T Full Duplex,100BASE-TX/FX Half Duplex,100BASE-TX/FX Full Duplex,100BASE-TX Half Duplex,Repeater mode,Power Down mode,All capable"
textline " "
hexmask.long.byte 0x00 0.--3. 1. " PHY_ADDRESS ,Bits 4:1 of phy mdio-address"
sif (cpu()=="NETX100")
width 22.
group.long 0x10++0x03
line.long 0x00 "PHY_CLK_RATE_MUL_ADD,PHY Clock Rate Multiplier Add Value"
hexmask.long 0x00 0.--30. 1. " PHYCLK_RATE_MUL_ADD ,Value added each clk200 cycle to phyclk_rate_mul to generate phyclk"
endif
width 0x0B
base asd:0x1c000c00
width 17.
group.long 0x00++0x13 "MII-Management Unit"
line.long 0x00 "MIIMU_RXTX,MIIMU Receive/Transmit Register "
hexmask.long.word 0x00 16.--31. 1. " MIIMU_DATA ,Data to or from PHY register"
bitfld.long 0x00 11.--15. " MIIMU_PHYADDR ,PHY address " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 6.--10. " MIIMU_REGADDR ,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5. " MIIMU_RTA ,Read Turn Around field" "1 bit,2 bit"
textline " "
bitfld.long 0x00 4. " PHY_NRES ,PHY hardware nReset" "No reset,Reset"
bitfld.long 0x00 3. " MIIMU_MDC_PERIOD ,MDC period" "400ns,800ns"
textline " "
bitfld.long 0x00 2. " MIIMU_OPMODE ,Operation mode" "Read,Write"
bitfld.long 0x00 1. " MIIMU_PREAMBLE ,Send preamble " "Not Sent,Sent"
textline " "
bitfld.long 0x00 0. " MIIMU_SNRDY ,Start not ready " "Ready,Not ready"
line.long 0x04 "MIIMU_MODE_EN,MIIMU Software Mode Enable"
bitfld.long 0x04 0. " MIIMU_SW_EN ,Enables software mode " "Disabled,Enabled"
line.long 0x08 "MIIMU_MODE_MDC,MIIMU Software Mode MDC Register"
bitfld.long 0x08 0. " MIIMU_SW_MDC ,MDC value for software mode " "0,1"
line.long 0x0c "MIIMU_MODE_MDO,MIIMU Software Mode MDO Register"
bitfld.long 0x0c 0. " MIIMU_SW_MDO ,MDO value for software mode " "0,1"
line.long 0x10 "MIIMU_MODE_MDOE,MIIMU Software Mode MDOE Register"
bitfld.long 0x10 0. " MIIMU_SW_MDOE ,MDOE value for software mode" "0,1"
rgroup.long 0x14++0x03
line.long 0x00 "MIIMU_MODE_MDI,MIIMU Software Mode MDI Register "
bitfld.long 0x00 0. " MIIMU_SW_MDI ,Current MDI value " "0,1"
width 0x0B
tree.end
tree "Pointer FIFO (PFIFO)"
base asd:0x1c064000
width 21.
tree "PTR_FIFO_BASE[0-31] (Pointer FIFO 0-31 Base Address)"
hgroup.long 0x0++0x3
hide.long 0x00 "PTR_FIFO_BASE0,Pointer FIFO 0 Base Address"
in
hgroup.long 0x4++0x3
hide.long 0x00 "PTR_FIFO_BASE1,Pointer FIFO 1 Base Address"
in
hgroup.long 0x8++0x3
hide.long 0x00 "PTR_FIFO_BASE2,Pointer FIFO 2 Base Address"
in
hgroup.long 0xC++0x3
hide.long 0x00 "PTR_FIFO_BASE3,Pointer FIFO 3 Base Address"
in
hgroup.long 0x10++0x3
hide.long 0x00 "PTR_FIFO_BASE4,Pointer FIFO 4 Base Address"
in
hgroup.long 0x14++0x3
hide.long 0x00 "PTR_FIFO_BASE5,Pointer FIFO 5 Base Address"
in
hgroup.long 0x18++0x3
hide.long 0x00 "PTR_FIFO_BASE6,Pointer FIFO 6 Base Address"
in
hgroup.long 0x1C++0x3
hide.long 0x00 "PTR_FIFO_BASE7,Pointer FIFO 7 Base Address"
in
hgroup.long 0x20++0x3
hide.long 0x00 "PTR_FIFO_BASE8,Pointer FIFO 8 Base Address"
in
hgroup.long 0x24++0x3
hide.long 0x00 "PTR_FIFO_BASE9,Pointer FIFO 9 Base Address"
in
hgroup.long 0x28++0x3
hide.long 0x00 "PTR_FIFO_BASE10,Pointer FIFO 10 Base Address"
in
hgroup.long 0x2C++0x3
hide.long 0x00 "PTR_FIFO_BASE11,Pointer FIFO 11 Base Address"
in
hgroup.long 0x30++0x3
hide.long 0x00 "PTR_FIFO_BASE12,Pointer FIFO 12 Base Address"
in
hgroup.long 0x34++0x3
hide.long 0x00 "PTR_FIFO_BASE13,Pointer FIFO 13 Base Address"
in
hgroup.long 0x38++0x3
hide.long 0x00 "PTR_FIFO_BASE14,Pointer FIFO 14 Base Address"
in
hgroup.long 0x3C++0x3
hide.long 0x00 "PTR_FIFO_BASE15,Pointer FIFO 15 Base Address"
in
hgroup.long 0x40++0x3
hide.long 0x00 "PTR_FIFO_BASE16,Pointer FIFO 16 Base Address"
in
hgroup.long 0x44++0x3
hide.long 0x00 "PTR_FIFO_BASE17,Pointer FIFO 17 Base Address"
in
hgroup.long 0x48++0x3
hide.long 0x00 "PTR_FIFO_BASE18,Pointer FIFO 18 Base Address"
in
hgroup.long 0x4C++0x3
hide.long 0x00 "PTR_FIFO_BASE19,Pointer FIFO 19 Base Address"
in
hgroup.long 0x50++0x3
hide.long 0x00 "PTR_FIFO_BASE20,Pointer FIFO 20 Base Address"
in
hgroup.long 0x54++0x3
hide.long 0x00 "PTR_FIFO_BASE21,Pointer FIFO 21 Base Address"
in
hgroup.long 0x58++0x3
hide.long 0x00 "PTR_FIFO_BASE22,Pointer FIFO 22 Base Address"
in
hgroup.long 0x5C++0x3
hide.long 0x00 "PTR_FIFO_BASE23,Pointer FIFO 23 Base Address"
in
hgroup.long 0x60++0x3
hide.long 0x00 "PTR_FIFO_BASE24,Pointer FIFO 24 Base Address"
in
hgroup.long 0x64++0x3
hide.long 0x00 "PTR_FIFO_BASE25,Pointer FIFO 25 Base Address"
in
hgroup.long 0x68++0x3
hide.long 0x00 "PTR_FIFO_BASE26,Pointer FIFO 26 Base Address"
in
hgroup.long 0x6C++0x3
hide.long 0x00 "PTR_FIFO_BASE27,Pointer FIFO 27 Base Address"
in
hgroup.long 0x70++0x3
hide.long 0x00 "PTR_FIFO_BASE28,Pointer FIFO 28 Base Address"
in
hgroup.long 0x74++0x3
hide.long 0x00 "PTR_FIFO_BASE29,Pointer FIFO 29 Base Address"
in
hgroup.long 0x78++0x3
hide.long 0x00 "PTR_FIFO_BASE30,Pointer FIFO 30 Base Address"
in
hgroup.long 0x7C++0x3
hide.long 0x00 "PTR_FIFO_BASE31,Pointer FIFO 31 Base Address"
in
tree.end
tree "PTR_FIFO_BOR_BASE[0-31] (Pointer FIFO 0-31 Upper Border)"
group.long 0x080++0x7F
textline " "
line.long 0x0 "PTR_FIFO_BOR_BASE0,Pointer FIFO 0 Upper Border"
hexmask.long.word 0x0 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x4 "PTR_FIFO_BOR_BASE1,Pointer FIFO 1 Upper Border"
hexmask.long.word 0x4 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x8 "PTR_FIFO_BOR_BASE2,Pointer FIFO 2 Upper Border"
hexmask.long.word 0x8 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0xC "PTR_FIFO_BOR_BASE3,Pointer FIFO 3 Upper Border"
hexmask.long.word 0xC 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x10 "PTR_FIFO_BOR_BASE4,Pointer FIFO 4 Upper Border"
hexmask.long.word 0x10 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x14 "PTR_FIFO_BOR_BASE5,Pointer FIFO 5 Upper Border"
hexmask.long.word 0x14 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x18 "PTR_FIFO_BOR_BASE6,Pointer FIFO 6 Upper Border"
hexmask.long.word 0x18 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x1C "PTR_FIFO_BOR_BASE7,Pointer FIFO 7 Upper Border"
hexmask.long.word 0x1C 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x20 "PTR_FIFO_BOR_BASE8,Pointer FIFO 8 Upper Border"
hexmask.long.word 0x20 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x24 "PTR_FIFO_BOR_BASE9,Pointer FIFO 9 Upper Border"
hexmask.long.word 0x24 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x28 "PTR_FIFO_BOR_BASE10,Pointer FIFO 10 Upper Border"
hexmask.long.word 0x28 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x2C "PTR_FIFO_BOR_BASE11,Pointer FIFO 11 Upper Border"
hexmask.long.word 0x2C 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x30 "PTR_FIFO_BOR_BASE12,Pointer FIFO 12 Upper Border"
hexmask.long.word 0x30 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x34 "PTR_FIFO_BOR_BASE13,Pointer FIFO 13 Upper Border"
hexmask.long.word 0x34 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x38 "PTR_FIFO_BOR_BASE14,Pointer FIFO 14 Upper Border"
hexmask.long.word 0x38 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x3C "PTR_FIFO_BOR_BASE15,Pointer FIFO 15 Upper Border"
hexmask.long.word 0x3C 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x40 "PTR_FIFO_BOR_BASE16,Pointer FIFO 16 Upper Border"
hexmask.long.word 0x40 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x44 "PTR_FIFO_BOR_BASE17,Pointer FIFO 17 Upper Border"
hexmask.long.word 0x44 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x48 "PTR_FIFO_BOR_BASE18,Pointer FIFO 18 Upper Border"
hexmask.long.word 0x48 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x4C "PTR_FIFO_BOR_BASE19,Pointer FIFO 19 Upper Border"
hexmask.long.word 0x4C 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x50 "PTR_FIFO_BOR_BASE20,Pointer FIFO 20 Upper Border"
hexmask.long.word 0x50 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x54 "PTR_FIFO_BOR_BASE21,Pointer FIFO 21 Upper Border"
hexmask.long.word 0x54 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x58 "PTR_FIFO_BOR_BASE22,Pointer FIFO 22 Upper Border"
hexmask.long.word 0x58 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x5C "PTR_FIFO_BOR_BASE23,Pointer FIFO 23 Upper Border"
hexmask.long.word 0x5C 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x60 "PTR_FIFO_BOR_BASE24,Pointer FIFO 24 Upper Border"
hexmask.long.word 0x60 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x64 "PTR_FIFO_BOR_BASE25,Pointer FIFO 25 Upper Border"
hexmask.long.word 0x64 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x68 "PTR_FIFO_BOR_BASE26,Pointer FIFO 26 Upper Border"
hexmask.long.word 0x68 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x6C "PTR_FIFO_BOR_BASE27,Pointer FIFO 27 Upper Border"
hexmask.long.word 0x6C 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x70 "PTR_FIFO_BOR_BASE28,Pointer FIFO 28 Upper Border"
hexmask.long.word 0x70 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x74 "PTR_FIFO_BOR_BASE29,Pointer FIFO 29 Upper Border"
hexmask.long.word 0x74 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x78 "PTR_FIFO_BOR_BASE30,Pointer FIFO 30 Upper Border"
hexmask.long.word 0x78 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
line.long 0x7C "PTR_FIFO_BOR_BASE31,Pointer FIFO 31 Upper Border"
hexmask.long.word 0x7C 0.--9. 1. " BORDER ,Last address of RAM used by appropriate FIFO"
tree.end
textline " "
group.long 0x100++0x003
line.long 0x000 "PTR_FIFO_RESET,Pointer FIFO Reset Vector"
bitfld.long 0x00 31. " PTR_FIFO_RESET31 ,Reset for FIFO 31" "No reset,Reset"
bitfld.long 0x00 30. " PTR_FIFO_RESET30 ,Reset for PFIFO 30" "No reset,Reset"
textline " "
bitfld.long 0x00 29. " PTR_FIFO_RESET29 ,Reset for FIFO 29" "No reset,Reset"
bitfld.long 0x00 28. " PTR_FIFO_RESET28 ,Reset for FIFO 28" "No reset,Reset"
textline " "
bitfld.long 0x00 27. " PTR_FIFO_RESET27 ,Reset for FIFO 27" "No reset,Reset"
bitfld.long 0x00 26. " PTR_FIFO_RESET26 ,Reset for FIFO 26" "No reset,Reset"
textline " "
bitfld.long 0x00 25. " PTR_FIFO_RESET25 ,Reset for FIFO 25" "No reset,Reset"
bitfld.long 0x00 24. " PTR_FIFO_RESET24 ,Reset for FIFO 24" "No reset,Reset"
textline " "
bitfld.long 0x00 23. " PTR_FIFO_RESET23 ,Reset for FIFO 23" "No reset,Reset"
bitfld.long 0x00 22. " PTR_FIFO_RESET22 ,Reset for FIFO 22" "No reset,Reset"
textline " "
bitfld.long 0x00 21. " PTR_FIFO_RESET21 ,Reset for FIFO 21" "No reset,Reset"
bitfld.long 0x00 20. " PTR_FIFO_RESET20 ,Reset for FIFO 20" "No reset,Reset"
textline " "
bitfld.long 0x00 19. " PTR_FIFO_RESET19 ,Reset for FIFO 19" "No reset,Reset"
bitfld.long 0x00 18. " PTR_FIFO_RESET18 ,Reset for FIFO 18" "No reset,Reset"
textline " "
bitfld.long 0x00 17. " PTR_FIFO_RESET17 ,Reset for FIFO 17" "No reset,Reset"
bitfld.long 0x00 16. " PTR_FIFO_RESET16 ,Reset for FIFO 16" "No reset,Reset"
textline " "
bitfld.long 0x00 15. " PTR_FIFO_RESET15 ,Reset for FIFO 15" "No reset,Reset"
bitfld.long 0x00 14. " PTR_FIFO_RESET14 ,Reset for FIFO 14" "No reset,Reset"
textline " "
bitfld.long 0x00 13. " PTR_FIFO_RESET13 ,Reset for FIFO 13" "No reset,Reset"
bitfld.long 0x00 12. " PTR_FIFO_RESET12 ,Reset for FIFO 12" "No reset,Reset"
textline " "
bitfld.long 0x00 11. " PTR_FIFO_RESET11 ,Reset for FIFO 11" "No reset,Reset"
bitfld.long 0x00 10. " PTR_FIFO_RESET10 ,Reset for FIFO 10" "No reset,Reset"
textline " "
bitfld.long 0x00 9. " PTR_FIFO_RESET9 ,Reset for FIFO 9" "No reset,Reset"
bitfld.long 0x00 8. " PTR_FIFO_RESET8 ,Reset for FIFO 8" "No reset,Reset"
textline " "
bitfld.long 0x00 7. " PTR_FIFO_RESET7 ,Reset for FIFO 7 " "No reset,Reset"
bitfld.long 0x00 6. " PTR_FIFO_RESET6 ,Reset for FIFO 6 " "No reset,Reset"
textline " "
bitfld.long 0x00 5. " PTR_FIFO_RESET5 ,Reset for FIFO 5 " "No reset,Reset"
bitfld.long 0x00 4. " PTR_FIFO_RESET4 ,Reset for FIFO 4 " "No reset,Reset"
textline " "
bitfld.long 0x00 3. " PTR_FIFO_RESET3 ,Reset for FIFO 3 " "No reset,Reset"
bitfld.long 0x00 2. " PTR_FIFO_RESET2 ,Reset for FIFO 2 " "No reset,Reset"
textline " "
bitfld.long 0x00 1. " PTR_FIFO_RESET1 ,Reset for FIFO 1 " "No reset,Reset"
bitfld.long 0x00 0. " PTR_FIFO_RESET0 ,Reset for FIFO 0 " "No reset,Reset"
rgroup.long 0x104++0x00F
line.long 0x000 "PTR_FIFO_FULL,Pointer FIFO Full Vector"
bitfld.long 0x00 31. " PTR_FIFO_FULL31 ,Full vector for FIFO 31" "Not full,Full"
bitfld.long 0x00 30. " PTR_FIFO_FULL30 ,Full vector for PFIFO 30" "Not full,Full"
textline " "
bitfld.long 0x00 29. " PTR_FIFO_FULL29 ,Full vector for FIFO 29" "Not full,Full"
bitfld.long 0x00 28. " PTR_FIFO_FULL28 ,Full vector for FIFO 28" "Not full,Full"
textline " "
bitfld.long 0x00 27. " PTR_FIFO_FULL27 ,Full vector for FIFO 27" "Not full,Full"
bitfld.long 0x00 26. " PTR_FIFO_FULL26 ,Full vector for FIFO 26" "Not full,Full"
textline " "
bitfld.long 0x00 25. " PTR_FIFO_FULL25 ,Full vector for FIFO 25" "Not full,Full"
bitfld.long 0x00 24. " PTR_FIFO_FULL24 ,Full vector for FIFO 24" "Not full,Full"
textline " "
bitfld.long 0x00 23. " PTR_FIFO_FULL23 ,Full vector for FIFO 23" "Not full,Full"
bitfld.long 0x00 22. " PTR_FIFO_FULL22 ,Full vector for FIFO 22" "Not full,Full"
textline " "
bitfld.long 0x00 21. " PTR_FIFO_FULL21 ,Full vector for FIFO 21" "Not full,Full"
bitfld.long 0x00 20. " PTR_FIFO_FULL20 ,Full vector for FIFO 20" "Not full,Full"
textline " "
bitfld.long 0x00 19. " PTR_FIFO_FULL19 ,Full vector for FIFO 19" "Not full,Full"
bitfld.long 0x00 18. " PTR_FIFO_FULL18 ,Full vector for FIFO 18" "Not full,Full"
textline " "
bitfld.long 0x00 17. " PTR_FIFO_FULL17 ,Full vector for FIFO 17" "Not full,Full"
bitfld.long 0x00 16. " PTR_FIFO_FULL16 ,Full vector for FIFO 16" "Not full,Full"
textline " "
bitfld.long 0x00 15. " PTR_FIFO_FULL15 ,Full vector for FIFO 15" "Not full,Full"
bitfld.long 0x00 14. " PTR_FIFO_FULL14 ,Full vector for FIFO 14" "Not full,Full"
textline " "
bitfld.long 0x00 13. " PTR_FIFO_FULL13 ,Full vector for FIFO 13" "Not full,Full"
bitfld.long 0x00 12. " PTR_FIFO_FULL12 ,Full vector for FIFO 12" "Not full,Full"
textline " "
bitfld.long 0x00 11. " PTR_FIFO_FULL11 ,Full vector for FIFO 11" "Not full,Full"
bitfld.long 0x00 10. " PTR_FIFO_FULL10 ,Full vector for FIFO 10" "Not full,Full"
textline " "
bitfld.long 0x00 9. " PTR_FIFO_FULL9 ,Full vector for FIFO 9" "Not full,Full"
bitfld.long 0x00 8. " PTR_FIFO_FULL8 ,Full vector for FIFO 8" "Not full,Full"
textline " "
bitfld.long 0x00 7. " PTR_FIFO_FULL7 ,Full vector for FIFO 7 " "Not full,Full"
bitfld.long 0x00 6. " PTR_FIFO_FULL6 ,Full vector for FIFO 6 " "Not full,Full"
textline " "
bitfld.long 0x00 5. " PTR_FIFO_FULL5 ,Full vector for FIFO 5 " "Not full,Full"
bitfld.long 0x00 4. " PTR_FIFO_FULL4 ,Full vector for FIFO 4 " "Not full,Full"
textline " "
bitfld.long 0x00 3. " PTR_FIFO_FULL3 ,Full vector for FIFO 3 " "Not full,Full"
bitfld.long 0x00 2. " PTR_FIFO_FULL2 ,Full vector for FIFO 2 " "Not full,Full"
textline " "
bitfld.long 0x00 1. " PTR_FIFO_FULL1 ,Full vector for FIFO 1 " "Not full,Full"
bitfld.long 0x00 0. " PTR_FIFO_FULL0 ,Full vector for FIFO 0 " "Not full,Full"
line.long 0x004 "PTR_FIFO_EMPTY,Pointer FIFO Empty Vector"
bitfld.long 0x04 31. " PTR_FIFO_EMPTY31 ,Empty vector for FIFO 31" "Not empty,Empty"
bitfld.long 0x04 30. " PTR_FIFO_EMPTY30 ,Empty vector for PFIFO 30" "Not empty,Empty"
textline " "
bitfld.long 0x04 29. " PTR_FIFO_EMPTY29 ,Empty vector for FIFO 29" "Not empty,Empty"
bitfld.long 0x04 28. " PTR_FIFO_EMPTY28 ,Empty vector for FIFO 28" "Not empty,Empty"
textline " "
bitfld.long 0x04 27. " PTR_FIFO_EMPTY27 ,Empty vector for FIFO 27" "Not empty,Empty"
bitfld.long 0x04 26. " PTR_FIFO_EMPTY26 ,Empty vector for FIFO 26" "Not empty,Empty"
textline " "
bitfld.long 0x04 25. " PTR_FIFO_EMPTY25 ,Empty vector for FIFO 25" "Not empty,Empty"
bitfld.long 0x04 24. " PTR_FIFO_EMPTY24 ,Empty vector for FIFO 24" "Not empty,Empty"
textline " "
bitfld.long 0x04 23. " PTR_FIFO_EMPTY23 ,Empty vector for FIFO 23" "Not empty,Empty"
bitfld.long 0x04 22. " PTR_FIFO_EMPTY22 ,Empty vector for FIFO 22" "Not empty,Empty"
textline " "
bitfld.long 0x04 21. " PTR_FIFO_EMPTY21 ,Empty vector for FIFO 21" "Not empty,Empty"
bitfld.long 0x04 20. " PTR_FIFO_EMPTY20 ,Empty vector for FIFO 20" "Not empty,Empty"
textline " "
bitfld.long 0x04 19. " PTR_FIFO_EMPTY19 ,Empty vector for FIFO 19" "Not empty,Empty"
bitfld.long 0x04 18. " PTR_FIFO_EMPTY18 ,Empty vector for FIFO 18" "Not empty,Empty"
textline " "
bitfld.long 0x04 17. " PTR_FIFO_EMPTY17 ,Empty vector for FIFO 17" "Not empty,Empty"
bitfld.long 0x04 16. " PTR_FIFO_EMPTY16 ,Empty vector for FIFO 16" "Not empty,Empty"
textline " "
bitfld.long 0x04 15. " PTR_FIFO_EMPTY15 ,Empty vector for FIFO 15" "Not empty,Empty"
bitfld.long 0x04 14. " PTR_FIFO_EMPTY14 ,Empty vector for FIFO 14" "Not empty,Empty"
textline " "
bitfld.long 0x04 13. " PTR_FIFO_EMPTY13 ,Empty vector for FIFO 13" "Not empty,Empty"
bitfld.long 0x04 12. " PTR_FIFO_EMPTY12 ,Empty vector for FIFO 12" "Not empty,Empty"
textline " "
bitfld.long 0x04 11. " PTR_FIFO_EMPTY11 ,Empty vector for FIFO 11" "Not empty,Empty"
bitfld.long 0x04 10. " PTR_FIFO_EMPTY10 ,Empty vector for FIFO 10" "Not empty,Empty"
textline " "
bitfld.long 0x04 9. " PTR_FIFO_EMPTY9 ,Empty vector for FIFO 9" "Not empty,Empty"
bitfld.long 0x04 8. " PTR_FIFO_EMPTY8 ,Empty vector for FIFO 8" "Not empty,Empty"
textline " "
bitfld.long 0x04 7. " PTR_FIFO_EMPTY7 ,Empty vector for FIFO 7 " "Not empty,Empty"
bitfld.long 0x04 6. " PTR_FIFO_EMPTY6 ,Empty vector for FIFO 6 " "Not empty,Empty"
textline " "
bitfld.long 0x04 5. " PTR_FIFO_EMPTY5 ,Empty vector for FIFO 5 " "Not empty,Empty"
bitfld.long 0x04 4. " PTR_FIFO_EMPTY4 ,Empty vector for FIFO 4 " "Not empty,Empty"
textline " "
bitfld.long 0x04 3. " PTR_FIFO_EMPTY3 ,Empty vector for FIFO 3 " "Not empty,Empty"
bitfld.long 0x04 2. " PTR_FIFO_EMPTY2 ,Empty vector for FIFO 2 " "Not empty,Empty"
textline " "
bitfld.long 0x04 1. " PTR_FIFO_EMPTY1 ,Empty vector for FIFO 1 " "Not empty,Empty"
bitfld.long 0x04 0. " PTR_FIFO_EMPTY0 ,Empty vector for FIFO 0 " "Not empty,Empty"
line.long 0x008 "PTR_FIFO_OVF,Pointer FIFO Overflow Vector"
bitfld.long 0x08 31. " FIFO_OVERFLOW31 ,Overflow vector for FIFO 31" "No overflow,Overflow"
bitfld.long 0x08 30. " FIFO_OVERFLOW30 ,Overflow vector for PFIFO 30" "No overflow,Overflow"
textline " "
bitfld.long 0x08 29. " FIFO_OVERFLOW29 ,Overflow vector for FIFO 29" "No overflow,Overflow"
bitfld.long 0x08 28. " FIFO_OVERFLOW28 ,Overflow vector for FIFO 28" "No overflow,Overflow"
textline " "
bitfld.long 0x08 27. " FIFO_OVERFLOW27 ,Overflow vector for FIFO 27" "No overflow,Overflow"
bitfld.long 0x08 26. " FIFO_OVERFLOW26 ,Overflow vector for FIFO 26" "No overflow,Overflow"
textline " "
bitfld.long 0x08 25. " FIFO_OVERFLOW25 ,Overflow vector for FIFO 25" "No overflow,Overflow"
bitfld.long 0x08 24. " FIFO_OVERFLOW24 ,Overflow vector for FIFO 24" "No overflow,Overflow"
textline " "
bitfld.long 0x08 23. " FIFO_OVERFLOW23 ,Overflow vector for FIFO 23" "No overflow,Overflow"
bitfld.long 0x08 22. " FIFO_OVERFLOW22 ,Overflow vector for FIFO 22" "No overflow,Overflow"
textline " "
bitfld.long 0x08 21. " FIFO_OVERFLOW21 ,Overflow vector for FIFO 21" "No overflow,Overflow"
bitfld.long 0x08 20. " FIFO_OVERFLOW20 ,Overflow vector for FIFO 20" "No overflow,Overflow"
textline " "
bitfld.long 0x08 19. " FIFO_OVERFLOW19 ,Overflow vector for FIFO 19" "No overflow,Overflow"
bitfld.long 0x08 18. " FIFO_OVERFLOW18 ,Overflow vector for FIFO 18" "No overflow,Overflow"
textline " "
bitfld.long 0x08 17. " FIFO_OVERFLOW17 ,Overflow vector for FIFO 17" "No overflow,Overflow"
bitfld.long 0x08 16. " FIFO_OVERFLOW16 ,Overflow vector for FIFO 16" "No overflow,Overflow"
textline " "
bitfld.long 0x08 15. " FIFO_OVERFLOW15 ,Overflow vector for FIFO 15" "No overflow,Overflow"
bitfld.long 0x08 14. " FIFO_OVERFLOW14 ,Overflow vector for FIFO 14" "No overflow,Overflow"
textline " "
bitfld.long 0x08 13. " FIFO_OVERFLOW13 ,Overflow vector for FIFO 13" "No overflow,Overflow"
bitfld.long 0x08 12. " FIFO_OVERFLOW12 ,Overflow vector for FIFO 12" "No overflow,Overflow"
textline " "
bitfld.long 0x08 11. " FIFO_OVERFLOW11 ,Overflow vector for FIFO 11" "No overflow,Overflow"
bitfld.long 0x08 10. " FIFO_OVERFLOW10 ,Overflow vector for FIFO 10" "No overflow,Overflow"
textline " "
bitfld.long 0x08 9. " FIFO_OVERFLOW9 ,Overflow vector for FIFO 9" "No overflow,Overflow"
bitfld.long 0x08 8. " FIFO_OVERFLOW8 ,Overflow vector for FIFO 8" "No overflow,Overflow"
textline " "
bitfld.long 0x08 7. " FIFO_OVERFLOW7 ,Overflow vector for FIFO 7 " "No overflow,Overflow"
bitfld.long 0x08 6. " FIFO_OVERFLOW6 ,Overflow vector for FIFO 6 " "No overflow,Overflow"
textline " "
bitfld.long 0x08 5. " FIFO_OVERFLOW5 ,Overflow vector for FIFO 5 " "No overflow,Overflow"
bitfld.long 0x08 4. " FIFO_OVERFLOW4 ,Overflow vector for FIFO 4 " "No overflow,Overflow"
textline " "
bitfld.long 0x08 3. " FIFO_OVERFLOW3 ,Overflow vector for FIFO 3 " "No overflow,Overflow"
bitfld.long 0x08 2. " FIFO_OVERFLOW2 ,Overflow vector for FIFO 2 " "No overflow,Overflow"
textline " "
bitfld.long 0x08 1. " FIFO_OVERFLOW1 ,Overflow vector for FIFO 1 " "No overflow,Overflow"
bitfld.long 0x08 0. " FIFO_OVERFLOW0 ,Overflow vector for FIFO 0 " "No overflow,Overflow"
line.long 0x0C "PTR_FIFO_UDR,Pointer FIFO Under Run Vector"
bitfld.long 0x0c 31. " FIFO_UNDERRUN31 ,Underrun vector for FIFO 31" "Not underrun,Underrun"
bitfld.long 0x0c 30. " FIFO_UNDERRUN30 ,Underrun vector for PFIFO 30" "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 29. " FIFO_UNDERRUN29 ,Underrun vector for FIFO 29" "Not underrun,Underrun"
bitfld.long 0x0c 28. " FIFO_UNDERRUN28 ,Underrun vector for FIFO 28" "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 27. " FIFO_UNDERRUN27 ,Underrun vector for FIFO 27" "Not underrun,Underrun"
bitfld.long 0x0c 26. " FIFO_UNDERRUN26 ,Underrun vector for FIFO 26" "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 25. " FIFO_UNDERRUN25 ,Underrun vector for FIFO 25" "Not underrun,Underrun"
bitfld.long 0x0c 24. " FIFO_UNDERRUN24 ,Underrun vector for FIFO 24" "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 23. " FIFO_UNDERRUN23 ,Underrun vector for FIFO 23" "Not underrun,Underrun"
bitfld.long 0x0c 22. " FIFO_UNDERRUN22 ,Underrun vector for FIFO 22" "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 21. " FIFO_UNDERRUN21 ,Underrun vector for FIFO 21" "Not underrun,Underrun"
bitfld.long 0x0c 20. " FIFO_UNDERRUN20 ,Underrun vector for FIFO 20" "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 19. " FIFO_UNDERRUN19 ,Underrun vector for FIFO 19" "Not underrun,Underrun"
bitfld.long 0x0c 18. " FIFO_UNDERRUN18 ,Underrun vector for FIFO 18" "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 17. " FIFO_UNDERRUN17 ,Underrun vector for FIFO 17" "Not underrun,Underrun"
bitfld.long 0x0c 16. " FIFO_UNDERRUN16 ,Underrun vector for FIFO 16" "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 15. " FIFO_UNDERRUN15 ,Underrun vector for FIFO 15" "Not underrun,Underrun"
bitfld.long 0x0c 14. " FIFO_UNDERRUN14 ,Underrun vector for FIFO 14" "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 13. " FIFO_UNDERRUN13 ,Underrun vector for FIFO 13" "Not underrun,Underrun"
bitfld.long 0x0c 12. " FIFO_UNDERRUN12 ,Underrun vector for FIFO 12" "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 11. " FIFO_UNDERRUN11 ,Underrun vector for FIFO 11" "Not underrun,Underrun"
bitfld.long 0x0c 10. " FIFO_UNDERRUN10 ,Underrun vector for FIFO 10" "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 9. " FIFO_UNDERRUN9 ,Underrun vector for FIFO 9" "Not underrun,Underrun"
bitfld.long 0x0c 8. " FIFO_UNDERRUN8 ,Underrun vector for FIFO 8" "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 7. " FIFO_UNDERRUN7 ,Underrun vector for FIFO 7 " "Not underrun,Underrun"
bitfld.long 0x0c 6. " FIFO_UNDERRUN6 ,Underrun vector for FIFO 6 " "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 5. " FIFO_UNDERRUN5 ,Underrun vector for FIFO 5 " "Not underrun,Underrun"
bitfld.long 0x0c 4. " FIFO_UNDERRUN4 ,Underrun vector for FIFO 4 " "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 3. " FIFO_UNDERRUN3 ,Underrun vector for FIFO 3 " "Not underrun,Underrun"
bitfld.long 0x0c 2. " FIFO_UNDERRUN2 ,Underrun vector for FIFO 2 " "Not underrun,Underrun"
textline " "
bitfld.long 0x0c 1. " FIFO_UNDERRUN1 ,Underrun vector for FIFO 1 " "Not underrun,Underrun"
bitfld.long 0x0c 0. " FIFO_UNDERRUN0 ,Underrun vector for FIFO 0 " "Not underrun,Underrun"
tree "PTR_FIFO_FILL_LVL_BASE[0-31] (Pointer FIFO Fill Level 0-31)"
width 25.
rgroup.long 0x180++0x07F
line.long 0x0 "PFIFO_FILL_LEVEL_BASE0,Pointer FIFO Fill Level 0"
hexmask.long.word 0x0 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x4 "PFIFO_FILL_LEVEL_BASE1,Pointer FIFO Fill Level 1"
hexmask.long.word 0x4 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x8 "PFIFO_FILL_LEVEL_BASE2,Pointer FIFO Fill Level 2"
hexmask.long.word 0x8 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0xC "PFIFO_FILL_LEVEL_BASE3,Pointer FIFO Fill Level 3"
hexmask.long.word 0xC 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x10 "PFIFO_FILL_LEVEL_BASE4,Pointer FIFO Fill Level 4"
hexmask.long.word 0x10 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x14 "PFIFO_FILL_LEVEL_BASE5,Pointer FIFO Fill Level 5"
hexmask.long.word 0x14 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x18 "PFIFO_FILL_LEVEL_BASE6,Pointer FIFO Fill Level 6"
hexmask.long.word 0x18 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x1C "PFIFO_FILL_LEVEL_BASE7,Pointer FIFO Fill Level 7"
hexmask.long.word 0x1C 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x20 "PFIFO_FILL_LEVEL_BASE8,Pointer FIFO Fill Level 8"
hexmask.long.word 0x20 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x24 "PFIFO_FILL_LEVEL_BASE9,Pointer FIFO Fill Level 9"
hexmask.long.word 0x24 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x28 "PFIFO_FILL_LEVEL_BASE10,Pointer FIFO Fill Level 10"
hexmask.long.word 0x28 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x2C "PFIFO_FILL_LEVEL_BASE11,Pointer FIFO Fill Level 11"
hexmask.long.word 0x2C 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x30 "PFIFO_FILL_LEVEL_BASE12,Pointer FIFO Fill Level 12"
hexmask.long.word 0x30 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x34 "PFIFO_FILL_LEVEL_BASE13,Pointer FIFO Fill Level 13"
hexmask.long.word 0x34 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x38 "PFIFO_FILL_LEVEL_BASE14,Pointer FIFO Fill Level 14"
hexmask.long.word 0x38 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x3C "PFIFO_FILL_LEVEL_BASE15,Pointer FIFO Fill Level 15"
hexmask.long.word 0x3C 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x40 "PFIFO_FILL_LEVEL_BASE16,Pointer FIFO Fill Level 16"
hexmask.long.word 0x40 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x44 "PFIFO_FILL_LEVEL_BASE17,Pointer FIFO Fill Level 17"
hexmask.long.word 0x44 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x48 "PFIFO_FILL_LEVEL_BASE18,Pointer FIFO Fill Level 18"
hexmask.long.word 0x48 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x4C "PFIFO_FILL_LEVEL_BASE19,Pointer FIFO Fill Level 19"
hexmask.long.word 0x4C 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x50 "PFIFO_FILL_LEVEL_BASE20,Pointer FIFO Fill Level 20"
hexmask.long.word 0x50 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x54 "PFIFO_FILL_LEVEL_BASE21,Pointer FIFO Fill Level 21"
hexmask.long.word 0x54 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x58 "PFIFO_FILL_LEVEL_BASE22,Pointer FIFO Fill Level 22"
hexmask.long.word 0x58 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x5C "PFIFO_FILL_LEVEL_BASE23,Pointer FIFO Fill Level 23"
hexmask.long.word 0x5C 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x60 "PFIFO_FILL_LEVEL_BASE24,Pointer FIFO Fill Level 24"
hexmask.long.word 0x60 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x64 "PFIFO_FILL_LEVEL_BASE25,Pointer FIFO Fill Level 25"
hexmask.long.word 0x64 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x68 "PFIFO_FILL_LEVEL_BASE26,Pointer FIFO Fill Level 26"
hexmask.long.word 0x68 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x6C "PFIFO_FILL_LEVEL_BASE27,Pointer FIFO Fill Level 27"
hexmask.long.word 0x6C 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x70 "PFIFO_FILL_LEVEL_BASE28,Pointer FIFO Fill Level 28"
hexmask.long.word 0x70 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x74 "PFIFO_FILL_LEVEL_BASE29,Pointer FIFO Fill Level 29"
hexmask.long.word 0x74 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x78 "PFIFO_FILL_LEVEL_BASE30,Pointer FIFO Fill Level 30"
hexmask.long.word 0x78 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
line.long 0x7C "PFIFO_FILL_LEVEL_BASE31,Pointer FIFO Fill Level 31"
hexmask.long.word 0x7C 0.--9. 1. " PTR_FIFO_FILL_LVL ,Actual number of words in FIFO"
tree.end
width 0x0B
tree.end
tree "Buffer Management Unit (BMU)"
base asd:0x1c065600
width 21.
if (((data.long(asd:(0x1c065600+0x00)))&0x80)==0x80)
group.long 0x00++0x3
line.long 0x00 "BUF_MAN_XPEC0 , BMU port of 1st master (xPEC0)"
bitfld.long 0x00 11. " SM_UPDATE_DIS ,De-activate SM_auto_update mode" "Enabled,Disabled"
bitfld.long 0x00 10. " SM_UPDATE_EN ,Activate SM_auto_update mode" "Disabled,Enabled"
bitfld.long 0x00 9. " RESET ,Reset channel" "No reset,Reset"
textline " "
bitfld.long 0x00 8. " PARALLEL_MODE ,Activate parallel mode" "Disabled,Enabled"
bitfld.long 0x00 7. " SEMAPHORE_MODE ,Activate semaphore mode" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5.--6. " REQ_TYPE ,Request type bits are write-only" "Request semaphore,Release semaphore,Release semaphore,Don't request semaphore"
textline " "
bitfld.long 0x00 0.--3. " BUF_NR ,Number of buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long 0x00++0x3
line.long 0x00 "BUF_MAN_XPEC0 , BMU port of 1st master (xPEC0)"
bitfld.long 0x00 11. " SM_UPDATE_DIS ,De-activate SM_auto_update mode" "Enabled,Disabled"
bitfld.long 0x00 10. " SM_UPDATE_EN ,Activate SM_auto_update mode" "Disabled,Enabled"
bitfld.long 0x00 9. " RESET ,Reset channel" "No reset,Reset"
textline " "
bitfld.long 0x00 8. " PARALLEL_MODE ,Activate parallel mode" "Disabled,Enabled"
bitfld.long 0x00 7. " SEMAPHORE_MODE ,Activate semaphore mode" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5.--6. " REQ_TYPE ,Request type bits are write-only" "Request read buffer,Request write buffer,Release write buffer,Don't request new buffer"
textline " "
bitfld.long 0x00 0.--3. " BUF_NR ,Number of buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
if (((data.long(asd:(0x1c065600+0x04)))&0x80)==0x80)
group.long 0x04++0x03
line.long 0x00 "BUF_MAN_XPEC1 ,BMU port of 2nd master (xPEC1)"
bitfld.long 0x00 11. " SM_UPDATE_DIS ,De-activate SM_auto_update mode" "Enabled,Disabled"
bitfld.long 0x00 10. " SM_UPDATE_EN ,Activate SM_auto_update mode" "Disabled,Enabled"
bitfld.long 0x00 9. " RESET ,Reset channel" "No reset,Reset"
textline " "
bitfld.long 0x00 8. " PARALLEL_MODE ,Activate parallel mode" "Disabled,Enabled"
bitfld.long 0x00 7. " SEMAPHORE_MODE ,Activate semaphore mode" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5.--6. " REQ_TYPE ,Request type bits are write-only" "Request semaphore,Release semaphore,Release semaphore,Don't request semaphore"
textline " "
bitfld.long 0x00 0.--3. " BUF_NR ,Number of buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long 0x04++0x03
line.long 0x00 "BUF_MAN_XPEC1 ,BMU port of 2nd master (xPEC1)"
bitfld.long 0x00 11. " SM_UPDATE_DIS ,De-activate SM_auto_update mode" "Enabled,Disabled"
bitfld.long 0x00 10. " SM_UPDATE_EN ,Activate SM_auto_update mode" "Disabled,Enabled"
bitfld.long 0x00 9. " RESET ,Reset channel" "No reset,Reset"
textline " "
bitfld.long 0x00 8. " PARALLEL_MODE ,Activate parallel mode" "Disabled,Enabled"
bitfld.long 0x00 7. " SEMAPHORE_MODE ,Activate semaphore mode" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5.--6. " REQ_TYPE ,Request type bits are write-only" "Request read buffer,Request write buffer,Release write buffer,Don't request new buffer"
textline " "
bitfld.long 0x00 0.--3. " BUF_NR ,Number of buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
if (((data.long(asd:(0x1c065600+0x08)))&0x80)==0x80)
group.long 0x08++0x03
line.long 0x00 "BUF_MAN_ARM ,BMU-port of 3rd master (ARM)"
bitfld.long 0x00 9. " RESET ,Reset channel" "No reset,Reset"
textline " "
bitfld.long 0x00 8. " PARALLEL_MODE ,Activate parallel mode" "Disabled,Enabled"
bitfld.long 0x00 7. " SEMAPHORE_MODE ,Activate semaphore mode" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5.--6. " REQ_TYPE ,Request type bits are write-only" "Request semaphore,Release semaphore,Release semaphore,Don't request semaphore"
textline " "
bitfld.long 0x00 0.--3. " BUF_NR ,Number of buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long 0x08++0x03
line.long 0x00 "BUF_MAN_ARM ,BMU-port of 3rd master (ARM)"
bitfld.long 0x00 9. " RESET ,Reset channel" "No reset,Reset"
textline " "
bitfld.long 0x00 8. " PARALLEL_MODE ,Activate parallel mode" "Disabled,Enabled"
bitfld.long 0x00 7. " SEMAPHORE_MODE ,Activate semaphore mode" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5.--6. " REQ_TYPE ,Request type bits are write-only" "Request read buffer,Request write buffer,Release write buffer,Don't request new buffer"
textline " "
bitfld.long 0x00 0.--3. " BUF_NR ,Number of buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
if (((data.long(asd:(0x1c065600+0x0c)))&0x80)==0x80)
group.long 0x0c++0x03
line.long 0x00 "BUF_MAN_HIF ,BMU-port of 4th master (HIF)"
bitfld.long 0x00 9. " RESET ,Reset channel" "No reset,Reset"
textline " "
bitfld.long 0x00 8. " PARALLEL_MODE ,Activate parallel mode" "Disabled,Enabled"
bitfld.long 0x00 7. " SEMAPHORE_MODE ,Activate semaphore mode" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5.--6. " REQ_TYPE ,Request type bits are write-only" "Request semaphore,Release semaphore,Release semaphore,Don't request semaphore"
textline " "
bitfld.long 0x00 0.--3. " BUF_NR ,Number of buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long 0x0c++0x03
line.long 0x00 "BUF_MAN_HIF ,BMU-port of 4th master (HIF)"
bitfld.long 0x00 9. " RESET ,Reset channel" "No reset,Reset"
textline " "
bitfld.long 0x00 8. " PARALLEL_MODE ,Activate parallel mode" "Disabled,Enabled"
bitfld.long 0x00 7. " SEMAPHORE_MODE ,Activate semaphore mode" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5.--6. " REQ_TYPE ,Request type bits are write-only" "Request read buffer,Request write buffer,Release write buffer,Don't request new buffer"
textline " "
bitfld.long 0x00 0.--3. " BUF_NR ,Number of buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
width 0x0B
tree.end
tree "Configurable CRC-Generator (CRC)"
base asd:0x1c001000
width 0x10
group.long 0x00++0x0F
sif ((cpu()=="NETX51")||(cpu()=="NETX50")||(cpu()=="NETX100"))
line.long 0x00 "CRC_VAL,CRC Register"
line.long 0x04 "CRC_IN_DATA,CRC Input Data Register"
hexmask.long.byte 0x04 0.--7. 1. " CRC_IN_DATA ,CRC input data"
else
line.long 0x00 "CRC_CRC,CRC Register"
line.long 0x04 "CRC_DATA,CRC Input Data Register"
hexmask.long.byte 0x04 0.--7. 1. " CRC_INPUT ,CRC input data"
endif
line.long 0x08 "CRC_POLYNOMIAL,CRC Polynomial Register"
line.long 0x0C "CRC_CONFIG,CRC Configuration Register"
bitfld.long 0x0C 10. " CRC_IN_MSB_LOW ,Swap crc_data_in" "MSB,LSB"
bitfld.long 0x0C 8.--9. " CRC_NOF_BITS ,Number of bits to be calculated in parallel" "1 bit,2 bits,4 bits,8 bits"
textline " "
bitfld.long 0x0C 7. " CRC_DIRECT_DIV ,Calculate direct polynomial division" "Disabled,Enabled"
bitfld.long 0x0C 6. " CRC_SHIFT_DIV ,Shift CRC" "Left,Right"
textline " "
hexmask.long.byte 0x0C 0.--5. 1. " CRC_LEN ,Length of CRC Polynom - 1"
width 0x0B
tree.end
tree "IRQs between XPEC and ARM Registers (ARM_to_XPEC_IRQ)"
base asd:0x1c064400
width 0x0B
sif (cpu()=="NETX50")
group.long 0x00++0x07
line.long 0x0 "IRQ_XPEC0,IRQs between XPEC0 and ARM Registers"
hexmask.long.word 0x0 16.--31. 1. " ARM_IRQ ,Set by arm ; reset by xpec"
hexmask.long.word 0x0 0.--15. 1. " XPEC_IRQ ,Set by xpec ; reset by arm"
line.long 0x4 "IRQ_XPEC1,IRQs between XPEC1 and ARM Registers"
hexmask.long.word 0x4 16.--31. 1. " ARM_IRQ ,Set by arm ; reset by xpec"
hexmask.long.word 0x4 0.--15. 1. " XPEC_IRQ ,Set by xpec ; reset by arm"
else
group.long 0x00++0x0F
line.long 0x0 "IRQ_XPEC0,IRQs between XPEC0 and ARM Registers"
hexmask.long.word 0x0 16.--31. 1. " ARM_IRQ ,Set by arm ; reset by xpec"
hexmask.long.word 0x0 0.--15. 1. " XPEC_IRQ ,Set by xpec ; reset by arm"
line.long 0x4 "IRQ_XPEC1,IRQs between XPEC1 and ARM Registers"
hexmask.long.word 0x4 16.--31. 1. " ARM_IRQ ,Set by arm ; reset by xpec"
hexmask.long.word 0x4 0.--15. 1. " XPEC_IRQ ,Set by xpec ; reset by arm"
line.long 0x8 "IRQ_XPEC2,IRQs between XPEC2 and ARM Registers"
hexmask.long.word 0x8 16.--31. 1. " ARM_IRQ ,Set by arm ; reset by xpec"
hexmask.long.word 0x8 0.--15. 1. " XPEC_IRQ ,Set by xpec ; reset by arm"
line.long 0xC "IRQ_XPEC3,IRQs between XPEC3 and ARM Registers"
hexmask.long.word 0xC 16.--31. 1. " ARM_IRQ ,Set by arm ; reset by xpec"
hexmask.long.word 0xC 0.--15. 1. " XPEC_IRQ ,Set by xpec ; reset by arm"
endif
width 0x0B
tree.end
tree.end
textline " "
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